1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Cadence MACB/GEM Ethernet Controller driver
4 *
5 * Copyright (C) 2004-2006 Atmel Corporation
6 */
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/crc32.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/circ_buf.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/phylink.h>
26 #include <linux/of.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/ip.h>
30 #include <linux/udp.h>
31 #include <linux/tcp.h>
32 #include <linux/iopoll.h>
33 #include <linux/phy/phy.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/ptp_classify.h>
36 #include <linux/reset.h>
37 #include <linux/firmware/xlnx-zynqmp.h>
38 #include <linux/inetdevice.h>
39 #include "macb.h"
40
41 /* This structure is only used for MACB on SiFive FU540 devices */
42 struct sifive_fu540_macb_mgmt {
43 void __iomem *reg;
44 unsigned long rate;
45 struct clk_hw hw;
46 };
47
48 #define MACB_RX_BUFFER_SIZE 128
49 #define RX_BUFFER_MULTIPLE 64 /* bytes */
50
51 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
52 #define MIN_RX_RING_SIZE 64
53 #define MAX_RX_RING_SIZE 8192
54 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
55 * (bp)->rx_ring_size)
56
57 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
58 #define MIN_TX_RING_SIZE 64
59 #define MAX_TX_RING_SIZE 4096
60 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
61 * (bp)->tx_ring_size)
62
63 /* level of occupied TX descriptors under which we wake up TX process */
64 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
65
66 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
67 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
68 | MACB_BIT(ISR_RLE) \
69 | MACB_BIT(TXERR))
70 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
71 | MACB_BIT(TXUBR))
72
73 /* Max length of transmit frame must be a multiple of 8 bytes */
74 #define MACB_TX_LEN_ALIGN 8
75 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
76 /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
77 * false amba_error in TX path from the DMA assuming there is not enough
78 * space in the SRAM (16KB) even when there is.
79 */
80 #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
81
82 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
83 #define MACB_NETIF_LSO NETIF_F_TSO
84
85 #define MACB_WOL_ENABLED BIT(0)
86
87 #define HS_SPEED_10000M 4
88 #define MACB_SERDES_RATE_10G 1
89
90 /* Graceful stop timeouts in us. We should allow up to
91 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
92 */
93 #define MACB_HALT_TIMEOUT 14000
94 #define MACB_PM_TIMEOUT 100 /* ms */
95
96 #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
97
98 /* DMA buffer descriptor might be different size
99 * depends on hardware configuration:
100 *
101 * 1. dma address width 32 bits:
102 * word 1: 32 bit address of Data Buffer
103 * word 2: control
104 *
105 * 2. dma address width 64 bits:
106 * word 1: 32 bit address of Data Buffer
107 * word 2: control
108 * word 3: upper 32 bit address of Data Buffer
109 * word 4: unused
110 *
111 * 3. dma address width 32 bits with hardware timestamping:
112 * word 1: 32 bit address of Data Buffer
113 * word 2: control
114 * word 3: timestamp word 1
115 * word 4: timestamp word 2
116 *
117 * 4. dma address width 64 bits with hardware timestamping:
118 * word 1: 32 bit address of Data Buffer
119 * word 2: control
120 * word 3: upper 32 bit address of Data Buffer
121 * word 4: unused
122 * word 5: timestamp word 1
123 * word 6: timestamp word 2
124 */
macb_dma_desc_get_size(struct macb * bp)125 static unsigned int macb_dma_desc_get_size(struct macb *bp)
126 {
127 #ifdef MACB_EXT_DESC
128 unsigned int desc_size;
129
130 switch (bp->hw_dma_cap) {
131 case HW_DMA_CAP_64B:
132 desc_size = sizeof(struct macb_dma_desc)
133 + sizeof(struct macb_dma_desc_64);
134 break;
135 case HW_DMA_CAP_PTP:
136 desc_size = sizeof(struct macb_dma_desc)
137 + sizeof(struct macb_dma_desc_ptp);
138 break;
139 case HW_DMA_CAP_64B_PTP:
140 desc_size = sizeof(struct macb_dma_desc)
141 + sizeof(struct macb_dma_desc_64)
142 + sizeof(struct macb_dma_desc_ptp);
143 break;
144 default:
145 desc_size = sizeof(struct macb_dma_desc);
146 }
147 return desc_size;
148 #endif
149 return sizeof(struct macb_dma_desc);
150 }
151
macb_adj_dma_desc_idx(struct macb * bp,unsigned int desc_idx)152 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
153 {
154 #ifdef MACB_EXT_DESC
155 switch (bp->hw_dma_cap) {
156 case HW_DMA_CAP_64B:
157 case HW_DMA_CAP_PTP:
158 desc_idx <<= 1;
159 break;
160 case HW_DMA_CAP_64B_PTP:
161 desc_idx *= 3;
162 break;
163 default:
164 break;
165 }
166 #endif
167 return desc_idx;
168 }
169
170 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
macb_64b_desc(struct macb * bp,struct macb_dma_desc * desc)171 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
172 {
173 return (struct macb_dma_desc_64 *)((void *)desc
174 + sizeof(struct macb_dma_desc));
175 }
176 #endif
177
178 /* Ring buffer accessors */
macb_tx_ring_wrap(struct macb * bp,unsigned int index)179 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
180 {
181 return index & (bp->tx_ring_size - 1);
182 }
183
macb_tx_desc(struct macb_queue * queue,unsigned int index)184 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
185 unsigned int index)
186 {
187 index = macb_tx_ring_wrap(queue->bp, index);
188 index = macb_adj_dma_desc_idx(queue->bp, index);
189 return &queue->tx_ring[index];
190 }
191
macb_tx_skb(struct macb_queue * queue,unsigned int index)192 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
193 unsigned int index)
194 {
195 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
196 }
197
macb_tx_dma(struct macb_queue * queue,unsigned int index)198 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
199 {
200 dma_addr_t offset;
201
202 offset = macb_tx_ring_wrap(queue->bp, index) *
203 macb_dma_desc_get_size(queue->bp);
204
205 return queue->tx_ring_dma + offset;
206 }
207
macb_rx_ring_wrap(struct macb * bp,unsigned int index)208 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
209 {
210 return index & (bp->rx_ring_size - 1);
211 }
212
macb_rx_desc(struct macb_queue * queue,unsigned int index)213 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
214 {
215 index = macb_rx_ring_wrap(queue->bp, index);
216 index = macb_adj_dma_desc_idx(queue->bp, index);
217 return &queue->rx_ring[index];
218 }
219
macb_rx_buffer(struct macb_queue * queue,unsigned int index)220 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
221 {
222 return queue->rx_buffers + queue->bp->rx_buffer_size *
223 macb_rx_ring_wrap(queue->bp, index);
224 }
225
226 /* I/O accessors */
hw_readl_native(struct macb * bp,int offset)227 static u32 hw_readl_native(struct macb *bp, int offset)
228 {
229 return __raw_readl(bp->regs + offset);
230 }
231
hw_writel_native(struct macb * bp,int offset,u32 value)232 static void hw_writel_native(struct macb *bp, int offset, u32 value)
233 {
234 __raw_writel(value, bp->regs + offset);
235 }
236
hw_readl(struct macb * bp,int offset)237 static u32 hw_readl(struct macb *bp, int offset)
238 {
239 return readl_relaxed(bp->regs + offset);
240 }
241
hw_writel(struct macb * bp,int offset,u32 value)242 static void hw_writel(struct macb *bp, int offset, u32 value)
243 {
244 writel_relaxed(value, bp->regs + offset);
245 }
246
247 /* Find the CPU endianness by using the loopback bit of NCR register. When the
248 * CPU is in big endian we need to program swapped mode for management
249 * descriptor access.
250 */
hw_is_native_io(void __iomem * addr)251 static bool hw_is_native_io(void __iomem *addr)
252 {
253 u32 value = MACB_BIT(LLB);
254
255 __raw_writel(value, addr + MACB_NCR);
256 value = __raw_readl(addr + MACB_NCR);
257
258 /* Write 0 back to disable everything */
259 __raw_writel(0, addr + MACB_NCR);
260
261 return value == MACB_BIT(LLB);
262 }
263
hw_is_gem(void __iomem * addr,bool native_io)264 static bool hw_is_gem(void __iomem *addr, bool native_io)
265 {
266 u32 id;
267
268 if (native_io)
269 id = __raw_readl(addr + MACB_MID);
270 else
271 id = readl_relaxed(addr + MACB_MID);
272
273 return MACB_BFEXT(IDNUM, id) >= 0x2;
274 }
275
macb_set_hwaddr(struct macb * bp)276 static void macb_set_hwaddr(struct macb *bp)
277 {
278 u32 bottom;
279 u16 top;
280
281 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
282 macb_or_gem_writel(bp, SA1B, bottom);
283 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
284 macb_or_gem_writel(bp, SA1T, top);
285
286 if (gem_has_ptp(bp)) {
287 gem_writel(bp, RXPTPUNI, bottom);
288 gem_writel(bp, TXPTPUNI, bottom);
289 }
290
291 /* Clear unused address register sets */
292 macb_or_gem_writel(bp, SA2B, 0);
293 macb_or_gem_writel(bp, SA2T, 0);
294 macb_or_gem_writel(bp, SA3B, 0);
295 macb_or_gem_writel(bp, SA3T, 0);
296 macb_or_gem_writel(bp, SA4B, 0);
297 macb_or_gem_writel(bp, SA4T, 0);
298 }
299
macb_get_hwaddr(struct macb * bp)300 static void macb_get_hwaddr(struct macb *bp)
301 {
302 u32 bottom;
303 u16 top;
304 u8 addr[6];
305 int i;
306
307 /* Check all 4 address register for valid address */
308 for (i = 0; i < 4; i++) {
309 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
310 top = macb_or_gem_readl(bp, SA1T + i * 8);
311
312 addr[0] = bottom & 0xff;
313 addr[1] = (bottom >> 8) & 0xff;
314 addr[2] = (bottom >> 16) & 0xff;
315 addr[3] = (bottom >> 24) & 0xff;
316 addr[4] = top & 0xff;
317 addr[5] = (top >> 8) & 0xff;
318
319 if (is_valid_ether_addr(addr)) {
320 eth_hw_addr_set(bp->dev, addr);
321 return;
322 }
323 }
324
325 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
326 eth_hw_addr_random(bp->dev);
327 }
328
macb_mdio_wait_for_idle(struct macb * bp)329 static int macb_mdio_wait_for_idle(struct macb *bp)
330 {
331 u32 val;
332
333 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
334 1, MACB_MDIO_TIMEOUT);
335 }
336
macb_mdio_read_c22(struct mii_bus * bus,int mii_id,int regnum)337 static int macb_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum)
338 {
339 struct macb *bp = bus->priv;
340 int status;
341
342 status = pm_runtime_resume_and_get(&bp->pdev->dev);
343 if (status < 0)
344 goto mdio_pm_exit;
345
346 status = macb_mdio_wait_for_idle(bp);
347 if (status < 0)
348 goto mdio_read_exit;
349
350 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
351 | MACB_BF(RW, MACB_MAN_C22_READ)
352 | MACB_BF(PHYA, mii_id)
353 | MACB_BF(REGA, regnum)
354 | MACB_BF(CODE, MACB_MAN_C22_CODE)));
355
356 status = macb_mdio_wait_for_idle(bp);
357 if (status < 0)
358 goto mdio_read_exit;
359
360 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
361
362 mdio_read_exit:
363 pm_runtime_mark_last_busy(&bp->pdev->dev);
364 pm_runtime_put_autosuspend(&bp->pdev->dev);
365 mdio_pm_exit:
366 return status;
367 }
368
macb_mdio_read_c45(struct mii_bus * bus,int mii_id,int devad,int regnum)369 static int macb_mdio_read_c45(struct mii_bus *bus, int mii_id, int devad,
370 int regnum)
371 {
372 struct macb *bp = bus->priv;
373 int status;
374
375 status = pm_runtime_get_sync(&bp->pdev->dev);
376 if (status < 0) {
377 pm_runtime_put_noidle(&bp->pdev->dev);
378 goto mdio_pm_exit;
379 }
380
381 status = macb_mdio_wait_for_idle(bp);
382 if (status < 0)
383 goto mdio_read_exit;
384
385 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
386 | MACB_BF(RW, MACB_MAN_C45_ADDR)
387 | MACB_BF(PHYA, mii_id)
388 | MACB_BF(REGA, devad & 0x1F)
389 | MACB_BF(DATA, regnum & 0xFFFF)
390 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
391
392 status = macb_mdio_wait_for_idle(bp);
393 if (status < 0)
394 goto mdio_read_exit;
395
396 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
397 | MACB_BF(RW, MACB_MAN_C45_READ)
398 | MACB_BF(PHYA, mii_id)
399 | MACB_BF(REGA, devad & 0x1F)
400 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
401
402 status = macb_mdio_wait_for_idle(bp);
403 if (status < 0)
404 goto mdio_read_exit;
405
406 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
407
408 mdio_read_exit:
409 pm_runtime_mark_last_busy(&bp->pdev->dev);
410 pm_runtime_put_autosuspend(&bp->pdev->dev);
411 mdio_pm_exit:
412 return status;
413 }
414
macb_mdio_write_c22(struct mii_bus * bus,int mii_id,int regnum,u16 value)415 static int macb_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,
416 u16 value)
417 {
418 struct macb *bp = bus->priv;
419 int status;
420
421 status = pm_runtime_resume_and_get(&bp->pdev->dev);
422 if (status < 0)
423 goto mdio_pm_exit;
424
425 status = macb_mdio_wait_for_idle(bp);
426 if (status < 0)
427 goto mdio_write_exit;
428
429 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
430 | MACB_BF(RW, MACB_MAN_C22_WRITE)
431 | MACB_BF(PHYA, mii_id)
432 | MACB_BF(REGA, regnum)
433 | MACB_BF(CODE, MACB_MAN_C22_CODE)
434 | MACB_BF(DATA, value)));
435
436 status = macb_mdio_wait_for_idle(bp);
437 if (status < 0)
438 goto mdio_write_exit;
439
440 mdio_write_exit:
441 pm_runtime_mark_last_busy(&bp->pdev->dev);
442 pm_runtime_put_autosuspend(&bp->pdev->dev);
443 mdio_pm_exit:
444 return status;
445 }
446
macb_mdio_write_c45(struct mii_bus * bus,int mii_id,int devad,int regnum,u16 value)447 static int macb_mdio_write_c45(struct mii_bus *bus, int mii_id,
448 int devad, int regnum,
449 u16 value)
450 {
451 struct macb *bp = bus->priv;
452 int status;
453
454 status = pm_runtime_get_sync(&bp->pdev->dev);
455 if (status < 0) {
456 pm_runtime_put_noidle(&bp->pdev->dev);
457 goto mdio_pm_exit;
458 }
459
460 status = macb_mdio_wait_for_idle(bp);
461 if (status < 0)
462 goto mdio_write_exit;
463
464 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
465 | MACB_BF(RW, MACB_MAN_C45_ADDR)
466 | MACB_BF(PHYA, mii_id)
467 | MACB_BF(REGA, devad & 0x1F)
468 | MACB_BF(DATA, regnum & 0xFFFF)
469 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
470
471 status = macb_mdio_wait_for_idle(bp);
472 if (status < 0)
473 goto mdio_write_exit;
474
475 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
476 | MACB_BF(RW, MACB_MAN_C45_WRITE)
477 | MACB_BF(PHYA, mii_id)
478 | MACB_BF(REGA, devad & 0x1F)
479 | MACB_BF(CODE, MACB_MAN_C45_CODE)
480 | MACB_BF(DATA, value)));
481
482 status = macb_mdio_wait_for_idle(bp);
483 if (status < 0)
484 goto mdio_write_exit;
485
486 mdio_write_exit:
487 pm_runtime_mark_last_busy(&bp->pdev->dev);
488 pm_runtime_put_autosuspend(&bp->pdev->dev);
489 mdio_pm_exit:
490 return status;
491 }
492
macb_init_buffers(struct macb * bp)493 static void macb_init_buffers(struct macb *bp)
494 {
495 struct macb_queue *queue;
496 unsigned int q;
497
498 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
499 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
500 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
501 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
502 queue_writel(queue, RBQPH,
503 upper_32_bits(queue->rx_ring_dma));
504 #endif
505 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
506 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
507 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
508 queue_writel(queue, TBQPH,
509 upper_32_bits(queue->tx_ring_dma));
510 #endif
511 }
512 }
513
514 /**
515 * macb_set_tx_clk() - Set a clock to a new frequency
516 * @bp: pointer to struct macb
517 * @speed: New frequency in Hz
518 */
macb_set_tx_clk(struct macb * bp,int speed)519 static void macb_set_tx_clk(struct macb *bp, int speed)
520 {
521 long ferr, rate, rate_rounded;
522
523 if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG))
524 return;
525
526 /* In case of MII the PHY is the clock master */
527 if (bp->phy_interface == PHY_INTERFACE_MODE_MII)
528 return;
529
530 rate = rgmii_clock(speed);
531 if (rate < 0)
532 return;
533
534 rate_rounded = clk_round_rate(bp->tx_clk, rate);
535 if (rate_rounded < 0)
536 return;
537
538 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
539 * is not satisfied.
540 */
541 ferr = abs(rate_rounded - rate);
542 ferr = DIV_ROUND_UP(ferr, rate / 100000);
543 if (ferr > 5)
544 netdev_warn(bp->dev,
545 "unable to generate target frequency: %ld Hz\n",
546 rate);
547
548 if (clk_set_rate(bp->tx_clk, rate_rounded))
549 netdev_err(bp->dev, "adjusting tx_clk failed.\n");
550 }
551
macb_usx_pcs_link_up(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,int speed,int duplex)552 static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
553 phy_interface_t interface, int speed,
554 int duplex)
555 {
556 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
557 u32 config;
558
559 config = gem_readl(bp, USX_CONTROL);
560 config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_10G, config);
561 config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_10000M, config);
562 config &= ~(GEM_BIT(TX_SCR_BYPASS) | GEM_BIT(RX_SCR_BYPASS));
563 config |= GEM_BIT(TX_EN);
564 gem_writel(bp, USX_CONTROL, config);
565 }
566
macb_usx_pcs_get_state(struct phylink_pcs * pcs,unsigned int neg_mode,struct phylink_link_state * state)567 static void macb_usx_pcs_get_state(struct phylink_pcs *pcs,
568 unsigned int neg_mode,
569 struct phylink_link_state *state)
570 {
571 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
572 u32 val;
573
574 state->speed = SPEED_10000;
575 state->duplex = 1;
576 state->an_complete = 1;
577
578 val = gem_readl(bp, USX_STATUS);
579 state->link = !!(val & GEM_BIT(USX_BLOCK_LOCK));
580 val = gem_readl(bp, NCFGR);
581 if (val & GEM_BIT(PAE))
582 state->pause = MLO_PAUSE_RX;
583 }
584
macb_usx_pcs_config(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,const unsigned long * advertising,bool permit_pause_to_mac)585 static int macb_usx_pcs_config(struct phylink_pcs *pcs,
586 unsigned int neg_mode,
587 phy_interface_t interface,
588 const unsigned long *advertising,
589 bool permit_pause_to_mac)
590 {
591 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
592
593 gem_writel(bp, USX_CONTROL, gem_readl(bp, USX_CONTROL) |
594 GEM_BIT(SIGNAL_OK));
595
596 return 0;
597 }
598
macb_pcs_get_state(struct phylink_pcs * pcs,unsigned int neg_mode,struct phylink_link_state * state)599 static void macb_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode,
600 struct phylink_link_state *state)
601 {
602 state->link = 0;
603 }
604
macb_pcs_an_restart(struct phylink_pcs * pcs)605 static void macb_pcs_an_restart(struct phylink_pcs *pcs)
606 {
607 /* Not supported */
608 }
609
macb_pcs_config(struct phylink_pcs * pcs,unsigned int neg_mode,phy_interface_t interface,const unsigned long * advertising,bool permit_pause_to_mac)610 static int macb_pcs_config(struct phylink_pcs *pcs,
611 unsigned int neg_mode,
612 phy_interface_t interface,
613 const unsigned long *advertising,
614 bool permit_pause_to_mac)
615 {
616 return 0;
617 }
618
619 static const struct phylink_pcs_ops macb_phylink_usx_pcs_ops = {
620 .pcs_get_state = macb_usx_pcs_get_state,
621 .pcs_config = macb_usx_pcs_config,
622 .pcs_link_up = macb_usx_pcs_link_up,
623 };
624
625 static const struct phylink_pcs_ops macb_phylink_pcs_ops = {
626 .pcs_get_state = macb_pcs_get_state,
627 .pcs_an_restart = macb_pcs_an_restart,
628 .pcs_config = macb_pcs_config,
629 };
630
macb_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)631 static void macb_mac_config(struct phylink_config *config, unsigned int mode,
632 const struct phylink_link_state *state)
633 {
634 struct net_device *ndev = to_net_dev(config->dev);
635 struct macb *bp = netdev_priv(ndev);
636 unsigned long flags;
637 u32 old_ctrl, ctrl;
638 u32 old_ncr, ncr;
639
640 spin_lock_irqsave(&bp->lock, flags);
641
642 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
643 old_ncr = ncr = macb_or_gem_readl(bp, NCR);
644
645 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
646 if (state->interface == PHY_INTERFACE_MODE_RMII)
647 ctrl |= MACB_BIT(RM9200_RMII);
648 } else if (macb_is_gem(bp)) {
649 ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
650 ncr &= ~GEM_BIT(ENABLE_HS_MAC);
651
652 if (state->interface == PHY_INTERFACE_MODE_SGMII) {
653 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
654 } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) {
655 ctrl |= GEM_BIT(PCSSEL);
656 ncr |= GEM_BIT(ENABLE_HS_MAC);
657 } else if (bp->caps & MACB_CAPS_MIIONRGMII &&
658 bp->phy_interface == PHY_INTERFACE_MODE_MII) {
659 ncr |= MACB_BIT(MIIONRGMII);
660 }
661 }
662
663 /* Apply the new configuration, if any */
664 if (old_ctrl ^ ctrl)
665 macb_or_gem_writel(bp, NCFGR, ctrl);
666
667 if (old_ncr ^ ncr)
668 macb_or_gem_writel(bp, NCR, ncr);
669
670 /* Disable AN for SGMII fixed link configuration, enable otherwise.
671 * Must be written after PCSSEL is set in NCFGR,
672 * otherwise writes will not take effect.
673 */
674 if (macb_is_gem(bp) && state->interface == PHY_INTERFACE_MODE_SGMII) {
675 u32 pcsctrl, old_pcsctrl;
676
677 old_pcsctrl = gem_readl(bp, PCSCNTRL);
678 if (mode == MLO_AN_FIXED)
679 pcsctrl = old_pcsctrl & ~GEM_BIT(PCSAUTONEG);
680 else
681 pcsctrl = old_pcsctrl | GEM_BIT(PCSAUTONEG);
682 if (old_pcsctrl != pcsctrl)
683 gem_writel(bp, PCSCNTRL, pcsctrl);
684 }
685
686 spin_unlock_irqrestore(&bp->lock, flags);
687 }
688
macb_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)689 static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
690 phy_interface_t interface)
691 {
692 struct net_device *ndev = to_net_dev(config->dev);
693 struct macb *bp = netdev_priv(ndev);
694 struct macb_queue *queue;
695 unsigned int q;
696 u32 ctrl;
697
698 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
699 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
700 queue_writel(queue, IDR,
701 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
702
703 /* Disable Rx and Tx */
704 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
705 macb_writel(bp, NCR, ctrl);
706
707 netif_tx_stop_all_queues(ndev);
708 }
709
macb_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)710 static void macb_mac_link_up(struct phylink_config *config,
711 struct phy_device *phy,
712 unsigned int mode, phy_interface_t interface,
713 int speed, int duplex,
714 bool tx_pause, bool rx_pause)
715 {
716 struct net_device *ndev = to_net_dev(config->dev);
717 struct macb *bp = netdev_priv(ndev);
718 struct macb_queue *queue;
719 unsigned long flags;
720 unsigned int q;
721 u32 ctrl;
722
723 spin_lock_irqsave(&bp->lock, flags);
724
725 ctrl = macb_or_gem_readl(bp, NCFGR);
726
727 ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
728
729 if (speed == SPEED_100)
730 ctrl |= MACB_BIT(SPD);
731
732 if (duplex)
733 ctrl |= MACB_BIT(FD);
734
735 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
736 ctrl &= ~MACB_BIT(PAE);
737 if (macb_is_gem(bp)) {
738 ctrl &= ~GEM_BIT(GBE);
739
740 if (speed == SPEED_1000)
741 ctrl |= GEM_BIT(GBE);
742 }
743
744 if (rx_pause)
745 ctrl |= MACB_BIT(PAE);
746
747 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
748 * cleared the pipeline and control registers.
749 */
750 bp->macbgem_ops.mog_init_rings(bp);
751 macb_init_buffers(bp);
752
753 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
754 queue_writel(queue, IER,
755 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
756 }
757
758 macb_or_gem_writel(bp, NCFGR, ctrl);
759
760 if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER)
761 gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M,
762 gem_readl(bp, HS_MAC_CONFIG)));
763
764 spin_unlock_irqrestore(&bp->lock, flags);
765
766 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
767 macb_set_tx_clk(bp, speed);
768
769 /* Enable Rx and Tx; Enable PTP unicast */
770 ctrl = macb_readl(bp, NCR);
771 if (gem_has_ptp(bp))
772 ctrl |= MACB_BIT(PTPUNI);
773
774 macb_writel(bp, NCR, ctrl | MACB_BIT(RE) | MACB_BIT(TE));
775
776 netif_tx_wake_all_queues(ndev);
777 }
778
macb_mac_select_pcs(struct phylink_config * config,phy_interface_t interface)779 static struct phylink_pcs *macb_mac_select_pcs(struct phylink_config *config,
780 phy_interface_t interface)
781 {
782 struct net_device *ndev = to_net_dev(config->dev);
783 struct macb *bp = netdev_priv(ndev);
784
785 if (interface == PHY_INTERFACE_MODE_10GBASER)
786 return &bp->phylink_usx_pcs;
787 else if (interface == PHY_INTERFACE_MODE_SGMII)
788 return &bp->phylink_sgmii_pcs;
789 else
790 return NULL;
791 }
792
793 static const struct phylink_mac_ops macb_phylink_ops = {
794 .mac_select_pcs = macb_mac_select_pcs,
795 .mac_config = macb_mac_config,
796 .mac_link_down = macb_mac_link_down,
797 .mac_link_up = macb_mac_link_up,
798 };
799
macb_phy_handle_exists(struct device_node * dn)800 static bool macb_phy_handle_exists(struct device_node *dn)
801 {
802 dn = of_parse_phandle(dn, "phy-handle", 0);
803 of_node_put(dn);
804 return dn != NULL;
805 }
806
macb_phylink_connect(struct macb * bp)807 static int macb_phylink_connect(struct macb *bp)
808 {
809 struct device_node *dn = bp->pdev->dev.of_node;
810 struct net_device *dev = bp->dev;
811 struct phy_device *phydev;
812 int ret;
813
814 if (dn)
815 ret = phylink_of_phy_connect(bp->phylink, dn, 0);
816
817 if (!dn || (ret && !macb_phy_handle_exists(dn))) {
818 phydev = phy_find_first(bp->mii_bus);
819 if (!phydev) {
820 netdev_err(dev, "no PHY found\n");
821 return -ENXIO;
822 }
823
824 /* attach the mac to the phy */
825 ret = phylink_connect_phy(bp->phylink, phydev);
826 }
827
828 if (ret) {
829 netdev_err(dev, "Could not attach PHY (%d)\n", ret);
830 return ret;
831 }
832
833 phylink_start(bp->phylink);
834
835 return 0;
836 }
837
macb_get_pcs_fixed_state(struct phylink_config * config,struct phylink_link_state * state)838 static void macb_get_pcs_fixed_state(struct phylink_config *config,
839 struct phylink_link_state *state)
840 {
841 struct net_device *ndev = to_net_dev(config->dev);
842 struct macb *bp = netdev_priv(ndev);
843
844 state->link = (macb_readl(bp, NSR) & MACB_BIT(NSR_LINK)) != 0;
845 }
846
847 /* based on au1000_eth. c*/
macb_mii_probe(struct net_device * dev)848 static int macb_mii_probe(struct net_device *dev)
849 {
850 struct macb *bp = netdev_priv(dev);
851
852 bp->phylink_sgmii_pcs.ops = &macb_phylink_pcs_ops;
853 bp->phylink_usx_pcs.ops = &macb_phylink_usx_pcs_ops;
854
855 bp->phylink_config.dev = &dev->dev;
856 bp->phylink_config.type = PHYLINK_NETDEV;
857 bp->phylink_config.mac_managed_pm = true;
858
859 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
860 bp->phylink_config.poll_fixed_state = true;
861 bp->phylink_config.get_fixed_state = macb_get_pcs_fixed_state;
862 }
863
864 bp->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
865 MAC_10 | MAC_100;
866
867 __set_bit(PHY_INTERFACE_MODE_MII,
868 bp->phylink_config.supported_interfaces);
869 __set_bit(PHY_INTERFACE_MODE_RMII,
870 bp->phylink_config.supported_interfaces);
871
872 /* Determine what modes are supported */
873 if (macb_is_gem(bp) && (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)) {
874 bp->phylink_config.mac_capabilities |= MAC_1000FD;
875 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
876 bp->phylink_config.mac_capabilities |= MAC_1000HD;
877
878 __set_bit(PHY_INTERFACE_MODE_GMII,
879 bp->phylink_config.supported_interfaces);
880 phy_interface_set_rgmii(bp->phylink_config.supported_interfaces);
881
882 if (bp->caps & MACB_CAPS_PCS)
883 __set_bit(PHY_INTERFACE_MODE_SGMII,
884 bp->phylink_config.supported_interfaces);
885
886 if (bp->caps & MACB_CAPS_HIGH_SPEED) {
887 __set_bit(PHY_INTERFACE_MODE_10GBASER,
888 bp->phylink_config.supported_interfaces);
889 bp->phylink_config.mac_capabilities |= MAC_10000FD;
890 }
891 }
892
893 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
894 bp->phy_interface, &macb_phylink_ops);
895 if (IS_ERR(bp->phylink)) {
896 netdev_err(dev, "Could not create a phylink instance (%ld)\n",
897 PTR_ERR(bp->phylink));
898 return PTR_ERR(bp->phylink);
899 }
900
901 return 0;
902 }
903
macb_mdiobus_register(struct macb * bp,struct device_node * mdio_np)904 static int macb_mdiobus_register(struct macb *bp, struct device_node *mdio_np)
905 {
906 struct device_node *child, *np = bp->pdev->dev.of_node;
907
908 /* If we have a child named mdio, probe it instead of looking for PHYs
909 * directly under the MAC node
910 */
911 if (mdio_np)
912 return of_mdiobus_register(bp->mii_bus, mdio_np);
913
914 /* Only create the PHY from the device tree if at least one PHY is
915 * described. Otherwise scan the entire MDIO bus. We do this to support
916 * old device tree that did not follow the best practices and did not
917 * describe their network PHYs.
918 */
919 for_each_available_child_of_node(np, child)
920 if (of_mdiobus_child_is_phy(child)) {
921 /* The loop increments the child refcount,
922 * decrement it before returning.
923 */
924 of_node_put(child);
925
926 return of_mdiobus_register(bp->mii_bus, np);
927 }
928
929 return mdiobus_register(bp->mii_bus);
930 }
931
macb_mii_init(struct macb * bp)932 static int macb_mii_init(struct macb *bp)
933 {
934 struct device_node *mdio_np, *np = bp->pdev->dev.of_node;
935 int err = -ENXIO;
936
937 /* With fixed-link, we don't need to register the MDIO bus,
938 * except if we have a child named "mdio" in the device tree.
939 * In that case, some devices may be attached to the MACB's MDIO bus.
940 */
941 mdio_np = of_get_child_by_name(np, "mdio");
942 if (!mdio_np && of_phy_is_fixed_link(np))
943 return macb_mii_probe(bp->dev);
944
945 /* Enable management port */
946 macb_writel(bp, NCR, MACB_BIT(MPE));
947
948 bp->mii_bus = mdiobus_alloc();
949 if (!bp->mii_bus) {
950 err = -ENOMEM;
951 goto err_out;
952 }
953
954 bp->mii_bus->name = "MACB_mii_bus";
955 bp->mii_bus->read = &macb_mdio_read_c22;
956 bp->mii_bus->write = &macb_mdio_write_c22;
957 bp->mii_bus->read_c45 = &macb_mdio_read_c45;
958 bp->mii_bus->write_c45 = &macb_mdio_write_c45;
959 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
960 bp->pdev->name, bp->pdev->id);
961 bp->mii_bus->priv = bp;
962 bp->mii_bus->parent = &bp->pdev->dev;
963
964 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
965
966 err = macb_mdiobus_register(bp, mdio_np);
967 if (err)
968 goto err_out_free_mdiobus;
969
970 err = macb_mii_probe(bp->dev);
971 if (err)
972 goto err_out_unregister_bus;
973
974 return 0;
975
976 err_out_unregister_bus:
977 mdiobus_unregister(bp->mii_bus);
978 err_out_free_mdiobus:
979 mdiobus_free(bp->mii_bus);
980 err_out:
981 of_node_put(mdio_np);
982
983 return err;
984 }
985
macb_update_stats(struct macb * bp)986 static void macb_update_stats(struct macb *bp)
987 {
988 u64 *p = &bp->hw_stats.macb.rx_pause_frames;
989 u64 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
990 int offset = MACB_PFR;
991
992 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
993
994 for (; p < end; p++, offset += 4)
995 *p += bp->macb_reg_readl(bp, offset);
996 }
997
macb_halt_tx(struct macb * bp)998 static int macb_halt_tx(struct macb *bp)
999 {
1000 unsigned long halt_time, timeout;
1001 u32 status;
1002
1003 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
1004
1005 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
1006 do {
1007 halt_time = jiffies;
1008 status = macb_readl(bp, TSR);
1009 if (!(status & MACB_BIT(TGO)))
1010 return 0;
1011
1012 udelay(250);
1013 } while (time_before(halt_time, timeout));
1014
1015 return -ETIMEDOUT;
1016 }
1017
macb_tx_unmap(struct macb * bp,struct macb_tx_skb * tx_skb,int budget)1018 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb, int budget)
1019 {
1020 if (tx_skb->mapping) {
1021 if (tx_skb->mapped_as_page)
1022 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
1023 tx_skb->size, DMA_TO_DEVICE);
1024 else
1025 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
1026 tx_skb->size, DMA_TO_DEVICE);
1027 tx_skb->mapping = 0;
1028 }
1029
1030 if (tx_skb->skb) {
1031 napi_consume_skb(tx_skb->skb, budget);
1032 tx_skb->skb = NULL;
1033 }
1034 }
1035
macb_set_addr(struct macb * bp,struct macb_dma_desc * desc,dma_addr_t addr)1036 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
1037 {
1038 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1039 struct macb_dma_desc_64 *desc_64;
1040
1041 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
1042 desc_64 = macb_64b_desc(bp, desc);
1043 desc_64->addrh = upper_32_bits(addr);
1044 /* The low bits of RX address contain the RX_USED bit, clearing
1045 * of which allows packet RX. Make sure the high bits are also
1046 * visible to HW at that point.
1047 */
1048 dma_wmb();
1049 }
1050 #endif
1051 desc->addr = lower_32_bits(addr);
1052 }
1053
macb_get_addr(struct macb * bp,struct macb_dma_desc * desc)1054 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
1055 {
1056 dma_addr_t addr = 0;
1057 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1058 struct macb_dma_desc_64 *desc_64;
1059
1060 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
1061 desc_64 = macb_64b_desc(bp, desc);
1062 addr = ((u64)(desc_64->addrh) << 32);
1063 }
1064 #endif
1065 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1066 #ifdef CONFIG_MACB_USE_HWSTAMP
1067 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
1068 addr &= ~GEM_BIT(DMA_RXVALID);
1069 #endif
1070 return addr;
1071 }
1072
macb_tx_error_task(struct work_struct * work)1073 static void macb_tx_error_task(struct work_struct *work)
1074 {
1075 struct macb_queue *queue = container_of(work, struct macb_queue,
1076 tx_error_task);
1077 bool halt_timeout = false;
1078 struct macb *bp = queue->bp;
1079 u32 queue_index;
1080 u32 packets = 0;
1081 u32 bytes = 0;
1082 struct macb_tx_skb *tx_skb;
1083 struct macb_dma_desc *desc;
1084 struct sk_buff *skb;
1085 unsigned int tail;
1086 unsigned long flags;
1087
1088 queue_index = queue - bp->queues;
1089 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
1090 queue_index, queue->tx_tail, queue->tx_head);
1091
1092 /* Prevent the queue NAPI TX poll from running, as it calls
1093 * macb_tx_complete(), which in turn may call netif_wake_subqueue().
1094 * As explained below, we have to halt the transmission before updating
1095 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
1096 * network engine about the macb/gem being halted.
1097 */
1098 napi_disable(&queue->napi_tx);
1099 spin_lock_irqsave(&bp->lock, flags);
1100
1101 /* Make sure nobody is trying to queue up new packets */
1102 netif_tx_stop_all_queues(bp->dev);
1103
1104 /* Stop transmission now
1105 * (in case we have just queued new packets)
1106 * macb/gem must be halted to write TBQP register
1107 */
1108 if (macb_halt_tx(bp)) {
1109 netdev_err(bp->dev, "BUG: halt tx timed out\n");
1110 macb_writel(bp, NCR, macb_readl(bp, NCR) & (~MACB_BIT(TE)));
1111 halt_timeout = true;
1112 }
1113
1114 /* Treat frames in TX queue including the ones that caused the error.
1115 * Free transmit buffers in upper layer.
1116 */
1117 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
1118 u32 ctrl;
1119
1120 desc = macb_tx_desc(queue, tail);
1121 ctrl = desc->ctrl;
1122 tx_skb = macb_tx_skb(queue, tail);
1123 skb = tx_skb->skb;
1124
1125 if (ctrl & MACB_BIT(TX_USED)) {
1126 /* skb is set for the last buffer of the frame */
1127 while (!skb) {
1128 macb_tx_unmap(bp, tx_skb, 0);
1129 tail++;
1130 tx_skb = macb_tx_skb(queue, tail);
1131 skb = tx_skb->skb;
1132 }
1133
1134 /* ctrl still refers to the first buffer descriptor
1135 * since it's the only one written back by the hardware
1136 */
1137 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
1138 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
1139 macb_tx_ring_wrap(bp, tail),
1140 skb->data);
1141 bp->dev->stats.tx_packets++;
1142 queue->stats.tx_packets++;
1143 packets++;
1144 bp->dev->stats.tx_bytes += skb->len;
1145 queue->stats.tx_bytes += skb->len;
1146 bytes += skb->len;
1147 }
1148 } else {
1149 /* "Buffers exhausted mid-frame" errors may only happen
1150 * if the driver is buggy, so complain loudly about
1151 * those. Statistics are updated by hardware.
1152 */
1153 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
1154 netdev_err(bp->dev,
1155 "BUG: TX buffers exhausted mid-frame\n");
1156
1157 desc->ctrl = ctrl | MACB_BIT(TX_USED);
1158 }
1159
1160 macb_tx_unmap(bp, tx_skb, 0);
1161 }
1162
1163 netdev_tx_completed_queue(netdev_get_tx_queue(bp->dev, queue_index),
1164 packets, bytes);
1165
1166 /* Set end of TX queue */
1167 desc = macb_tx_desc(queue, 0);
1168 macb_set_addr(bp, desc, 0);
1169 desc->ctrl = MACB_BIT(TX_USED);
1170
1171 /* Make descriptor updates visible to hardware */
1172 wmb();
1173
1174 /* Reinitialize the TX desc queue */
1175 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1176 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1177 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1178 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
1179 #endif
1180 /* Make TX ring reflect state of hardware */
1181 queue->tx_head = 0;
1182 queue->tx_tail = 0;
1183
1184 /* Housework before enabling TX IRQ */
1185 macb_writel(bp, TSR, macb_readl(bp, TSR));
1186 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
1187
1188 if (halt_timeout)
1189 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TE));
1190
1191 /* Now we are ready to start transmission again */
1192 netif_tx_start_all_queues(bp->dev);
1193 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1194
1195 spin_unlock_irqrestore(&bp->lock, flags);
1196 napi_enable(&queue->napi_tx);
1197 }
1198
ptp_one_step_sync(struct sk_buff * skb)1199 static bool ptp_one_step_sync(struct sk_buff *skb)
1200 {
1201 struct ptp_header *hdr;
1202 unsigned int ptp_class;
1203 u8 msgtype;
1204
1205 /* No need to parse packet if PTP TS is not involved */
1206 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
1207 goto not_oss;
1208
1209 /* Identify and return whether PTP one step sync is being processed */
1210 ptp_class = ptp_classify_raw(skb);
1211 if (ptp_class == PTP_CLASS_NONE)
1212 goto not_oss;
1213
1214 hdr = ptp_parse_header(skb, ptp_class);
1215 if (!hdr)
1216 goto not_oss;
1217
1218 if (hdr->flag_field[0] & PTP_FLAG_TWOSTEP)
1219 goto not_oss;
1220
1221 msgtype = ptp_get_msgtype(hdr, ptp_class);
1222 if (msgtype == PTP_MSGTYPE_SYNC)
1223 return true;
1224
1225 not_oss:
1226 return false;
1227 }
1228
macb_tx_complete(struct macb_queue * queue,int budget)1229 static int macb_tx_complete(struct macb_queue *queue, int budget)
1230 {
1231 struct macb *bp = queue->bp;
1232 u16 queue_index = queue - bp->queues;
1233 unsigned int tail;
1234 unsigned int head;
1235 int packets = 0;
1236 u32 bytes = 0;
1237
1238 spin_lock(&queue->tx_ptr_lock);
1239 head = queue->tx_head;
1240 for (tail = queue->tx_tail; tail != head && packets < budget; tail++) {
1241 struct macb_tx_skb *tx_skb;
1242 struct sk_buff *skb;
1243 struct macb_dma_desc *desc;
1244 u32 ctrl;
1245
1246 desc = macb_tx_desc(queue, tail);
1247
1248 /* Make hw descriptor updates visible to CPU */
1249 rmb();
1250
1251 ctrl = desc->ctrl;
1252
1253 /* TX_USED bit is only set by hardware on the very first buffer
1254 * descriptor of the transmitted frame.
1255 */
1256 if (!(ctrl & MACB_BIT(TX_USED)))
1257 break;
1258
1259 /* Process all buffers of the current transmitted frame */
1260 for (;; tail++) {
1261 tx_skb = macb_tx_skb(queue, tail);
1262 skb = tx_skb->skb;
1263
1264 /* First, update TX stats if needed */
1265 if (skb) {
1266 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1267 !ptp_one_step_sync(skb))
1268 gem_ptp_do_txstamp(bp, skb, desc);
1269
1270 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
1271 macb_tx_ring_wrap(bp, tail),
1272 skb->data);
1273 bp->dev->stats.tx_packets++;
1274 queue->stats.tx_packets++;
1275 bp->dev->stats.tx_bytes += skb->len;
1276 queue->stats.tx_bytes += skb->len;
1277 packets++;
1278 bytes += skb->len;
1279 }
1280
1281 /* Now we can safely release resources */
1282 macb_tx_unmap(bp, tx_skb, budget);
1283
1284 /* skb is set only for the last buffer of the frame.
1285 * WARNING: at this point skb has been freed by
1286 * macb_tx_unmap().
1287 */
1288 if (skb)
1289 break;
1290 }
1291 }
1292
1293 netdev_tx_completed_queue(netdev_get_tx_queue(bp->dev, queue_index),
1294 packets, bytes);
1295
1296 queue->tx_tail = tail;
1297 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
1298 CIRC_CNT(queue->tx_head, queue->tx_tail,
1299 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1300 netif_wake_subqueue(bp->dev, queue_index);
1301 spin_unlock(&queue->tx_ptr_lock);
1302
1303 return packets;
1304 }
1305
gem_rx_refill(struct macb_queue * queue)1306 static void gem_rx_refill(struct macb_queue *queue)
1307 {
1308 unsigned int entry;
1309 struct sk_buff *skb;
1310 dma_addr_t paddr;
1311 struct macb *bp = queue->bp;
1312 struct macb_dma_desc *desc;
1313
1314 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1315 bp->rx_ring_size) > 0) {
1316 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1317
1318 /* Make hw descriptor updates visible to CPU */
1319 rmb();
1320
1321 desc = macb_rx_desc(queue, entry);
1322
1323 if (!queue->rx_skbuff[entry]) {
1324 /* allocate sk_buff for this free entry in ring */
1325 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1326 if (unlikely(!skb)) {
1327 netdev_err(bp->dev,
1328 "Unable to allocate sk_buff\n");
1329 break;
1330 }
1331
1332 /* now fill corresponding descriptor entry */
1333 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1334 bp->rx_buffer_size,
1335 DMA_FROM_DEVICE);
1336 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1337 dev_kfree_skb(skb);
1338 break;
1339 }
1340
1341 queue->rx_skbuff[entry] = skb;
1342
1343 if (entry == bp->rx_ring_size - 1)
1344 paddr |= MACB_BIT(RX_WRAP);
1345 desc->ctrl = 0;
1346 /* Setting addr clears RX_USED and allows reception,
1347 * make sure ctrl is cleared first to avoid a race.
1348 */
1349 dma_wmb();
1350 macb_set_addr(bp, desc, paddr);
1351
1352 /* properly align Ethernet header */
1353 skb_reserve(skb, NET_IP_ALIGN);
1354 } else {
1355 desc->ctrl = 0;
1356 dma_wmb();
1357 desc->addr &= ~MACB_BIT(RX_USED);
1358 }
1359 queue->rx_prepared_head++;
1360 }
1361
1362 /* Make descriptor updates visible to hardware */
1363 wmb();
1364
1365 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1366 queue, queue->rx_prepared_head, queue->rx_tail);
1367 }
1368
1369 /* Mark DMA descriptors from begin up to and not including end as unused */
discard_partial_frame(struct macb_queue * queue,unsigned int begin,unsigned int end)1370 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1371 unsigned int end)
1372 {
1373 unsigned int frag;
1374
1375 for (frag = begin; frag != end; frag++) {
1376 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1377
1378 desc->addr &= ~MACB_BIT(RX_USED);
1379 }
1380
1381 /* Make descriptor updates visible to hardware */
1382 wmb();
1383
1384 /* When this happens, the hardware stats registers for
1385 * whatever caused this is updated, so we don't have to record
1386 * anything.
1387 */
1388 }
1389
gem_rx(struct macb_queue * queue,struct napi_struct * napi,int budget)1390 static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1391 int budget)
1392 {
1393 struct macb *bp = queue->bp;
1394 unsigned int len;
1395 unsigned int entry;
1396 struct sk_buff *skb;
1397 struct macb_dma_desc *desc;
1398 int count = 0;
1399
1400 while (count < budget) {
1401 u32 ctrl;
1402 dma_addr_t addr;
1403 bool rxused;
1404
1405 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1406 desc = macb_rx_desc(queue, entry);
1407
1408 /* Make hw descriptor updates visible to CPU */
1409 rmb();
1410
1411 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1412 addr = macb_get_addr(bp, desc);
1413
1414 if (!rxused)
1415 break;
1416
1417 /* Ensure ctrl is at least as up-to-date as rxused */
1418 dma_rmb();
1419
1420 ctrl = desc->ctrl;
1421
1422 queue->rx_tail++;
1423 count++;
1424
1425 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1426 netdev_err(bp->dev,
1427 "not whole frame pointed by descriptor\n");
1428 bp->dev->stats.rx_dropped++;
1429 queue->stats.rx_dropped++;
1430 break;
1431 }
1432 skb = queue->rx_skbuff[entry];
1433 if (unlikely(!skb)) {
1434 netdev_err(bp->dev,
1435 "inconsistent Rx descriptor chain\n");
1436 bp->dev->stats.rx_dropped++;
1437 queue->stats.rx_dropped++;
1438 break;
1439 }
1440 /* now everything is ready for receiving packet */
1441 queue->rx_skbuff[entry] = NULL;
1442 len = ctrl & bp->rx_frm_len_mask;
1443
1444 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1445
1446 skb_put(skb, len);
1447 dma_unmap_single(&bp->pdev->dev, addr,
1448 bp->rx_buffer_size, DMA_FROM_DEVICE);
1449
1450 skb->protocol = eth_type_trans(skb, bp->dev);
1451 skb_checksum_none_assert(skb);
1452 if (bp->dev->features & NETIF_F_RXCSUM &&
1453 !(bp->dev->flags & IFF_PROMISC) &&
1454 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1455 skb->ip_summed = CHECKSUM_UNNECESSARY;
1456
1457 bp->dev->stats.rx_packets++;
1458 queue->stats.rx_packets++;
1459 bp->dev->stats.rx_bytes += skb->len;
1460 queue->stats.rx_bytes += skb->len;
1461
1462 gem_ptp_do_rxstamp(bp, skb, desc);
1463
1464 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1465 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1466 skb->len, skb->csum);
1467 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1468 skb_mac_header(skb), 16, true);
1469 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1470 skb->data, 32, true);
1471 #endif
1472
1473 napi_gro_receive(napi, skb);
1474 }
1475
1476 gem_rx_refill(queue);
1477
1478 return count;
1479 }
1480
macb_rx_frame(struct macb_queue * queue,struct napi_struct * napi,unsigned int first_frag,unsigned int last_frag)1481 static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1482 unsigned int first_frag, unsigned int last_frag)
1483 {
1484 unsigned int len;
1485 unsigned int frag;
1486 unsigned int offset;
1487 struct sk_buff *skb;
1488 struct macb_dma_desc *desc;
1489 struct macb *bp = queue->bp;
1490
1491 desc = macb_rx_desc(queue, last_frag);
1492 len = desc->ctrl & bp->rx_frm_len_mask;
1493
1494 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1495 macb_rx_ring_wrap(bp, first_frag),
1496 macb_rx_ring_wrap(bp, last_frag), len);
1497
1498 /* The ethernet header starts NET_IP_ALIGN bytes into the
1499 * first buffer. Since the header is 14 bytes, this makes the
1500 * payload word-aligned.
1501 *
1502 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1503 * the two padding bytes into the skb so that we avoid hitting
1504 * the slowpath in memcpy(), and pull them off afterwards.
1505 */
1506 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1507 if (!skb) {
1508 bp->dev->stats.rx_dropped++;
1509 for (frag = first_frag; ; frag++) {
1510 desc = macb_rx_desc(queue, frag);
1511 desc->addr &= ~MACB_BIT(RX_USED);
1512 if (frag == last_frag)
1513 break;
1514 }
1515
1516 /* Make descriptor updates visible to hardware */
1517 wmb();
1518
1519 return 1;
1520 }
1521
1522 offset = 0;
1523 len += NET_IP_ALIGN;
1524 skb_checksum_none_assert(skb);
1525 skb_put(skb, len);
1526
1527 for (frag = first_frag; ; frag++) {
1528 unsigned int frag_len = bp->rx_buffer_size;
1529
1530 if (offset + frag_len > len) {
1531 if (unlikely(frag != last_frag)) {
1532 dev_kfree_skb_any(skb);
1533 return -1;
1534 }
1535 frag_len = len - offset;
1536 }
1537 skb_copy_to_linear_data_offset(skb, offset,
1538 macb_rx_buffer(queue, frag),
1539 frag_len);
1540 offset += bp->rx_buffer_size;
1541 desc = macb_rx_desc(queue, frag);
1542 desc->addr &= ~MACB_BIT(RX_USED);
1543
1544 if (frag == last_frag)
1545 break;
1546 }
1547
1548 /* Make descriptor updates visible to hardware */
1549 wmb();
1550
1551 __skb_pull(skb, NET_IP_ALIGN);
1552 skb->protocol = eth_type_trans(skb, bp->dev);
1553
1554 bp->dev->stats.rx_packets++;
1555 bp->dev->stats.rx_bytes += skb->len;
1556 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1557 skb->len, skb->csum);
1558 napi_gro_receive(napi, skb);
1559
1560 return 0;
1561 }
1562
macb_init_rx_ring(struct macb_queue * queue)1563 static inline void macb_init_rx_ring(struct macb_queue *queue)
1564 {
1565 struct macb *bp = queue->bp;
1566 dma_addr_t addr;
1567 struct macb_dma_desc *desc = NULL;
1568 int i;
1569
1570 addr = queue->rx_buffers_dma;
1571 for (i = 0; i < bp->rx_ring_size; i++) {
1572 desc = macb_rx_desc(queue, i);
1573 macb_set_addr(bp, desc, addr);
1574 desc->ctrl = 0;
1575 addr += bp->rx_buffer_size;
1576 }
1577 desc->addr |= MACB_BIT(RX_WRAP);
1578 queue->rx_tail = 0;
1579 }
1580
macb_rx(struct macb_queue * queue,struct napi_struct * napi,int budget)1581 static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1582 int budget)
1583 {
1584 struct macb *bp = queue->bp;
1585 bool reset_rx_queue = false;
1586 int received = 0;
1587 unsigned int tail;
1588 int first_frag = -1;
1589
1590 for (tail = queue->rx_tail; budget > 0; tail++) {
1591 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1592 u32 ctrl;
1593
1594 /* Make hw descriptor updates visible to CPU */
1595 rmb();
1596
1597 if (!(desc->addr & MACB_BIT(RX_USED)))
1598 break;
1599
1600 /* Ensure ctrl is at least as up-to-date as addr */
1601 dma_rmb();
1602
1603 ctrl = desc->ctrl;
1604
1605 if (ctrl & MACB_BIT(RX_SOF)) {
1606 if (first_frag != -1)
1607 discard_partial_frame(queue, first_frag, tail);
1608 first_frag = tail;
1609 }
1610
1611 if (ctrl & MACB_BIT(RX_EOF)) {
1612 int dropped;
1613
1614 if (unlikely(first_frag == -1)) {
1615 reset_rx_queue = true;
1616 continue;
1617 }
1618
1619 dropped = macb_rx_frame(queue, napi, first_frag, tail);
1620 first_frag = -1;
1621 if (unlikely(dropped < 0)) {
1622 reset_rx_queue = true;
1623 continue;
1624 }
1625 if (!dropped) {
1626 received++;
1627 budget--;
1628 }
1629 }
1630 }
1631
1632 if (unlikely(reset_rx_queue)) {
1633 unsigned long flags;
1634 u32 ctrl;
1635
1636 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1637
1638 spin_lock_irqsave(&bp->lock, flags);
1639
1640 ctrl = macb_readl(bp, NCR);
1641 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1642
1643 macb_init_rx_ring(queue);
1644 queue_writel(queue, RBQP, queue->rx_ring_dma);
1645
1646 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1647
1648 spin_unlock_irqrestore(&bp->lock, flags);
1649 return received;
1650 }
1651
1652 if (first_frag != -1)
1653 queue->rx_tail = first_frag;
1654 else
1655 queue->rx_tail = tail;
1656
1657 return received;
1658 }
1659
macb_rx_pending(struct macb_queue * queue)1660 static bool macb_rx_pending(struct macb_queue *queue)
1661 {
1662 struct macb *bp = queue->bp;
1663 unsigned int entry;
1664 struct macb_dma_desc *desc;
1665
1666 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1667 desc = macb_rx_desc(queue, entry);
1668
1669 /* Make hw descriptor updates visible to CPU */
1670 rmb();
1671
1672 return (desc->addr & MACB_BIT(RX_USED)) != 0;
1673 }
1674
macb_rx_poll(struct napi_struct * napi,int budget)1675 static int macb_rx_poll(struct napi_struct *napi, int budget)
1676 {
1677 struct macb_queue *queue = container_of(napi, struct macb_queue, napi_rx);
1678 struct macb *bp = queue->bp;
1679 int work_done;
1680
1681 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1682
1683 netdev_vdbg(bp->dev, "RX poll: queue = %u, work_done = %d, budget = %d\n",
1684 (unsigned int)(queue - bp->queues), work_done, budget);
1685
1686 if (work_done < budget && napi_complete_done(napi, work_done)) {
1687 queue_writel(queue, IER, bp->rx_intr_mask);
1688
1689 /* Packet completions only seem to propagate to raise
1690 * interrupts when interrupts are enabled at the time, so if
1691 * packets were received while interrupts were disabled,
1692 * they will not cause another interrupt to be generated when
1693 * interrupts are re-enabled.
1694 * Check for this case here to avoid losing a wakeup. This can
1695 * potentially race with the interrupt handler doing the same
1696 * actions if an interrupt is raised just after enabling them,
1697 * but this should be harmless.
1698 */
1699 if (macb_rx_pending(queue)) {
1700 queue_writel(queue, IDR, bp->rx_intr_mask);
1701 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1702 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1703 netdev_vdbg(bp->dev, "poll: packets pending, reschedule\n");
1704 napi_schedule(napi);
1705 }
1706 }
1707
1708 /* TODO: Handle errors */
1709
1710 return work_done;
1711 }
1712
macb_tx_restart(struct macb_queue * queue)1713 static void macb_tx_restart(struct macb_queue *queue)
1714 {
1715 struct macb *bp = queue->bp;
1716 unsigned int head_idx, tbqp;
1717
1718 spin_lock(&queue->tx_ptr_lock);
1719
1720 if (queue->tx_head == queue->tx_tail)
1721 goto out_tx_ptr_unlock;
1722
1723 tbqp = queue_readl(queue, TBQP) / macb_dma_desc_get_size(bp);
1724 tbqp = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, tbqp));
1725 head_idx = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, queue->tx_head));
1726
1727 if (tbqp == head_idx)
1728 goto out_tx_ptr_unlock;
1729
1730 spin_lock_irq(&bp->lock);
1731 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1732 spin_unlock_irq(&bp->lock);
1733
1734 out_tx_ptr_unlock:
1735 spin_unlock(&queue->tx_ptr_lock);
1736 }
1737
macb_tx_complete_pending(struct macb_queue * queue)1738 static bool macb_tx_complete_pending(struct macb_queue *queue)
1739 {
1740 bool retval = false;
1741
1742 spin_lock(&queue->tx_ptr_lock);
1743 if (queue->tx_head != queue->tx_tail) {
1744 /* Make hw descriptor updates visible to CPU */
1745 rmb();
1746
1747 if (macb_tx_desc(queue, queue->tx_tail)->ctrl & MACB_BIT(TX_USED))
1748 retval = true;
1749 }
1750 spin_unlock(&queue->tx_ptr_lock);
1751 return retval;
1752 }
1753
macb_tx_poll(struct napi_struct * napi,int budget)1754 static int macb_tx_poll(struct napi_struct *napi, int budget)
1755 {
1756 struct macb_queue *queue = container_of(napi, struct macb_queue, napi_tx);
1757 struct macb *bp = queue->bp;
1758 int work_done;
1759
1760 work_done = macb_tx_complete(queue, budget);
1761
1762 rmb(); // ensure txubr_pending is up to date
1763 if (queue->txubr_pending) {
1764 queue->txubr_pending = false;
1765 netdev_vdbg(bp->dev, "poll: tx restart\n");
1766 macb_tx_restart(queue);
1767 }
1768
1769 netdev_vdbg(bp->dev, "TX poll: queue = %u, work_done = %d, budget = %d\n",
1770 (unsigned int)(queue - bp->queues), work_done, budget);
1771
1772 if (work_done < budget && napi_complete_done(napi, work_done)) {
1773 queue_writel(queue, IER, MACB_BIT(TCOMP));
1774
1775 /* Packet completions only seem to propagate to raise
1776 * interrupts when interrupts are enabled at the time, so if
1777 * packets were sent while interrupts were disabled,
1778 * they will not cause another interrupt to be generated when
1779 * interrupts are re-enabled.
1780 * Check for this case here to avoid losing a wakeup. This can
1781 * potentially race with the interrupt handler doing the same
1782 * actions if an interrupt is raised just after enabling them,
1783 * but this should be harmless.
1784 */
1785 if (macb_tx_complete_pending(queue)) {
1786 queue_writel(queue, IDR, MACB_BIT(TCOMP));
1787 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1788 queue_writel(queue, ISR, MACB_BIT(TCOMP));
1789 netdev_vdbg(bp->dev, "TX poll: packets pending, reschedule\n");
1790 napi_schedule(napi);
1791 }
1792 }
1793
1794 return work_done;
1795 }
1796
macb_hresp_error_task(struct work_struct * work)1797 static void macb_hresp_error_task(struct work_struct *work)
1798 {
1799 struct macb *bp = from_work(bp, work, hresp_err_bh_work);
1800 struct net_device *dev = bp->dev;
1801 struct macb_queue *queue;
1802 unsigned int q;
1803 u32 ctrl;
1804
1805 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1806 queue_writel(queue, IDR, bp->rx_intr_mask |
1807 MACB_TX_INT_FLAGS |
1808 MACB_BIT(HRESP));
1809 }
1810 ctrl = macb_readl(bp, NCR);
1811 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1812 macb_writel(bp, NCR, ctrl);
1813
1814 netif_tx_stop_all_queues(dev);
1815 netif_carrier_off(dev);
1816
1817 bp->macbgem_ops.mog_init_rings(bp);
1818
1819 /* Initialize TX and RX buffers */
1820 macb_init_buffers(bp);
1821
1822 /* Enable interrupts */
1823 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1824 queue_writel(queue, IER,
1825 bp->rx_intr_mask |
1826 MACB_TX_INT_FLAGS |
1827 MACB_BIT(HRESP));
1828
1829 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1830 macb_writel(bp, NCR, ctrl);
1831
1832 netif_carrier_on(dev);
1833 netif_tx_start_all_queues(dev);
1834 }
1835
macb_wol_interrupt(int irq,void * dev_id)1836 static irqreturn_t macb_wol_interrupt(int irq, void *dev_id)
1837 {
1838 struct macb_queue *queue = dev_id;
1839 struct macb *bp = queue->bp;
1840 u32 status;
1841
1842 status = queue_readl(queue, ISR);
1843
1844 if (unlikely(!status))
1845 return IRQ_NONE;
1846
1847 spin_lock(&bp->lock);
1848
1849 if (status & MACB_BIT(WOL)) {
1850 queue_writel(queue, IDR, MACB_BIT(WOL));
1851 macb_writel(bp, WOL, 0);
1852 netdev_vdbg(bp->dev, "MACB WoL: queue = %u, isr = 0x%08lx\n",
1853 (unsigned int)(queue - bp->queues),
1854 (unsigned long)status);
1855 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1856 queue_writel(queue, ISR, MACB_BIT(WOL));
1857 pm_wakeup_event(&bp->pdev->dev, 0);
1858 }
1859
1860 spin_unlock(&bp->lock);
1861
1862 return IRQ_HANDLED;
1863 }
1864
gem_wol_interrupt(int irq,void * dev_id)1865 static irqreturn_t gem_wol_interrupt(int irq, void *dev_id)
1866 {
1867 struct macb_queue *queue = dev_id;
1868 struct macb *bp = queue->bp;
1869 u32 status;
1870
1871 status = queue_readl(queue, ISR);
1872
1873 if (unlikely(!status))
1874 return IRQ_NONE;
1875
1876 spin_lock(&bp->lock);
1877
1878 if (status & GEM_BIT(WOL)) {
1879 queue_writel(queue, IDR, GEM_BIT(WOL));
1880 gem_writel(bp, WOL, 0);
1881 netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n",
1882 (unsigned int)(queue - bp->queues),
1883 (unsigned long)status);
1884 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1885 queue_writel(queue, ISR, GEM_BIT(WOL));
1886 pm_wakeup_event(&bp->pdev->dev, 0);
1887 }
1888
1889 spin_unlock(&bp->lock);
1890
1891 return IRQ_HANDLED;
1892 }
1893
macb_interrupt(int irq,void * dev_id)1894 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1895 {
1896 struct macb_queue *queue = dev_id;
1897 struct macb *bp = queue->bp;
1898 struct net_device *dev = bp->dev;
1899 u32 status, ctrl;
1900
1901 status = queue_readl(queue, ISR);
1902
1903 if (unlikely(!status))
1904 return IRQ_NONE;
1905
1906 spin_lock(&bp->lock);
1907
1908 while (status) {
1909 /* close possible race with dev_close */
1910 if (unlikely(!netif_running(dev))) {
1911 queue_writel(queue, IDR, -1);
1912 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1913 queue_writel(queue, ISR, -1);
1914 break;
1915 }
1916
1917 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1918 (unsigned int)(queue - bp->queues),
1919 (unsigned long)status);
1920
1921 if (status & bp->rx_intr_mask) {
1922 /* There's no point taking any more interrupts
1923 * until we have processed the buffers. The
1924 * scheduling call may fail if the poll routine
1925 * is already scheduled, so disable interrupts
1926 * now.
1927 */
1928 queue_writel(queue, IDR, bp->rx_intr_mask);
1929 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1930 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1931
1932 if (napi_schedule_prep(&queue->napi_rx)) {
1933 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1934 __napi_schedule(&queue->napi_rx);
1935 }
1936 }
1937
1938 if (status & (MACB_BIT(TCOMP) |
1939 MACB_BIT(TXUBR))) {
1940 queue_writel(queue, IDR, MACB_BIT(TCOMP));
1941 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1942 queue_writel(queue, ISR, MACB_BIT(TCOMP) |
1943 MACB_BIT(TXUBR));
1944
1945 if (status & MACB_BIT(TXUBR)) {
1946 queue->txubr_pending = true;
1947 wmb(); // ensure softirq can see update
1948 }
1949
1950 if (napi_schedule_prep(&queue->napi_tx)) {
1951 netdev_vdbg(bp->dev, "scheduling TX softirq\n");
1952 __napi_schedule(&queue->napi_tx);
1953 }
1954 }
1955
1956 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1957 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1958 schedule_work(&queue->tx_error_task);
1959
1960 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1961 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1962
1963 break;
1964 }
1965
1966 /* Link change detection isn't possible with RMII, so we'll
1967 * add that if/when we get our hands on a full-blown MII PHY.
1968 */
1969
1970 /* There is a hardware issue under heavy load where DMA can
1971 * stop, this causes endless "used buffer descriptor read"
1972 * interrupts but it can be cleared by re-enabling RX. See
1973 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1974 * section 16.7.4 for details. RXUBR is only enabled for
1975 * these two versions.
1976 */
1977 if (status & MACB_BIT(RXUBR)) {
1978 ctrl = macb_readl(bp, NCR);
1979 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1980 wmb();
1981 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1982
1983 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1984 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1985 }
1986
1987 if (status & MACB_BIT(ISR_ROVR)) {
1988 /* We missed at least one packet */
1989 spin_lock(&bp->stats_lock);
1990 if (macb_is_gem(bp))
1991 bp->hw_stats.gem.rx_overruns++;
1992 else
1993 bp->hw_stats.macb.rx_overruns++;
1994 spin_unlock(&bp->stats_lock);
1995
1996 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1997 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1998 }
1999
2000 if (status & MACB_BIT(HRESP)) {
2001 queue_work(system_bh_wq, &bp->hresp_err_bh_work);
2002 netdev_err(dev, "DMA bus error: HRESP not OK\n");
2003
2004 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2005 queue_writel(queue, ISR, MACB_BIT(HRESP));
2006 }
2007 status = queue_readl(queue, ISR);
2008 }
2009
2010 spin_unlock(&bp->lock);
2011
2012 return IRQ_HANDLED;
2013 }
2014
2015 #ifdef CONFIG_NET_POLL_CONTROLLER
2016 /* Polling receive - used by netconsole and other diagnostic tools
2017 * to allow network i/o with interrupts disabled.
2018 */
macb_poll_controller(struct net_device * dev)2019 static void macb_poll_controller(struct net_device *dev)
2020 {
2021 struct macb *bp = netdev_priv(dev);
2022 struct macb_queue *queue;
2023 unsigned long flags;
2024 unsigned int q;
2025
2026 local_irq_save(flags);
2027 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2028 macb_interrupt(dev->irq, queue);
2029 local_irq_restore(flags);
2030 }
2031 #endif
2032
macb_tx_map(struct macb * bp,struct macb_queue * queue,struct sk_buff * skb,unsigned int hdrlen)2033 static unsigned int macb_tx_map(struct macb *bp,
2034 struct macb_queue *queue,
2035 struct sk_buff *skb,
2036 unsigned int hdrlen)
2037 {
2038 dma_addr_t mapping;
2039 unsigned int len, entry, i, tx_head = queue->tx_head;
2040 struct macb_tx_skb *tx_skb = NULL;
2041 struct macb_dma_desc *desc;
2042 unsigned int offset, size, count = 0;
2043 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
2044 unsigned int eof = 1, mss_mfs = 0;
2045 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
2046
2047 /* LSO */
2048 if (skb_shinfo(skb)->gso_size != 0) {
2049 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2050 /* UDP - UFO */
2051 lso_ctrl = MACB_LSO_UFO_ENABLE;
2052 else
2053 /* TCP - TSO */
2054 lso_ctrl = MACB_LSO_TSO_ENABLE;
2055 }
2056
2057 /* First, map non-paged data */
2058 len = skb_headlen(skb);
2059
2060 /* first buffer length */
2061 size = hdrlen;
2062
2063 offset = 0;
2064 while (len) {
2065 entry = macb_tx_ring_wrap(bp, tx_head);
2066 tx_skb = &queue->tx_skb[entry];
2067
2068 mapping = dma_map_single(&bp->pdev->dev,
2069 skb->data + offset,
2070 size, DMA_TO_DEVICE);
2071 if (dma_mapping_error(&bp->pdev->dev, mapping))
2072 goto dma_error;
2073
2074 /* Save info to properly release resources */
2075 tx_skb->skb = NULL;
2076 tx_skb->mapping = mapping;
2077 tx_skb->size = size;
2078 tx_skb->mapped_as_page = false;
2079
2080 len -= size;
2081 offset += size;
2082 count++;
2083 tx_head++;
2084
2085 size = min(len, bp->max_tx_length);
2086 }
2087
2088 /* Then, map paged data from fragments */
2089 for (f = 0; f < nr_frags; f++) {
2090 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2091
2092 len = skb_frag_size(frag);
2093 offset = 0;
2094 while (len) {
2095 size = min(len, bp->max_tx_length);
2096 entry = macb_tx_ring_wrap(bp, tx_head);
2097 tx_skb = &queue->tx_skb[entry];
2098
2099 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
2100 offset, size, DMA_TO_DEVICE);
2101 if (dma_mapping_error(&bp->pdev->dev, mapping))
2102 goto dma_error;
2103
2104 /* Save info to properly release resources */
2105 tx_skb->skb = NULL;
2106 tx_skb->mapping = mapping;
2107 tx_skb->size = size;
2108 tx_skb->mapped_as_page = true;
2109
2110 len -= size;
2111 offset += size;
2112 count++;
2113 tx_head++;
2114 }
2115 }
2116
2117 /* Should never happen */
2118 if (unlikely(!tx_skb)) {
2119 netdev_err(bp->dev, "BUG! empty skb!\n");
2120 return 0;
2121 }
2122
2123 /* This is the last buffer of the frame: save socket buffer */
2124 tx_skb->skb = skb;
2125
2126 /* Update TX ring: update buffer descriptors in reverse order
2127 * to avoid race condition
2128 */
2129
2130 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
2131 * to set the end of TX queue
2132 */
2133 i = tx_head;
2134 entry = macb_tx_ring_wrap(bp, i);
2135 ctrl = MACB_BIT(TX_USED);
2136 desc = macb_tx_desc(queue, entry);
2137 desc->ctrl = ctrl;
2138
2139 if (lso_ctrl) {
2140 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
2141 /* include header and FCS in value given to h/w */
2142 mss_mfs = skb_shinfo(skb)->gso_size +
2143 skb_transport_offset(skb) +
2144 ETH_FCS_LEN;
2145 else /* TSO */ {
2146 mss_mfs = skb_shinfo(skb)->gso_size;
2147 /* TCP Sequence Number Source Select
2148 * can be set only for TSO
2149 */
2150 seq_ctrl = 0;
2151 }
2152 }
2153
2154 do {
2155 i--;
2156 entry = macb_tx_ring_wrap(bp, i);
2157 tx_skb = &queue->tx_skb[entry];
2158 desc = macb_tx_desc(queue, entry);
2159
2160 ctrl = (u32)tx_skb->size;
2161 if (eof) {
2162 ctrl |= MACB_BIT(TX_LAST);
2163 eof = 0;
2164 }
2165 if (unlikely(entry == (bp->tx_ring_size - 1)))
2166 ctrl |= MACB_BIT(TX_WRAP);
2167
2168 /* First descriptor is header descriptor */
2169 if (i == queue->tx_head) {
2170 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
2171 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
2172 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
2173 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl &&
2174 !ptp_one_step_sync(skb))
2175 ctrl |= MACB_BIT(TX_NOCRC);
2176 } else
2177 /* Only set MSS/MFS on payload descriptors
2178 * (second or later descriptor)
2179 */
2180 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
2181
2182 /* Set TX buffer descriptor */
2183 macb_set_addr(bp, desc, tx_skb->mapping);
2184 /* desc->addr must be visible to hardware before clearing
2185 * 'TX_USED' bit in desc->ctrl.
2186 */
2187 wmb();
2188 desc->ctrl = ctrl;
2189 } while (i != queue->tx_head);
2190
2191 queue->tx_head = tx_head;
2192
2193 return count;
2194
2195 dma_error:
2196 netdev_err(bp->dev, "TX DMA map failed\n");
2197
2198 for (i = queue->tx_head; i != tx_head; i++) {
2199 tx_skb = macb_tx_skb(queue, i);
2200
2201 macb_tx_unmap(bp, tx_skb, 0);
2202 }
2203
2204 return 0;
2205 }
2206
macb_features_check(struct sk_buff * skb,struct net_device * dev,netdev_features_t features)2207 static netdev_features_t macb_features_check(struct sk_buff *skb,
2208 struct net_device *dev,
2209 netdev_features_t features)
2210 {
2211 unsigned int nr_frags, f;
2212 unsigned int hdrlen;
2213
2214 /* Validate LSO compatibility */
2215
2216 /* there is only one buffer or protocol is not UDP */
2217 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
2218 return features;
2219
2220 /* length of header */
2221 hdrlen = skb_transport_offset(skb);
2222
2223 /* For UFO only:
2224 * When software supplies two or more payload buffers all payload buffers
2225 * apart from the last must be a multiple of 8 bytes in size.
2226 */
2227 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
2228 return features & ~MACB_NETIF_LSO;
2229
2230 nr_frags = skb_shinfo(skb)->nr_frags;
2231 /* No need to check last fragment */
2232 nr_frags--;
2233 for (f = 0; f < nr_frags; f++) {
2234 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2235
2236 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
2237 return features & ~MACB_NETIF_LSO;
2238 }
2239 return features;
2240 }
2241
macb_clear_csum(struct sk_buff * skb)2242 static inline int macb_clear_csum(struct sk_buff *skb)
2243 {
2244 /* no change for packets without checksum offloading */
2245 if (skb->ip_summed != CHECKSUM_PARTIAL)
2246 return 0;
2247
2248 /* make sure we can modify the header */
2249 if (unlikely(skb_cow_head(skb, 0)))
2250 return -1;
2251
2252 /* initialize checksum field
2253 * This is required - at least for Zynq, which otherwise calculates
2254 * wrong UDP header checksums for UDP packets with UDP data len <=2
2255 */
2256 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
2257 return 0;
2258 }
2259
macb_pad_and_fcs(struct sk_buff ** skb,struct net_device * ndev)2260 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
2261 {
2262 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb) ||
2263 skb_is_nonlinear(*skb);
2264 int padlen = ETH_ZLEN - (*skb)->len;
2265 int tailroom = skb_tailroom(*skb);
2266 struct sk_buff *nskb;
2267 u32 fcs;
2268
2269 if (!(ndev->features & NETIF_F_HW_CSUM) ||
2270 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
2271 skb_shinfo(*skb)->gso_size || ptp_one_step_sync(*skb))
2272 return 0;
2273
2274 if (padlen <= 0) {
2275 /* FCS could be appeded to tailroom. */
2276 if (tailroom >= ETH_FCS_LEN)
2277 goto add_fcs;
2278 /* No room for FCS, need to reallocate skb. */
2279 else
2280 padlen = ETH_FCS_LEN;
2281 } else {
2282 /* Add room for FCS. */
2283 padlen += ETH_FCS_LEN;
2284 }
2285
2286 if (cloned || tailroom < padlen) {
2287 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
2288 if (!nskb)
2289 return -ENOMEM;
2290
2291 dev_consume_skb_any(*skb);
2292 *skb = nskb;
2293 }
2294
2295 if (padlen > ETH_FCS_LEN)
2296 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
2297
2298 add_fcs:
2299 /* set FCS to packet */
2300 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
2301 fcs = ~fcs;
2302
2303 skb_put_u8(*skb, fcs & 0xff);
2304 skb_put_u8(*skb, (fcs >> 8) & 0xff);
2305 skb_put_u8(*skb, (fcs >> 16) & 0xff);
2306 skb_put_u8(*skb, (fcs >> 24) & 0xff);
2307
2308 return 0;
2309 }
2310
macb_start_xmit(struct sk_buff * skb,struct net_device * dev)2311 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
2312 {
2313 u16 queue_index = skb_get_queue_mapping(skb);
2314 struct macb *bp = netdev_priv(dev);
2315 struct macb_queue *queue = &bp->queues[queue_index];
2316 unsigned int desc_cnt, nr_frags, frag_size, f;
2317 unsigned int hdrlen;
2318 bool is_lso;
2319 netdev_tx_t ret = NETDEV_TX_OK;
2320
2321 if (macb_clear_csum(skb)) {
2322 dev_kfree_skb_any(skb);
2323 return ret;
2324 }
2325
2326 if (macb_pad_and_fcs(&skb, dev)) {
2327 dev_kfree_skb_any(skb);
2328 return ret;
2329 }
2330
2331 #ifdef CONFIG_MACB_USE_HWSTAMP
2332 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2333 (bp->hw_dma_cap & HW_DMA_CAP_PTP))
2334 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2335 #endif
2336
2337 is_lso = (skb_shinfo(skb)->gso_size != 0);
2338
2339 if (is_lso) {
2340 /* length of headers */
2341 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2342 /* only queue eth + ip headers separately for UDP */
2343 hdrlen = skb_transport_offset(skb);
2344 else
2345 hdrlen = skb_tcp_all_headers(skb);
2346 if (skb_headlen(skb) < hdrlen) {
2347 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
2348 /* if this is required, would need to copy to single buffer */
2349 return NETDEV_TX_BUSY;
2350 }
2351 } else
2352 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
2353
2354 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
2355 netdev_vdbg(bp->dev,
2356 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
2357 queue_index, skb->len, skb->head, skb->data,
2358 skb_tail_pointer(skb), skb_end_pointer(skb));
2359 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
2360 skb->data, 16, true);
2361 #endif
2362
2363 /* Count how many TX buffer descriptors are needed to send this
2364 * socket buffer: skb fragments of jumbo frames may need to be
2365 * split into many buffer descriptors.
2366 */
2367 if (is_lso && (skb_headlen(skb) > hdrlen))
2368 /* extra header descriptor if also payload in first buffer */
2369 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
2370 else
2371 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
2372 nr_frags = skb_shinfo(skb)->nr_frags;
2373 for (f = 0; f < nr_frags; f++) {
2374 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
2375 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
2376 }
2377
2378 spin_lock_bh(&queue->tx_ptr_lock);
2379
2380 /* This is a hard error, log it. */
2381 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
2382 bp->tx_ring_size) < desc_cnt) {
2383 netif_stop_subqueue(dev, queue_index);
2384 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
2385 queue->tx_head, queue->tx_tail);
2386 ret = NETDEV_TX_BUSY;
2387 goto unlock;
2388 }
2389
2390 /* Map socket buffer for DMA transfer */
2391 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
2392 dev_kfree_skb_any(skb);
2393 goto unlock;
2394 }
2395
2396 /* Make newly initialized descriptor visible to hardware */
2397 wmb();
2398 skb_tx_timestamp(skb);
2399 netdev_tx_sent_queue(netdev_get_tx_queue(bp->dev, queue_index),
2400 skb->len);
2401
2402 spin_lock_irq(&bp->lock);
2403 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
2404 spin_unlock_irq(&bp->lock);
2405
2406 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
2407 netif_stop_subqueue(dev, queue_index);
2408
2409 unlock:
2410 spin_unlock_bh(&queue->tx_ptr_lock);
2411
2412 return ret;
2413 }
2414
macb_init_rx_buffer_size(struct macb * bp,size_t size)2415 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
2416 {
2417 if (!macb_is_gem(bp)) {
2418 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
2419 } else {
2420 bp->rx_buffer_size = size;
2421
2422 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
2423 netdev_dbg(bp->dev,
2424 "RX buffer must be multiple of %d bytes, expanding\n",
2425 RX_BUFFER_MULTIPLE);
2426 bp->rx_buffer_size =
2427 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
2428 }
2429 }
2430
2431 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
2432 bp->dev->mtu, bp->rx_buffer_size);
2433 }
2434
gem_free_rx_buffers(struct macb * bp)2435 static void gem_free_rx_buffers(struct macb *bp)
2436 {
2437 struct sk_buff *skb;
2438 struct macb_dma_desc *desc;
2439 struct macb_queue *queue;
2440 dma_addr_t addr;
2441 unsigned int q;
2442 int i;
2443
2444 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2445 if (!queue->rx_skbuff)
2446 continue;
2447
2448 for (i = 0; i < bp->rx_ring_size; i++) {
2449 skb = queue->rx_skbuff[i];
2450
2451 if (!skb)
2452 continue;
2453
2454 desc = macb_rx_desc(queue, i);
2455 addr = macb_get_addr(bp, desc);
2456
2457 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
2458 DMA_FROM_DEVICE);
2459 dev_kfree_skb_any(skb);
2460 skb = NULL;
2461 }
2462
2463 kfree(queue->rx_skbuff);
2464 queue->rx_skbuff = NULL;
2465 }
2466 }
2467
macb_free_rx_buffers(struct macb * bp)2468 static void macb_free_rx_buffers(struct macb *bp)
2469 {
2470 struct macb_queue *queue = &bp->queues[0];
2471
2472 if (queue->rx_buffers) {
2473 dma_free_coherent(&bp->pdev->dev,
2474 bp->rx_ring_size * bp->rx_buffer_size,
2475 queue->rx_buffers, queue->rx_buffers_dma);
2476 queue->rx_buffers = NULL;
2477 }
2478 }
2479
macb_free_consistent(struct macb * bp)2480 static void macb_free_consistent(struct macb *bp)
2481 {
2482 struct macb_queue *queue;
2483 unsigned int q;
2484 int size;
2485
2486 if (bp->rx_ring_tieoff) {
2487 dma_free_coherent(&bp->pdev->dev, macb_dma_desc_get_size(bp),
2488 bp->rx_ring_tieoff, bp->rx_ring_tieoff_dma);
2489 bp->rx_ring_tieoff = NULL;
2490 }
2491
2492 bp->macbgem_ops.mog_free_rx_buffers(bp);
2493
2494 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2495 kfree(queue->tx_skb);
2496 queue->tx_skb = NULL;
2497 if (queue->tx_ring) {
2498 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2499 dma_free_coherent(&bp->pdev->dev, size,
2500 queue->tx_ring, queue->tx_ring_dma);
2501 queue->tx_ring = NULL;
2502 }
2503 if (queue->rx_ring) {
2504 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2505 dma_free_coherent(&bp->pdev->dev, size,
2506 queue->rx_ring, queue->rx_ring_dma);
2507 queue->rx_ring = NULL;
2508 }
2509 }
2510 }
2511
gem_alloc_rx_buffers(struct macb * bp)2512 static int gem_alloc_rx_buffers(struct macb *bp)
2513 {
2514 struct macb_queue *queue;
2515 unsigned int q;
2516 int size;
2517
2518 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2519 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2520 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2521 if (!queue->rx_skbuff)
2522 return -ENOMEM;
2523 else
2524 netdev_dbg(bp->dev,
2525 "Allocated %d RX struct sk_buff entries at %p\n",
2526 bp->rx_ring_size, queue->rx_skbuff);
2527 }
2528 return 0;
2529 }
2530
macb_alloc_rx_buffers(struct macb * bp)2531 static int macb_alloc_rx_buffers(struct macb *bp)
2532 {
2533 struct macb_queue *queue = &bp->queues[0];
2534 int size;
2535
2536 size = bp->rx_ring_size * bp->rx_buffer_size;
2537 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2538 &queue->rx_buffers_dma, GFP_KERNEL);
2539 if (!queue->rx_buffers)
2540 return -ENOMEM;
2541
2542 netdev_dbg(bp->dev,
2543 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2544 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2545 return 0;
2546 }
2547
macb_alloc_consistent(struct macb * bp)2548 static int macb_alloc_consistent(struct macb *bp)
2549 {
2550 struct macb_queue *queue;
2551 unsigned int q;
2552 int size;
2553
2554 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2555 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2556 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2557 &queue->tx_ring_dma,
2558 GFP_KERNEL);
2559 if (!queue->tx_ring)
2560 goto out_err;
2561 netdev_dbg(bp->dev,
2562 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2563 q, size, (unsigned long)queue->tx_ring_dma,
2564 queue->tx_ring);
2565
2566 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2567 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2568 if (!queue->tx_skb)
2569 goto out_err;
2570
2571 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2572 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2573 &queue->rx_ring_dma, GFP_KERNEL);
2574 if (!queue->rx_ring)
2575 goto out_err;
2576 netdev_dbg(bp->dev,
2577 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2578 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2579 }
2580 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2581 goto out_err;
2582
2583 /* Required for tie off descriptor for PM cases */
2584 if (!(bp->caps & MACB_CAPS_QUEUE_DISABLE)) {
2585 bp->rx_ring_tieoff = dma_alloc_coherent(&bp->pdev->dev,
2586 macb_dma_desc_get_size(bp),
2587 &bp->rx_ring_tieoff_dma,
2588 GFP_KERNEL);
2589 if (!bp->rx_ring_tieoff)
2590 goto out_err;
2591 }
2592
2593 return 0;
2594
2595 out_err:
2596 macb_free_consistent(bp);
2597 return -ENOMEM;
2598 }
2599
macb_init_tieoff(struct macb * bp)2600 static void macb_init_tieoff(struct macb *bp)
2601 {
2602 struct macb_dma_desc *desc = bp->rx_ring_tieoff;
2603
2604 if (bp->caps & MACB_CAPS_QUEUE_DISABLE)
2605 return;
2606 /* Setup a wrapping descriptor with no free slots
2607 * (WRAP and USED) to tie off/disable unused RX queues.
2608 */
2609 macb_set_addr(bp, desc, MACB_BIT(RX_WRAP) | MACB_BIT(RX_USED));
2610 desc->ctrl = 0;
2611 }
2612
gem_init_rings(struct macb * bp)2613 static void gem_init_rings(struct macb *bp)
2614 {
2615 struct macb_queue *queue;
2616 struct macb_dma_desc *desc = NULL;
2617 unsigned int q;
2618 int i;
2619
2620 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2621 for (i = 0; i < bp->tx_ring_size; i++) {
2622 desc = macb_tx_desc(queue, i);
2623 macb_set_addr(bp, desc, 0);
2624 desc->ctrl = MACB_BIT(TX_USED);
2625 }
2626 desc->ctrl |= MACB_BIT(TX_WRAP);
2627 queue->tx_head = 0;
2628 queue->tx_tail = 0;
2629
2630 queue->rx_tail = 0;
2631 queue->rx_prepared_head = 0;
2632
2633 gem_rx_refill(queue);
2634 }
2635
2636 macb_init_tieoff(bp);
2637 }
2638
macb_init_rings(struct macb * bp)2639 static void macb_init_rings(struct macb *bp)
2640 {
2641 int i;
2642 struct macb_dma_desc *desc = NULL;
2643
2644 macb_init_rx_ring(&bp->queues[0]);
2645
2646 for (i = 0; i < bp->tx_ring_size; i++) {
2647 desc = macb_tx_desc(&bp->queues[0], i);
2648 macb_set_addr(bp, desc, 0);
2649 desc->ctrl = MACB_BIT(TX_USED);
2650 }
2651 bp->queues[0].tx_head = 0;
2652 bp->queues[0].tx_tail = 0;
2653 desc->ctrl |= MACB_BIT(TX_WRAP);
2654
2655 macb_init_tieoff(bp);
2656 }
2657
macb_reset_hw(struct macb * bp)2658 static void macb_reset_hw(struct macb *bp)
2659 {
2660 struct macb_queue *queue;
2661 unsigned int q;
2662 u32 ctrl = macb_readl(bp, NCR);
2663
2664 /* Disable RX and TX (XXX: Should we halt the transmission
2665 * more gracefully?)
2666 */
2667 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2668
2669 /* Clear the stats registers (XXX: Update stats first?) */
2670 ctrl |= MACB_BIT(CLRSTAT);
2671
2672 macb_writel(bp, NCR, ctrl);
2673
2674 /* Clear all status flags */
2675 macb_writel(bp, TSR, -1);
2676 macb_writel(bp, RSR, -1);
2677
2678 /* Disable RX partial store and forward and reset watermark value */
2679 gem_writel(bp, PBUFRXCUT, 0);
2680
2681 /* Disable all interrupts */
2682 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2683 queue_writel(queue, IDR, -1);
2684 queue_readl(queue, ISR);
2685 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2686 queue_writel(queue, ISR, -1);
2687 }
2688 }
2689
gem_mdc_clk_div(struct macb * bp)2690 static u32 gem_mdc_clk_div(struct macb *bp)
2691 {
2692 u32 config;
2693 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2694
2695 if (pclk_hz <= 20000000)
2696 config = GEM_BF(CLK, GEM_CLK_DIV8);
2697 else if (pclk_hz <= 40000000)
2698 config = GEM_BF(CLK, GEM_CLK_DIV16);
2699 else if (pclk_hz <= 80000000)
2700 config = GEM_BF(CLK, GEM_CLK_DIV32);
2701 else if (pclk_hz <= 120000000)
2702 config = GEM_BF(CLK, GEM_CLK_DIV48);
2703 else if (pclk_hz <= 160000000)
2704 config = GEM_BF(CLK, GEM_CLK_DIV64);
2705 else if (pclk_hz <= 240000000)
2706 config = GEM_BF(CLK, GEM_CLK_DIV96);
2707 else if (pclk_hz <= 320000000)
2708 config = GEM_BF(CLK, GEM_CLK_DIV128);
2709 else
2710 config = GEM_BF(CLK, GEM_CLK_DIV224);
2711
2712 return config;
2713 }
2714
macb_mdc_clk_div(struct macb * bp)2715 static u32 macb_mdc_clk_div(struct macb *bp)
2716 {
2717 u32 config;
2718 unsigned long pclk_hz;
2719
2720 if (macb_is_gem(bp))
2721 return gem_mdc_clk_div(bp);
2722
2723 pclk_hz = clk_get_rate(bp->pclk);
2724 if (pclk_hz <= 20000000)
2725 config = MACB_BF(CLK, MACB_CLK_DIV8);
2726 else if (pclk_hz <= 40000000)
2727 config = MACB_BF(CLK, MACB_CLK_DIV16);
2728 else if (pclk_hz <= 80000000)
2729 config = MACB_BF(CLK, MACB_CLK_DIV32);
2730 else
2731 config = MACB_BF(CLK, MACB_CLK_DIV64);
2732
2733 return config;
2734 }
2735
2736 /* Get the DMA bus width field of the network configuration register that we
2737 * should program. We find the width from decoding the design configuration
2738 * register to find the maximum supported data bus width.
2739 */
macb_dbw(struct macb * bp)2740 static u32 macb_dbw(struct macb *bp)
2741 {
2742 if (!macb_is_gem(bp))
2743 return 0;
2744
2745 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2746 case 4:
2747 return GEM_BF(DBW, GEM_DBW128);
2748 case 2:
2749 return GEM_BF(DBW, GEM_DBW64);
2750 case 1:
2751 default:
2752 return GEM_BF(DBW, GEM_DBW32);
2753 }
2754 }
2755
2756 /* Configure the receive DMA engine
2757 * - use the correct receive buffer size
2758 * - set best burst length for DMA operations
2759 * (if not supported by FIFO, it will fallback to default)
2760 * - set both rx/tx packet buffers to full memory size
2761 * These are configurable parameters for GEM.
2762 */
macb_configure_dma(struct macb * bp)2763 static void macb_configure_dma(struct macb *bp)
2764 {
2765 struct macb_queue *queue;
2766 u32 buffer_size;
2767 unsigned int q;
2768 u32 dmacfg;
2769
2770 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2771 if (macb_is_gem(bp)) {
2772 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2773 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2774 if (q)
2775 queue_writel(queue, RBQS, buffer_size);
2776 else
2777 dmacfg |= GEM_BF(RXBS, buffer_size);
2778 }
2779 if (bp->dma_burst_length)
2780 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2781 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2782 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2783
2784 if (bp->native_io)
2785 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2786 else
2787 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2788
2789 if (bp->dev->features & NETIF_F_HW_CSUM)
2790 dmacfg |= GEM_BIT(TXCOEN);
2791 else
2792 dmacfg &= ~GEM_BIT(TXCOEN);
2793
2794 dmacfg &= ~GEM_BIT(ADDR64);
2795 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2796 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2797 dmacfg |= GEM_BIT(ADDR64);
2798 #endif
2799 #ifdef CONFIG_MACB_USE_HWSTAMP
2800 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2801 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2802 #endif
2803 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2804 dmacfg);
2805 gem_writel(bp, DMACFG, dmacfg);
2806 }
2807 }
2808
macb_init_hw(struct macb * bp)2809 static void macb_init_hw(struct macb *bp)
2810 {
2811 u32 config;
2812
2813 macb_reset_hw(bp);
2814 macb_set_hwaddr(bp);
2815
2816 config = macb_mdc_clk_div(bp);
2817 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2818 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2819 if (bp->caps & MACB_CAPS_JUMBO)
2820 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2821 else
2822 config |= MACB_BIT(BIG); /* Receive oversized frames */
2823 if (bp->dev->flags & IFF_PROMISC)
2824 config |= MACB_BIT(CAF); /* Copy All Frames */
2825 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2826 config |= GEM_BIT(RXCOEN);
2827 if (!(bp->dev->flags & IFF_BROADCAST))
2828 config |= MACB_BIT(NBC); /* No BroadCast */
2829 config |= macb_dbw(bp);
2830 macb_writel(bp, NCFGR, config);
2831 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2832 gem_writel(bp, JML, bp->jumbo_max_len);
2833 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2834 if (bp->caps & MACB_CAPS_JUMBO)
2835 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2836
2837 macb_configure_dma(bp);
2838
2839 /* Enable RX partial store and forward and set watermark */
2840 if (bp->rx_watermark)
2841 gem_writel(bp, PBUFRXCUT, (bp->rx_watermark | GEM_BIT(ENCUTTHRU)));
2842 }
2843
2844 /* The hash address register is 64 bits long and takes up two
2845 * locations in the memory map. The least significant bits are stored
2846 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2847 *
2848 * The unicast hash enable and the multicast hash enable bits in the
2849 * network configuration register enable the reception of hash matched
2850 * frames. The destination address is reduced to a 6 bit index into
2851 * the 64 bit hash register using the following hash function. The
2852 * hash function is an exclusive or of every sixth bit of the
2853 * destination address.
2854 *
2855 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2856 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2857 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2858 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2859 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2860 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2861 *
2862 * da[0] represents the least significant bit of the first byte
2863 * received, that is, the multicast/unicast indicator, and da[47]
2864 * represents the most significant bit of the last byte received. If
2865 * the hash index, hi[n], points to a bit that is set in the hash
2866 * register then the frame will be matched according to whether the
2867 * frame is multicast or unicast. A multicast match will be signalled
2868 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2869 * index points to a bit set in the hash register. A unicast match
2870 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2871 * and the hash index points to a bit set in the hash register. To
2872 * receive all multicast frames, the hash register should be set with
2873 * all ones and the multicast hash enable bit should be set in the
2874 * network configuration register.
2875 */
2876
hash_bit_value(int bitnr,__u8 * addr)2877 static inline int hash_bit_value(int bitnr, __u8 *addr)
2878 {
2879 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2880 return 1;
2881 return 0;
2882 }
2883
2884 /* Return the hash index value for the specified address. */
hash_get_index(__u8 * addr)2885 static int hash_get_index(__u8 *addr)
2886 {
2887 int i, j, bitval;
2888 int hash_index = 0;
2889
2890 for (j = 0; j < 6; j++) {
2891 for (i = 0, bitval = 0; i < 8; i++)
2892 bitval ^= hash_bit_value(i * 6 + j, addr);
2893
2894 hash_index |= (bitval << j);
2895 }
2896
2897 return hash_index;
2898 }
2899
2900 /* Add multicast addresses to the internal multicast-hash table. */
macb_sethashtable(struct net_device * dev)2901 static void macb_sethashtable(struct net_device *dev)
2902 {
2903 struct netdev_hw_addr *ha;
2904 unsigned long mc_filter[2];
2905 unsigned int bitnr;
2906 struct macb *bp = netdev_priv(dev);
2907
2908 mc_filter[0] = 0;
2909 mc_filter[1] = 0;
2910
2911 netdev_for_each_mc_addr(ha, dev) {
2912 bitnr = hash_get_index(ha->addr);
2913 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2914 }
2915
2916 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2917 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2918 }
2919
2920 /* Enable/Disable promiscuous and multicast modes. */
macb_set_rx_mode(struct net_device * dev)2921 static void macb_set_rx_mode(struct net_device *dev)
2922 {
2923 unsigned long cfg;
2924 struct macb *bp = netdev_priv(dev);
2925
2926 cfg = macb_readl(bp, NCFGR);
2927
2928 if (dev->flags & IFF_PROMISC) {
2929 /* Enable promiscuous mode */
2930 cfg |= MACB_BIT(CAF);
2931
2932 /* Disable RX checksum offload */
2933 if (macb_is_gem(bp))
2934 cfg &= ~GEM_BIT(RXCOEN);
2935 } else {
2936 /* Disable promiscuous mode */
2937 cfg &= ~MACB_BIT(CAF);
2938
2939 /* Enable RX checksum offload only if requested */
2940 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2941 cfg |= GEM_BIT(RXCOEN);
2942 }
2943
2944 if (dev->flags & IFF_ALLMULTI) {
2945 /* Enable all multicast mode */
2946 macb_or_gem_writel(bp, HRB, -1);
2947 macb_or_gem_writel(bp, HRT, -1);
2948 cfg |= MACB_BIT(NCFGR_MTI);
2949 } else if (!netdev_mc_empty(dev)) {
2950 /* Enable specific multicasts */
2951 macb_sethashtable(dev);
2952 cfg |= MACB_BIT(NCFGR_MTI);
2953 } else if (dev->flags & (~IFF_ALLMULTI)) {
2954 /* Disable all multicast mode */
2955 macb_or_gem_writel(bp, HRB, 0);
2956 macb_or_gem_writel(bp, HRT, 0);
2957 cfg &= ~MACB_BIT(NCFGR_MTI);
2958 }
2959
2960 macb_writel(bp, NCFGR, cfg);
2961 }
2962
macb_open(struct net_device * dev)2963 static int macb_open(struct net_device *dev)
2964 {
2965 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2966 struct macb *bp = netdev_priv(dev);
2967 struct macb_queue *queue;
2968 unsigned int q;
2969 int err;
2970
2971 netdev_dbg(bp->dev, "open\n");
2972
2973 err = pm_runtime_resume_and_get(&bp->pdev->dev);
2974 if (err < 0)
2975 return err;
2976
2977 /* RX buffers initialization */
2978 macb_init_rx_buffer_size(bp, bufsz);
2979
2980 err = macb_alloc_consistent(bp);
2981 if (err) {
2982 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2983 err);
2984 goto pm_exit;
2985 }
2986
2987 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2988 napi_enable(&queue->napi_rx);
2989 napi_enable(&queue->napi_tx);
2990 }
2991
2992 macb_init_hw(bp);
2993
2994 err = phy_power_on(bp->sgmii_phy);
2995 if (err)
2996 goto reset_hw;
2997
2998 err = macb_phylink_connect(bp);
2999 if (err)
3000 goto phy_off;
3001
3002 netif_tx_start_all_queues(dev);
3003
3004 if (bp->ptp_info)
3005 bp->ptp_info->ptp_init(dev);
3006
3007 return 0;
3008
3009 phy_off:
3010 phy_power_off(bp->sgmii_phy);
3011
3012 reset_hw:
3013 macb_reset_hw(bp);
3014 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
3015 napi_disable(&queue->napi_rx);
3016 napi_disable(&queue->napi_tx);
3017 }
3018 macb_free_consistent(bp);
3019 pm_exit:
3020 pm_runtime_put_sync(&bp->pdev->dev);
3021 return err;
3022 }
3023
macb_close(struct net_device * dev)3024 static int macb_close(struct net_device *dev)
3025 {
3026 struct macb *bp = netdev_priv(dev);
3027 struct macb_queue *queue;
3028 unsigned long flags;
3029 unsigned int q;
3030
3031 netif_tx_stop_all_queues(dev);
3032
3033 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
3034 napi_disable(&queue->napi_rx);
3035 napi_disable(&queue->napi_tx);
3036 netdev_tx_reset_queue(netdev_get_tx_queue(dev, q));
3037 }
3038
3039 phylink_stop(bp->phylink);
3040 phylink_disconnect_phy(bp->phylink);
3041
3042 phy_power_off(bp->sgmii_phy);
3043
3044 spin_lock_irqsave(&bp->lock, flags);
3045 macb_reset_hw(bp);
3046 netif_carrier_off(dev);
3047 spin_unlock_irqrestore(&bp->lock, flags);
3048
3049 macb_free_consistent(bp);
3050
3051 if (bp->ptp_info)
3052 bp->ptp_info->ptp_remove(dev);
3053
3054 pm_runtime_put(&bp->pdev->dev);
3055
3056 return 0;
3057 }
3058
macb_change_mtu(struct net_device * dev,int new_mtu)3059 static int macb_change_mtu(struct net_device *dev, int new_mtu)
3060 {
3061 if (netif_running(dev))
3062 return -EBUSY;
3063
3064 WRITE_ONCE(dev->mtu, new_mtu);
3065
3066 return 0;
3067 }
3068
macb_set_mac_addr(struct net_device * dev,void * addr)3069 static int macb_set_mac_addr(struct net_device *dev, void *addr)
3070 {
3071 int err;
3072
3073 err = eth_mac_addr(dev, addr);
3074 if (err < 0)
3075 return err;
3076
3077 macb_set_hwaddr(netdev_priv(dev));
3078 return 0;
3079 }
3080
gem_update_stats(struct macb * bp)3081 static void gem_update_stats(struct macb *bp)
3082 {
3083 struct macb_queue *queue;
3084 unsigned int i, q, idx;
3085 unsigned long *stat;
3086
3087 u64 *p = &bp->hw_stats.gem.tx_octets;
3088
3089 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
3090 u32 offset = gem_statistics[i].offset;
3091 u64 val = bp->macb_reg_readl(bp, offset);
3092
3093 bp->ethtool_stats[i] += val;
3094 *p += val;
3095
3096 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
3097 /* Add GEM_OCTTXH, GEM_OCTRXH */
3098 val = bp->macb_reg_readl(bp, offset + 4);
3099 bp->ethtool_stats[i] += ((u64)val) << 32;
3100 *(p++) += ((u64)val) << 32;
3101 }
3102 }
3103
3104 idx = GEM_STATS_LEN;
3105 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
3106 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
3107 bp->ethtool_stats[idx++] = *stat;
3108 }
3109
gem_get_stats(struct macb * bp,struct rtnl_link_stats64 * nstat)3110 static void gem_get_stats(struct macb *bp, struct rtnl_link_stats64 *nstat)
3111 {
3112 struct gem_stats *hwstat = &bp->hw_stats.gem;
3113
3114 spin_lock_irq(&bp->stats_lock);
3115 if (netif_running(bp->dev))
3116 gem_update_stats(bp);
3117
3118 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
3119 hwstat->rx_alignment_errors +
3120 hwstat->rx_resource_errors +
3121 hwstat->rx_overruns +
3122 hwstat->rx_oversize_frames +
3123 hwstat->rx_jabbers +
3124 hwstat->rx_undersized_frames +
3125 hwstat->rx_length_field_frame_errors);
3126 nstat->tx_errors = (hwstat->tx_late_collisions +
3127 hwstat->tx_excessive_collisions +
3128 hwstat->tx_underrun +
3129 hwstat->tx_carrier_sense_errors);
3130 nstat->multicast = hwstat->rx_multicast_frames;
3131 nstat->collisions = (hwstat->tx_single_collision_frames +
3132 hwstat->tx_multiple_collision_frames +
3133 hwstat->tx_excessive_collisions);
3134 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
3135 hwstat->rx_jabbers +
3136 hwstat->rx_undersized_frames +
3137 hwstat->rx_length_field_frame_errors);
3138 nstat->rx_over_errors = hwstat->rx_resource_errors;
3139 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
3140 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
3141 nstat->rx_fifo_errors = hwstat->rx_overruns;
3142 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
3143 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
3144 nstat->tx_fifo_errors = hwstat->tx_underrun;
3145 spin_unlock_irq(&bp->stats_lock);
3146 }
3147
gem_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)3148 static void gem_get_ethtool_stats(struct net_device *dev,
3149 struct ethtool_stats *stats, u64 *data)
3150 {
3151 struct macb *bp = netdev_priv(dev);
3152
3153 spin_lock_irq(&bp->stats_lock);
3154 gem_update_stats(bp);
3155 memcpy(data, &bp->ethtool_stats, sizeof(u64)
3156 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
3157 spin_unlock_irq(&bp->stats_lock);
3158 }
3159
gem_get_sset_count(struct net_device * dev,int sset)3160 static int gem_get_sset_count(struct net_device *dev, int sset)
3161 {
3162 struct macb *bp = netdev_priv(dev);
3163
3164 switch (sset) {
3165 case ETH_SS_STATS:
3166 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
3167 default:
3168 return -EOPNOTSUPP;
3169 }
3170 }
3171
gem_get_ethtool_strings(struct net_device * dev,u32 sset,u8 * p)3172 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
3173 {
3174 char stat_string[ETH_GSTRING_LEN];
3175 struct macb *bp = netdev_priv(dev);
3176 struct macb_queue *queue;
3177 unsigned int i;
3178 unsigned int q;
3179
3180 switch (sset) {
3181 case ETH_SS_STATS:
3182 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
3183 memcpy(p, gem_statistics[i].stat_string,
3184 ETH_GSTRING_LEN);
3185
3186 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
3187 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
3188 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
3189 q, queue_statistics[i].stat_string);
3190 memcpy(p, stat_string, ETH_GSTRING_LEN);
3191 }
3192 }
3193 break;
3194 }
3195 }
3196
macb_get_stats(struct net_device * dev,struct rtnl_link_stats64 * nstat)3197 static void macb_get_stats(struct net_device *dev,
3198 struct rtnl_link_stats64 *nstat)
3199 {
3200 struct macb *bp = netdev_priv(dev);
3201 struct macb_stats *hwstat = &bp->hw_stats.macb;
3202
3203 netdev_stats_to_stats64(nstat, &bp->dev->stats);
3204 if (macb_is_gem(bp)) {
3205 gem_get_stats(bp, nstat);
3206 return;
3207 }
3208
3209 /* read stats from hardware */
3210 spin_lock_irq(&bp->stats_lock);
3211 macb_update_stats(bp);
3212
3213 /* Convert HW stats into netdevice stats */
3214 nstat->rx_errors = (hwstat->rx_fcs_errors +
3215 hwstat->rx_align_errors +
3216 hwstat->rx_resource_errors +
3217 hwstat->rx_overruns +
3218 hwstat->rx_oversize_pkts +
3219 hwstat->rx_jabbers +
3220 hwstat->rx_undersize_pkts +
3221 hwstat->rx_length_mismatch);
3222 nstat->tx_errors = (hwstat->tx_late_cols +
3223 hwstat->tx_excessive_cols +
3224 hwstat->tx_underruns +
3225 hwstat->tx_carrier_errors +
3226 hwstat->sqe_test_errors);
3227 nstat->collisions = (hwstat->tx_single_cols +
3228 hwstat->tx_multiple_cols +
3229 hwstat->tx_excessive_cols);
3230 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
3231 hwstat->rx_jabbers +
3232 hwstat->rx_undersize_pkts +
3233 hwstat->rx_length_mismatch);
3234 nstat->rx_over_errors = hwstat->rx_resource_errors +
3235 hwstat->rx_overruns;
3236 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
3237 nstat->rx_frame_errors = hwstat->rx_align_errors;
3238 nstat->rx_fifo_errors = hwstat->rx_overruns;
3239 /* XXX: What does "missed" mean? */
3240 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
3241 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
3242 nstat->tx_fifo_errors = hwstat->tx_underruns;
3243 /* Don't know about heartbeat or window errors... */
3244 spin_unlock_irq(&bp->stats_lock);
3245 }
3246
macb_get_pause_stats(struct net_device * dev,struct ethtool_pause_stats * pause_stats)3247 static void macb_get_pause_stats(struct net_device *dev,
3248 struct ethtool_pause_stats *pause_stats)
3249 {
3250 struct macb *bp = netdev_priv(dev);
3251 struct macb_stats *hwstat = &bp->hw_stats.macb;
3252
3253 spin_lock_irq(&bp->stats_lock);
3254 macb_update_stats(bp);
3255 pause_stats->tx_pause_frames = hwstat->tx_pause_frames;
3256 pause_stats->rx_pause_frames = hwstat->rx_pause_frames;
3257 spin_unlock_irq(&bp->stats_lock);
3258 }
3259
gem_get_pause_stats(struct net_device * dev,struct ethtool_pause_stats * pause_stats)3260 static void gem_get_pause_stats(struct net_device *dev,
3261 struct ethtool_pause_stats *pause_stats)
3262 {
3263 struct macb *bp = netdev_priv(dev);
3264 struct gem_stats *hwstat = &bp->hw_stats.gem;
3265
3266 spin_lock_irq(&bp->stats_lock);
3267 gem_update_stats(bp);
3268 pause_stats->tx_pause_frames = hwstat->tx_pause_frames;
3269 pause_stats->rx_pause_frames = hwstat->rx_pause_frames;
3270 spin_unlock_irq(&bp->stats_lock);
3271 }
3272
macb_get_eth_mac_stats(struct net_device * dev,struct ethtool_eth_mac_stats * mac_stats)3273 static void macb_get_eth_mac_stats(struct net_device *dev,
3274 struct ethtool_eth_mac_stats *mac_stats)
3275 {
3276 struct macb *bp = netdev_priv(dev);
3277 struct macb_stats *hwstat = &bp->hw_stats.macb;
3278
3279 spin_lock_irq(&bp->stats_lock);
3280 macb_update_stats(bp);
3281 mac_stats->FramesTransmittedOK = hwstat->tx_ok;
3282 mac_stats->SingleCollisionFrames = hwstat->tx_single_cols;
3283 mac_stats->MultipleCollisionFrames = hwstat->tx_multiple_cols;
3284 mac_stats->FramesReceivedOK = hwstat->rx_ok;
3285 mac_stats->FrameCheckSequenceErrors = hwstat->rx_fcs_errors;
3286 mac_stats->AlignmentErrors = hwstat->rx_align_errors;
3287 mac_stats->FramesWithDeferredXmissions = hwstat->tx_deferred;
3288 mac_stats->LateCollisions = hwstat->tx_late_cols;
3289 mac_stats->FramesAbortedDueToXSColls = hwstat->tx_excessive_cols;
3290 mac_stats->FramesLostDueToIntMACXmitError = hwstat->tx_underruns;
3291 mac_stats->CarrierSenseErrors = hwstat->tx_carrier_errors;
3292 mac_stats->FramesLostDueToIntMACRcvError = hwstat->rx_overruns;
3293 mac_stats->InRangeLengthErrors = hwstat->rx_length_mismatch;
3294 mac_stats->FrameTooLongErrors = hwstat->rx_oversize_pkts;
3295 spin_unlock_irq(&bp->stats_lock);
3296 }
3297
gem_get_eth_mac_stats(struct net_device * dev,struct ethtool_eth_mac_stats * mac_stats)3298 static void gem_get_eth_mac_stats(struct net_device *dev,
3299 struct ethtool_eth_mac_stats *mac_stats)
3300 {
3301 struct macb *bp = netdev_priv(dev);
3302 struct gem_stats *hwstat = &bp->hw_stats.gem;
3303
3304 spin_lock_irq(&bp->stats_lock);
3305 gem_update_stats(bp);
3306 mac_stats->FramesTransmittedOK = hwstat->tx_frames;
3307 mac_stats->SingleCollisionFrames = hwstat->tx_single_collision_frames;
3308 mac_stats->MultipleCollisionFrames =
3309 hwstat->tx_multiple_collision_frames;
3310 mac_stats->FramesReceivedOK = hwstat->rx_frames;
3311 mac_stats->FrameCheckSequenceErrors =
3312 hwstat->rx_frame_check_sequence_errors;
3313 mac_stats->AlignmentErrors = hwstat->rx_alignment_errors;
3314 mac_stats->OctetsTransmittedOK = hwstat->tx_octets;
3315 mac_stats->FramesWithDeferredXmissions = hwstat->tx_deferred_frames;
3316 mac_stats->LateCollisions = hwstat->tx_late_collisions;
3317 mac_stats->FramesAbortedDueToXSColls = hwstat->tx_excessive_collisions;
3318 mac_stats->FramesLostDueToIntMACXmitError = hwstat->tx_underrun;
3319 mac_stats->CarrierSenseErrors = hwstat->tx_carrier_sense_errors;
3320 mac_stats->OctetsReceivedOK = hwstat->rx_octets;
3321 mac_stats->MulticastFramesXmittedOK = hwstat->tx_multicast_frames;
3322 mac_stats->BroadcastFramesXmittedOK = hwstat->tx_broadcast_frames;
3323 mac_stats->MulticastFramesReceivedOK = hwstat->rx_multicast_frames;
3324 mac_stats->BroadcastFramesReceivedOK = hwstat->rx_broadcast_frames;
3325 mac_stats->InRangeLengthErrors = hwstat->rx_length_field_frame_errors;
3326 mac_stats->FrameTooLongErrors = hwstat->rx_oversize_frames;
3327 spin_unlock_irq(&bp->stats_lock);
3328 }
3329
3330 /* TODO: Report SQE test errors when added to phy_stats */
macb_get_eth_phy_stats(struct net_device * dev,struct ethtool_eth_phy_stats * phy_stats)3331 static void macb_get_eth_phy_stats(struct net_device *dev,
3332 struct ethtool_eth_phy_stats *phy_stats)
3333 {
3334 struct macb *bp = netdev_priv(dev);
3335 struct macb_stats *hwstat = &bp->hw_stats.macb;
3336
3337 spin_lock_irq(&bp->stats_lock);
3338 macb_update_stats(bp);
3339 phy_stats->SymbolErrorDuringCarrier = hwstat->rx_symbol_errors;
3340 spin_unlock_irq(&bp->stats_lock);
3341 }
3342
gem_get_eth_phy_stats(struct net_device * dev,struct ethtool_eth_phy_stats * phy_stats)3343 static void gem_get_eth_phy_stats(struct net_device *dev,
3344 struct ethtool_eth_phy_stats *phy_stats)
3345 {
3346 struct macb *bp = netdev_priv(dev);
3347 struct gem_stats *hwstat = &bp->hw_stats.gem;
3348
3349 spin_lock_irq(&bp->stats_lock);
3350 gem_update_stats(bp);
3351 phy_stats->SymbolErrorDuringCarrier = hwstat->rx_symbol_errors;
3352 spin_unlock_irq(&bp->stats_lock);
3353 }
3354
macb_get_rmon_stats(struct net_device * dev,struct ethtool_rmon_stats * rmon_stats,const struct ethtool_rmon_hist_range ** ranges)3355 static void macb_get_rmon_stats(struct net_device *dev,
3356 struct ethtool_rmon_stats *rmon_stats,
3357 const struct ethtool_rmon_hist_range **ranges)
3358 {
3359 struct macb *bp = netdev_priv(dev);
3360 struct macb_stats *hwstat = &bp->hw_stats.macb;
3361
3362 spin_lock_irq(&bp->stats_lock);
3363 macb_update_stats(bp);
3364 rmon_stats->undersize_pkts = hwstat->rx_undersize_pkts;
3365 rmon_stats->oversize_pkts = hwstat->rx_oversize_pkts;
3366 rmon_stats->jabbers = hwstat->rx_jabbers;
3367 spin_unlock_irq(&bp->stats_lock);
3368 }
3369
3370 static const struct ethtool_rmon_hist_range gem_rmon_ranges[] = {
3371 { 64, 64 },
3372 { 65, 127 },
3373 { 128, 255 },
3374 { 256, 511 },
3375 { 512, 1023 },
3376 { 1024, 1518 },
3377 { 1519, 16384 },
3378 { },
3379 };
3380
gem_get_rmon_stats(struct net_device * dev,struct ethtool_rmon_stats * rmon_stats,const struct ethtool_rmon_hist_range ** ranges)3381 static void gem_get_rmon_stats(struct net_device *dev,
3382 struct ethtool_rmon_stats *rmon_stats,
3383 const struct ethtool_rmon_hist_range **ranges)
3384 {
3385 struct macb *bp = netdev_priv(dev);
3386 struct gem_stats *hwstat = &bp->hw_stats.gem;
3387
3388 spin_lock_irq(&bp->stats_lock);
3389 gem_update_stats(bp);
3390 rmon_stats->undersize_pkts = hwstat->rx_undersized_frames;
3391 rmon_stats->oversize_pkts = hwstat->rx_oversize_frames;
3392 rmon_stats->jabbers = hwstat->rx_jabbers;
3393 rmon_stats->hist[0] = hwstat->rx_64_byte_frames;
3394 rmon_stats->hist[1] = hwstat->rx_65_127_byte_frames;
3395 rmon_stats->hist[2] = hwstat->rx_128_255_byte_frames;
3396 rmon_stats->hist[3] = hwstat->rx_256_511_byte_frames;
3397 rmon_stats->hist[4] = hwstat->rx_512_1023_byte_frames;
3398 rmon_stats->hist[5] = hwstat->rx_1024_1518_byte_frames;
3399 rmon_stats->hist[6] = hwstat->rx_greater_than_1518_byte_frames;
3400 rmon_stats->hist_tx[0] = hwstat->tx_64_byte_frames;
3401 rmon_stats->hist_tx[1] = hwstat->tx_65_127_byte_frames;
3402 rmon_stats->hist_tx[2] = hwstat->tx_128_255_byte_frames;
3403 rmon_stats->hist_tx[3] = hwstat->tx_256_511_byte_frames;
3404 rmon_stats->hist_tx[4] = hwstat->tx_512_1023_byte_frames;
3405 rmon_stats->hist_tx[5] = hwstat->tx_1024_1518_byte_frames;
3406 rmon_stats->hist_tx[6] = hwstat->tx_greater_than_1518_byte_frames;
3407 spin_unlock_irq(&bp->stats_lock);
3408 *ranges = gem_rmon_ranges;
3409 }
3410
macb_get_regs_len(struct net_device * netdev)3411 static int macb_get_regs_len(struct net_device *netdev)
3412 {
3413 return MACB_GREGS_NBR * sizeof(u32);
3414 }
3415
macb_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * p)3416 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3417 void *p)
3418 {
3419 struct macb *bp = netdev_priv(dev);
3420 unsigned int tail, head;
3421 u32 *regs_buff = p;
3422
3423 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
3424 | MACB_GREGS_VERSION;
3425
3426 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
3427 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
3428
3429 regs_buff[0] = macb_readl(bp, NCR);
3430 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
3431 regs_buff[2] = macb_readl(bp, NSR);
3432 regs_buff[3] = macb_readl(bp, TSR);
3433 regs_buff[4] = macb_readl(bp, RBQP);
3434 regs_buff[5] = macb_readl(bp, TBQP);
3435 regs_buff[6] = macb_readl(bp, RSR);
3436 regs_buff[7] = macb_readl(bp, IMR);
3437
3438 regs_buff[8] = tail;
3439 regs_buff[9] = head;
3440 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
3441 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
3442
3443 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
3444 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
3445 if (macb_is_gem(bp))
3446 regs_buff[13] = gem_readl(bp, DMACFG);
3447 }
3448
macb_get_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)3449 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3450 {
3451 struct macb *bp = netdev_priv(netdev);
3452
3453 phylink_ethtool_get_wol(bp->phylink, wol);
3454 wol->supported |= (WAKE_MAGIC | WAKE_ARP);
3455
3456 /* Add macb wolopts to phy wolopts */
3457 wol->wolopts |= bp->wolopts;
3458 }
3459
macb_set_wol(struct net_device * netdev,struct ethtool_wolinfo * wol)3460 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3461 {
3462 struct macb *bp = netdev_priv(netdev);
3463 int ret;
3464
3465 /* Pass the order to phylink layer */
3466 ret = phylink_ethtool_set_wol(bp->phylink, wol);
3467 /* Don't manage WoL on MAC, if PHY set_wol() fails */
3468 if (ret && ret != -EOPNOTSUPP)
3469 return ret;
3470
3471 bp->wolopts = (wol->wolopts & WAKE_MAGIC) ? WAKE_MAGIC : 0;
3472 bp->wolopts |= (wol->wolopts & WAKE_ARP) ? WAKE_ARP : 0;
3473 bp->wol = (wol->wolopts) ? MACB_WOL_ENABLED : 0;
3474
3475 device_set_wakeup_enable(&bp->pdev->dev, bp->wol);
3476
3477 return 0;
3478 }
3479
macb_get_link_ksettings(struct net_device * netdev,struct ethtool_link_ksettings * kset)3480 static int macb_get_link_ksettings(struct net_device *netdev,
3481 struct ethtool_link_ksettings *kset)
3482 {
3483 struct macb *bp = netdev_priv(netdev);
3484
3485 return phylink_ethtool_ksettings_get(bp->phylink, kset);
3486 }
3487
macb_set_link_ksettings(struct net_device * netdev,const struct ethtool_link_ksettings * kset)3488 static int macb_set_link_ksettings(struct net_device *netdev,
3489 const struct ethtool_link_ksettings *kset)
3490 {
3491 struct macb *bp = netdev_priv(netdev);
3492
3493 return phylink_ethtool_ksettings_set(bp->phylink, kset);
3494 }
3495
macb_get_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring,struct kernel_ethtool_ringparam * kernel_ring,struct netlink_ext_ack * extack)3496 static void macb_get_ringparam(struct net_device *netdev,
3497 struct ethtool_ringparam *ring,
3498 struct kernel_ethtool_ringparam *kernel_ring,
3499 struct netlink_ext_ack *extack)
3500 {
3501 struct macb *bp = netdev_priv(netdev);
3502
3503 ring->rx_max_pending = MAX_RX_RING_SIZE;
3504 ring->tx_max_pending = MAX_TX_RING_SIZE;
3505
3506 ring->rx_pending = bp->rx_ring_size;
3507 ring->tx_pending = bp->tx_ring_size;
3508 }
3509
macb_set_ringparam(struct net_device * netdev,struct ethtool_ringparam * ring,struct kernel_ethtool_ringparam * kernel_ring,struct netlink_ext_ack * extack)3510 static int macb_set_ringparam(struct net_device *netdev,
3511 struct ethtool_ringparam *ring,
3512 struct kernel_ethtool_ringparam *kernel_ring,
3513 struct netlink_ext_ack *extack)
3514 {
3515 struct macb *bp = netdev_priv(netdev);
3516 u32 new_rx_size, new_tx_size;
3517 unsigned int reset = 0;
3518
3519 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
3520 return -EINVAL;
3521
3522 new_rx_size = clamp_t(u32, ring->rx_pending,
3523 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
3524 new_rx_size = roundup_pow_of_two(new_rx_size);
3525
3526 new_tx_size = clamp_t(u32, ring->tx_pending,
3527 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
3528 new_tx_size = roundup_pow_of_two(new_tx_size);
3529
3530 if ((new_tx_size == bp->tx_ring_size) &&
3531 (new_rx_size == bp->rx_ring_size)) {
3532 /* nothing to do */
3533 return 0;
3534 }
3535
3536 if (netif_running(bp->dev)) {
3537 reset = 1;
3538 macb_close(bp->dev);
3539 }
3540
3541 bp->rx_ring_size = new_rx_size;
3542 bp->tx_ring_size = new_tx_size;
3543
3544 if (reset)
3545 macb_open(bp->dev);
3546
3547 return 0;
3548 }
3549
3550 #ifdef CONFIG_MACB_USE_HWSTAMP
gem_get_tsu_rate(struct macb * bp)3551 static unsigned int gem_get_tsu_rate(struct macb *bp)
3552 {
3553 struct clk *tsu_clk;
3554 unsigned int tsu_rate;
3555
3556 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
3557 if (!IS_ERR(tsu_clk))
3558 tsu_rate = clk_get_rate(tsu_clk);
3559 /* try pclk instead */
3560 else if (!IS_ERR(bp->pclk)) {
3561 tsu_clk = bp->pclk;
3562 tsu_rate = clk_get_rate(tsu_clk);
3563 } else
3564 return -ENOTSUPP;
3565 return tsu_rate;
3566 }
3567
gem_get_ptp_max_adj(void)3568 static s32 gem_get_ptp_max_adj(void)
3569 {
3570 return 64000000;
3571 }
3572
gem_get_ts_info(struct net_device * dev,struct kernel_ethtool_ts_info * info)3573 static int gem_get_ts_info(struct net_device *dev,
3574 struct kernel_ethtool_ts_info *info)
3575 {
3576 struct macb *bp = netdev_priv(dev);
3577
3578 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
3579 ethtool_op_get_ts_info(dev, info);
3580 return 0;
3581 }
3582
3583 info->so_timestamping =
3584 SOF_TIMESTAMPING_TX_SOFTWARE |
3585 SOF_TIMESTAMPING_TX_HARDWARE |
3586 SOF_TIMESTAMPING_RX_HARDWARE |
3587 SOF_TIMESTAMPING_RAW_HARDWARE;
3588 info->tx_types =
3589 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
3590 (1 << HWTSTAMP_TX_OFF) |
3591 (1 << HWTSTAMP_TX_ON);
3592 info->rx_filters =
3593 (1 << HWTSTAMP_FILTER_NONE) |
3594 (1 << HWTSTAMP_FILTER_ALL);
3595
3596 if (bp->ptp_clock)
3597 info->phc_index = ptp_clock_index(bp->ptp_clock);
3598
3599 return 0;
3600 }
3601
3602 static struct macb_ptp_info gem_ptp_info = {
3603 .ptp_init = gem_ptp_init,
3604 .ptp_remove = gem_ptp_remove,
3605 .get_ptp_max_adj = gem_get_ptp_max_adj,
3606 .get_tsu_rate = gem_get_tsu_rate,
3607 .get_ts_info = gem_get_ts_info,
3608 .get_hwtst = gem_get_hwtst,
3609 .set_hwtst = gem_set_hwtst,
3610 };
3611 #endif
3612
macb_get_ts_info(struct net_device * netdev,struct kernel_ethtool_ts_info * info)3613 static int macb_get_ts_info(struct net_device *netdev,
3614 struct kernel_ethtool_ts_info *info)
3615 {
3616 struct macb *bp = netdev_priv(netdev);
3617
3618 if (bp->ptp_info)
3619 return bp->ptp_info->get_ts_info(netdev, info);
3620
3621 return ethtool_op_get_ts_info(netdev, info);
3622 }
3623
gem_enable_flow_filters(struct macb * bp,bool enable)3624 static void gem_enable_flow_filters(struct macb *bp, bool enable)
3625 {
3626 struct net_device *netdev = bp->dev;
3627 struct ethtool_rx_fs_item *item;
3628 u32 t2_scr;
3629 int num_t2_scr;
3630
3631 if (!(netdev->features & NETIF_F_NTUPLE))
3632 return;
3633
3634 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
3635
3636 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3637 struct ethtool_rx_flow_spec *fs = &item->fs;
3638 struct ethtool_tcpip4_spec *tp4sp_m;
3639
3640 if (fs->location >= num_t2_scr)
3641 continue;
3642
3643 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
3644
3645 /* enable/disable screener regs for the flow entry */
3646 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
3647
3648 /* only enable fields with no masking */
3649 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3650
3651 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
3652 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
3653 else
3654 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
3655
3656 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
3657 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
3658 else
3659 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
3660
3661 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
3662 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
3663 else
3664 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
3665
3666 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
3667 }
3668 }
3669
gem_prog_cmp_regs(struct macb * bp,struct ethtool_rx_flow_spec * fs)3670 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
3671 {
3672 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
3673 uint16_t index = fs->location;
3674 u32 w0, w1, t2_scr;
3675 bool cmp_a = false;
3676 bool cmp_b = false;
3677 bool cmp_c = false;
3678
3679 if (!macb_is_gem(bp))
3680 return;
3681
3682 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
3683 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3684
3685 /* ignore field if any masking set */
3686 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
3687 /* 1st compare reg - IP source address */
3688 w0 = 0;
3689 w1 = 0;
3690 w0 = tp4sp_v->ip4src;
3691 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3692 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3693 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
3694 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
3695 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
3696 cmp_a = true;
3697 }
3698
3699 /* ignore field if any masking set */
3700 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
3701 /* 2nd compare reg - IP destination address */
3702 w0 = 0;
3703 w1 = 0;
3704 w0 = tp4sp_v->ip4dst;
3705 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3706 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3707 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3708 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3709 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3710 cmp_b = true;
3711 }
3712
3713 /* ignore both port fields if masking set in both */
3714 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3715 /* 3rd compare reg - source port, destination port */
3716 w0 = 0;
3717 w1 = 0;
3718 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3719 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3720 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3721 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3722 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3723 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3724 } else {
3725 /* only one port definition */
3726 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3727 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3728 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3729 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3730 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3731 } else { /* dst port */
3732 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3733 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3734 }
3735 }
3736 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3737 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3738 cmp_c = true;
3739 }
3740
3741 t2_scr = 0;
3742 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3743 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3744 if (cmp_a)
3745 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3746 if (cmp_b)
3747 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3748 if (cmp_c)
3749 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3750 gem_writel_n(bp, SCRT2, index, t2_scr);
3751 }
3752
gem_add_flow_filter(struct net_device * netdev,struct ethtool_rxnfc * cmd)3753 static int gem_add_flow_filter(struct net_device *netdev,
3754 struct ethtool_rxnfc *cmd)
3755 {
3756 struct macb *bp = netdev_priv(netdev);
3757 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3758 struct ethtool_rx_fs_item *item, *newfs;
3759 unsigned long flags;
3760 int ret = -EINVAL;
3761 bool added = false;
3762
3763 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3764 if (newfs == NULL)
3765 return -ENOMEM;
3766 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3767
3768 netdev_dbg(netdev,
3769 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3770 fs->flow_type, (int)fs->ring_cookie, fs->location,
3771 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3772 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3773 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc),
3774 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst));
3775
3776 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3777
3778 /* find correct place to add in list */
3779 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3780 if (item->fs.location > newfs->fs.location) {
3781 list_add_tail(&newfs->list, &item->list);
3782 added = true;
3783 break;
3784 } else if (item->fs.location == fs->location) {
3785 netdev_err(netdev, "Rule not added: location %d not free!\n",
3786 fs->location);
3787 ret = -EBUSY;
3788 goto err;
3789 }
3790 }
3791 if (!added)
3792 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3793
3794 gem_prog_cmp_regs(bp, fs);
3795 bp->rx_fs_list.count++;
3796 /* enable filtering if NTUPLE on */
3797 gem_enable_flow_filters(bp, 1);
3798
3799 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3800 return 0;
3801
3802 err:
3803 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3804 kfree(newfs);
3805 return ret;
3806 }
3807
gem_del_flow_filter(struct net_device * netdev,struct ethtool_rxnfc * cmd)3808 static int gem_del_flow_filter(struct net_device *netdev,
3809 struct ethtool_rxnfc *cmd)
3810 {
3811 struct macb *bp = netdev_priv(netdev);
3812 struct ethtool_rx_fs_item *item;
3813 struct ethtool_rx_flow_spec *fs;
3814 unsigned long flags;
3815
3816 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3817
3818 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3819 if (item->fs.location == cmd->fs.location) {
3820 /* disable screener regs for the flow entry */
3821 fs = &(item->fs);
3822 netdev_dbg(netdev,
3823 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3824 fs->flow_type, (int)fs->ring_cookie, fs->location,
3825 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3826 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3827 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc),
3828 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst));
3829
3830 gem_writel_n(bp, SCRT2, fs->location, 0);
3831
3832 list_del(&item->list);
3833 bp->rx_fs_list.count--;
3834 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3835 kfree(item);
3836 return 0;
3837 }
3838 }
3839
3840 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3841 return -EINVAL;
3842 }
3843
gem_get_flow_entry(struct net_device * netdev,struct ethtool_rxnfc * cmd)3844 static int gem_get_flow_entry(struct net_device *netdev,
3845 struct ethtool_rxnfc *cmd)
3846 {
3847 struct macb *bp = netdev_priv(netdev);
3848 struct ethtool_rx_fs_item *item;
3849
3850 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3851 if (item->fs.location == cmd->fs.location) {
3852 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3853 return 0;
3854 }
3855 }
3856 return -EINVAL;
3857 }
3858
gem_get_all_flow_entries(struct net_device * netdev,struct ethtool_rxnfc * cmd,u32 * rule_locs)3859 static int gem_get_all_flow_entries(struct net_device *netdev,
3860 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3861 {
3862 struct macb *bp = netdev_priv(netdev);
3863 struct ethtool_rx_fs_item *item;
3864 uint32_t cnt = 0;
3865
3866 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3867 if (cnt == cmd->rule_cnt)
3868 return -EMSGSIZE;
3869 rule_locs[cnt] = item->fs.location;
3870 cnt++;
3871 }
3872 cmd->data = bp->max_tuples;
3873 cmd->rule_cnt = cnt;
3874
3875 return 0;
3876 }
3877
gem_get_rxnfc(struct net_device * netdev,struct ethtool_rxnfc * cmd,u32 * rule_locs)3878 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3879 u32 *rule_locs)
3880 {
3881 struct macb *bp = netdev_priv(netdev);
3882 int ret = 0;
3883
3884 switch (cmd->cmd) {
3885 case ETHTOOL_GRXRINGS:
3886 cmd->data = bp->num_queues;
3887 break;
3888 case ETHTOOL_GRXCLSRLCNT:
3889 cmd->rule_cnt = bp->rx_fs_list.count;
3890 break;
3891 case ETHTOOL_GRXCLSRULE:
3892 ret = gem_get_flow_entry(netdev, cmd);
3893 break;
3894 case ETHTOOL_GRXCLSRLALL:
3895 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3896 break;
3897 default:
3898 netdev_err(netdev,
3899 "Command parameter %d is not supported\n", cmd->cmd);
3900 ret = -EOPNOTSUPP;
3901 }
3902
3903 return ret;
3904 }
3905
gem_set_rxnfc(struct net_device * netdev,struct ethtool_rxnfc * cmd)3906 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3907 {
3908 struct macb *bp = netdev_priv(netdev);
3909 int ret;
3910
3911 switch (cmd->cmd) {
3912 case ETHTOOL_SRXCLSRLINS:
3913 if ((cmd->fs.location >= bp->max_tuples)
3914 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3915 ret = -EINVAL;
3916 break;
3917 }
3918 ret = gem_add_flow_filter(netdev, cmd);
3919 break;
3920 case ETHTOOL_SRXCLSRLDEL:
3921 ret = gem_del_flow_filter(netdev, cmd);
3922 break;
3923 default:
3924 netdev_err(netdev,
3925 "Command parameter %d is not supported\n", cmd->cmd);
3926 ret = -EOPNOTSUPP;
3927 }
3928
3929 return ret;
3930 }
3931
3932 static const struct ethtool_ops macb_ethtool_ops = {
3933 .get_regs_len = macb_get_regs_len,
3934 .get_regs = macb_get_regs,
3935 .get_link = ethtool_op_get_link,
3936 .get_ts_info = ethtool_op_get_ts_info,
3937 .get_pause_stats = macb_get_pause_stats,
3938 .get_eth_mac_stats = macb_get_eth_mac_stats,
3939 .get_eth_phy_stats = macb_get_eth_phy_stats,
3940 .get_rmon_stats = macb_get_rmon_stats,
3941 .get_wol = macb_get_wol,
3942 .set_wol = macb_set_wol,
3943 .get_link_ksettings = macb_get_link_ksettings,
3944 .set_link_ksettings = macb_set_link_ksettings,
3945 .get_ringparam = macb_get_ringparam,
3946 .set_ringparam = macb_set_ringparam,
3947 };
3948
3949 static const struct ethtool_ops gem_ethtool_ops = {
3950 .get_regs_len = macb_get_regs_len,
3951 .get_regs = macb_get_regs,
3952 .get_wol = macb_get_wol,
3953 .set_wol = macb_set_wol,
3954 .get_link = ethtool_op_get_link,
3955 .get_ts_info = macb_get_ts_info,
3956 .get_ethtool_stats = gem_get_ethtool_stats,
3957 .get_strings = gem_get_ethtool_strings,
3958 .get_sset_count = gem_get_sset_count,
3959 .get_pause_stats = gem_get_pause_stats,
3960 .get_eth_mac_stats = gem_get_eth_mac_stats,
3961 .get_eth_phy_stats = gem_get_eth_phy_stats,
3962 .get_rmon_stats = gem_get_rmon_stats,
3963 .get_link_ksettings = macb_get_link_ksettings,
3964 .set_link_ksettings = macb_set_link_ksettings,
3965 .get_ringparam = macb_get_ringparam,
3966 .set_ringparam = macb_set_ringparam,
3967 .get_rxnfc = gem_get_rxnfc,
3968 .set_rxnfc = gem_set_rxnfc,
3969 };
3970
macb_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)3971 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3972 {
3973 struct macb *bp = netdev_priv(dev);
3974
3975 if (!netif_running(dev))
3976 return -EINVAL;
3977
3978 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3979 }
3980
macb_hwtstamp_get(struct net_device * dev,struct kernel_hwtstamp_config * cfg)3981 static int macb_hwtstamp_get(struct net_device *dev,
3982 struct kernel_hwtstamp_config *cfg)
3983 {
3984 struct macb *bp = netdev_priv(dev);
3985
3986 if (!netif_running(dev))
3987 return -EINVAL;
3988
3989 if (!bp->ptp_info)
3990 return -EOPNOTSUPP;
3991
3992 return bp->ptp_info->get_hwtst(dev, cfg);
3993 }
3994
macb_hwtstamp_set(struct net_device * dev,struct kernel_hwtstamp_config * cfg,struct netlink_ext_ack * extack)3995 static int macb_hwtstamp_set(struct net_device *dev,
3996 struct kernel_hwtstamp_config *cfg,
3997 struct netlink_ext_ack *extack)
3998 {
3999 struct macb *bp = netdev_priv(dev);
4000
4001 if (!netif_running(dev))
4002 return -EINVAL;
4003
4004 if (!bp->ptp_info)
4005 return -EOPNOTSUPP;
4006
4007 return bp->ptp_info->set_hwtst(dev, cfg, extack);
4008 }
4009
macb_set_txcsum_feature(struct macb * bp,netdev_features_t features)4010 static inline void macb_set_txcsum_feature(struct macb *bp,
4011 netdev_features_t features)
4012 {
4013 u32 val;
4014
4015 if (!macb_is_gem(bp))
4016 return;
4017
4018 val = gem_readl(bp, DMACFG);
4019 if (features & NETIF_F_HW_CSUM)
4020 val |= GEM_BIT(TXCOEN);
4021 else
4022 val &= ~GEM_BIT(TXCOEN);
4023
4024 gem_writel(bp, DMACFG, val);
4025 }
4026
macb_set_rxcsum_feature(struct macb * bp,netdev_features_t features)4027 static inline void macb_set_rxcsum_feature(struct macb *bp,
4028 netdev_features_t features)
4029 {
4030 struct net_device *netdev = bp->dev;
4031 u32 val;
4032
4033 if (!macb_is_gem(bp))
4034 return;
4035
4036 val = gem_readl(bp, NCFGR);
4037 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
4038 val |= GEM_BIT(RXCOEN);
4039 else
4040 val &= ~GEM_BIT(RXCOEN);
4041
4042 gem_writel(bp, NCFGR, val);
4043 }
4044
macb_set_rxflow_feature(struct macb * bp,netdev_features_t features)4045 static inline void macb_set_rxflow_feature(struct macb *bp,
4046 netdev_features_t features)
4047 {
4048 if (!macb_is_gem(bp))
4049 return;
4050
4051 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
4052 }
4053
macb_set_features(struct net_device * netdev,netdev_features_t features)4054 static int macb_set_features(struct net_device *netdev,
4055 netdev_features_t features)
4056 {
4057 struct macb *bp = netdev_priv(netdev);
4058 netdev_features_t changed = features ^ netdev->features;
4059
4060 /* TX checksum offload */
4061 if (changed & NETIF_F_HW_CSUM)
4062 macb_set_txcsum_feature(bp, features);
4063
4064 /* RX checksum offload */
4065 if (changed & NETIF_F_RXCSUM)
4066 macb_set_rxcsum_feature(bp, features);
4067
4068 /* RX Flow Filters */
4069 if (changed & NETIF_F_NTUPLE)
4070 macb_set_rxflow_feature(bp, features);
4071
4072 return 0;
4073 }
4074
macb_restore_features(struct macb * bp)4075 static void macb_restore_features(struct macb *bp)
4076 {
4077 struct net_device *netdev = bp->dev;
4078 netdev_features_t features = netdev->features;
4079 struct ethtool_rx_fs_item *item;
4080
4081 /* TX checksum offload */
4082 macb_set_txcsum_feature(bp, features);
4083
4084 /* RX checksum offload */
4085 macb_set_rxcsum_feature(bp, features);
4086
4087 /* RX Flow Filters */
4088 list_for_each_entry(item, &bp->rx_fs_list.list, list)
4089 gem_prog_cmp_regs(bp, &item->fs);
4090
4091 macb_set_rxflow_feature(bp, features);
4092 }
4093
4094 static const struct net_device_ops macb_netdev_ops = {
4095 .ndo_open = macb_open,
4096 .ndo_stop = macb_close,
4097 .ndo_start_xmit = macb_start_xmit,
4098 .ndo_set_rx_mode = macb_set_rx_mode,
4099 .ndo_get_stats64 = macb_get_stats,
4100 .ndo_eth_ioctl = macb_ioctl,
4101 .ndo_validate_addr = eth_validate_addr,
4102 .ndo_change_mtu = macb_change_mtu,
4103 .ndo_set_mac_address = macb_set_mac_addr,
4104 #ifdef CONFIG_NET_POLL_CONTROLLER
4105 .ndo_poll_controller = macb_poll_controller,
4106 #endif
4107 .ndo_set_features = macb_set_features,
4108 .ndo_features_check = macb_features_check,
4109 .ndo_hwtstamp_set = macb_hwtstamp_set,
4110 .ndo_hwtstamp_get = macb_hwtstamp_get,
4111 };
4112
4113 /* Configure peripheral capabilities according to device tree
4114 * and integration options used
4115 */
macb_configure_caps(struct macb * bp,const struct macb_config * dt_conf)4116 static void macb_configure_caps(struct macb *bp,
4117 const struct macb_config *dt_conf)
4118 {
4119 u32 dcfg;
4120
4121 if (dt_conf)
4122 bp->caps = dt_conf->caps;
4123
4124 if (hw_is_gem(bp->regs, bp->native_io)) {
4125 bp->caps |= MACB_CAPS_MACB_IS_GEM;
4126
4127 dcfg = gem_readl(bp, DCFG1);
4128 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
4129 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
4130 if (GEM_BFEXT(NO_PCS, dcfg) == 0)
4131 bp->caps |= MACB_CAPS_PCS;
4132 dcfg = gem_readl(bp, DCFG12);
4133 if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1)
4134 bp->caps |= MACB_CAPS_HIGH_SPEED;
4135 dcfg = gem_readl(bp, DCFG2);
4136 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
4137 bp->caps |= MACB_CAPS_FIFO_MODE;
4138 if (gem_has_ptp(bp)) {
4139 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
4140 dev_err(&bp->pdev->dev,
4141 "GEM doesn't support hardware ptp.\n");
4142 else {
4143 #ifdef CONFIG_MACB_USE_HWSTAMP
4144 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
4145 bp->ptp_info = &gem_ptp_info;
4146 #endif
4147 }
4148 }
4149 }
4150
4151 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
4152 }
4153
macb_probe_queues(void __iomem * mem,bool native_io,unsigned int * queue_mask,unsigned int * num_queues)4154 static void macb_probe_queues(void __iomem *mem,
4155 bool native_io,
4156 unsigned int *queue_mask,
4157 unsigned int *num_queues)
4158 {
4159 *queue_mask = 0x1;
4160 *num_queues = 1;
4161
4162 /* is it macb or gem ?
4163 *
4164 * We need to read directly from the hardware here because
4165 * we are early in the probe process and don't have the
4166 * MACB_CAPS_MACB_IS_GEM flag positioned
4167 */
4168 if (!hw_is_gem(mem, native_io))
4169 return;
4170
4171 /* bit 0 is never set but queue 0 always exists */
4172 *queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xff;
4173 *num_queues = hweight32(*queue_mask);
4174 }
4175
macb_clks_disable(struct clk * pclk,struct clk * hclk,struct clk * tx_clk,struct clk * rx_clk,struct clk * tsu_clk)4176 static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk,
4177 struct clk *rx_clk, struct clk *tsu_clk)
4178 {
4179 struct clk_bulk_data clks[] = {
4180 { .clk = tsu_clk, },
4181 { .clk = rx_clk, },
4182 { .clk = pclk, },
4183 { .clk = hclk, },
4184 { .clk = tx_clk },
4185 };
4186
4187 clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks);
4188 }
4189
macb_clk_init(struct platform_device * pdev,struct clk ** pclk,struct clk ** hclk,struct clk ** tx_clk,struct clk ** rx_clk,struct clk ** tsu_clk)4190 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
4191 struct clk **hclk, struct clk **tx_clk,
4192 struct clk **rx_clk, struct clk **tsu_clk)
4193 {
4194 struct macb_platform_data *pdata;
4195 int err;
4196
4197 pdata = dev_get_platdata(&pdev->dev);
4198 if (pdata) {
4199 *pclk = pdata->pclk;
4200 *hclk = pdata->hclk;
4201 } else {
4202 *pclk = devm_clk_get(&pdev->dev, "pclk");
4203 *hclk = devm_clk_get(&pdev->dev, "hclk");
4204 }
4205
4206 if (IS_ERR_OR_NULL(*pclk))
4207 return dev_err_probe(&pdev->dev,
4208 IS_ERR(*pclk) ? PTR_ERR(*pclk) : -ENODEV,
4209 "failed to get pclk\n");
4210
4211 if (IS_ERR_OR_NULL(*hclk))
4212 return dev_err_probe(&pdev->dev,
4213 IS_ERR(*hclk) ? PTR_ERR(*hclk) : -ENODEV,
4214 "failed to get hclk\n");
4215
4216 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
4217 if (IS_ERR(*tx_clk))
4218 return PTR_ERR(*tx_clk);
4219
4220 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
4221 if (IS_ERR(*rx_clk))
4222 return PTR_ERR(*rx_clk);
4223
4224 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
4225 if (IS_ERR(*tsu_clk))
4226 return PTR_ERR(*tsu_clk);
4227
4228 err = clk_prepare_enable(*pclk);
4229 if (err) {
4230 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4231 return err;
4232 }
4233
4234 err = clk_prepare_enable(*hclk);
4235 if (err) {
4236 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
4237 goto err_disable_pclk;
4238 }
4239
4240 err = clk_prepare_enable(*tx_clk);
4241 if (err) {
4242 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
4243 goto err_disable_hclk;
4244 }
4245
4246 err = clk_prepare_enable(*rx_clk);
4247 if (err) {
4248 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
4249 goto err_disable_txclk;
4250 }
4251
4252 err = clk_prepare_enable(*tsu_clk);
4253 if (err) {
4254 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
4255 goto err_disable_rxclk;
4256 }
4257
4258 return 0;
4259
4260 err_disable_rxclk:
4261 clk_disable_unprepare(*rx_clk);
4262
4263 err_disable_txclk:
4264 clk_disable_unprepare(*tx_clk);
4265
4266 err_disable_hclk:
4267 clk_disable_unprepare(*hclk);
4268
4269 err_disable_pclk:
4270 clk_disable_unprepare(*pclk);
4271
4272 return err;
4273 }
4274
macb_init(struct platform_device * pdev)4275 static int macb_init(struct platform_device *pdev)
4276 {
4277 struct net_device *dev = platform_get_drvdata(pdev);
4278 unsigned int hw_q, q;
4279 struct macb *bp = netdev_priv(dev);
4280 struct macb_queue *queue;
4281 int err;
4282 u32 val, reg;
4283
4284 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
4285 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
4286
4287 /* set the queue register mapping once for all: queue0 has a special
4288 * register mapping but we don't want to test the queue index then
4289 * compute the corresponding register offset at run time.
4290 */
4291 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
4292 if (!(bp->queue_mask & (1 << hw_q)))
4293 continue;
4294
4295 queue = &bp->queues[q];
4296 queue->bp = bp;
4297 spin_lock_init(&queue->tx_ptr_lock);
4298 netif_napi_add(dev, &queue->napi_rx, macb_rx_poll);
4299 netif_napi_add(dev, &queue->napi_tx, macb_tx_poll);
4300 if (hw_q) {
4301 queue->ISR = GEM_ISR(hw_q - 1);
4302 queue->IER = GEM_IER(hw_q - 1);
4303 queue->IDR = GEM_IDR(hw_q - 1);
4304 queue->IMR = GEM_IMR(hw_q - 1);
4305 queue->TBQP = GEM_TBQP(hw_q - 1);
4306 queue->RBQP = GEM_RBQP(hw_q - 1);
4307 queue->RBQS = GEM_RBQS(hw_q - 1);
4308 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4309 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
4310 queue->TBQPH = GEM_TBQPH(hw_q - 1);
4311 queue->RBQPH = GEM_RBQPH(hw_q - 1);
4312 }
4313 #endif
4314 } else {
4315 /* queue0 uses legacy registers */
4316 queue->ISR = MACB_ISR;
4317 queue->IER = MACB_IER;
4318 queue->IDR = MACB_IDR;
4319 queue->IMR = MACB_IMR;
4320 queue->TBQP = MACB_TBQP;
4321 queue->RBQP = MACB_RBQP;
4322 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4323 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
4324 queue->TBQPH = MACB_TBQPH;
4325 queue->RBQPH = MACB_RBQPH;
4326 }
4327 #endif
4328 }
4329
4330 /* get irq: here we use the linux queue index, not the hardware
4331 * queue index. the queue irq definitions in the device tree
4332 * must remove the optional gaps that could exist in the
4333 * hardware queue mask.
4334 */
4335 queue->irq = platform_get_irq(pdev, q);
4336 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
4337 IRQF_SHARED, dev->name, queue);
4338 if (err) {
4339 dev_err(&pdev->dev,
4340 "Unable to request IRQ %d (error %d)\n",
4341 queue->irq, err);
4342 return err;
4343 }
4344
4345 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
4346 q++;
4347 }
4348
4349 dev->netdev_ops = &macb_netdev_ops;
4350
4351 /* setup appropriated routines according to adapter type */
4352 if (macb_is_gem(bp)) {
4353 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
4354 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
4355 bp->macbgem_ops.mog_init_rings = gem_init_rings;
4356 bp->macbgem_ops.mog_rx = gem_rx;
4357 dev->ethtool_ops = &gem_ethtool_ops;
4358 } else {
4359 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
4360 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
4361 bp->macbgem_ops.mog_init_rings = macb_init_rings;
4362 bp->macbgem_ops.mog_rx = macb_rx;
4363 dev->ethtool_ops = &macb_ethtool_ops;
4364 }
4365
4366 netdev_sw_irq_coalesce_default_on(dev);
4367
4368 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
4369
4370 /* Set features */
4371 dev->hw_features = NETIF_F_SG;
4372
4373 /* Check LSO capability */
4374 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
4375 dev->hw_features |= MACB_NETIF_LSO;
4376
4377 /* Checksum offload is only available on gem with packet buffer */
4378 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
4379 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
4380 if (bp->caps & MACB_CAPS_SG_DISABLED)
4381 dev->hw_features &= ~NETIF_F_SG;
4382 dev->features = dev->hw_features;
4383
4384 /* Check RX Flow Filters support.
4385 * Max Rx flows set by availability of screeners & compare regs:
4386 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
4387 */
4388 reg = gem_readl(bp, DCFG8);
4389 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
4390 GEM_BFEXT(T2SCR, reg));
4391 INIT_LIST_HEAD(&bp->rx_fs_list.list);
4392 if (bp->max_tuples > 0) {
4393 /* also needs one ethtype match to check IPv4 */
4394 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
4395 /* program this reg now */
4396 reg = 0;
4397 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
4398 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
4399 /* Filtering is supported in hw but don't enable it in kernel now */
4400 dev->hw_features |= NETIF_F_NTUPLE;
4401 /* init Rx flow definitions */
4402 bp->rx_fs_list.count = 0;
4403 spin_lock_init(&bp->rx_fs_lock);
4404 } else
4405 bp->max_tuples = 0;
4406 }
4407
4408 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
4409 val = 0;
4410 if (phy_interface_mode_is_rgmii(bp->phy_interface))
4411 val = bp->usrio->rgmii;
4412 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
4413 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
4414 val = bp->usrio->rmii;
4415 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
4416 val = bp->usrio->mii;
4417
4418 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
4419 val |= bp->usrio->refclk;
4420
4421 macb_or_gem_writel(bp, USRIO, val);
4422 }
4423
4424 /* Set MII management clock divider */
4425 val = macb_mdc_clk_div(bp);
4426 val |= macb_dbw(bp);
4427 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
4428 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
4429 macb_writel(bp, NCFGR, val);
4430
4431 return 0;
4432 }
4433
4434 static const struct macb_usrio_config macb_default_usrio = {
4435 .mii = MACB_BIT(MII),
4436 .rmii = MACB_BIT(RMII),
4437 .rgmii = GEM_BIT(RGMII),
4438 .refclk = MACB_BIT(CLKEN),
4439 };
4440
4441 #if defined(CONFIG_OF)
4442 /* 1518 rounded up */
4443 #define AT91ETHER_MAX_RBUFF_SZ 0x600
4444 /* max number of receive buffers */
4445 #define AT91ETHER_MAX_RX_DESCR 9
4446
4447 static struct sifive_fu540_macb_mgmt *mgmt;
4448
at91ether_alloc_coherent(struct macb * lp)4449 static int at91ether_alloc_coherent(struct macb *lp)
4450 {
4451 struct macb_queue *q = &lp->queues[0];
4452
4453 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
4454 (AT91ETHER_MAX_RX_DESCR *
4455 macb_dma_desc_get_size(lp)),
4456 &q->rx_ring_dma, GFP_KERNEL);
4457 if (!q->rx_ring)
4458 return -ENOMEM;
4459
4460 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
4461 AT91ETHER_MAX_RX_DESCR *
4462 AT91ETHER_MAX_RBUFF_SZ,
4463 &q->rx_buffers_dma, GFP_KERNEL);
4464 if (!q->rx_buffers) {
4465 dma_free_coherent(&lp->pdev->dev,
4466 AT91ETHER_MAX_RX_DESCR *
4467 macb_dma_desc_get_size(lp),
4468 q->rx_ring, q->rx_ring_dma);
4469 q->rx_ring = NULL;
4470 return -ENOMEM;
4471 }
4472
4473 return 0;
4474 }
4475
at91ether_free_coherent(struct macb * lp)4476 static void at91ether_free_coherent(struct macb *lp)
4477 {
4478 struct macb_queue *q = &lp->queues[0];
4479
4480 if (q->rx_ring) {
4481 dma_free_coherent(&lp->pdev->dev,
4482 AT91ETHER_MAX_RX_DESCR *
4483 macb_dma_desc_get_size(lp),
4484 q->rx_ring, q->rx_ring_dma);
4485 q->rx_ring = NULL;
4486 }
4487
4488 if (q->rx_buffers) {
4489 dma_free_coherent(&lp->pdev->dev,
4490 AT91ETHER_MAX_RX_DESCR *
4491 AT91ETHER_MAX_RBUFF_SZ,
4492 q->rx_buffers, q->rx_buffers_dma);
4493 q->rx_buffers = NULL;
4494 }
4495 }
4496
4497 /* Initialize and start the Receiver and Transmit subsystems */
at91ether_start(struct macb * lp)4498 static int at91ether_start(struct macb *lp)
4499 {
4500 struct macb_queue *q = &lp->queues[0];
4501 struct macb_dma_desc *desc;
4502 dma_addr_t addr;
4503 u32 ctl;
4504 int i, ret;
4505
4506 ret = at91ether_alloc_coherent(lp);
4507 if (ret)
4508 return ret;
4509
4510 addr = q->rx_buffers_dma;
4511 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
4512 desc = macb_rx_desc(q, i);
4513 macb_set_addr(lp, desc, addr);
4514 desc->ctrl = 0;
4515 addr += AT91ETHER_MAX_RBUFF_SZ;
4516 }
4517
4518 /* Set the Wrap bit on the last descriptor */
4519 desc->addr |= MACB_BIT(RX_WRAP);
4520
4521 /* Reset buffer index */
4522 q->rx_tail = 0;
4523
4524 /* Program address of descriptor list in Rx Buffer Queue register */
4525 macb_writel(lp, RBQP, q->rx_ring_dma);
4526
4527 /* Enable Receive and Transmit */
4528 ctl = macb_readl(lp, NCR);
4529 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
4530
4531 /* Enable MAC interrupts */
4532 macb_writel(lp, IER, MACB_BIT(RCOMP) |
4533 MACB_BIT(RXUBR) |
4534 MACB_BIT(ISR_TUND) |
4535 MACB_BIT(ISR_RLE) |
4536 MACB_BIT(TCOMP) |
4537 MACB_BIT(ISR_ROVR) |
4538 MACB_BIT(HRESP));
4539
4540 return 0;
4541 }
4542
at91ether_stop(struct macb * lp)4543 static void at91ether_stop(struct macb *lp)
4544 {
4545 u32 ctl;
4546
4547 /* Disable MAC interrupts */
4548 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
4549 MACB_BIT(RXUBR) |
4550 MACB_BIT(ISR_TUND) |
4551 MACB_BIT(ISR_RLE) |
4552 MACB_BIT(TCOMP) |
4553 MACB_BIT(ISR_ROVR) |
4554 MACB_BIT(HRESP));
4555
4556 /* Disable Receiver and Transmitter */
4557 ctl = macb_readl(lp, NCR);
4558 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
4559
4560 /* Free resources. */
4561 at91ether_free_coherent(lp);
4562 }
4563
4564 /* Open the ethernet interface */
at91ether_open(struct net_device * dev)4565 static int at91ether_open(struct net_device *dev)
4566 {
4567 struct macb *lp = netdev_priv(dev);
4568 u32 ctl;
4569 int ret;
4570
4571 ret = pm_runtime_resume_and_get(&lp->pdev->dev);
4572 if (ret < 0)
4573 return ret;
4574
4575 /* Clear internal statistics */
4576 ctl = macb_readl(lp, NCR);
4577 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
4578
4579 macb_set_hwaddr(lp);
4580
4581 ret = at91ether_start(lp);
4582 if (ret)
4583 goto pm_exit;
4584
4585 ret = macb_phylink_connect(lp);
4586 if (ret)
4587 goto stop;
4588
4589 netif_start_queue(dev);
4590
4591 return 0;
4592
4593 stop:
4594 at91ether_stop(lp);
4595 pm_exit:
4596 pm_runtime_put_sync(&lp->pdev->dev);
4597 return ret;
4598 }
4599
4600 /* Close the interface */
at91ether_close(struct net_device * dev)4601 static int at91ether_close(struct net_device *dev)
4602 {
4603 struct macb *lp = netdev_priv(dev);
4604
4605 netif_stop_queue(dev);
4606
4607 phylink_stop(lp->phylink);
4608 phylink_disconnect_phy(lp->phylink);
4609
4610 at91ether_stop(lp);
4611
4612 return pm_runtime_put(&lp->pdev->dev);
4613 }
4614
4615 /* Transmit packet */
at91ether_start_xmit(struct sk_buff * skb,struct net_device * dev)4616 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
4617 struct net_device *dev)
4618 {
4619 struct macb *lp = netdev_priv(dev);
4620
4621 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
4622 int desc = 0;
4623
4624 netif_stop_queue(dev);
4625
4626 /* Store packet information (to free when Tx completed) */
4627 lp->rm9200_txq[desc].skb = skb;
4628 lp->rm9200_txq[desc].size = skb->len;
4629 lp->rm9200_txq[desc].mapping = dma_map_single(&lp->pdev->dev, skb->data,
4630 skb->len, DMA_TO_DEVICE);
4631 if (dma_mapping_error(&lp->pdev->dev, lp->rm9200_txq[desc].mapping)) {
4632 dev_kfree_skb_any(skb);
4633 dev->stats.tx_dropped++;
4634 netdev_err(dev, "%s: DMA mapping error\n", __func__);
4635 return NETDEV_TX_OK;
4636 }
4637
4638 /* Set address of the data in the Transmit Address register */
4639 macb_writel(lp, TAR, lp->rm9200_txq[desc].mapping);
4640 /* Set length of the packet in the Transmit Control register */
4641 macb_writel(lp, TCR, skb->len);
4642
4643 } else {
4644 netdev_err(dev, "%s called, but device is busy!\n", __func__);
4645 return NETDEV_TX_BUSY;
4646 }
4647
4648 return NETDEV_TX_OK;
4649 }
4650
4651 /* Extract received frame from buffer descriptors and sent to upper layers.
4652 * (Called from interrupt context)
4653 */
at91ether_rx(struct net_device * dev)4654 static void at91ether_rx(struct net_device *dev)
4655 {
4656 struct macb *lp = netdev_priv(dev);
4657 struct macb_queue *q = &lp->queues[0];
4658 struct macb_dma_desc *desc;
4659 unsigned char *p_recv;
4660 struct sk_buff *skb;
4661 unsigned int pktlen;
4662
4663 desc = macb_rx_desc(q, q->rx_tail);
4664 while (desc->addr & MACB_BIT(RX_USED)) {
4665 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
4666 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
4667 skb = netdev_alloc_skb(dev, pktlen + 2);
4668 if (skb) {
4669 skb_reserve(skb, 2);
4670 skb_put_data(skb, p_recv, pktlen);
4671
4672 skb->protocol = eth_type_trans(skb, dev);
4673 dev->stats.rx_packets++;
4674 dev->stats.rx_bytes += pktlen;
4675 netif_rx(skb);
4676 } else {
4677 dev->stats.rx_dropped++;
4678 }
4679
4680 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
4681 dev->stats.multicast++;
4682
4683 /* reset ownership bit */
4684 desc->addr &= ~MACB_BIT(RX_USED);
4685
4686 /* wrap after last buffer */
4687 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
4688 q->rx_tail = 0;
4689 else
4690 q->rx_tail++;
4691
4692 desc = macb_rx_desc(q, q->rx_tail);
4693 }
4694 }
4695
4696 /* MAC interrupt handler */
at91ether_interrupt(int irq,void * dev_id)4697 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
4698 {
4699 struct net_device *dev = dev_id;
4700 struct macb *lp = netdev_priv(dev);
4701 u32 intstatus, ctl;
4702 unsigned int desc;
4703
4704 /* MAC Interrupt Status register indicates what interrupts are pending.
4705 * It is automatically cleared once read.
4706 */
4707 intstatus = macb_readl(lp, ISR);
4708
4709 /* Receive complete */
4710 if (intstatus & MACB_BIT(RCOMP))
4711 at91ether_rx(dev);
4712
4713 /* Transmit complete */
4714 if (intstatus & MACB_BIT(TCOMP)) {
4715 /* The TCOM bit is set even if the transmission failed */
4716 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
4717 dev->stats.tx_errors++;
4718
4719 desc = 0;
4720 if (lp->rm9200_txq[desc].skb) {
4721 dev_consume_skb_irq(lp->rm9200_txq[desc].skb);
4722 lp->rm9200_txq[desc].skb = NULL;
4723 dma_unmap_single(&lp->pdev->dev, lp->rm9200_txq[desc].mapping,
4724 lp->rm9200_txq[desc].size, DMA_TO_DEVICE);
4725 dev->stats.tx_packets++;
4726 dev->stats.tx_bytes += lp->rm9200_txq[desc].size;
4727 }
4728 netif_wake_queue(dev);
4729 }
4730
4731 /* Work-around for EMAC Errata section 41.3.1 */
4732 if (intstatus & MACB_BIT(RXUBR)) {
4733 ctl = macb_readl(lp, NCR);
4734 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
4735 wmb();
4736 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
4737 }
4738
4739 if (intstatus & MACB_BIT(ISR_ROVR))
4740 netdev_err(dev, "ROVR error\n");
4741
4742 return IRQ_HANDLED;
4743 }
4744
4745 #ifdef CONFIG_NET_POLL_CONTROLLER
at91ether_poll_controller(struct net_device * dev)4746 static void at91ether_poll_controller(struct net_device *dev)
4747 {
4748 unsigned long flags;
4749
4750 local_irq_save(flags);
4751 at91ether_interrupt(dev->irq, dev);
4752 local_irq_restore(flags);
4753 }
4754 #endif
4755
4756 static const struct net_device_ops at91ether_netdev_ops = {
4757 .ndo_open = at91ether_open,
4758 .ndo_stop = at91ether_close,
4759 .ndo_start_xmit = at91ether_start_xmit,
4760 .ndo_get_stats64 = macb_get_stats,
4761 .ndo_set_rx_mode = macb_set_rx_mode,
4762 .ndo_set_mac_address = eth_mac_addr,
4763 .ndo_eth_ioctl = macb_ioctl,
4764 .ndo_validate_addr = eth_validate_addr,
4765 #ifdef CONFIG_NET_POLL_CONTROLLER
4766 .ndo_poll_controller = at91ether_poll_controller,
4767 #endif
4768 .ndo_hwtstamp_set = macb_hwtstamp_set,
4769 .ndo_hwtstamp_get = macb_hwtstamp_get,
4770 };
4771
at91ether_clk_init(struct platform_device * pdev,struct clk ** pclk,struct clk ** hclk,struct clk ** tx_clk,struct clk ** rx_clk,struct clk ** tsu_clk)4772 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
4773 struct clk **hclk, struct clk **tx_clk,
4774 struct clk **rx_clk, struct clk **tsu_clk)
4775 {
4776 int err;
4777
4778 *hclk = NULL;
4779 *tx_clk = NULL;
4780 *rx_clk = NULL;
4781 *tsu_clk = NULL;
4782
4783 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
4784 if (IS_ERR(*pclk))
4785 return PTR_ERR(*pclk);
4786
4787 err = clk_prepare_enable(*pclk);
4788 if (err) {
4789 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4790 return err;
4791 }
4792
4793 return 0;
4794 }
4795
at91ether_init(struct platform_device * pdev)4796 static int at91ether_init(struct platform_device *pdev)
4797 {
4798 struct net_device *dev = platform_get_drvdata(pdev);
4799 struct macb *bp = netdev_priv(dev);
4800 int err;
4801
4802 bp->queues[0].bp = bp;
4803
4804 dev->netdev_ops = &at91ether_netdev_ops;
4805 dev->ethtool_ops = &macb_ethtool_ops;
4806
4807 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4808 0, dev->name, dev);
4809 if (err)
4810 return err;
4811
4812 macb_writel(bp, NCR, 0);
4813
4814 macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
4815
4816 return 0;
4817 }
4818
fu540_macb_tx_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)4819 static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4820 unsigned long parent_rate)
4821 {
4822 return mgmt->rate;
4823 }
4824
fu540_macb_tx_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)4825 static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4826 unsigned long *parent_rate)
4827 {
4828 if (WARN_ON(rate < 2500000))
4829 return 2500000;
4830 else if (rate == 2500000)
4831 return 2500000;
4832 else if (WARN_ON(rate < 13750000))
4833 return 2500000;
4834 else if (WARN_ON(rate < 25000000))
4835 return 25000000;
4836 else if (rate == 25000000)
4837 return 25000000;
4838 else if (WARN_ON(rate < 75000000))
4839 return 25000000;
4840 else if (WARN_ON(rate < 125000000))
4841 return 125000000;
4842 else if (rate == 125000000)
4843 return 125000000;
4844
4845 WARN_ON(rate > 125000000);
4846
4847 return 125000000;
4848 }
4849
fu540_macb_tx_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)4850 static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4851 unsigned long parent_rate)
4852 {
4853 rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4854 if (rate != 125000000)
4855 iowrite32(1, mgmt->reg);
4856 else
4857 iowrite32(0, mgmt->reg);
4858 mgmt->rate = rate;
4859
4860 return 0;
4861 }
4862
4863 static const struct clk_ops fu540_c000_ops = {
4864 .recalc_rate = fu540_macb_tx_recalc_rate,
4865 .round_rate = fu540_macb_tx_round_rate,
4866 .set_rate = fu540_macb_tx_set_rate,
4867 };
4868
fu540_c000_clk_init(struct platform_device * pdev,struct clk ** pclk,struct clk ** hclk,struct clk ** tx_clk,struct clk ** rx_clk,struct clk ** tsu_clk)4869 static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4870 struct clk **hclk, struct clk **tx_clk,
4871 struct clk **rx_clk, struct clk **tsu_clk)
4872 {
4873 struct clk_init_data init;
4874 int err = 0;
4875
4876 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4877 if (err)
4878 return err;
4879
4880 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4881 if (!mgmt) {
4882 err = -ENOMEM;
4883 goto err_disable_clks;
4884 }
4885
4886 init.name = "sifive-gemgxl-mgmt";
4887 init.ops = &fu540_c000_ops;
4888 init.flags = 0;
4889 init.num_parents = 0;
4890
4891 mgmt->rate = 0;
4892 mgmt->hw.init = &init;
4893
4894 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
4895 if (IS_ERR(*tx_clk)) {
4896 err = PTR_ERR(*tx_clk);
4897 goto err_disable_clks;
4898 }
4899
4900 err = clk_prepare_enable(*tx_clk);
4901 if (err) {
4902 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4903 *tx_clk = NULL;
4904 goto err_disable_clks;
4905 } else {
4906 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4907 }
4908
4909 return 0;
4910
4911 err_disable_clks:
4912 macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk);
4913
4914 return err;
4915 }
4916
fu540_c000_init(struct platform_device * pdev)4917 static int fu540_c000_init(struct platform_device *pdev)
4918 {
4919 mgmt->reg = devm_platform_ioremap_resource(pdev, 1);
4920 if (IS_ERR(mgmt->reg))
4921 return PTR_ERR(mgmt->reg);
4922
4923 return macb_init(pdev);
4924 }
4925
init_reset_optional(struct platform_device * pdev)4926 static int init_reset_optional(struct platform_device *pdev)
4927 {
4928 struct net_device *dev = platform_get_drvdata(pdev);
4929 struct macb *bp = netdev_priv(dev);
4930 int ret;
4931
4932 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
4933 /* Ensure PHY device used in SGMII mode is ready */
4934 bp->sgmii_phy = devm_phy_optional_get(&pdev->dev, NULL);
4935
4936 if (IS_ERR(bp->sgmii_phy))
4937 return dev_err_probe(&pdev->dev, PTR_ERR(bp->sgmii_phy),
4938 "failed to get SGMII PHY\n");
4939
4940 ret = phy_init(bp->sgmii_phy);
4941 if (ret)
4942 return dev_err_probe(&pdev->dev, ret,
4943 "failed to init SGMII PHY\n");
4944
4945 ret = zynqmp_pm_is_function_supported(PM_IOCTL, IOCTL_SET_GEM_CONFIG);
4946 if (!ret) {
4947 u32 pm_info[2];
4948
4949 ret = of_property_read_u32_array(pdev->dev.of_node, "power-domains",
4950 pm_info, ARRAY_SIZE(pm_info));
4951 if (ret) {
4952 dev_err(&pdev->dev, "Failed to read power management information\n");
4953 goto err_out_phy_exit;
4954 }
4955 ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_FIXED, 0);
4956 if (ret)
4957 goto err_out_phy_exit;
4958
4959 ret = zynqmp_pm_set_gem_config(pm_info[1], GEM_CONFIG_SGMII_MODE, 1);
4960 if (ret)
4961 goto err_out_phy_exit;
4962 }
4963
4964 }
4965
4966 /* Fully reset controller at hardware level if mapped in device tree */
4967 ret = device_reset_optional(&pdev->dev);
4968 if (ret) {
4969 phy_exit(bp->sgmii_phy);
4970 return dev_err_probe(&pdev->dev, ret, "failed to reset controller");
4971 }
4972
4973 ret = macb_init(pdev);
4974
4975 err_out_phy_exit:
4976 if (ret)
4977 phy_exit(bp->sgmii_phy);
4978
4979 return ret;
4980 }
4981
4982 static const struct macb_usrio_config sama7g5_usrio = {
4983 .mii = 0,
4984 .rmii = 1,
4985 .rgmii = 2,
4986 .refclk = BIT(2),
4987 .hdfctlen = BIT(6),
4988 };
4989
4990 static const struct macb_config fu540_c000_config = {
4991 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4992 MACB_CAPS_GEM_HAS_PTP,
4993 .dma_burst_length = 16,
4994 .clk_init = fu540_c000_clk_init,
4995 .init = fu540_c000_init,
4996 .jumbo_max_len = 10240,
4997 .usrio = &macb_default_usrio,
4998 };
4999
5000 static const struct macb_config at91sam9260_config = {
5001 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
5002 .clk_init = macb_clk_init,
5003 .init = macb_init,
5004 .usrio = &macb_default_usrio,
5005 };
5006
5007 static const struct macb_config sama5d3macb_config = {
5008 .caps = MACB_CAPS_SG_DISABLED |
5009 MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
5010 .clk_init = macb_clk_init,
5011 .init = macb_init,
5012 .usrio = &macb_default_usrio,
5013 };
5014
5015 static const struct macb_config pc302gem_config = {
5016 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
5017 .dma_burst_length = 16,
5018 .clk_init = macb_clk_init,
5019 .init = macb_init,
5020 .usrio = &macb_default_usrio,
5021 };
5022
5023 static const struct macb_config sama5d2_config = {
5024 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
5025 .dma_burst_length = 16,
5026 .clk_init = macb_clk_init,
5027 .init = macb_init,
5028 .jumbo_max_len = 10240,
5029 .usrio = &macb_default_usrio,
5030 };
5031
5032 static const struct macb_config sama5d29_config = {
5033 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_GEM_HAS_PTP,
5034 .dma_burst_length = 16,
5035 .clk_init = macb_clk_init,
5036 .init = macb_init,
5037 .usrio = &macb_default_usrio,
5038 };
5039
5040 static const struct macb_config sama5d3_config = {
5041 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE |
5042 MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
5043 .dma_burst_length = 16,
5044 .clk_init = macb_clk_init,
5045 .init = macb_init,
5046 .jumbo_max_len = 10240,
5047 .usrio = &macb_default_usrio,
5048 };
5049
5050 static const struct macb_config sama5d4_config = {
5051 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
5052 .dma_burst_length = 4,
5053 .clk_init = macb_clk_init,
5054 .init = macb_init,
5055 .usrio = &macb_default_usrio,
5056 };
5057
5058 static const struct macb_config emac_config = {
5059 .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
5060 .clk_init = at91ether_clk_init,
5061 .init = at91ether_init,
5062 .usrio = &macb_default_usrio,
5063 };
5064
5065 static const struct macb_config np4_config = {
5066 .caps = MACB_CAPS_USRIO_DISABLED,
5067 .clk_init = macb_clk_init,
5068 .init = macb_init,
5069 .usrio = &macb_default_usrio,
5070 };
5071
5072 static const struct macb_config zynqmp_config = {
5073 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
5074 MACB_CAPS_JUMBO |
5075 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
5076 .dma_burst_length = 16,
5077 .clk_init = macb_clk_init,
5078 .init = init_reset_optional,
5079 .jumbo_max_len = 10240,
5080 .usrio = &macb_default_usrio,
5081 };
5082
5083 static const struct macb_config zynq_config = {
5084 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
5085 MACB_CAPS_NEEDS_RSTONUBR,
5086 .dma_burst_length = 16,
5087 .clk_init = macb_clk_init,
5088 .init = macb_init,
5089 .usrio = &macb_default_usrio,
5090 };
5091
5092 static const struct macb_config mpfs_config = {
5093 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
5094 MACB_CAPS_JUMBO |
5095 MACB_CAPS_GEM_HAS_PTP,
5096 .dma_burst_length = 16,
5097 .clk_init = macb_clk_init,
5098 .init = init_reset_optional,
5099 .usrio = &macb_default_usrio,
5100 .max_tx_length = 4040, /* Cadence Erratum 1686 */
5101 .jumbo_max_len = 4040,
5102 };
5103
5104 static const struct macb_config sama7g5_gem_config = {
5105 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG |
5106 MACB_CAPS_MIIONRGMII | MACB_CAPS_GEM_HAS_PTP,
5107 .dma_burst_length = 16,
5108 .clk_init = macb_clk_init,
5109 .init = macb_init,
5110 .usrio = &sama7g5_usrio,
5111 };
5112
5113 static const struct macb_config sama7g5_emac_config = {
5114 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII |
5115 MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_MIIONRGMII |
5116 MACB_CAPS_GEM_HAS_PTP,
5117 .dma_burst_length = 16,
5118 .clk_init = macb_clk_init,
5119 .init = macb_init,
5120 .usrio = &sama7g5_usrio,
5121 };
5122
5123 static const struct macb_config versal_config = {
5124 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
5125 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH | MACB_CAPS_NEED_TSUCLK |
5126 MACB_CAPS_QUEUE_DISABLE,
5127 .dma_burst_length = 16,
5128 .clk_init = macb_clk_init,
5129 .init = init_reset_optional,
5130 .jumbo_max_len = 10240,
5131 .usrio = &macb_default_usrio,
5132 };
5133
5134 static const struct of_device_id macb_dt_ids[] = {
5135 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
5136 { .compatible = "cdns,macb" },
5137 { .compatible = "cdns,np4-macb", .data = &np4_config },
5138 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
5139 { .compatible = "cdns,gem", .data = &pc302gem_config },
5140 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
5141 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
5142 { .compatible = "atmel,sama5d29-gem", .data = &sama5d29_config },
5143 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
5144 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
5145 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
5146 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
5147 { .compatible = "cdns,emac", .data = &emac_config },
5148 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, /* deprecated */
5149 { .compatible = "cdns,zynq-gem", .data = &zynq_config }, /* deprecated */
5150 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
5151 { .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
5152 { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
5153 { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
5154 { .compatible = "xlnx,zynqmp-gem", .data = &zynqmp_config},
5155 { .compatible = "xlnx,zynq-gem", .data = &zynq_config },
5156 { .compatible = "xlnx,versal-gem", .data = &versal_config},
5157 { /* sentinel */ }
5158 };
5159 MODULE_DEVICE_TABLE(of, macb_dt_ids);
5160 #endif /* CONFIG_OF */
5161
5162 static const struct macb_config default_gem_config = {
5163 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
5164 MACB_CAPS_JUMBO |
5165 MACB_CAPS_GEM_HAS_PTP,
5166 .dma_burst_length = 16,
5167 .clk_init = macb_clk_init,
5168 .init = macb_init,
5169 .usrio = &macb_default_usrio,
5170 .jumbo_max_len = 10240,
5171 };
5172
macb_probe(struct platform_device * pdev)5173 static int macb_probe(struct platform_device *pdev)
5174 {
5175 const struct macb_config *macb_config = &default_gem_config;
5176 int (*clk_init)(struct platform_device *, struct clk **,
5177 struct clk **, struct clk **, struct clk **,
5178 struct clk **) = macb_config->clk_init;
5179 int (*init)(struct platform_device *) = macb_config->init;
5180 struct device_node *np = pdev->dev.of_node;
5181 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
5182 struct clk *tsu_clk = NULL;
5183 unsigned int queue_mask, num_queues;
5184 bool native_io;
5185 phy_interface_t interface;
5186 struct net_device *dev;
5187 struct resource *regs;
5188 u32 wtrmrk_rst_val;
5189 void __iomem *mem;
5190 struct macb *bp;
5191 int err, val;
5192
5193 mem = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
5194 if (IS_ERR(mem))
5195 return PTR_ERR(mem);
5196
5197 if (np) {
5198 const struct of_device_id *match;
5199
5200 match = of_match_node(macb_dt_ids, np);
5201 if (match && match->data) {
5202 macb_config = match->data;
5203 clk_init = macb_config->clk_init;
5204 init = macb_config->init;
5205 }
5206 }
5207
5208 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
5209 if (err)
5210 return err;
5211
5212 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
5213 pm_runtime_use_autosuspend(&pdev->dev);
5214 pm_runtime_get_noresume(&pdev->dev);
5215 pm_runtime_set_active(&pdev->dev);
5216 pm_runtime_enable(&pdev->dev);
5217 native_io = hw_is_native_io(mem);
5218
5219 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
5220 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
5221 if (!dev) {
5222 err = -ENOMEM;
5223 goto err_disable_clocks;
5224 }
5225
5226 dev->base_addr = regs->start;
5227
5228 SET_NETDEV_DEV(dev, &pdev->dev);
5229
5230 bp = netdev_priv(dev);
5231 bp->pdev = pdev;
5232 bp->dev = dev;
5233 bp->regs = mem;
5234 bp->native_io = native_io;
5235 if (native_io) {
5236 bp->macb_reg_readl = hw_readl_native;
5237 bp->macb_reg_writel = hw_writel_native;
5238 } else {
5239 bp->macb_reg_readl = hw_readl;
5240 bp->macb_reg_writel = hw_writel;
5241 }
5242 bp->num_queues = num_queues;
5243 bp->queue_mask = queue_mask;
5244 if (macb_config)
5245 bp->dma_burst_length = macb_config->dma_burst_length;
5246 bp->pclk = pclk;
5247 bp->hclk = hclk;
5248 bp->tx_clk = tx_clk;
5249 bp->rx_clk = rx_clk;
5250 bp->tsu_clk = tsu_clk;
5251 if (macb_config)
5252 bp->jumbo_max_len = macb_config->jumbo_max_len;
5253
5254 if (!hw_is_gem(bp->regs, bp->native_io))
5255 bp->max_tx_length = MACB_MAX_TX_LEN;
5256 else if (macb_config->max_tx_length)
5257 bp->max_tx_length = macb_config->max_tx_length;
5258 else
5259 bp->max_tx_length = GEM_MAX_TX_LEN;
5260
5261 bp->wol = 0;
5262 device_set_wakeup_capable(&pdev->dev, 1);
5263
5264 bp->usrio = macb_config->usrio;
5265
5266 /* By default we set to partial store and forward mode for zynqmp.
5267 * Disable if not set in devicetree.
5268 */
5269 if (GEM_BFEXT(PBUF_CUTTHRU, gem_readl(bp, DCFG6))) {
5270 err = of_property_read_u32(bp->pdev->dev.of_node,
5271 "cdns,rx-watermark",
5272 &bp->rx_watermark);
5273
5274 if (!err) {
5275 /* Disable partial store and forward in case of error or
5276 * invalid watermark value
5277 */
5278 wtrmrk_rst_val = (1 << (GEM_BFEXT(RX_PBUF_ADDR, gem_readl(bp, DCFG2)))) - 1;
5279 if (bp->rx_watermark > wtrmrk_rst_val || !bp->rx_watermark) {
5280 dev_info(&bp->pdev->dev, "Invalid watermark value\n");
5281 bp->rx_watermark = 0;
5282 }
5283 }
5284 }
5285 spin_lock_init(&bp->lock);
5286 spin_lock_init(&bp->stats_lock);
5287
5288 /* setup capabilities */
5289 macb_configure_caps(bp, macb_config);
5290
5291 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
5292 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
5293 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
5294 bp->hw_dma_cap |= HW_DMA_CAP_64B;
5295 }
5296 #endif
5297 platform_set_drvdata(pdev, dev);
5298
5299 dev->irq = platform_get_irq(pdev, 0);
5300 if (dev->irq < 0) {
5301 err = dev->irq;
5302 goto err_out_free_netdev;
5303 }
5304
5305 /* MTU range: 68 - 1518 or 10240 */
5306 dev->min_mtu = GEM_MTU_MIN_SIZE;
5307 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
5308 dev->max_mtu = bp->jumbo_max_len - ETH_HLEN - ETH_FCS_LEN;
5309 else
5310 dev->max_mtu = 1536 - ETH_HLEN - ETH_FCS_LEN;
5311
5312 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
5313 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
5314 if (val)
5315 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
5316 macb_dma_desc_get_size(bp);
5317
5318 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
5319 if (val)
5320 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
5321 macb_dma_desc_get_size(bp);
5322 }
5323
5324 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
5325 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
5326 bp->rx_intr_mask |= MACB_BIT(RXUBR);
5327
5328 err = of_get_ethdev_address(np, bp->dev);
5329 if (err == -EPROBE_DEFER)
5330 goto err_out_free_netdev;
5331 else if (err)
5332 macb_get_hwaddr(bp);
5333
5334 err = of_get_phy_mode(np, &interface);
5335 if (err)
5336 /* not found in DT, MII by default */
5337 bp->phy_interface = PHY_INTERFACE_MODE_MII;
5338 else
5339 bp->phy_interface = interface;
5340
5341 /* IP specific init */
5342 err = init(pdev);
5343 if (err)
5344 goto err_out_free_netdev;
5345
5346 err = macb_mii_init(bp);
5347 if (err)
5348 goto err_out_phy_exit;
5349
5350 netif_carrier_off(dev);
5351
5352 err = register_netdev(dev);
5353 if (err) {
5354 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
5355 goto err_out_unregister_mdio;
5356 }
5357
5358 INIT_WORK(&bp->hresp_err_bh_work, macb_hresp_error_task);
5359
5360 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
5361 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
5362 dev->base_addr, dev->irq, dev->dev_addr);
5363
5364 pm_runtime_mark_last_busy(&bp->pdev->dev);
5365 pm_runtime_put_autosuspend(&bp->pdev->dev);
5366
5367 return 0;
5368
5369 err_out_unregister_mdio:
5370 mdiobus_unregister(bp->mii_bus);
5371 mdiobus_free(bp->mii_bus);
5372
5373 err_out_phy_exit:
5374 phy_exit(bp->sgmii_phy);
5375
5376 err_out_free_netdev:
5377 free_netdev(dev);
5378
5379 err_disable_clocks:
5380 macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk);
5381 pm_runtime_disable(&pdev->dev);
5382 pm_runtime_set_suspended(&pdev->dev);
5383 pm_runtime_dont_use_autosuspend(&pdev->dev);
5384
5385 return err;
5386 }
5387
macb_remove(struct platform_device * pdev)5388 static void macb_remove(struct platform_device *pdev)
5389 {
5390 struct net_device *dev;
5391 struct macb *bp;
5392
5393 dev = platform_get_drvdata(pdev);
5394
5395 if (dev) {
5396 bp = netdev_priv(dev);
5397 phy_exit(bp->sgmii_phy);
5398 mdiobus_unregister(bp->mii_bus);
5399 mdiobus_free(bp->mii_bus);
5400
5401 unregister_netdev(dev);
5402 cancel_work_sync(&bp->hresp_err_bh_work);
5403 pm_runtime_disable(&pdev->dev);
5404 pm_runtime_dont_use_autosuspend(&pdev->dev);
5405 if (!pm_runtime_suspended(&pdev->dev)) {
5406 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk,
5407 bp->rx_clk, bp->tsu_clk);
5408 pm_runtime_set_suspended(&pdev->dev);
5409 }
5410 phylink_destroy(bp->phylink);
5411 free_netdev(dev);
5412 }
5413 }
5414
macb_suspend(struct device * dev)5415 static int __maybe_unused macb_suspend(struct device *dev)
5416 {
5417 struct net_device *netdev = dev_get_drvdata(dev);
5418 struct macb *bp = netdev_priv(netdev);
5419 struct in_ifaddr *ifa = NULL;
5420 struct macb_queue *queue;
5421 struct in_device *idev;
5422 unsigned long flags;
5423 unsigned int q;
5424 int err;
5425 u32 tmp;
5426
5427 if (!device_may_wakeup(&bp->dev->dev))
5428 phy_exit(bp->sgmii_phy);
5429
5430 if (!netif_running(netdev))
5431 return 0;
5432
5433 if (bp->wol & MACB_WOL_ENABLED) {
5434 /* Check for IP address in WOL ARP mode */
5435 idev = __in_dev_get_rcu(bp->dev);
5436 if (idev)
5437 ifa = rcu_dereference(idev->ifa_list);
5438 if ((bp->wolopts & WAKE_ARP) && !ifa) {
5439 netdev_err(netdev, "IP address not assigned as required by WoL walk ARP\n");
5440 return -EOPNOTSUPP;
5441 }
5442 spin_lock_irqsave(&bp->lock, flags);
5443
5444 /* Disable Tx and Rx engines before disabling the queues,
5445 * this is mandatory as per the IP spec sheet
5446 */
5447 tmp = macb_readl(bp, NCR);
5448 macb_writel(bp, NCR, tmp & ~(MACB_BIT(TE) | MACB_BIT(RE)));
5449 for (q = 0, queue = bp->queues; q < bp->num_queues;
5450 ++q, ++queue) {
5451 /* Disable RX queues */
5452 if (bp->caps & MACB_CAPS_QUEUE_DISABLE) {
5453 queue_writel(queue, RBQP, MACB_BIT(QUEUE_DISABLE));
5454 } else {
5455 /* Tie off RX queues */
5456 queue_writel(queue, RBQP,
5457 lower_32_bits(bp->rx_ring_tieoff_dma));
5458 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
5459 queue_writel(queue, RBQPH,
5460 upper_32_bits(bp->rx_ring_tieoff_dma));
5461 #endif
5462 }
5463 /* Disable all interrupts */
5464 queue_writel(queue, IDR, -1);
5465 queue_readl(queue, ISR);
5466 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
5467 queue_writel(queue, ISR, -1);
5468 }
5469 /* Enable Receive engine */
5470 macb_writel(bp, NCR, tmp | MACB_BIT(RE));
5471 /* Flush all status bits */
5472 macb_writel(bp, TSR, -1);
5473 macb_writel(bp, RSR, -1);
5474
5475 tmp = (bp->wolopts & WAKE_MAGIC) ? MACB_BIT(MAG) : 0;
5476 if (bp->wolopts & WAKE_ARP) {
5477 tmp |= MACB_BIT(ARP);
5478 /* write IP address into register */
5479 tmp |= MACB_BFEXT(IP, be32_to_cpu(ifa->ifa_local));
5480 }
5481
5482 /* Change interrupt handler and
5483 * Enable WoL IRQ on queue 0
5484 */
5485 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
5486 if (macb_is_gem(bp)) {
5487 err = devm_request_irq(dev, bp->queues[0].irq, gem_wol_interrupt,
5488 IRQF_SHARED, netdev->name, bp->queues);
5489 if (err) {
5490 dev_err(dev,
5491 "Unable to request IRQ %d (error %d)\n",
5492 bp->queues[0].irq, err);
5493 spin_unlock_irqrestore(&bp->lock, flags);
5494 return err;
5495 }
5496 queue_writel(bp->queues, IER, GEM_BIT(WOL));
5497 gem_writel(bp, WOL, tmp);
5498 } else {
5499 err = devm_request_irq(dev, bp->queues[0].irq, macb_wol_interrupt,
5500 IRQF_SHARED, netdev->name, bp->queues);
5501 if (err) {
5502 dev_err(dev,
5503 "Unable to request IRQ %d (error %d)\n",
5504 bp->queues[0].irq, err);
5505 spin_unlock_irqrestore(&bp->lock, flags);
5506 return err;
5507 }
5508 queue_writel(bp->queues, IER, MACB_BIT(WOL));
5509 macb_writel(bp, WOL, tmp);
5510 }
5511 spin_unlock_irqrestore(&bp->lock, flags);
5512
5513 enable_irq_wake(bp->queues[0].irq);
5514 }
5515
5516 netif_device_detach(netdev);
5517 for (q = 0, queue = bp->queues; q < bp->num_queues;
5518 ++q, ++queue) {
5519 napi_disable(&queue->napi_rx);
5520 napi_disable(&queue->napi_tx);
5521 }
5522
5523 if (!(bp->wol & MACB_WOL_ENABLED)) {
5524 rtnl_lock();
5525 phylink_stop(bp->phylink);
5526 rtnl_unlock();
5527 spin_lock_irqsave(&bp->lock, flags);
5528 macb_reset_hw(bp);
5529 spin_unlock_irqrestore(&bp->lock, flags);
5530 }
5531
5532 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
5533 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
5534
5535 if (netdev->hw_features & NETIF_F_NTUPLE)
5536 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
5537
5538 if (bp->ptp_info)
5539 bp->ptp_info->ptp_remove(netdev);
5540 if (!device_may_wakeup(dev))
5541 pm_runtime_force_suspend(dev);
5542
5543 return 0;
5544 }
5545
macb_resume(struct device * dev)5546 static int __maybe_unused macb_resume(struct device *dev)
5547 {
5548 struct net_device *netdev = dev_get_drvdata(dev);
5549 struct macb *bp = netdev_priv(netdev);
5550 struct macb_queue *queue;
5551 unsigned long flags;
5552 unsigned int q;
5553 int err;
5554
5555 if (!device_may_wakeup(&bp->dev->dev))
5556 phy_init(bp->sgmii_phy);
5557
5558 if (!netif_running(netdev))
5559 return 0;
5560
5561 if (!device_may_wakeup(dev))
5562 pm_runtime_force_resume(dev);
5563
5564 if (bp->wol & MACB_WOL_ENABLED) {
5565 spin_lock_irqsave(&bp->lock, flags);
5566 /* Disable WoL */
5567 if (macb_is_gem(bp)) {
5568 queue_writel(bp->queues, IDR, GEM_BIT(WOL));
5569 gem_writel(bp, WOL, 0);
5570 } else {
5571 queue_writel(bp->queues, IDR, MACB_BIT(WOL));
5572 macb_writel(bp, WOL, 0);
5573 }
5574 /* Clear ISR on queue 0 */
5575 queue_readl(bp->queues, ISR);
5576 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
5577 queue_writel(bp->queues, ISR, -1);
5578 /* Replace interrupt handler on queue 0 */
5579 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
5580 err = devm_request_irq(dev, bp->queues[0].irq, macb_interrupt,
5581 IRQF_SHARED, netdev->name, bp->queues);
5582 if (err) {
5583 dev_err(dev,
5584 "Unable to request IRQ %d (error %d)\n",
5585 bp->queues[0].irq, err);
5586 spin_unlock_irqrestore(&bp->lock, flags);
5587 return err;
5588 }
5589 spin_unlock_irqrestore(&bp->lock, flags);
5590
5591 disable_irq_wake(bp->queues[0].irq);
5592
5593 /* Now make sure we disable phy before moving
5594 * to common restore path
5595 */
5596 rtnl_lock();
5597 phylink_stop(bp->phylink);
5598 rtnl_unlock();
5599 }
5600
5601 for (q = 0, queue = bp->queues; q < bp->num_queues;
5602 ++q, ++queue) {
5603 napi_enable(&queue->napi_rx);
5604 napi_enable(&queue->napi_tx);
5605 }
5606
5607 if (netdev->hw_features & NETIF_F_NTUPLE)
5608 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
5609
5610 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
5611 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
5612
5613 macb_writel(bp, NCR, MACB_BIT(MPE));
5614 macb_init_hw(bp);
5615 macb_set_rx_mode(netdev);
5616 macb_restore_features(bp);
5617 rtnl_lock();
5618
5619 phylink_start(bp->phylink);
5620 rtnl_unlock();
5621
5622 netif_device_attach(netdev);
5623 if (bp->ptp_info)
5624 bp->ptp_info->ptp_init(netdev);
5625
5626 return 0;
5627 }
5628
macb_runtime_suspend(struct device * dev)5629 static int __maybe_unused macb_runtime_suspend(struct device *dev)
5630 {
5631 struct net_device *netdev = dev_get_drvdata(dev);
5632 struct macb *bp = netdev_priv(netdev);
5633
5634 if (!(device_may_wakeup(dev)))
5635 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk);
5636 else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK))
5637 macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk);
5638
5639 return 0;
5640 }
5641
macb_runtime_resume(struct device * dev)5642 static int __maybe_unused macb_runtime_resume(struct device *dev)
5643 {
5644 struct net_device *netdev = dev_get_drvdata(dev);
5645 struct macb *bp = netdev_priv(netdev);
5646
5647 if (!(device_may_wakeup(dev))) {
5648 clk_prepare_enable(bp->pclk);
5649 clk_prepare_enable(bp->hclk);
5650 clk_prepare_enable(bp->tx_clk);
5651 clk_prepare_enable(bp->rx_clk);
5652 clk_prepare_enable(bp->tsu_clk);
5653 } else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK)) {
5654 clk_prepare_enable(bp->tsu_clk);
5655 }
5656
5657 return 0;
5658 }
5659
5660 static const struct dev_pm_ops macb_pm_ops = {
5661 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
5662 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
5663 };
5664
5665 static struct platform_driver macb_driver = {
5666 .probe = macb_probe,
5667 .remove = macb_remove,
5668 .driver = {
5669 .name = "macb",
5670 .of_match_table = of_match_ptr(macb_dt_ids),
5671 .pm = &macb_pm_ops,
5672 },
5673 };
5674
5675 module_platform_driver(macb_driver);
5676
5677 MODULE_LICENSE("GPL");
5678 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
5679 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
5680 MODULE_ALIAS("platform:macb");
5681