1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCI Specific M_CAN Glue
4 *
5 * Copyright (C) 2018-2020 Intel Corporation
6 * Author: Felipe Balbi (Intel)
7 * Author: Jarkko Nikula <jarkko.nikula@linux.intel.com>
8 * Author: Raymond Tan <raymond.tan@intel.com>
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/pci.h>
15 #include <linux/pm_runtime.h>
16
17 #include "m_can.h"
18
19 #define M_CAN_PCI_MMIO_BAR 0
20
21 #define M_CAN_CLOCK_FREQ_EHL 200000000
22 #define CTL_CSR_INT_CTL_OFFSET 0x508
23
24 struct m_can_pci_priv {
25 struct m_can_classdev cdev;
26
27 void __iomem *base;
28 };
29
cdev_to_priv(struct m_can_classdev * cdev)30 static inline struct m_can_pci_priv *cdev_to_priv(struct m_can_classdev *cdev)
31 {
32 return container_of(cdev, struct m_can_pci_priv, cdev);
33 }
34
iomap_read_reg(struct m_can_classdev * cdev,int reg)35 static u32 iomap_read_reg(struct m_can_classdev *cdev, int reg)
36 {
37 struct m_can_pci_priv *priv = cdev_to_priv(cdev);
38
39 return readl(priv->base + reg);
40 }
41
iomap_read_fifo(struct m_can_classdev * cdev,int offset,void * val,size_t val_count)42 static int iomap_read_fifo(struct m_can_classdev *cdev, int offset, void *val, size_t val_count)
43 {
44 struct m_can_pci_priv *priv = cdev_to_priv(cdev);
45 void __iomem *src = priv->base + offset;
46
47 while (val_count--) {
48 *(unsigned int *)val = ioread32(src);
49 val += 4;
50 src += 4;
51 }
52
53 return 0;
54 }
55
iomap_write_reg(struct m_can_classdev * cdev,int reg,int val)56 static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val)
57 {
58 struct m_can_pci_priv *priv = cdev_to_priv(cdev);
59
60 writel(val, priv->base + reg);
61
62 return 0;
63 }
64
iomap_write_fifo(struct m_can_classdev * cdev,int offset,const void * val,size_t val_count)65 static int iomap_write_fifo(struct m_can_classdev *cdev, int offset,
66 const void *val, size_t val_count)
67 {
68 struct m_can_pci_priv *priv = cdev_to_priv(cdev);
69 void __iomem *dst = priv->base + offset;
70
71 while (val_count--) {
72 iowrite32(*(unsigned int *)val, dst);
73 val += 4;
74 dst += 4;
75 }
76
77 return 0;
78 }
79
80 static const struct m_can_ops m_can_pci_ops = {
81 .read_reg = iomap_read_reg,
82 .write_reg = iomap_write_reg,
83 .write_fifo = iomap_write_fifo,
84 .read_fifo = iomap_read_fifo,
85 };
86
m_can_pci_probe(struct pci_dev * pci,const struct pci_device_id * id)87 static int m_can_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
88 {
89 struct device *dev = &pci->dev;
90 struct m_can_classdev *mcan_class;
91 struct m_can_pci_priv *priv;
92 void __iomem *base;
93 int ret;
94
95 ret = pcim_enable_device(pci);
96 if (ret)
97 return ret;
98
99 pci_set_master(pci);
100
101 ret = pcim_iomap_regions(pci, BIT(M_CAN_PCI_MMIO_BAR), pci_name(pci));
102 if (ret)
103 return ret;
104
105 base = pcim_iomap_table(pci)[M_CAN_PCI_MMIO_BAR];
106
107 if (!base) {
108 dev_err(dev, "failed to map BARs\n");
109 return -ENOMEM;
110 }
111
112 mcan_class = m_can_class_allocate_dev(&pci->dev,
113 sizeof(struct m_can_pci_priv));
114 if (!mcan_class)
115 return -ENOMEM;
116
117 priv = cdev_to_priv(mcan_class);
118
119 priv->base = base;
120
121 ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_ALL_TYPES);
122 if (ret < 0)
123 goto err_free_dev;
124
125 mcan_class->dev = &pci->dev;
126 mcan_class->net->irq = pci_irq_vector(pci, 0);
127 mcan_class->pm_clock_support = 1;
128 mcan_class->pm_wake_source = 0;
129 mcan_class->can.clock.freq = id->driver_data;
130 mcan_class->irq_edge_triggered = true;
131 mcan_class->ops = &m_can_pci_ops;
132
133 pci_set_drvdata(pci, mcan_class);
134
135 ret = m_can_class_register(mcan_class);
136 if (ret)
137 goto err_free_irq;
138
139 /* Enable interrupt control at CAN wrapper IP */
140 writel(0x1, base + CTL_CSR_INT_CTL_OFFSET);
141
142 pm_runtime_set_autosuspend_delay(dev, 1000);
143 pm_runtime_use_autosuspend(dev);
144 pm_runtime_put_noidle(dev);
145 pm_runtime_allow(dev);
146
147 return 0;
148
149 err_free_irq:
150 pci_free_irq_vectors(pci);
151 err_free_dev:
152 m_can_class_free_dev(mcan_class->net);
153 return ret;
154 }
155
m_can_pci_remove(struct pci_dev * pci)156 static void m_can_pci_remove(struct pci_dev *pci)
157 {
158 struct m_can_classdev *mcan_class = pci_get_drvdata(pci);
159 struct m_can_pci_priv *priv = cdev_to_priv(mcan_class);
160
161 pm_runtime_forbid(&pci->dev);
162 pm_runtime_get_noresume(&pci->dev);
163
164 /* Disable interrupt control at CAN wrapper IP */
165 writel(0x0, priv->base + CTL_CSR_INT_CTL_OFFSET);
166
167 m_can_class_unregister(mcan_class);
168 m_can_class_free_dev(mcan_class->net);
169 pci_free_irq_vectors(pci);
170 }
171
m_can_pci_suspend(struct device * dev)172 static __maybe_unused int m_can_pci_suspend(struct device *dev)
173 {
174 return m_can_class_suspend(dev);
175 }
176
m_can_pci_resume(struct device * dev)177 static __maybe_unused int m_can_pci_resume(struct device *dev)
178 {
179 return m_can_class_resume(dev);
180 }
181
182 static SIMPLE_DEV_PM_OPS(m_can_pci_pm_ops,
183 m_can_pci_suspend, m_can_pci_resume);
184
185 static const struct pci_device_id m_can_pci_id_table[] = {
186 { PCI_VDEVICE(INTEL, 0x4bc1), M_CAN_CLOCK_FREQ_EHL, },
187 { PCI_VDEVICE(INTEL, 0x4bc2), M_CAN_CLOCK_FREQ_EHL, },
188 { } /* Terminating Entry */
189 };
190 MODULE_DEVICE_TABLE(pci, m_can_pci_id_table);
191
192 static struct pci_driver m_can_pci_driver = {
193 .name = "m_can_pci",
194 .probe = m_can_pci_probe,
195 .remove = m_can_pci_remove,
196 .id_table = m_can_pci_id_table,
197 .driver = {
198 .pm = &m_can_pci_pm_ops,
199 },
200 };
201
202 module_pci_driver(m_can_pci_driver);
203
204 MODULE_AUTHOR("Felipe Balbi (Intel)");
205 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
206 MODULE_AUTHOR("Raymond Tan <raymond.tan@intel.com>");
207 MODULE_LICENSE("GPL");
208 MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller on PCI bus");
209