1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /*
3 * LTC2992 - Dual Wide Range Power Monitor
4 *
5 * Copyright 2020 Analog Devices Inc.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/err.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/hwmon.h>
13 #include <linux/i2c.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/property.h>
17 #include <linux/regmap.h>
18
19 #define LTC2992_CTRLB 0x01
20 #define LTC2992_FAULT1 0x03
21 #define LTC2992_POWER1 0x05
22 #define LTC2992_POWER1_MAX 0x08
23 #define LTC2992_POWER1_MIN 0x0B
24 #define LTC2992_POWER1_MAX_THRESH 0x0E
25 #define LTC2992_POWER1_MIN_THRESH 0x11
26 #define LTC2992_DSENSE1 0x14
27 #define LTC2992_DSENSE1_MAX 0x16
28 #define LTC2992_DSENSE1_MIN 0x18
29 #define LTC2992_DSENSE1_MAX_THRESH 0x1A
30 #define LTC2992_DSENSE1_MIN_THRESH 0x1C
31 #define LTC2992_SENSE1 0x1E
32 #define LTC2992_SENSE1_MAX 0x20
33 #define LTC2992_SENSE1_MIN 0x22
34 #define LTC2992_SENSE1_MAX_THRESH 0x24
35 #define LTC2992_SENSE1_MIN_THRESH 0x26
36 #define LTC2992_G1 0x28
37 #define LTC2992_G1_MAX 0x2A
38 #define LTC2992_G1_MIN 0x2C
39 #define LTC2992_G1_MAX_THRESH 0x2E
40 #define LTC2992_G1_MIN_THRESH 0x30
41 #define LTC2992_FAULT2 0x35
42 #define LTC2992_G2 0x5A
43 #define LTC2992_G2_MAX 0x5C
44 #define LTC2992_G2_MIN 0x5E
45 #define LTC2992_G2_MAX_THRESH 0x60
46 #define LTC2992_G2_MIN_THRESH 0x62
47 #define LTC2992_G3 0x64
48 #define LTC2992_G3_MAX 0x66
49 #define LTC2992_G3_MIN 0x68
50 #define LTC2992_G3_MAX_THRESH 0x6A
51 #define LTC2992_G3_MIN_THRESH 0x6C
52 #define LTC2992_G4 0x6E
53 #define LTC2992_G4_MAX 0x70
54 #define LTC2992_G4_MIN 0x72
55 #define LTC2992_G4_MAX_THRESH 0x74
56 #define LTC2992_G4_MIN_THRESH 0x76
57 #define LTC2992_FAULT3 0x92
58 #define LTC2992_GPIO_STATUS 0x95
59 #define LTC2992_GPIO_IO_CTRL 0x96
60 #define LTC2992_GPIO_CTRL 0x97
61
62 #define LTC2992_POWER(x) (LTC2992_POWER1 + ((x) * 0x32))
63 #define LTC2992_POWER_MAX(x) (LTC2992_POWER1_MAX + ((x) * 0x32))
64 #define LTC2992_POWER_MIN(x) (LTC2992_POWER1_MIN + ((x) * 0x32))
65 #define LTC2992_POWER_MAX_THRESH(x) (LTC2992_POWER1_MAX_THRESH + ((x) * 0x32))
66 #define LTC2992_POWER_MIN_THRESH(x) (LTC2992_POWER1_MIN_THRESH + ((x) * 0x32))
67 #define LTC2992_DSENSE(x) (LTC2992_DSENSE1 + ((x) * 0x32))
68 #define LTC2992_DSENSE_MAX(x) (LTC2992_DSENSE1_MAX + ((x) * 0x32))
69 #define LTC2992_DSENSE_MIN(x) (LTC2992_DSENSE1_MIN + ((x) * 0x32))
70 #define LTC2992_DSENSE_MAX_THRESH(x) (LTC2992_DSENSE1_MAX_THRESH + ((x) * 0x32))
71 #define LTC2992_DSENSE_MIN_THRESH(x) (LTC2992_DSENSE1_MIN_THRESH + ((x) * 0x32))
72 #define LTC2992_SENSE(x) (LTC2992_SENSE1 + ((x) * 0x32))
73 #define LTC2992_SENSE_MAX(x) (LTC2992_SENSE1_MAX + ((x) * 0x32))
74 #define LTC2992_SENSE_MIN(x) (LTC2992_SENSE1_MIN + ((x) * 0x32))
75 #define LTC2992_SENSE_MAX_THRESH(x) (LTC2992_SENSE1_MAX_THRESH + ((x) * 0x32))
76 #define LTC2992_SENSE_MIN_THRESH(x) (LTC2992_SENSE1_MIN_THRESH + ((x) * 0x32))
77 #define LTC2992_POWER_FAULT(x) (LTC2992_FAULT1 + ((x) * 0x32))
78 #define LTC2992_SENSE_FAULT(x) (LTC2992_FAULT1 + ((x) * 0x32))
79 #define LTC2992_DSENSE_FAULT(x) (LTC2992_FAULT1 + ((x) * 0x32))
80
81 /* CTRLB register bitfields */
82 #define LTC2992_RESET_HISTORY BIT(3)
83
84 /* FAULT1 FAULT2 registers common bitfields */
85 #define LTC2992_POWER_FAULT_MSK(x) (BIT(6) << (x))
86 #define LTC2992_DSENSE_FAULT_MSK(x) (BIT(4) << (x))
87 #define LTC2992_SENSE_FAULT_MSK(x) (BIT(2) << (x))
88
89 /* FAULT1 bitfields */
90 #define LTC2992_GPIO1_FAULT_MSK(x) (BIT(0) << (x))
91
92 /* FAULT2 bitfields */
93 #define LTC2992_GPIO2_FAULT_MSK(x) (BIT(0) << (x))
94
95 /* FAULT3 bitfields */
96 #define LTC2992_GPIO3_FAULT_MSK(x) (BIT(6) << (x))
97 #define LTC2992_GPIO4_FAULT_MSK(x) (BIT(4) << (x))
98
99 #define LTC2992_IADC_NANOV_LSB 12500
100 #define LTC2992_VADC_UV_LSB 25000
101 #define LTC2992_VADC_GPIO_UV_LSB 500
102
103 #define LTC2992_GPIO_NR 4
104 #define LTC2992_GPIO1_BIT 7
105 #define LTC2992_GPIO2_BIT 6
106 #define LTC2992_GPIO3_BIT 0
107 #define LTC2992_GPIO4_BIT 6
108 #define LTC2992_GPIO_BIT(x) (LTC2992_GPIO_NR - (x) - 1)
109
110 struct ltc2992_state {
111 struct i2c_client *client;
112 struct gpio_chip gc;
113 struct mutex gpio_mutex; /* lock for gpio access */
114 const char *gpio_names[LTC2992_GPIO_NR];
115 struct regmap *regmap;
116 u32 r_sense_uohm[2];
117 };
118
119 struct ltc2992_gpio_regs {
120 u8 data;
121 u8 max;
122 u8 min;
123 u8 max_thresh;
124 u8 min_thresh;
125 u8 alarm;
126 u8 min_alarm_msk;
127 u8 max_alarm_msk;
128 u8 ctrl;
129 u8 ctrl_bit;
130 };
131
132 static const struct ltc2992_gpio_regs ltc2992_gpio_addr_map[] = {
133 {
134 .data = LTC2992_G1,
135 .max = LTC2992_G1_MAX,
136 .min = LTC2992_G1_MIN,
137 .max_thresh = LTC2992_G1_MAX_THRESH,
138 .min_thresh = LTC2992_G1_MIN_THRESH,
139 .alarm = LTC2992_FAULT1,
140 .min_alarm_msk = LTC2992_GPIO1_FAULT_MSK(0),
141 .max_alarm_msk = LTC2992_GPIO1_FAULT_MSK(1),
142 .ctrl = LTC2992_GPIO_IO_CTRL,
143 .ctrl_bit = LTC2992_GPIO1_BIT,
144 },
145 {
146 .data = LTC2992_G2,
147 .max = LTC2992_G2_MAX,
148 .min = LTC2992_G2_MIN,
149 .max_thresh = LTC2992_G2_MAX_THRESH,
150 .min_thresh = LTC2992_G2_MIN_THRESH,
151 .alarm = LTC2992_FAULT2,
152 .min_alarm_msk = LTC2992_GPIO2_FAULT_MSK(0),
153 .max_alarm_msk = LTC2992_GPIO2_FAULT_MSK(1),
154 .ctrl = LTC2992_GPIO_IO_CTRL,
155 .ctrl_bit = LTC2992_GPIO2_BIT,
156 },
157 {
158 .data = LTC2992_G3,
159 .max = LTC2992_G3_MAX,
160 .min = LTC2992_G3_MIN,
161 .max_thresh = LTC2992_G3_MAX_THRESH,
162 .min_thresh = LTC2992_G3_MIN_THRESH,
163 .alarm = LTC2992_FAULT3,
164 .min_alarm_msk = LTC2992_GPIO3_FAULT_MSK(0),
165 .max_alarm_msk = LTC2992_GPIO3_FAULT_MSK(1),
166 .ctrl = LTC2992_GPIO_IO_CTRL,
167 .ctrl_bit = LTC2992_GPIO3_BIT,
168 },
169 {
170 .data = LTC2992_G4,
171 .max = LTC2992_G4_MAX,
172 .min = LTC2992_G4_MIN,
173 .max_thresh = LTC2992_G4_MAX_THRESH,
174 .min_thresh = LTC2992_G4_MIN_THRESH,
175 .alarm = LTC2992_FAULT3,
176 .min_alarm_msk = LTC2992_GPIO4_FAULT_MSK(0),
177 .max_alarm_msk = LTC2992_GPIO4_FAULT_MSK(1),
178 .ctrl = LTC2992_GPIO_CTRL,
179 .ctrl_bit = LTC2992_GPIO4_BIT,
180 },
181 };
182
183 static const char *ltc2992_gpio_names[LTC2992_GPIO_NR] = {
184 "GPIO1", "GPIO2", "GPIO3", "GPIO4",
185 };
186
ltc2992_read_reg(struct ltc2992_state * st,u8 addr,const u8 reg_len)187 static int ltc2992_read_reg(struct ltc2992_state *st, u8 addr, const u8 reg_len)
188 {
189 u8 regvals[4];
190 int val;
191 int ret;
192 int i;
193
194 ret = regmap_bulk_read(st->regmap, addr, regvals, reg_len);
195 if (ret < 0)
196 return ret;
197
198 val = 0;
199 for (i = 0; i < reg_len; i++)
200 val |= regvals[reg_len - i - 1] << (i * 8);
201
202 return val;
203 }
204
ltc2992_write_reg(struct ltc2992_state * st,u8 addr,const u8 reg_len,u32 val)205 static int ltc2992_write_reg(struct ltc2992_state *st, u8 addr, const u8 reg_len, u32 val)
206 {
207 u8 regvals[4];
208 int i;
209
210 for (i = 0; i < reg_len; i++)
211 regvals[reg_len - i - 1] = (val >> (i * 8)) & 0xFF;
212
213 return regmap_bulk_write(st->regmap, addr, regvals, reg_len);
214 }
215
ltc2992_gpio_get(struct gpio_chip * chip,unsigned int offset)216 static int ltc2992_gpio_get(struct gpio_chip *chip, unsigned int offset)
217 {
218 struct ltc2992_state *st = gpiochip_get_data(chip);
219 unsigned long gpio_status;
220 int reg;
221
222 mutex_lock(&st->gpio_mutex);
223 reg = ltc2992_read_reg(st, LTC2992_GPIO_STATUS, 1);
224 mutex_unlock(&st->gpio_mutex);
225
226 if (reg < 0)
227 return reg;
228
229 gpio_status = reg;
230
231 return !test_bit(LTC2992_GPIO_BIT(offset), &gpio_status);
232 }
233
ltc2992_gpio_get_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)234 static int ltc2992_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
235 unsigned long *bits)
236 {
237 struct ltc2992_state *st = gpiochip_get_data(chip);
238 unsigned long gpio_status;
239 unsigned int gpio_nr;
240 int reg;
241
242 mutex_lock(&st->gpio_mutex);
243 reg = ltc2992_read_reg(st, LTC2992_GPIO_STATUS, 1);
244 mutex_unlock(&st->gpio_mutex);
245
246 if (reg < 0)
247 return reg;
248
249 gpio_status = reg;
250
251 for_each_set_bit(gpio_nr, mask, LTC2992_GPIO_NR) {
252 if (test_bit(LTC2992_GPIO_BIT(gpio_nr), &gpio_status))
253 set_bit(gpio_nr, bits);
254 }
255
256 return 0;
257 }
258
ltc2992_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)259 static int ltc2992_gpio_set(struct gpio_chip *chip, unsigned int offset,
260 int value)
261 {
262 struct ltc2992_state *st = gpiochip_get_data(chip);
263 unsigned long gpio_ctrl;
264 int reg, ret;
265
266 mutex_lock(&st->gpio_mutex);
267 reg = ltc2992_read_reg(st, ltc2992_gpio_addr_map[offset].ctrl, 1);
268 if (reg < 0) {
269 mutex_unlock(&st->gpio_mutex);
270 return reg;
271 }
272
273 gpio_ctrl = reg;
274 assign_bit(ltc2992_gpio_addr_map[offset].ctrl_bit, &gpio_ctrl, value);
275
276 ret = ltc2992_write_reg(st, ltc2992_gpio_addr_map[offset].ctrl, 1,
277 gpio_ctrl);
278 mutex_unlock(&st->gpio_mutex);
279
280 return ret;
281 }
282
ltc2992_gpio_set_multiple(struct gpio_chip * chip,unsigned long * mask,unsigned long * bits)283 static int ltc2992_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
284 unsigned long *bits)
285 {
286 struct ltc2992_state *st = gpiochip_get_data(chip);
287 unsigned long gpio_ctrl_io = 0;
288 unsigned long gpio_ctrl = 0;
289 unsigned int gpio_nr;
290 int ret;
291
292 for_each_set_bit(gpio_nr, mask, LTC2992_GPIO_NR) {
293 if (gpio_nr < 3)
294 assign_bit(ltc2992_gpio_addr_map[gpio_nr].ctrl_bit, &gpio_ctrl_io, true);
295
296 if (gpio_nr == 3)
297 assign_bit(ltc2992_gpio_addr_map[gpio_nr].ctrl_bit, &gpio_ctrl, true);
298 }
299
300 mutex_lock(&st->gpio_mutex);
301 ret = ltc2992_write_reg(st, LTC2992_GPIO_IO_CTRL, 1, gpio_ctrl_io);
302 if (ret)
303 goto out;
304
305 ret = ltc2992_write_reg(st, LTC2992_GPIO_CTRL, 1, gpio_ctrl);
306 out:
307 mutex_unlock(&st->gpio_mutex);
308 return ret;
309 }
310
ltc2992_config_gpio(struct ltc2992_state * st)311 static int ltc2992_config_gpio(struct ltc2992_state *st)
312 {
313 const char *name = dev_name(&st->client->dev);
314 char *gpio_name;
315 int ret;
316 int i;
317
318 ret = ltc2992_write_reg(st, LTC2992_GPIO_IO_CTRL, 1, 0);
319 if (ret < 0)
320 return ret;
321
322 mutex_init(&st->gpio_mutex);
323
324 for (i = 0; i < ARRAY_SIZE(st->gpio_names); i++) {
325 gpio_name = devm_kasprintf(&st->client->dev, GFP_KERNEL, "ltc2992-%x-%s",
326 st->client->addr, ltc2992_gpio_names[i]);
327 if (!gpio_name)
328 return -ENOMEM;
329
330 st->gpio_names[i] = gpio_name;
331 }
332
333 st->gc.label = name;
334 st->gc.parent = &st->client->dev;
335 st->gc.owner = THIS_MODULE;
336 st->gc.can_sleep = true;
337 st->gc.base = -1;
338 st->gc.names = st->gpio_names;
339 st->gc.ngpio = ARRAY_SIZE(st->gpio_names);
340 st->gc.get = ltc2992_gpio_get;
341 st->gc.get_multiple = ltc2992_gpio_get_multiple;
342 st->gc.set = ltc2992_gpio_set;
343 st->gc.set_multiple = ltc2992_gpio_set_multiple;
344
345 ret = devm_gpiochip_add_data(&st->client->dev, &st->gc, st);
346 if (ret)
347 dev_err(&st->client->dev, "GPIO registering failed (%d)\n", ret);
348
349 return ret;
350 }
351
ltc2992_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)352 static umode_t ltc2992_is_visible(const void *data, enum hwmon_sensor_types type, u32 attr,
353 int channel)
354 {
355 const struct ltc2992_state *st = data;
356
357 switch (type) {
358 case hwmon_chip:
359 switch (attr) {
360 case hwmon_chip_in_reset_history:
361 return 0200;
362 }
363 break;
364 case hwmon_in:
365 switch (attr) {
366 case hwmon_in_input:
367 case hwmon_in_lowest:
368 case hwmon_in_highest:
369 case hwmon_in_min_alarm:
370 case hwmon_in_max_alarm:
371 return 0444;
372 case hwmon_in_min:
373 case hwmon_in_max:
374 return 0644;
375 }
376 break;
377 case hwmon_curr:
378 switch (attr) {
379 case hwmon_curr_input:
380 case hwmon_curr_lowest:
381 case hwmon_curr_highest:
382 case hwmon_curr_min_alarm:
383 case hwmon_curr_max_alarm:
384 if (st->r_sense_uohm[channel])
385 return 0444;
386 break;
387 case hwmon_curr_min:
388 case hwmon_curr_max:
389 if (st->r_sense_uohm[channel])
390 return 0644;
391 break;
392 }
393 break;
394 case hwmon_power:
395 switch (attr) {
396 case hwmon_power_input:
397 case hwmon_power_input_lowest:
398 case hwmon_power_input_highest:
399 case hwmon_power_min_alarm:
400 case hwmon_power_max_alarm:
401 if (st->r_sense_uohm[channel])
402 return 0444;
403 break;
404 case hwmon_power_min:
405 case hwmon_power_max:
406 if (st->r_sense_uohm[channel])
407 return 0644;
408 break;
409 }
410 break;
411 default:
412 break;
413 }
414
415 return 0;
416 }
417
ltc2992_get_voltage(struct ltc2992_state * st,u32 reg,u32 scale,long * val)418 static int ltc2992_get_voltage(struct ltc2992_state *st, u32 reg, u32 scale, long *val)
419 {
420 int reg_val;
421
422 reg_val = ltc2992_read_reg(st, reg, 2);
423 if (reg_val < 0)
424 return reg_val;
425
426 reg_val = reg_val >> 4;
427 *val = DIV_ROUND_CLOSEST(reg_val * scale, 1000);
428
429 return 0;
430 }
431
ltc2992_set_voltage(struct ltc2992_state * st,u32 reg,u32 scale,long val)432 static int ltc2992_set_voltage(struct ltc2992_state *st, u32 reg, u32 scale, long val)
433 {
434 u32 reg_val;
435 long vmax;
436
437 vmax = DIV_ROUND_CLOSEST_ULL(0xFFFULL * scale, 1000);
438 val = max(val, 0L);
439 val = min(val, vmax);
440 reg_val = min(DIV_ROUND_CLOSEST_ULL((u64)val * 1000, scale),
441 0xFFFULL) << 4;
442
443 return ltc2992_write_reg(st, reg, 2, reg_val);
444 }
445
ltc2992_read_gpio_alarm(struct ltc2992_state * st,int nr_gpio,u32 attr,long * val)446 static int ltc2992_read_gpio_alarm(struct ltc2992_state *st, int nr_gpio, u32 attr, long *val)
447 {
448 int reg_val;
449 u32 mask;
450
451 if (attr == hwmon_in_max_alarm)
452 mask = ltc2992_gpio_addr_map[nr_gpio].max_alarm_msk;
453 else
454 mask = ltc2992_gpio_addr_map[nr_gpio].min_alarm_msk;
455
456 reg_val = ltc2992_read_reg(st, ltc2992_gpio_addr_map[nr_gpio].alarm, 1);
457 if (reg_val < 0)
458 return reg_val;
459
460 *val = !!(reg_val & mask);
461 reg_val &= ~mask;
462
463 return ltc2992_write_reg(st, ltc2992_gpio_addr_map[nr_gpio].alarm, 1, reg_val);
464 }
465
ltc2992_read_gpios_in(struct device * dev,u32 attr,int nr_gpio,long * val)466 static int ltc2992_read_gpios_in(struct device *dev, u32 attr, int nr_gpio, long *val)
467 {
468 struct ltc2992_state *st = dev_get_drvdata(dev);
469 u32 reg;
470
471 switch (attr) {
472 case hwmon_in_input:
473 reg = ltc2992_gpio_addr_map[nr_gpio].data;
474 break;
475 case hwmon_in_lowest:
476 reg = ltc2992_gpio_addr_map[nr_gpio].min;
477 break;
478 case hwmon_in_highest:
479 reg = ltc2992_gpio_addr_map[nr_gpio].max;
480 break;
481 case hwmon_in_min:
482 reg = ltc2992_gpio_addr_map[nr_gpio].min_thresh;
483 break;
484 case hwmon_in_max:
485 reg = ltc2992_gpio_addr_map[nr_gpio].max_thresh;
486 break;
487 case hwmon_in_min_alarm:
488 case hwmon_in_max_alarm:
489 return ltc2992_read_gpio_alarm(st, nr_gpio, attr, val);
490 default:
491 return -EOPNOTSUPP;
492 }
493
494 return ltc2992_get_voltage(st, reg, LTC2992_VADC_GPIO_UV_LSB, val);
495 }
496
ltc2992_read_in_alarm(struct ltc2992_state * st,int channel,long * val,u32 attr)497 static int ltc2992_read_in_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
498 {
499 int reg_val;
500 u32 mask;
501
502 if (attr == hwmon_in_max_alarm)
503 mask = LTC2992_SENSE_FAULT_MSK(1);
504 else
505 mask = LTC2992_SENSE_FAULT_MSK(0);
506
507 reg_val = ltc2992_read_reg(st, LTC2992_SENSE_FAULT(channel), 1);
508 if (reg_val < 0)
509 return reg_val;
510
511 *val = !!(reg_val & mask);
512 reg_val &= ~mask;
513
514 return ltc2992_write_reg(st, LTC2992_SENSE_FAULT(channel), 1, reg_val);
515 }
516
ltc2992_read_in(struct device * dev,u32 attr,int channel,long * val)517 static int ltc2992_read_in(struct device *dev, u32 attr, int channel, long *val)
518 {
519 struct ltc2992_state *st = dev_get_drvdata(dev);
520 u32 reg;
521
522 if (channel > 1)
523 return ltc2992_read_gpios_in(dev, attr, channel - 2, val);
524
525 switch (attr) {
526 case hwmon_in_input:
527 reg = LTC2992_SENSE(channel);
528 break;
529 case hwmon_in_lowest:
530 reg = LTC2992_SENSE_MIN(channel);
531 break;
532 case hwmon_in_highest:
533 reg = LTC2992_SENSE_MAX(channel);
534 break;
535 case hwmon_in_min:
536 reg = LTC2992_SENSE_MIN_THRESH(channel);
537 break;
538 case hwmon_in_max:
539 reg = LTC2992_SENSE_MAX_THRESH(channel);
540 break;
541 case hwmon_in_min_alarm:
542 case hwmon_in_max_alarm:
543 return ltc2992_read_in_alarm(st, channel, val, attr);
544 default:
545 return -EOPNOTSUPP;
546 }
547
548 return ltc2992_get_voltage(st, reg, LTC2992_VADC_UV_LSB, val);
549 }
550
ltc2992_get_current(struct ltc2992_state * st,u32 reg,u32 channel,long * val)551 static int ltc2992_get_current(struct ltc2992_state *st, u32 reg, u32 channel, long *val)
552 {
553 int reg_val;
554
555 reg_val = ltc2992_read_reg(st, reg, 2);
556 if (reg_val < 0)
557 return reg_val;
558
559 reg_val = reg_val >> 4;
560 *val = DIV_ROUND_CLOSEST(reg_val * LTC2992_IADC_NANOV_LSB, st->r_sense_uohm[channel]);
561
562 return 0;
563 }
564
ltc2992_set_current(struct ltc2992_state * st,u32 reg,u32 channel,long val)565 static int ltc2992_set_current(struct ltc2992_state *st, u32 reg, u32 channel, long val)
566 {
567 u32 reg_val;
568 long cmax;
569
570 cmax = DIV_ROUND_CLOSEST_ULL(0xFFFULL * LTC2992_IADC_NANOV_LSB,
571 st->r_sense_uohm[channel]);
572 val = max(val, 0L);
573 val = min(val, cmax);
574 reg_val = min(DIV_ROUND_CLOSEST_ULL((u64)val * st->r_sense_uohm[channel],
575 LTC2992_IADC_NANOV_LSB),
576 0xFFFULL) << 4;
577
578 return ltc2992_write_reg(st, reg, 2, reg_val);
579 }
580
ltc2992_read_curr_alarm(struct ltc2992_state * st,int channel,long * val,u32 attr)581 static int ltc2992_read_curr_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
582 {
583 int reg_val;
584 u32 mask;
585
586 if (attr == hwmon_curr_max_alarm)
587 mask = LTC2992_DSENSE_FAULT_MSK(1);
588 else
589 mask = LTC2992_DSENSE_FAULT_MSK(0);
590
591 reg_val = ltc2992_read_reg(st, LTC2992_DSENSE_FAULT(channel), 1);
592 if (reg_val < 0)
593 return reg_val;
594
595 *val = !!(reg_val & mask);
596
597 reg_val &= ~mask;
598 return ltc2992_write_reg(st, LTC2992_DSENSE_FAULT(channel), 1, reg_val);
599 }
600
ltc2992_read_curr(struct device * dev,u32 attr,int channel,long * val)601 static int ltc2992_read_curr(struct device *dev, u32 attr, int channel, long *val)
602 {
603 struct ltc2992_state *st = dev_get_drvdata(dev);
604 u32 reg;
605
606 switch (attr) {
607 case hwmon_curr_input:
608 reg = LTC2992_DSENSE(channel);
609 break;
610 case hwmon_curr_lowest:
611 reg = LTC2992_DSENSE_MIN(channel);
612 break;
613 case hwmon_curr_highest:
614 reg = LTC2992_DSENSE_MAX(channel);
615 break;
616 case hwmon_curr_min:
617 reg = LTC2992_DSENSE_MIN_THRESH(channel);
618 break;
619 case hwmon_curr_max:
620 reg = LTC2992_DSENSE_MAX_THRESH(channel);
621 break;
622 case hwmon_curr_min_alarm:
623 case hwmon_curr_max_alarm:
624 return ltc2992_read_curr_alarm(st, channel, val, attr);
625 default:
626 return -EOPNOTSUPP;
627 }
628
629 return ltc2992_get_current(st, reg, channel, val);
630 }
631
ltc2992_get_power(struct ltc2992_state * st,u32 reg,u32 channel,long * val)632 static int ltc2992_get_power(struct ltc2992_state *st, u32 reg, u32 channel, long *val)
633 {
634 int reg_val;
635
636 reg_val = ltc2992_read_reg(st, reg, 3);
637 if (reg_val < 0)
638 return reg_val;
639
640 *val = mul_u64_u32_div(reg_val,
641 LTC2992_VADC_UV_LSB / 1000 *
642 LTC2992_IADC_NANOV_LSB,
643 st->r_sense_uohm[channel]);
644
645 return 0;
646 }
647
ltc2992_set_power(struct ltc2992_state * st,u32 reg,u32 channel,long val)648 static int ltc2992_set_power(struct ltc2992_state *st, u32 reg, u32 channel, long val)
649 {
650 u32 reg_val;
651 u64 pmax, uval;
652
653 uval = max(val, 0L);
654 pmax = mul_u64_u32_div(0xFFFFFFULL,
655 LTC2992_VADC_UV_LSB / 1000 *
656 LTC2992_IADC_NANOV_LSB,
657 st->r_sense_uohm[channel]);
658 uval = min(uval, pmax);
659 reg_val = min(mul_u64_u32_div(uval, st->r_sense_uohm[channel],
660 LTC2992_VADC_UV_LSB / 1000 *
661 LTC2992_IADC_NANOV_LSB),
662 0xFFFFFFULL);
663
664 return ltc2992_write_reg(st, reg, 3, reg_val);
665 }
666
ltc2992_read_power_alarm(struct ltc2992_state * st,int channel,long * val,u32 attr)667 static int ltc2992_read_power_alarm(struct ltc2992_state *st, int channel, long *val, u32 attr)
668 {
669 int reg_val;
670 u32 mask;
671
672 if (attr == hwmon_power_max_alarm)
673 mask = LTC2992_POWER_FAULT_MSK(1);
674 else
675 mask = LTC2992_POWER_FAULT_MSK(0);
676
677 reg_val = ltc2992_read_reg(st, LTC2992_POWER_FAULT(channel), 1);
678 if (reg_val < 0)
679 return reg_val;
680
681 *val = !!(reg_val & mask);
682 reg_val &= ~mask;
683
684 return ltc2992_write_reg(st, LTC2992_POWER_FAULT(channel), 1, reg_val);
685 }
686
ltc2992_read_power(struct device * dev,u32 attr,int channel,long * val)687 static int ltc2992_read_power(struct device *dev, u32 attr, int channel, long *val)
688 {
689 struct ltc2992_state *st = dev_get_drvdata(dev);
690 u32 reg;
691
692 switch (attr) {
693 case hwmon_power_input:
694 reg = LTC2992_POWER(channel);
695 break;
696 case hwmon_power_input_lowest:
697 reg = LTC2992_POWER_MIN(channel);
698 break;
699 case hwmon_power_input_highest:
700 reg = LTC2992_POWER_MAX(channel);
701 break;
702 case hwmon_power_min:
703 reg = LTC2992_POWER_MIN_THRESH(channel);
704 break;
705 case hwmon_power_max:
706 reg = LTC2992_POWER_MAX_THRESH(channel);
707 break;
708 case hwmon_power_min_alarm:
709 case hwmon_power_max_alarm:
710 return ltc2992_read_power_alarm(st, channel, val, attr);
711 default:
712 return -EOPNOTSUPP;
713 }
714
715 return ltc2992_get_power(st, reg, channel, val);
716 }
717
ltc2992_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)718 static int ltc2992_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel,
719 long *val)
720 {
721 switch (type) {
722 case hwmon_in:
723 return ltc2992_read_in(dev, attr, channel, val);
724 case hwmon_curr:
725 return ltc2992_read_curr(dev, attr, channel, val);
726 case hwmon_power:
727 return ltc2992_read_power(dev, attr, channel, val);
728 default:
729 return -EOPNOTSUPP;
730 }
731 }
732
ltc2992_write_curr(struct device * dev,u32 attr,int channel,long val)733 static int ltc2992_write_curr(struct device *dev, u32 attr, int channel, long val)
734 {
735 struct ltc2992_state *st = dev_get_drvdata(dev);
736 u32 reg;
737
738 switch (attr) {
739 case hwmon_curr_min:
740 reg = LTC2992_DSENSE_MIN_THRESH(channel);
741 break;
742 case hwmon_curr_max:
743 reg = LTC2992_DSENSE_MAX_THRESH(channel);
744 break;
745 default:
746 return -EOPNOTSUPP;
747 }
748
749 return ltc2992_set_current(st, reg, channel, val);
750 }
751
ltc2992_write_gpios_in(struct device * dev,u32 attr,int nr_gpio,long val)752 static int ltc2992_write_gpios_in(struct device *dev, u32 attr, int nr_gpio, long val)
753 {
754 struct ltc2992_state *st = dev_get_drvdata(dev);
755 u32 reg;
756
757 switch (attr) {
758 case hwmon_in_min:
759 reg = ltc2992_gpio_addr_map[nr_gpio].min_thresh;
760 break;
761 case hwmon_in_max:
762 reg = ltc2992_gpio_addr_map[nr_gpio].max_thresh;
763 break;
764 default:
765 return -EOPNOTSUPP;
766 }
767
768 return ltc2992_set_voltage(st, reg, LTC2992_VADC_GPIO_UV_LSB, val);
769 }
770
ltc2992_write_in(struct device * dev,u32 attr,int channel,long val)771 static int ltc2992_write_in(struct device *dev, u32 attr, int channel, long val)
772 {
773 struct ltc2992_state *st = dev_get_drvdata(dev);
774 u32 reg;
775
776 if (channel > 1)
777 return ltc2992_write_gpios_in(dev, attr, channel - 2, val);
778
779 switch (attr) {
780 case hwmon_in_min:
781 reg = LTC2992_SENSE_MIN_THRESH(channel);
782 break;
783 case hwmon_in_max:
784 reg = LTC2992_SENSE_MAX_THRESH(channel);
785 break;
786 default:
787 return -EOPNOTSUPP;
788 }
789
790 return ltc2992_set_voltage(st, reg, LTC2992_VADC_UV_LSB, val);
791 }
792
ltc2992_write_power(struct device * dev,u32 attr,int channel,long val)793 static int ltc2992_write_power(struct device *dev, u32 attr, int channel, long val)
794 {
795 struct ltc2992_state *st = dev_get_drvdata(dev);
796 u32 reg;
797
798 switch (attr) {
799 case hwmon_power_min:
800 reg = LTC2992_POWER_MIN_THRESH(channel);
801 break;
802 case hwmon_power_max:
803 reg = LTC2992_POWER_MAX_THRESH(channel);
804 break;
805 default:
806 return -EOPNOTSUPP;
807 }
808
809 return ltc2992_set_power(st, reg, channel, val);
810 }
811
ltc2992_write_chip(struct device * dev,u32 attr,int channel,long val)812 static int ltc2992_write_chip(struct device *dev, u32 attr, int channel, long val)
813 {
814 struct ltc2992_state *st = dev_get_drvdata(dev);
815
816 switch (attr) {
817 case hwmon_chip_in_reset_history:
818 return regmap_update_bits(st->regmap, LTC2992_CTRLB, LTC2992_RESET_HISTORY,
819 LTC2992_RESET_HISTORY);
820 default:
821 return -EOPNOTSUPP;
822 }
823 }
824
ltc2992_write(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long val)825 static int ltc2992_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel,
826 long val)
827 {
828 switch (type) {
829 case hwmon_chip:
830 return ltc2992_write_chip(dev, attr, channel, val);
831 case hwmon_in:
832 return ltc2992_write_in(dev, attr, channel, val);
833 case hwmon_curr:
834 return ltc2992_write_curr(dev, attr, channel, val);
835 case hwmon_power:
836 return ltc2992_write_power(dev, attr, channel, val);
837 default:
838 return -EOPNOTSUPP;
839 }
840 }
841
842 static const struct hwmon_ops ltc2992_hwmon_ops = {
843 .is_visible = ltc2992_is_visible,
844 .read = ltc2992_read,
845 .write = ltc2992_write,
846 };
847
848 static const struct hwmon_channel_info * const ltc2992_info[] = {
849 HWMON_CHANNEL_INFO(chip,
850 HWMON_C_IN_RESET_HISTORY),
851 HWMON_CHANNEL_INFO(in,
852 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
853 HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
854 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
855 HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
856 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
857 HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
858 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
859 HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
860 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
861 HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM,
862 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | HWMON_I_MIN |
863 HWMON_I_MAX | HWMON_I_MIN_ALARM | HWMON_I_MAX_ALARM),
864 HWMON_CHANNEL_INFO(curr,
865 HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | HWMON_C_MIN |
866 HWMON_C_MAX | HWMON_C_MIN_ALARM | HWMON_C_MAX_ALARM,
867 HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | HWMON_C_MIN |
868 HWMON_C_MAX | HWMON_C_MIN_ALARM | HWMON_C_MAX_ALARM),
869 HWMON_CHANNEL_INFO(power,
870 HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | HWMON_P_INPUT_HIGHEST |
871 HWMON_P_MIN | HWMON_P_MAX | HWMON_P_MIN_ALARM | HWMON_P_MAX_ALARM,
872 HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | HWMON_P_INPUT_HIGHEST |
873 HWMON_P_MIN | HWMON_P_MAX | HWMON_P_MIN_ALARM | HWMON_P_MAX_ALARM),
874 NULL
875 };
876
877 static const struct hwmon_chip_info ltc2992_chip_info = {
878 .ops = <c2992_hwmon_ops,
879 .info = ltc2992_info,
880 };
881
882 static const struct regmap_config ltc2992_regmap_config = {
883 .reg_bits = 8,
884 .val_bits = 8,
885 .max_register = 0xE8,
886 };
887
ltc2992_parse_dt(struct ltc2992_state * st)888 static int ltc2992_parse_dt(struct ltc2992_state *st)
889 {
890 u32 addr;
891 u32 val;
892 int ret;
893
894 device_for_each_child_node_scoped(&st->client->dev, child) {
895 ret = fwnode_property_read_u32(child, "reg", &addr);
896 if (ret < 0)
897 return ret;
898
899 if (addr > 1)
900 return -EINVAL;
901
902 ret = fwnode_property_read_u32(child, "shunt-resistor-micro-ohms", &val);
903 if (!ret) {
904 if (!val)
905 return dev_err_probe(&st->client->dev, -EINVAL,
906 "shunt resistor value cannot be zero\n");
907
908 st->r_sense_uohm[addr] = val;
909 }
910 }
911
912 return 0;
913 }
914
ltc2992_i2c_probe(struct i2c_client * client)915 static int ltc2992_i2c_probe(struct i2c_client *client)
916 {
917 struct device *hwmon_dev;
918 struct ltc2992_state *st;
919 int ret;
920
921 st = devm_kzalloc(&client->dev, sizeof(*st), GFP_KERNEL);
922 if (!st)
923 return -ENOMEM;
924
925 st->client = client;
926 st->regmap = devm_regmap_init_i2c(client, <c2992_regmap_config);
927 if (IS_ERR(st->regmap))
928 return PTR_ERR(st->regmap);
929
930 ret = ltc2992_parse_dt(st);
931 if (ret < 0)
932 return ret;
933
934 ret = ltc2992_config_gpio(st);
935 if (ret < 0)
936 return ret;
937
938 hwmon_dev = devm_hwmon_device_register_with_info(&client->dev, client->name, st,
939 <c2992_chip_info, NULL);
940
941 return PTR_ERR_OR_ZERO(hwmon_dev);
942 }
943
944 static const struct of_device_id ltc2992_of_match[] = {
945 { .compatible = "adi,ltc2992" },
946 { }
947 };
948 MODULE_DEVICE_TABLE(of, ltc2992_of_match);
949
950 static const struct i2c_device_id ltc2992_i2c_id[] = {
951 {"ltc2992"},
952 {}
953 };
954 MODULE_DEVICE_TABLE(i2c, ltc2992_i2c_id);
955
956 static struct i2c_driver ltc2992_i2c_driver = {
957 .driver = {
958 .name = "ltc2992",
959 .of_match_table = ltc2992_of_match,
960 },
961 .probe = ltc2992_i2c_probe,
962 .id_table = ltc2992_i2c_id,
963 };
964
965 module_i2c_driver(ltc2992_i2c_driver);
966
967 MODULE_AUTHOR("Alexandru Tachici <alexandru.tachici@analog.com>");
968 MODULE_DESCRIPTION("Hwmon driver for Linear Technology 2992");
969 MODULE_LICENSE("Dual BSD/GPL");
970