1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Freescale SCFG MSI(-X) support
4 *
5 * Copyright (C) 2016 Freescale Semiconductor.
6 *
7 * Author: Minghuan Lian <Minghuan.Lian@nxp.com>
8 */
9
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/msi.h>
13 #include <linux/interrupt.h>
14 #include <linux/iommu.h>
15 #include <linux/irq.h>
16 #include <linux/irqchip/chained_irq.h>
17 #include <linux/irqdomain.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_pci.h>
20 #include <linux/platform_device.h>
21 #include <linux/property.h>
22 #include <linux/spinlock.h>
23
24 #define MSI_IRQS_PER_MSIR 32
25 #define MSI_MSIR_OFFSET 4
26
27 #define MSI_LS1043V1_1_IRQS_PER_MSIR 8
28 #define MSI_LS1043V1_1_MSIR_OFFSET 0x10
29
30 struct ls_scfg_msi_cfg {
31 u32 ibs_shift; /* Shift of interrupt bit select */
32 u32 msir_irqs; /* The irq number per MSIR */
33 u32 msir_base; /* The base address of MSIR */
34 };
35
36 struct ls_scfg_msir {
37 struct ls_scfg_msi *msi_data;
38 unsigned int index;
39 unsigned int gic_irq;
40 unsigned int bit_start;
41 unsigned int bit_end;
42 unsigned int srs; /* Shared interrupt register select */
43 void __iomem *reg;
44 };
45
46 struct ls_scfg_msi {
47 spinlock_t lock;
48 struct platform_device *pdev;
49 struct irq_domain *parent;
50 struct irq_domain *msi_domain;
51 void __iomem *regs;
52 phys_addr_t msiir_addr;
53 struct ls_scfg_msi_cfg *cfg;
54 u32 msir_num;
55 struct ls_scfg_msir *msir;
56 u32 irqs_num;
57 unsigned long *used;
58 };
59
60 static struct irq_chip ls_scfg_msi_irq_chip = {
61 .name = "MSI",
62 .irq_mask = pci_msi_mask_irq,
63 .irq_unmask = pci_msi_unmask_irq,
64 };
65
66 static struct msi_domain_info ls_scfg_msi_domain_info = {
67 .flags = (MSI_FLAG_USE_DEF_DOM_OPS |
68 MSI_FLAG_USE_DEF_CHIP_OPS |
69 MSI_FLAG_PCI_MSIX),
70 .chip = &ls_scfg_msi_irq_chip,
71 };
72
73 static int msi_affinity_flag = 1;
74
early_parse_ls_scfg_msi(char * p)75 static int __init early_parse_ls_scfg_msi(char *p)
76 {
77 if (p && strncmp(p, "no-affinity", 11) == 0)
78 msi_affinity_flag = 0;
79 else
80 msi_affinity_flag = 1;
81
82 return 0;
83 }
84 early_param("lsmsi", early_parse_ls_scfg_msi);
85
ls_scfg_msi_compose_msg(struct irq_data * data,struct msi_msg * msg)86 static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
87 {
88 struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data);
89
90 msg->data = data->hwirq;
91
92 if (msi_affinity_flag) {
93 const struct cpumask *mask;
94
95 mask = irq_data_get_effective_affinity_mask(data);
96 msg->data |= cpumask_first(mask);
97 }
98
99 msi_msg_set_addr(irq_data_get_msi_desc(data), msg,
100 msi_data->msiir_addr);
101 }
102
ls_scfg_msi_set_affinity(struct irq_data * irq_data,const struct cpumask * mask,bool force)103 static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
104 const struct cpumask *mask, bool force)
105 {
106 struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(irq_data);
107 u32 cpu;
108
109 if (!msi_affinity_flag)
110 return -EINVAL;
111
112 if (!force)
113 cpu = cpumask_any_and(mask, cpu_online_mask);
114 else
115 cpu = cpumask_first(mask);
116
117 if (cpu >= msi_data->msir_num)
118 return -EINVAL;
119
120 if (msi_data->msir[cpu].gic_irq <= 0) {
121 pr_warn("cannot bind the irq to cpu%d\n", cpu);
122 return -EINVAL;
123 }
124
125 irq_data_update_effective_affinity(irq_data, cpumask_of(cpu));
126
127 return IRQ_SET_MASK_OK;
128 }
129
130 static struct irq_chip ls_scfg_msi_parent_chip = {
131 .name = "SCFG",
132 .irq_compose_msi_msg = ls_scfg_msi_compose_msg,
133 .irq_set_affinity = ls_scfg_msi_set_affinity,
134 };
135
ls_scfg_msi_domain_irq_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * args)136 static int ls_scfg_msi_domain_irq_alloc(struct irq_domain *domain,
137 unsigned int virq,
138 unsigned int nr_irqs,
139 void *args)
140 {
141 msi_alloc_info_t *info = args;
142 struct ls_scfg_msi *msi_data = domain->host_data;
143 int pos, err = 0;
144
145 WARN_ON(nr_irqs != 1);
146
147 spin_lock(&msi_data->lock);
148 pos = find_first_zero_bit(msi_data->used, msi_data->irqs_num);
149 if (pos < msi_data->irqs_num)
150 __set_bit(pos, msi_data->used);
151 else
152 err = -ENOSPC;
153 spin_unlock(&msi_data->lock);
154
155 if (err)
156 return err;
157
158 err = iommu_dma_prepare_msi(info->desc, msi_data->msiir_addr);
159 if (err)
160 return err;
161
162 irq_domain_set_info(domain, virq, pos,
163 &ls_scfg_msi_parent_chip, msi_data,
164 handle_simple_irq, NULL, NULL);
165
166 return 0;
167 }
168
ls_scfg_msi_domain_irq_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)169 static void ls_scfg_msi_domain_irq_free(struct irq_domain *domain,
170 unsigned int virq, unsigned int nr_irqs)
171 {
172 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
173 struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(d);
174 int pos;
175
176 pos = d->hwirq;
177 if (pos < 0 || pos >= msi_data->irqs_num) {
178 pr_err("failed to teardown msi. Invalid hwirq %d\n", pos);
179 return;
180 }
181
182 spin_lock(&msi_data->lock);
183 __clear_bit(pos, msi_data->used);
184 spin_unlock(&msi_data->lock);
185 }
186
187 static const struct irq_domain_ops ls_scfg_msi_domain_ops = {
188 .alloc = ls_scfg_msi_domain_irq_alloc,
189 .free = ls_scfg_msi_domain_irq_free,
190 };
191
ls_scfg_msi_irq_handler(struct irq_desc * desc)192 static void ls_scfg_msi_irq_handler(struct irq_desc *desc)
193 {
194 struct ls_scfg_msir *msir = irq_desc_get_handler_data(desc);
195 struct ls_scfg_msi *msi_data = msir->msi_data;
196 unsigned long val;
197 int pos, size, hwirq;
198
199 chained_irq_enter(irq_desc_get_chip(desc), desc);
200
201 val = ioread32be(msir->reg);
202
203 pos = msir->bit_start;
204 size = msir->bit_end + 1;
205
206 for_each_set_bit_from(pos, &val, size) {
207 hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) |
208 msir->srs;
209 generic_handle_domain_irq(msi_data->parent, hwirq);
210 }
211
212 chained_irq_exit(irq_desc_get_chip(desc), desc);
213 }
214
ls_scfg_msi_domains_init(struct ls_scfg_msi * msi_data)215 static int ls_scfg_msi_domains_init(struct ls_scfg_msi *msi_data)
216 {
217 /* Initialize MSI domain parent */
218 msi_data->parent = irq_domain_create_linear(NULL,
219 msi_data->irqs_num,
220 &ls_scfg_msi_domain_ops,
221 msi_data);
222 if (!msi_data->parent) {
223 dev_err(&msi_data->pdev->dev, "failed to create IRQ domain\n");
224 return -ENOMEM;
225 }
226
227 msi_data->msi_domain = pci_msi_create_irq_domain(
228 of_fwnode_handle(msi_data->pdev->dev.of_node),
229 &ls_scfg_msi_domain_info,
230 msi_data->parent);
231 if (!msi_data->msi_domain) {
232 dev_err(&msi_data->pdev->dev, "failed to create MSI domain\n");
233 irq_domain_remove(msi_data->parent);
234 return -ENOMEM;
235 }
236
237 return 0;
238 }
239
ls_scfg_msi_setup_hwirq(struct ls_scfg_msi * msi_data,int index)240 static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int index)
241 {
242 struct ls_scfg_msir *msir;
243 int virq, i, hwirq;
244
245 virq = platform_get_irq(msi_data->pdev, index);
246 if (virq <= 0)
247 return -ENODEV;
248
249 msir = &msi_data->msir[index];
250 msir->index = index;
251 msir->msi_data = msi_data;
252 msir->gic_irq = virq;
253 msir->reg = msi_data->regs + msi_data->cfg->msir_base + 4 * index;
254
255 if (msi_data->cfg->msir_irqs == MSI_LS1043V1_1_IRQS_PER_MSIR) {
256 msir->bit_start = 32 - ((msir->index + 1) *
257 MSI_LS1043V1_1_IRQS_PER_MSIR);
258 msir->bit_end = msir->bit_start +
259 MSI_LS1043V1_1_IRQS_PER_MSIR - 1;
260 } else {
261 msir->bit_start = 0;
262 msir->bit_end = msi_data->cfg->msir_irqs - 1;
263 }
264
265 irq_set_chained_handler_and_data(msir->gic_irq,
266 ls_scfg_msi_irq_handler,
267 msir);
268
269 if (msi_affinity_flag) {
270 /* Associate MSIR interrupt to the cpu */
271 irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
272 msir->srs = 0; /* This value is determined by the CPU */
273 } else
274 msir->srs = index;
275
276 /* Release the hwirqs corresponding to this MSIR */
277 if (!msi_affinity_flag || msir->index == 0) {
278 for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
279 hwirq = i << msi_data->cfg->ibs_shift | msir->index;
280 bitmap_clear(msi_data->used, hwirq, 1);
281 }
282 }
283
284 return 0;
285 }
286
ls_scfg_msi_teardown_hwirq(struct ls_scfg_msir * msir)287 static int ls_scfg_msi_teardown_hwirq(struct ls_scfg_msir *msir)
288 {
289 struct ls_scfg_msi *msi_data = msir->msi_data;
290 int i, hwirq;
291
292 if (msir->gic_irq > 0)
293 irq_set_chained_handler_and_data(msir->gic_irq, NULL, NULL);
294
295 for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
296 hwirq = i << msi_data->cfg->ibs_shift | msir->index;
297 bitmap_set(msi_data->used, hwirq, 1);
298 }
299
300 return 0;
301 }
302
303 static struct ls_scfg_msi_cfg ls1021_msi_cfg = {
304 .ibs_shift = 3,
305 .msir_irqs = MSI_IRQS_PER_MSIR,
306 .msir_base = MSI_MSIR_OFFSET,
307 };
308
309 static struct ls_scfg_msi_cfg ls1046_msi_cfg = {
310 .ibs_shift = 2,
311 .msir_irqs = MSI_IRQS_PER_MSIR,
312 .msir_base = MSI_MSIR_OFFSET,
313 };
314
315 static struct ls_scfg_msi_cfg ls1043_v1_1_msi_cfg = {
316 .ibs_shift = 2,
317 .msir_irqs = MSI_LS1043V1_1_IRQS_PER_MSIR,
318 .msir_base = MSI_LS1043V1_1_MSIR_OFFSET,
319 };
320
321 static const struct of_device_id ls_scfg_msi_id[] = {
322 /* The following two misspelled compatibles are obsolete */
323 { .compatible = "fsl,1s1021a-msi", .data = &ls1021_msi_cfg},
324 { .compatible = "fsl,1s1043a-msi", .data = &ls1021_msi_cfg},
325
326 { .compatible = "fsl,ls1012a-msi", .data = &ls1021_msi_cfg },
327 { .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg },
328 { .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg },
329 { .compatible = "fsl,ls1043a-v1.1-msi", .data = &ls1043_v1_1_msi_cfg },
330 { .compatible = "fsl,ls1046a-msi", .data = &ls1046_msi_cfg },
331 {},
332 };
333 MODULE_DEVICE_TABLE(of, ls_scfg_msi_id);
334
ls_scfg_msi_probe(struct platform_device * pdev)335 static int ls_scfg_msi_probe(struct platform_device *pdev)
336 {
337 struct ls_scfg_msi *msi_data;
338 struct resource *res;
339 int i, ret;
340
341 msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL);
342 if (!msi_data)
343 return -ENOMEM;
344
345 msi_data->cfg = (struct ls_scfg_msi_cfg *)device_get_match_data(&pdev->dev);
346 if (!msi_data->cfg)
347 return -ENODEV;
348
349 msi_data->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
350 if (IS_ERR(msi_data->regs)) {
351 dev_err(&pdev->dev, "failed to initialize 'regs'\n");
352 return PTR_ERR(msi_data->regs);
353 }
354 msi_data->msiir_addr = res->start;
355
356 msi_data->pdev = pdev;
357 spin_lock_init(&msi_data->lock);
358
359 msi_data->irqs_num = MSI_IRQS_PER_MSIR *
360 (1 << msi_data->cfg->ibs_shift);
361 msi_data->used = devm_bitmap_zalloc(&pdev->dev, msi_data->irqs_num, GFP_KERNEL);
362 if (!msi_data->used)
363 return -ENOMEM;
364 /*
365 * Reserve all the hwirqs
366 * The available hwirqs will be released in ls1_msi_setup_hwirq()
367 */
368 bitmap_set(msi_data->used, 0, msi_data->irqs_num);
369
370 msi_data->msir_num = of_irq_count(pdev->dev.of_node);
371
372 if (msi_affinity_flag) {
373 u32 cpu_num;
374
375 cpu_num = num_possible_cpus();
376 if (msi_data->msir_num >= cpu_num)
377 msi_data->msir_num = cpu_num;
378 else
379 msi_affinity_flag = 0;
380 }
381
382 msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num,
383 sizeof(*msi_data->msir),
384 GFP_KERNEL);
385 if (!msi_data->msir)
386 return -ENOMEM;
387
388 for (i = 0; i < msi_data->msir_num; i++)
389 ls_scfg_msi_setup_hwirq(msi_data, i);
390
391 ret = ls_scfg_msi_domains_init(msi_data);
392 if (ret)
393 return ret;
394
395 platform_set_drvdata(pdev, msi_data);
396
397 return 0;
398 }
399
ls_scfg_msi_remove(struct platform_device * pdev)400 static void ls_scfg_msi_remove(struct platform_device *pdev)
401 {
402 struct ls_scfg_msi *msi_data = platform_get_drvdata(pdev);
403 int i;
404
405 for (i = 0; i < msi_data->msir_num; i++)
406 ls_scfg_msi_teardown_hwirq(&msi_data->msir[i]);
407
408 irq_domain_remove(msi_data->msi_domain);
409 irq_domain_remove(msi_data->parent);
410
411 platform_set_drvdata(pdev, NULL);
412 }
413
414 static struct platform_driver ls_scfg_msi_driver = {
415 .driver = {
416 .name = "ls-scfg-msi",
417 .of_match_table = ls_scfg_msi_id,
418 },
419 .probe = ls_scfg_msi_probe,
420 .remove = ls_scfg_msi_remove,
421 };
422
423 module_platform_driver(ls_scfg_msi_driver);
424
425 MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@nxp.com>");
426 MODULE_DESCRIPTION("Freescale Layerscape SCFG MSI controller driver");
427