1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * This driver supports the digital controls for the internal codec 4 * found in Allwinner's A33 SoCs. 5 * 6 * (C) Copyright 2010-2016 7 * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com> 8 * huangxin <huangxin@Reuuimllatech.com> 9 * Mylène Josserand <mylene.josserand@free-electrons.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/clk.h> 15 #include <linux/input.h> 16 #include <linux/io.h> 17 #include <linux/irq.h> 18 #include <linux/mutex.h> 19 #include <linux/of.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regmap.h> 22 #include <linux/log2.h> 23 24 #include <sound/jack.h> 25 #include <sound/pcm_params.h> 26 #include <sound/soc.h> 27 #include <sound/soc-dapm.h> 28 #include <sound/tlv.h> 29 30 #define SUN8I_SYSCLK_CTL 0x00c 31 #define SUN8I_SYSCLK_CTL_AIF1CLK_ENA 11 32 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL (0x2 << 8) 33 #define SUN8I_SYSCLK_CTL_AIF2CLK_ENA 7 34 #define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_PLL (0x2 << 4) 35 #define SUN8I_SYSCLK_CTL_SYSCLK_ENA 3 36 #define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0 37 #define SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK (0x0 << 0) 38 #define SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF2CLK (0x1 << 0) 39 #define SUN8I_MOD_CLK_ENA 0x010 40 #define SUN8I_MOD_CLK_ENA_AIF1 15 41 #define SUN8I_MOD_CLK_ENA_AIF2 14 42 #define SUN8I_MOD_CLK_ENA_AIF3 13 43 #define SUN8I_MOD_CLK_ENA_ADC 3 44 #define SUN8I_MOD_CLK_ENA_DAC 2 45 #define SUN8I_MOD_RST_CTL 0x014 46 #define SUN8I_MOD_RST_CTL_AIF1 15 47 #define SUN8I_MOD_RST_CTL_AIF2 14 48 #define SUN8I_MOD_RST_CTL_AIF3 13 49 #define SUN8I_MOD_RST_CTL_ADC 3 50 #define SUN8I_MOD_RST_CTL_DAC 2 51 #define SUN8I_SYS_SR_CTRL 0x018 52 #define SUN8I_SYS_SR_CTRL_AIF1_FS 12 53 #define SUN8I_SYS_SR_CTRL_AIF2_FS 8 54 #define SUN8I_AIF_CLK_CTRL(n) (0x040 * (1 + (n))) 55 #define SUN8I_AIF_CLK_CTRL_MSTR_MOD 15 56 #define SUN8I_AIF_CLK_CTRL_CLK_INV 13 57 #define SUN8I_AIF_CLK_CTRL_BCLK_DIV 9 58 #define SUN8I_AIF_CLK_CTRL_LRCK_DIV 6 59 #define SUN8I_AIF_CLK_CTRL_WORD_SIZ 4 60 #define SUN8I_AIF_CLK_CTRL_DATA_FMT 2 61 #define SUN8I_AIF1_ADCDAT_CTRL 0x044 62 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA 15 63 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA 14 64 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC 10 65 #define SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC 8 66 #define SUN8I_AIF1_DACDAT_CTRL 0x048 67 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15 68 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14 69 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC 10 70 #define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC 8 71 #define SUN8I_AIF1_MXR_SRC 0x04c 72 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L 15 73 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL 14 74 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL 13 75 #define SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR 12 76 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R 11 77 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR 10 78 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR 9 79 #define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL 8 80 #define SUN8I_AIF1_VOL_CTRL1 0x050 81 #define SUN8I_AIF1_VOL_CTRL1_AD0L_VOL 8 82 #define SUN8I_AIF1_VOL_CTRL1_AD0R_VOL 0 83 #define SUN8I_AIF1_VOL_CTRL3 0x058 84 #define SUN8I_AIF1_VOL_CTRL3_DA0L_VOL 8 85 #define SUN8I_AIF1_VOL_CTRL3_DA0R_VOL 0 86 #define SUN8I_AIF2_ADCDAT_CTRL 0x084 87 #define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_ENA 15 88 #define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_ENA 14 89 #define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_SRC 10 90 #define SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_SRC 8 91 #define SUN8I_AIF2_DACDAT_CTRL 0x088 92 #define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_ENA 15 93 #define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_ENA 14 94 #define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_SRC 10 95 #define SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_SRC 8 96 #define SUN8I_AIF2_MXR_SRC 0x08c 97 #define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA0L 15 98 #define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA1L 14 99 #define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF2DACR 13 100 #define SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_ADCL 12 101 #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA0R 11 102 #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA1R 10 103 #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF2DACL 9 104 #define SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_ADCR 8 105 #define SUN8I_AIF2_VOL_CTRL1 0x090 106 #define SUN8I_AIF2_VOL_CTRL1_ADCL_VOL 8 107 #define SUN8I_AIF2_VOL_CTRL1_ADCR_VOL 0 108 #define SUN8I_AIF2_VOL_CTRL2 0x098 109 #define SUN8I_AIF2_VOL_CTRL2_DACL_VOL 8 110 #define SUN8I_AIF2_VOL_CTRL2_DACR_VOL 0 111 #define SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_AIF1 (0x0 << 0) 112 #define SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_AIF2 (0x1 << 0) 113 #define SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_AIF1CLK (0x2 << 0) 114 #define SUN8I_AIF3_PATH_CTRL 0x0cc 115 #define SUN8I_AIF3_PATH_CTRL_AIF3_ADC_SRC 10 116 #define SUN8I_AIF3_PATH_CTRL_AIF2_DAC_SRC 8 117 #define SUN8I_AIF3_PATH_CTRL_AIF3_PINS_TRI 7 118 #define SUN8I_ADC_DIG_CTRL 0x100 119 #define SUN8I_ADC_DIG_CTRL_ENAD 15 120 #define SUN8I_ADC_DIG_CTRL_ADOUT_DTS 2 121 #define SUN8I_ADC_DIG_CTRL_ADOUT_DLY 1 122 #define SUN8I_ADC_VOL_CTRL 0x104 123 #define SUN8I_ADC_VOL_CTRL_ADCL_VOL 8 124 #define SUN8I_ADC_VOL_CTRL_ADCR_VOL 0 125 #define SUN8I_HMIC_CTRL1 0x110 126 #define SUN8I_HMIC_CTRL1_HMIC_M 12 127 #define SUN8I_HMIC_CTRL1_HMIC_N 8 128 #define SUN8I_HMIC_CTRL1_MDATA_THRESHOLD_DB 5 129 #define SUN8I_HMIC_CTRL1_JACK_OUT_IRQ_EN 4 130 #define SUN8I_HMIC_CTRL1_JACK_IN_IRQ_EN 3 131 #define SUN8I_HMIC_CTRL1_HMIC_DATA_IRQ_EN 0 132 #define SUN8I_HMIC_CTRL2 0x114 133 #define SUN8I_HMIC_CTRL2_HMIC_SAMPLE 14 134 #define SUN8I_HMIC_CTRL2_HMIC_MDATA_THRESHOLD 8 135 #define SUN8I_HMIC_CTRL2_HMIC_SF 6 136 #define SUN8I_HMIC_STS 0x118 137 #define SUN8I_HMIC_STS_MDATA_DISCARD 13 138 #define SUN8I_HMIC_STS_HMIC_DATA 8 139 #define SUN8I_HMIC_STS_JACK_OUT_IRQ_ST 4 140 #define SUN8I_HMIC_STS_JACK_IN_IRQ_ST 3 141 #define SUN8I_HMIC_STS_HMIC_DATA_IRQ_ST 0 142 #define SUN8I_DAC_DIG_CTRL 0x120 143 #define SUN8I_DAC_DIG_CTRL_ENDA 15 144 #define SUN8I_DAC_VOL_CTRL 0x124 145 #define SUN8I_DAC_VOL_CTRL_DACL_VOL 8 146 #define SUN8I_DAC_VOL_CTRL_DACR_VOL 0 147 #define SUN8I_DAC_MXR_SRC 0x130 148 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L 15 149 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L 14 150 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL 13 151 #define SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL 12 152 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R 11 153 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R 10 154 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR 9 155 #define SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR 8 156 157 #define SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK GENMASK(9, 8) 158 #define SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK GENMASK(5, 4) 159 #define SUN8I_SYS_SR_CTRL_AIF1_FS_MASK GENMASK(15, 12) 160 #define SUN8I_SYS_SR_CTRL_AIF2_FS_MASK GENMASK(11, 8) 161 #define SUN8I_AIF_CLK_CTRL_CLK_INV_MASK GENMASK(14, 13) 162 #define SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK GENMASK(12, 9) 163 #define SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK GENMASK(8, 6) 164 #define SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK GENMASK(5, 4) 165 #define SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK GENMASK(3, 2) 166 #define SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_MASK GENMASK(1, 0) 167 #define SUN8I_HMIC_CTRL1_HMIC_M_MASK GENMASK(15, 12) 168 #define SUN8I_HMIC_CTRL1_HMIC_N_MASK GENMASK(11, 8) 169 #define SUN8I_HMIC_CTRL1_MDATA_THRESHOLD_DB_MASK GENMASK(6, 5) 170 #define SUN8I_HMIC_CTRL2_HMIC_SAMPLE_MASK GENMASK(15, 14) 171 #define SUN8I_HMIC_CTRL2_HMIC_SF_MASK GENMASK(7, 6) 172 #define SUN8I_HMIC_STS_HMIC_DATA_MASK GENMASK(12, 8) 173 174 #define SUN8I_CODEC_BUTTONS (SND_JACK_BTN_0|\ 175 SND_JACK_BTN_1|\ 176 SND_JACK_BTN_2|\ 177 SND_JACK_BTN_3) 178 179 #define SUN8I_CODEC_PASSTHROUGH_SAMPLE_RATE 48000 180 181 #define SUN8I_CODEC_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 |\ 182 SNDRV_PCM_FMTBIT_S16_LE |\ 183 SNDRV_PCM_FMTBIT_S20_LE |\ 184 SNDRV_PCM_FMTBIT_S24_LE |\ 185 SNDRV_PCM_FMTBIT_S20_3LE|\ 186 SNDRV_PCM_FMTBIT_S24_3LE) 187 188 #define SUN8I_CODEC_PCM_RATES (SNDRV_PCM_RATE_8000_48000|\ 189 SNDRV_PCM_RATE_88200 |\ 190 SNDRV_PCM_RATE_96000 |\ 191 SNDRV_PCM_RATE_176400 |\ 192 SNDRV_PCM_RATE_192000 |\ 193 SNDRV_PCM_RATE_KNOT) 194 195 enum { 196 SUN8I_CODEC_AIF1, 197 SUN8I_CODEC_AIF2, 198 SUN8I_CODEC_AIF3, 199 SUN8I_CODEC_NAIFS 200 }; 201 202 struct sun8i_codec_aif { 203 unsigned int lrck_div_order; 204 unsigned int sample_rate; 205 unsigned int slots; 206 unsigned int slot_width; 207 unsigned int active_streams : 2; 208 unsigned int open_streams : 2; 209 }; 210 211 struct sun8i_codec_quirks { 212 bool bus_clock : 1; 213 bool jack_detection : 1; 214 bool legacy_widgets : 1; 215 bool lrck_inversion : 1; 216 }; 217 218 enum { 219 SUN8I_JACK_STATUS_DISCONNECTED, 220 SUN8I_JACK_STATUS_WAITING_HBIAS, 221 SUN8I_JACK_STATUS_CONNECTED, 222 }; 223 224 struct sun8i_codec { 225 struct snd_soc_component *component; 226 struct regmap *regmap; 227 struct clk *clk_bus; 228 struct clk *clk_module; 229 const struct sun8i_codec_quirks *quirks; 230 struct sun8i_codec_aif aifs[SUN8I_CODEC_NAIFS]; 231 struct snd_soc_jack *jack; 232 struct delayed_work jack_work; 233 int jack_irq; 234 int jack_status; 235 int jack_type; 236 int jack_last_sample; 237 ktime_t jack_hbias_ready; 238 struct mutex jack_mutex; 239 int last_hmic_irq; 240 unsigned int sysclk_rate; 241 int sysclk_refcnt; 242 }; 243 244 static struct snd_soc_dai_driver sun8i_codec_dais[]; 245 246 static int sun8i_codec_runtime_resume(struct device *dev) 247 { 248 struct sun8i_codec *scodec = dev_get_drvdata(dev); 249 int ret; 250 251 ret = clk_prepare_enable(scodec->clk_bus); 252 if (ret) { 253 dev_err(dev, "Failed to enable the bus clock\n"); 254 return ret; 255 } 256 257 regcache_cache_only(scodec->regmap, false); 258 259 ret = regcache_sync(scodec->regmap); 260 if (ret) { 261 dev_err(dev, "Failed to sync regmap cache\n"); 262 return ret; 263 } 264 265 return 0; 266 } 267 268 static int sun8i_codec_runtime_suspend(struct device *dev) 269 { 270 struct sun8i_codec *scodec = dev_get_drvdata(dev); 271 272 regcache_cache_only(scodec->regmap, true); 273 regcache_mark_dirty(scodec->regmap); 274 275 clk_disable_unprepare(scodec->clk_bus); 276 277 return 0; 278 } 279 280 static int sun8i_codec_get_hw_rate(unsigned int sample_rate) 281 { 282 switch (sample_rate) { 283 case 7350: 284 case 8000: 285 return 0x0; 286 case 11025: 287 return 0x1; 288 case 12000: 289 return 0x2; 290 case 14700: 291 case 16000: 292 return 0x3; 293 case 22050: 294 return 0x4; 295 case 24000: 296 return 0x5; 297 case 29400: 298 case 32000: 299 return 0x6; 300 case 44100: 301 return 0x7; 302 case 48000: 303 return 0x8; 304 case 88200: 305 case 96000: 306 return 0x9; 307 case 176400: 308 case 192000: 309 return 0xa; 310 default: 311 return -EINVAL; 312 } 313 } 314 315 static int sun8i_codec_update_sample_rate(struct sun8i_codec *scodec) 316 { 317 unsigned int max_rate = 0; 318 int hw_rate, i; 319 320 for (i = SUN8I_CODEC_AIF1; i < SUN8I_CODEC_NAIFS; ++i) { 321 struct sun8i_codec_aif *aif = &scodec->aifs[i]; 322 323 if (aif->active_streams) 324 max_rate = max(max_rate, aif->sample_rate); 325 } 326 327 /* Set the sample rate for ADC->DAC passthrough when no AIF is active. */ 328 if (!max_rate) 329 max_rate = SUN8I_CODEC_PASSTHROUGH_SAMPLE_RATE; 330 331 hw_rate = sun8i_codec_get_hw_rate(max_rate); 332 if (hw_rate < 0) 333 return hw_rate; 334 335 regmap_update_bits(scodec->regmap, SUN8I_SYS_SR_CTRL, 336 SUN8I_SYS_SR_CTRL_AIF1_FS_MASK, 337 hw_rate << SUN8I_SYS_SR_CTRL_AIF1_FS); 338 339 return 0; 340 } 341 342 static int sun8i_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 343 { 344 struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); 345 u32 dsp_format, format, invert, value; 346 347 /* clock masters */ 348 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 349 case SND_SOC_DAIFMT_CBC_CFC: /* Codec slave, DAI master */ 350 value = 0x1; 351 break; 352 case SND_SOC_DAIFMT_CBP_CFP: /* Codec Master, DAI slave */ 353 value = 0x0; 354 break; 355 default: 356 return -EINVAL; 357 } 358 359 if (dai->id == SUN8I_CODEC_AIF3) { 360 /* AIF3 only supports master mode. */ 361 if (value) 362 return -EINVAL; 363 364 /* Use the AIF2 BCLK and LRCK for AIF3. */ 365 regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id), 366 SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_MASK, 367 SUN8I_AIF3_CLK_CTRL_AIF3_CLK_SRC_AIF2); 368 } else { 369 regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id), 370 BIT(SUN8I_AIF_CLK_CTRL_MSTR_MOD), 371 value << SUN8I_AIF_CLK_CTRL_MSTR_MOD); 372 } 373 374 /* DAI format */ 375 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 376 case SND_SOC_DAIFMT_I2S: 377 format = 0x0; 378 break; 379 case SND_SOC_DAIFMT_LEFT_J: 380 format = 0x1; 381 break; 382 case SND_SOC_DAIFMT_RIGHT_J: 383 format = 0x2; 384 break; 385 case SND_SOC_DAIFMT_DSP_A: 386 format = 0x3; 387 dsp_format = 0x0; /* Set LRCK_INV to 0 */ 388 break; 389 case SND_SOC_DAIFMT_DSP_B: 390 format = 0x3; 391 dsp_format = 0x1; /* Set LRCK_INV to 1 */ 392 break; 393 default: 394 return -EINVAL; 395 } 396 397 if (dai->id == SUN8I_CODEC_AIF3) { 398 /* AIF3 only supports DSP mode. */ 399 if (format != 3) 400 return -EINVAL; 401 } else { 402 regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id), 403 SUN8I_AIF_CLK_CTRL_DATA_FMT_MASK, 404 format << SUN8I_AIF_CLK_CTRL_DATA_FMT); 405 } 406 407 /* clock inversion */ 408 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 409 case SND_SOC_DAIFMT_NB_NF: /* Normal */ 410 invert = 0x0; 411 break; 412 case SND_SOC_DAIFMT_NB_IF: /* Inverted LRCK */ 413 invert = 0x1; 414 break; 415 case SND_SOC_DAIFMT_IB_NF: /* Inverted BCLK */ 416 invert = 0x2; 417 break; 418 case SND_SOC_DAIFMT_IB_IF: /* Both inverted */ 419 invert = 0x3; 420 break; 421 default: 422 return -EINVAL; 423 } 424 425 if (format == 0x3) { 426 /* Inverted LRCK is not available in DSP mode. */ 427 if (invert & BIT(0)) 428 return -EINVAL; 429 430 /* Instead, the bit selects between DSP A/B formats. */ 431 invert |= dsp_format; 432 } else { 433 /* 434 * It appears that the DAI and the codec in the A33 SoC don't 435 * share the same polarity for the LRCK signal when they mean 436 * 'normal' and 'inverted' in the datasheet. 437 * 438 * Since the DAI here is our regular i2s driver that have been 439 * tested with way more codecs than just this one, it means 440 * that the codec probably gets it backward, and we have to 441 * invert the value here. 442 */ 443 invert ^= scodec->quirks->lrck_inversion; 444 } 445 446 regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id), 447 SUN8I_AIF_CLK_CTRL_CLK_INV_MASK, 448 invert << SUN8I_AIF_CLK_CTRL_CLK_INV); 449 450 return 0; 451 } 452 453 static int sun8i_codec_set_tdm_slot(struct snd_soc_dai *dai, 454 unsigned int tx_mask, unsigned int rx_mask, 455 int slots, int slot_width) 456 { 457 struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); 458 struct sun8i_codec_aif *aif = &scodec->aifs[dai->id]; 459 460 if (slot_width && !is_power_of_2(slot_width)) 461 return -EINVAL; 462 463 aif->slots = slots; 464 aif->slot_width = slot_width; 465 466 return 0; 467 } 468 469 static const unsigned int sun8i_codec_rates[] = { 470 7350, 8000, 11025, 12000, 14700, 16000, 22050, 24000, 471 29400, 32000, 44100, 48000, 88200, 96000, 176400, 192000, 472 }; 473 474 static const struct snd_pcm_hw_constraint_list sun8i_codec_all_rates = { 475 .list = sun8i_codec_rates, 476 .count = ARRAY_SIZE(sun8i_codec_rates), 477 }; 478 479 static const struct snd_pcm_hw_constraint_list sun8i_codec_22M_rates = { 480 .list = sun8i_codec_rates, 481 .count = ARRAY_SIZE(sun8i_codec_rates), 482 .mask = 0x5555, 483 }; 484 485 static const struct snd_pcm_hw_constraint_list sun8i_codec_24M_rates = { 486 .list = sun8i_codec_rates, 487 .count = ARRAY_SIZE(sun8i_codec_rates), 488 .mask = 0xaaaa, 489 }; 490 491 static int sun8i_codec_startup(struct snd_pcm_substream *substream, 492 struct snd_soc_dai *dai) 493 { 494 struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); 495 const struct snd_pcm_hw_constraint_list *list; 496 497 /* hw_constraints is not relevant for codec2codec DAIs. */ 498 if (dai->id != SUN8I_CODEC_AIF1) 499 return 0; 500 501 if (!scodec->sysclk_refcnt) 502 list = &sun8i_codec_all_rates; 503 else if (scodec->sysclk_rate == 22579200) 504 list = &sun8i_codec_22M_rates; 505 else if (scodec->sysclk_rate == 24576000) 506 list = &sun8i_codec_24M_rates; 507 else 508 return -EINVAL; 509 510 return snd_pcm_hw_constraint_list(substream->runtime, 0, 511 SNDRV_PCM_HW_PARAM_RATE, list); 512 } 513 514 struct sun8i_codec_clk_div { 515 u8 div; 516 u8 val; 517 }; 518 519 static const struct sun8i_codec_clk_div sun8i_codec_bclk_div[] = { 520 { .div = 1, .val = 0 }, 521 { .div = 2, .val = 1 }, 522 { .div = 4, .val = 2 }, 523 { .div = 6, .val = 3 }, 524 { .div = 8, .val = 4 }, 525 { .div = 12, .val = 5 }, 526 { .div = 16, .val = 6 }, 527 { .div = 24, .val = 7 }, 528 { .div = 32, .val = 8 }, 529 { .div = 48, .val = 9 }, 530 { .div = 64, .val = 10 }, 531 { .div = 96, .val = 11 }, 532 { .div = 128, .val = 12 }, 533 { .div = 192, .val = 13 }, 534 }; 535 536 static int sun8i_codec_get_bclk_div(unsigned int sysclk_rate, 537 unsigned int lrck_div_order, 538 unsigned int sample_rate) 539 { 540 unsigned int div = sysclk_rate / sample_rate >> lrck_div_order; 541 int i; 542 543 for (i = 0; i < ARRAY_SIZE(sun8i_codec_bclk_div); i++) { 544 const struct sun8i_codec_clk_div *bdiv = &sun8i_codec_bclk_div[i]; 545 546 if (bdiv->div == div) 547 return bdiv->val; 548 } 549 550 return -EINVAL; 551 } 552 553 static int sun8i_codec_get_lrck_div_order(unsigned int slots, 554 unsigned int slot_width) 555 { 556 unsigned int div = slots * slot_width; 557 558 if (div < 16 || div > 256) 559 return -EINVAL; 560 561 return order_base_2(div); 562 } 563 564 static unsigned int sun8i_codec_get_sysclk_rate(unsigned int sample_rate) 565 { 566 return (sample_rate % 4000) ? 22579200 : 24576000; 567 } 568 569 static int sun8i_codec_hw_params(struct snd_pcm_substream *substream, 570 struct snd_pcm_hw_params *params, 571 struct snd_soc_dai *dai) 572 { 573 struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); 574 struct sun8i_codec_aif *aif = &scodec->aifs[dai->id]; 575 unsigned int sample_rate = params_rate(params); 576 unsigned int slots = aif->slots ?: params_channels(params); 577 unsigned int slot_width = aif->slot_width ?: params_width(params); 578 unsigned int sysclk_rate = sun8i_codec_get_sysclk_rate(sample_rate); 579 int bclk_div, lrck_div_order, ret, word_size; 580 u32 clk_reg; 581 582 /* word size */ 583 switch (params_width(params)) { 584 case 8: 585 word_size = 0x0; 586 break; 587 case 16: 588 word_size = 0x1; 589 break; 590 case 20: 591 word_size = 0x2; 592 break; 593 case 24: 594 word_size = 0x3; 595 break; 596 default: 597 return -EINVAL; 598 } 599 600 regmap_update_bits(scodec->regmap, SUN8I_AIF_CLK_CTRL(dai->id), 601 SUN8I_AIF_CLK_CTRL_WORD_SIZ_MASK, 602 word_size << SUN8I_AIF_CLK_CTRL_WORD_SIZ); 603 604 /* LRCK divider (BCLK/LRCK ratio) */ 605 lrck_div_order = sun8i_codec_get_lrck_div_order(slots, slot_width); 606 if (lrck_div_order < 0) 607 return lrck_div_order; 608 609 if (dai->id == SUN8I_CODEC_AIF2 || dai->id == SUN8I_CODEC_AIF3) { 610 /* AIF2 and AIF3 share AIF2's BCLK and LRCK generation circuitry. */ 611 int partner = (SUN8I_CODEC_AIF2 + SUN8I_CODEC_AIF3) - dai->id; 612 const struct sun8i_codec_aif *partner_aif = &scodec->aifs[partner]; 613 const char *partner_name = sun8i_codec_dais[partner].name; 614 615 if (partner_aif->open_streams && 616 (lrck_div_order != partner_aif->lrck_div_order || 617 sample_rate != partner_aif->sample_rate)) { 618 dev_err(dai->dev, 619 "%s sample and bit rates must match %s when both are used\n", 620 dai->name, partner_name); 621 return -EBUSY; 622 } 623 624 clk_reg = SUN8I_AIF_CLK_CTRL(SUN8I_CODEC_AIF2); 625 } else { 626 clk_reg = SUN8I_AIF_CLK_CTRL(dai->id); 627 } 628 629 regmap_update_bits(scodec->regmap, clk_reg, 630 SUN8I_AIF_CLK_CTRL_LRCK_DIV_MASK, 631 (lrck_div_order - 4) << SUN8I_AIF_CLK_CTRL_LRCK_DIV); 632 633 /* BCLK divider (SYSCLK/BCLK ratio) */ 634 bclk_div = sun8i_codec_get_bclk_div(sysclk_rate, lrck_div_order, sample_rate); 635 if (bclk_div < 0) 636 return bclk_div; 637 638 regmap_update_bits(scodec->regmap, clk_reg, 639 SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK, 640 bclk_div << SUN8I_AIF_CLK_CTRL_BCLK_DIV); 641 642 /* 643 * SYSCLK rate 644 * 645 * Clock rate protection is reference counted; but hw_params may be 646 * called many times per substream, without matching calls to hw_free. 647 * Protect the clock rate once per AIF, on the first hw_params call 648 * for the first substream. clk_set_rate() will allow clock rate 649 * changes on subsequent calls if only one AIF has open streams. 650 */ 651 ret = (aif->open_streams ? clk_set_rate : clk_set_rate_exclusive)(scodec->clk_module, 652 sysclk_rate); 653 if (ret == -EBUSY) 654 dev_err(dai->dev, 655 "%s sample rate (%u Hz) conflicts with other audio streams\n", 656 dai->name, sample_rate); 657 if (ret < 0) 658 return ret; 659 660 if (!aif->open_streams) 661 scodec->sysclk_refcnt++; 662 scodec->sysclk_rate = sysclk_rate; 663 664 aif->lrck_div_order = lrck_div_order; 665 aif->sample_rate = sample_rate; 666 aif->open_streams |= BIT(substream->stream); 667 668 return sun8i_codec_update_sample_rate(scodec); 669 } 670 671 static int sun8i_codec_hw_free(struct snd_pcm_substream *substream, 672 struct snd_soc_dai *dai) 673 { 674 struct sun8i_codec *scodec = snd_soc_dai_get_drvdata(dai); 675 struct sun8i_codec_aif *aif = &scodec->aifs[dai->id]; 676 677 /* Drop references when the last substream for the AIF is freed. */ 678 if (aif->open_streams != BIT(substream->stream)) 679 goto done; 680 681 clk_rate_exclusive_put(scodec->clk_module); 682 scodec->sysclk_refcnt--; 683 aif->lrck_div_order = 0; 684 aif->sample_rate = 0; 685 686 done: 687 aif->open_streams &= ~BIT(substream->stream); 688 return 0; 689 } 690 691 static const u64 sun8i_codec_selectable_formats = 692 SND_SOC_POSSIBLE_DAIFMT_I2S | 693 SND_SOC_POSSIBLE_DAIFMT_RIGHT_J | 694 SND_SOC_POSSIBLE_DAIFMT_LEFT_J | 695 SND_SOC_POSSIBLE_DAIFMT_DSP_A | 696 SND_SOC_POSSIBLE_DAIFMT_DSP_B | 697 SND_SOC_POSSIBLE_DAIFMT_NB_NF | 698 SND_SOC_POSSIBLE_DAIFMT_NB_IF | 699 SND_SOC_POSSIBLE_DAIFMT_IB_NF | 700 SND_SOC_POSSIBLE_DAIFMT_IB_IF; 701 702 static const struct snd_soc_dai_ops sun8i_codec_dai_ops = { 703 .set_fmt = sun8i_codec_set_fmt, 704 .set_tdm_slot = sun8i_codec_set_tdm_slot, 705 .startup = sun8i_codec_startup, 706 .hw_params = sun8i_codec_hw_params, 707 .hw_free = sun8i_codec_hw_free, 708 .auto_selectable_formats = &sun8i_codec_selectable_formats, 709 .num_auto_selectable_formats = 1, 710 }; 711 712 static struct snd_soc_dai_driver sun8i_codec_dais[] = { 713 { 714 .name = "sun8i-codec-aif1", 715 .id = SUN8I_CODEC_AIF1, 716 .ops = &sun8i_codec_dai_ops, 717 /* capture capabilities */ 718 .capture = { 719 .stream_name = "AIF1 Capture", 720 .channels_min = 1, 721 .channels_max = 2, 722 .rates = SUN8I_CODEC_PCM_RATES, 723 .formats = SUN8I_CODEC_PCM_FORMATS, 724 .sig_bits = 24, 725 }, 726 /* playback capabilities */ 727 .playback = { 728 .stream_name = "AIF1 Playback", 729 .channels_min = 1, 730 .channels_max = 2, 731 .rates = SUN8I_CODEC_PCM_RATES, 732 .formats = SUN8I_CODEC_PCM_FORMATS, 733 }, 734 .symmetric_rate = true, 735 .symmetric_channels = true, 736 .symmetric_sample_bits = true, 737 }, 738 { 739 .name = "sun8i-codec-aif2", 740 .id = SUN8I_CODEC_AIF2, 741 .ops = &sun8i_codec_dai_ops, 742 /* capture capabilities */ 743 .capture = { 744 .stream_name = "AIF2 Capture", 745 .channels_min = 1, 746 .channels_max = 2, 747 .rates = SUN8I_CODEC_PCM_RATES, 748 .formats = SUN8I_CODEC_PCM_FORMATS, 749 .sig_bits = 24, 750 }, 751 /* playback capabilities */ 752 .playback = { 753 .stream_name = "AIF2 Playback", 754 .channels_min = 1, 755 .channels_max = 2, 756 .rates = SUN8I_CODEC_PCM_RATES, 757 .formats = SUN8I_CODEC_PCM_FORMATS, 758 }, 759 .symmetric_rate = true, 760 .symmetric_channels = true, 761 .symmetric_sample_bits = true, 762 }, 763 { 764 .name = "sun8i-codec-aif3", 765 .id = SUN8I_CODEC_AIF3, 766 .ops = &sun8i_codec_dai_ops, 767 /* capture capabilities */ 768 .capture = { 769 .stream_name = "AIF3 Capture", 770 .channels_min = 1, 771 .channels_max = 1, 772 .rates = SUN8I_CODEC_PCM_RATES, 773 .formats = SUN8I_CODEC_PCM_FORMATS, 774 .sig_bits = 24, 775 }, 776 /* playback capabilities */ 777 .playback = { 778 .stream_name = "AIF3 Playback", 779 .channels_min = 1, 780 .channels_max = 1, 781 .rates = SUN8I_CODEC_PCM_RATES, 782 .formats = SUN8I_CODEC_PCM_FORMATS, 783 }, 784 .symmetric_rate = true, 785 .symmetric_channels = true, 786 .symmetric_sample_bits = true, 787 }, 788 }; 789 790 static const DECLARE_TLV_DB_SCALE(sun8i_codec_vol_scale, -12000, 75, 1); 791 792 static const struct snd_kcontrol_new sun8i_codec_controls[] = { 793 SOC_DOUBLE_TLV("AIF1 AD0 Capture Volume", 794 SUN8I_AIF1_VOL_CTRL1, 795 SUN8I_AIF1_VOL_CTRL1_AD0L_VOL, 796 SUN8I_AIF1_VOL_CTRL1_AD0R_VOL, 797 0xc0, 0, sun8i_codec_vol_scale), 798 SOC_DOUBLE_TLV("AIF1 DA0 Playback Volume", 799 SUN8I_AIF1_VOL_CTRL3, 800 SUN8I_AIF1_VOL_CTRL3_DA0L_VOL, 801 SUN8I_AIF1_VOL_CTRL3_DA0R_VOL, 802 0xc0, 0, sun8i_codec_vol_scale), 803 SOC_DOUBLE_TLV("AIF2 ADC Capture Volume", 804 SUN8I_AIF2_VOL_CTRL1, 805 SUN8I_AIF2_VOL_CTRL1_ADCL_VOL, 806 SUN8I_AIF2_VOL_CTRL1_ADCR_VOL, 807 0xc0, 0, sun8i_codec_vol_scale), 808 SOC_DOUBLE_TLV("AIF2 DAC Playback Volume", 809 SUN8I_AIF2_VOL_CTRL2, 810 SUN8I_AIF2_VOL_CTRL2_DACL_VOL, 811 SUN8I_AIF2_VOL_CTRL2_DACR_VOL, 812 0xc0, 0, sun8i_codec_vol_scale), 813 SOC_DOUBLE_TLV("ADC Capture Volume", 814 SUN8I_ADC_VOL_CTRL, 815 SUN8I_ADC_VOL_CTRL_ADCL_VOL, 816 SUN8I_ADC_VOL_CTRL_ADCR_VOL, 817 0xc0, 0, sun8i_codec_vol_scale), 818 SOC_DOUBLE_TLV("DAC Playback Volume", 819 SUN8I_DAC_VOL_CTRL, 820 SUN8I_DAC_VOL_CTRL_DACL_VOL, 821 SUN8I_DAC_VOL_CTRL_DACR_VOL, 822 0xc0, 0, sun8i_codec_vol_scale), 823 }; 824 825 static int sun8i_codec_aif_event(struct snd_soc_dapm_widget *w, 826 struct snd_kcontrol *kcontrol, int event) 827 { 828 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 829 struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component); 830 struct sun8i_codec_aif *aif = &scodec->aifs[w->sname[3] - '1']; 831 int stream = w->id == snd_soc_dapm_aif_out; 832 833 if (SND_SOC_DAPM_EVENT_ON(event)) 834 aif->active_streams |= BIT(stream); 835 else 836 aif->active_streams &= ~BIT(stream); 837 838 return sun8i_codec_update_sample_rate(scodec); 839 } 840 841 static const char *const sun8i_aif_stereo_mux_enum_values[] = { 842 "Stereo", "Reverse Stereo", "Sum Mono", "Mix Mono" 843 }; 844 845 static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_ad0_stereo_mux_enum, 846 SUN8I_AIF1_ADCDAT_CTRL, 847 SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_SRC, 848 SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_SRC, 849 sun8i_aif_stereo_mux_enum_values); 850 851 static const struct snd_kcontrol_new sun8i_aif1_ad0_stereo_mux_control = 852 SOC_DAPM_ENUM("AIF1 AD0 Stereo Capture Route", 853 sun8i_aif1_ad0_stereo_mux_enum); 854 855 static SOC_ENUM_DOUBLE_DECL(sun8i_aif2_adc_stereo_mux_enum, 856 SUN8I_AIF2_ADCDAT_CTRL, 857 SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_SRC, 858 SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_SRC, 859 sun8i_aif_stereo_mux_enum_values); 860 861 static const struct snd_kcontrol_new sun8i_aif2_adc_stereo_mux_control = 862 SOC_DAPM_ENUM("AIF2 ADC Stereo Capture Route", 863 sun8i_aif2_adc_stereo_mux_enum); 864 865 static const char *const sun8i_aif3_adc_mux_enum_values[] = { 866 "None", "AIF2 ADCL", "AIF2 ADCR" 867 }; 868 869 static SOC_ENUM_SINGLE_DECL(sun8i_aif3_adc_mux_enum, 870 SUN8I_AIF3_PATH_CTRL, 871 SUN8I_AIF3_PATH_CTRL_AIF3_ADC_SRC, 872 sun8i_aif3_adc_mux_enum_values); 873 874 static const struct snd_kcontrol_new sun8i_aif3_adc_mux_control = 875 SOC_DAPM_ENUM("AIF3 ADC Source Capture Route", 876 sun8i_aif3_adc_mux_enum); 877 878 static const struct snd_kcontrol_new sun8i_aif1_ad0_mixer_controls[] = { 879 SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch", 880 SUN8I_AIF1_MXR_SRC, 881 SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF1DA0L, 882 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0), 883 SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch", 884 SUN8I_AIF1_MXR_SRC, 885 SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACL, 886 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR, 1, 0), 887 SOC_DAPM_DOUBLE("AIF1 Data Digital ADC Capture Switch", 888 SUN8I_AIF1_MXR_SRC, 889 SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_ADCL, 890 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0), 891 SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch", 892 SUN8I_AIF1_MXR_SRC, 893 SUN8I_AIF1_MXR_SRC_AD0L_MXR_SRC_AIF2DACR, 894 SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0), 895 }; 896 897 static const struct snd_kcontrol_new sun8i_aif2_adc_mixer_controls[] = { 898 SOC_DAPM_DOUBLE("AIF2 ADC Mixer AIF1 DA0 Capture Switch", 899 SUN8I_AIF2_MXR_SRC, 900 SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA0L, 901 SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA0R, 1, 0), 902 SOC_DAPM_DOUBLE("AIF2 ADC Mixer AIF1 DA1 Capture Switch", 903 SUN8I_AIF2_MXR_SRC, 904 SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF1DA1L, 905 SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF1DA1R, 1, 0), 906 SOC_DAPM_DOUBLE("AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", 907 SUN8I_AIF2_MXR_SRC, 908 SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_AIF2DACR, 909 SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_AIF2DACL, 1, 0), 910 SOC_DAPM_DOUBLE("AIF2 ADC Mixer ADC Capture Switch", 911 SUN8I_AIF2_MXR_SRC, 912 SUN8I_AIF2_MXR_SRC_ADCL_MXR_SRC_ADCL, 913 SUN8I_AIF2_MXR_SRC_ADCR_MXR_SRC_ADCR, 1, 0), 914 }; 915 916 static const char *const sun8i_aif2_dac_mux_enum_values[] = { 917 "AIF2", "AIF3+2", "AIF2+3" 918 }; 919 920 static SOC_ENUM_SINGLE_DECL(sun8i_aif2_dac_mux_enum, 921 SUN8I_AIF3_PATH_CTRL, 922 SUN8I_AIF3_PATH_CTRL_AIF2_DAC_SRC, 923 sun8i_aif2_dac_mux_enum_values); 924 925 static const struct snd_kcontrol_new sun8i_aif2_dac_mux_control = 926 SOC_DAPM_ENUM("AIF2 DAC Source Playback Route", 927 sun8i_aif2_dac_mux_enum); 928 929 static SOC_ENUM_DOUBLE_DECL(sun8i_aif1_da0_stereo_mux_enum, 930 SUN8I_AIF1_DACDAT_CTRL, 931 SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_SRC, 932 SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_SRC, 933 sun8i_aif_stereo_mux_enum_values); 934 935 static const struct snd_kcontrol_new sun8i_aif1_da0_stereo_mux_control = 936 SOC_DAPM_ENUM("AIF1 DA0 Stereo Playback Route", 937 sun8i_aif1_da0_stereo_mux_enum); 938 939 static SOC_ENUM_DOUBLE_DECL(sun8i_aif2_dac_stereo_mux_enum, 940 SUN8I_AIF2_DACDAT_CTRL, 941 SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_SRC, 942 SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_SRC, 943 sun8i_aif_stereo_mux_enum_values); 944 945 static const struct snd_kcontrol_new sun8i_aif2_dac_stereo_mux_control = 946 SOC_DAPM_ENUM("AIF2 DAC Stereo Playback Route", 947 sun8i_aif2_dac_stereo_mux_enum); 948 949 static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = { 950 SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital DAC Playback Switch", 951 SUN8I_DAC_MXR_SRC, 952 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA0L, 953 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA0R, 1, 0), 954 SOC_DAPM_DOUBLE("AIF1 Slot 1 Digital DAC Playback Switch", 955 SUN8I_DAC_MXR_SRC, 956 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF1DA1L, 957 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF1DA1R, 1, 0), 958 SOC_DAPM_DOUBLE("AIF2 Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, 959 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_AIF2DACL, 960 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_AIF2DACR, 1, 0), 961 SOC_DAPM_DOUBLE("ADC Digital DAC Playback Switch", SUN8I_DAC_MXR_SRC, 962 SUN8I_DAC_MXR_SRC_DACL_MXR_SRC_ADCL, 963 SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0), 964 }; 965 966 static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = { 967 /* System Clocks */ 968 SND_SOC_DAPM_CLOCK_SUPPLY("mod"), 969 970 SND_SOC_DAPM_SUPPLY("AIF1CLK", 971 SUN8I_SYSCLK_CTL, 972 SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0), 973 SND_SOC_DAPM_SUPPLY("AIF2CLK", 974 SUN8I_SYSCLK_CTL, 975 SUN8I_SYSCLK_CTL_AIF2CLK_ENA, 0, NULL, 0), 976 SND_SOC_DAPM_SUPPLY("SYSCLK", 977 SUN8I_SYSCLK_CTL, 978 SUN8I_SYSCLK_CTL_SYSCLK_ENA, 0, NULL, 0), 979 980 /* Module Clocks */ 981 SND_SOC_DAPM_SUPPLY("CLK AIF1", 982 SUN8I_MOD_CLK_ENA, 983 SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0), 984 SND_SOC_DAPM_SUPPLY("CLK AIF2", 985 SUN8I_MOD_CLK_ENA, 986 SUN8I_MOD_CLK_ENA_AIF2, 0, NULL, 0), 987 SND_SOC_DAPM_SUPPLY("CLK AIF3", 988 SUN8I_MOD_CLK_ENA, 989 SUN8I_MOD_CLK_ENA_AIF3, 0, NULL, 0), 990 SND_SOC_DAPM_SUPPLY("CLK ADC", 991 SUN8I_MOD_CLK_ENA, 992 SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0), 993 SND_SOC_DAPM_SUPPLY("CLK DAC", 994 SUN8I_MOD_CLK_ENA, 995 SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0), 996 997 /* Module Resets */ 998 SND_SOC_DAPM_SUPPLY("RST AIF1", 999 SUN8I_MOD_RST_CTL, 1000 SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0), 1001 SND_SOC_DAPM_SUPPLY("RST AIF2", 1002 SUN8I_MOD_RST_CTL, 1003 SUN8I_MOD_RST_CTL_AIF2, 0, NULL, 0), 1004 SND_SOC_DAPM_SUPPLY("RST AIF3", 1005 SUN8I_MOD_RST_CTL, 1006 SUN8I_MOD_RST_CTL_AIF3, 0, NULL, 0), 1007 SND_SOC_DAPM_SUPPLY("RST ADC", 1008 SUN8I_MOD_RST_CTL, 1009 SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0), 1010 SND_SOC_DAPM_SUPPLY("RST DAC", 1011 SUN8I_MOD_RST_CTL, 1012 SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0), 1013 1014 /* Module Supplies */ 1015 SND_SOC_DAPM_SUPPLY("ADC", 1016 SUN8I_ADC_DIG_CTRL, 1017 SUN8I_ADC_DIG_CTRL_ENAD, 0, NULL, 0), 1018 SND_SOC_DAPM_SUPPLY("DAC", 1019 SUN8I_DAC_DIG_CTRL, 1020 SUN8I_DAC_DIG_CTRL_ENDA, 0, NULL, 0), 1021 1022 /* AIF "ADC" Outputs */ 1023 SND_SOC_DAPM_AIF_OUT_E("AIF1 AD0L", "AIF1 Capture", 0, 1024 SUN8I_AIF1_ADCDAT_CTRL, 1025 SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0L_ENA, 0, 1026 sun8i_codec_aif_event, 1027 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1028 SND_SOC_DAPM_AIF_OUT("AIF1 AD0R", "AIF1 Capture", 1, 1029 SUN8I_AIF1_ADCDAT_CTRL, 1030 SUN8I_AIF1_ADCDAT_CTRL_AIF1_AD0R_ENA, 0), 1031 1032 SND_SOC_DAPM_AIF_OUT_E("AIF2 ADCL", "AIF2 Capture", 0, 1033 SUN8I_AIF2_ADCDAT_CTRL, 1034 SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCL_ENA, 0, 1035 sun8i_codec_aif_event, 1036 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1037 SND_SOC_DAPM_AIF_OUT("AIF2 ADCR", "AIF2 Capture", 1, 1038 SUN8I_AIF2_ADCDAT_CTRL, 1039 SUN8I_AIF2_ADCDAT_CTRL_AIF2_ADCR_ENA, 0), 1040 1041 SND_SOC_DAPM_AIF_OUT_E("AIF3 ADC", "AIF3 Capture", 0, 1042 SND_SOC_NOPM, 0, 0, 1043 sun8i_codec_aif_event, 1044 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1045 1046 /* AIF "ADC" Mono/Stereo Muxes */ 1047 SND_SOC_DAPM_MUX("AIF1 AD0L Stereo Mux", SND_SOC_NOPM, 0, 0, 1048 &sun8i_aif1_ad0_stereo_mux_control), 1049 SND_SOC_DAPM_MUX("AIF1 AD0R Stereo Mux", SND_SOC_NOPM, 0, 0, 1050 &sun8i_aif1_ad0_stereo_mux_control), 1051 1052 SND_SOC_DAPM_MUX("AIF2 ADCL Stereo Mux", SND_SOC_NOPM, 0, 0, 1053 &sun8i_aif2_adc_stereo_mux_control), 1054 SND_SOC_DAPM_MUX("AIF2 ADCR Stereo Mux", SND_SOC_NOPM, 0, 0, 1055 &sun8i_aif2_adc_stereo_mux_control), 1056 1057 /* AIF "ADC" Output Muxes */ 1058 SND_SOC_DAPM_MUX("AIF3 ADC Source Capture Route", SND_SOC_NOPM, 0, 0, 1059 &sun8i_aif3_adc_mux_control), 1060 1061 /* AIF "ADC" Mixers */ 1062 SOC_MIXER_ARRAY("AIF1 AD0L Mixer", SND_SOC_NOPM, 0, 0, 1063 sun8i_aif1_ad0_mixer_controls), 1064 SOC_MIXER_ARRAY("AIF1 AD0R Mixer", SND_SOC_NOPM, 0, 0, 1065 sun8i_aif1_ad0_mixer_controls), 1066 1067 SOC_MIXER_ARRAY("AIF2 ADCL Mixer", SND_SOC_NOPM, 0, 0, 1068 sun8i_aif2_adc_mixer_controls), 1069 SOC_MIXER_ARRAY("AIF2 ADCR Mixer", SND_SOC_NOPM, 0, 0, 1070 sun8i_aif2_adc_mixer_controls), 1071 1072 /* AIF "DAC" Input Muxes */ 1073 SND_SOC_DAPM_MUX("AIF2 DACL Source", SND_SOC_NOPM, 0, 0, 1074 &sun8i_aif2_dac_mux_control), 1075 SND_SOC_DAPM_MUX("AIF2 DACR Source", SND_SOC_NOPM, 0, 0, 1076 &sun8i_aif2_dac_mux_control), 1077 1078 /* AIF "DAC" Mono/Stereo Muxes */ 1079 SND_SOC_DAPM_MUX("AIF1 DA0L Stereo Mux", SND_SOC_NOPM, 0, 0, 1080 &sun8i_aif1_da0_stereo_mux_control), 1081 SND_SOC_DAPM_MUX("AIF1 DA0R Stereo Mux", SND_SOC_NOPM, 0, 0, 1082 &sun8i_aif1_da0_stereo_mux_control), 1083 1084 SND_SOC_DAPM_MUX("AIF2 DACL Stereo Mux", SND_SOC_NOPM, 0, 0, 1085 &sun8i_aif2_dac_stereo_mux_control), 1086 SND_SOC_DAPM_MUX("AIF2 DACR Stereo Mux", SND_SOC_NOPM, 0, 0, 1087 &sun8i_aif2_dac_stereo_mux_control), 1088 1089 /* AIF "DAC" Inputs */ 1090 SND_SOC_DAPM_AIF_IN_E("AIF1 DA0L", "AIF1 Playback", 0, 1091 SUN8I_AIF1_DACDAT_CTRL, 1092 SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA, 0, 1093 sun8i_codec_aif_event, 1094 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1095 SND_SOC_DAPM_AIF_IN("AIF1 DA0R", "AIF1 Playback", 1, 1096 SUN8I_AIF1_DACDAT_CTRL, 1097 SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0), 1098 1099 SND_SOC_DAPM_AIF_IN_E("AIF2 DACL", "AIF2 Playback", 0, 1100 SUN8I_AIF2_DACDAT_CTRL, 1101 SUN8I_AIF2_DACDAT_CTRL_AIF2_DACL_ENA, 0, 1102 sun8i_codec_aif_event, 1103 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1104 SND_SOC_DAPM_AIF_IN("AIF2 DACR", "AIF2 Playback", 1, 1105 SUN8I_AIF2_DACDAT_CTRL, 1106 SUN8I_AIF2_DACDAT_CTRL_AIF2_DACR_ENA, 0), 1107 1108 SND_SOC_DAPM_AIF_IN_E("AIF3 DAC", "AIF3 Playback", 0, 1109 SND_SOC_NOPM, 0, 0, 1110 sun8i_codec_aif_event, 1111 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1112 1113 /* ADC Inputs (connected to analog codec DAPM context) */ 1114 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 0, 0), 1115 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0), 1116 1117 /* DAC Outputs (connected to analog codec DAPM context) */ 1118 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), 1119 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), 1120 1121 /* DAC Mixers */ 1122 SOC_MIXER_ARRAY("DACL Mixer", SND_SOC_NOPM, 0, 0, 1123 sun8i_dac_mixer_controls), 1124 SOC_MIXER_ARRAY("DACR Mixer", SND_SOC_NOPM, 0, 0, 1125 sun8i_dac_mixer_controls), 1126 }; 1127 1128 static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = { 1129 /* Clock Routes */ 1130 { "AIF1CLK", NULL, "mod" }, 1131 1132 { "SYSCLK", NULL, "AIF1CLK" }, 1133 1134 { "CLK AIF1", NULL, "AIF1CLK" }, 1135 { "CLK AIF1", NULL, "SYSCLK" }, 1136 { "RST AIF1", NULL, "CLK AIF1" }, 1137 { "AIF1 AD0L", NULL, "RST AIF1" }, 1138 { "AIF1 AD0R", NULL, "RST AIF1" }, 1139 { "AIF1 DA0L", NULL, "RST AIF1" }, 1140 { "AIF1 DA0R", NULL, "RST AIF1" }, 1141 1142 { "CLK AIF2", NULL, "AIF2CLK" }, 1143 { "CLK AIF2", NULL, "SYSCLK" }, 1144 { "RST AIF2", NULL, "CLK AIF2" }, 1145 { "AIF2 ADCL", NULL, "RST AIF2" }, 1146 { "AIF2 ADCR", NULL, "RST AIF2" }, 1147 { "AIF2 DACL", NULL, "RST AIF2" }, 1148 { "AIF2 DACR", NULL, "RST AIF2" }, 1149 1150 { "CLK AIF3", NULL, "AIF1CLK" }, 1151 { "CLK AIF3", NULL, "SYSCLK" }, 1152 { "RST AIF3", NULL, "CLK AIF3" }, 1153 { "AIF3 ADC", NULL, "RST AIF3" }, 1154 { "AIF3 DAC", NULL, "RST AIF3" }, 1155 1156 { "CLK ADC", NULL, "SYSCLK" }, 1157 { "RST ADC", NULL, "CLK ADC" }, 1158 { "ADC", NULL, "RST ADC" }, 1159 { "ADCL", NULL, "ADC" }, 1160 { "ADCR", NULL, "ADC" }, 1161 1162 { "CLK DAC", NULL, "SYSCLK" }, 1163 { "RST DAC", NULL, "CLK DAC" }, 1164 { "DAC", NULL, "RST DAC" }, 1165 { "DACL", NULL, "DAC" }, 1166 { "DACR", NULL, "DAC" }, 1167 1168 /* AIF "ADC" Output Routes */ 1169 { "AIF1 AD0L", NULL, "AIF1 AD0L Stereo Mux" }, 1170 { "AIF1 AD0R", NULL, "AIF1 AD0R Stereo Mux" }, 1171 1172 { "AIF2 ADCL", NULL, "AIF2 ADCL Stereo Mux" }, 1173 { "AIF2 ADCR", NULL, "AIF2 ADCR Stereo Mux" }, 1174 1175 { "AIF3 ADC", NULL, "AIF3 ADC Source Capture Route" }, 1176 1177 /* AIF "ADC" Mono/Stereo Mux Routes */ 1178 { "AIF1 AD0L Stereo Mux", "Stereo", "AIF1 AD0L Mixer" }, 1179 { "AIF1 AD0L Stereo Mux", "Reverse Stereo", "AIF1 AD0R Mixer" }, 1180 { "AIF1 AD0L Stereo Mux", "Sum Mono", "AIF1 AD0L Mixer" }, 1181 { "AIF1 AD0L Stereo Mux", "Sum Mono", "AIF1 AD0R Mixer" }, 1182 { "AIF1 AD0L Stereo Mux", "Mix Mono", "AIF1 AD0L Mixer" }, 1183 { "AIF1 AD0L Stereo Mux", "Mix Mono", "AIF1 AD0R Mixer" }, 1184 1185 { "AIF1 AD0R Stereo Mux", "Stereo", "AIF1 AD0R Mixer" }, 1186 { "AIF1 AD0R Stereo Mux", "Reverse Stereo", "AIF1 AD0L Mixer" }, 1187 { "AIF1 AD0R Stereo Mux", "Sum Mono", "AIF1 AD0L Mixer" }, 1188 { "AIF1 AD0R Stereo Mux", "Sum Mono", "AIF1 AD0R Mixer" }, 1189 { "AIF1 AD0R Stereo Mux", "Mix Mono", "AIF1 AD0L Mixer" }, 1190 { "AIF1 AD0R Stereo Mux", "Mix Mono", "AIF1 AD0R Mixer" }, 1191 1192 { "AIF2 ADCL Stereo Mux", "Stereo", "AIF2 ADCL Mixer" }, 1193 { "AIF2 ADCL Stereo Mux", "Reverse Stereo", "AIF2 ADCR Mixer" }, 1194 { "AIF2 ADCL Stereo Mux", "Sum Mono", "AIF2 ADCL Mixer" }, 1195 { "AIF2 ADCL Stereo Mux", "Sum Mono", "AIF2 ADCR Mixer" }, 1196 { "AIF2 ADCL Stereo Mux", "Mix Mono", "AIF2 ADCL Mixer" }, 1197 { "AIF2 ADCL Stereo Mux", "Mix Mono", "AIF2 ADCR Mixer" }, 1198 1199 { "AIF2 ADCR Stereo Mux", "Stereo", "AIF2 ADCR Mixer" }, 1200 { "AIF2 ADCR Stereo Mux", "Reverse Stereo", "AIF2 ADCL Mixer" }, 1201 { "AIF2 ADCR Stereo Mux", "Sum Mono", "AIF2 ADCL Mixer" }, 1202 { "AIF2 ADCR Stereo Mux", "Sum Mono", "AIF2 ADCR Mixer" }, 1203 { "AIF2 ADCR Stereo Mux", "Mix Mono", "AIF2 ADCL Mixer" }, 1204 { "AIF2 ADCR Stereo Mux", "Mix Mono", "AIF2 ADCR Mixer" }, 1205 1206 /* AIF "ADC" Output Mux Routes */ 1207 { "AIF3 ADC Source Capture Route", "AIF2 ADCL", "AIF2 ADCL Mixer" }, 1208 { "AIF3 ADC Source Capture Route", "AIF2 ADCR", "AIF2 ADCR Mixer" }, 1209 1210 /* AIF "ADC" Mixer Routes */ 1211 { "AIF1 AD0L Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0L Stereo Mux" }, 1212 { "AIF1 AD0L Mixer", "AIF2 Digital ADC Capture Switch", "AIF2 DACL Source" }, 1213 { "AIF1 AD0L Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCL" }, 1214 { "AIF1 AD0L Mixer", "AIF2 Inv Digital ADC Capture Switch", "AIF2 DACR Source" }, 1215 1216 { "AIF1 AD0R Mixer", "AIF1 Slot 0 Digital ADC Capture Switch", "AIF1 DA0R Stereo Mux" }, 1217 { "AIF1 AD0R Mixer", "AIF2 Digital ADC Capture Switch", "AIF2 DACR Source" }, 1218 { "AIF1 AD0R Mixer", "AIF1 Data Digital ADC Capture Switch", "ADCR" }, 1219 { "AIF1 AD0R Mixer", "AIF2 Inv Digital ADC Capture Switch", "AIF2 DACL Source" }, 1220 1221 { "AIF2 ADCL Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0L Stereo Mux" }, 1222 { "AIF2 ADCL Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DACR Source" }, 1223 { "AIF2 ADCL Mixer", "AIF2 ADC Mixer ADC Capture Switch", "ADCL" }, 1224 1225 { "AIF2 ADCR Mixer", "AIF2 ADC Mixer AIF1 DA0 Capture Switch", "AIF1 DA0R Stereo Mux" }, 1226 { "AIF2 ADCR Mixer", "AIF2 ADC Mixer AIF2 DAC Rev Capture Switch", "AIF2 DACL Source" }, 1227 { "AIF2 ADCR Mixer", "AIF2 ADC Mixer ADC Capture Switch", "ADCR" }, 1228 1229 /* AIF "DAC" Input Mux Routes */ 1230 { "AIF2 DACL Source", "AIF2", "AIF2 DACL Stereo Mux" }, 1231 { "AIF2 DACL Source", "AIF3+2", "AIF3 DAC" }, 1232 { "AIF2 DACL Source", "AIF2+3", "AIF2 DACL Stereo Mux" }, 1233 1234 { "AIF2 DACR Source", "AIF2", "AIF2 DACR Stereo Mux" }, 1235 { "AIF2 DACR Source", "AIF3+2", "AIF2 DACR Stereo Mux" }, 1236 { "AIF2 DACR Source", "AIF2+3", "AIF3 DAC" }, 1237 1238 /* AIF "DAC" Mono/Stereo Mux Routes */ 1239 { "AIF1 DA0L Stereo Mux", "Stereo", "AIF1 DA0L" }, 1240 { "AIF1 DA0L Stereo Mux", "Reverse Stereo", "AIF1 DA0R" }, 1241 { "AIF1 DA0L Stereo Mux", "Sum Mono", "AIF1 DA0L" }, 1242 { "AIF1 DA0L Stereo Mux", "Sum Mono", "AIF1 DA0R" }, 1243 { "AIF1 DA0L Stereo Mux", "Mix Mono", "AIF1 DA0L" }, 1244 { "AIF1 DA0L Stereo Mux", "Mix Mono", "AIF1 DA0R" }, 1245 1246 { "AIF1 DA0R Stereo Mux", "Stereo", "AIF1 DA0R" }, 1247 { "AIF1 DA0R Stereo Mux", "Reverse Stereo", "AIF1 DA0L" }, 1248 { "AIF1 DA0R Stereo Mux", "Sum Mono", "AIF1 DA0L" }, 1249 { "AIF1 DA0R Stereo Mux", "Sum Mono", "AIF1 DA0R" }, 1250 { "AIF1 DA0R Stereo Mux", "Mix Mono", "AIF1 DA0L" }, 1251 { "AIF1 DA0R Stereo Mux", "Mix Mono", "AIF1 DA0R" }, 1252 1253 { "AIF2 DACL Stereo Mux", "Stereo", "AIF2 DACL" }, 1254 { "AIF2 DACL Stereo Mux", "Reverse Stereo", "AIF2 DACR" }, 1255 { "AIF2 DACL Stereo Mux", "Sum Mono", "AIF2 DACL" }, 1256 { "AIF2 DACL Stereo Mux", "Sum Mono", "AIF2 DACR" }, 1257 { "AIF2 DACL Stereo Mux", "Mix Mono", "AIF2 DACL" }, 1258 { "AIF2 DACL Stereo Mux", "Mix Mono", "AIF2 DACR" }, 1259 1260 { "AIF2 DACR Stereo Mux", "Stereo", "AIF2 DACR" }, 1261 { "AIF2 DACR Stereo Mux", "Reverse Stereo", "AIF2 DACL" }, 1262 { "AIF2 DACR Stereo Mux", "Sum Mono", "AIF2 DACL" }, 1263 { "AIF2 DACR Stereo Mux", "Sum Mono", "AIF2 DACR" }, 1264 { "AIF2 DACR Stereo Mux", "Mix Mono", "AIF2 DACL" }, 1265 { "AIF2 DACR Stereo Mux", "Mix Mono", "AIF2 DACR" }, 1266 1267 /* DAC Output Routes */ 1268 { "DACL", NULL, "DACL Mixer" }, 1269 { "DACR", NULL, "DACR Mixer" }, 1270 1271 /* DAC Mixer Routes */ 1272 { "DACL Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0L Stereo Mux" }, 1273 { "DACL Mixer", "AIF2 Digital DAC Playback Switch", "AIF2 DACL Source" }, 1274 { "DACL Mixer", "ADC Digital DAC Playback Switch", "ADCL" }, 1275 1276 { "DACR Mixer", "AIF1 Slot 0 Digital DAC Playback Switch", "AIF1 DA0R Stereo Mux" }, 1277 { "DACR Mixer", "AIF2 Digital DAC Playback Switch", "AIF2 DACR Source" }, 1278 { "DACR Mixer", "ADC Digital DAC Playback Switch", "ADCR" }, 1279 }; 1280 1281 static const struct snd_soc_dapm_widget sun8i_codec_legacy_widgets[] = { 1282 /* Legacy ADC Inputs (connected to analog codec DAPM context) */ 1283 SND_SOC_DAPM_ADC("AIF1 Slot 0 Left ADC", NULL, SND_SOC_NOPM, 0, 0), 1284 SND_SOC_DAPM_ADC("AIF1 Slot 0 Right ADC", NULL, SND_SOC_NOPM, 0, 0), 1285 1286 /* Legacy DAC Outputs (connected to analog codec DAPM context) */ 1287 SND_SOC_DAPM_DAC("AIF1 Slot 0 Left", NULL, SND_SOC_NOPM, 0, 0), 1288 SND_SOC_DAPM_DAC("AIF1 Slot 0 Right", NULL, SND_SOC_NOPM, 0, 0), 1289 }; 1290 1291 static const struct snd_soc_dapm_route sun8i_codec_legacy_routes[] = { 1292 /* Legacy ADC Routes */ 1293 { "ADCL", NULL, "AIF1 Slot 0 Left ADC" }, 1294 { "ADCR", NULL, "AIF1 Slot 0 Right ADC" }, 1295 1296 /* Legacy DAC Routes */ 1297 { "AIF1 Slot 0 Left", NULL, "DACL" }, 1298 { "AIF1 Slot 0 Right", NULL, "DACR" }, 1299 }; 1300 1301 static int sun8i_codec_component_probe(struct snd_soc_component *component) 1302 { 1303 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(component); 1304 struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component); 1305 int ret; 1306 1307 scodec->component = component; 1308 1309 /* Add widgets for backward compatibility with old device trees. */ 1310 if (scodec->quirks->legacy_widgets) { 1311 ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_legacy_widgets, 1312 ARRAY_SIZE(sun8i_codec_legacy_widgets)); 1313 if (ret) 1314 return ret; 1315 1316 ret = snd_soc_dapm_add_routes(dapm, sun8i_codec_legacy_routes, 1317 ARRAY_SIZE(sun8i_codec_legacy_routes)); 1318 if (ret) 1319 return ret; 1320 } 1321 1322 /* 1323 * AIF1CLK and AIF2CLK share a pair of clock parents: PLL_AUDIO ("mod") 1324 * and MCLK (from the CPU DAI connected to AIF1). MCLK's parent is also 1325 * PLL_AUDIO, so using it adds no additional flexibility. Use PLL_AUDIO 1326 * directly to simplify the clock tree. 1327 */ 1328 regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL, 1329 SUN8I_SYSCLK_CTL_AIF1CLK_SRC_MASK | 1330 SUN8I_SYSCLK_CTL_AIF2CLK_SRC_MASK, 1331 SUN8I_SYSCLK_CTL_AIF1CLK_SRC_PLL | 1332 SUN8I_SYSCLK_CTL_AIF2CLK_SRC_PLL); 1333 1334 /* Use AIF1CLK as the SYSCLK parent since AIF1 is used most often. */ 1335 regmap_update_bits(scodec->regmap, SUN8I_SYSCLK_CTL, 1336 BIT(SUN8I_SYSCLK_CTL_SYSCLK_SRC), 1337 SUN8I_SYSCLK_CTL_SYSCLK_SRC_AIF1CLK); 1338 1339 /* Program the default sample rate. */ 1340 sun8i_codec_update_sample_rate(scodec); 1341 1342 return 0; 1343 } 1344 1345 static void sun8i_codec_set_hmic_bias(struct sun8i_codec *scodec, bool enable) 1346 { 1347 struct snd_soc_dapm_context *dapm = snd_soc_card_to_dapm(scodec->component->card); 1348 int irq_mask = BIT(SUN8I_HMIC_CTRL1_HMIC_DATA_IRQ_EN); 1349 1350 if (enable) 1351 snd_soc_dapm_force_enable_pin(dapm, "HBIAS"); 1352 else 1353 snd_soc_dapm_disable_pin(dapm, "HBIAS"); 1354 1355 snd_soc_dapm_sync(dapm); 1356 1357 regmap_update_bits(scodec->regmap, SUN8I_HMIC_CTRL1, 1358 irq_mask, enable ? irq_mask : 0); 1359 } 1360 1361 static void sun8i_codec_jack_work(struct work_struct *work) 1362 { 1363 struct sun8i_codec *scodec = container_of(work, struct sun8i_codec, 1364 jack_work.work); 1365 unsigned int mdata; 1366 int type; 1367 1368 guard(mutex)(&scodec->jack_mutex); 1369 1370 if (scodec->jack_status == SUN8I_JACK_STATUS_DISCONNECTED) { 1371 if (scodec->last_hmic_irq != SUN8I_HMIC_STS_JACK_IN_IRQ_ST) 1372 return; 1373 1374 scodec->jack_last_sample = -1; 1375 1376 if (scodec->jack_type & SND_JACK_MICROPHONE) { 1377 /* 1378 * If we were in disconnected state, we enable HBIAS and 1379 * wait 600ms before reading initial HDATA value. 1380 */ 1381 scodec->jack_hbias_ready = ktime_add_ms(ktime_get(), 600); 1382 sun8i_codec_set_hmic_bias(scodec, true); 1383 queue_delayed_work(system_power_efficient_wq, 1384 &scodec->jack_work, 1385 msecs_to_jiffies(610)); 1386 scodec->jack_status = SUN8I_JACK_STATUS_WAITING_HBIAS; 1387 } else { 1388 snd_soc_jack_report(scodec->jack, SND_JACK_HEADPHONE, 1389 scodec->jack_type); 1390 scodec->jack_status = SUN8I_JACK_STATUS_CONNECTED; 1391 } 1392 } else if (scodec->jack_status == SUN8I_JACK_STATUS_WAITING_HBIAS) { 1393 /* 1394 * If we're waiting for HBIAS to stabilize, and we get plug-out 1395 * interrupt and nothing more for > 100ms, just cancel the 1396 * initialization. 1397 */ 1398 if (scodec->last_hmic_irq == SUN8I_HMIC_STS_JACK_OUT_IRQ_ST) { 1399 scodec->jack_status = SUN8I_JACK_STATUS_DISCONNECTED; 1400 sun8i_codec_set_hmic_bias(scodec, false); 1401 return; 1402 } 1403 1404 /* 1405 * If we're not done waiting for HBIAS to stabilize, wait more. 1406 */ 1407 if (!ktime_after(ktime_get(), scodec->jack_hbias_ready)) { 1408 s64 msecs = ktime_ms_delta(scodec->jack_hbias_ready, 1409 ktime_get()); 1410 1411 queue_delayed_work(system_power_efficient_wq, 1412 &scodec->jack_work, 1413 msecs_to_jiffies(msecs + 10)); 1414 return; 1415 } 1416 1417 /* 1418 * Everything is stabilized, determine jack type and report it. 1419 */ 1420 regmap_read(scodec->regmap, SUN8I_HMIC_STS, &mdata); 1421 mdata &= SUN8I_HMIC_STS_HMIC_DATA_MASK; 1422 mdata >>= SUN8I_HMIC_STS_HMIC_DATA; 1423 1424 regmap_write(scodec->regmap, SUN8I_HMIC_STS, 0); 1425 1426 type = mdata < 16 ? SND_JACK_HEADPHONE : SND_JACK_HEADSET; 1427 if (type == SND_JACK_HEADPHONE) 1428 sun8i_codec_set_hmic_bias(scodec, false); 1429 1430 snd_soc_jack_report(scodec->jack, type, scodec->jack_type); 1431 scodec->jack_status = SUN8I_JACK_STATUS_CONNECTED; 1432 } else if (scodec->jack_status == SUN8I_JACK_STATUS_CONNECTED) { 1433 if (scodec->last_hmic_irq != SUN8I_HMIC_STS_JACK_OUT_IRQ_ST) 1434 return; 1435 1436 scodec->jack_status = SUN8I_JACK_STATUS_DISCONNECTED; 1437 if (scodec->jack_type & SND_JACK_MICROPHONE) 1438 sun8i_codec_set_hmic_bias(scodec, false); 1439 1440 snd_soc_jack_report(scodec->jack, 0, scodec->jack_type); 1441 } 1442 } 1443 1444 static irqreturn_t sun8i_codec_jack_irq(int irq, void *dev_id) 1445 { 1446 struct sun8i_codec *scodec = dev_id; 1447 int type = SND_JACK_HEADSET; 1448 unsigned int status, value; 1449 1450 guard(mutex)(&scodec->jack_mutex); 1451 1452 regmap_read(scodec->regmap, SUN8I_HMIC_STS, &status); 1453 regmap_write(scodec->regmap, SUN8I_HMIC_STS, status); 1454 1455 /* 1456 * De-bounce in/out interrupts via a delayed work re-scheduling to 1457 * 100ms after each interrupt.. 1458 */ 1459 if (status & BIT(SUN8I_HMIC_STS_JACK_OUT_IRQ_ST)) { 1460 /* 1461 * Out interrupt has priority over in interrupt so that if 1462 * we get both, we assume the disconnected state, which is 1463 * safer. 1464 */ 1465 scodec->last_hmic_irq = SUN8I_HMIC_STS_JACK_OUT_IRQ_ST; 1466 mod_delayed_work(system_power_efficient_wq, &scodec->jack_work, 1467 msecs_to_jiffies(100)); 1468 } else if (status & BIT(SUN8I_HMIC_STS_JACK_IN_IRQ_ST)) { 1469 scodec->last_hmic_irq = SUN8I_HMIC_STS_JACK_IN_IRQ_ST; 1470 mod_delayed_work(system_power_efficient_wq, &scodec->jack_work, 1471 msecs_to_jiffies(100)); 1472 } else if (status & BIT(SUN8I_HMIC_STS_HMIC_DATA_IRQ_ST)) { 1473 /* 1474 * Ignore data interrupts until jack status turns to connected 1475 * state, which is after HMIC enable stabilization is completed. 1476 * Until then tha data are bogus. 1477 */ 1478 if (scodec->jack_status != SUN8I_JACK_STATUS_CONNECTED) 1479 return IRQ_HANDLED; 1480 1481 value = (status & SUN8I_HMIC_STS_HMIC_DATA_MASK) >> 1482 SUN8I_HMIC_STS_HMIC_DATA; 1483 1484 /* 1485 * Assumes 60 mV per ADC LSB increment, 2V bias voltage, 2.2kOhm 1486 * bias resistor. 1487 */ 1488 if (value == 0) 1489 type |= SND_JACK_BTN_0; 1490 else if (value == 1) 1491 type |= SND_JACK_BTN_3; 1492 else if (value <= 3) 1493 type |= SND_JACK_BTN_1; 1494 else if (value <= 8) 1495 type |= SND_JACK_BTN_2; 1496 1497 /* 1498 * De-bounce. Only report button after two consecutive A/D 1499 * samples are identical. 1500 */ 1501 if (scodec->jack_last_sample >= 0 && 1502 scodec->jack_last_sample == value) 1503 snd_soc_jack_report(scodec->jack, type, 1504 scodec->jack_type); 1505 1506 scodec->jack_last_sample = value; 1507 } 1508 1509 return IRQ_HANDLED; 1510 } 1511 1512 static int sun8i_codec_enable_jack_detect(struct snd_soc_component *component, 1513 struct snd_soc_jack *jack, void *data) 1514 { 1515 struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component); 1516 struct platform_device *pdev = to_platform_device(component->dev); 1517 int ret; 1518 1519 if (!scodec->quirks->jack_detection) 1520 return 0; 1521 1522 scodec->jack = jack; 1523 1524 scodec->jack_irq = platform_get_irq(pdev, 0); 1525 if (scodec->jack_irq < 0) 1526 return scodec->jack_irq; 1527 1528 /* Reserved value required for jack IRQs to trigger. */ 1529 regmap_write(scodec->regmap, SUN8I_HMIC_CTRL1, 1530 0xf << SUN8I_HMIC_CTRL1_HMIC_N | 1531 0x0 << SUN8I_HMIC_CTRL1_MDATA_THRESHOLD_DB | 1532 0x4 << SUN8I_HMIC_CTRL1_HMIC_M); 1533 1534 /* Sample the ADC at 128 Hz; bypass smooth filter. */ 1535 regmap_write(scodec->regmap, SUN8I_HMIC_CTRL2, 1536 0x0 << SUN8I_HMIC_CTRL2_HMIC_SAMPLE | 1537 0x17 << SUN8I_HMIC_CTRL2_HMIC_MDATA_THRESHOLD | 1538 0x0 << SUN8I_HMIC_CTRL2_HMIC_SF); 1539 1540 /* Do not discard any MDATA, enable user written MDATA threshold. */ 1541 regmap_write(scodec->regmap, SUN8I_HMIC_STS, 0); 1542 1543 regmap_set_bits(scodec->regmap, SUN8I_HMIC_CTRL1, 1544 BIT(SUN8I_HMIC_CTRL1_JACK_OUT_IRQ_EN) | 1545 BIT(SUN8I_HMIC_CTRL1_JACK_IN_IRQ_EN)); 1546 1547 ret = devm_request_threaded_irq(&pdev->dev, scodec->jack_irq, 1548 NULL, sun8i_codec_jack_irq, 1549 IRQF_ONESHOT, 1550 dev_name(&pdev->dev), scodec); 1551 if (ret) 1552 return ret; 1553 1554 return 0; 1555 } 1556 1557 static void sun8i_codec_disable_jack_detect(struct snd_soc_component *component) 1558 { 1559 struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component); 1560 1561 if (!scodec->quirks->jack_detection) 1562 return; 1563 1564 devm_free_irq(component->dev, scodec->jack_irq, scodec); 1565 1566 cancel_delayed_work_sync(&scodec->jack_work); 1567 1568 regmap_clear_bits(scodec->regmap, SUN8I_HMIC_CTRL1, 1569 BIT(SUN8I_HMIC_CTRL1_JACK_OUT_IRQ_EN) | 1570 BIT(SUN8I_HMIC_CTRL1_JACK_IN_IRQ_EN) | 1571 BIT(SUN8I_HMIC_CTRL1_HMIC_DATA_IRQ_EN)); 1572 1573 scodec->jack = NULL; 1574 } 1575 1576 static int sun8i_codec_component_set_jack(struct snd_soc_component *component, 1577 struct snd_soc_jack *jack, void *data) 1578 { 1579 int ret = 0; 1580 1581 if (jack) 1582 ret = sun8i_codec_enable_jack_detect(component, jack, data); 1583 else 1584 sun8i_codec_disable_jack_detect(component); 1585 1586 return ret; 1587 } 1588 1589 static const struct snd_soc_component_driver sun8i_soc_component = { 1590 .controls = sun8i_codec_controls, 1591 .num_controls = ARRAY_SIZE(sun8i_codec_controls), 1592 .dapm_widgets = sun8i_codec_dapm_widgets, 1593 .num_dapm_widgets = ARRAY_SIZE(sun8i_codec_dapm_widgets), 1594 .dapm_routes = sun8i_codec_dapm_routes, 1595 .num_dapm_routes = ARRAY_SIZE(sun8i_codec_dapm_routes), 1596 .set_jack = sun8i_codec_component_set_jack, 1597 .probe = sun8i_codec_component_probe, 1598 .idle_bias_on = 1, 1599 .suspend_bias_off = 1, 1600 .endianness = 1, 1601 }; 1602 1603 static bool sun8i_codec_volatile_reg(struct device *dev, unsigned int reg) 1604 { 1605 return reg == SUN8I_HMIC_STS; 1606 } 1607 1608 static const struct regmap_config sun8i_codec_regmap_config = { 1609 .reg_bits = 32, 1610 .reg_stride = 4, 1611 .val_bits = 32, 1612 .volatile_reg = sun8i_codec_volatile_reg, 1613 .max_register = SUN8I_DAC_MXR_SRC, 1614 1615 .cache_type = REGCACHE_FLAT, 1616 }; 1617 1618 static int sun8i_codec_probe(struct platform_device *pdev) 1619 { 1620 struct sun8i_codec *scodec; 1621 void __iomem *base; 1622 int ret; 1623 1624 scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL); 1625 if (!scodec) 1626 return -ENOMEM; 1627 1628 scodec->quirks = of_device_get_match_data(&pdev->dev); 1629 INIT_DELAYED_WORK(&scodec->jack_work, sun8i_codec_jack_work); 1630 mutex_init(&scodec->jack_mutex); 1631 1632 platform_set_drvdata(pdev, scodec); 1633 1634 if (scodec->quirks->bus_clock) { 1635 scodec->clk_bus = devm_clk_get(&pdev->dev, "bus"); 1636 if (IS_ERR(scodec->clk_bus)) { 1637 dev_err(&pdev->dev, "Failed to get the bus clock\n"); 1638 return PTR_ERR(scodec->clk_bus); 1639 } 1640 } 1641 1642 scodec->clk_module = devm_clk_get(&pdev->dev, "mod"); 1643 if (IS_ERR(scodec->clk_module)) { 1644 dev_err(&pdev->dev, "Failed to get the module clock\n"); 1645 return PTR_ERR(scodec->clk_module); 1646 } 1647 1648 base = devm_platform_ioremap_resource(pdev, 0); 1649 if (IS_ERR(base)) { 1650 dev_err(&pdev->dev, "Failed to map the registers\n"); 1651 return PTR_ERR(base); 1652 } 1653 1654 scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base, 1655 &sun8i_codec_regmap_config); 1656 if (IS_ERR(scodec->regmap)) { 1657 dev_err(&pdev->dev, "Failed to create our regmap\n"); 1658 return PTR_ERR(scodec->regmap); 1659 } 1660 1661 regcache_cache_only(scodec->regmap, true); 1662 pm_runtime_enable(&pdev->dev); 1663 if (!pm_runtime_enabled(&pdev->dev)) { 1664 ret = sun8i_codec_runtime_resume(&pdev->dev); 1665 if (ret) 1666 goto err_pm_disable; 1667 } 1668 1669 ret = devm_snd_soc_register_component(&pdev->dev, &sun8i_soc_component, 1670 sun8i_codec_dais, 1671 ARRAY_SIZE(sun8i_codec_dais)); 1672 if (ret) { 1673 dev_err(&pdev->dev, "Failed to register codec\n"); 1674 goto err_suspend; 1675 } 1676 1677 return ret; 1678 1679 err_suspend: 1680 if (!pm_runtime_status_suspended(&pdev->dev)) 1681 sun8i_codec_runtime_suspend(&pdev->dev); 1682 1683 err_pm_disable: 1684 pm_runtime_disable(&pdev->dev); 1685 1686 return ret; 1687 } 1688 1689 static void sun8i_codec_remove(struct platform_device *pdev) 1690 { 1691 pm_runtime_disable(&pdev->dev); 1692 if (!pm_runtime_status_suspended(&pdev->dev)) 1693 sun8i_codec_runtime_suspend(&pdev->dev); 1694 } 1695 1696 static const struct sun8i_codec_quirks sun8i_a33_quirks = { 1697 .bus_clock = true, 1698 .legacy_widgets = true, 1699 .lrck_inversion = true, 1700 }; 1701 1702 static const struct sun8i_codec_quirks sun50i_a64_quirks = { 1703 .bus_clock = true, 1704 .jack_detection = true, 1705 }; 1706 1707 static const struct of_device_id sun8i_codec_of_match[] = { 1708 { .compatible = "allwinner,sun8i-a33-codec", .data = &sun8i_a33_quirks }, 1709 { .compatible = "allwinner,sun50i-a64-codec", .data = &sun50i_a64_quirks }, 1710 {} 1711 }; 1712 MODULE_DEVICE_TABLE(of, sun8i_codec_of_match); 1713 1714 static const struct dev_pm_ops sun8i_codec_pm_ops = { 1715 RUNTIME_PM_OPS(sun8i_codec_runtime_suspend, 1716 sun8i_codec_runtime_resume, NULL) 1717 }; 1718 1719 static struct platform_driver sun8i_codec_driver = { 1720 .driver = { 1721 .name = "sun8i-codec", 1722 .of_match_table = sun8i_codec_of_match, 1723 .pm = pm_ptr(&sun8i_codec_pm_ops), 1724 }, 1725 .probe = sun8i_codec_probe, 1726 .remove = sun8i_codec_remove, 1727 }; 1728 module_platform_driver(sun8i_codec_driver); 1729 1730 MODULE_DESCRIPTION("Allwinner A33 (sun8i) codec driver"); 1731 MODULE_AUTHOR("Mylène Josserand <mylene.josserand@free-electrons.com>"); 1732 MODULE_LICENSE("GPL"); 1733 MODULE_ALIAS("platform:sun8i-codec"); 1734