1 /* 2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sub license, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the 12 * next paragraph) shall be included in all copies or substantial portions 13 * of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/gpio/consumer.h> 26 #include <linux/i2c.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/regulator/consumer.h> 33 34 #include <video/display_timing.h> 35 #include <video/of_display_timing.h> 36 #include <video/videomode.h> 37 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_device.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_panel.h> 43 #include <drm/drm_of.h> 44 45 /** 46 * struct panel_desc - Describes a simple panel. 47 */ 48 struct panel_desc { 49 /** 50 * @modes: Pointer to array of fixed modes appropriate for this panel. 51 * 52 * If only one mode then this can just be the address of the mode. 53 * NOTE: cannot be used with "timings" and also if this is specified 54 * then you cannot override the mode in the device tree. 55 */ 56 const struct drm_display_mode *modes; 57 58 /** @num_modes: Number of elements in modes array. */ 59 unsigned int num_modes; 60 61 /** 62 * @timings: Pointer to array of display timings 63 * 64 * NOTE: cannot be used with "modes" and also these will be used to 65 * validate a device tree override if one is present. 66 */ 67 const struct display_timing *timings; 68 69 /** @num_timings: Number of elements in timings array. */ 70 unsigned int num_timings; 71 72 /** @bpc: Bits per color. */ 73 unsigned int bpc; 74 75 /** @size: Structure containing the physical size of this panel. */ 76 struct { 77 /** 78 * @size.width: Width (in mm) of the active display area. 79 */ 80 unsigned int width; 81 82 /** 83 * @size.height: Height (in mm) of the active display area. 84 */ 85 unsigned int height; 86 } size; 87 88 /** @delay: Structure containing various delay values for this panel. */ 89 struct { 90 /** 91 * @delay.prepare: Time for the panel to become ready. 92 * 93 * The time (in milliseconds) that it takes for the panel to 94 * become ready and start receiving video data 95 */ 96 unsigned int prepare; 97 98 /** 99 * @delay.enable: Time for the panel to display a valid frame. 100 * 101 * The time (in milliseconds) that it takes for the panel to 102 * display the first valid frame after starting to receive 103 * video data. 104 */ 105 unsigned int enable; 106 107 /** 108 * @delay.disable: Time for the panel to turn the display off. 109 * 110 * The time (in milliseconds) that it takes for the panel to 111 * turn the display off (no content is visible). 112 */ 113 unsigned int disable; 114 115 /** 116 * @delay.unprepare: Time to power down completely. 117 * 118 * The time (in milliseconds) that it takes for the panel 119 * to power itself down completely. 120 * 121 * This time is used to prevent a future "prepare" from 122 * starting until at least this many milliseconds has passed. 123 * If at prepare time less time has passed since unprepare 124 * finished, the driver waits for the remaining time. 125 */ 126 unsigned int unprepare; 127 } delay; 128 129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */ 130 u32 bus_format; 131 132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */ 133 u32 bus_flags; 134 135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */ 136 int connector_type; 137 }; 138 139 struct panel_simple { 140 struct drm_panel base; 141 142 ktime_t unprepared_time; 143 144 const struct panel_desc *desc; 145 146 struct regulator *supply; 147 struct i2c_adapter *ddc; 148 149 struct gpio_desc *enable_gpio; 150 151 const struct drm_edid *drm_edid; 152 153 struct drm_display_mode override_mode; 154 155 enum drm_panel_orientation orientation; 156 }; 157 158 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel) 159 { 160 return container_of(panel, struct panel_simple, base); 161 } 162 163 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel, 164 struct drm_connector *connector) 165 { 166 struct drm_display_mode *mode; 167 unsigned int i, num = 0; 168 169 for (i = 0; i < panel->desc->num_timings; i++) { 170 const struct display_timing *dt = &panel->desc->timings[i]; 171 struct videomode vm; 172 173 videomode_from_timing(dt, &vm); 174 mode = drm_mode_create(connector->dev); 175 if (!mode) { 176 dev_err(panel->base.dev, "failed to add mode %ux%u\n", 177 dt->hactive.typ, dt->vactive.typ); 178 continue; 179 } 180 181 drm_display_mode_from_videomode(&vm, mode); 182 183 mode->type |= DRM_MODE_TYPE_DRIVER; 184 185 if (panel->desc->num_timings == 1) 186 mode->type |= DRM_MODE_TYPE_PREFERRED; 187 188 drm_mode_probed_add(connector, mode); 189 num++; 190 } 191 192 return num; 193 } 194 195 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel, 196 struct drm_connector *connector) 197 { 198 struct drm_display_mode *mode; 199 unsigned int i, num = 0; 200 201 for (i = 0; i < panel->desc->num_modes; i++) { 202 const struct drm_display_mode *m = &panel->desc->modes[i]; 203 204 mode = drm_mode_duplicate(connector->dev, m); 205 if (!mode) { 206 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n", 207 m->hdisplay, m->vdisplay, 208 drm_mode_vrefresh(m)); 209 continue; 210 } 211 212 mode->type |= DRM_MODE_TYPE_DRIVER; 213 214 if (panel->desc->num_modes == 1) 215 mode->type |= DRM_MODE_TYPE_PREFERRED; 216 217 drm_mode_set_name(mode); 218 219 drm_mode_probed_add(connector, mode); 220 num++; 221 } 222 223 return num; 224 } 225 226 static int panel_simple_get_non_edid_modes(struct panel_simple *panel, 227 struct drm_connector *connector) 228 { 229 struct drm_display_mode *mode; 230 bool has_override = panel->override_mode.type; 231 unsigned int num = 0; 232 233 if (!panel->desc) 234 return 0; 235 236 if (has_override) { 237 mode = drm_mode_duplicate(connector->dev, 238 &panel->override_mode); 239 if (mode) { 240 drm_mode_probed_add(connector, mode); 241 num = 1; 242 } else { 243 dev_err(panel->base.dev, "failed to add override mode\n"); 244 } 245 } 246 247 /* Only add timings if override was not there or failed to validate */ 248 if (num == 0 && panel->desc->num_timings) 249 num = panel_simple_get_timings_modes(panel, connector); 250 251 /* 252 * Only add fixed modes if timings/override added no mode. 253 * 254 * We should only ever have either the display timings specified 255 * or a fixed mode. Anything else is rather bogus. 256 */ 257 WARN_ON(panel->desc->num_timings && panel->desc->num_modes); 258 if (num == 0) 259 num = panel_simple_get_display_modes(panel, connector); 260 261 connector->display_info.bpc = panel->desc->bpc; 262 connector->display_info.width_mm = panel->desc->size.width; 263 connector->display_info.height_mm = panel->desc->size.height; 264 if (panel->desc->bus_format) 265 drm_display_info_set_bus_formats(&connector->display_info, 266 &panel->desc->bus_format, 1); 267 connector->display_info.bus_flags = panel->desc->bus_flags; 268 269 return num; 270 } 271 272 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms) 273 { 274 ktime_t now_ktime, min_ktime; 275 276 if (!min_ms) 277 return; 278 279 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms)); 280 now_ktime = ktime_get_boottime(); 281 282 if (ktime_before(now_ktime, min_ktime)) 283 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1); 284 } 285 286 static int panel_simple_disable(struct drm_panel *panel) 287 { 288 struct panel_simple *p = to_panel_simple(panel); 289 290 if (p->desc->delay.disable) 291 msleep(p->desc->delay.disable); 292 293 return 0; 294 } 295 296 static int panel_simple_suspend(struct device *dev) 297 { 298 struct panel_simple *p = dev_get_drvdata(dev); 299 300 gpiod_set_value_cansleep(p->enable_gpio, 0); 301 regulator_disable(p->supply); 302 p->unprepared_time = ktime_get_boottime(); 303 304 drm_edid_free(p->drm_edid); 305 p->drm_edid = NULL; 306 307 return 0; 308 } 309 310 static int panel_simple_unprepare(struct drm_panel *panel) 311 { 312 int ret; 313 314 pm_runtime_mark_last_busy(panel->dev); 315 ret = pm_runtime_put_autosuspend(panel->dev); 316 if (ret < 0) 317 return ret; 318 319 return 0; 320 } 321 322 static int panel_simple_resume(struct device *dev) 323 { 324 struct panel_simple *p = dev_get_drvdata(dev); 325 int err; 326 327 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare); 328 329 err = regulator_enable(p->supply); 330 if (err < 0) { 331 dev_err(dev, "failed to enable supply: %d\n", err); 332 return err; 333 } 334 335 gpiod_set_value_cansleep(p->enable_gpio, 1); 336 337 if (p->desc->delay.prepare) 338 msleep(p->desc->delay.prepare); 339 340 return 0; 341 } 342 343 static int panel_simple_prepare(struct drm_panel *panel) 344 { 345 int ret; 346 347 ret = pm_runtime_get_sync(panel->dev); 348 if (ret < 0) { 349 pm_runtime_put_autosuspend(panel->dev); 350 return ret; 351 } 352 353 return 0; 354 } 355 356 static int panel_simple_enable(struct drm_panel *panel) 357 { 358 struct panel_simple *p = to_panel_simple(panel); 359 360 if (p->desc->delay.enable) 361 msleep(p->desc->delay.enable); 362 363 return 0; 364 } 365 366 static int panel_simple_get_modes(struct drm_panel *panel, 367 struct drm_connector *connector) 368 { 369 struct panel_simple *p = to_panel_simple(panel); 370 int num = 0; 371 372 /* probe EDID if a DDC bus is available */ 373 if (p->ddc) { 374 pm_runtime_get_sync(panel->dev); 375 376 if (!p->drm_edid) 377 p->drm_edid = drm_edid_read_ddc(connector, p->ddc); 378 379 drm_edid_connector_update(connector, p->drm_edid); 380 381 num += drm_edid_connector_add_modes(connector); 382 383 pm_runtime_mark_last_busy(panel->dev); 384 pm_runtime_put_autosuspend(panel->dev); 385 } 386 387 /* add hard-coded panel modes */ 388 num += panel_simple_get_non_edid_modes(p, connector); 389 390 /* 391 * TODO: Remove once all drm drivers call 392 * drm_connector_set_orientation_from_panel() 393 */ 394 drm_connector_set_panel_orientation(connector, p->orientation); 395 396 return num; 397 } 398 399 static int panel_simple_get_timings(struct drm_panel *panel, 400 unsigned int num_timings, 401 struct display_timing *timings) 402 { 403 struct panel_simple *p = to_panel_simple(panel); 404 unsigned int i; 405 406 if (p->desc->num_timings < num_timings) 407 num_timings = p->desc->num_timings; 408 409 if (timings) 410 for (i = 0; i < num_timings; i++) 411 timings[i] = p->desc->timings[i]; 412 413 return p->desc->num_timings; 414 } 415 416 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) 417 { 418 struct panel_simple *p = to_panel_simple(panel); 419 420 return p->orientation; 421 } 422 423 static const struct drm_panel_funcs panel_simple_funcs = { 424 .disable = panel_simple_disable, 425 .unprepare = panel_simple_unprepare, 426 .prepare = panel_simple_prepare, 427 .enable = panel_simple_enable, 428 .get_modes = panel_simple_get_modes, 429 .get_orientation = panel_simple_get_orientation, 430 .get_timings = panel_simple_get_timings, 431 }; 432 433 static struct panel_desc panel_dpi; 434 435 static int panel_dpi_probe(struct device *dev, 436 struct panel_simple *panel) 437 { 438 struct display_timing *timing; 439 const struct device_node *np; 440 struct panel_desc *desc; 441 unsigned int bus_flags; 442 struct videomode vm; 443 int ret; 444 445 np = dev->of_node; 446 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); 447 if (!desc) 448 return -ENOMEM; 449 450 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL); 451 if (!timing) 452 return -ENOMEM; 453 454 ret = of_get_display_timing(np, "panel-timing", timing); 455 if (ret < 0) { 456 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n", 457 np); 458 return ret; 459 } 460 461 desc->timings = timing; 462 desc->num_timings = 1; 463 464 of_property_read_u32(np, "width-mm", &desc->size.width); 465 of_property_read_u32(np, "height-mm", &desc->size.height); 466 467 /* Extract bus_flags from display_timing */ 468 bus_flags = 0; 469 vm.flags = timing->flags; 470 drm_bus_flags_from_videomode(&vm, &bus_flags); 471 desc->bus_flags = bus_flags; 472 473 /* We do not know the connector for the DT node, so guess it */ 474 desc->connector_type = DRM_MODE_CONNECTOR_DPI; 475 476 panel->desc = desc; 477 478 return 0; 479 } 480 481 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \ 482 (to_check->field.typ >= bounds->field.min && \ 483 to_check->field.typ <= bounds->field.max) 484 static void panel_simple_parse_panel_timing_node(struct device *dev, 485 struct panel_simple *panel, 486 const struct display_timing *ot) 487 { 488 const struct panel_desc *desc = panel->desc; 489 struct videomode vm; 490 unsigned int i; 491 492 if (WARN_ON(desc->num_modes)) { 493 dev_err(dev, "Reject override mode: panel has a fixed mode\n"); 494 return; 495 } 496 if (WARN_ON(!desc->num_timings)) { 497 dev_err(dev, "Reject override mode: no timings specified\n"); 498 return; 499 } 500 501 for (i = 0; i < panel->desc->num_timings; i++) { 502 const struct display_timing *dt = &panel->desc->timings[i]; 503 504 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) || 505 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) || 506 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) || 507 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) || 508 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) || 509 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) || 510 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) || 511 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len)) 512 continue; 513 514 if (ot->flags != dt->flags) 515 continue; 516 517 videomode_from_timing(ot, &vm); 518 drm_display_mode_from_videomode(&vm, &panel->override_mode); 519 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER | 520 DRM_MODE_TYPE_PREFERRED; 521 break; 522 } 523 524 if (WARN_ON(!panel->override_mode.type)) 525 dev_err(dev, "Reject override mode: No display_timing found\n"); 526 } 527 528 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev, 529 struct panel_simple *panel) 530 { 531 int ret, bpc; 532 533 ret = drm_of_lvds_get_data_mapping(dev->of_node); 534 if (ret < 0) { 535 if (ret == -EINVAL) 536 dev_warn(dev, "Ignore invalid data-mapping property\n"); 537 538 /* 539 * Ignore non-existing or malformatted property, fallback to 540 * default data-mapping, and return 0. 541 */ 542 return 0; 543 } 544 545 switch (ret) { 546 default: 547 WARN_ON(1); 548 fallthrough; 549 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 550 fallthrough; 551 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 552 bpc = 8; 553 break; 554 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 555 bpc = 6; 556 } 557 558 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) { 559 struct panel_desc *override_desc; 560 561 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL); 562 if (!override_desc) 563 return -ENOMEM; 564 565 override_desc->bus_format = ret; 566 override_desc->bpc = bpc; 567 panel->desc = override_desc; 568 } 569 570 return 0; 571 } 572 573 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) 574 { 575 struct panel_simple *panel; 576 struct display_timing dt; 577 struct device_node *ddc; 578 int connector_type; 579 u32 bus_flags; 580 int err; 581 582 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL); 583 if (!panel) 584 return -ENOMEM; 585 586 panel->desc = desc; 587 588 panel->supply = devm_regulator_get(dev, "power"); 589 if (IS_ERR(panel->supply)) 590 return PTR_ERR(panel->supply); 591 592 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 593 GPIOD_OUT_LOW); 594 if (IS_ERR(panel->enable_gpio)) 595 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), 596 "failed to request GPIO\n"); 597 598 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation); 599 if (err) { 600 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err); 601 return err; 602 } 603 604 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); 605 if (ddc) { 606 panel->ddc = of_find_i2c_adapter_by_node(ddc); 607 of_node_put(ddc); 608 609 if (!panel->ddc) 610 return -EPROBE_DEFER; 611 } 612 613 if (desc == &panel_dpi) { 614 /* Handle the generic panel-dpi binding */ 615 err = panel_dpi_probe(dev, panel); 616 if (err) 617 goto free_ddc; 618 desc = panel->desc; 619 } else { 620 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt)) 621 panel_simple_parse_panel_timing_node(dev, panel, &dt); 622 } 623 624 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) { 625 /* Optional data-mapping property for overriding bus format */ 626 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel); 627 if (err) 628 goto free_ddc; 629 } 630 631 connector_type = desc->connector_type; 632 /* Catch common mistakes for panels. */ 633 switch (connector_type) { 634 case 0: 635 dev_warn(dev, "Specify missing connector_type\n"); 636 connector_type = DRM_MODE_CONNECTOR_DPI; 637 break; 638 case DRM_MODE_CONNECTOR_LVDS: 639 WARN_ON(desc->bus_flags & 640 ~(DRM_BUS_FLAG_DE_LOW | 641 DRM_BUS_FLAG_DE_HIGH | 642 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 643 DRM_BUS_FLAG_DATA_LSB_TO_MSB)); 644 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 645 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG && 646 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA); 647 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG && 648 desc->bpc != 6); 649 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG || 650 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) && 651 desc->bpc != 8); 652 break; 653 case DRM_MODE_CONNECTOR_eDP: 654 dev_warn(dev, "eDP panels moved to panel-edp\n"); 655 err = -EINVAL; 656 goto free_ddc; 657 case DRM_MODE_CONNECTOR_DSI: 658 if (desc->bpc != 6 && desc->bpc != 8) 659 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 660 break; 661 case DRM_MODE_CONNECTOR_DPI: 662 bus_flags = DRM_BUS_FLAG_DE_LOW | 663 DRM_BUS_FLAG_DE_HIGH | 664 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | 665 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 666 DRM_BUS_FLAG_DATA_MSB_TO_LSB | 667 DRM_BUS_FLAG_DATA_LSB_TO_MSB | 668 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE | 669 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE; 670 if (desc->bus_flags & ~bus_flags) 671 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags); 672 if (!(desc->bus_flags & bus_flags)) 673 dev_warn(dev, "Specify missing bus_flags\n"); 674 if (desc->bus_format == 0) 675 dev_warn(dev, "Specify missing bus_format\n"); 676 if (desc->bpc != 6 && desc->bpc != 8) 677 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc); 678 break; 679 default: 680 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type); 681 connector_type = DRM_MODE_CONNECTOR_DPI; 682 break; 683 } 684 685 dev_set_drvdata(dev, panel); 686 687 /* 688 * We use runtime PM for prepare / unprepare since those power the panel 689 * on and off and those can be very slow operations. This is important 690 * to optimize powering the panel on briefly to read the EDID before 691 * fully enabling the panel. 692 */ 693 pm_runtime_enable(dev); 694 pm_runtime_set_autosuspend_delay(dev, 1000); 695 pm_runtime_use_autosuspend(dev); 696 697 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type); 698 699 err = drm_panel_of_backlight(&panel->base); 700 if (err) { 701 dev_err_probe(dev, err, "Could not find backlight\n"); 702 goto disable_pm_runtime; 703 } 704 705 drm_panel_add(&panel->base); 706 707 return 0; 708 709 disable_pm_runtime: 710 pm_runtime_dont_use_autosuspend(dev); 711 pm_runtime_disable(dev); 712 free_ddc: 713 if (panel->ddc) 714 put_device(&panel->ddc->dev); 715 716 return err; 717 } 718 719 static void panel_simple_shutdown(struct device *dev) 720 { 721 struct panel_simple *panel = dev_get_drvdata(dev); 722 723 /* 724 * NOTE: the following two calls don't really belong here. It is the 725 * responsibility of a correctly written DRM modeset driver to call 726 * drm_atomic_helper_shutdown() at shutdown time and that should 727 * cause the panel to be disabled / unprepared if needed. For now, 728 * however, we'll keep these calls due to the sheer number of 729 * different DRM modeset drivers used with panel-simple. Once we've 730 * confirmed that all DRM modeset drivers using this panel properly 731 * call drm_atomic_helper_shutdown() we can simply delete the two 732 * calls below. 733 * 734 * TO BE EXPLICIT: THE CALLS BELOW SHOULDN'T BE COPIED TO ANY NEW 735 * PANEL DRIVERS. 736 * 737 * FIXME: If we're still haven't figured out if all DRM modeset 738 * drivers properly call drm_atomic_helper_shutdown() but we _have_ 739 * managed to make sure that DRM modeset drivers get their shutdown() 740 * callback before the panel's shutdown() callback (perhaps using 741 * device link), we could add a WARN_ON here to help move forward. 742 */ 743 if (panel->base.enabled) 744 drm_panel_disable(&panel->base); 745 if (panel->base.prepared) 746 drm_panel_unprepare(&panel->base); 747 } 748 749 static void panel_simple_remove(struct device *dev) 750 { 751 struct panel_simple *panel = dev_get_drvdata(dev); 752 753 drm_panel_remove(&panel->base); 754 panel_simple_shutdown(dev); 755 756 pm_runtime_dont_use_autosuspend(dev); 757 pm_runtime_disable(dev); 758 if (panel->ddc) 759 put_device(&panel->ddc->dev); 760 } 761 762 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = { 763 .clock = 71100, 764 .hdisplay = 1280, 765 .hsync_start = 1280 + 40, 766 .hsync_end = 1280 + 40 + 80, 767 .htotal = 1280 + 40 + 80 + 40, 768 .vdisplay = 800, 769 .vsync_start = 800 + 3, 770 .vsync_end = 800 + 3 + 10, 771 .vtotal = 800 + 3 + 10 + 10, 772 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 773 }; 774 775 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = { 776 .modes = &ire_am_1280800n3tzqw_t00h_mode, 777 .num_modes = 1, 778 .bpc = 8, 779 .size = { 780 .width = 217, 781 .height = 136, 782 }, 783 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 784 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 785 .connector_type = DRM_MODE_CONNECTOR_LVDS, 786 }; 787 788 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = { 789 .clock = 9000, 790 .hdisplay = 480, 791 .hsync_start = 480 + 2, 792 .hsync_end = 480 + 2 + 41, 793 .htotal = 480 + 2 + 41 + 2, 794 .vdisplay = 272, 795 .vsync_start = 272 + 2, 796 .vsync_end = 272 + 2 + 10, 797 .vtotal = 272 + 2 + 10 + 2, 798 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 799 }; 800 801 static const struct panel_desc ampire_am_480272h3tmqw_t01h = { 802 .modes = &ire_am_480272h3tmqw_t01h_mode, 803 .num_modes = 1, 804 .bpc = 8, 805 .size = { 806 .width = 99, 807 .height = 58, 808 }, 809 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 810 }; 811 812 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = { 813 .clock = 33333, 814 .hdisplay = 800, 815 .hsync_start = 800 + 0, 816 .hsync_end = 800 + 0 + 255, 817 .htotal = 800 + 0 + 255 + 0, 818 .vdisplay = 480, 819 .vsync_start = 480 + 2, 820 .vsync_end = 480 + 2 + 45, 821 .vtotal = 480 + 2 + 45 + 0, 822 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 823 }; 824 825 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = { 826 .pixelclock = { 29930000, 33260000, 36590000 }, 827 .hactive = { 800, 800, 800 }, 828 .hfront_porch = { 1, 40, 168 }, 829 .hback_porch = { 88, 88, 88 }, 830 .hsync_len = { 1, 128, 128 }, 831 .vactive = { 480, 480, 480 }, 832 .vfront_porch = { 1, 35, 37 }, 833 .vback_porch = { 8, 8, 8 }, 834 .vsync_len = { 1, 2, 2 }, 835 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 836 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 837 DISPLAY_FLAGS_SYNC_POSEDGE, 838 }; 839 840 static const struct panel_desc ampire_am_800480l1tmqw_t00h = { 841 .timings = &ire_am_800480l1tmqw_t00h_timing, 842 .num_timings = 1, 843 .bpc = 8, 844 .size = { 845 .width = 111, 846 .height = 67, 847 }, 848 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 849 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 850 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 851 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 852 .connector_type = DRM_MODE_CONNECTOR_DPI, 853 }; 854 855 static const struct panel_desc ampire_am800480r3tmqwa1h = { 856 .modes = &ire_am800480r3tmqwa1h_mode, 857 .num_modes = 1, 858 .bpc = 6, 859 .size = { 860 .width = 152, 861 .height = 91, 862 }, 863 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 864 }; 865 866 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = { 867 .pixelclock = { 34500000, 39600000, 50400000 }, 868 .hactive = { 800, 800, 800 }, 869 .hfront_porch = { 12, 112, 312 }, 870 .hback_porch = { 87, 87, 48 }, 871 .hsync_len = { 1, 1, 40 }, 872 .vactive = { 600, 600, 600 }, 873 .vfront_porch = { 1, 21, 61 }, 874 .vback_porch = { 38, 38, 19 }, 875 .vsync_len = { 1, 1, 20 }, 876 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 877 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 878 DISPLAY_FLAGS_SYNC_POSEDGE, 879 }; 880 881 static const struct panel_desc ampire_am800600p5tmqwtb8h = { 882 .timings = &ire_am800600p5tmqw_tb8h_timing, 883 .num_timings = 1, 884 .bpc = 6, 885 .size = { 886 .width = 162, 887 .height = 122, 888 }, 889 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 890 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 891 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 892 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 893 .connector_type = DRM_MODE_CONNECTOR_DPI, 894 }; 895 896 static const struct display_timing santek_st0700i5y_rbslw_f_timing = { 897 .pixelclock = { 26400000, 33300000, 46800000 }, 898 .hactive = { 800, 800, 800 }, 899 .hfront_porch = { 16, 210, 354 }, 900 .hback_porch = { 45, 36, 6 }, 901 .hsync_len = { 1, 10, 40 }, 902 .vactive = { 480, 480, 480 }, 903 .vfront_porch = { 7, 22, 147 }, 904 .vback_porch = { 22, 13, 3 }, 905 .vsync_len = { 1, 10, 20 }, 906 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 907 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE 908 }; 909 910 static const struct panel_desc armadeus_st0700_adapt = { 911 .timings = &santek_st0700i5y_rbslw_f_timing, 912 .num_timings = 1, 913 .bpc = 6, 914 .size = { 915 .width = 154, 916 .height = 86, 917 }, 918 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 919 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 920 }; 921 922 static const struct drm_display_mode auo_b101aw03_mode = { 923 .clock = 51450, 924 .hdisplay = 1024, 925 .hsync_start = 1024 + 156, 926 .hsync_end = 1024 + 156 + 8, 927 .htotal = 1024 + 156 + 8 + 156, 928 .vdisplay = 600, 929 .vsync_start = 600 + 16, 930 .vsync_end = 600 + 16 + 6, 931 .vtotal = 600 + 16 + 6 + 16, 932 }; 933 934 static const struct panel_desc auo_b101aw03 = { 935 .modes = &auo_b101aw03_mode, 936 .num_modes = 1, 937 .bpc = 6, 938 .size = { 939 .width = 223, 940 .height = 125, 941 }, 942 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 943 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 944 .connector_type = DRM_MODE_CONNECTOR_LVDS, 945 }; 946 947 static const struct drm_display_mode auo_b101xtn01_mode = { 948 .clock = 72000, 949 .hdisplay = 1366, 950 .hsync_start = 1366 + 20, 951 .hsync_end = 1366 + 20 + 70, 952 .htotal = 1366 + 20 + 70, 953 .vdisplay = 768, 954 .vsync_start = 768 + 14, 955 .vsync_end = 768 + 14 + 42, 956 .vtotal = 768 + 14 + 42, 957 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 958 }; 959 960 static const struct panel_desc auo_b101xtn01 = { 961 .modes = &auo_b101xtn01_mode, 962 .num_modes = 1, 963 .bpc = 6, 964 .size = { 965 .width = 223, 966 .height = 125, 967 }, 968 }; 969 970 static const struct drm_display_mode auo_b116xw03_mode = { 971 .clock = 70589, 972 .hdisplay = 1366, 973 .hsync_start = 1366 + 40, 974 .hsync_end = 1366 + 40 + 40, 975 .htotal = 1366 + 40 + 40 + 32, 976 .vdisplay = 768, 977 .vsync_start = 768 + 10, 978 .vsync_end = 768 + 10 + 12, 979 .vtotal = 768 + 10 + 12 + 6, 980 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 981 }; 982 983 static const struct panel_desc auo_b116xw03 = { 984 .modes = &auo_b116xw03_mode, 985 .num_modes = 1, 986 .bpc = 6, 987 .size = { 988 .width = 256, 989 .height = 144, 990 }, 991 .delay = { 992 .prepare = 1, 993 .enable = 200, 994 .disable = 200, 995 .unprepare = 500, 996 }, 997 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 998 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 999 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1000 }; 1001 1002 static const struct display_timing auo_g070vvn01_timings = { 1003 .pixelclock = { 33300000, 34209000, 45000000 }, 1004 .hactive = { 800, 800, 800 }, 1005 .hfront_porch = { 20, 40, 200 }, 1006 .hback_porch = { 87, 40, 1 }, 1007 .hsync_len = { 1, 48, 87 }, 1008 .vactive = { 480, 480, 480 }, 1009 .vfront_porch = { 5, 13, 200 }, 1010 .vback_porch = { 31, 31, 29 }, 1011 .vsync_len = { 1, 1, 3 }, 1012 }; 1013 1014 static const struct panel_desc auo_g070vvn01 = { 1015 .timings = &auo_g070vvn01_timings, 1016 .num_timings = 1, 1017 .bpc = 8, 1018 .size = { 1019 .width = 152, 1020 .height = 91, 1021 }, 1022 .delay = { 1023 .prepare = 200, 1024 .enable = 50, 1025 .disable = 50, 1026 .unprepare = 1000, 1027 }, 1028 }; 1029 1030 static const struct drm_display_mode auo_g101evn010_mode = { 1031 .clock = 68930, 1032 .hdisplay = 1280, 1033 .hsync_start = 1280 + 82, 1034 .hsync_end = 1280 + 82 + 2, 1035 .htotal = 1280 + 82 + 2 + 84, 1036 .vdisplay = 800, 1037 .vsync_start = 800 + 8, 1038 .vsync_end = 800 + 8 + 2, 1039 .vtotal = 800 + 8 + 2 + 6, 1040 }; 1041 1042 static const struct panel_desc auo_g101evn010 = { 1043 .modes = &auo_g101evn010_mode, 1044 .num_modes = 1, 1045 .bpc = 6, 1046 .size = { 1047 .width = 216, 1048 .height = 135, 1049 }, 1050 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1051 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1052 }; 1053 1054 static const struct drm_display_mode auo_g104sn02_mode = { 1055 .clock = 40000, 1056 .hdisplay = 800, 1057 .hsync_start = 800 + 40, 1058 .hsync_end = 800 + 40 + 216, 1059 .htotal = 800 + 40 + 216 + 128, 1060 .vdisplay = 600, 1061 .vsync_start = 600 + 10, 1062 .vsync_end = 600 + 10 + 35, 1063 .vtotal = 600 + 10 + 35 + 2, 1064 }; 1065 1066 static const struct panel_desc auo_g104sn02 = { 1067 .modes = &auo_g104sn02_mode, 1068 .num_modes = 1, 1069 .bpc = 8, 1070 .size = { 1071 .width = 211, 1072 .height = 158, 1073 }, 1074 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1075 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1076 }; 1077 1078 static const struct drm_display_mode auo_g104stn01_mode = { 1079 .clock = 40000, 1080 .hdisplay = 800, 1081 .hsync_start = 800 + 40, 1082 .hsync_end = 800 + 40 + 88, 1083 .htotal = 800 + 40 + 88 + 128, 1084 .vdisplay = 600, 1085 .vsync_start = 600 + 1, 1086 .vsync_end = 600 + 1 + 23, 1087 .vtotal = 600 + 1 + 23 + 4, 1088 }; 1089 1090 static const struct panel_desc auo_g104stn01 = { 1091 .modes = &auo_g104stn01_mode, 1092 .num_modes = 1, 1093 .bpc = 8, 1094 .size = { 1095 .width = 211, 1096 .height = 158, 1097 }, 1098 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1099 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1100 }; 1101 1102 static const struct display_timing auo_g121ean01_timing = { 1103 .pixelclock = { 60000000, 74400000, 90000000 }, 1104 .hactive = { 1280, 1280, 1280 }, 1105 .hfront_porch = { 20, 50, 100 }, 1106 .hback_porch = { 20, 50, 100 }, 1107 .hsync_len = { 30, 100, 200 }, 1108 .vactive = { 800, 800, 800 }, 1109 .vfront_porch = { 2, 10, 25 }, 1110 .vback_porch = { 2, 10, 25 }, 1111 .vsync_len = { 4, 18, 50 }, 1112 }; 1113 1114 static const struct panel_desc auo_g121ean01 = { 1115 .timings = &auo_g121ean01_timing, 1116 .num_timings = 1, 1117 .bpc = 8, 1118 .size = { 1119 .width = 261, 1120 .height = 163, 1121 }, 1122 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1123 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1124 }; 1125 1126 static const struct display_timing auo_g133han01_timings = { 1127 .pixelclock = { 134000000, 141200000, 149000000 }, 1128 .hactive = { 1920, 1920, 1920 }, 1129 .hfront_porch = { 39, 58, 77 }, 1130 .hback_porch = { 59, 88, 117 }, 1131 .hsync_len = { 28, 42, 56 }, 1132 .vactive = { 1080, 1080, 1080 }, 1133 .vfront_porch = { 3, 8, 11 }, 1134 .vback_porch = { 5, 14, 19 }, 1135 .vsync_len = { 4, 14, 19 }, 1136 }; 1137 1138 static const struct panel_desc auo_g133han01 = { 1139 .timings = &auo_g133han01_timings, 1140 .num_timings = 1, 1141 .bpc = 8, 1142 .size = { 1143 .width = 293, 1144 .height = 165, 1145 }, 1146 .delay = { 1147 .prepare = 200, 1148 .enable = 50, 1149 .disable = 50, 1150 .unprepare = 1000, 1151 }, 1152 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1153 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1154 }; 1155 1156 static const struct display_timing auo_g156han04_timings = { 1157 .pixelclock = { 137000000, 141000000, 146000000 }, 1158 .hactive = { 1920, 1920, 1920 }, 1159 .hfront_porch = { 60, 60, 60 }, 1160 .hback_porch = { 90, 92, 111 }, 1161 .hsync_len = { 32, 32, 32 }, 1162 .vactive = { 1080, 1080, 1080 }, 1163 .vfront_porch = { 12, 12, 12 }, 1164 .vback_porch = { 24, 36, 56 }, 1165 .vsync_len = { 8, 8, 8 }, 1166 }; 1167 1168 static const struct panel_desc auo_g156han04 = { 1169 .timings = &auo_g156han04_timings, 1170 .num_timings = 1, 1171 .bpc = 8, 1172 .size = { 1173 .width = 344, 1174 .height = 194, 1175 }, 1176 .delay = { 1177 .prepare = 50, /* T2 */ 1178 .enable = 200, /* T3 */ 1179 .disable = 110, /* T10 */ 1180 .unprepare = 1000, /* T13 */ 1181 }, 1182 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1183 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1184 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1185 }; 1186 1187 static const struct drm_display_mode auo_g156xtn01_mode = { 1188 .clock = 76000, 1189 .hdisplay = 1366, 1190 .hsync_start = 1366 + 33, 1191 .hsync_end = 1366 + 33 + 67, 1192 .htotal = 1560, 1193 .vdisplay = 768, 1194 .vsync_start = 768 + 4, 1195 .vsync_end = 768 + 4 + 4, 1196 .vtotal = 806, 1197 }; 1198 1199 static const struct panel_desc auo_g156xtn01 = { 1200 .modes = &auo_g156xtn01_mode, 1201 .num_modes = 1, 1202 .bpc = 8, 1203 .size = { 1204 .width = 344, 1205 .height = 194, 1206 }, 1207 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1208 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1209 }; 1210 1211 static const struct display_timing auo_g185han01_timings = { 1212 .pixelclock = { 120000000, 144000000, 175000000 }, 1213 .hactive = { 1920, 1920, 1920 }, 1214 .hfront_porch = { 36, 120, 148 }, 1215 .hback_porch = { 24, 88, 108 }, 1216 .hsync_len = { 20, 48, 64 }, 1217 .vactive = { 1080, 1080, 1080 }, 1218 .vfront_porch = { 6, 10, 40 }, 1219 .vback_porch = { 2, 5, 20 }, 1220 .vsync_len = { 2, 5, 20 }, 1221 }; 1222 1223 static const struct panel_desc auo_g185han01 = { 1224 .timings = &auo_g185han01_timings, 1225 .num_timings = 1, 1226 .bpc = 8, 1227 .size = { 1228 .width = 409, 1229 .height = 230, 1230 }, 1231 .delay = { 1232 .prepare = 50, 1233 .enable = 200, 1234 .disable = 110, 1235 .unprepare = 1000, 1236 }, 1237 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1238 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1239 }; 1240 1241 static const struct display_timing auo_g190ean01_timings = { 1242 .pixelclock = { 90000000, 108000000, 135000000 }, 1243 .hactive = { 1280, 1280, 1280 }, 1244 .hfront_porch = { 126, 184, 1266 }, 1245 .hback_porch = { 84, 122, 844 }, 1246 .hsync_len = { 70, 102, 704 }, 1247 .vactive = { 1024, 1024, 1024 }, 1248 .vfront_porch = { 4, 26, 76 }, 1249 .vback_porch = { 2, 8, 25 }, 1250 .vsync_len = { 2, 8, 25 }, 1251 }; 1252 1253 static const struct panel_desc auo_g190ean01 = { 1254 .timings = &auo_g190ean01_timings, 1255 .num_timings = 1, 1256 .bpc = 8, 1257 .size = { 1258 .width = 376, 1259 .height = 301, 1260 }, 1261 .delay = { 1262 .prepare = 50, 1263 .enable = 200, 1264 .disable = 110, 1265 .unprepare = 1000, 1266 }, 1267 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1268 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1269 }; 1270 1271 static const struct display_timing auo_p320hvn03_timings = { 1272 .pixelclock = { 106000000, 148500000, 164000000 }, 1273 .hactive = { 1920, 1920, 1920 }, 1274 .hfront_porch = { 25, 50, 130 }, 1275 .hback_porch = { 25, 50, 130 }, 1276 .hsync_len = { 20, 40, 105 }, 1277 .vactive = { 1080, 1080, 1080 }, 1278 .vfront_porch = { 8, 17, 150 }, 1279 .vback_porch = { 8, 17, 150 }, 1280 .vsync_len = { 4, 11, 100 }, 1281 }; 1282 1283 static const struct panel_desc auo_p320hvn03 = { 1284 .timings = &auo_p320hvn03_timings, 1285 .num_timings = 1, 1286 .bpc = 8, 1287 .size = { 1288 .width = 698, 1289 .height = 393, 1290 }, 1291 .delay = { 1292 .prepare = 1, 1293 .enable = 450, 1294 .unprepare = 500, 1295 }, 1296 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1297 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1298 }; 1299 1300 static const struct drm_display_mode auo_t215hvn01_mode = { 1301 .clock = 148800, 1302 .hdisplay = 1920, 1303 .hsync_start = 1920 + 88, 1304 .hsync_end = 1920 + 88 + 44, 1305 .htotal = 1920 + 88 + 44 + 148, 1306 .vdisplay = 1080, 1307 .vsync_start = 1080 + 4, 1308 .vsync_end = 1080 + 4 + 5, 1309 .vtotal = 1080 + 4 + 5 + 36, 1310 }; 1311 1312 static const struct panel_desc auo_t215hvn01 = { 1313 .modes = &auo_t215hvn01_mode, 1314 .num_modes = 1, 1315 .bpc = 8, 1316 .size = { 1317 .width = 430, 1318 .height = 270, 1319 }, 1320 .delay = { 1321 .disable = 5, 1322 .unprepare = 1000, 1323 }, 1324 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1325 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1326 }; 1327 1328 static const struct drm_display_mode avic_tm070ddh03_mode = { 1329 .clock = 51200, 1330 .hdisplay = 1024, 1331 .hsync_start = 1024 + 160, 1332 .hsync_end = 1024 + 160 + 4, 1333 .htotal = 1024 + 160 + 4 + 156, 1334 .vdisplay = 600, 1335 .vsync_start = 600 + 17, 1336 .vsync_end = 600 + 17 + 1, 1337 .vtotal = 600 + 17 + 1 + 17, 1338 }; 1339 1340 static const struct panel_desc avic_tm070ddh03 = { 1341 .modes = &avic_tm070ddh03_mode, 1342 .num_modes = 1, 1343 .bpc = 8, 1344 .size = { 1345 .width = 154, 1346 .height = 90, 1347 }, 1348 .delay = { 1349 .prepare = 20, 1350 .enable = 200, 1351 .disable = 200, 1352 }, 1353 }; 1354 1355 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = { 1356 .clock = 30000, 1357 .hdisplay = 800, 1358 .hsync_start = 800 + 40, 1359 .hsync_end = 800 + 40 + 48, 1360 .htotal = 800 + 40 + 48 + 40, 1361 .vdisplay = 480, 1362 .vsync_start = 480 + 13, 1363 .vsync_end = 480 + 13 + 3, 1364 .vtotal = 480 + 13 + 3 + 29, 1365 }; 1366 1367 static const struct panel_desc bananapi_s070wv20_ct16 = { 1368 .modes = &bananapi_s070wv20_ct16_mode, 1369 .num_modes = 1, 1370 .bpc = 6, 1371 .size = { 1372 .width = 154, 1373 .height = 86, 1374 }, 1375 }; 1376 1377 static const struct display_timing boe_av101hdt_a10_timing = { 1378 .pixelclock = { 74210000, 75330000, 76780000, }, 1379 .hactive = { 1280, 1280, 1280, }, 1380 .hfront_porch = { 10, 42, 33, }, 1381 .hback_porch = { 10, 18, 33, }, 1382 .hsync_len = { 30, 10, 30, }, 1383 .vactive = { 720, 720, 720, }, 1384 .vfront_porch = { 200, 183, 200, }, 1385 .vback_porch = { 8, 8, 8, }, 1386 .vsync_len = { 2, 19, 2, }, 1387 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1388 }; 1389 1390 static const struct panel_desc boe_av101hdt_a10 = { 1391 .timings = &boe_av101hdt_a10_timing, 1392 .num_timings = 1, 1393 .bpc = 8, 1394 .size = { 1395 .width = 224, 1396 .height = 126, 1397 }, 1398 .delay = { 1399 .enable = 50, 1400 .disable = 50, 1401 }, 1402 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1403 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1404 }; 1405 1406 static const struct display_timing boe_av123z7m_n17_timing = { 1407 .pixelclock = { 86600000, 88000000, 90800000, }, 1408 .hactive = { 1920, 1920, 1920, }, 1409 .hfront_porch = { 10, 10, 10, }, 1410 .hback_porch = { 10, 10, 10, }, 1411 .hsync_len = { 9, 12, 25, }, 1412 .vactive = { 720, 720, 720, }, 1413 .vfront_porch = { 7, 10, 13, }, 1414 .vback_porch = { 7, 10, 13, }, 1415 .vsync_len = { 7, 11, 14, }, 1416 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1417 }; 1418 1419 static const struct panel_desc boe_av123z7m_n17 = { 1420 .timings = &boe_av123z7m_n17_timing, 1421 .bpc = 8, 1422 .num_timings = 1, 1423 .size = { 1424 .width = 292, 1425 .height = 110, 1426 }, 1427 .delay = { 1428 .prepare = 50, 1429 .disable = 50, 1430 }, 1431 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1432 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1433 }; 1434 1435 static const struct drm_display_mode boe_bp101wx1_100_mode = { 1436 .clock = 78945, 1437 .hdisplay = 1280, 1438 .hsync_start = 1280 + 0, 1439 .hsync_end = 1280 + 0 + 2, 1440 .htotal = 1280 + 62 + 0 + 2, 1441 .vdisplay = 800, 1442 .vsync_start = 800 + 8, 1443 .vsync_end = 800 + 8 + 2, 1444 .vtotal = 800 + 6 + 8 + 2, 1445 }; 1446 1447 static const struct panel_desc boe_bp082wx1_100 = { 1448 .modes = &boe_bp101wx1_100_mode, 1449 .num_modes = 1, 1450 .bpc = 8, 1451 .size = { 1452 .width = 177, 1453 .height = 110, 1454 }, 1455 .delay = { 1456 .enable = 50, 1457 .disable = 50, 1458 }, 1459 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1460 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1461 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1462 }; 1463 1464 static const struct panel_desc boe_bp101wx1_100 = { 1465 .modes = &boe_bp101wx1_100_mode, 1466 .num_modes = 1, 1467 .bpc = 8, 1468 .size = { 1469 .width = 217, 1470 .height = 136, 1471 }, 1472 .delay = { 1473 .enable = 50, 1474 .disable = 50, 1475 }, 1476 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 1477 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1478 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1479 }; 1480 1481 static const struct display_timing boe_ev121wxm_n10_1850_timing = { 1482 .pixelclock = { 69922000, 71000000, 72293000 }, 1483 .hactive = { 1280, 1280, 1280 }, 1484 .hfront_porch = { 48, 48, 48 }, 1485 .hback_porch = { 80, 80, 80 }, 1486 .hsync_len = { 32, 32, 32 }, 1487 .vactive = { 800, 800, 800 }, 1488 .vfront_porch = { 3, 3, 3 }, 1489 .vback_porch = { 14, 14, 14 }, 1490 .vsync_len = { 6, 6, 6 }, 1491 }; 1492 1493 static const struct panel_desc boe_ev121wxm_n10_1850 = { 1494 .timings = &boe_ev121wxm_n10_1850_timing, 1495 .num_timings = 1, 1496 .bpc = 8, 1497 .size = { 1498 .width = 261, 1499 .height = 163, 1500 }, 1501 .delay = { 1502 .prepare = 9, 1503 .enable = 300, 1504 .unprepare = 300, 1505 .disable = 560, 1506 }, 1507 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1508 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1509 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1510 }; 1511 1512 static const struct drm_display_mode boe_hv070wsa_mode = { 1513 .clock = 42105, 1514 .hdisplay = 1024, 1515 .hsync_start = 1024 + 30, 1516 .hsync_end = 1024 + 30 + 30, 1517 .htotal = 1024 + 30 + 30 + 30, 1518 .vdisplay = 600, 1519 .vsync_start = 600 + 10, 1520 .vsync_end = 600 + 10 + 10, 1521 .vtotal = 600 + 10 + 10 + 10, 1522 }; 1523 1524 static const struct panel_desc boe_hv070wsa = { 1525 .modes = &boe_hv070wsa_mode, 1526 .num_modes = 1, 1527 .bpc = 8, 1528 .size = { 1529 .width = 154, 1530 .height = 90, 1531 }, 1532 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1533 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1534 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1535 }; 1536 1537 static const struct display_timing cct_cmt430b19n00_timing = { 1538 .pixelclock = { 8000000, 9000000, 12000000 }, 1539 .hactive = { 480, 480, 480 }, 1540 .hfront_porch = { 2, 8, 75 }, 1541 .hback_porch = { 3, 43, 43 }, 1542 .hsync_len = { 2, 4, 75 }, 1543 .vactive = { 272, 272, 272 }, 1544 .vfront_porch = { 2, 8, 37 }, 1545 .vback_porch = { 2, 12, 12 }, 1546 .vsync_len = { 2, 4, 37 }, 1547 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW 1548 }; 1549 1550 static const struct panel_desc cct_cmt430b19n00 = { 1551 .timings = &cct_cmt430b19n00_timing, 1552 .num_timings = 1, 1553 .bpc = 8, 1554 .size = { 1555 .width = 95, 1556 .height = 53, 1557 }, 1558 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1559 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1560 .connector_type = DRM_MODE_CONNECTOR_DPI, 1561 }; 1562 1563 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = { 1564 .clock = 9000, 1565 .hdisplay = 480, 1566 .hsync_start = 480 + 5, 1567 .hsync_end = 480 + 5 + 5, 1568 .htotal = 480 + 5 + 5 + 40, 1569 .vdisplay = 272, 1570 .vsync_start = 272 + 8, 1571 .vsync_end = 272 + 8 + 8, 1572 .vtotal = 272 + 8 + 8 + 8, 1573 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1574 }; 1575 1576 static const struct panel_desc cdtech_s043wq26h_ct7 = { 1577 .modes = &cdtech_s043wq26h_ct7_mode, 1578 .num_modes = 1, 1579 .bpc = 8, 1580 .size = { 1581 .width = 95, 1582 .height = 54, 1583 }, 1584 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1585 }; 1586 1587 /* S070PWS19HP-FC21 2017/04/22 */ 1588 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = { 1589 .clock = 51200, 1590 .hdisplay = 1024, 1591 .hsync_start = 1024 + 160, 1592 .hsync_end = 1024 + 160 + 20, 1593 .htotal = 1024 + 160 + 20 + 140, 1594 .vdisplay = 600, 1595 .vsync_start = 600 + 12, 1596 .vsync_end = 600 + 12 + 3, 1597 .vtotal = 600 + 12 + 3 + 20, 1598 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1599 }; 1600 1601 static const struct panel_desc cdtech_s070pws19hp_fc21 = { 1602 .modes = &cdtech_s070pws19hp_fc21_mode, 1603 .num_modes = 1, 1604 .bpc = 6, 1605 .size = { 1606 .width = 154, 1607 .height = 86, 1608 }, 1609 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1610 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1611 .connector_type = DRM_MODE_CONNECTOR_DPI, 1612 }; 1613 1614 /* S070SWV29HG-DC44 2017/09/21 */ 1615 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = { 1616 .clock = 33300, 1617 .hdisplay = 800, 1618 .hsync_start = 800 + 210, 1619 .hsync_end = 800 + 210 + 2, 1620 .htotal = 800 + 210 + 2 + 44, 1621 .vdisplay = 480, 1622 .vsync_start = 480 + 22, 1623 .vsync_end = 480 + 22 + 2, 1624 .vtotal = 480 + 22 + 2 + 21, 1625 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1626 }; 1627 1628 static const struct panel_desc cdtech_s070swv29hg_dc44 = { 1629 .modes = &cdtech_s070swv29hg_dc44_mode, 1630 .num_modes = 1, 1631 .bpc = 6, 1632 .size = { 1633 .width = 154, 1634 .height = 86, 1635 }, 1636 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1637 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 1638 .connector_type = DRM_MODE_CONNECTOR_DPI, 1639 }; 1640 1641 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = { 1642 .clock = 35000, 1643 .hdisplay = 800, 1644 .hsync_start = 800 + 40, 1645 .hsync_end = 800 + 40 + 40, 1646 .htotal = 800 + 40 + 40 + 48, 1647 .vdisplay = 480, 1648 .vsync_start = 480 + 29, 1649 .vsync_end = 480 + 29 + 13, 1650 .vtotal = 480 + 29 + 13 + 3, 1651 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1652 }; 1653 1654 static const struct panel_desc cdtech_s070wv95_ct16 = { 1655 .modes = &cdtech_s070wv95_ct16_mode, 1656 .num_modes = 1, 1657 .bpc = 8, 1658 .size = { 1659 .width = 154, 1660 .height = 85, 1661 }, 1662 }; 1663 1664 static const struct display_timing chefree_ch101olhlwh_002_timing = { 1665 .pixelclock = { 68900000, 71100000, 73400000 }, 1666 .hactive = { 1280, 1280, 1280 }, 1667 .hfront_porch = { 65, 80, 95 }, 1668 .hback_porch = { 64, 79, 94 }, 1669 .hsync_len = { 1, 1, 1 }, 1670 .vactive = { 800, 800, 800 }, 1671 .vfront_porch = { 7, 11, 14 }, 1672 .vback_porch = { 7, 11, 14 }, 1673 .vsync_len = { 1, 1, 1 }, 1674 .flags = DISPLAY_FLAGS_DE_HIGH, 1675 }; 1676 1677 static const struct panel_desc chefree_ch101olhlwh_002 = { 1678 .timings = &chefree_ch101olhlwh_002_timing, 1679 .num_timings = 1, 1680 .bpc = 8, 1681 .size = { 1682 .width = 217, 1683 .height = 135, 1684 }, 1685 .delay = { 1686 .enable = 200, 1687 .disable = 200, 1688 }, 1689 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1690 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1691 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1692 }; 1693 1694 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { 1695 .clock = 66770, 1696 .hdisplay = 800, 1697 .hsync_start = 800 + 49, 1698 .hsync_end = 800 + 49 + 33, 1699 .htotal = 800 + 49 + 33 + 17, 1700 .vdisplay = 1280, 1701 .vsync_start = 1280 + 1, 1702 .vsync_end = 1280 + 1 + 7, 1703 .vtotal = 1280 + 1 + 7 + 15, 1704 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1705 }; 1706 1707 static const struct panel_desc chunghwa_claa070wp03xg = { 1708 .modes = &chunghwa_claa070wp03xg_mode, 1709 .num_modes = 1, 1710 .bpc = 6, 1711 .size = { 1712 .width = 94, 1713 .height = 150, 1714 }, 1715 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1716 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1717 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1718 }; 1719 1720 static const struct drm_display_mode chunghwa_claa101wa01a_mode = { 1721 .clock = 72070, 1722 .hdisplay = 1366, 1723 .hsync_start = 1366 + 58, 1724 .hsync_end = 1366 + 58 + 58, 1725 .htotal = 1366 + 58 + 58 + 58, 1726 .vdisplay = 768, 1727 .vsync_start = 768 + 4, 1728 .vsync_end = 768 + 4 + 4, 1729 .vtotal = 768 + 4 + 4 + 4, 1730 }; 1731 1732 static const struct panel_desc chunghwa_claa101wa01a = { 1733 .modes = &chunghwa_claa101wa01a_mode, 1734 .num_modes = 1, 1735 .bpc = 6, 1736 .size = { 1737 .width = 220, 1738 .height = 120, 1739 }, 1740 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1741 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1742 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1743 }; 1744 1745 static const struct drm_display_mode chunghwa_claa101wb01_mode = { 1746 .clock = 69300, 1747 .hdisplay = 1366, 1748 .hsync_start = 1366 + 48, 1749 .hsync_end = 1366 + 48 + 32, 1750 .htotal = 1366 + 48 + 32 + 20, 1751 .vdisplay = 768, 1752 .vsync_start = 768 + 16, 1753 .vsync_end = 768 + 16 + 8, 1754 .vtotal = 768 + 16 + 8 + 16, 1755 }; 1756 1757 static const struct panel_desc chunghwa_claa101wb01 = { 1758 .modes = &chunghwa_claa101wb01_mode, 1759 .num_modes = 1, 1760 .bpc = 6, 1761 .size = { 1762 .width = 223, 1763 .height = 125, 1764 }, 1765 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1766 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 1767 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1768 }; 1769 1770 static const struct display_timing dataimage_fg040346dsswbg04_timing = { 1771 .pixelclock = { 5000000, 9000000, 12000000 }, 1772 .hactive = { 480, 480, 480 }, 1773 .hfront_porch = { 12, 12, 12 }, 1774 .hback_porch = { 12, 12, 12 }, 1775 .hsync_len = { 21, 21, 21 }, 1776 .vactive = { 272, 272, 272 }, 1777 .vfront_porch = { 4, 4, 4 }, 1778 .vback_porch = { 4, 4, 4 }, 1779 .vsync_len = { 8, 8, 8 }, 1780 }; 1781 1782 static const struct panel_desc dataimage_fg040346dsswbg04 = { 1783 .timings = &dataimage_fg040346dsswbg04_timing, 1784 .num_timings = 1, 1785 .bpc = 8, 1786 .size = { 1787 .width = 95, 1788 .height = 54, 1789 }, 1790 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1791 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1792 .connector_type = DRM_MODE_CONNECTOR_DPI, 1793 }; 1794 1795 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = { 1796 .pixelclock = { 68900000, 71110000, 73400000 }, 1797 .hactive = { 1280, 1280, 1280 }, 1798 .vactive = { 800, 800, 800 }, 1799 .hback_porch = { 100, 100, 100 }, 1800 .hfront_porch = { 100, 100, 100 }, 1801 .vback_porch = { 5, 5, 5 }, 1802 .vfront_porch = { 5, 5, 5 }, 1803 .hsync_len = { 24, 24, 24 }, 1804 .vsync_len = { 3, 3, 3 }, 1805 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 1806 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 1807 }; 1808 1809 static const struct panel_desc dataimage_fg1001l0dsswmg01 = { 1810 .timings = &dataimage_fg1001l0dsswmg01_timing, 1811 .num_timings = 1, 1812 .bpc = 8, 1813 .size = { 1814 .width = 217, 1815 .height = 136, 1816 }, 1817 }; 1818 1819 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = { 1820 .clock = 33260, 1821 .hdisplay = 800, 1822 .hsync_start = 800 + 40, 1823 .hsync_end = 800 + 40 + 128, 1824 .htotal = 800 + 40 + 128 + 88, 1825 .vdisplay = 480, 1826 .vsync_start = 480 + 10, 1827 .vsync_end = 480 + 10 + 2, 1828 .vtotal = 480 + 10 + 2 + 33, 1829 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1830 }; 1831 1832 static const struct panel_desc dataimage_scf0700c48ggu18 = { 1833 .modes = &dataimage_scf0700c48ggu18_mode, 1834 .num_modes = 1, 1835 .bpc = 8, 1836 .size = { 1837 .width = 152, 1838 .height = 91, 1839 }, 1840 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1841 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 1842 }; 1843 1844 static const struct display_timing dlc_dlc0700yzg_1_timing = { 1845 .pixelclock = { 45000000, 51200000, 57000000 }, 1846 .hactive = { 1024, 1024, 1024 }, 1847 .hfront_porch = { 100, 106, 113 }, 1848 .hback_porch = { 100, 106, 113 }, 1849 .hsync_len = { 100, 108, 114 }, 1850 .vactive = { 600, 600, 600 }, 1851 .vfront_porch = { 8, 11, 15 }, 1852 .vback_porch = { 8, 11, 15 }, 1853 .vsync_len = { 9, 13, 15 }, 1854 .flags = DISPLAY_FLAGS_DE_HIGH, 1855 }; 1856 1857 static const struct panel_desc dlc_dlc0700yzg_1 = { 1858 .timings = &dlc_dlc0700yzg_1_timing, 1859 .num_timings = 1, 1860 .bpc = 6, 1861 .size = { 1862 .width = 154, 1863 .height = 86, 1864 }, 1865 .delay = { 1866 .prepare = 30, 1867 .enable = 200, 1868 .disable = 200, 1869 }, 1870 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 1871 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1872 }; 1873 1874 static const struct display_timing dlc_dlc1010gig_timing = { 1875 .pixelclock = { 68900000, 71100000, 73400000 }, 1876 .hactive = { 1280, 1280, 1280 }, 1877 .hfront_porch = { 43, 53, 63 }, 1878 .hback_porch = { 43, 53, 63 }, 1879 .hsync_len = { 44, 54, 64 }, 1880 .vactive = { 800, 800, 800 }, 1881 .vfront_porch = { 5, 8, 11 }, 1882 .vback_porch = { 5, 8, 11 }, 1883 .vsync_len = { 5, 7, 11 }, 1884 .flags = DISPLAY_FLAGS_DE_HIGH, 1885 }; 1886 1887 static const struct panel_desc dlc_dlc1010gig = { 1888 .timings = &dlc_dlc1010gig_timing, 1889 .num_timings = 1, 1890 .bpc = 8, 1891 .size = { 1892 .width = 216, 1893 .height = 135, 1894 }, 1895 .delay = { 1896 .prepare = 60, 1897 .enable = 150, 1898 .disable = 100, 1899 .unprepare = 60, 1900 }, 1901 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 1902 .connector_type = DRM_MODE_CONNECTOR_LVDS, 1903 }; 1904 1905 static const struct drm_display_mode edt_et035012dm6_mode = { 1906 .clock = 6500, 1907 .hdisplay = 320, 1908 .hsync_start = 320 + 20, 1909 .hsync_end = 320 + 20 + 30, 1910 .htotal = 320 + 20 + 68, 1911 .vdisplay = 240, 1912 .vsync_start = 240 + 4, 1913 .vsync_end = 240 + 4 + 4, 1914 .vtotal = 240 + 4 + 4 + 14, 1915 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1916 }; 1917 1918 static const struct panel_desc edt_et035012dm6 = { 1919 .modes = &edt_et035012dm6_mode, 1920 .num_modes = 1, 1921 .bpc = 8, 1922 .size = { 1923 .width = 70, 1924 .height = 52, 1925 }, 1926 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1927 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 1928 }; 1929 1930 static const struct drm_display_mode edt_etm0350g0dh6_mode = { 1931 .clock = 6520, 1932 .hdisplay = 320, 1933 .hsync_start = 320 + 20, 1934 .hsync_end = 320 + 20 + 68, 1935 .htotal = 320 + 20 + 68, 1936 .vdisplay = 240, 1937 .vsync_start = 240 + 4, 1938 .vsync_end = 240 + 4 + 18, 1939 .vtotal = 240 + 4 + 18, 1940 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 1941 }; 1942 1943 static const struct panel_desc edt_etm0350g0dh6 = { 1944 .modes = &edt_etm0350g0dh6_mode, 1945 .num_modes = 1, 1946 .bpc = 6, 1947 .size = { 1948 .width = 70, 1949 .height = 53, 1950 }, 1951 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 1952 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 1953 .connector_type = DRM_MODE_CONNECTOR_DPI, 1954 }; 1955 1956 static const struct drm_display_mode edt_etm043080dh6gp_mode = { 1957 .clock = 10870, 1958 .hdisplay = 480, 1959 .hsync_start = 480 + 8, 1960 .hsync_end = 480 + 8 + 4, 1961 .htotal = 480 + 8 + 4 + 41, 1962 1963 /* 1964 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while 1965 * fb_align 1966 */ 1967 1968 .vdisplay = 288, 1969 .vsync_start = 288 + 2, 1970 .vsync_end = 288 + 2 + 4, 1971 .vtotal = 288 + 2 + 4 + 10, 1972 }; 1973 1974 static const struct panel_desc edt_etm043080dh6gp = { 1975 .modes = &edt_etm043080dh6gp_mode, 1976 .num_modes = 1, 1977 .bpc = 8, 1978 .size = { 1979 .width = 100, 1980 .height = 65, 1981 }, 1982 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 1983 .connector_type = DRM_MODE_CONNECTOR_DPI, 1984 }; 1985 1986 static const struct drm_display_mode edt_etm0430g0dh6_mode = { 1987 .clock = 9000, 1988 .hdisplay = 480, 1989 .hsync_start = 480 + 2, 1990 .hsync_end = 480 + 2 + 41, 1991 .htotal = 480 + 2 + 41 + 2, 1992 .vdisplay = 272, 1993 .vsync_start = 272 + 2, 1994 .vsync_end = 272 + 2 + 10, 1995 .vtotal = 272 + 2 + 10 + 2, 1996 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 1997 }; 1998 1999 static const struct panel_desc edt_etm0430g0dh6 = { 2000 .modes = &edt_etm0430g0dh6_mode, 2001 .num_modes = 1, 2002 .bpc = 6, 2003 .size = { 2004 .width = 95, 2005 .height = 54, 2006 }, 2007 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2008 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2009 .connector_type = DRM_MODE_CONNECTOR_DPI, 2010 }; 2011 2012 static const struct drm_display_mode edt_et057090dhu_mode = { 2013 .clock = 25175, 2014 .hdisplay = 640, 2015 .hsync_start = 640 + 16, 2016 .hsync_end = 640 + 16 + 30, 2017 .htotal = 640 + 16 + 30 + 114, 2018 .vdisplay = 480, 2019 .vsync_start = 480 + 10, 2020 .vsync_end = 480 + 10 + 3, 2021 .vtotal = 480 + 10 + 3 + 32, 2022 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2023 }; 2024 2025 static const struct panel_desc edt_et057090dhu = { 2026 .modes = &edt_et057090dhu_mode, 2027 .num_modes = 1, 2028 .bpc = 6, 2029 .size = { 2030 .width = 115, 2031 .height = 86, 2032 }, 2033 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2034 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2035 .connector_type = DRM_MODE_CONNECTOR_DPI, 2036 }; 2037 2038 static const struct drm_display_mode edt_etm0700g0dh6_mode = { 2039 .clock = 33260, 2040 .hdisplay = 800, 2041 .hsync_start = 800 + 40, 2042 .hsync_end = 800 + 40 + 128, 2043 .htotal = 800 + 40 + 128 + 88, 2044 .vdisplay = 480, 2045 .vsync_start = 480 + 10, 2046 .vsync_end = 480 + 10 + 2, 2047 .vtotal = 480 + 10 + 2 + 33, 2048 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2049 }; 2050 2051 static const struct panel_desc edt_etm0700g0dh6 = { 2052 .modes = &edt_etm0700g0dh6_mode, 2053 .num_modes = 1, 2054 .bpc = 6, 2055 .size = { 2056 .width = 152, 2057 .height = 91, 2058 }, 2059 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2060 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2061 .connector_type = DRM_MODE_CONNECTOR_DPI, 2062 }; 2063 2064 static const struct panel_desc edt_etm0700g0bdh6 = { 2065 .modes = &edt_etm0700g0dh6_mode, 2066 .num_modes = 1, 2067 .bpc = 6, 2068 .size = { 2069 .width = 152, 2070 .height = 91, 2071 }, 2072 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 2073 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2074 .connector_type = DRM_MODE_CONNECTOR_DPI, 2075 }; 2076 2077 static const struct display_timing edt_etml0700y5dha_timing = { 2078 .pixelclock = { 40800000, 51200000, 67200000 }, 2079 .hactive = { 1024, 1024, 1024 }, 2080 .hfront_porch = { 30, 106, 125 }, 2081 .hback_porch = { 30, 106, 125 }, 2082 .hsync_len = { 30, 108, 126 }, 2083 .vactive = { 600, 600, 600 }, 2084 .vfront_porch = { 3, 12, 67}, 2085 .vback_porch = { 3, 12, 67 }, 2086 .vsync_len = { 4, 11, 66 }, 2087 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2088 DISPLAY_FLAGS_DE_HIGH, 2089 }; 2090 2091 static const struct panel_desc edt_etml0700y5dha = { 2092 .timings = &edt_etml0700y5dha_timing, 2093 .num_timings = 1, 2094 .bpc = 8, 2095 .size = { 2096 .width = 155, 2097 .height = 86, 2098 }, 2099 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2100 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2101 }; 2102 2103 static const struct display_timing edt_etml1010g3dra_timing = { 2104 .pixelclock = { 66300000, 72400000, 78900000 }, 2105 .hactive = { 1280, 1280, 1280 }, 2106 .hfront_porch = { 12, 72, 132 }, 2107 .hback_porch = { 86, 86, 86 }, 2108 .hsync_len = { 2, 2, 2 }, 2109 .vactive = { 800, 800, 800 }, 2110 .vfront_porch = { 1, 15, 49 }, 2111 .vback_porch = { 21, 21, 21 }, 2112 .vsync_len = { 2, 2, 2 }, 2113 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 2114 DISPLAY_FLAGS_DE_HIGH, 2115 }; 2116 2117 static const struct panel_desc edt_etml1010g3dra = { 2118 .timings = &edt_etml1010g3dra_timing, 2119 .num_timings = 1, 2120 .bpc = 8, 2121 .size = { 2122 .width = 216, 2123 .height = 135, 2124 }, 2125 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2126 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2127 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2128 }; 2129 2130 static const struct drm_display_mode edt_etmv570g2dhu_mode = { 2131 .clock = 25175, 2132 .hdisplay = 640, 2133 .hsync_start = 640, 2134 .hsync_end = 640 + 16, 2135 .htotal = 640 + 16 + 30 + 114, 2136 .vdisplay = 480, 2137 .vsync_start = 480 + 10, 2138 .vsync_end = 480 + 10 + 3, 2139 .vtotal = 480 + 10 + 3 + 35, 2140 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC, 2141 }; 2142 2143 static const struct panel_desc edt_etmv570g2dhu = { 2144 .modes = &edt_etmv570g2dhu_mode, 2145 .num_modes = 1, 2146 .bpc = 6, 2147 .size = { 2148 .width = 115, 2149 .height = 86, 2150 }, 2151 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2152 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 2153 .connector_type = DRM_MODE_CONNECTOR_DPI, 2154 }; 2155 2156 static const struct display_timing eink_vb3300_kca_timing = { 2157 .pixelclock = { 40000000, 40000000, 40000000 }, 2158 .hactive = { 334, 334, 334 }, 2159 .hfront_porch = { 1, 1, 1 }, 2160 .hback_porch = { 1, 1, 1 }, 2161 .hsync_len = { 1, 1, 1 }, 2162 .vactive = { 1405, 1405, 1405 }, 2163 .vfront_porch = { 1, 1, 1 }, 2164 .vback_porch = { 1, 1, 1 }, 2165 .vsync_len = { 1, 1, 1 }, 2166 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2167 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 2168 }; 2169 2170 static const struct panel_desc eink_vb3300_kca = { 2171 .timings = &eink_vb3300_kca_timing, 2172 .num_timings = 1, 2173 .bpc = 6, 2174 .size = { 2175 .width = 157, 2176 .height = 209, 2177 }, 2178 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2179 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2180 .connector_type = DRM_MODE_CONNECTOR_DPI, 2181 }; 2182 2183 static const struct display_timing evervision_vgg644804_timing = { 2184 .pixelclock = { 25175000, 25175000, 25175000 }, 2185 .hactive = { 640, 640, 640 }, 2186 .hfront_porch = { 16, 16, 16 }, 2187 .hback_porch = { 82, 114, 170 }, 2188 .hsync_len = { 5, 30, 30 }, 2189 .vactive = { 480, 480, 480 }, 2190 .vfront_porch = { 10, 10, 10 }, 2191 .vback_porch = { 30, 32, 34 }, 2192 .vsync_len = { 1, 3, 5 }, 2193 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 2194 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 2195 DISPLAY_FLAGS_SYNC_POSEDGE, 2196 }; 2197 2198 static const struct panel_desc evervision_vgg644804 = { 2199 .timings = &evervision_vgg644804_timing, 2200 .num_timings = 1, 2201 .bpc = 8, 2202 .size = { 2203 .width = 115, 2204 .height = 86, 2205 }, 2206 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2207 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2208 }; 2209 2210 static const struct display_timing evervision_vgg804821_timing = { 2211 .pixelclock = { 27600000, 33300000, 50000000 }, 2212 .hactive = { 800, 800, 800 }, 2213 .hfront_porch = { 40, 66, 70 }, 2214 .hback_porch = { 40, 67, 70 }, 2215 .hsync_len = { 40, 67, 70 }, 2216 .vactive = { 480, 480, 480 }, 2217 .vfront_porch = { 6, 10, 10 }, 2218 .vback_porch = { 7, 11, 11 }, 2219 .vsync_len = { 7, 11, 11 }, 2220 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | 2221 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 2222 DISPLAY_FLAGS_SYNC_NEGEDGE, 2223 }; 2224 2225 static const struct panel_desc evervision_vgg804821 = { 2226 .timings = &evervision_vgg804821_timing, 2227 .num_timings = 1, 2228 .bpc = 8, 2229 .size = { 2230 .width = 108, 2231 .height = 64, 2232 }, 2233 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2234 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2235 }; 2236 2237 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = { 2238 .clock = 32260, 2239 .hdisplay = 800, 2240 .hsync_start = 800 + 168, 2241 .hsync_end = 800 + 168 + 64, 2242 .htotal = 800 + 168 + 64 + 88, 2243 .vdisplay = 480, 2244 .vsync_start = 480 + 37, 2245 .vsync_end = 480 + 37 + 2, 2246 .vtotal = 480 + 37 + 2 + 8, 2247 }; 2248 2249 static const struct panel_desc foxlink_fl500wvr00_a0t = { 2250 .modes = &foxlink_fl500wvr00_a0t_mode, 2251 .num_modes = 1, 2252 .bpc = 8, 2253 .size = { 2254 .width = 108, 2255 .height = 65, 2256 }, 2257 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2258 }; 2259 2260 static const struct drm_display_mode frida_frd350h54004_modes[] = { 2261 { /* 60 Hz */ 2262 .clock = 6000, 2263 .hdisplay = 320, 2264 .hsync_start = 320 + 44, 2265 .hsync_end = 320 + 44 + 16, 2266 .htotal = 320 + 44 + 16 + 20, 2267 .vdisplay = 240, 2268 .vsync_start = 240 + 2, 2269 .vsync_end = 240 + 2 + 6, 2270 .vtotal = 240 + 2 + 6 + 2, 2271 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2272 }, 2273 { /* 50 Hz */ 2274 .clock = 5400, 2275 .hdisplay = 320, 2276 .hsync_start = 320 + 56, 2277 .hsync_end = 320 + 56 + 16, 2278 .htotal = 320 + 56 + 16 + 40, 2279 .vdisplay = 240, 2280 .vsync_start = 240 + 2, 2281 .vsync_end = 240 + 2 + 6, 2282 .vtotal = 240 + 2 + 6 + 2, 2283 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2284 }, 2285 }; 2286 2287 static const struct panel_desc frida_frd350h54004 = { 2288 .modes = frida_frd350h54004_modes, 2289 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes), 2290 .bpc = 8, 2291 .size = { 2292 .width = 77, 2293 .height = 64, 2294 }, 2295 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2296 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 2297 .connector_type = DRM_MODE_CONNECTOR_DPI, 2298 }; 2299 2300 static const struct drm_display_mode friendlyarm_hd702e_mode = { 2301 .clock = 67185, 2302 .hdisplay = 800, 2303 .hsync_start = 800 + 20, 2304 .hsync_end = 800 + 20 + 24, 2305 .htotal = 800 + 20 + 24 + 20, 2306 .vdisplay = 1280, 2307 .vsync_start = 1280 + 4, 2308 .vsync_end = 1280 + 4 + 8, 2309 .vtotal = 1280 + 4 + 8 + 4, 2310 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 2311 }; 2312 2313 static const struct panel_desc friendlyarm_hd702e = { 2314 .modes = &friendlyarm_hd702e_mode, 2315 .num_modes = 1, 2316 .size = { 2317 .width = 94, 2318 .height = 151, 2319 }, 2320 }; 2321 2322 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { 2323 .clock = 9000, 2324 .hdisplay = 480, 2325 .hsync_start = 480 + 5, 2326 .hsync_end = 480 + 5 + 1, 2327 .htotal = 480 + 5 + 1 + 40, 2328 .vdisplay = 272, 2329 .vsync_start = 272 + 8, 2330 .vsync_end = 272 + 8 + 1, 2331 .vtotal = 272 + 8 + 1 + 8, 2332 }; 2333 2334 static const struct panel_desc giantplus_gpg482739qs5 = { 2335 .modes = &giantplus_gpg482739qs5_mode, 2336 .num_modes = 1, 2337 .bpc = 8, 2338 .size = { 2339 .width = 95, 2340 .height = 54, 2341 }, 2342 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2343 }; 2344 2345 static const struct display_timing giantplus_gpm940b0_timing = { 2346 .pixelclock = { 13500000, 27000000, 27500000 }, 2347 .hactive = { 320, 320, 320 }, 2348 .hfront_porch = { 14, 686, 718 }, 2349 .hback_porch = { 50, 70, 255 }, 2350 .hsync_len = { 1, 1, 1 }, 2351 .vactive = { 240, 240, 240 }, 2352 .vfront_porch = { 1, 1, 179 }, 2353 .vback_porch = { 1, 21, 31 }, 2354 .vsync_len = { 1, 1, 6 }, 2355 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2356 }; 2357 2358 static const struct panel_desc giantplus_gpm940b0 = { 2359 .timings = &giantplus_gpm940b0_timing, 2360 .num_timings = 1, 2361 .bpc = 8, 2362 .size = { 2363 .width = 60, 2364 .height = 45, 2365 }, 2366 .bus_format = MEDIA_BUS_FMT_RGB888_3X8, 2367 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 2368 }; 2369 2370 static const struct display_timing hannstar_hsd070pww1_timing = { 2371 .pixelclock = { 64300000, 71100000, 82000000 }, 2372 .hactive = { 1280, 1280, 1280 }, 2373 .hfront_porch = { 1, 1, 10 }, 2374 .hback_porch = { 1, 1, 10 }, 2375 /* 2376 * According to the data sheet, the minimum horizontal blanking interval 2377 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the 2378 * minimum working horizontal blanking interval to be 60 clocks. 2379 */ 2380 .hsync_len = { 58, 158, 661 }, 2381 .vactive = { 800, 800, 800 }, 2382 .vfront_porch = { 1, 1, 10 }, 2383 .vback_porch = { 1, 1, 10 }, 2384 .vsync_len = { 1, 21, 203 }, 2385 .flags = DISPLAY_FLAGS_DE_HIGH, 2386 }; 2387 2388 static const struct panel_desc hannstar_hsd070pww1 = { 2389 .timings = &hannstar_hsd070pww1_timing, 2390 .num_timings = 1, 2391 .bpc = 6, 2392 .size = { 2393 .width = 151, 2394 .height = 94, 2395 }, 2396 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2397 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2398 }; 2399 2400 static const struct display_timing hannstar_hsd100pxn1_timing = { 2401 .pixelclock = { 55000000, 65000000, 75000000 }, 2402 .hactive = { 1024, 1024, 1024 }, 2403 .hfront_porch = { 40, 40, 40 }, 2404 .hback_porch = { 220, 220, 220 }, 2405 .hsync_len = { 20, 60, 100 }, 2406 .vactive = { 768, 768, 768 }, 2407 .vfront_porch = { 7, 7, 7 }, 2408 .vback_porch = { 21, 21, 21 }, 2409 .vsync_len = { 10, 10, 10 }, 2410 .flags = DISPLAY_FLAGS_DE_HIGH, 2411 }; 2412 2413 static const struct panel_desc hannstar_hsd100pxn1 = { 2414 .timings = &hannstar_hsd100pxn1_timing, 2415 .num_timings = 1, 2416 .bpc = 6, 2417 .size = { 2418 .width = 203, 2419 .height = 152, 2420 }, 2421 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2422 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2423 }; 2424 2425 static const struct display_timing hannstar_hsd101pww2_timing = { 2426 .pixelclock = { 64300000, 71100000, 82000000 }, 2427 .hactive = { 1280, 1280, 1280 }, 2428 .hfront_porch = { 1, 1, 10 }, 2429 .hback_porch = { 1, 1, 10 }, 2430 .hsync_len = { 58, 158, 661 }, 2431 .vactive = { 800, 800, 800 }, 2432 .vfront_porch = { 1, 1, 10 }, 2433 .vback_porch = { 1, 1, 10 }, 2434 .vsync_len = { 1, 21, 203 }, 2435 .flags = DISPLAY_FLAGS_DE_HIGH, 2436 }; 2437 2438 static const struct panel_desc hannstar_hsd101pww2 = { 2439 .timings = &hannstar_hsd101pww2_timing, 2440 .num_timings = 1, 2441 .bpc = 8, 2442 .size = { 2443 .width = 217, 2444 .height = 136, 2445 }, 2446 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2447 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2448 }; 2449 2450 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = { 2451 .clock = 33333, 2452 .hdisplay = 800, 2453 .hsync_start = 800 + 85, 2454 .hsync_end = 800 + 85 + 86, 2455 .htotal = 800 + 85 + 86 + 85, 2456 .vdisplay = 480, 2457 .vsync_start = 480 + 16, 2458 .vsync_end = 480 + 16 + 13, 2459 .vtotal = 480 + 16 + 13 + 16, 2460 }; 2461 2462 static const struct panel_desc hitachi_tx23d38vm0caa = { 2463 .modes = &hitachi_tx23d38vm0caa_mode, 2464 .num_modes = 1, 2465 .bpc = 6, 2466 .size = { 2467 .width = 195, 2468 .height = 117, 2469 }, 2470 .delay = { 2471 .enable = 160, 2472 .disable = 160, 2473 }, 2474 }; 2475 2476 static const struct drm_display_mode innolux_at043tn24_mode = { 2477 .clock = 9000, 2478 .hdisplay = 480, 2479 .hsync_start = 480 + 2, 2480 .hsync_end = 480 + 2 + 41, 2481 .htotal = 480 + 2 + 41 + 2, 2482 .vdisplay = 272, 2483 .vsync_start = 272 + 2, 2484 .vsync_end = 272 + 2 + 10, 2485 .vtotal = 272 + 2 + 10 + 2, 2486 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 2487 }; 2488 2489 static const struct panel_desc innolux_at043tn24 = { 2490 .modes = &innolux_at043tn24_mode, 2491 .num_modes = 1, 2492 .bpc = 8, 2493 .size = { 2494 .width = 95, 2495 .height = 54, 2496 }, 2497 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2498 .connector_type = DRM_MODE_CONNECTOR_DPI, 2499 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2500 }; 2501 2502 static const struct drm_display_mode innolux_at070tn92_mode = { 2503 .clock = 33333, 2504 .hdisplay = 800, 2505 .hsync_start = 800 + 210, 2506 .hsync_end = 800 + 210 + 20, 2507 .htotal = 800 + 210 + 20 + 46, 2508 .vdisplay = 480, 2509 .vsync_start = 480 + 22, 2510 .vsync_end = 480 + 22 + 10, 2511 .vtotal = 480 + 22 + 23 + 10, 2512 }; 2513 2514 static const struct panel_desc innolux_at070tn92 = { 2515 .modes = &innolux_at070tn92_mode, 2516 .num_modes = 1, 2517 .size = { 2518 .width = 154, 2519 .height = 86, 2520 }, 2521 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2522 }; 2523 2524 static const struct display_timing innolux_g070ace_l01_timing = { 2525 .pixelclock = { 25200000, 35000000, 35700000 }, 2526 .hactive = { 800, 800, 800 }, 2527 .hfront_porch = { 30, 32, 87 }, 2528 .hback_porch = { 30, 32, 87 }, 2529 .hsync_len = { 1, 1, 1 }, 2530 .vactive = { 480, 480, 480 }, 2531 .vfront_porch = { 3, 3, 3 }, 2532 .vback_porch = { 13, 13, 13 }, 2533 .vsync_len = { 1, 1, 4 }, 2534 .flags = DISPLAY_FLAGS_DE_HIGH, 2535 }; 2536 2537 static const struct panel_desc innolux_g070ace_l01 = { 2538 .timings = &innolux_g070ace_l01_timing, 2539 .num_timings = 1, 2540 .bpc = 8, 2541 .size = { 2542 .width = 152, 2543 .height = 91, 2544 }, 2545 .delay = { 2546 .prepare = 10, 2547 .enable = 50, 2548 .disable = 50, 2549 .unprepare = 500, 2550 }, 2551 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2552 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2553 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2554 }; 2555 2556 static const struct display_timing innolux_g070y2_l01_timing = { 2557 .pixelclock = { 28000000, 29500000, 32000000 }, 2558 .hactive = { 800, 800, 800 }, 2559 .hfront_porch = { 61, 91, 141 }, 2560 .hback_porch = { 60, 90, 140 }, 2561 .hsync_len = { 12, 12, 12 }, 2562 .vactive = { 480, 480, 480 }, 2563 .vfront_porch = { 4, 9, 30 }, 2564 .vback_porch = { 4, 8, 28 }, 2565 .vsync_len = { 2, 2, 2 }, 2566 .flags = DISPLAY_FLAGS_DE_HIGH, 2567 }; 2568 2569 static const struct panel_desc innolux_g070y2_l01 = { 2570 .timings = &innolux_g070y2_l01_timing, 2571 .num_timings = 1, 2572 .bpc = 8, 2573 .size = { 2574 .width = 152, 2575 .height = 91, 2576 }, 2577 .delay = { 2578 .prepare = 10, 2579 .enable = 100, 2580 .disable = 100, 2581 .unprepare = 800, 2582 }, 2583 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2584 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2585 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2586 }; 2587 2588 static const struct display_timing innolux_g070ace_lh3_timing = { 2589 .pixelclock = { 25200000, 25400000, 35700000 }, 2590 .hactive = { 800, 800, 800 }, 2591 .hfront_porch = { 30, 32, 87 }, 2592 .hback_porch = { 29, 31, 86 }, 2593 .hsync_len = { 1, 1, 1 }, 2594 .vactive = { 480, 480, 480 }, 2595 .vfront_porch = { 4, 5, 65 }, 2596 .vback_porch = { 3, 4, 65 }, 2597 .vsync_len = { 1, 1, 1 }, 2598 .flags = DISPLAY_FLAGS_DE_HIGH, 2599 }; 2600 2601 static const struct panel_desc innolux_g070ace_lh3 = { 2602 .timings = &innolux_g070ace_lh3_timing, 2603 .num_timings = 1, 2604 .bpc = 8, 2605 .size = { 2606 .width = 152, 2607 .height = 91, 2608 }, 2609 .delay = { 2610 .prepare = 10, 2611 .enable = 450, 2612 .disable = 200, 2613 .unprepare = 510, 2614 }, 2615 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2616 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2617 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2618 }; 2619 2620 static const struct drm_display_mode innolux_g070y2_t02_mode = { 2621 .clock = 33333, 2622 .hdisplay = 800, 2623 .hsync_start = 800 + 210, 2624 .hsync_end = 800 + 210 + 20, 2625 .htotal = 800 + 210 + 20 + 46, 2626 .vdisplay = 480, 2627 .vsync_start = 480 + 22, 2628 .vsync_end = 480 + 22 + 10, 2629 .vtotal = 480 + 22 + 23 + 10, 2630 }; 2631 2632 static const struct panel_desc innolux_g070y2_t02 = { 2633 .modes = &innolux_g070y2_t02_mode, 2634 .num_modes = 1, 2635 .bpc = 8, 2636 .size = { 2637 .width = 152, 2638 .height = 92, 2639 }, 2640 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2641 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 2642 .connector_type = DRM_MODE_CONNECTOR_DPI, 2643 }; 2644 2645 static const struct display_timing innolux_g101ice_l01_timing = { 2646 .pixelclock = { 60400000, 71100000, 74700000 }, 2647 .hactive = { 1280, 1280, 1280 }, 2648 .hfront_porch = { 30, 60, 70 }, 2649 .hback_porch = { 30, 60, 70 }, 2650 .hsync_len = { 22, 40, 60 }, 2651 .vactive = { 800, 800, 800 }, 2652 .vfront_porch = { 3, 8, 14 }, 2653 .vback_porch = { 3, 8, 14 }, 2654 .vsync_len = { 4, 7, 12 }, 2655 .flags = DISPLAY_FLAGS_DE_HIGH, 2656 }; 2657 2658 static const struct panel_desc innolux_g101ice_l01 = { 2659 .timings = &innolux_g101ice_l01_timing, 2660 .num_timings = 1, 2661 .bpc = 8, 2662 .size = { 2663 .width = 217, 2664 .height = 135, 2665 }, 2666 .delay = { 2667 .enable = 200, 2668 .disable = 200, 2669 }, 2670 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2671 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2672 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2673 }; 2674 2675 static const struct display_timing innolux_g121i1_l01_timing = { 2676 .pixelclock = { 67450000, 71000000, 74550000 }, 2677 .hactive = { 1280, 1280, 1280 }, 2678 .hfront_porch = { 40, 80, 160 }, 2679 .hback_porch = { 39, 79, 159 }, 2680 .hsync_len = { 1, 1, 1 }, 2681 .vactive = { 800, 800, 800 }, 2682 .vfront_porch = { 5, 11, 100 }, 2683 .vback_porch = { 4, 11, 99 }, 2684 .vsync_len = { 1, 1, 1 }, 2685 }; 2686 2687 static const struct panel_desc innolux_g121i1_l01 = { 2688 .timings = &innolux_g121i1_l01_timing, 2689 .num_timings = 1, 2690 .bpc = 6, 2691 .size = { 2692 .width = 261, 2693 .height = 163, 2694 }, 2695 .delay = { 2696 .enable = 200, 2697 .disable = 20, 2698 }, 2699 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2700 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2701 }; 2702 2703 static const struct display_timing innolux_g121x1_l03_timings = { 2704 .pixelclock = { 57500000, 64900000, 74400000 }, 2705 .hactive = { 1024, 1024, 1024 }, 2706 .hfront_porch = { 90, 140, 190 }, 2707 .hback_porch = { 90, 140, 190 }, 2708 .hsync_len = { 36, 40, 60 }, 2709 .vactive = { 768, 768, 768 }, 2710 .vfront_porch = { 2, 15, 30 }, 2711 .vback_porch = { 2, 15, 30 }, 2712 .vsync_len = { 2, 8, 20 }, 2713 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 2714 }; 2715 2716 static const struct panel_desc innolux_g121x1_l03 = { 2717 .timings = &innolux_g121x1_l03_timings, 2718 .num_timings = 1, 2719 .bpc = 6, 2720 .size = { 2721 .width = 246, 2722 .height = 185, 2723 }, 2724 .delay = { 2725 .enable = 200, 2726 .unprepare = 200, 2727 .disable = 400, 2728 }, 2729 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2730 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2731 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2732 }; 2733 2734 static const struct panel_desc innolux_g121xce_l01 = { 2735 .timings = &innolux_g121x1_l03_timings, 2736 .num_timings = 1, 2737 .bpc = 8, 2738 .size = { 2739 .width = 246, 2740 .height = 185, 2741 }, 2742 .delay = { 2743 .enable = 200, 2744 .unprepare = 200, 2745 .disable = 400, 2746 }, 2747 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2748 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2749 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2750 }; 2751 2752 static const struct display_timing innolux_g156hce_l01_timings = { 2753 .pixelclock = { 120000000, 141860000, 150000000 }, 2754 .hactive = { 1920, 1920, 1920 }, 2755 .hfront_porch = { 80, 90, 100 }, 2756 .hback_porch = { 80, 90, 100 }, 2757 .hsync_len = { 20, 30, 30 }, 2758 .vactive = { 1080, 1080, 1080 }, 2759 .vfront_porch = { 3, 10, 20 }, 2760 .vback_porch = { 3, 10, 20 }, 2761 .vsync_len = { 4, 10, 10 }, 2762 }; 2763 2764 static const struct panel_desc innolux_g156hce_l01 = { 2765 .timings = &innolux_g156hce_l01_timings, 2766 .num_timings = 1, 2767 .bpc = 8, 2768 .size = { 2769 .width = 344, 2770 .height = 194, 2771 }, 2772 .delay = { 2773 .prepare = 1, /* T1+T2 */ 2774 .enable = 450, /* T5 */ 2775 .disable = 200, /* T6 */ 2776 .unprepare = 10, /* T3+T7 */ 2777 }, 2778 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2779 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2780 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2781 }; 2782 2783 static const struct drm_display_mode innolux_n156bge_l21_mode = { 2784 .clock = 69300, 2785 .hdisplay = 1366, 2786 .hsync_start = 1366 + 16, 2787 .hsync_end = 1366 + 16 + 34, 2788 .htotal = 1366 + 16 + 34 + 50, 2789 .vdisplay = 768, 2790 .vsync_start = 768 + 2, 2791 .vsync_end = 768 + 2 + 6, 2792 .vtotal = 768 + 2 + 6 + 12, 2793 }; 2794 2795 static const struct panel_desc innolux_n156bge_l21 = { 2796 .modes = &innolux_n156bge_l21_mode, 2797 .num_modes = 1, 2798 .bpc = 6, 2799 .size = { 2800 .width = 344, 2801 .height = 193, 2802 }, 2803 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2804 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2805 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2806 }; 2807 2808 static const struct drm_display_mode innolux_zj070na_01p_mode = { 2809 .clock = 51501, 2810 .hdisplay = 1024, 2811 .hsync_start = 1024 + 128, 2812 .hsync_end = 1024 + 128 + 64, 2813 .htotal = 1024 + 128 + 64 + 128, 2814 .vdisplay = 600, 2815 .vsync_start = 600 + 16, 2816 .vsync_end = 600 + 16 + 4, 2817 .vtotal = 600 + 16 + 4 + 16, 2818 }; 2819 2820 static const struct panel_desc innolux_zj070na_01p = { 2821 .modes = &innolux_zj070na_01p_mode, 2822 .num_modes = 1, 2823 .bpc = 6, 2824 .size = { 2825 .width = 154, 2826 .height = 90, 2827 }, 2828 }; 2829 2830 static const struct display_timing koe_tx14d24vm1bpa_timing = { 2831 .pixelclock = { 5580000, 5850000, 6200000 }, 2832 .hactive = { 320, 320, 320 }, 2833 .hfront_porch = { 30, 30, 30 }, 2834 .hback_porch = { 30, 30, 30 }, 2835 .hsync_len = { 1, 5, 17 }, 2836 .vactive = { 240, 240, 240 }, 2837 .vfront_porch = { 6, 6, 6 }, 2838 .vback_porch = { 5, 5, 5 }, 2839 .vsync_len = { 1, 2, 11 }, 2840 .flags = DISPLAY_FLAGS_DE_HIGH, 2841 }; 2842 2843 static const struct panel_desc koe_tx14d24vm1bpa = { 2844 .timings = &koe_tx14d24vm1bpa_timing, 2845 .num_timings = 1, 2846 .bpc = 6, 2847 .size = { 2848 .width = 115, 2849 .height = 86, 2850 }, 2851 }; 2852 2853 static const struct display_timing koe_tx26d202vm0bwa_timing = { 2854 .pixelclock = { 151820000, 156720000, 159780000 }, 2855 .hactive = { 1920, 1920, 1920 }, 2856 .hfront_porch = { 105, 130, 142 }, 2857 .hback_porch = { 45, 70, 82 }, 2858 .hsync_len = { 30, 30, 30 }, 2859 .vactive = { 1200, 1200, 1200}, 2860 .vfront_porch = { 3, 5, 10 }, 2861 .vback_porch = { 2, 5, 10 }, 2862 .vsync_len = { 5, 5, 5 }, 2863 .flags = DISPLAY_FLAGS_DE_HIGH, 2864 }; 2865 2866 static const struct panel_desc koe_tx26d202vm0bwa = { 2867 .timings = &koe_tx26d202vm0bwa_timing, 2868 .num_timings = 1, 2869 .bpc = 8, 2870 .size = { 2871 .width = 217, 2872 .height = 136, 2873 }, 2874 .delay = { 2875 .prepare = 1000, 2876 .enable = 1000, 2877 .unprepare = 1000, 2878 .disable = 1000, 2879 }, 2880 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2881 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 2882 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2883 }; 2884 2885 static const struct display_timing koe_tx31d200vm0baa_timing = { 2886 .pixelclock = { 39600000, 43200000, 48000000 }, 2887 .hactive = { 1280, 1280, 1280 }, 2888 .hfront_porch = { 16, 36, 56 }, 2889 .hback_porch = { 16, 36, 56 }, 2890 .hsync_len = { 8, 8, 8 }, 2891 .vactive = { 480, 480, 480 }, 2892 .vfront_porch = { 6, 21, 33 }, 2893 .vback_porch = { 6, 21, 33 }, 2894 .vsync_len = { 8, 8, 8 }, 2895 .flags = DISPLAY_FLAGS_DE_HIGH, 2896 }; 2897 2898 static const struct panel_desc koe_tx31d200vm0baa = { 2899 .timings = &koe_tx31d200vm0baa_timing, 2900 .num_timings = 1, 2901 .bpc = 6, 2902 .size = { 2903 .width = 292, 2904 .height = 109, 2905 }, 2906 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 2907 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2908 }; 2909 2910 static const struct display_timing kyo_tcg121xglp_timing = { 2911 .pixelclock = { 52000000, 65000000, 71000000 }, 2912 .hactive = { 1024, 1024, 1024 }, 2913 .hfront_porch = { 2, 2, 2 }, 2914 .hback_porch = { 2, 2, 2 }, 2915 .hsync_len = { 86, 124, 244 }, 2916 .vactive = { 768, 768, 768 }, 2917 .vfront_porch = { 2, 2, 2 }, 2918 .vback_porch = { 2, 2, 2 }, 2919 .vsync_len = { 6, 34, 73 }, 2920 .flags = DISPLAY_FLAGS_DE_HIGH, 2921 }; 2922 2923 static const struct panel_desc kyo_tcg121xglp = { 2924 .timings = &kyo_tcg121xglp_timing, 2925 .num_timings = 1, 2926 .bpc = 8, 2927 .size = { 2928 .width = 246, 2929 .height = 184, 2930 }, 2931 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2932 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2933 }; 2934 2935 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = { 2936 .clock = 7000, 2937 .hdisplay = 320, 2938 .hsync_start = 320 + 20, 2939 .hsync_end = 320 + 20 + 30, 2940 .htotal = 320 + 20 + 30 + 38, 2941 .vdisplay = 240, 2942 .vsync_start = 240 + 4, 2943 .vsync_end = 240 + 4 + 3, 2944 .vtotal = 240 + 4 + 3 + 15, 2945 }; 2946 2947 static const struct panel_desc lemaker_bl035_rgb_002 = { 2948 .modes = &lemaker_bl035_rgb_002_mode, 2949 .num_modes = 1, 2950 .size = { 2951 .width = 70, 2952 .height = 52, 2953 }, 2954 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 2955 .bus_flags = DRM_BUS_FLAG_DE_LOW, 2956 }; 2957 2958 static const struct display_timing lg_lb070wv8_timing = { 2959 .pixelclock = { 31950000, 33260000, 34600000 }, 2960 .hactive = { 800, 800, 800 }, 2961 .hfront_porch = { 88, 88, 88 }, 2962 .hback_porch = { 88, 88, 88 }, 2963 .hsync_len = { 80, 80, 80 }, 2964 .vactive = { 480, 480, 480 }, 2965 .vfront_porch = { 10, 10, 10 }, 2966 .vback_porch = { 10, 10, 10 }, 2967 .vsync_len = { 25, 25, 25 }, 2968 }; 2969 2970 static const struct panel_desc lg_lb070wv8 = { 2971 .timings = &lg_lb070wv8_timing, 2972 .num_timings = 1, 2973 .bpc = 8, 2974 .size = { 2975 .width = 151, 2976 .height = 91, 2977 }, 2978 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 2979 .connector_type = DRM_MODE_CONNECTOR_LVDS, 2980 }; 2981 2982 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = { 2983 .clock = 155127, 2984 .hdisplay = 1920, 2985 .hsync_start = 1920 + 128, 2986 .hsync_end = 1920 + 128 + 20, 2987 .htotal = 1920 + 128 + 20 + 12, 2988 .vdisplay = 1200, 2989 .vsync_start = 1200 + 19, 2990 .vsync_end = 1200 + 19 + 4, 2991 .vtotal = 1200 + 19 + 4 + 20, 2992 }; 2993 2994 static const struct panel_desc lincolntech_lcd185_101ct = { 2995 .modes = &lincolntech_lcd185_101ct_mode, 2996 .bpc = 8, 2997 .num_modes = 1, 2998 .size = { 2999 .width = 217, 3000 .height = 136, 3001 }, 3002 .delay = { 3003 .prepare = 50, 3004 .disable = 50, 3005 }, 3006 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3007 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3008 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3009 }; 3010 3011 static const struct display_timing logictechno_lt161010_2nh_timing = { 3012 .pixelclock = { 26400000, 33300000, 46800000 }, 3013 .hactive = { 800, 800, 800 }, 3014 .hfront_porch = { 16, 210, 354 }, 3015 .hback_porch = { 46, 46, 46 }, 3016 .hsync_len = { 1, 20, 40 }, 3017 .vactive = { 480, 480, 480 }, 3018 .vfront_porch = { 7, 22, 147 }, 3019 .vback_porch = { 23, 23, 23 }, 3020 .vsync_len = { 1, 10, 20 }, 3021 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3022 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3023 DISPLAY_FLAGS_SYNC_POSEDGE, 3024 }; 3025 3026 static const struct panel_desc logictechno_lt161010_2nh = { 3027 .timings = &logictechno_lt161010_2nh_timing, 3028 .num_timings = 1, 3029 .bpc = 6, 3030 .size = { 3031 .width = 154, 3032 .height = 86, 3033 }, 3034 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3035 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3036 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3037 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3038 .connector_type = DRM_MODE_CONNECTOR_DPI, 3039 }; 3040 3041 static const struct display_timing logictechno_lt170410_2whc_timing = { 3042 .pixelclock = { 68900000, 71100000, 73400000 }, 3043 .hactive = { 1280, 1280, 1280 }, 3044 .hfront_porch = { 23, 60, 71 }, 3045 .hback_porch = { 23, 60, 71 }, 3046 .hsync_len = { 15, 40, 47 }, 3047 .vactive = { 800, 800, 800 }, 3048 .vfront_porch = { 5, 7, 10 }, 3049 .vback_porch = { 5, 7, 10 }, 3050 .vsync_len = { 6, 9, 12 }, 3051 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3052 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3053 DISPLAY_FLAGS_SYNC_POSEDGE, 3054 }; 3055 3056 static const struct panel_desc logictechno_lt170410_2whc = { 3057 .timings = &logictechno_lt170410_2whc_timing, 3058 .num_timings = 1, 3059 .bpc = 8, 3060 .size = { 3061 .width = 217, 3062 .height = 136, 3063 }, 3064 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3065 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3066 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3067 }; 3068 3069 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = { 3070 .clock = 33000, 3071 .hdisplay = 800, 3072 .hsync_start = 800 + 112, 3073 .hsync_end = 800 + 112 + 3, 3074 .htotal = 800 + 112 + 3 + 85, 3075 .vdisplay = 480, 3076 .vsync_start = 480 + 38, 3077 .vsync_end = 480 + 38 + 3, 3078 .vtotal = 480 + 38 + 3 + 29, 3079 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3080 }; 3081 3082 static const struct panel_desc logictechno_lttd800480070_l2rt = { 3083 .modes = &logictechno_lttd800480070_l2rt_mode, 3084 .num_modes = 1, 3085 .bpc = 8, 3086 .size = { 3087 .width = 154, 3088 .height = 86, 3089 }, 3090 .delay = { 3091 .prepare = 45, 3092 .enable = 100, 3093 .disable = 100, 3094 .unprepare = 45 3095 }, 3096 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3097 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3098 .connector_type = DRM_MODE_CONNECTOR_DPI, 3099 }; 3100 3101 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = { 3102 .clock = 33000, 3103 .hdisplay = 800, 3104 .hsync_start = 800 + 154, 3105 .hsync_end = 800 + 154 + 3, 3106 .htotal = 800 + 154 + 3 + 43, 3107 .vdisplay = 480, 3108 .vsync_start = 480 + 47, 3109 .vsync_end = 480 + 47 + 3, 3110 .vtotal = 480 + 47 + 3 + 20, 3111 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3112 }; 3113 3114 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = { 3115 .modes = &logictechno_lttd800480070_l6wh_rt_mode, 3116 .num_modes = 1, 3117 .bpc = 8, 3118 .size = { 3119 .width = 154, 3120 .height = 86, 3121 }, 3122 .delay = { 3123 .prepare = 45, 3124 .enable = 100, 3125 .disable = 100, 3126 .unprepare = 45 3127 }, 3128 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3129 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3130 .connector_type = DRM_MODE_CONNECTOR_DPI, 3131 }; 3132 3133 static const struct drm_display_mode logicpd_type_28_mode = { 3134 .clock = 9107, 3135 .hdisplay = 480, 3136 .hsync_start = 480 + 3, 3137 .hsync_end = 480 + 3 + 42, 3138 .htotal = 480 + 3 + 42 + 2, 3139 3140 .vdisplay = 272, 3141 .vsync_start = 272 + 2, 3142 .vsync_end = 272 + 2 + 11, 3143 .vtotal = 272 + 2 + 11 + 3, 3144 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3145 }; 3146 3147 static const struct panel_desc logicpd_type_28 = { 3148 .modes = &logicpd_type_28_mode, 3149 .num_modes = 1, 3150 .bpc = 8, 3151 .size = { 3152 .width = 105, 3153 .height = 67, 3154 }, 3155 .delay = { 3156 .prepare = 200, 3157 .enable = 200, 3158 .unprepare = 200, 3159 .disable = 200, 3160 }, 3161 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3162 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3163 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE, 3164 .connector_type = DRM_MODE_CONNECTOR_DPI, 3165 }; 3166 3167 static const struct drm_display_mode microtips_mf_101hiebcaf0_c_mode = { 3168 .clock = 150275, 3169 .hdisplay = 1920, 3170 .hsync_start = 1920 + 32, 3171 .hsync_end = 1920 + 32 + 52, 3172 .htotal = 1920 + 32 + 52 + 24, 3173 .vdisplay = 1200, 3174 .vsync_start = 1200 + 24, 3175 .vsync_end = 1200 + 24 + 8, 3176 .vtotal = 1200 + 24 + 8 + 3, 3177 }; 3178 3179 static const struct panel_desc microtips_mf_101hiebcaf0_c = { 3180 .modes = µtips_mf_101hiebcaf0_c_mode, 3181 .bpc = 8, 3182 .num_modes = 1, 3183 .size = { 3184 .width = 217, 3185 .height = 136, 3186 }, 3187 .delay = { 3188 .prepare = 50, 3189 .disable = 50, 3190 }, 3191 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3192 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3193 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3194 }; 3195 3196 static const struct drm_display_mode microtips_mf_103hieb0ga0_mode = { 3197 .clock = 93301, 3198 .hdisplay = 1920, 3199 .hsync_start = 1920 + 72, 3200 .hsync_end = 1920 + 72 + 72, 3201 .htotal = 1920 + 72 + 72 + 72, 3202 .vdisplay = 720, 3203 .vsync_start = 720 + 3, 3204 .vsync_end = 720 + 3 + 3, 3205 .vtotal = 720 + 3 + 3 + 2, 3206 }; 3207 3208 static const struct panel_desc microtips_mf_103hieb0ga0 = { 3209 .modes = µtips_mf_103hieb0ga0_mode, 3210 .bpc = 8, 3211 .num_modes = 1, 3212 .size = { 3213 .width = 244, 3214 .height = 92, 3215 }, 3216 .delay = { 3217 .prepare = 50, 3218 .disable = 50, 3219 }, 3220 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3221 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3222 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3223 }; 3224 3225 static const struct drm_display_mode mitsubishi_aa070mc01_mode = { 3226 .clock = 30400, 3227 .hdisplay = 800, 3228 .hsync_start = 800 + 0, 3229 .hsync_end = 800 + 1, 3230 .htotal = 800 + 0 + 1 + 160, 3231 .vdisplay = 480, 3232 .vsync_start = 480 + 0, 3233 .vsync_end = 480 + 48 + 1, 3234 .vtotal = 480 + 48 + 1 + 0, 3235 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3236 }; 3237 3238 static const struct panel_desc mitsubishi_aa070mc01 = { 3239 .modes = &mitsubishi_aa070mc01_mode, 3240 .num_modes = 1, 3241 .bpc = 8, 3242 .size = { 3243 .width = 152, 3244 .height = 91, 3245 }, 3246 3247 .delay = { 3248 .enable = 200, 3249 .unprepare = 200, 3250 .disable = 400, 3251 }, 3252 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3253 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3254 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3255 }; 3256 3257 static const struct drm_display_mode mitsubishi_aa084xe01_mode = { 3258 .clock = 56234, 3259 .hdisplay = 1024, 3260 .hsync_start = 1024 + 24, 3261 .hsync_end = 1024 + 24 + 63, 3262 .htotal = 1024 + 24 + 63 + 1, 3263 .vdisplay = 768, 3264 .vsync_start = 768 + 3, 3265 .vsync_end = 768 + 3 + 6, 3266 .vtotal = 768 + 3 + 6 + 1, 3267 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3268 }; 3269 3270 static const struct panel_desc mitsubishi_aa084xe01 = { 3271 .modes = &mitsubishi_aa084xe01_mode, 3272 .num_modes = 1, 3273 .bpc = 8, 3274 .size = { 3275 .width = 1024, 3276 .height = 768, 3277 }, 3278 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 3279 .connector_type = DRM_MODE_CONNECTOR_DPI, 3280 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3281 }; 3282 3283 static const struct display_timing multi_inno_mi0700a2t_30_timing = { 3284 .pixelclock = { 26400000, 33000000, 46800000 }, 3285 .hactive = { 800, 800, 800 }, 3286 .hfront_porch = { 16, 204, 354 }, 3287 .hback_porch = { 46, 46, 46 }, 3288 .hsync_len = { 1, 6, 40 }, 3289 .vactive = { 480, 480, 480 }, 3290 .vfront_porch = { 7, 22, 147 }, 3291 .vback_porch = { 23, 23, 23 }, 3292 .vsync_len = { 1, 3, 20 }, 3293 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3294 DISPLAY_FLAGS_DE_HIGH, 3295 }; 3296 3297 static const struct panel_desc multi_inno_mi0700a2t_30 = { 3298 .timings = &multi_inno_mi0700a2t_30_timing, 3299 .num_timings = 1, 3300 .bpc = 6, 3301 .size = { 3302 .width = 153, 3303 .height = 92, 3304 }, 3305 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3306 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3307 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3308 }; 3309 3310 static const struct display_timing multi_inno_mi0700s4t_6_timing = { 3311 .pixelclock = { 29000000, 33000000, 38000000 }, 3312 .hactive = { 800, 800, 800 }, 3313 .hfront_porch = { 180, 210, 240 }, 3314 .hback_porch = { 16, 16, 16 }, 3315 .hsync_len = { 30, 30, 30 }, 3316 .vactive = { 480, 480, 480 }, 3317 .vfront_porch = { 12, 22, 32 }, 3318 .vback_porch = { 10, 10, 10 }, 3319 .vsync_len = { 13, 13, 13 }, 3320 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3321 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3322 DISPLAY_FLAGS_SYNC_POSEDGE, 3323 }; 3324 3325 static const struct panel_desc multi_inno_mi0700s4t_6 = { 3326 .timings = &multi_inno_mi0700s4t_6_timing, 3327 .num_timings = 1, 3328 .bpc = 8, 3329 .size = { 3330 .width = 154, 3331 .height = 86, 3332 }, 3333 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3334 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3335 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3336 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3337 .connector_type = DRM_MODE_CONNECTOR_DPI, 3338 }; 3339 3340 static const struct display_timing multi_inno_mi0800ft_9_timing = { 3341 .pixelclock = { 32000000, 40000000, 50000000 }, 3342 .hactive = { 800, 800, 800 }, 3343 .hfront_porch = { 16, 210, 354 }, 3344 .hback_porch = { 6, 26, 45 }, 3345 .hsync_len = { 1, 20, 40 }, 3346 .vactive = { 600, 600, 600 }, 3347 .vfront_porch = { 1, 12, 77 }, 3348 .vback_porch = { 3, 13, 22 }, 3349 .vsync_len = { 1, 10, 20 }, 3350 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3351 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3352 DISPLAY_FLAGS_SYNC_POSEDGE, 3353 }; 3354 3355 static const struct panel_desc multi_inno_mi0800ft_9 = { 3356 .timings = &multi_inno_mi0800ft_9_timing, 3357 .num_timings = 1, 3358 .bpc = 8, 3359 .size = { 3360 .width = 162, 3361 .height = 122, 3362 }, 3363 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3364 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3365 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3366 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3367 .connector_type = DRM_MODE_CONNECTOR_DPI, 3368 }; 3369 3370 static const struct display_timing multi_inno_mi1010ait_1cp_timing = { 3371 .pixelclock = { 68900000, 70000000, 73400000 }, 3372 .hactive = { 1280, 1280, 1280 }, 3373 .hfront_porch = { 30, 60, 71 }, 3374 .hback_porch = { 30, 60, 71 }, 3375 .hsync_len = { 10, 10, 48 }, 3376 .vactive = { 800, 800, 800 }, 3377 .vfront_porch = { 5, 10, 10 }, 3378 .vback_porch = { 5, 10, 10 }, 3379 .vsync_len = { 5, 6, 13 }, 3380 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3381 DISPLAY_FLAGS_DE_HIGH, 3382 }; 3383 3384 static const struct panel_desc multi_inno_mi1010ait_1cp = { 3385 .timings = &multi_inno_mi1010ait_1cp_timing, 3386 .num_timings = 1, 3387 .bpc = 8, 3388 .size = { 3389 .width = 217, 3390 .height = 136, 3391 }, 3392 .delay = { 3393 .enable = 50, 3394 .disable = 50, 3395 }, 3396 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3397 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3398 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3399 }; 3400 3401 static const struct display_timing multi_inno_mi1010z1t_1cp11_timing = { 3402 .pixelclock = { 40800000, 51200000, 67200000 }, 3403 .hactive = { 1024, 1024, 1024 }, 3404 .hfront_porch = { 30, 110, 130 }, 3405 .hback_porch = { 30, 110, 130 }, 3406 .hsync_len = { 30, 100, 116 }, 3407 .vactive = { 600, 600, 600 }, 3408 .vfront_porch = { 4, 13, 80 }, 3409 .vback_porch = { 4, 13, 80 }, 3410 .vsync_len = { 2, 9, 40 }, 3411 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3412 DISPLAY_FLAGS_DE_HIGH, 3413 }; 3414 3415 static const struct panel_desc multi_inno_mi1010z1t_1cp11 = { 3416 .timings = &multi_inno_mi1010z1t_1cp11_timing, 3417 .num_timings = 1, 3418 .bpc = 6, 3419 .size = { 3420 .width = 260, 3421 .height = 162, 3422 }, 3423 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 3424 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3425 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3426 }; 3427 3428 static const struct display_timing nec_nl12880bc20_05_timing = { 3429 .pixelclock = { 67000000, 71000000, 75000000 }, 3430 .hactive = { 1280, 1280, 1280 }, 3431 .hfront_porch = { 2, 30, 30 }, 3432 .hback_porch = { 6, 100, 100 }, 3433 .hsync_len = { 2, 30, 30 }, 3434 .vactive = { 800, 800, 800 }, 3435 .vfront_porch = { 5, 5, 5 }, 3436 .vback_porch = { 11, 11, 11 }, 3437 .vsync_len = { 7, 7, 7 }, 3438 }; 3439 3440 static const struct panel_desc nec_nl12880bc20_05 = { 3441 .timings = &nec_nl12880bc20_05_timing, 3442 .num_timings = 1, 3443 .bpc = 8, 3444 .size = { 3445 .width = 261, 3446 .height = 163, 3447 }, 3448 .delay = { 3449 .enable = 50, 3450 .disable = 50, 3451 }, 3452 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3453 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3454 }; 3455 3456 static const struct drm_display_mode nec_nl4827hc19_05b_mode = { 3457 .clock = 10870, 3458 .hdisplay = 480, 3459 .hsync_start = 480 + 2, 3460 .hsync_end = 480 + 2 + 41, 3461 .htotal = 480 + 2 + 41 + 2, 3462 .vdisplay = 272, 3463 .vsync_start = 272 + 2, 3464 .vsync_end = 272 + 2 + 4, 3465 .vtotal = 272 + 2 + 4 + 2, 3466 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3467 }; 3468 3469 static const struct panel_desc nec_nl4827hc19_05b = { 3470 .modes = &nec_nl4827hc19_05b_mode, 3471 .num_modes = 1, 3472 .bpc = 8, 3473 .size = { 3474 .width = 95, 3475 .height = 54, 3476 }, 3477 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3478 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3479 }; 3480 3481 static const struct drm_display_mode netron_dy_e231732_mode = { 3482 .clock = 66000, 3483 .hdisplay = 1024, 3484 .hsync_start = 1024 + 160, 3485 .hsync_end = 1024 + 160 + 70, 3486 .htotal = 1024 + 160 + 70 + 90, 3487 .vdisplay = 600, 3488 .vsync_start = 600 + 127, 3489 .vsync_end = 600 + 127 + 20, 3490 .vtotal = 600 + 127 + 20 + 3, 3491 }; 3492 3493 static const struct panel_desc netron_dy_e231732 = { 3494 .modes = &netron_dy_e231732_mode, 3495 .num_modes = 1, 3496 .size = { 3497 .width = 154, 3498 .height = 87, 3499 }, 3500 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3501 }; 3502 3503 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = { 3504 .clock = 9000, 3505 .hdisplay = 480, 3506 .hsync_start = 480 + 2, 3507 .hsync_end = 480 + 2 + 41, 3508 .htotal = 480 + 2 + 41 + 2, 3509 .vdisplay = 272, 3510 .vsync_start = 272 + 2, 3511 .vsync_end = 272 + 2 + 10, 3512 .vtotal = 272 + 2 + 10 + 2, 3513 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3514 }; 3515 3516 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = { 3517 .modes = &newhaven_nhd_43_480272ef_atxl_mode, 3518 .num_modes = 1, 3519 .bpc = 8, 3520 .size = { 3521 .width = 95, 3522 .height = 54, 3523 }, 3524 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3525 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3526 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3527 .connector_type = DRM_MODE_CONNECTOR_DPI, 3528 }; 3529 3530 static const struct display_timing nlt_nl192108ac18_02d_timing = { 3531 .pixelclock = { 130000000, 148350000, 163000000 }, 3532 .hactive = { 1920, 1920, 1920 }, 3533 .hfront_porch = { 80, 100, 100 }, 3534 .hback_porch = { 100, 120, 120 }, 3535 .hsync_len = { 50, 60, 60 }, 3536 .vactive = { 1080, 1080, 1080 }, 3537 .vfront_porch = { 12, 30, 30 }, 3538 .vback_porch = { 4, 10, 10 }, 3539 .vsync_len = { 4, 5, 5 }, 3540 }; 3541 3542 static const struct panel_desc nlt_nl192108ac18_02d = { 3543 .timings = &nlt_nl192108ac18_02d_timing, 3544 .num_timings = 1, 3545 .bpc = 8, 3546 .size = { 3547 .width = 344, 3548 .height = 194, 3549 }, 3550 .delay = { 3551 .unprepare = 500, 3552 }, 3553 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3554 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3555 }; 3556 3557 static const struct drm_display_mode nvd_9128_mode = { 3558 .clock = 29500, 3559 .hdisplay = 800, 3560 .hsync_start = 800 + 130, 3561 .hsync_end = 800 + 130 + 98, 3562 .htotal = 800 + 0 + 130 + 98, 3563 .vdisplay = 480, 3564 .vsync_start = 480 + 10, 3565 .vsync_end = 480 + 10 + 50, 3566 .vtotal = 480 + 0 + 10 + 50, 3567 }; 3568 3569 static const struct panel_desc nvd_9128 = { 3570 .modes = &nvd_9128_mode, 3571 .num_modes = 1, 3572 .bpc = 8, 3573 .size = { 3574 .width = 156, 3575 .height = 88, 3576 }, 3577 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3578 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3579 }; 3580 3581 static const struct display_timing okaya_rs800480t_7x0gp_timing = { 3582 .pixelclock = { 30000000, 30000000, 40000000 }, 3583 .hactive = { 800, 800, 800 }, 3584 .hfront_porch = { 40, 40, 40 }, 3585 .hback_porch = { 40, 40, 40 }, 3586 .hsync_len = { 1, 48, 48 }, 3587 .vactive = { 480, 480, 480 }, 3588 .vfront_porch = { 13, 13, 13 }, 3589 .vback_porch = { 29, 29, 29 }, 3590 .vsync_len = { 3, 3, 3 }, 3591 .flags = DISPLAY_FLAGS_DE_HIGH, 3592 }; 3593 3594 static const struct panel_desc okaya_rs800480t_7x0gp = { 3595 .timings = &okaya_rs800480t_7x0gp_timing, 3596 .num_timings = 1, 3597 .bpc = 6, 3598 .size = { 3599 .width = 154, 3600 .height = 87, 3601 }, 3602 .delay = { 3603 .prepare = 41, 3604 .enable = 50, 3605 .unprepare = 41, 3606 .disable = 50, 3607 }, 3608 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3609 }; 3610 3611 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = { 3612 .clock = 9000, 3613 .hdisplay = 480, 3614 .hsync_start = 480 + 5, 3615 .hsync_end = 480 + 5 + 30, 3616 .htotal = 480 + 5 + 30 + 10, 3617 .vdisplay = 272, 3618 .vsync_start = 272 + 8, 3619 .vsync_end = 272 + 8 + 5, 3620 .vtotal = 272 + 8 + 5 + 3, 3621 }; 3622 3623 static const struct panel_desc olimex_lcd_olinuxino_43ts = { 3624 .modes = &olimex_lcd_olinuxino_43ts_mode, 3625 .num_modes = 1, 3626 .size = { 3627 .width = 95, 3628 .height = 54, 3629 }, 3630 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3631 }; 3632 3633 static const struct display_timing ontat_kd50g21_40nt_a1_timing = { 3634 .pixelclock = { 30000000, 30000000, 50000000 }, 3635 .hactive = { 800, 800, 800 }, 3636 .hfront_porch = { 1, 40, 255 }, 3637 .hback_porch = { 1, 40, 87 }, 3638 .hsync_len = { 1, 48, 87 }, 3639 .vactive = { 480, 480, 480 }, 3640 .vfront_porch = { 1, 13, 255 }, 3641 .vback_porch = { 1, 29, 29 }, 3642 .vsync_len = { 3, 3, 31 }, 3643 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 3644 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 3645 }; 3646 3647 static const struct panel_desc ontat_kd50g21_40nt_a1 = { 3648 .timings = &ontat_kd50g21_40nt_a1_timing, 3649 .num_timings = 1, 3650 .bpc = 8, 3651 .size = { 3652 .width = 108, 3653 .height = 65, 3654 }, 3655 .delay = { 3656 .prepare = 147, /* 5 VSDs */ 3657 .enable = 147, /* 5 VSDs */ 3658 .disable = 88, /* 3 VSDs */ 3659 .unprepare = 117, /* 4 VSDs */ 3660 }, 3661 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3662 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3663 .connector_type = DRM_MODE_CONNECTOR_DPI, 3664 }; 3665 3666 /* 3667 * 800x480 CVT. The panel appears to be quite accepting, at least as far as 3668 * pixel clocks, but this is the timing that was being used in the Adafruit 3669 * installation instructions. 3670 */ 3671 static const struct drm_display_mode ontat_yx700wv03_mode = { 3672 .clock = 29500, 3673 .hdisplay = 800, 3674 .hsync_start = 824, 3675 .hsync_end = 896, 3676 .htotal = 992, 3677 .vdisplay = 480, 3678 .vsync_start = 483, 3679 .vsync_end = 493, 3680 .vtotal = 500, 3681 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3682 }; 3683 3684 /* 3685 * Specification at: 3686 * https://www.adafruit.com/images/product-files/2406/c3163.pdf 3687 */ 3688 static const struct panel_desc ontat_yx700wv03 = { 3689 .modes = &ontat_yx700wv03_mode, 3690 .num_modes = 1, 3691 .bpc = 8, 3692 .size = { 3693 .width = 154, 3694 .height = 83, 3695 }, 3696 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3697 }; 3698 3699 static const struct drm_display_mode ortustech_com37h3m_mode = { 3700 .clock = 22230, 3701 .hdisplay = 480, 3702 .hsync_start = 480 + 40, 3703 .hsync_end = 480 + 40 + 10, 3704 .htotal = 480 + 40 + 10 + 40, 3705 .vdisplay = 640, 3706 .vsync_start = 640 + 4, 3707 .vsync_end = 640 + 4 + 2, 3708 .vtotal = 640 + 4 + 2 + 4, 3709 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3710 }; 3711 3712 static const struct panel_desc ortustech_com37h3m = { 3713 .modes = &ortustech_com37h3m_mode, 3714 .num_modes = 1, 3715 .bpc = 8, 3716 .size = { 3717 .width = 56, /* 56.16mm */ 3718 .height = 75, /* 74.88mm */ 3719 }, 3720 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3721 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3722 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3723 }; 3724 3725 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = { 3726 .clock = 25000, 3727 .hdisplay = 480, 3728 .hsync_start = 480 + 10, 3729 .hsync_end = 480 + 10 + 10, 3730 .htotal = 480 + 10 + 10 + 15, 3731 .vdisplay = 800, 3732 .vsync_start = 800 + 3, 3733 .vsync_end = 800 + 3 + 3, 3734 .vtotal = 800 + 3 + 3 + 3, 3735 }; 3736 3737 static const struct panel_desc ortustech_com43h4m85ulc = { 3738 .modes = &ortustech_com43h4m85ulc_mode, 3739 .num_modes = 1, 3740 .bpc = 6, 3741 .size = { 3742 .width = 56, 3743 .height = 93, 3744 }, 3745 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3746 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 3747 .connector_type = DRM_MODE_CONNECTOR_DPI, 3748 }; 3749 3750 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = { 3751 .clock = 33000, 3752 .hdisplay = 800, 3753 .hsync_start = 800 + 210, 3754 .hsync_end = 800 + 210 + 30, 3755 .htotal = 800 + 210 + 30 + 16, 3756 .vdisplay = 480, 3757 .vsync_start = 480 + 22, 3758 .vsync_end = 480 + 22 + 13, 3759 .vtotal = 480 + 22 + 13 + 10, 3760 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3761 }; 3762 3763 static const struct panel_desc osddisplays_osd070t1718_19ts = { 3764 .modes = &osddisplays_osd070t1718_19ts_mode, 3765 .num_modes = 1, 3766 .bpc = 8, 3767 .size = { 3768 .width = 152, 3769 .height = 91, 3770 }, 3771 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3772 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE | 3773 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 3774 .connector_type = DRM_MODE_CONNECTOR_DPI, 3775 }; 3776 3777 static const struct drm_display_mode pda_91_00156_a0_mode = { 3778 .clock = 33300, 3779 .hdisplay = 800, 3780 .hsync_start = 800 + 1, 3781 .hsync_end = 800 + 1 + 64, 3782 .htotal = 800 + 1 + 64 + 64, 3783 .vdisplay = 480, 3784 .vsync_start = 480 + 1, 3785 .vsync_end = 480 + 1 + 23, 3786 .vtotal = 480 + 1 + 23 + 22, 3787 }; 3788 3789 static const struct panel_desc pda_91_00156_a0 = { 3790 .modes = &pda_91_00156_a0_mode, 3791 .num_modes = 1, 3792 .size = { 3793 .width = 152, 3794 .height = 91, 3795 }, 3796 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3797 }; 3798 3799 static const struct drm_display_mode powertip_ph128800t006_zhc01_mode = { 3800 .clock = 66500, 3801 .hdisplay = 1280, 3802 .hsync_start = 1280 + 12, 3803 .hsync_end = 1280 + 12 + 20, 3804 .htotal = 1280 + 12 + 20 + 56, 3805 .vdisplay = 800, 3806 .vsync_start = 800 + 1, 3807 .vsync_end = 800 + 1 + 3, 3808 .vtotal = 800 + 1 + 3 + 20, 3809 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 3810 }; 3811 3812 static const struct panel_desc powertip_ph128800t006_zhc01 = { 3813 .modes = &powertip_ph128800t006_zhc01_mode, 3814 .num_modes = 1, 3815 .bpc = 8, 3816 .size = { 3817 .width = 216, 3818 .height = 135, 3819 }, 3820 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 3821 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 3822 .connector_type = DRM_MODE_CONNECTOR_LVDS, 3823 }; 3824 3825 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = { 3826 .clock = 24750, 3827 .hdisplay = 800, 3828 .hsync_start = 800 + 54, 3829 .hsync_end = 800 + 54 + 2, 3830 .htotal = 800 + 54 + 2 + 44, 3831 .vdisplay = 480, 3832 .vsync_start = 480 + 49, 3833 .vsync_end = 480 + 49 + 2, 3834 .vtotal = 480 + 49 + 2 + 22, 3835 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3836 }; 3837 3838 static const struct panel_desc powertip_ph800480t013_idf02 = { 3839 .modes = &powertip_ph800480t013_idf02_mode, 3840 .num_modes = 1, 3841 .bpc = 8, 3842 .size = { 3843 .width = 152, 3844 .height = 91, 3845 }, 3846 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 3847 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 3848 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 3849 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3850 .connector_type = DRM_MODE_CONNECTOR_DPI, 3851 }; 3852 3853 static const struct drm_display_mode primeview_pm070wl4_mode = { 3854 .clock = 32000, 3855 .hdisplay = 800, 3856 .hsync_start = 800 + 42, 3857 .hsync_end = 800 + 42 + 128, 3858 .htotal = 800 + 42 + 128 + 86, 3859 .vdisplay = 480, 3860 .vsync_start = 480 + 10, 3861 .vsync_end = 480 + 10 + 2, 3862 .vtotal = 480 + 10 + 2 + 33, 3863 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 3864 }; 3865 3866 static const struct panel_desc primeview_pm070wl4 = { 3867 .modes = &primeview_pm070wl4_mode, 3868 .num_modes = 1, 3869 .bpc = 6, 3870 .size = { 3871 .width = 152, 3872 .height = 91, 3873 }, 3874 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 3875 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3876 .connector_type = DRM_MODE_CONNECTOR_DPI, 3877 }; 3878 3879 static const struct drm_display_mode qd43003c0_40_mode = { 3880 .clock = 9000, 3881 .hdisplay = 480, 3882 .hsync_start = 480 + 8, 3883 .hsync_end = 480 + 8 + 4, 3884 .htotal = 480 + 8 + 4 + 39, 3885 .vdisplay = 272, 3886 .vsync_start = 272 + 4, 3887 .vsync_end = 272 + 4 + 10, 3888 .vtotal = 272 + 4 + 10 + 2, 3889 }; 3890 3891 static const struct panel_desc qd43003c0_40 = { 3892 .modes = &qd43003c0_40_mode, 3893 .num_modes = 1, 3894 .bpc = 8, 3895 .size = { 3896 .width = 95, 3897 .height = 53, 3898 }, 3899 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3900 }; 3901 3902 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = { 3903 { /* 60 Hz */ 3904 .clock = 10800, 3905 .hdisplay = 480, 3906 .hsync_start = 480 + 77, 3907 .hsync_end = 480 + 77 + 41, 3908 .htotal = 480 + 77 + 41 + 2, 3909 .vdisplay = 272, 3910 .vsync_start = 272 + 16, 3911 .vsync_end = 272 + 16 + 10, 3912 .vtotal = 272 + 16 + 10 + 2, 3913 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3914 }, 3915 { /* 50 Hz */ 3916 .clock = 10800, 3917 .hdisplay = 480, 3918 .hsync_start = 480 + 17, 3919 .hsync_end = 480 + 17 + 41, 3920 .htotal = 480 + 17 + 41 + 2, 3921 .vdisplay = 272, 3922 .vsync_start = 272 + 116, 3923 .vsync_end = 272 + 116 + 10, 3924 .vtotal = 272 + 116 + 10 + 2, 3925 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 3926 }, 3927 }; 3928 3929 static const struct panel_desc qishenglong_gopher2b_lcd = { 3930 .modes = qishenglong_gopher2b_lcd_modes, 3931 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes), 3932 .bpc = 8, 3933 .size = { 3934 .width = 95, 3935 .height = 54, 3936 }, 3937 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3938 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 3939 .connector_type = DRM_MODE_CONNECTOR_DPI, 3940 }; 3941 3942 static const struct display_timing rocktech_rk043fn48h_timing = { 3943 .pixelclock = { 6000000, 9000000, 12000000 }, 3944 .hactive = { 480, 480, 480 }, 3945 .hback_porch = { 8, 43, 43 }, 3946 .hfront_porch = { 2, 8, 10 }, 3947 .hsync_len = { 1, 1, 1 }, 3948 .vactive = { 272, 272, 272 }, 3949 .vback_porch = { 2, 12, 26 }, 3950 .vfront_porch = { 1, 4, 4 }, 3951 .vsync_len = { 1, 10, 10 }, 3952 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW | 3953 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 3954 DISPLAY_FLAGS_SYNC_POSEDGE, 3955 }; 3956 3957 static const struct panel_desc rocktech_rk043fn48h = { 3958 .timings = &rocktech_rk043fn48h_timing, 3959 .num_timings = 1, 3960 .bpc = 8, 3961 .size = { 3962 .width = 95, 3963 .height = 54, 3964 }, 3965 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 3966 .connector_type = DRM_MODE_CONNECTOR_DPI, 3967 }; 3968 3969 static const struct display_timing rocktech_rk070er9427_timing = { 3970 .pixelclock = { 26400000, 33300000, 46800000 }, 3971 .hactive = { 800, 800, 800 }, 3972 .hfront_porch = { 16, 210, 354 }, 3973 .hback_porch = { 46, 46, 46 }, 3974 .hsync_len = { 1, 1, 1 }, 3975 .vactive = { 480, 480, 480 }, 3976 .vfront_porch = { 7, 22, 147 }, 3977 .vback_porch = { 23, 23, 23 }, 3978 .vsync_len = { 1, 1, 1 }, 3979 .flags = DISPLAY_FLAGS_DE_HIGH, 3980 }; 3981 3982 static const struct panel_desc rocktech_rk070er9427 = { 3983 .timings = &rocktech_rk070er9427_timing, 3984 .num_timings = 1, 3985 .bpc = 6, 3986 .size = { 3987 .width = 154, 3988 .height = 86, 3989 }, 3990 .delay = { 3991 .prepare = 41, 3992 .enable = 50, 3993 .unprepare = 41, 3994 .disable = 50, 3995 }, 3996 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 3997 }; 3998 3999 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = { 4000 .clock = 71100, 4001 .hdisplay = 1280, 4002 .hsync_start = 1280 + 48, 4003 .hsync_end = 1280 + 48 + 32, 4004 .htotal = 1280 + 48 + 32 + 80, 4005 .vdisplay = 800, 4006 .vsync_start = 800 + 2, 4007 .vsync_end = 800 + 2 + 5, 4008 .vtotal = 800 + 2 + 5 + 16, 4009 }; 4010 4011 static const struct panel_desc rocktech_rk101ii01d_ct = { 4012 .modes = &rocktech_rk101ii01d_ct_mode, 4013 .bpc = 8, 4014 .num_modes = 1, 4015 .size = { 4016 .width = 217, 4017 .height = 136, 4018 }, 4019 .delay = { 4020 .prepare = 50, 4021 .disable = 50, 4022 }, 4023 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4024 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4025 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4026 }; 4027 4028 static const struct display_timing samsung_ltl101al01_timing = { 4029 .pixelclock = { 66663000, 66663000, 66663000 }, 4030 .hactive = { 1280, 1280, 1280 }, 4031 .hfront_porch = { 18, 18, 18 }, 4032 .hback_porch = { 36, 36, 36 }, 4033 .hsync_len = { 16, 16, 16 }, 4034 .vactive = { 800, 800, 800 }, 4035 .vfront_porch = { 4, 4, 4 }, 4036 .vback_porch = { 16, 16, 16 }, 4037 .vsync_len = { 3, 3, 3 }, 4038 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4039 }; 4040 4041 static const struct panel_desc samsung_ltl101al01 = { 4042 .timings = &samsung_ltl101al01_timing, 4043 .num_timings = 1, 4044 .bpc = 8, 4045 .size = { 4046 .width = 217, 4047 .height = 135, 4048 }, 4049 .delay = { 4050 .prepare = 40, 4051 .enable = 300, 4052 .disable = 200, 4053 .unprepare = 600, 4054 }, 4055 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4056 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4057 }; 4058 4059 static const struct drm_display_mode samsung_ltn101nt05_mode = { 4060 .clock = 54030, 4061 .hdisplay = 1024, 4062 .hsync_start = 1024 + 24, 4063 .hsync_end = 1024 + 24 + 136, 4064 .htotal = 1024 + 24 + 136 + 160, 4065 .vdisplay = 600, 4066 .vsync_start = 600 + 3, 4067 .vsync_end = 600 + 3 + 6, 4068 .vtotal = 600 + 3 + 6 + 61, 4069 }; 4070 4071 static const struct panel_desc samsung_ltn101nt05 = { 4072 .modes = &samsung_ltn101nt05_mode, 4073 .num_modes = 1, 4074 .bpc = 6, 4075 .size = { 4076 .width = 223, 4077 .height = 125, 4078 }, 4079 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4080 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4081 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4082 }; 4083 4084 static const struct display_timing satoz_sat050at40h12r2_timing = { 4085 .pixelclock = {33300000, 33300000, 50000000}, 4086 .hactive = {800, 800, 800}, 4087 .hfront_porch = {16, 210, 354}, 4088 .hback_porch = {46, 46, 46}, 4089 .hsync_len = {1, 1, 40}, 4090 .vactive = {480, 480, 480}, 4091 .vfront_porch = {7, 22, 147}, 4092 .vback_porch = {23, 23, 23}, 4093 .vsync_len = {1, 1, 20}, 4094 }; 4095 4096 static const struct panel_desc satoz_sat050at40h12r2 = { 4097 .timings = &satoz_sat050at40h12r2_timing, 4098 .num_timings = 1, 4099 .bpc = 8, 4100 .size = { 4101 .width = 108, 4102 .height = 65, 4103 }, 4104 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4105 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4106 }; 4107 4108 static const struct drm_display_mode sharp_lq070y3dg3b_mode = { 4109 .clock = 33260, 4110 .hdisplay = 800, 4111 .hsync_start = 800 + 64, 4112 .hsync_end = 800 + 64 + 128, 4113 .htotal = 800 + 64 + 128 + 64, 4114 .vdisplay = 480, 4115 .vsync_start = 480 + 8, 4116 .vsync_end = 480 + 8 + 2, 4117 .vtotal = 480 + 8 + 2 + 35, 4118 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4119 }; 4120 4121 static const struct panel_desc sharp_lq070y3dg3b = { 4122 .modes = &sharp_lq070y3dg3b_mode, 4123 .num_modes = 1, 4124 .bpc = 8, 4125 .size = { 4126 .width = 152, /* 152.4mm */ 4127 .height = 91, /* 91.4mm */ 4128 }, 4129 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4130 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4131 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE, 4132 }; 4133 4134 static const struct drm_display_mode sharp_lq035q7db03_mode = { 4135 .clock = 5500, 4136 .hdisplay = 240, 4137 .hsync_start = 240 + 16, 4138 .hsync_end = 240 + 16 + 7, 4139 .htotal = 240 + 16 + 7 + 5, 4140 .vdisplay = 320, 4141 .vsync_start = 320 + 9, 4142 .vsync_end = 320 + 9 + 1, 4143 .vtotal = 320 + 9 + 1 + 7, 4144 }; 4145 4146 static const struct panel_desc sharp_lq035q7db03 = { 4147 .modes = &sharp_lq035q7db03_mode, 4148 .num_modes = 1, 4149 .bpc = 6, 4150 .size = { 4151 .width = 54, 4152 .height = 72, 4153 }, 4154 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4155 }; 4156 4157 static const struct display_timing sharp_lq101k1ly04_timing = { 4158 .pixelclock = { 60000000, 65000000, 80000000 }, 4159 .hactive = { 1280, 1280, 1280 }, 4160 .hfront_porch = { 20, 20, 20 }, 4161 .hback_porch = { 20, 20, 20 }, 4162 .hsync_len = { 10, 10, 10 }, 4163 .vactive = { 800, 800, 800 }, 4164 .vfront_porch = { 4, 4, 4 }, 4165 .vback_porch = { 4, 4, 4 }, 4166 .vsync_len = { 4, 4, 4 }, 4167 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE, 4168 }; 4169 4170 static const struct panel_desc sharp_lq101k1ly04 = { 4171 .timings = &sharp_lq101k1ly04_timing, 4172 .num_timings = 1, 4173 .bpc = 8, 4174 .size = { 4175 .width = 217, 4176 .height = 136, 4177 }, 4178 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4179 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4180 }; 4181 4182 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = { 4183 { /* 50 Hz */ 4184 .clock = 3000, 4185 .hdisplay = 240, 4186 .hsync_start = 240 + 58, 4187 .hsync_end = 240 + 58 + 1, 4188 .htotal = 240 + 58 + 1 + 1, 4189 .vdisplay = 160, 4190 .vsync_start = 160 + 24, 4191 .vsync_end = 160 + 24 + 10, 4192 .vtotal = 160 + 24 + 10 + 6, 4193 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4194 }, 4195 { /* 60 Hz */ 4196 .clock = 3000, 4197 .hdisplay = 240, 4198 .hsync_start = 240 + 8, 4199 .hsync_end = 240 + 8 + 1, 4200 .htotal = 240 + 8 + 1 + 1, 4201 .vdisplay = 160, 4202 .vsync_start = 160 + 24, 4203 .vsync_end = 160 + 24 + 10, 4204 .vtotal = 160 + 24 + 10 + 6, 4205 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC, 4206 }, 4207 }; 4208 4209 static const struct panel_desc sharp_ls020b1dd01d = { 4210 .modes = sharp_ls020b1dd01d_modes, 4211 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes), 4212 .bpc = 6, 4213 .size = { 4214 .width = 42, 4215 .height = 28, 4216 }, 4217 .bus_format = MEDIA_BUS_FMT_RGB565_1X16, 4218 .bus_flags = DRM_BUS_FLAG_DE_HIGH 4219 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 4220 | DRM_BUS_FLAG_SHARP_SIGNALS, 4221 }; 4222 4223 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = { 4224 .clock = 33300, 4225 .hdisplay = 800, 4226 .hsync_start = 800 + 1, 4227 .hsync_end = 800 + 1 + 64, 4228 .htotal = 800 + 1 + 64 + 64, 4229 .vdisplay = 480, 4230 .vsync_start = 480 + 1, 4231 .vsync_end = 480 + 1 + 23, 4232 .vtotal = 480 + 1 + 23 + 22, 4233 }; 4234 4235 static const struct panel_desc shelly_sca07010_bfn_lnn = { 4236 .modes = &shelly_sca07010_bfn_lnn_mode, 4237 .num_modes = 1, 4238 .size = { 4239 .width = 152, 4240 .height = 91, 4241 }, 4242 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4243 }; 4244 4245 static const struct drm_display_mode starry_kr070pe2t_mode = { 4246 .clock = 33000, 4247 .hdisplay = 800, 4248 .hsync_start = 800 + 209, 4249 .hsync_end = 800 + 209 + 1, 4250 .htotal = 800 + 209 + 1 + 45, 4251 .vdisplay = 480, 4252 .vsync_start = 480 + 22, 4253 .vsync_end = 480 + 22 + 1, 4254 .vtotal = 480 + 22 + 1 + 22, 4255 }; 4256 4257 static const struct panel_desc starry_kr070pe2t = { 4258 .modes = &starry_kr070pe2t_mode, 4259 .num_modes = 1, 4260 .bpc = 8, 4261 .size = { 4262 .width = 152, 4263 .height = 86, 4264 }, 4265 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4266 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE, 4267 .connector_type = DRM_MODE_CONNECTOR_DPI, 4268 }; 4269 4270 static const struct display_timing startek_kd070wvfpa_mode = { 4271 .pixelclock = { 25200000, 27200000, 30500000 }, 4272 .hactive = { 800, 800, 800 }, 4273 .hfront_porch = { 19, 44, 115 }, 4274 .hback_porch = { 5, 16, 101 }, 4275 .hsync_len = { 1, 2, 100 }, 4276 .vactive = { 480, 480, 480 }, 4277 .vfront_porch = { 5, 43, 67 }, 4278 .vback_porch = { 5, 5, 67 }, 4279 .vsync_len = { 1, 2, 66 }, 4280 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4281 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | 4282 DISPLAY_FLAGS_SYNC_POSEDGE, 4283 }; 4284 4285 static const struct panel_desc startek_kd070wvfpa = { 4286 .timings = &startek_kd070wvfpa_mode, 4287 .num_timings = 1, 4288 .bpc = 8, 4289 .size = { 4290 .width = 152, 4291 .height = 91, 4292 }, 4293 .delay = { 4294 .prepare = 20, 4295 .enable = 200, 4296 .disable = 200, 4297 }, 4298 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4299 .connector_type = DRM_MODE_CONNECTOR_DPI, 4300 .bus_flags = DRM_BUS_FLAG_DE_HIGH | 4301 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | 4302 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, 4303 }; 4304 4305 static const struct display_timing tsd_tst043015cmhx_timing = { 4306 .pixelclock = { 5000000, 9000000, 12000000 }, 4307 .hactive = { 480, 480, 480 }, 4308 .hfront_porch = { 4, 5, 65 }, 4309 .hback_porch = { 36, 40, 255 }, 4310 .hsync_len = { 1, 1, 1 }, 4311 .vactive = { 272, 272, 272 }, 4312 .vfront_porch = { 2, 8, 97 }, 4313 .vback_porch = { 3, 8, 31 }, 4314 .vsync_len = { 1, 1, 1 }, 4315 4316 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | 4317 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, 4318 }; 4319 4320 static const struct panel_desc tsd_tst043015cmhx = { 4321 .timings = &tsd_tst043015cmhx_timing, 4322 .num_timings = 1, 4323 .bpc = 8, 4324 .size = { 4325 .width = 105, 4326 .height = 67, 4327 }, 4328 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4329 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4330 }; 4331 4332 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = { 4333 .clock = 30000, 4334 .hdisplay = 800, 4335 .hsync_start = 800 + 39, 4336 .hsync_end = 800 + 39 + 47, 4337 .htotal = 800 + 39 + 47 + 39, 4338 .vdisplay = 480, 4339 .vsync_start = 480 + 13, 4340 .vsync_end = 480 + 13 + 2, 4341 .vtotal = 480 + 13 + 2 + 29, 4342 }; 4343 4344 static const struct panel_desc tfc_s9700rtwv43tr_01b = { 4345 .modes = &tfc_s9700rtwv43tr_01b_mode, 4346 .num_modes = 1, 4347 .bpc = 8, 4348 .size = { 4349 .width = 155, 4350 .height = 90, 4351 }, 4352 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4353 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4354 }; 4355 4356 static const struct display_timing tianma_tm070jdhg30_timing = { 4357 .pixelclock = { 62600000, 68200000, 78100000 }, 4358 .hactive = { 1280, 1280, 1280 }, 4359 .hfront_porch = { 15, 64, 159 }, 4360 .hback_porch = { 5, 5, 5 }, 4361 .hsync_len = { 1, 1, 256 }, 4362 .vactive = { 800, 800, 800 }, 4363 .vfront_porch = { 3, 40, 99 }, 4364 .vback_porch = { 2, 2, 2 }, 4365 .vsync_len = { 1, 1, 128 }, 4366 .flags = DISPLAY_FLAGS_DE_HIGH, 4367 }; 4368 4369 static const struct panel_desc tianma_tm070jdhg30 = { 4370 .timings = &tianma_tm070jdhg30_timing, 4371 .num_timings = 1, 4372 .bpc = 8, 4373 .size = { 4374 .width = 151, 4375 .height = 95, 4376 }, 4377 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4378 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4379 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4380 }; 4381 4382 static const struct panel_desc tianma_tm070jvhg33 = { 4383 .timings = &tianma_tm070jdhg30_timing, 4384 .num_timings = 1, 4385 .bpc = 8, 4386 .size = { 4387 .width = 150, 4388 .height = 94, 4389 }, 4390 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4391 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4392 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4393 }; 4394 4395 /* 4396 * The datasheet computes total blanking as back porch + front porch, not 4397 * including sync pulse width. This is for both H and V. To make the total 4398 * blanking and period correct, subtract the pulse width from the front 4399 * porch. 4400 * 4401 * This works well for the Min and Typ values, but for Max values the sync 4402 * pulse width is higher than back porch + front porch, so work around that 4403 * by reducing the Max sync length value to 1 and then treating the Max 4404 * porches as in the Min and Typ cases. 4405 * 4406 * Exact datasheet values are added as a comment where they differ from the 4407 * ones implemented for the above reason. 4408 */ 4409 static const struct display_timing tianma_tm070jdhg34_00_timing = { 4410 .pixelclock = { 68400000, 71900000, 78100000 }, 4411 .hactive = { 1280, 1280, 1280 }, 4412 .hfront_porch = { 130, 138, 158 }, /* 131, 139, 159 */ 4413 .hback_porch = { 5, 5, 5 }, 4414 .hsync_len = { 1, 1, 1 }, /* 1, 1, 256 */ 4415 .vactive = { 800, 800, 800 }, 4416 .vfront_porch = { 2, 39, 98 }, /* 3, 40, 99 */ 4417 .vback_porch = { 2, 2, 2 }, 4418 .vsync_len = { 1, 1, 1 }, /* 1, 1, 128 */ 4419 .flags = DISPLAY_FLAGS_DE_HIGH, 4420 }; 4421 4422 static const struct panel_desc tianma_tm070jdhg34_00 = { 4423 .timings = &tianma_tm070jdhg34_00_timing, 4424 .num_timings = 1, 4425 .bpc = 8, 4426 .size = { 4427 .width = 150, /* 149.76 */ 4428 .height = 94, /* 93.60 */ 4429 }, 4430 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4431 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4432 }; 4433 4434 static const struct display_timing tianma_tm070rvhg71_timing = { 4435 .pixelclock = { 27700000, 29200000, 39600000 }, 4436 .hactive = { 800, 800, 800 }, 4437 .hfront_porch = { 12, 40, 212 }, 4438 .hback_porch = { 88, 88, 88 }, 4439 .hsync_len = { 1, 1, 40 }, 4440 .vactive = { 480, 480, 480 }, 4441 .vfront_porch = { 1, 13, 88 }, 4442 .vback_porch = { 32, 32, 32 }, 4443 .vsync_len = { 1, 1, 3 }, 4444 .flags = DISPLAY_FLAGS_DE_HIGH, 4445 }; 4446 4447 static const struct panel_desc tianma_tm070rvhg71 = { 4448 .timings = &tianma_tm070rvhg71_timing, 4449 .num_timings = 1, 4450 .bpc = 8, 4451 .size = { 4452 .width = 154, 4453 .height = 86, 4454 }, 4455 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4456 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4457 }; 4458 4459 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { 4460 { 4461 .clock = 10000, 4462 .hdisplay = 320, 4463 .hsync_start = 320 + 50, 4464 .hsync_end = 320 + 50 + 6, 4465 .htotal = 320 + 50 + 6 + 38, 4466 .vdisplay = 240, 4467 .vsync_start = 240 + 3, 4468 .vsync_end = 240 + 3 + 1, 4469 .vtotal = 240 + 3 + 1 + 17, 4470 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4471 }, 4472 }; 4473 4474 static const struct panel_desc ti_nspire_cx_lcd_panel = { 4475 .modes = ti_nspire_cx_lcd_mode, 4476 .num_modes = 1, 4477 .bpc = 8, 4478 .size = { 4479 .width = 65, 4480 .height = 49, 4481 }, 4482 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4483 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE, 4484 }; 4485 4486 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { 4487 { 4488 .clock = 10000, 4489 .hdisplay = 320, 4490 .hsync_start = 320 + 6, 4491 .hsync_end = 320 + 6 + 6, 4492 .htotal = 320 + 6 + 6 + 6, 4493 .vdisplay = 240, 4494 .vsync_start = 240 + 0, 4495 .vsync_end = 240 + 0 + 1, 4496 .vtotal = 240 + 0 + 1 + 0, 4497 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4498 }, 4499 }; 4500 4501 static const struct panel_desc ti_nspire_classic_lcd_panel = { 4502 .modes = ti_nspire_classic_lcd_mode, 4503 .num_modes = 1, 4504 /* The grayscale panel has 8 bit for the color .. Y (black) */ 4505 .bpc = 8, 4506 .size = { 4507 .width = 71, 4508 .height = 53, 4509 }, 4510 /* This is the grayscale bus format */ 4511 .bus_format = MEDIA_BUS_FMT_Y8_1X8, 4512 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4513 }; 4514 4515 static const struct display_timing topland_tian_g07017_01_timing = { 4516 .pixelclock = { 44900000, 51200000, 63000000 }, 4517 .hactive = { 1024, 1024, 1024 }, 4518 .hfront_porch = { 16, 160, 216 }, 4519 .hback_porch = { 160, 160, 160 }, 4520 .hsync_len = { 1, 1, 140 }, 4521 .vactive = { 600, 600, 600 }, 4522 .vfront_porch = { 1, 12, 127 }, 4523 .vback_porch = { 23, 23, 23 }, 4524 .vsync_len = { 1, 1, 20 }, 4525 }; 4526 4527 static const struct panel_desc topland_tian_g07017_01 = { 4528 .timings = &topland_tian_g07017_01_timing, 4529 .num_timings = 1, 4530 .bpc = 8, 4531 .size = { 4532 .width = 154, 4533 .height = 86, 4534 }, 4535 .delay = { 4536 .prepare = 1, /* 6.5 - 150µs PLL wake-up time */ 4537 .enable = 100, /* 6.4 - Power on: 6 VSyncs */ 4538 .disable = 84, /* 6.4 - Power off: 5 Vsyncs */ 4539 .unprepare = 50, /* 6.4 - Power off: 3 Vsyncs */ 4540 }, 4541 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4542 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4543 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4544 }; 4545 4546 static const struct drm_display_mode toshiba_lt089ac29000_mode = { 4547 .clock = 79500, 4548 .hdisplay = 1280, 4549 .hsync_start = 1280 + 192, 4550 .hsync_end = 1280 + 192 + 128, 4551 .htotal = 1280 + 192 + 128 + 64, 4552 .vdisplay = 768, 4553 .vsync_start = 768 + 20, 4554 .vsync_end = 768 + 20 + 7, 4555 .vtotal = 768 + 20 + 7 + 3, 4556 }; 4557 4558 static const struct panel_desc toshiba_lt089ac29000 = { 4559 .modes = &toshiba_lt089ac29000_mode, 4560 .num_modes = 1, 4561 .size = { 4562 .width = 194, 4563 .height = 116, 4564 }, 4565 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4566 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4567 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4568 }; 4569 4570 static const struct drm_display_mode tpk_f07a_0102_mode = { 4571 .clock = 33260, 4572 .hdisplay = 800, 4573 .hsync_start = 800 + 40, 4574 .hsync_end = 800 + 40 + 128, 4575 .htotal = 800 + 40 + 128 + 88, 4576 .vdisplay = 480, 4577 .vsync_start = 480 + 10, 4578 .vsync_end = 480 + 10 + 2, 4579 .vtotal = 480 + 10 + 2 + 33, 4580 }; 4581 4582 static const struct panel_desc tpk_f07a_0102 = { 4583 .modes = &tpk_f07a_0102_mode, 4584 .num_modes = 1, 4585 .size = { 4586 .width = 152, 4587 .height = 91, 4588 }, 4589 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, 4590 }; 4591 4592 static const struct drm_display_mode tpk_f10a_0102_mode = { 4593 .clock = 45000, 4594 .hdisplay = 1024, 4595 .hsync_start = 1024 + 176, 4596 .hsync_end = 1024 + 176 + 5, 4597 .htotal = 1024 + 176 + 5 + 88, 4598 .vdisplay = 600, 4599 .vsync_start = 600 + 20, 4600 .vsync_end = 600 + 20 + 5, 4601 .vtotal = 600 + 20 + 5 + 25, 4602 }; 4603 4604 static const struct panel_desc tpk_f10a_0102 = { 4605 .modes = &tpk_f10a_0102_mode, 4606 .num_modes = 1, 4607 .size = { 4608 .width = 223, 4609 .height = 125, 4610 }, 4611 }; 4612 4613 static const struct display_timing urt_umsh_8596md_timing = { 4614 .pixelclock = { 33260000, 33260000, 33260000 }, 4615 .hactive = { 800, 800, 800 }, 4616 .hfront_porch = { 41, 41, 41 }, 4617 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 }, 4618 .hsync_len = { 71, 128, 128 }, 4619 .vactive = { 480, 480, 480 }, 4620 .vfront_porch = { 10, 10, 10 }, 4621 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 }, 4622 .vsync_len = { 2, 2, 2 }, 4623 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE | 4624 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW, 4625 }; 4626 4627 static const struct panel_desc urt_umsh_8596md_lvds = { 4628 .timings = &urt_umsh_8596md_timing, 4629 .num_timings = 1, 4630 .bpc = 6, 4631 .size = { 4632 .width = 152, 4633 .height = 91, 4634 }, 4635 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4636 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4637 }; 4638 4639 static const struct panel_desc urt_umsh_8596md_parallel = { 4640 .timings = &urt_umsh_8596md_timing, 4641 .num_timings = 1, 4642 .bpc = 6, 4643 .size = { 4644 .width = 152, 4645 .height = 91, 4646 }, 4647 .bus_format = MEDIA_BUS_FMT_RGB666_1X18, 4648 }; 4649 4650 static const struct drm_display_mode vivax_tpc9150_panel_mode = { 4651 .clock = 60000, 4652 .hdisplay = 1024, 4653 .hsync_start = 1024 + 160, 4654 .hsync_end = 1024 + 160 + 100, 4655 .htotal = 1024 + 160 + 100 + 60, 4656 .vdisplay = 600, 4657 .vsync_start = 600 + 12, 4658 .vsync_end = 600 + 12 + 10, 4659 .vtotal = 600 + 12 + 10 + 13, 4660 }; 4661 4662 static const struct panel_desc vivax_tpc9150_panel = { 4663 .modes = &vivax_tpc9150_panel_mode, 4664 .num_modes = 1, 4665 .bpc = 6, 4666 .size = { 4667 .width = 200, 4668 .height = 115, 4669 }, 4670 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 4671 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4672 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4673 }; 4674 4675 static const struct drm_display_mode vl050_8048nt_c01_mode = { 4676 .clock = 33333, 4677 .hdisplay = 800, 4678 .hsync_start = 800 + 210, 4679 .hsync_end = 800 + 210 + 20, 4680 .htotal = 800 + 210 + 20 + 46, 4681 .vdisplay = 480, 4682 .vsync_start = 480 + 22, 4683 .vsync_end = 480 + 22 + 10, 4684 .vtotal = 480 + 22 + 10 + 23, 4685 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 4686 }; 4687 4688 static const struct panel_desc vl050_8048nt_c01 = { 4689 .modes = &vl050_8048nt_c01_mode, 4690 .num_modes = 1, 4691 .bpc = 8, 4692 .size = { 4693 .width = 120, 4694 .height = 76, 4695 }, 4696 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4697 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE, 4698 }; 4699 4700 static const struct drm_display_mode winstar_wf35ltiacd_mode = { 4701 .clock = 6410, 4702 .hdisplay = 320, 4703 .hsync_start = 320 + 20, 4704 .hsync_end = 320 + 20 + 30, 4705 .htotal = 320 + 20 + 30 + 38, 4706 .vdisplay = 240, 4707 .vsync_start = 240 + 4, 4708 .vsync_end = 240 + 4 + 3, 4709 .vtotal = 240 + 4 + 3 + 15, 4710 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4711 }; 4712 4713 static const struct panel_desc winstar_wf35ltiacd = { 4714 .modes = &winstar_wf35ltiacd_mode, 4715 .num_modes = 1, 4716 .bpc = 8, 4717 .size = { 4718 .width = 70, 4719 .height = 53, 4720 }, 4721 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4722 }; 4723 4724 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = { 4725 .clock = 51200, 4726 .hdisplay = 1024, 4727 .hsync_start = 1024 + 100, 4728 .hsync_end = 1024 + 100 + 100, 4729 .htotal = 1024 + 100 + 100 + 120, 4730 .vdisplay = 600, 4731 .vsync_start = 600 + 10, 4732 .vsync_end = 600 + 10 + 10, 4733 .vtotal = 600 + 10 + 10 + 15, 4734 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, 4735 }; 4736 4737 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = { 4738 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode, 4739 .num_modes = 1, 4740 .bpc = 8, 4741 .size = { 4742 .width = 154, 4743 .height = 90, 4744 }, 4745 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4746 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 4747 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4748 }; 4749 4750 static const struct drm_display_mode mchp_ac69t88a_mode = { 4751 .clock = 25000, 4752 .hdisplay = 800, 4753 .hsync_start = 800 + 88, 4754 .hsync_end = 800 + 88 + 5, 4755 .htotal = 800 + 88 + 5 + 40, 4756 .vdisplay = 480, 4757 .vsync_start = 480 + 23, 4758 .vsync_end = 480 + 23 + 5, 4759 .vtotal = 480 + 23 + 5 + 1, 4760 }; 4761 4762 static const struct panel_desc mchp_ac69t88a = { 4763 .modes = &mchp_ac69t88a_mode, 4764 .num_modes = 1, 4765 .bpc = 8, 4766 .size = { 4767 .width = 108, 4768 .height = 65, 4769 }, 4770 .bus_flags = DRM_BUS_FLAG_DE_HIGH, 4771 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 4772 .connector_type = DRM_MODE_CONNECTOR_LVDS, 4773 }; 4774 4775 static const struct drm_display_mode arm_rtsm_mode[] = { 4776 { 4777 .clock = 65000, 4778 .hdisplay = 1024, 4779 .hsync_start = 1024 + 24, 4780 .hsync_end = 1024 + 24 + 136, 4781 .htotal = 1024 + 24 + 136 + 160, 4782 .vdisplay = 768, 4783 .vsync_start = 768 + 3, 4784 .vsync_end = 768 + 3 + 6, 4785 .vtotal = 768 + 3 + 6 + 29, 4786 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 4787 }, 4788 }; 4789 4790 static const struct panel_desc arm_rtsm = { 4791 .modes = arm_rtsm_mode, 4792 .num_modes = 1, 4793 .bpc = 8, 4794 .size = { 4795 .width = 400, 4796 .height = 300, 4797 }, 4798 .bus_format = MEDIA_BUS_FMT_RGB888_1X24, 4799 }; 4800 4801 static const struct of_device_id platform_of_match[] = { 4802 { 4803 .compatible = "ampire,am-1280800n3tzqw-t00h", 4804 .data = &ire_am_1280800n3tzqw_t00h, 4805 }, { 4806 .compatible = "ampire,am-480272h3tmqw-t01h", 4807 .data = &ire_am_480272h3tmqw_t01h, 4808 }, { 4809 .compatible = "ampire,am-800480l1tmqw-t00h", 4810 .data = &ire_am_800480l1tmqw_t00h, 4811 }, { 4812 .compatible = "ampire,am800480r3tmqwa1h", 4813 .data = &ire_am800480r3tmqwa1h, 4814 }, { 4815 .compatible = "ampire,am800600p5tmqw-tb8h", 4816 .data = &ire_am800600p5tmqwtb8h, 4817 }, { 4818 .compatible = "arm,rtsm-display", 4819 .data = &arm_rtsm, 4820 }, { 4821 .compatible = "armadeus,st0700-adapt", 4822 .data = &armadeus_st0700_adapt, 4823 }, { 4824 .compatible = "auo,b101aw03", 4825 .data = &auo_b101aw03, 4826 }, { 4827 .compatible = "auo,b101xtn01", 4828 .data = &auo_b101xtn01, 4829 }, { 4830 .compatible = "auo,b116xw03", 4831 .data = &auo_b116xw03, 4832 }, { 4833 .compatible = "auo,g070vvn01", 4834 .data = &auo_g070vvn01, 4835 }, { 4836 .compatible = "auo,g101evn010", 4837 .data = &auo_g101evn010, 4838 }, { 4839 .compatible = "auo,g104sn02", 4840 .data = &auo_g104sn02, 4841 }, { 4842 .compatible = "auo,g104stn01", 4843 .data = &auo_g104stn01, 4844 }, { 4845 .compatible = "auo,g121ean01", 4846 .data = &auo_g121ean01, 4847 }, { 4848 .compatible = "auo,g133han01", 4849 .data = &auo_g133han01, 4850 }, { 4851 .compatible = "auo,g156han04", 4852 .data = &auo_g156han04, 4853 }, { 4854 .compatible = "auo,g156xtn01", 4855 .data = &auo_g156xtn01, 4856 }, { 4857 .compatible = "auo,g185han01", 4858 .data = &auo_g185han01, 4859 }, { 4860 .compatible = "auo,g190ean01", 4861 .data = &auo_g190ean01, 4862 }, { 4863 .compatible = "auo,p320hvn03", 4864 .data = &auo_p320hvn03, 4865 }, { 4866 .compatible = "auo,t215hvn01", 4867 .data = &auo_t215hvn01, 4868 }, { 4869 .compatible = "avic,tm070ddh03", 4870 .data = &avic_tm070ddh03, 4871 }, { 4872 .compatible = "bananapi,s070wv20-ct16", 4873 .data = &bananapi_s070wv20_ct16, 4874 }, { 4875 .compatible = "boe,av101hdt-a10", 4876 .data = &boe_av101hdt_a10, 4877 }, { 4878 .compatible = "boe,av123z7m-n17", 4879 .data = &boe_av123z7m_n17, 4880 }, { 4881 .compatible = "boe,bp082wx1-100", 4882 .data = &boe_bp082wx1_100, 4883 }, { 4884 .compatible = "boe,bp101wx1-100", 4885 .data = &boe_bp101wx1_100, 4886 }, { 4887 .compatible = "boe,ev121wxm-n10-1850", 4888 .data = &boe_ev121wxm_n10_1850, 4889 }, { 4890 .compatible = "boe,hv070wsa-100", 4891 .data = &boe_hv070wsa 4892 }, { 4893 .compatible = "cct,cmt430b19n00", 4894 .data = &cct_cmt430b19n00, 4895 }, { 4896 .compatible = "cdtech,s043wq26h-ct7", 4897 .data = &cdtech_s043wq26h_ct7, 4898 }, { 4899 .compatible = "cdtech,s070pws19hp-fc21", 4900 .data = &cdtech_s070pws19hp_fc21, 4901 }, { 4902 .compatible = "cdtech,s070swv29hg-dc44", 4903 .data = &cdtech_s070swv29hg_dc44, 4904 }, { 4905 .compatible = "cdtech,s070wv95-ct16", 4906 .data = &cdtech_s070wv95_ct16, 4907 }, { 4908 .compatible = "chefree,ch101olhlwh-002", 4909 .data = &chefree_ch101olhlwh_002, 4910 }, { 4911 .compatible = "chunghwa,claa070wp03xg", 4912 .data = &chunghwa_claa070wp03xg, 4913 }, { 4914 .compatible = "chunghwa,claa101wa01a", 4915 .data = &chunghwa_claa101wa01a 4916 }, { 4917 .compatible = "chunghwa,claa101wb01", 4918 .data = &chunghwa_claa101wb01 4919 }, { 4920 .compatible = "dataimage,fg040346dsswbg04", 4921 .data = &dataimage_fg040346dsswbg04, 4922 }, { 4923 .compatible = "dataimage,fg1001l0dsswmg01", 4924 .data = &dataimage_fg1001l0dsswmg01, 4925 }, { 4926 .compatible = "dataimage,scf0700c48ggu18", 4927 .data = &dataimage_scf0700c48ggu18, 4928 }, { 4929 .compatible = "dlc,dlc0700yzg-1", 4930 .data = &dlc_dlc0700yzg_1, 4931 }, { 4932 .compatible = "dlc,dlc1010gig", 4933 .data = &dlc_dlc1010gig, 4934 }, { 4935 .compatible = "edt,et035012dm6", 4936 .data = &edt_et035012dm6, 4937 }, { 4938 .compatible = "edt,etm0350g0dh6", 4939 .data = &edt_etm0350g0dh6, 4940 }, { 4941 .compatible = "edt,etm043080dh6gp", 4942 .data = &edt_etm043080dh6gp, 4943 }, { 4944 .compatible = "edt,etm0430g0dh6", 4945 .data = &edt_etm0430g0dh6, 4946 }, { 4947 .compatible = "edt,et057090dhu", 4948 .data = &edt_et057090dhu, 4949 }, { 4950 .compatible = "edt,et070080dh6", 4951 .data = &edt_etm0700g0dh6, 4952 }, { 4953 .compatible = "edt,etm0700g0dh6", 4954 .data = &edt_etm0700g0dh6, 4955 }, { 4956 .compatible = "edt,etm0700g0bdh6", 4957 .data = &edt_etm0700g0bdh6, 4958 }, { 4959 .compatible = "edt,etm0700g0edh6", 4960 .data = &edt_etm0700g0bdh6, 4961 }, { 4962 .compatible = "edt,etml0700y5dha", 4963 .data = &edt_etml0700y5dha, 4964 }, { 4965 .compatible = "edt,etml1010g3dra", 4966 .data = &edt_etml1010g3dra, 4967 }, { 4968 .compatible = "edt,etmv570g2dhu", 4969 .data = &edt_etmv570g2dhu, 4970 }, { 4971 .compatible = "eink,vb3300-kca", 4972 .data = &eink_vb3300_kca, 4973 }, { 4974 .compatible = "evervision,vgg644804", 4975 .data = &evervision_vgg644804, 4976 }, { 4977 .compatible = "evervision,vgg804821", 4978 .data = &evervision_vgg804821, 4979 }, { 4980 .compatible = "foxlink,fl500wvr00-a0t", 4981 .data = &foxlink_fl500wvr00_a0t, 4982 }, { 4983 .compatible = "frida,frd350h54004", 4984 .data = &frida_frd350h54004, 4985 }, { 4986 .compatible = "friendlyarm,hd702e", 4987 .data = &friendlyarm_hd702e, 4988 }, { 4989 .compatible = "giantplus,gpg482739qs5", 4990 .data = &giantplus_gpg482739qs5 4991 }, { 4992 .compatible = "giantplus,gpm940b0", 4993 .data = &giantplus_gpm940b0, 4994 }, { 4995 .compatible = "hannstar,hsd070pww1", 4996 .data = &hannstar_hsd070pww1, 4997 }, { 4998 .compatible = "hannstar,hsd100pxn1", 4999 .data = &hannstar_hsd100pxn1, 5000 }, { 5001 .compatible = "hannstar,hsd101pww2", 5002 .data = &hannstar_hsd101pww2, 5003 }, { 5004 .compatible = "hit,tx23d38vm0caa", 5005 .data = &hitachi_tx23d38vm0caa 5006 }, { 5007 .compatible = "innolux,at043tn24", 5008 .data = &innolux_at043tn24, 5009 }, { 5010 .compatible = "innolux,at070tn92", 5011 .data = &innolux_at070tn92, 5012 }, { 5013 .compatible = "innolux,g070ace-l01", 5014 .data = &innolux_g070ace_l01, 5015 }, { 5016 .compatible = "innolux,g070ace-lh3", 5017 .data = &innolux_g070ace_lh3, 5018 }, { 5019 .compatible = "innolux,g070y2-l01", 5020 .data = &innolux_g070y2_l01, 5021 }, { 5022 .compatible = "innolux,g070y2-t02", 5023 .data = &innolux_g070y2_t02, 5024 }, { 5025 .compatible = "innolux,g101ice-l01", 5026 .data = &innolux_g101ice_l01 5027 }, { 5028 .compatible = "innolux,g121i1-l01", 5029 .data = &innolux_g121i1_l01 5030 }, { 5031 .compatible = "innolux,g121x1-l03", 5032 .data = &innolux_g121x1_l03, 5033 }, { 5034 .compatible = "innolux,g121xce-l01", 5035 .data = &innolux_g121xce_l01, 5036 }, { 5037 .compatible = "innolux,g156hce-l01", 5038 .data = &innolux_g156hce_l01, 5039 }, { 5040 .compatible = "innolux,n156bge-l21", 5041 .data = &innolux_n156bge_l21, 5042 }, { 5043 .compatible = "innolux,zj070na-01p", 5044 .data = &innolux_zj070na_01p, 5045 }, { 5046 .compatible = "koe,tx14d24vm1bpa", 5047 .data = &koe_tx14d24vm1bpa, 5048 }, { 5049 .compatible = "koe,tx26d202vm0bwa", 5050 .data = &koe_tx26d202vm0bwa, 5051 }, { 5052 .compatible = "koe,tx31d200vm0baa", 5053 .data = &koe_tx31d200vm0baa, 5054 }, { 5055 .compatible = "kyo,tcg121xglp", 5056 .data = &kyo_tcg121xglp, 5057 }, { 5058 .compatible = "lemaker,bl035-rgb-002", 5059 .data = &lemaker_bl035_rgb_002, 5060 }, { 5061 .compatible = "lg,lb070wv8", 5062 .data = &lg_lb070wv8, 5063 }, { 5064 .compatible = "lincolntech,lcd185-101ct", 5065 .data = &lincolntech_lcd185_101ct, 5066 }, { 5067 .compatible = "logicpd,type28", 5068 .data = &logicpd_type_28, 5069 }, { 5070 .compatible = "logictechno,lt161010-2nhc", 5071 .data = &logictechno_lt161010_2nh, 5072 }, { 5073 .compatible = "logictechno,lt161010-2nhr", 5074 .data = &logictechno_lt161010_2nh, 5075 }, { 5076 .compatible = "logictechno,lt170410-2whc", 5077 .data = &logictechno_lt170410_2whc, 5078 }, { 5079 .compatible = "logictechno,lttd800480070-l2rt", 5080 .data = &logictechno_lttd800480070_l2rt, 5081 }, { 5082 .compatible = "logictechno,lttd800480070-l6wh-rt", 5083 .data = &logictechno_lttd800480070_l6wh_rt, 5084 }, { 5085 .compatible = "microtips,mf-101hiebcaf0", 5086 .data = µtips_mf_101hiebcaf0_c, 5087 }, { 5088 .compatible = "microtips,mf-103hieb0ga0", 5089 .data = µtips_mf_103hieb0ga0, 5090 }, { 5091 .compatible = "mitsubishi,aa070mc01-ca1", 5092 .data = &mitsubishi_aa070mc01, 5093 }, { 5094 .compatible = "mitsubishi,aa084xe01", 5095 .data = &mitsubishi_aa084xe01, 5096 }, { 5097 .compatible = "multi-inno,mi0700a2t-30", 5098 .data = &multi_inno_mi0700a2t_30, 5099 }, { 5100 .compatible = "multi-inno,mi0700s4t-6", 5101 .data = &multi_inno_mi0700s4t_6, 5102 }, { 5103 .compatible = "multi-inno,mi0800ft-9", 5104 .data = &multi_inno_mi0800ft_9, 5105 }, { 5106 .compatible = "multi-inno,mi1010ait-1cp", 5107 .data = &multi_inno_mi1010ait_1cp, 5108 }, { 5109 .compatible = "multi-inno,mi1010z1t-1cp11", 5110 .data = &multi_inno_mi1010z1t_1cp11, 5111 }, { 5112 .compatible = "nec,nl12880bc20-05", 5113 .data = &nec_nl12880bc20_05, 5114 }, { 5115 .compatible = "nec,nl4827hc19-05b", 5116 .data = &nec_nl4827hc19_05b, 5117 }, { 5118 .compatible = "netron-dy,e231732", 5119 .data = &netron_dy_e231732, 5120 }, { 5121 .compatible = "newhaven,nhd-4.3-480272ef-atxl", 5122 .data = &newhaven_nhd_43_480272ef_atxl, 5123 }, { 5124 .compatible = "nlt,nl192108ac18-02d", 5125 .data = &nlt_nl192108ac18_02d, 5126 }, { 5127 .compatible = "nvd,9128", 5128 .data = &nvd_9128, 5129 }, { 5130 .compatible = "okaya,rs800480t-7x0gp", 5131 .data = &okaya_rs800480t_7x0gp, 5132 }, { 5133 .compatible = "olimex,lcd-olinuxino-43-ts", 5134 .data = &olimex_lcd_olinuxino_43ts, 5135 }, { 5136 .compatible = "ontat,kd50g21-40nt-a1", 5137 .data = &ontat_kd50g21_40nt_a1, 5138 }, { 5139 .compatible = "ontat,yx700wv03", 5140 .data = &ontat_yx700wv03, 5141 }, { 5142 .compatible = "ortustech,com37h3m05dtc", 5143 .data = &ortustech_com37h3m, 5144 }, { 5145 .compatible = "ortustech,com37h3m99dtc", 5146 .data = &ortustech_com37h3m, 5147 }, { 5148 .compatible = "ortustech,com43h4m85ulc", 5149 .data = &ortustech_com43h4m85ulc, 5150 }, { 5151 .compatible = "osddisplays,osd070t1718-19ts", 5152 .data = &osddisplays_osd070t1718_19ts, 5153 }, { 5154 .compatible = "pda,91-00156-a0", 5155 .data = &pda_91_00156_a0, 5156 }, { 5157 .compatible = "powertip,ph128800t006-zhc01", 5158 .data = &powertip_ph128800t006_zhc01, 5159 }, { 5160 .compatible = "powertip,ph800480t013-idf02", 5161 .data = &powertip_ph800480t013_idf02, 5162 }, { 5163 .compatible = "primeview,pm070wl4", 5164 .data = &primeview_pm070wl4, 5165 }, { 5166 .compatible = "qiaodian,qd43003c0-40", 5167 .data = &qd43003c0_40, 5168 }, { 5169 .compatible = "qishenglong,gopher2b-lcd", 5170 .data = &qishenglong_gopher2b_lcd, 5171 }, { 5172 .compatible = "rocktech,rk043fn48h", 5173 .data = &rocktech_rk043fn48h, 5174 }, { 5175 .compatible = "rocktech,rk070er9427", 5176 .data = &rocktech_rk070er9427, 5177 }, { 5178 .compatible = "rocktech,rk101ii01d-ct", 5179 .data = &rocktech_rk101ii01d_ct, 5180 }, { 5181 .compatible = "samsung,ltl101al01", 5182 .data = &samsung_ltl101al01, 5183 }, { 5184 .compatible = "samsung,ltn101nt05", 5185 .data = &samsung_ltn101nt05, 5186 }, { 5187 .compatible = "satoz,sat050at40h12r2", 5188 .data = &satoz_sat050at40h12r2, 5189 }, { 5190 .compatible = "sharp,lq035q7db03", 5191 .data = &sharp_lq035q7db03, 5192 }, { 5193 .compatible = "sharp,lq070y3dg3b", 5194 .data = &sharp_lq070y3dg3b, 5195 }, { 5196 .compatible = "sharp,lq101k1ly04", 5197 .data = &sharp_lq101k1ly04, 5198 }, { 5199 .compatible = "sharp,ls020b1dd01d", 5200 .data = &sharp_ls020b1dd01d, 5201 }, { 5202 .compatible = "shelly,sca07010-bfn-lnn", 5203 .data = &shelly_sca07010_bfn_lnn, 5204 }, { 5205 .compatible = "starry,kr070pe2t", 5206 .data = &starry_kr070pe2t, 5207 }, { 5208 .compatible = "startek,kd070wvfpa", 5209 .data = &startek_kd070wvfpa, 5210 }, { 5211 .compatible = "team-source-display,tst043015cmhx", 5212 .data = &tsd_tst043015cmhx, 5213 }, { 5214 .compatible = "tfc,s9700rtwv43tr-01b", 5215 .data = &tfc_s9700rtwv43tr_01b, 5216 }, { 5217 .compatible = "tianma,tm070jdhg30", 5218 .data = &tianma_tm070jdhg30, 5219 }, { 5220 .compatible = "tianma,tm070jdhg34-00", 5221 .data = &tianma_tm070jdhg34_00, 5222 }, { 5223 .compatible = "tianma,tm070jvhg33", 5224 .data = &tianma_tm070jvhg33, 5225 }, { 5226 .compatible = "tianma,tm070rvhg71", 5227 .data = &tianma_tm070rvhg71, 5228 }, { 5229 .compatible = "ti,nspire-cx-lcd-panel", 5230 .data = &ti_nspire_cx_lcd_panel, 5231 }, { 5232 .compatible = "ti,nspire-classic-lcd-panel", 5233 .data = &ti_nspire_classic_lcd_panel, 5234 }, { 5235 .compatible = "toshiba,lt089ac29000", 5236 .data = &toshiba_lt089ac29000, 5237 }, { 5238 .compatible = "topland,tian-g07017-01", 5239 .data = &topland_tian_g07017_01, 5240 }, { 5241 .compatible = "tpk,f07a-0102", 5242 .data = &tpk_f07a_0102, 5243 }, { 5244 .compatible = "tpk,f10a-0102", 5245 .data = &tpk_f10a_0102, 5246 }, { 5247 .compatible = "urt,umsh-8596md-t", 5248 .data = &urt_umsh_8596md_parallel, 5249 }, { 5250 .compatible = "urt,umsh-8596md-1t", 5251 .data = &urt_umsh_8596md_parallel, 5252 }, { 5253 .compatible = "urt,umsh-8596md-7t", 5254 .data = &urt_umsh_8596md_parallel, 5255 }, { 5256 .compatible = "urt,umsh-8596md-11t", 5257 .data = &urt_umsh_8596md_lvds, 5258 }, { 5259 .compatible = "urt,umsh-8596md-19t", 5260 .data = &urt_umsh_8596md_lvds, 5261 }, { 5262 .compatible = "urt,umsh-8596md-20t", 5263 .data = &urt_umsh_8596md_parallel, 5264 }, { 5265 .compatible = "vivax,tpc9150-panel", 5266 .data = &vivax_tpc9150_panel, 5267 }, { 5268 .compatible = "vxt,vl050-8048nt-c01", 5269 .data = &vl050_8048nt_c01, 5270 }, { 5271 .compatible = "winstar,wf35ltiacd", 5272 .data = &winstar_wf35ltiacd, 5273 }, { 5274 .compatible = "yes-optoelectronics,ytc700tlag-05-201c", 5275 .data = &yes_optoelectronics_ytc700tlag_05_201c, 5276 }, { 5277 .compatible = "microchip,ac69t88a", 5278 .data = &mchp_ac69t88a, 5279 }, { 5280 /* Must be the last entry */ 5281 .compatible = "panel-dpi", 5282 .data = &panel_dpi, 5283 }, { 5284 /* sentinel */ 5285 } 5286 }; 5287 MODULE_DEVICE_TABLE(of, platform_of_match); 5288 5289 static int panel_simple_platform_probe(struct platform_device *pdev) 5290 { 5291 const struct panel_desc *desc; 5292 5293 desc = of_device_get_match_data(&pdev->dev); 5294 if (!desc) 5295 return -ENODEV; 5296 5297 return panel_simple_probe(&pdev->dev, desc); 5298 } 5299 5300 static void panel_simple_platform_remove(struct platform_device *pdev) 5301 { 5302 panel_simple_remove(&pdev->dev); 5303 } 5304 5305 static void panel_simple_platform_shutdown(struct platform_device *pdev) 5306 { 5307 panel_simple_shutdown(&pdev->dev); 5308 } 5309 5310 static const struct dev_pm_ops panel_simple_pm_ops = { 5311 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL) 5312 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 5313 pm_runtime_force_resume) 5314 }; 5315 5316 static struct platform_driver panel_simple_platform_driver = { 5317 .driver = { 5318 .name = "panel-simple", 5319 .of_match_table = platform_of_match, 5320 .pm = &panel_simple_pm_ops, 5321 }, 5322 .probe = panel_simple_platform_probe, 5323 .remove = panel_simple_platform_remove, 5324 .shutdown = panel_simple_platform_shutdown, 5325 }; 5326 5327 struct panel_desc_dsi { 5328 struct panel_desc desc; 5329 5330 unsigned long flags; 5331 enum mipi_dsi_pixel_format format; 5332 unsigned int lanes; 5333 }; 5334 5335 static const struct drm_display_mode auo_b080uan01_mode = { 5336 .clock = 154500, 5337 .hdisplay = 1200, 5338 .hsync_start = 1200 + 62, 5339 .hsync_end = 1200 + 62 + 4, 5340 .htotal = 1200 + 62 + 4 + 62, 5341 .vdisplay = 1920, 5342 .vsync_start = 1920 + 9, 5343 .vsync_end = 1920 + 9 + 2, 5344 .vtotal = 1920 + 9 + 2 + 8, 5345 }; 5346 5347 static const struct panel_desc_dsi auo_b080uan01 = { 5348 .desc = { 5349 .modes = &auo_b080uan01_mode, 5350 .num_modes = 1, 5351 .bpc = 8, 5352 .size = { 5353 .width = 108, 5354 .height = 272, 5355 }, 5356 .connector_type = DRM_MODE_CONNECTOR_DSI, 5357 }, 5358 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5359 .format = MIPI_DSI_FMT_RGB888, 5360 .lanes = 4, 5361 }; 5362 5363 static const struct drm_display_mode boe_tv080wum_nl0_mode = { 5364 .clock = 160000, 5365 .hdisplay = 1200, 5366 .hsync_start = 1200 + 120, 5367 .hsync_end = 1200 + 120 + 20, 5368 .htotal = 1200 + 120 + 20 + 21, 5369 .vdisplay = 1920, 5370 .vsync_start = 1920 + 21, 5371 .vsync_end = 1920 + 21 + 3, 5372 .vtotal = 1920 + 21 + 3 + 18, 5373 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, 5374 }; 5375 5376 static const struct panel_desc_dsi boe_tv080wum_nl0 = { 5377 .desc = { 5378 .modes = &boe_tv080wum_nl0_mode, 5379 .num_modes = 1, 5380 .size = { 5381 .width = 107, 5382 .height = 172, 5383 }, 5384 .connector_type = DRM_MODE_CONNECTOR_DSI, 5385 }, 5386 .flags = MIPI_DSI_MODE_VIDEO | 5387 MIPI_DSI_MODE_VIDEO_BURST | 5388 MIPI_DSI_MODE_VIDEO_SYNC_PULSE, 5389 .format = MIPI_DSI_FMT_RGB888, 5390 .lanes = 4, 5391 }; 5392 5393 static const struct drm_display_mode lg_ld070wx3_sl01_mode = { 5394 .clock = 71000, 5395 .hdisplay = 800, 5396 .hsync_start = 800 + 32, 5397 .hsync_end = 800 + 32 + 1, 5398 .htotal = 800 + 32 + 1 + 57, 5399 .vdisplay = 1280, 5400 .vsync_start = 1280 + 28, 5401 .vsync_end = 1280 + 28 + 1, 5402 .vtotal = 1280 + 28 + 1 + 14, 5403 }; 5404 5405 static const struct panel_desc_dsi lg_ld070wx3_sl01 = { 5406 .desc = { 5407 .modes = &lg_ld070wx3_sl01_mode, 5408 .num_modes = 1, 5409 .bpc = 8, 5410 .size = { 5411 .width = 94, 5412 .height = 151, 5413 }, 5414 .connector_type = DRM_MODE_CONNECTOR_DSI, 5415 }, 5416 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS, 5417 .format = MIPI_DSI_FMT_RGB888, 5418 .lanes = 4, 5419 }; 5420 5421 static const struct drm_display_mode lg_lh500wx1_sd03_mode = { 5422 .clock = 67000, 5423 .hdisplay = 720, 5424 .hsync_start = 720 + 12, 5425 .hsync_end = 720 + 12 + 4, 5426 .htotal = 720 + 12 + 4 + 112, 5427 .vdisplay = 1280, 5428 .vsync_start = 1280 + 8, 5429 .vsync_end = 1280 + 8 + 4, 5430 .vtotal = 1280 + 8 + 4 + 12, 5431 }; 5432 5433 static const struct panel_desc_dsi lg_lh500wx1_sd03 = { 5434 .desc = { 5435 .modes = &lg_lh500wx1_sd03_mode, 5436 .num_modes = 1, 5437 .bpc = 8, 5438 .size = { 5439 .width = 62, 5440 .height = 110, 5441 }, 5442 .connector_type = DRM_MODE_CONNECTOR_DSI, 5443 }, 5444 .flags = MIPI_DSI_MODE_VIDEO, 5445 .format = MIPI_DSI_FMT_RGB888, 5446 .lanes = 4, 5447 }; 5448 5449 static const struct drm_display_mode panasonic_vvx10f004b00_mode = { 5450 .clock = 157200, 5451 .hdisplay = 1920, 5452 .hsync_start = 1920 + 154, 5453 .hsync_end = 1920 + 154 + 16, 5454 .htotal = 1920 + 154 + 16 + 32, 5455 .vdisplay = 1200, 5456 .vsync_start = 1200 + 17, 5457 .vsync_end = 1200 + 17 + 2, 5458 .vtotal = 1200 + 17 + 2 + 16, 5459 }; 5460 5461 static const struct panel_desc_dsi panasonic_vvx10f004b00 = { 5462 .desc = { 5463 .modes = &panasonic_vvx10f004b00_mode, 5464 .num_modes = 1, 5465 .bpc = 8, 5466 .size = { 5467 .width = 217, 5468 .height = 136, 5469 }, 5470 .connector_type = DRM_MODE_CONNECTOR_DSI, 5471 }, 5472 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5473 MIPI_DSI_CLOCK_NON_CONTINUOUS, 5474 .format = MIPI_DSI_FMT_RGB888, 5475 .lanes = 4, 5476 }; 5477 5478 static const struct drm_display_mode lg_acx467akm_7_mode = { 5479 .clock = 150000, 5480 .hdisplay = 1080, 5481 .hsync_start = 1080 + 2, 5482 .hsync_end = 1080 + 2 + 2, 5483 .htotal = 1080 + 2 + 2 + 2, 5484 .vdisplay = 1920, 5485 .vsync_start = 1920 + 2, 5486 .vsync_end = 1920 + 2 + 2, 5487 .vtotal = 1920 + 2 + 2 + 2, 5488 }; 5489 5490 static const struct panel_desc_dsi lg_acx467akm_7 = { 5491 .desc = { 5492 .modes = &lg_acx467akm_7_mode, 5493 .num_modes = 1, 5494 .bpc = 8, 5495 .size = { 5496 .width = 62, 5497 .height = 110, 5498 }, 5499 .connector_type = DRM_MODE_CONNECTOR_DSI, 5500 }, 5501 .flags = 0, 5502 .format = MIPI_DSI_FMT_RGB888, 5503 .lanes = 4, 5504 }; 5505 5506 static const struct drm_display_mode osd101t2045_53ts_mode = { 5507 .clock = 154500, 5508 .hdisplay = 1920, 5509 .hsync_start = 1920 + 112, 5510 .hsync_end = 1920 + 112 + 16, 5511 .htotal = 1920 + 112 + 16 + 32, 5512 .vdisplay = 1200, 5513 .vsync_start = 1200 + 16, 5514 .vsync_end = 1200 + 16 + 2, 5515 .vtotal = 1200 + 16 + 2 + 16, 5516 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, 5517 }; 5518 5519 static const struct panel_desc_dsi osd101t2045_53ts = { 5520 .desc = { 5521 .modes = &osd101t2045_53ts_mode, 5522 .num_modes = 1, 5523 .bpc = 8, 5524 .size = { 5525 .width = 217, 5526 .height = 136, 5527 }, 5528 .connector_type = DRM_MODE_CONNECTOR_DSI, 5529 }, 5530 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 5531 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 5532 MIPI_DSI_MODE_NO_EOT_PACKET, 5533 .format = MIPI_DSI_FMT_RGB888, 5534 .lanes = 4, 5535 }; 5536 5537 static const struct of_device_id dsi_of_match[] = { 5538 { 5539 .compatible = "auo,b080uan01", 5540 .data = &auo_b080uan01 5541 }, { 5542 .compatible = "boe,tv080wum-nl0", 5543 .data = &boe_tv080wum_nl0 5544 }, { 5545 .compatible = "lg,ld070wx3-sl01", 5546 .data = &lg_ld070wx3_sl01 5547 }, { 5548 .compatible = "lg,lh500wx1-sd03", 5549 .data = &lg_lh500wx1_sd03 5550 }, { 5551 .compatible = "panasonic,vvx10f004b00", 5552 .data = &panasonic_vvx10f004b00 5553 }, { 5554 .compatible = "lg,acx467akm-7", 5555 .data = &lg_acx467akm_7 5556 }, { 5557 .compatible = "osddisplays,osd101t2045-53ts", 5558 .data = &osd101t2045_53ts 5559 }, { 5560 /* sentinel */ 5561 } 5562 }; 5563 MODULE_DEVICE_TABLE(of, dsi_of_match); 5564 5565 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi) 5566 { 5567 const struct panel_desc_dsi *desc; 5568 int err; 5569 5570 desc = of_device_get_match_data(&dsi->dev); 5571 if (!desc) 5572 return -ENODEV; 5573 5574 err = panel_simple_probe(&dsi->dev, &desc->desc); 5575 if (err < 0) 5576 return err; 5577 5578 dsi->mode_flags = desc->flags; 5579 dsi->format = desc->format; 5580 dsi->lanes = desc->lanes; 5581 5582 err = mipi_dsi_attach(dsi); 5583 if (err) { 5584 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi); 5585 5586 drm_panel_remove(&panel->base); 5587 } 5588 5589 return err; 5590 } 5591 5592 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi) 5593 { 5594 int err; 5595 5596 err = mipi_dsi_detach(dsi); 5597 if (err < 0) 5598 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err); 5599 5600 panel_simple_remove(&dsi->dev); 5601 } 5602 5603 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi) 5604 { 5605 panel_simple_shutdown(&dsi->dev); 5606 } 5607 5608 static struct mipi_dsi_driver panel_simple_dsi_driver = { 5609 .driver = { 5610 .name = "panel-simple-dsi", 5611 .of_match_table = dsi_of_match, 5612 .pm = &panel_simple_pm_ops, 5613 }, 5614 .probe = panel_simple_dsi_probe, 5615 .remove = panel_simple_dsi_remove, 5616 .shutdown = panel_simple_dsi_shutdown, 5617 }; 5618 5619 static int __init panel_simple_init(void) 5620 { 5621 int err; 5622 5623 err = platform_driver_register(&panel_simple_platform_driver); 5624 if (err < 0) 5625 return err; 5626 5627 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) { 5628 err = mipi_dsi_driver_register(&panel_simple_dsi_driver); 5629 if (err < 0) 5630 goto err_did_platform_register; 5631 } 5632 5633 return 0; 5634 5635 err_did_platform_register: 5636 platform_driver_unregister(&panel_simple_platform_driver); 5637 5638 return err; 5639 } 5640 module_init(panel_simple_init); 5641 5642 static void __exit panel_simple_exit(void) 5643 { 5644 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 5645 mipi_dsi_driver_unregister(&panel_simple_dsi_driver); 5646 5647 platform_driver_unregister(&panel_simple_platform_driver); 5648 } 5649 module_exit(panel_simple_exit); 5650 5651 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 5652 MODULE_DESCRIPTION("DRM Driver for Simple Panels"); 5653 MODULE_LICENSE("GPL and additional rights"); 5654