1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * OpenRISC Linux 4 * 5 * Linux architectural port borrowing liberally from similar works of 6 * others. All original copyrights apply as per the original source 7 * declaration. 8 * 9 * OpenRISC implementation: 10 * Copyright (C) Jan Henrik Weinstock <jan.weinstock@rwth-aachen.de> 11 * et al. 12 */ 13 14 #ifndef __ASM_CACHEFLUSH_H 15 #define __ASM_CACHEFLUSH_H 16 17 #include <linux/mm.h> 18 19 /* 20 * Helper function for flushing or invalidating entire pages from data 21 * and instruction caches. SMP needs a little extra work, since we need 22 * to flush the pages on all cpus. 23 */ 24 extern void local_dcache_page_flush(struct page *page); 25 extern void local_icache_page_inv(struct page *page); 26 extern void local_dcache_range_flush(unsigned long start, unsigned long end); 27 extern void local_dcache_range_inv(unsigned long start, unsigned long end); 28 extern void local_icache_range_inv(unsigned long start, unsigned long end); 29 extern void local_icache_all_inv(void); 30 31 /* 32 * Data cache flushing always happen on the local cpu. Instruction cache 33 * invalidations need to be broadcasted to all other cpu in the system in 34 * case of SMP configurations. 35 */ 36 #ifndef CONFIG_SMP 37 #define dcache_page_flush(page) local_dcache_page_flush(page) 38 #define icache_page_inv(page) local_icache_page_inv(page) 39 #define icache_all_inv() local_icache_all_inv() 40 #else /* CONFIG_SMP */ 41 #define dcache_page_flush(page) local_dcache_page_flush(page) 42 #define icache_page_inv(page) smp_icache_page_inv(page) 43 #define icache_all_inv() smp_icache_all_inv() 44 extern void smp_icache_page_inv(struct page *page); 45 extern void smp_icache_all_inv(void); 46 #endif /* CONFIG_SMP */ 47 48 /* 49 * Even if the actual block size is larger than L1_CACHE_BYTES, paddr 50 * can be incremented by L1_CACHE_BYTES. When paddr is written to the 51 * invalidate register, the entire cache line encompassing this address 52 * is invalidated. Each subsequent reference to the same cache line will 53 * not affect the invalidation process. 54 */ 55 #define local_dcache_block_flush(addr) \ 56 local_dcache_range_flush(addr, addr + L1_CACHE_BYTES) 57 #define local_dcache_block_inv(addr) \ 58 local_dcache_range_inv(addr, addr + L1_CACHE_BYTES) 59 #define local_icache_block_inv(addr) \ 60 local_icache_range_inv(addr, addr + L1_CACHE_BYTES) 61 62 /* 63 * Synchronizes caches. Whenever a cpu writes executable code to memory, this 64 * should be called to make sure the processor sees the newly written code. 65 */ 66 static inline void sync_icache_dcache(struct page *page) 67 { 68 if (!IS_ENABLED(CONFIG_DCACHE_WRITETHROUGH)) 69 dcache_page_flush(page); 70 icache_page_inv(page); 71 } 72 73 /* 74 * Pages with this bit set need not be flushed/invalidated, since 75 * they have not changed since last flush. New pages start with 76 * PG_arch_1 not set and are therefore dirty by default. 77 */ 78 #define PG_dc_clean PG_arch_1 79 80 static inline void flush_dcache_folio(struct folio *folio) 81 { 82 clear_bit(PG_dc_clean, &folio->flags.f); 83 } 84 #define flush_dcache_folio flush_dcache_folio 85 86 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 87 static inline void flush_dcache_page(struct page *page) 88 { 89 flush_dcache_folio(page_folio(page)); 90 } 91 92 #define flush_icache_user_page(vma, page, addr, len) \ 93 do { \ 94 if (vma->vm_flags & VM_EXEC) \ 95 sync_icache_dcache(page); \ 96 } while (0) 97 98 #include <asm-generic/cacheflush.h> 99 100 #endif /* __ASM_CACHEFLUSH_H */ 101