1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2025 Google LLC
4 * Author: Marc Zyngier <maz@kernel.org>
5 */
6
7 #include <linux/kvm_host.h>
8 #include <asm/kvm_emulate.h>
9 #include <asm/kvm_nested.h>
10 #include <asm/sysreg.h>
11
12 /*
13 * Describes the dependencies between a set of bits (or the negation
14 * of a set of RES0 bits) and a feature. The flags indicate how the
15 * data is interpreted.
16 */
17 struct reg_bits_to_feat_map {
18 union {
19 u64 bits;
20 struct fgt_masks *masks;
21 };
22
23 #define NEVER_FGU BIT(0) /* Can trap, but never UNDEF */
24 #define CALL_FUNC BIT(1) /* Needs to evaluate tons of crap */
25 #define FORCE_RESx BIT(2) /* Unconditional RESx */
26 #define MASKS_POINTER BIT(3) /* Pointer to fgt_masks struct instead of bits */
27 #define AS_RES1 BIT(4) /* RES1 when not supported */
28 #define REQUIRES_E2H1 BIT(5) /* Add HCR_EL2.E2H RES1 as a pre-condition */
29 #define RES1_WHEN_E2H0 BIT(6) /* RES1 when E2H=0 and not supported */
30 #define RES1_WHEN_E2H1 BIT(7) /* RES1 when E2H=1 and not supported */
31
32 unsigned long flags;
33
34 union {
35 struct {
36 u8 regidx;
37 u8 shift;
38 u8 width;
39 bool sign;
40 s8 lo_lim;
41 };
42 bool (*match)(struct kvm *);
43 };
44 };
45
46 /*
47 * Describes the dependencies for a given register:
48 *
49 * @feat_map describes the dependency for the whole register. If the
50 * features the register depends on are not present, the whole
51 * register is effectively RES0.
52 *
53 * @bit_feat_map describes the dependencies for a set of bits in that
54 * register. If the features these bits depend on are not present, the
55 * bits are effectively RES0.
56 */
57 struct reg_feat_map_desc {
58 const char *name;
59 const struct reg_bits_to_feat_map feat_map;
60 const struct reg_bits_to_feat_map *bit_feat_map;
61 const unsigned int bit_feat_map_sz;
62 };
63
64 #define __NEEDS_FEAT_3(m, f, w, id, fld, lim) \
65 { \
66 .w = (m), \
67 .flags = (f), \
68 .regidx = IDREG_IDX(SYS_ ## id), \
69 .shift = id ##_## fld ## _SHIFT, \
70 .width = id ##_## fld ## _WIDTH, \
71 .sign = id ##_## fld ## _SIGNED, \
72 .lo_lim = id ##_## fld ##_## lim \
73 }
74
75 #define __NEEDS_FEAT_1(m, f, w, fun) \
76 { \
77 .w = (m), \
78 .flags = (f) | CALL_FUNC, \
79 .match = (fun), \
80 }
81
82 #define __NEEDS_FEAT_0(m, f, w, ...) \
83 { \
84 .w = (m), \
85 .flags = (f), \
86 }
87
88 #define __NEEDS_FEAT_FLAG(m, f, w, ...) \
89 CONCATENATE(__NEEDS_FEAT_, COUNT_ARGS(__VA_ARGS__))(m, f, w, __VA_ARGS__)
90
91 #define NEEDS_FEAT_FLAG(m, f, ...) \
92 __NEEDS_FEAT_FLAG(m, f, bits, __VA_ARGS__)
93
94 #define NEEDS_FEAT_MASKS(p, ...) \
95 __NEEDS_FEAT_FLAG(p, MASKS_POINTER, masks, __VA_ARGS__)
96
97 /*
98 * Declare the dependency between a set of bits and a set of features,
99 * generating a struct reg_bit_to_feat_map.
100 */
101 #define NEEDS_FEAT(m, ...) NEEDS_FEAT_FLAG(m, 0, __VA_ARGS__)
102
103 /* Declare fixed RESx bits */
104 #define FORCE_RES0(m) NEEDS_FEAT_FLAG(m, FORCE_RESx)
105 #define FORCE_RES1(m) NEEDS_FEAT_FLAG(m, FORCE_RESx | AS_RES1)
106
107 /*
108 * Declare the dependency between a non-FGT register, a set of features,
109 * and the set of individual bits it contains. This generates a struct
110 * reg_feat_map_desc.
111 */
112 #define DECLARE_FEAT_MAP(n, r, m, f) \
113 struct reg_feat_map_desc n = { \
114 .name = #r, \
115 .feat_map = NEEDS_FEAT(~(r##_RES0 | \
116 r##_RES1), f), \
117 .bit_feat_map = m, \
118 .bit_feat_map_sz = ARRAY_SIZE(m), \
119 }
120
121 /*
122 * Specialised version of the above for FGT registers that have their
123 * RESx masks described as struct fgt_masks.
124 */
125 #define DECLARE_FEAT_MAP_FGT(n, msk, m, f) \
126 struct reg_feat_map_desc n = { \
127 .name = #msk, \
128 .feat_map = NEEDS_FEAT_MASKS(&msk, f), \
129 .bit_feat_map = m, \
130 .bit_feat_map_sz = ARRAY_SIZE(m), \
131 }
132
133 #define FEAT_SPE ID_AA64DFR0_EL1, PMSVer, IMP
134 #define FEAT_BRBE ID_AA64DFR0_EL1, BRBE, IMP
135 #define FEAT_TRC_SR ID_AA64DFR0_EL1, TraceVer, IMP
136 #define FEAT_PMUv3 ID_AA64DFR0_EL1, PMUVer, IMP
137 #define FEAT_TRBE ID_AA64DFR0_EL1, TraceBuffer, IMP
138 #define FEAT_TRBEv1p1 ID_AA64DFR0_EL1, TraceBuffer, TRBE_V1P1
139 #define FEAT_DoubleLock ID_AA64DFR0_EL1, DoubleLock, IMP
140 #define FEAT_TRF ID_AA64DFR0_EL1, TraceFilt, IMP
141 #define FEAT_AA32EL0 ID_AA64PFR0_EL1, EL0, AARCH32
142 #define FEAT_AA32EL1 ID_AA64PFR0_EL1, EL1, AARCH32
143 #define FEAT_AA64EL1 ID_AA64PFR0_EL1, EL1, IMP
144 #define FEAT_AA64EL2 ID_AA64PFR0_EL1, EL2, IMP
145 #define FEAT_AA64EL3 ID_AA64PFR0_EL1, EL3, IMP
146 #define FEAT_SEL2 ID_AA64PFR0_EL1, SEL2, IMP
147 #define FEAT_AIE ID_AA64MMFR3_EL1, AIE, IMP
148 #define FEAT_S2POE ID_AA64MMFR3_EL1, S2POE, IMP
149 #define FEAT_S1POE ID_AA64MMFR3_EL1, S1POE, IMP
150 #define FEAT_S1PIE ID_AA64MMFR3_EL1, S1PIE, IMP
151 #define FEAT_THE ID_AA64PFR1_EL1, THE, IMP
152 #define FEAT_SME ID_AA64PFR1_EL1, SME, IMP
153 #define FEAT_GCS ID_AA64PFR1_EL1, GCS, IMP
154 #define FEAT_LS64 ID_AA64ISAR1_EL1, LS64, LS64
155 #define FEAT_LS64_V ID_AA64ISAR1_EL1, LS64, LS64_V
156 #define FEAT_LS64_ACCDATA ID_AA64ISAR1_EL1, LS64, LS64_ACCDATA
157 #define FEAT_RAS ID_AA64PFR0_EL1, RAS, IMP
158 #define FEAT_RASv2 ID_AA64PFR0_EL1, RAS, V2
159 #define FEAT_GICv3 ID_AA64PFR0_EL1, GIC, IMP
160 #define FEAT_LOR ID_AA64MMFR1_EL1, LO, IMP
161 #define FEAT_SPEv1p2 ID_AA64DFR0_EL1, PMSVer, V1P2
162 #define FEAT_SPEv1p4 ID_AA64DFR0_EL1, PMSVer, V1P4
163 #define FEAT_SPEv1p5 ID_AA64DFR0_EL1, PMSVer, V1P5
164 #define FEAT_ATS1A ID_AA64ISAR2_EL1, ATS1A, IMP
165 #define FEAT_SPECRES2 ID_AA64ISAR1_EL1, SPECRES, COSP_RCTX
166 #define FEAT_SPECRES ID_AA64ISAR1_EL1, SPECRES, IMP
167 #define FEAT_TLBIRANGE ID_AA64ISAR0_EL1, TLB, RANGE
168 #define FEAT_TLBIOS ID_AA64ISAR0_EL1, TLB, OS
169 #define FEAT_PAN2 ID_AA64MMFR1_EL1, PAN, PAN2
170 #define FEAT_DPB2 ID_AA64ISAR1_EL1, DPB, DPB2
171 #define FEAT_AMUv1 ID_AA64PFR0_EL1, AMU, IMP
172 #define FEAT_AMUv1p1 ID_AA64PFR0_EL1, AMU, V1P1
173 #define FEAT_CMOW ID_AA64MMFR1_EL1, CMOW, IMP
174 #define FEAT_D128 ID_AA64MMFR3_EL1, D128, IMP
175 #define FEAT_DoubleFault2 ID_AA64PFR1_EL1, DF2, IMP
176 #define FEAT_FPMR ID_AA64PFR2_EL1, FPMR, IMP
177 #define FEAT_MOPS ID_AA64ISAR2_EL1, MOPS, IMP
178 #define FEAT_NMI ID_AA64PFR1_EL1, NMI, IMP
179 #define FEAT_SCTLR2 ID_AA64MMFR3_EL1, SCTLRX, IMP
180 #define FEAT_SYSREG128 ID_AA64ISAR2_EL1, SYSREG_128, IMP
181 #define FEAT_TCR2 ID_AA64MMFR3_EL1, TCRX, IMP
182 #define FEAT_XS ID_AA64ISAR1_EL1, XS, IMP
183 #define FEAT_EVT ID_AA64MMFR2_EL1, EVT, IMP
184 #define FEAT_EVT_TTLBxS ID_AA64MMFR2_EL1, EVT, TTLBxS
185 #define FEAT_MTE2 ID_AA64PFR1_EL1, MTE, MTE2
186 #define FEAT_RME ID_AA64PFR0_EL1, RME, IMP
187 #define FEAT_MPAM ID_AA64PFR0_EL1, MPAM, 1
188 #define FEAT_S2FWB ID_AA64MMFR2_EL1, FWB, IMP
189 #define FEAT_TWED ID_AA64MMFR1_EL1, TWED, IMP
190 #define FEAT_E2H0 ID_AA64MMFR4_EL1, E2H0, IMP
191 #define FEAT_SRMASK ID_AA64MMFR4_EL1, SRMASK, IMP
192 #define FEAT_PoPS ID_AA64MMFR4_EL1, PoPS, IMP
193 #define FEAT_PFAR ID_AA64PFR1_EL1, PFAR, IMP
194 #define FEAT_Debugv8p9 ID_AA64DFR0_EL1, DebugVer, V8P9
195 #define FEAT_PMUv3_SS ID_AA64DFR0_EL1, PMSS, IMP
196 #define FEAT_SEBEP ID_AA64DFR0_EL1, SEBEP, IMP
197 #define FEAT_EBEP ID_AA64DFR1_EL1, EBEP, IMP
198 #define FEAT_ITE ID_AA64DFR1_EL1, ITE, IMP
199 #define FEAT_PMUv3_ICNTR ID_AA64DFR1_EL1, PMICNTR, IMP
200 #define FEAT_SPMU ID_AA64DFR1_EL1, SPMU, IMP
201 #define FEAT_SPE_nVM ID_AA64DFR2_EL1, SPE_nVM, IMP
202 #define FEAT_STEP2 ID_AA64DFR2_EL1, STEP, IMP
203 #define FEAT_CPA2 ID_AA64ISAR3_EL1, CPA, CPA2
204 #define FEAT_ASID2 ID_AA64MMFR4_EL1, ASID2, IMP
205 #define FEAT_MEC ID_AA64MMFR3_EL1, MEC, IMP
206 #define FEAT_HAFT ID_AA64MMFR1_EL1, HAFDBS, HAFT
207 #define FEAT_HDBSS ID_AA64MMFR1_EL1, HAFDBS, HDBSS
208 #define FEAT_HPDS2 ID_AA64MMFR1_EL1, HPDS, HPDS2
209 #define FEAT_BTI ID_AA64PFR1_EL1, BT, IMP
210 #define FEAT_ExS ID_AA64MMFR0_EL1, EXS, IMP
211 #define FEAT_IESB ID_AA64MMFR2_EL1, IESB, IMP
212 #define FEAT_LSE2 ID_AA64MMFR2_EL1, AT, IMP
213 #define FEAT_LSMAOC ID_AA64MMFR2_EL1, LSM, IMP
214 #define FEAT_MixedEnd ID_AA64MMFR0_EL1, BIGEND, IMP
215 #define FEAT_MixedEndEL0 ID_AA64MMFR0_EL1, BIGENDEL0, IMP
216 #define FEAT_MTE_ASYNC ID_AA64PFR1_EL1, MTE_frac, ASYNC
217 #define FEAT_MTE_STORE_ONLY ID_AA64PFR2_EL1, MTESTOREONLY, IMP
218 #define FEAT_PAN ID_AA64MMFR1_EL1, PAN, IMP
219 #define FEAT_PAN3 ID_AA64MMFR1_EL1, PAN, PAN3
220 #define FEAT_SSBS ID_AA64PFR1_EL1, SSBS, IMP
221 #define FEAT_TIDCP1 ID_AA64MMFR1_EL1, TIDCP1, IMP
222 #define FEAT_FGT ID_AA64MMFR0_EL1, FGT, IMP
223 #define FEAT_FGT2 ID_AA64MMFR0_EL1, FGT, FGT2
224 #define FEAT_MTPMU ID_AA64DFR0_EL1, MTPMU, IMP
225 #define FEAT_HCX ID_AA64MMFR1_EL1, HCX, IMP
226 #define FEAT_S2PIE ID_AA64MMFR3_EL1, S2PIE, IMP
227 #define FEAT_GCIE ID_AA64PFR2_EL1, GCIE, IMP
228 #define FEAT_NV3 ID_AA64MMFR4_EL1, NV_frac, NV3
229
not_feat_aa64el3(struct kvm * kvm)230 static bool not_feat_aa64el3(struct kvm *kvm)
231 {
232 return !kvm_has_feat(kvm, FEAT_AA64EL3);
233 }
234
feat_nv2(struct kvm * kvm)235 static bool feat_nv2(struct kvm *kvm)
236 {
237 return ((kvm_has_feat(kvm, ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) &&
238 kvm_has_feat_enum(kvm, ID_AA64MMFR2_EL1, NV, NI)) ||
239 kvm_has_feat(kvm, ID_AA64MMFR2_EL1, NV, NV2));
240 }
241
feat_nv2_e2h0_ni(struct kvm * kvm)242 static bool feat_nv2_e2h0_ni(struct kvm *kvm)
243 {
244 return feat_nv2(kvm) && !kvm_has_feat(kvm, FEAT_E2H0);
245 }
246
feat_rasv1p1(struct kvm * kvm)247 static bool feat_rasv1p1(struct kvm *kvm)
248 {
249 return (kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, V1P1) ||
250 (kvm_has_feat_enum(kvm, ID_AA64PFR0_EL1, RAS, IMP) &&
251 kvm_has_feat(kvm, ID_AA64PFR1_EL1, RAS_frac, RASv1p1)));
252 }
253
feat_csv2_2_csv2_1p2(struct kvm * kvm)254 static bool feat_csv2_2_csv2_1p2(struct kvm *kvm)
255 {
256 return (kvm_has_feat(kvm, ID_AA64PFR0_EL1, CSV2, CSV2_2) ||
257 (kvm_has_feat(kvm, ID_AA64PFR1_EL1, CSV2_frac, CSV2_1p2) &&
258 kvm_has_feat_enum(kvm, ID_AA64PFR0_EL1, CSV2, IMP)));
259 }
260
feat_pauth(struct kvm * kvm)261 static bool feat_pauth(struct kvm *kvm)
262 {
263 return kvm_has_pauth(kvm, PAuth);
264 }
265
feat_pauth_lr(struct kvm * kvm)266 static bool feat_pauth_lr(struct kvm *kvm)
267 {
268 return kvm_has_pauth(kvm, PAuth_LR);
269 }
270
feat_aderr(struct kvm * kvm)271 static bool feat_aderr(struct kvm *kvm)
272 {
273 return (kvm_has_feat(kvm, ID_AA64MMFR3_EL1, ADERR, FEAT_ADERR) &&
274 kvm_has_feat(kvm, ID_AA64MMFR3_EL1, SDERR, FEAT_ADERR));
275 }
276
feat_anerr(struct kvm * kvm)277 static bool feat_anerr(struct kvm *kvm)
278 {
279 return (kvm_has_feat(kvm, ID_AA64MMFR3_EL1, ANERR, FEAT_ANERR) &&
280 kvm_has_feat(kvm, ID_AA64MMFR3_EL1, SNERR, FEAT_ANERR));
281 }
282
feat_sme_smps(struct kvm * kvm)283 static bool feat_sme_smps(struct kvm *kvm)
284 {
285 /*
286 * Revisit this if KVM ever supports SME -- this really should
287 * look at the guest's view of SMIDR_EL1. Funnily enough, this
288 * is not captured in the JSON file, but only as a note in the
289 * ARM ARM.
290 */
291 return (kvm_has_feat(kvm, FEAT_SME) &&
292 (read_sysreg_s(SYS_SMIDR_EL1) & SMIDR_EL1_SMPS));
293 }
294
feat_spe_fds(struct kvm * kvm)295 static bool feat_spe_fds(struct kvm *kvm)
296 {
297 /*
298 * Revisit this if KVM ever supports SPE -- this really should
299 * look at the guest's view of PMSIDR_EL1.
300 */
301 return (kvm_has_feat(kvm, FEAT_SPEv1p4) &&
302 (read_sysreg_s(SYS_PMSIDR_EL1) & PMSIDR_EL1_FDS));
303 }
304
feat_spe_fne(struct kvm * kvm)305 static bool feat_spe_fne(struct kvm *kvm)
306 {
307 /*
308 * Revisit this if KVM ever supports SPE -- this really should
309 * look at the guest's view of PMSIDR_EL1.
310 */
311 return (kvm_has_feat(kvm, FEAT_SPEv1p2) &&
312 (read_sysreg_s(SYS_PMSIDR_EL1) & PMSIDR_EL1_FnE));
313 }
314
feat_trbe_mpam(struct kvm * kvm)315 static bool feat_trbe_mpam(struct kvm *kvm)
316 {
317 /*
318 * Revisit this if KVM ever supports both MPAM and TRBE --
319 * this really should look at the guest's view of TRBIDR_EL1.
320 */
321 return (kvm_has_feat(kvm, FEAT_TRBE) &&
322 kvm_has_feat(kvm, FEAT_MPAM) &&
323 (read_sysreg_s(SYS_TRBIDR_EL1) & TRBIDR_EL1_MPAM));
324 }
325
feat_ebep_pmuv3_ss(struct kvm * kvm)326 static bool feat_ebep_pmuv3_ss(struct kvm *kvm)
327 {
328 return kvm_has_feat(kvm, FEAT_EBEP) || kvm_has_feat(kvm, FEAT_PMUv3_SS);
329 }
330
feat_mixedendel0(struct kvm * kvm)331 static bool feat_mixedendel0(struct kvm *kvm)
332 {
333 return kvm_has_feat(kvm, FEAT_MixedEnd) || kvm_has_feat(kvm, FEAT_MixedEndEL0);
334 }
335
feat_mte_async(struct kvm * kvm)336 static bool feat_mte_async(struct kvm *kvm)
337 {
338 return kvm_has_feat(kvm, FEAT_MTE2) && kvm_has_feat_enum(kvm, FEAT_MTE_ASYNC);
339 }
340
341 #define check_pmu_revision(k, r) \
342 ({ \
343 (kvm_has_feat((k), ID_AA64DFR0_EL1, PMUVer, r) && \
344 !kvm_has_feat((k), ID_AA64DFR0_EL1, PMUVer, IMP_DEF)); \
345 })
346
feat_pmuv3p1(struct kvm * kvm)347 static bool feat_pmuv3p1(struct kvm *kvm)
348 {
349 return check_pmu_revision(kvm, V3P1);
350 }
351
feat_pmuv3p5(struct kvm * kvm)352 static bool feat_pmuv3p5(struct kvm *kvm)
353 {
354 return check_pmu_revision(kvm, V3P5);
355 }
356
feat_pmuv3p7(struct kvm * kvm)357 static bool feat_pmuv3p7(struct kvm *kvm)
358 {
359 return check_pmu_revision(kvm, V3P7);
360 }
361
feat_pmuv3p9(struct kvm * kvm)362 static bool feat_pmuv3p9(struct kvm *kvm)
363 {
364 return check_pmu_revision(kvm, V3P9);
365 }
366
367 #define has_feat_s2tgran(k, s) \
368 ((kvm_has_feat_enum(kvm, ID_AA64MMFR0_EL1, TGRAN##s##_2, TGRAN##s) && \
369 kvm_has_feat(kvm, ID_AA64MMFR0_EL1, TGRAN##s, IMP)) || \
370 kvm_has_feat(kvm, ID_AA64MMFR0_EL1, TGRAN##s##_2, IMP))
371
feat_lpa2(struct kvm * kvm)372 static bool feat_lpa2(struct kvm *kvm)
373 {
374 return ((kvm_has_feat(kvm, ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) ||
375 !kvm_has_feat(kvm, ID_AA64MMFR0_EL1, TGRAN4, IMP)) &&
376 (kvm_has_feat(kvm, ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) ||
377 !kvm_has_feat(kvm, ID_AA64MMFR0_EL1, TGRAN16, IMP)) &&
378 (kvm_has_feat(kvm, ID_AA64MMFR0_EL1, TGRAN4_2, 52_BIT) ||
379 !has_feat_s2tgran(kvm, 4)) &&
380 (kvm_has_feat(kvm, ID_AA64MMFR0_EL1, TGRAN16_2, 52_BIT) ||
381 !has_feat_s2tgran(kvm, 16)));
382 }
383
feat_vmid16(struct kvm * kvm)384 static bool feat_vmid16(struct kvm *kvm)
385 {
386 return kvm_has_feat_enum(kvm, ID_AA64MMFR1_EL1, VMIDBits, 16);
387 }
388
389 static const struct reg_bits_to_feat_map hfgrtr_feat_map[] = {
390 NEEDS_FEAT(HFGRTR_EL2_nAMAIR2_EL1 |
391 HFGRTR_EL2_nMAIR2_EL1,
392 FEAT_AIE),
393 NEEDS_FEAT(HFGRTR_EL2_nS2POR_EL1, FEAT_S2POE),
394 NEEDS_FEAT(HFGRTR_EL2_nPOR_EL1 |
395 HFGRTR_EL2_nPOR_EL0,
396 FEAT_S1POE),
397 NEEDS_FEAT(HFGRTR_EL2_nPIR_EL1 |
398 HFGRTR_EL2_nPIRE0_EL1,
399 FEAT_S1PIE),
400 NEEDS_FEAT(HFGRTR_EL2_nRCWMASK_EL1, FEAT_THE),
401 NEEDS_FEAT(HFGRTR_EL2_nTPIDR2_EL0 |
402 HFGRTR_EL2_nSMPRI_EL1,
403 FEAT_SME),
404 NEEDS_FEAT(HFGRTR_EL2_nGCS_EL1 |
405 HFGRTR_EL2_nGCS_EL0,
406 FEAT_GCS),
407 NEEDS_FEAT(HFGRTR_EL2_nACCDATA_EL1, FEAT_LS64_ACCDATA),
408 NEEDS_FEAT(HFGRTR_EL2_ERXADDR_EL1 |
409 HFGRTR_EL2_ERXMISCn_EL1 |
410 HFGRTR_EL2_ERXSTATUS_EL1 |
411 HFGRTR_EL2_ERXCTLR_EL1 |
412 HFGRTR_EL2_ERXFR_EL1 |
413 HFGRTR_EL2_ERRSELR_EL1 |
414 HFGRTR_EL2_ERRIDR_EL1,
415 FEAT_RAS),
416 NEEDS_FEAT(HFGRTR_EL2_ERXPFGCDN_EL1 |
417 HFGRTR_EL2_ERXPFGCTL_EL1 |
418 HFGRTR_EL2_ERXPFGF_EL1,
419 feat_rasv1p1),
420 NEEDS_FEAT(HFGRTR_EL2_ICC_IGRPENn_EL1, FEAT_GICv3),
421 NEEDS_FEAT(HFGRTR_EL2_SCXTNUM_EL0 |
422 HFGRTR_EL2_SCXTNUM_EL1,
423 feat_csv2_2_csv2_1p2),
424 NEEDS_FEAT(HFGRTR_EL2_LORSA_EL1 |
425 HFGRTR_EL2_LORN_EL1 |
426 HFGRTR_EL2_LORID_EL1 |
427 HFGRTR_EL2_LOREA_EL1 |
428 HFGRTR_EL2_LORC_EL1,
429 FEAT_LOR),
430 NEEDS_FEAT(HFGRTR_EL2_APIBKey |
431 HFGRTR_EL2_APIAKey |
432 HFGRTR_EL2_APGAKey |
433 HFGRTR_EL2_APDBKey |
434 HFGRTR_EL2_APDAKey,
435 feat_pauth),
436 NEEDS_FEAT_FLAG(HFGRTR_EL2_VBAR_EL1 |
437 HFGRTR_EL2_TTBR1_EL1 |
438 HFGRTR_EL2_TTBR0_EL1 |
439 HFGRTR_EL2_TPIDR_EL0 |
440 HFGRTR_EL2_TPIDRRO_EL0 |
441 HFGRTR_EL2_TPIDR_EL1 |
442 HFGRTR_EL2_TCR_EL1 |
443 HFGRTR_EL2_SCTLR_EL1 |
444 HFGRTR_EL2_REVIDR_EL1 |
445 HFGRTR_EL2_PAR_EL1 |
446 HFGRTR_EL2_MPIDR_EL1 |
447 HFGRTR_EL2_MIDR_EL1 |
448 HFGRTR_EL2_MAIR_EL1 |
449 HFGRTR_EL2_ISR_EL1 |
450 HFGRTR_EL2_FAR_EL1 |
451 HFGRTR_EL2_ESR_EL1 |
452 HFGRTR_EL2_DCZID_EL0 |
453 HFGRTR_EL2_CTR_EL0 |
454 HFGRTR_EL2_CSSELR_EL1 |
455 HFGRTR_EL2_CPACR_EL1 |
456 HFGRTR_EL2_CONTEXTIDR_EL1|
457 HFGRTR_EL2_CLIDR_EL1 |
458 HFGRTR_EL2_CCSIDR_EL1 |
459 HFGRTR_EL2_AMAIR_EL1 |
460 HFGRTR_EL2_AIDR_EL1 |
461 HFGRTR_EL2_AFSR1_EL1 |
462 HFGRTR_EL2_AFSR0_EL1,
463 NEVER_FGU, FEAT_AA64EL1),
464 };
465
466
467 static const DECLARE_FEAT_MAP_FGT(hfgrtr_desc, hfgrtr_masks,
468 hfgrtr_feat_map, FEAT_FGT);
469
470 static const struct reg_bits_to_feat_map hfgwtr_feat_map[] = {
471 NEEDS_FEAT(HFGWTR_EL2_nAMAIR2_EL1 |
472 HFGWTR_EL2_nMAIR2_EL1,
473 FEAT_AIE),
474 NEEDS_FEAT(HFGWTR_EL2_nS2POR_EL1, FEAT_S2POE),
475 NEEDS_FEAT(HFGWTR_EL2_nPOR_EL1 |
476 HFGWTR_EL2_nPOR_EL0,
477 FEAT_S1POE),
478 NEEDS_FEAT(HFGWTR_EL2_nPIR_EL1 |
479 HFGWTR_EL2_nPIRE0_EL1,
480 FEAT_S1PIE),
481 NEEDS_FEAT(HFGWTR_EL2_nRCWMASK_EL1, FEAT_THE),
482 NEEDS_FEAT(HFGWTR_EL2_nTPIDR2_EL0 |
483 HFGWTR_EL2_nSMPRI_EL1,
484 FEAT_SME),
485 NEEDS_FEAT(HFGWTR_EL2_nGCS_EL1 |
486 HFGWTR_EL2_nGCS_EL0,
487 FEAT_GCS),
488 NEEDS_FEAT(HFGWTR_EL2_nACCDATA_EL1, FEAT_LS64_ACCDATA),
489 NEEDS_FEAT(HFGWTR_EL2_ERXADDR_EL1 |
490 HFGWTR_EL2_ERXMISCn_EL1 |
491 HFGWTR_EL2_ERXSTATUS_EL1 |
492 HFGWTR_EL2_ERXCTLR_EL1 |
493 HFGWTR_EL2_ERRSELR_EL1,
494 FEAT_RAS),
495 NEEDS_FEAT(HFGWTR_EL2_ERXPFGCDN_EL1 |
496 HFGWTR_EL2_ERXPFGCTL_EL1,
497 feat_rasv1p1),
498 NEEDS_FEAT(HFGWTR_EL2_ICC_IGRPENn_EL1, FEAT_GICv3),
499 NEEDS_FEAT(HFGWTR_EL2_SCXTNUM_EL0 |
500 HFGWTR_EL2_SCXTNUM_EL1,
501 feat_csv2_2_csv2_1p2),
502 NEEDS_FEAT(HFGWTR_EL2_LORSA_EL1 |
503 HFGWTR_EL2_LORN_EL1 |
504 HFGWTR_EL2_LOREA_EL1 |
505 HFGWTR_EL2_LORC_EL1,
506 FEAT_LOR),
507 NEEDS_FEAT(HFGWTR_EL2_APIBKey |
508 HFGWTR_EL2_APIAKey |
509 HFGWTR_EL2_APGAKey |
510 HFGWTR_EL2_APDBKey |
511 HFGWTR_EL2_APDAKey,
512 feat_pauth),
513 NEEDS_FEAT_FLAG(HFGWTR_EL2_VBAR_EL1 |
514 HFGWTR_EL2_TTBR1_EL1 |
515 HFGWTR_EL2_TTBR0_EL1 |
516 HFGWTR_EL2_TPIDR_EL0 |
517 HFGWTR_EL2_TPIDRRO_EL0 |
518 HFGWTR_EL2_TPIDR_EL1 |
519 HFGWTR_EL2_TCR_EL1 |
520 HFGWTR_EL2_SCTLR_EL1 |
521 HFGWTR_EL2_PAR_EL1 |
522 HFGWTR_EL2_MAIR_EL1 |
523 HFGWTR_EL2_FAR_EL1 |
524 HFGWTR_EL2_ESR_EL1 |
525 HFGWTR_EL2_CSSELR_EL1 |
526 HFGWTR_EL2_CPACR_EL1 |
527 HFGWTR_EL2_CONTEXTIDR_EL1|
528 HFGWTR_EL2_AMAIR_EL1 |
529 HFGWTR_EL2_AFSR1_EL1 |
530 HFGWTR_EL2_AFSR0_EL1,
531 NEVER_FGU, FEAT_AA64EL1),
532 };
533
534 static const DECLARE_FEAT_MAP_FGT(hfgwtr_desc, hfgwtr_masks,
535 hfgwtr_feat_map, FEAT_FGT);
536
537 static const struct reg_bits_to_feat_map hdfgrtr_feat_map[] = {
538 NEEDS_FEAT(HDFGRTR_EL2_PMBIDR_EL1 |
539 HDFGRTR_EL2_PMSLATFR_EL1 |
540 HDFGRTR_EL2_PMSIRR_EL1 |
541 HDFGRTR_EL2_PMSIDR_EL1 |
542 HDFGRTR_EL2_PMSICR_EL1 |
543 HDFGRTR_EL2_PMSFCR_EL1 |
544 HDFGRTR_EL2_PMSEVFR_EL1 |
545 HDFGRTR_EL2_PMSCR_EL1 |
546 HDFGRTR_EL2_PMBSR_EL1 |
547 HDFGRTR_EL2_PMBPTR_EL1 |
548 HDFGRTR_EL2_PMBLIMITR_EL1,
549 FEAT_SPE),
550 NEEDS_FEAT(HDFGRTR_EL2_nPMSNEVFR_EL1, feat_spe_fne),
551 NEEDS_FEAT(HDFGRTR_EL2_nBRBDATA |
552 HDFGRTR_EL2_nBRBCTL |
553 HDFGRTR_EL2_nBRBIDR,
554 FEAT_BRBE),
555 NEEDS_FEAT(HDFGRTR_EL2_TRCVICTLR |
556 HDFGRTR_EL2_TRCSTATR |
557 HDFGRTR_EL2_TRCSSCSRn |
558 HDFGRTR_EL2_TRCSEQSTR |
559 HDFGRTR_EL2_TRCPRGCTLR |
560 HDFGRTR_EL2_TRCOSLSR |
561 HDFGRTR_EL2_TRCIMSPECn |
562 HDFGRTR_EL2_TRCID |
563 HDFGRTR_EL2_TRCCNTVRn |
564 HDFGRTR_EL2_TRCCLAIM |
565 HDFGRTR_EL2_TRCAUXCTLR |
566 HDFGRTR_EL2_TRCAUTHSTATUS |
567 HDFGRTR_EL2_TRC,
568 FEAT_TRC_SR),
569 NEEDS_FEAT(HDFGRTR_EL2_PMCEIDn_EL0 |
570 HDFGRTR_EL2_PMUSERENR_EL0 |
571 HDFGRTR_EL2_PMMIR_EL1 |
572 HDFGRTR_EL2_PMSELR_EL0 |
573 HDFGRTR_EL2_PMOVS |
574 HDFGRTR_EL2_PMINTEN |
575 HDFGRTR_EL2_PMCNTEN |
576 HDFGRTR_EL2_PMCCNTR_EL0 |
577 HDFGRTR_EL2_PMCCFILTR_EL0 |
578 HDFGRTR_EL2_PMEVTYPERn_EL0 |
579 HDFGRTR_EL2_PMEVCNTRn_EL0,
580 FEAT_PMUv3),
581 NEEDS_FEAT(HDFGRTR_EL2_TRBTRG_EL1 |
582 HDFGRTR_EL2_TRBSR_EL1 |
583 HDFGRTR_EL2_TRBPTR_EL1 |
584 HDFGRTR_EL2_TRBMAR_EL1 |
585 HDFGRTR_EL2_TRBLIMITR_EL1 |
586 HDFGRTR_EL2_TRBIDR_EL1 |
587 HDFGRTR_EL2_TRBBASER_EL1,
588 FEAT_TRBE),
589 NEEDS_FEAT_FLAG(HDFGRTR_EL2_OSDLR_EL1, NEVER_FGU,
590 FEAT_DoubleLock),
591 NEEDS_FEAT_FLAG(HDFGRTR_EL2_OSECCR_EL1 |
592 HDFGRTR_EL2_OSLSR_EL1 |
593 HDFGRTR_EL2_DBGPRCR_EL1 |
594 HDFGRTR_EL2_DBGAUTHSTATUS_EL1|
595 HDFGRTR_EL2_DBGCLAIM |
596 HDFGRTR_EL2_MDSCR_EL1 |
597 HDFGRTR_EL2_DBGWVRn_EL1 |
598 HDFGRTR_EL2_DBGWCRn_EL1 |
599 HDFGRTR_EL2_DBGBVRn_EL1 |
600 HDFGRTR_EL2_DBGBCRn_EL1,
601 NEVER_FGU, FEAT_AA64EL1)
602 };
603
604 static const DECLARE_FEAT_MAP_FGT(hdfgrtr_desc, hdfgrtr_masks,
605 hdfgrtr_feat_map, FEAT_FGT);
606
607 static const struct reg_bits_to_feat_map hdfgwtr_feat_map[] = {
608 NEEDS_FEAT(HDFGWTR_EL2_PMSLATFR_EL1 |
609 HDFGWTR_EL2_PMSIRR_EL1 |
610 HDFGWTR_EL2_PMSICR_EL1 |
611 HDFGWTR_EL2_PMSFCR_EL1 |
612 HDFGWTR_EL2_PMSEVFR_EL1 |
613 HDFGWTR_EL2_PMSCR_EL1 |
614 HDFGWTR_EL2_PMBSR_EL1 |
615 HDFGWTR_EL2_PMBPTR_EL1 |
616 HDFGWTR_EL2_PMBLIMITR_EL1,
617 FEAT_SPE),
618 NEEDS_FEAT(HDFGWTR_EL2_nPMSNEVFR_EL1, feat_spe_fne),
619 NEEDS_FEAT(HDFGWTR_EL2_nBRBDATA |
620 HDFGWTR_EL2_nBRBCTL,
621 FEAT_BRBE),
622 NEEDS_FEAT(HDFGWTR_EL2_TRCVICTLR |
623 HDFGWTR_EL2_TRCSSCSRn |
624 HDFGWTR_EL2_TRCSEQSTR |
625 HDFGWTR_EL2_TRCPRGCTLR |
626 HDFGWTR_EL2_TRCOSLAR |
627 HDFGWTR_EL2_TRCIMSPECn |
628 HDFGWTR_EL2_TRCCNTVRn |
629 HDFGWTR_EL2_TRCCLAIM |
630 HDFGWTR_EL2_TRCAUXCTLR |
631 HDFGWTR_EL2_TRC,
632 FEAT_TRC_SR),
633 NEEDS_FEAT(HDFGWTR_EL2_PMUSERENR_EL0 |
634 HDFGWTR_EL2_PMCR_EL0 |
635 HDFGWTR_EL2_PMSWINC_EL0 |
636 HDFGWTR_EL2_PMSELR_EL0 |
637 HDFGWTR_EL2_PMOVS |
638 HDFGWTR_EL2_PMINTEN |
639 HDFGWTR_EL2_PMCNTEN |
640 HDFGWTR_EL2_PMCCNTR_EL0 |
641 HDFGWTR_EL2_PMCCFILTR_EL0 |
642 HDFGWTR_EL2_PMEVTYPERn_EL0 |
643 HDFGWTR_EL2_PMEVCNTRn_EL0,
644 FEAT_PMUv3),
645 NEEDS_FEAT(HDFGWTR_EL2_TRBTRG_EL1 |
646 HDFGWTR_EL2_TRBSR_EL1 |
647 HDFGWTR_EL2_TRBPTR_EL1 |
648 HDFGWTR_EL2_TRBMAR_EL1 |
649 HDFGWTR_EL2_TRBLIMITR_EL1 |
650 HDFGWTR_EL2_TRBBASER_EL1,
651 FEAT_TRBE),
652 NEEDS_FEAT_FLAG(HDFGWTR_EL2_OSDLR_EL1,
653 NEVER_FGU, FEAT_DoubleLock),
654 NEEDS_FEAT_FLAG(HDFGWTR_EL2_OSECCR_EL1 |
655 HDFGWTR_EL2_OSLAR_EL1 |
656 HDFGWTR_EL2_DBGPRCR_EL1 |
657 HDFGWTR_EL2_DBGCLAIM |
658 HDFGWTR_EL2_MDSCR_EL1 |
659 HDFGWTR_EL2_DBGWVRn_EL1 |
660 HDFGWTR_EL2_DBGWCRn_EL1 |
661 HDFGWTR_EL2_DBGBVRn_EL1 |
662 HDFGWTR_EL2_DBGBCRn_EL1,
663 NEVER_FGU, FEAT_AA64EL1),
664 NEEDS_FEAT(HDFGWTR_EL2_TRFCR_EL1, FEAT_TRF),
665 };
666
667 static const DECLARE_FEAT_MAP_FGT(hdfgwtr_desc, hdfgwtr_masks,
668 hdfgwtr_feat_map, FEAT_FGT);
669
670 static const struct reg_bits_to_feat_map hfgitr_feat_map[] = {
671 NEEDS_FEAT(HFGITR_EL2_PSBCSYNC, FEAT_SPEv1p5),
672 NEEDS_FEAT(HFGITR_EL2_ATS1E1A, FEAT_ATS1A),
673 NEEDS_FEAT(HFGITR_EL2_COSPRCTX, FEAT_SPECRES2),
674 NEEDS_FEAT(HFGITR_EL2_nGCSEPP |
675 HFGITR_EL2_nGCSSTR_EL1 |
676 HFGITR_EL2_nGCSPUSHM_EL1,
677 FEAT_GCS),
678 NEEDS_FEAT(HFGITR_EL2_nBRBIALL |
679 HFGITR_EL2_nBRBINJ,
680 FEAT_BRBE),
681 NEEDS_FEAT(HFGITR_EL2_CPPRCTX |
682 HFGITR_EL2_DVPRCTX |
683 HFGITR_EL2_CFPRCTX,
684 FEAT_SPECRES),
685 NEEDS_FEAT(HFGITR_EL2_TLBIRVAALE1 |
686 HFGITR_EL2_TLBIRVALE1 |
687 HFGITR_EL2_TLBIRVAAE1 |
688 HFGITR_EL2_TLBIRVAE1 |
689 HFGITR_EL2_TLBIRVAALE1IS |
690 HFGITR_EL2_TLBIRVALE1IS |
691 HFGITR_EL2_TLBIRVAAE1IS |
692 HFGITR_EL2_TLBIRVAE1IS |
693 HFGITR_EL2_TLBIRVAALE1OS |
694 HFGITR_EL2_TLBIRVALE1OS |
695 HFGITR_EL2_TLBIRVAAE1OS |
696 HFGITR_EL2_TLBIRVAE1OS,
697 FEAT_TLBIRANGE),
698 NEEDS_FEAT(HFGITR_EL2_TLBIVAALE1OS |
699 HFGITR_EL2_TLBIVALE1OS |
700 HFGITR_EL2_TLBIVAAE1OS |
701 HFGITR_EL2_TLBIASIDE1OS |
702 HFGITR_EL2_TLBIVAE1OS |
703 HFGITR_EL2_TLBIVMALLE1OS,
704 FEAT_TLBIOS),
705 NEEDS_FEAT(HFGITR_EL2_ATS1E1WP |
706 HFGITR_EL2_ATS1E1RP,
707 FEAT_PAN2),
708 NEEDS_FEAT(HFGITR_EL2_DCCVADP, FEAT_DPB2),
709 NEEDS_FEAT_FLAG(HFGITR_EL2_DCCVAC |
710 HFGITR_EL2_SVC_EL1 |
711 HFGITR_EL2_SVC_EL0 |
712 HFGITR_EL2_ERET |
713 HFGITR_EL2_TLBIVAALE1 |
714 HFGITR_EL2_TLBIVALE1 |
715 HFGITR_EL2_TLBIVAAE1 |
716 HFGITR_EL2_TLBIASIDE1 |
717 HFGITR_EL2_TLBIVAE1 |
718 HFGITR_EL2_TLBIVMALLE1 |
719 HFGITR_EL2_TLBIVAALE1IS |
720 HFGITR_EL2_TLBIVALE1IS |
721 HFGITR_EL2_TLBIVAAE1IS |
722 HFGITR_EL2_TLBIASIDE1IS |
723 HFGITR_EL2_TLBIVAE1IS |
724 HFGITR_EL2_TLBIVMALLE1IS|
725 HFGITR_EL2_ATS1E0W |
726 HFGITR_EL2_ATS1E0R |
727 HFGITR_EL2_ATS1E1W |
728 HFGITR_EL2_ATS1E1R |
729 HFGITR_EL2_DCZVA |
730 HFGITR_EL2_DCCIVAC |
731 HFGITR_EL2_DCCVAP |
732 HFGITR_EL2_DCCVAU |
733 HFGITR_EL2_DCCISW |
734 HFGITR_EL2_DCCSW |
735 HFGITR_EL2_DCISW |
736 HFGITR_EL2_DCIVAC |
737 HFGITR_EL2_ICIVAU |
738 HFGITR_EL2_ICIALLU |
739 HFGITR_EL2_ICIALLUIS,
740 NEVER_FGU, FEAT_AA64EL1),
741 };
742
743 static const DECLARE_FEAT_MAP_FGT(hfgitr_desc, hfgitr_masks,
744 hfgitr_feat_map, FEAT_FGT);
745
746 static const struct reg_bits_to_feat_map hafgrtr_feat_map[] = {
747 NEEDS_FEAT(HAFGRTR_EL2_AMEVTYPER115_EL0 |
748 HAFGRTR_EL2_AMEVTYPER114_EL0 |
749 HAFGRTR_EL2_AMEVTYPER113_EL0 |
750 HAFGRTR_EL2_AMEVTYPER112_EL0 |
751 HAFGRTR_EL2_AMEVTYPER111_EL0 |
752 HAFGRTR_EL2_AMEVTYPER110_EL0 |
753 HAFGRTR_EL2_AMEVTYPER19_EL0 |
754 HAFGRTR_EL2_AMEVTYPER18_EL0 |
755 HAFGRTR_EL2_AMEVTYPER17_EL0 |
756 HAFGRTR_EL2_AMEVTYPER16_EL0 |
757 HAFGRTR_EL2_AMEVTYPER15_EL0 |
758 HAFGRTR_EL2_AMEVTYPER14_EL0 |
759 HAFGRTR_EL2_AMEVTYPER13_EL0 |
760 HAFGRTR_EL2_AMEVTYPER12_EL0 |
761 HAFGRTR_EL2_AMEVTYPER11_EL0 |
762 HAFGRTR_EL2_AMEVTYPER10_EL0 |
763 HAFGRTR_EL2_AMEVCNTR115_EL0 |
764 HAFGRTR_EL2_AMEVCNTR114_EL0 |
765 HAFGRTR_EL2_AMEVCNTR113_EL0 |
766 HAFGRTR_EL2_AMEVCNTR112_EL0 |
767 HAFGRTR_EL2_AMEVCNTR111_EL0 |
768 HAFGRTR_EL2_AMEVCNTR110_EL0 |
769 HAFGRTR_EL2_AMEVCNTR19_EL0 |
770 HAFGRTR_EL2_AMEVCNTR18_EL0 |
771 HAFGRTR_EL2_AMEVCNTR17_EL0 |
772 HAFGRTR_EL2_AMEVCNTR16_EL0 |
773 HAFGRTR_EL2_AMEVCNTR15_EL0 |
774 HAFGRTR_EL2_AMEVCNTR14_EL0 |
775 HAFGRTR_EL2_AMEVCNTR13_EL0 |
776 HAFGRTR_EL2_AMEVCNTR12_EL0 |
777 HAFGRTR_EL2_AMEVCNTR11_EL0 |
778 HAFGRTR_EL2_AMEVCNTR10_EL0 |
779 HAFGRTR_EL2_AMCNTEN1 |
780 HAFGRTR_EL2_AMCNTEN0 |
781 HAFGRTR_EL2_AMEVCNTR03_EL0 |
782 HAFGRTR_EL2_AMEVCNTR02_EL0 |
783 HAFGRTR_EL2_AMEVCNTR01_EL0 |
784 HAFGRTR_EL2_AMEVCNTR00_EL0,
785 FEAT_AMUv1),
786 };
787
788 static const DECLARE_FEAT_MAP_FGT(hafgrtr_desc, hafgrtr_masks,
789 hafgrtr_feat_map, FEAT_FGT);
790
791 static const struct reg_bits_to_feat_map hfgitr2_feat_map[] = {
792 NEEDS_FEAT(HFGITR2_EL2_nDCCIVAPS, FEAT_PoPS),
793 NEEDS_FEAT(HFGITR2_EL2_TSBCSYNC, FEAT_TRBEv1p1)
794 };
795
796 static const DECLARE_FEAT_MAP_FGT(hfgitr2_desc, hfgitr2_masks,
797 hfgitr2_feat_map, FEAT_FGT2);
798
799 static const struct reg_bits_to_feat_map hfgrtr2_feat_map[] = {
800 NEEDS_FEAT(HFGRTR2_EL2_nPFAR_EL1, FEAT_PFAR),
801 NEEDS_FEAT(HFGRTR2_EL2_nERXGSR_EL1, FEAT_RASv2),
802 NEEDS_FEAT(HFGRTR2_EL2_nACTLRALIAS_EL1 |
803 HFGRTR2_EL2_nACTLRMASK_EL1 |
804 HFGRTR2_EL2_nCPACRALIAS_EL1 |
805 HFGRTR2_EL2_nCPACRMASK_EL1 |
806 HFGRTR2_EL2_nSCTLR2MASK_EL1 |
807 HFGRTR2_EL2_nSCTLR2ALIAS_EL1 |
808 HFGRTR2_EL2_nSCTLRALIAS_EL1 |
809 HFGRTR2_EL2_nSCTLRMASK_EL1 |
810 HFGRTR2_EL2_nTCR2ALIAS_EL1 |
811 HFGRTR2_EL2_nTCR2MASK_EL1 |
812 HFGRTR2_EL2_nTCRALIAS_EL1 |
813 HFGRTR2_EL2_nTCRMASK_EL1,
814 FEAT_SRMASK),
815 NEEDS_FEAT(HFGRTR2_EL2_nRCWSMASK_EL1, FEAT_THE),
816 };
817
818 static const DECLARE_FEAT_MAP_FGT(hfgrtr2_desc, hfgrtr2_masks,
819 hfgrtr2_feat_map, FEAT_FGT2);
820
821 static const struct reg_bits_to_feat_map hfgwtr2_feat_map[] = {
822 NEEDS_FEAT(HFGWTR2_EL2_nPFAR_EL1, FEAT_PFAR),
823 NEEDS_FEAT(HFGWTR2_EL2_nACTLRALIAS_EL1 |
824 HFGWTR2_EL2_nACTLRMASK_EL1 |
825 HFGWTR2_EL2_nCPACRALIAS_EL1 |
826 HFGWTR2_EL2_nCPACRMASK_EL1 |
827 HFGWTR2_EL2_nSCTLR2MASK_EL1 |
828 HFGWTR2_EL2_nSCTLR2ALIAS_EL1 |
829 HFGWTR2_EL2_nSCTLRALIAS_EL1 |
830 HFGWTR2_EL2_nSCTLRMASK_EL1 |
831 HFGWTR2_EL2_nTCR2ALIAS_EL1 |
832 HFGWTR2_EL2_nTCR2MASK_EL1 |
833 HFGWTR2_EL2_nTCRALIAS_EL1 |
834 HFGWTR2_EL2_nTCRMASK_EL1,
835 FEAT_SRMASK),
836 NEEDS_FEAT(HFGWTR2_EL2_nRCWSMASK_EL1, FEAT_THE),
837 };
838
839 static const DECLARE_FEAT_MAP_FGT(hfgwtr2_desc, hfgwtr2_masks,
840 hfgwtr2_feat_map, FEAT_FGT2);
841
842 static const struct reg_bits_to_feat_map hdfgrtr2_feat_map[] = {
843 NEEDS_FEAT(HDFGRTR2_EL2_nMDSELR_EL1, FEAT_Debugv8p9),
844 NEEDS_FEAT(HDFGRTR2_EL2_nPMECR_EL1, feat_ebep_pmuv3_ss),
845 NEEDS_FEAT(HDFGRTR2_EL2_nTRCITECR_EL1, FEAT_ITE),
846 NEEDS_FEAT(HDFGRTR2_EL2_nPMICFILTR_EL0 |
847 HDFGRTR2_EL2_nPMICNTR_EL0,
848 FEAT_PMUv3_ICNTR),
849 NEEDS_FEAT(HDFGRTR2_EL2_nPMUACR_EL1, feat_pmuv3p9),
850 NEEDS_FEAT(HDFGRTR2_EL2_nPMSSCR_EL1 |
851 HDFGRTR2_EL2_nPMSSDATA,
852 FEAT_PMUv3_SS),
853 NEEDS_FEAT(HDFGRTR2_EL2_nPMIAR_EL1, FEAT_SEBEP),
854 NEEDS_FEAT(HDFGRTR2_EL2_nPMSDSFR_EL1, feat_spe_fds),
855 NEEDS_FEAT(HDFGRTR2_EL2_nPMBMAR_EL1, FEAT_SPE_nVM),
856 NEEDS_FEAT(HDFGRTR2_EL2_nSPMACCESSR_EL1 |
857 HDFGRTR2_EL2_nSPMCNTEN |
858 HDFGRTR2_EL2_nSPMCR_EL0 |
859 HDFGRTR2_EL2_nSPMDEVAFF_EL1 |
860 HDFGRTR2_EL2_nSPMEVCNTRn_EL0 |
861 HDFGRTR2_EL2_nSPMEVTYPERn_EL0|
862 HDFGRTR2_EL2_nSPMID |
863 HDFGRTR2_EL2_nSPMINTEN |
864 HDFGRTR2_EL2_nSPMOVS |
865 HDFGRTR2_EL2_nSPMSCR_EL1 |
866 HDFGRTR2_EL2_nSPMSELR_EL0,
867 FEAT_SPMU),
868 NEEDS_FEAT(HDFGRTR2_EL2_nMDSTEPOP_EL1, FEAT_STEP2),
869 NEEDS_FEAT(HDFGRTR2_EL2_nTRBMPAM_EL1, feat_trbe_mpam),
870 };
871
872 static const DECLARE_FEAT_MAP_FGT(hdfgrtr2_desc, hdfgrtr2_masks,
873 hdfgrtr2_feat_map, FEAT_FGT2);
874
875 static const struct reg_bits_to_feat_map hdfgwtr2_feat_map[] = {
876 NEEDS_FEAT(HDFGWTR2_EL2_nMDSELR_EL1, FEAT_Debugv8p9),
877 NEEDS_FEAT(HDFGWTR2_EL2_nPMECR_EL1, feat_ebep_pmuv3_ss),
878 NEEDS_FEAT(HDFGWTR2_EL2_nTRCITECR_EL1, FEAT_ITE),
879 NEEDS_FEAT(HDFGWTR2_EL2_nPMICFILTR_EL0 |
880 HDFGWTR2_EL2_nPMICNTR_EL0,
881 FEAT_PMUv3_ICNTR),
882 NEEDS_FEAT(HDFGWTR2_EL2_nPMUACR_EL1 |
883 HDFGWTR2_EL2_nPMZR_EL0,
884 feat_pmuv3p9),
885 NEEDS_FEAT(HDFGWTR2_EL2_nPMSSCR_EL1, FEAT_PMUv3_SS),
886 NEEDS_FEAT(HDFGWTR2_EL2_nPMIAR_EL1, FEAT_SEBEP),
887 NEEDS_FEAT(HDFGWTR2_EL2_nPMSDSFR_EL1, feat_spe_fds),
888 NEEDS_FEAT(HDFGWTR2_EL2_nPMBMAR_EL1, FEAT_SPE_nVM),
889 NEEDS_FEAT(HDFGWTR2_EL2_nSPMACCESSR_EL1 |
890 HDFGWTR2_EL2_nSPMCNTEN |
891 HDFGWTR2_EL2_nSPMCR_EL0 |
892 HDFGWTR2_EL2_nSPMEVCNTRn_EL0 |
893 HDFGWTR2_EL2_nSPMEVTYPERn_EL0|
894 HDFGWTR2_EL2_nSPMINTEN |
895 HDFGWTR2_EL2_nSPMOVS |
896 HDFGWTR2_EL2_nSPMSCR_EL1 |
897 HDFGWTR2_EL2_nSPMSELR_EL0,
898 FEAT_SPMU),
899 NEEDS_FEAT(HDFGWTR2_EL2_nMDSTEPOP_EL1, FEAT_STEP2),
900 NEEDS_FEAT(HDFGWTR2_EL2_nTRBMPAM_EL1, feat_trbe_mpam),
901 };
902
903 static const DECLARE_FEAT_MAP_FGT(hdfgwtr2_desc, hdfgwtr2_masks,
904 hdfgwtr2_feat_map, FEAT_FGT2);
905
906
907 static const struct reg_bits_to_feat_map hcrx_feat_map[] = {
908 NEEDS_FEAT(HCRX_EL2_NVTGE |
909 HCRX_EL2_NVnTTLB |
910 HCRX_EL2_NVnTTLBIS |
911 HCRX_EL2_NVnTTLBOS,
912 FEAT_NV3),
913 NEEDS_FEAT(HCRX_EL2_SRMASKEn, FEAT_SRMASK),
914 NEEDS_FEAT(HCRX_EL2_PACMEn, feat_pauth_lr),
915 NEEDS_FEAT(HCRX_EL2_EnFPM, FEAT_FPMR),
916 NEEDS_FEAT(HCRX_EL2_GCSEn, FEAT_GCS),
917 NEEDS_FEAT(HCRX_EL2_EnIDCP128, FEAT_SYSREG128),
918 NEEDS_FEAT(HCRX_EL2_EnSDERR, feat_aderr),
919 NEEDS_FEAT(HCRX_EL2_TMEA, FEAT_DoubleFault2),
920 NEEDS_FEAT(HCRX_EL2_EnSNERR, feat_anerr),
921 NEEDS_FEAT(HCRX_EL2_D128En, FEAT_D128),
922 NEEDS_FEAT(HCRX_EL2_PTTWI, FEAT_THE),
923 NEEDS_FEAT(HCRX_EL2_SCTLR2En, FEAT_SCTLR2),
924 NEEDS_FEAT(HCRX_EL2_TCR2En, FEAT_TCR2),
925 NEEDS_FEAT(HCRX_EL2_MSCEn |
926 HCRX_EL2_MCE2,
927 FEAT_MOPS),
928 NEEDS_FEAT(HCRX_EL2_CMOW, FEAT_CMOW),
929 NEEDS_FEAT(HCRX_EL2_VFNMI |
930 HCRX_EL2_VINMI |
931 HCRX_EL2_TALLINT,
932 FEAT_NMI),
933 NEEDS_FEAT(HCRX_EL2_SMPME, feat_sme_smps),
934 NEEDS_FEAT(HCRX_EL2_FGTnXS |
935 HCRX_EL2_FnXS,
936 FEAT_XS),
937 NEEDS_FEAT(HCRX_EL2_EnASR, FEAT_LS64_V),
938 NEEDS_FEAT(HCRX_EL2_EnALS, FEAT_LS64),
939 NEEDS_FEAT(HCRX_EL2_EnAS0, FEAT_LS64_ACCDATA),
940 FORCE_RES0(HCRX_EL2_RES0),
941 FORCE_RES1(HCRX_EL2_RES1),
942 };
943
944
945 static const DECLARE_FEAT_MAP(hcrx_desc, HCRX_EL2,
946 hcrx_feat_map, FEAT_HCX);
947
948 static const struct reg_bits_to_feat_map hcr_feat_map[] = {
949 NEEDS_FEAT(HCR_EL2_TID0, FEAT_AA32EL0),
950 NEEDS_FEAT_FLAG(HCR_EL2_RW, AS_RES1, FEAT_AA32EL1),
951 NEEDS_FEAT(HCR_EL2_HCD, not_feat_aa64el3),
952 NEEDS_FEAT(HCR_EL2_AMO |
953 HCR_EL2_BSU |
954 HCR_EL2_CD |
955 HCR_EL2_DC |
956 HCR_EL2_FB |
957 HCR_EL2_FMO |
958 HCR_EL2_ID |
959 HCR_EL2_IMO |
960 HCR_EL2_PTW |
961 HCR_EL2_SWIO |
962 HCR_EL2_TACR |
963 HCR_EL2_TDZ |
964 HCR_EL2_TGE |
965 HCR_EL2_TID1 |
966 HCR_EL2_TID2 |
967 HCR_EL2_TID3 |
968 HCR_EL2_TIDCP |
969 HCR_EL2_TPCP |
970 HCR_EL2_TPU |
971 HCR_EL2_TRVM |
972 HCR_EL2_TSC |
973 HCR_EL2_TSW |
974 HCR_EL2_TTLB |
975 HCR_EL2_TVM |
976 HCR_EL2_TWE |
977 HCR_EL2_TWI |
978 HCR_EL2_VF |
979 HCR_EL2_VI |
980 HCR_EL2_VM |
981 HCR_EL2_VSE,
982 FEAT_AA64EL1),
983 NEEDS_FEAT(HCR_EL2_AMVOFFEN, FEAT_AMUv1p1),
984 NEEDS_FEAT(HCR_EL2_EnSCXT, feat_csv2_2_csv2_1p2),
985 NEEDS_FEAT(HCR_EL2_TICAB |
986 HCR_EL2_TID4 |
987 HCR_EL2_TOCU,
988 FEAT_EVT),
989 NEEDS_FEAT(HCR_EL2_TTLBIS |
990 HCR_EL2_TTLBOS,
991 FEAT_EVT_TTLBxS),
992 NEEDS_FEAT(HCR_EL2_TLOR, FEAT_LOR),
993 NEEDS_FEAT(HCR_EL2_ATA |
994 HCR_EL2_DCT |
995 HCR_EL2_TID5,
996 FEAT_MTE2),
997 NEEDS_FEAT(HCR_EL2_AT | /* Ignore the original FEAT_NV */
998 HCR_EL2_NV2 |
999 HCR_EL2_NV,
1000 feat_nv2),
1001 NEEDS_FEAT(HCR_EL2_NV1, feat_nv2_e2h0_ni), /* Missing from JSON */
1002 NEEDS_FEAT(HCR_EL2_API |
1003 HCR_EL2_APK,
1004 feat_pauth),
1005 NEEDS_FEAT(HCR_EL2_TEA |
1006 HCR_EL2_TERR,
1007 FEAT_RAS),
1008 NEEDS_FEAT(HCR_EL2_FIEN, feat_rasv1p1),
1009 NEEDS_FEAT(HCR_EL2_GPF, FEAT_RME),
1010 NEEDS_FEAT(HCR_EL2_FWB, FEAT_S2FWB),
1011 NEEDS_FEAT(HCR_EL2_TWEDEL |
1012 HCR_EL2_TWEDEn,
1013 FEAT_TWED),
1014 NEEDS_FEAT_FLAG(HCR_EL2_E2H, RES1_WHEN_E2H1 | FORCE_RESx),
1015 FORCE_RES0(HCR_EL2_RES0),
1016 FORCE_RES1(HCR_EL2_RES1),
1017 };
1018
1019 static const DECLARE_FEAT_MAP(hcr_desc, HCR_EL2,
1020 hcr_feat_map, FEAT_AA64EL2);
1021
1022 static const DECLARE_FEAT_MAP(nvhcr_desc, NVHCR_EL2,
1023 hcr_feat_map, FEAT_NV3);
1024
1025 static const struct reg_bits_to_feat_map sctlr2_feat_map[] = {
1026 NEEDS_FEAT(SCTLR2_EL1_NMEA |
1027 SCTLR2_EL1_EASE,
1028 FEAT_DoubleFault2),
1029 NEEDS_FEAT(SCTLR2_EL1_EnADERR, feat_aderr),
1030 NEEDS_FEAT(SCTLR2_EL1_EnANERR, feat_anerr),
1031 NEEDS_FEAT(SCTLR2_EL1_EnIDCP128, FEAT_SYSREG128),
1032 NEEDS_FEAT(SCTLR2_EL1_EnPACM |
1033 SCTLR2_EL1_EnPACM0,
1034 feat_pauth_lr),
1035 NEEDS_FEAT(SCTLR2_EL1_CPTA |
1036 SCTLR2_EL1_CPTA0 |
1037 SCTLR2_EL1_CPTM |
1038 SCTLR2_EL1_CPTM0,
1039 FEAT_CPA2),
1040 FORCE_RES0(SCTLR2_EL1_RES0),
1041 FORCE_RES1(SCTLR2_EL1_RES1),
1042 };
1043
1044 static const DECLARE_FEAT_MAP(sctlr2_desc, SCTLR2_EL1,
1045 sctlr2_feat_map, FEAT_SCTLR2);
1046
1047 static const struct reg_bits_to_feat_map tcr2_el2_feat_map[] = {
1048 NEEDS_FEAT_FLAG(TCR2_EL2_FNG1 |
1049 TCR2_EL2_FNG0 |
1050 TCR2_EL2_A2,
1051 REQUIRES_E2H1, FEAT_ASID2),
1052 NEEDS_FEAT_FLAG(TCR2_EL2_DisCH1 |
1053 TCR2_EL2_DisCH0 |
1054 TCR2_EL2_D128,
1055 REQUIRES_E2H1, FEAT_D128),
1056 NEEDS_FEAT_FLAG(TCR2_EL2_AMEC1, REQUIRES_E2H1, FEAT_MEC),
1057 NEEDS_FEAT(TCR2_EL2_AMEC0, FEAT_MEC),
1058 NEEDS_FEAT(TCR2_EL2_HAFT, FEAT_HAFT),
1059 NEEDS_FEAT(TCR2_EL2_PTTWI |
1060 TCR2_EL2_PnCH,
1061 FEAT_THE),
1062 NEEDS_FEAT(TCR2_EL2_AIE, FEAT_AIE),
1063 NEEDS_FEAT(TCR2_EL2_POE |
1064 TCR2_EL2_E0POE,
1065 FEAT_S1POE),
1066 NEEDS_FEAT(TCR2_EL2_PIE, FEAT_S1PIE),
1067 FORCE_RES0(TCR2_EL2_RES0),
1068 FORCE_RES1(TCR2_EL2_RES1),
1069 };
1070
1071 static const DECLARE_FEAT_MAP(tcr2_el2_desc, TCR2_EL2,
1072 tcr2_el2_feat_map, FEAT_TCR2);
1073
1074 static const struct reg_bits_to_feat_map sctlr_el1_feat_map[] = {
1075 NEEDS_FEAT(SCTLR_EL1_CP15BEN, FEAT_AA32EL0),
1076 NEEDS_FEAT_FLAG(SCTLR_EL1_ITD |
1077 SCTLR_EL1_SED,
1078 AS_RES1, FEAT_AA32EL0),
1079 NEEDS_FEAT(SCTLR_EL1_BT0 |
1080 SCTLR_EL1_BT1,
1081 FEAT_BTI),
1082 NEEDS_FEAT(SCTLR_EL1_CMOW, FEAT_CMOW),
1083 NEEDS_FEAT_FLAG(SCTLR_EL1_TSCXT,
1084 AS_RES1, feat_csv2_2_csv2_1p2),
1085 NEEDS_FEAT_FLAG(SCTLR_EL1_EIS |
1086 SCTLR_EL1_EOS,
1087 AS_RES1, FEAT_ExS),
1088 NEEDS_FEAT(SCTLR_EL1_EnFPM, FEAT_FPMR),
1089 NEEDS_FEAT(SCTLR_EL1_IESB, FEAT_IESB),
1090 NEEDS_FEAT(SCTLR_EL1_EnALS, FEAT_LS64),
1091 NEEDS_FEAT(SCTLR_EL1_EnAS0, FEAT_LS64_ACCDATA),
1092 NEEDS_FEAT(SCTLR_EL1_EnASR, FEAT_LS64_V),
1093 NEEDS_FEAT(SCTLR_EL1_nAA, FEAT_LSE2),
1094 NEEDS_FEAT_FLAG(SCTLR_EL1_LSMAOE |
1095 SCTLR_EL1_nTLSMD,
1096 AS_RES1, FEAT_LSMAOC),
1097 NEEDS_FEAT(SCTLR_EL1_EE, FEAT_MixedEnd),
1098 NEEDS_FEAT(SCTLR_EL1_E0E, feat_mixedendel0),
1099 NEEDS_FEAT(SCTLR_EL1_MSCEn, FEAT_MOPS),
1100 NEEDS_FEAT(SCTLR_EL1_ATA0 |
1101 SCTLR_EL1_ATA |
1102 SCTLR_EL1_TCF0 |
1103 SCTLR_EL1_TCF,
1104 FEAT_MTE2),
1105 NEEDS_FEAT(SCTLR_EL1_ITFSB, feat_mte_async),
1106 NEEDS_FEAT(SCTLR_EL1_TCSO0 |
1107 SCTLR_EL1_TCSO,
1108 FEAT_MTE_STORE_ONLY),
1109 NEEDS_FEAT(SCTLR_EL1_NMI |
1110 SCTLR_EL1_SPINTMASK,
1111 FEAT_NMI),
1112 NEEDS_FEAT_FLAG(SCTLR_EL1_SPAN,
1113 AS_RES1, FEAT_PAN),
1114 NEEDS_FEAT(SCTLR_EL1_EPAN, FEAT_PAN3),
1115 NEEDS_FEAT(SCTLR_EL1_EnDA |
1116 SCTLR_EL1_EnDB |
1117 SCTLR_EL1_EnIA |
1118 SCTLR_EL1_EnIB,
1119 feat_pauth),
1120 NEEDS_FEAT(SCTLR_EL1_EnTP2, FEAT_SME),
1121 NEEDS_FEAT(SCTLR_EL1_EnRCTX, FEAT_SPECRES),
1122 NEEDS_FEAT(SCTLR_EL1_DSSBS, FEAT_SSBS),
1123 NEEDS_FEAT(SCTLR_EL1_TIDCP, FEAT_TIDCP1),
1124 NEEDS_FEAT(SCTLR_EL1_TWEDEL |
1125 SCTLR_EL1_TWEDEn,
1126 FEAT_TWED),
1127 NEEDS_FEAT(SCTLR_EL1_UCI |
1128 SCTLR_EL1_WXN |
1129 SCTLR_EL1_nTWE |
1130 SCTLR_EL1_nTWI |
1131 SCTLR_EL1_UCT |
1132 SCTLR_EL1_DZE |
1133 SCTLR_EL1_I |
1134 SCTLR_EL1_UMA |
1135 SCTLR_EL1_SA0 |
1136 SCTLR_EL1_SA |
1137 SCTLR_EL1_C |
1138 SCTLR_EL1_A |
1139 SCTLR_EL1_M,
1140 FEAT_AA64EL1),
1141 FORCE_RES0(SCTLR_EL1_RES0),
1142 FORCE_RES1(SCTLR_EL1_RES1),
1143 };
1144
1145 static const DECLARE_FEAT_MAP(sctlr_el1_desc, SCTLR_EL1,
1146 sctlr_el1_feat_map, FEAT_AA64EL1);
1147
1148 static const struct reg_bits_to_feat_map sctlr_el2_feat_map[] = {
1149 NEEDS_FEAT_FLAG(SCTLR_EL2_CP15BEN,
1150 RES1_WHEN_E2H0 | REQUIRES_E2H1,
1151 FEAT_AA32EL0),
1152 NEEDS_FEAT_FLAG(SCTLR_EL2_ITD |
1153 SCTLR_EL2_SED,
1154 RES1_WHEN_E2H1 | REQUIRES_E2H1,
1155 FEAT_AA32EL0),
1156 NEEDS_FEAT_FLAG(SCTLR_EL2_BT0, REQUIRES_E2H1, FEAT_BTI),
1157 NEEDS_FEAT(SCTLR_EL2_BT, FEAT_BTI),
1158 NEEDS_FEAT_FLAG(SCTLR_EL2_CMOW, REQUIRES_E2H1, FEAT_CMOW),
1159 NEEDS_FEAT_FLAG(SCTLR_EL2_TSCXT,
1160 RES1_WHEN_E2H1 | REQUIRES_E2H1,
1161 feat_csv2_2_csv2_1p2),
1162 NEEDS_FEAT_FLAG(SCTLR_EL2_EIS |
1163 SCTLR_EL2_EOS,
1164 AS_RES1, FEAT_ExS),
1165 NEEDS_FEAT(SCTLR_EL2_EnFPM, FEAT_FPMR),
1166 NEEDS_FEAT(SCTLR_EL2_IESB, FEAT_IESB),
1167 NEEDS_FEAT_FLAG(SCTLR_EL2_EnALS, REQUIRES_E2H1, FEAT_LS64),
1168 NEEDS_FEAT_FLAG(SCTLR_EL2_EnAS0, REQUIRES_E2H1, FEAT_LS64_ACCDATA),
1169 NEEDS_FEAT_FLAG(SCTLR_EL2_EnASR, REQUIRES_E2H1, FEAT_LS64_V),
1170 NEEDS_FEAT(SCTLR_EL2_nAA, FEAT_LSE2),
1171 NEEDS_FEAT_FLAG(SCTLR_EL2_LSMAOE |
1172 SCTLR_EL2_nTLSMD,
1173 AS_RES1 | REQUIRES_E2H1, FEAT_LSMAOC),
1174 NEEDS_FEAT(SCTLR_EL2_EE, FEAT_MixedEnd),
1175 NEEDS_FEAT_FLAG(SCTLR_EL2_E0E, REQUIRES_E2H1, feat_mixedendel0),
1176 NEEDS_FEAT_FLAG(SCTLR_EL2_MSCEn, REQUIRES_E2H1, FEAT_MOPS),
1177 NEEDS_FEAT_FLAG(SCTLR_EL2_ATA0 |
1178 SCTLR_EL2_TCF0,
1179 REQUIRES_E2H1, FEAT_MTE2),
1180 NEEDS_FEAT(SCTLR_EL2_ATA |
1181 SCTLR_EL2_TCF,
1182 FEAT_MTE2),
1183 NEEDS_FEAT(SCTLR_EL2_ITFSB, feat_mte_async),
1184 NEEDS_FEAT_FLAG(SCTLR_EL2_TCSO0, REQUIRES_E2H1, FEAT_MTE_STORE_ONLY),
1185 NEEDS_FEAT(SCTLR_EL2_TCSO,
1186 FEAT_MTE_STORE_ONLY),
1187 NEEDS_FEAT(SCTLR_EL2_NMI |
1188 SCTLR_EL2_SPINTMASK,
1189 FEAT_NMI),
1190 NEEDS_FEAT_FLAG(SCTLR_EL2_SPAN, AS_RES1 | REQUIRES_E2H1, FEAT_PAN),
1191 NEEDS_FEAT_FLAG(SCTLR_EL2_EPAN, REQUIRES_E2H1, FEAT_PAN3),
1192 NEEDS_FEAT(SCTLR_EL2_EnDA |
1193 SCTLR_EL2_EnDB |
1194 SCTLR_EL2_EnIA |
1195 SCTLR_EL2_EnIB,
1196 feat_pauth),
1197 NEEDS_FEAT_FLAG(SCTLR_EL2_EnTP2, REQUIRES_E2H1, FEAT_SME),
1198 NEEDS_FEAT(SCTLR_EL2_EnRCTX, FEAT_SPECRES),
1199 NEEDS_FEAT(SCTLR_EL2_DSSBS, FEAT_SSBS),
1200 NEEDS_FEAT_FLAG(SCTLR_EL2_TIDCP, REQUIRES_E2H1, FEAT_TIDCP1),
1201 NEEDS_FEAT_FLAG(SCTLR_EL2_TWEDEL |
1202 SCTLR_EL2_TWEDEn,
1203 REQUIRES_E2H1, FEAT_TWED),
1204 NEEDS_FEAT_FLAG(SCTLR_EL2_nTWE |
1205 SCTLR_EL2_nTWI,
1206 AS_RES1 | REQUIRES_E2H1, FEAT_AA64EL2),
1207 NEEDS_FEAT_FLAG(SCTLR_EL2_UCI |
1208 SCTLR_EL2_UCT |
1209 SCTLR_EL2_DZE |
1210 SCTLR_EL2_SA0,
1211 REQUIRES_E2H1, FEAT_AA64EL2),
1212 NEEDS_FEAT(SCTLR_EL2_WXN |
1213 SCTLR_EL2_I |
1214 SCTLR_EL2_SA |
1215 SCTLR_EL2_C |
1216 SCTLR_EL2_A |
1217 SCTLR_EL2_M,
1218 FEAT_AA64EL2),
1219 FORCE_RES0(SCTLR_EL2_RES0),
1220 FORCE_RES1(SCTLR_EL2_RES1),
1221 };
1222
1223 static const DECLARE_FEAT_MAP(sctlr_el2_desc, SCTLR_EL2,
1224 sctlr_el2_feat_map, FEAT_AA64EL2);
1225
1226 static const struct reg_bits_to_feat_map mdcr_el2_feat_map[] = {
1227 NEEDS_FEAT(MDCR_EL2_EBWE, FEAT_Debugv8p9),
1228 NEEDS_FEAT(MDCR_EL2_TDOSA, FEAT_DoubleLock),
1229 NEEDS_FEAT(MDCR_EL2_PMEE, FEAT_EBEP),
1230 NEEDS_FEAT(MDCR_EL2_TDCC, FEAT_FGT),
1231 NEEDS_FEAT(MDCR_EL2_MTPME, FEAT_MTPMU),
1232 NEEDS_FEAT(MDCR_EL2_HPME |
1233 MDCR_EL2_HPMN |
1234 MDCR_EL2_TPMCR |
1235 MDCR_EL2_TPM,
1236 FEAT_PMUv3),
1237 NEEDS_FEAT(MDCR_EL2_HPMD, feat_pmuv3p1),
1238 NEEDS_FEAT(MDCR_EL2_HCCD |
1239 MDCR_EL2_HLP,
1240 feat_pmuv3p5),
1241 NEEDS_FEAT(MDCR_EL2_HPMFZO, feat_pmuv3p7),
1242 NEEDS_FEAT(MDCR_EL2_PMSSE, FEAT_PMUv3_SS),
1243 NEEDS_FEAT(MDCR_EL2_E2PB |
1244 MDCR_EL2_TPMS,
1245 FEAT_SPE),
1246 NEEDS_FEAT(MDCR_EL2_HPMFZS, FEAT_SPEv1p2),
1247 NEEDS_FEAT(MDCR_EL2_EnSPM, FEAT_SPMU),
1248 NEEDS_FEAT(MDCR_EL2_EnSTEPOP, FEAT_STEP2),
1249 NEEDS_FEAT(MDCR_EL2_E2TB, FEAT_TRBE),
1250 NEEDS_FEAT(MDCR_EL2_TTRF, FEAT_TRF),
1251 NEEDS_FEAT(MDCR_EL2_TDA |
1252 MDCR_EL2_TDE |
1253 MDCR_EL2_TDRA,
1254 FEAT_AA64EL1),
1255 FORCE_RES0(MDCR_EL2_RES0),
1256 FORCE_RES1(MDCR_EL2_RES1),
1257 };
1258
1259 static const DECLARE_FEAT_MAP(mdcr_el2_desc, MDCR_EL2,
1260 mdcr_el2_feat_map, FEAT_AA64EL2);
1261
1262 static const struct reg_bits_to_feat_map vtcr_el2_feat_map[] = {
1263 NEEDS_FEAT(VTCR_EL2_HDBSS, FEAT_HDBSS),
1264 NEEDS_FEAT(VTCR_EL2_HAFT, FEAT_HAFT),
1265 NEEDS_FEAT(VTCR_EL2_TL0 |
1266 VTCR_EL2_TL1 |
1267 VTCR_EL2_AssuredOnly |
1268 VTCR_EL2_GCSH,
1269 FEAT_THE),
1270 NEEDS_FEAT(VTCR_EL2_D128, FEAT_D128),
1271 NEEDS_FEAT(VTCR_EL2_S2POE, FEAT_S2POE),
1272 NEEDS_FEAT(VTCR_EL2_S2PIE, FEAT_S2PIE),
1273 NEEDS_FEAT(VTCR_EL2_SL2 |
1274 VTCR_EL2_DS,
1275 feat_lpa2),
1276 NEEDS_FEAT(VTCR_EL2_NSA |
1277 VTCR_EL2_NSW,
1278 FEAT_SEL2),
1279 NEEDS_FEAT(VTCR_EL2_HWU62 |
1280 VTCR_EL2_HWU61 |
1281 VTCR_EL2_HWU60 |
1282 VTCR_EL2_HWU59,
1283 FEAT_HPDS2),
1284 NEEDS_FEAT(VTCR_EL2_HD, ID_AA64MMFR1_EL1, HAFDBS, DBM),
1285 NEEDS_FEAT(VTCR_EL2_HA, ID_AA64MMFR1_EL1, HAFDBS, AF),
1286 NEEDS_FEAT(VTCR_EL2_VS, feat_vmid16),
1287 NEEDS_FEAT(VTCR_EL2_PS |
1288 VTCR_EL2_TG0 |
1289 VTCR_EL2_SH0 |
1290 VTCR_EL2_ORGN0 |
1291 VTCR_EL2_IRGN0 |
1292 VTCR_EL2_SL0 |
1293 VTCR_EL2_T0SZ,
1294 FEAT_AA64EL1),
1295 FORCE_RES0(VTCR_EL2_RES0),
1296 FORCE_RES1(VTCR_EL2_RES1),
1297 };
1298
1299 static const DECLARE_FEAT_MAP(vtcr_el2_desc, VTCR_EL2,
1300 vtcr_el2_feat_map, FEAT_AA64EL2);
1301
1302 static const struct reg_bits_to_feat_map ich_hfgrtr_feat_map[] = {
1303 NEEDS_FEAT(ICH_HFGRTR_EL2_ICC_APR_EL1 |
1304 ICH_HFGRTR_EL2_ICC_IDRn_EL1 |
1305 ICH_HFGRTR_EL2_ICC_CR0_EL1 |
1306 ICH_HFGRTR_EL2_ICC_HPPIR_EL1 |
1307 ICH_HFGRTR_EL2_ICC_PCR_EL1 |
1308 ICH_HFGRTR_EL2_ICC_ICSR_EL1 |
1309 ICH_HFGRTR_EL2_ICC_IAFFIDR_EL1 |
1310 ICH_HFGRTR_EL2_ICC_PPI_HMRn_EL1 |
1311 ICH_HFGRTR_EL2_ICC_PPI_ENABLERn_EL1 |
1312 ICH_HFGRTR_EL2_ICC_PPI_PENDRn_EL1 |
1313 ICH_HFGRTR_EL2_ICC_PPI_PRIORITYRn_EL1 |
1314 ICH_HFGRTR_EL2_ICC_PPI_ACTIVERn_EL1,
1315 FEAT_GCIE),
1316 };
1317
1318 static const DECLARE_FEAT_MAP_FGT(ich_hfgrtr_desc, ich_hfgrtr_masks,
1319 ich_hfgrtr_feat_map, FEAT_GCIE);
1320
1321 static const struct reg_bits_to_feat_map ich_hfgwtr_feat_map[] = {
1322 NEEDS_FEAT(ICH_HFGWTR_EL2_ICC_APR_EL1 |
1323 ICH_HFGWTR_EL2_ICC_CR0_EL1 |
1324 ICH_HFGWTR_EL2_ICC_PCR_EL1 |
1325 ICH_HFGWTR_EL2_ICC_ICSR_EL1 |
1326 ICH_HFGWTR_EL2_ICC_PPI_ENABLERn_EL1 |
1327 ICH_HFGWTR_EL2_ICC_PPI_PENDRn_EL1 |
1328 ICH_HFGWTR_EL2_ICC_PPI_PRIORITYRn_EL1 |
1329 ICH_HFGWTR_EL2_ICC_PPI_ACTIVERn_EL1,
1330 FEAT_GCIE),
1331 };
1332
1333 static const DECLARE_FEAT_MAP_FGT(ich_hfgwtr_desc, ich_hfgwtr_masks,
1334 ich_hfgwtr_feat_map, FEAT_GCIE);
1335
1336 static const struct reg_bits_to_feat_map ich_hfgitr_feat_map[] = {
1337 NEEDS_FEAT(ICH_HFGITR_EL2_GICCDEN |
1338 ICH_HFGITR_EL2_GICCDDIS |
1339 ICH_HFGITR_EL2_GICCDPRI |
1340 ICH_HFGITR_EL2_GICCDAFF |
1341 ICH_HFGITR_EL2_GICCDPEND |
1342 ICH_HFGITR_EL2_GICCDRCFG |
1343 ICH_HFGITR_EL2_GICCDHM |
1344 ICH_HFGITR_EL2_GICCDEOI |
1345 ICH_HFGITR_EL2_GICCDDI |
1346 ICH_HFGITR_EL2_GICRCDIA |
1347 ICH_HFGITR_EL2_GICRCDNMIA,
1348 FEAT_GCIE),
1349 };
1350
1351 static const DECLARE_FEAT_MAP_FGT(ich_hfgitr_desc, ich_hfgitr_masks,
1352 ich_hfgitr_feat_map, FEAT_GCIE);
1353
check_feat_map(const struct reg_bits_to_feat_map * map,int map_size,u64 resx,const char * str)1354 static void __init check_feat_map(const struct reg_bits_to_feat_map *map,
1355 int map_size, u64 resx, const char *str)
1356 {
1357 u64 mask = 0;
1358
1359 /*
1360 * Don't account for FORCE_RESx that are architectural, and
1361 * therefore part of the resx parameter. Other FORCE_RESx bits
1362 * are implementation choices, and therefore accounted for.
1363 */
1364 for (int i = 0; i < map_size; i++)
1365 if (!((map[i].flags & FORCE_RESx) && (map[i].bits & resx)))
1366 mask |= map[i].bits;
1367
1368 if (mask != ~resx)
1369 kvm_err("Undefined %s behaviour, bits %016llx\n",
1370 str, mask ^ ~resx);
1371 }
1372
reg_feat_map_bits(const struct reg_bits_to_feat_map * map)1373 static u64 reg_feat_map_bits(const struct reg_bits_to_feat_map *map)
1374 {
1375 return map->flags & MASKS_POINTER ? (map->masks->mask | map->masks->nmask) : map->bits;
1376 }
1377
check_reg_desc(const struct reg_feat_map_desc * r)1378 static void __init check_reg_desc(const struct reg_feat_map_desc *r)
1379 {
1380 check_feat_map(r->bit_feat_map, r->bit_feat_map_sz,
1381 ~reg_feat_map_bits(&r->feat_map), r->name);
1382 }
1383
check_feature_map(void)1384 void __init check_feature_map(void)
1385 {
1386 check_reg_desc(&hfgrtr_desc);
1387 check_reg_desc(&hfgwtr_desc);
1388 check_reg_desc(&hfgitr_desc);
1389 check_reg_desc(&hdfgrtr_desc);
1390 check_reg_desc(&hdfgwtr_desc);
1391 check_reg_desc(&hafgrtr_desc);
1392 check_reg_desc(&hfgrtr2_desc);
1393 check_reg_desc(&hfgwtr2_desc);
1394 check_reg_desc(&hfgitr2_desc);
1395 check_reg_desc(&hdfgrtr2_desc);
1396 check_reg_desc(&hdfgwtr2_desc);
1397 check_reg_desc(&hcrx_desc);
1398 check_reg_desc(&hcr_desc);
1399 check_reg_desc(&nvhcr_desc);
1400 check_reg_desc(&sctlr2_desc);
1401 check_reg_desc(&tcr2_el2_desc);
1402 check_reg_desc(&sctlr_el1_desc);
1403 check_reg_desc(&sctlr_el2_desc);
1404 check_reg_desc(&mdcr_el2_desc);
1405 check_reg_desc(&vtcr_el2_desc);
1406 check_reg_desc(&ich_hfgrtr_desc);
1407 check_reg_desc(&ich_hfgwtr_desc);
1408 check_reg_desc(&ich_hfgitr_desc);
1409 }
1410
idreg_feat_match(struct kvm * kvm,const struct reg_bits_to_feat_map * map)1411 static bool idreg_feat_match(struct kvm *kvm, const struct reg_bits_to_feat_map *map)
1412 {
1413 u64 regval = kvm->arch.id_regs[map->regidx];
1414 u64 regfld = (regval >> map->shift) & GENMASK(map->width - 1, 0);
1415
1416 if (map->sign) {
1417 s64 sfld = sign_extend64(regfld, map->width - 1);
1418 s64 slim = sign_extend64(map->lo_lim, map->width - 1);
1419 return sfld >= slim;
1420 } else {
1421 return regfld >= map->lo_lim;
1422 }
1423 }
1424
compute_resx_bits(struct kvm * kvm,const struct reg_bits_to_feat_map * map,int map_size,unsigned long require,unsigned long exclude)1425 static struct resx compute_resx_bits(struct kvm *kvm,
1426 const struct reg_bits_to_feat_map *map,
1427 int map_size,
1428 unsigned long require,
1429 unsigned long exclude)
1430 {
1431 bool e2h0 = kvm_has_feat(kvm, FEAT_E2H0);
1432 struct resx resx = {};
1433
1434 for (int i = 0; i < map_size; i++) {
1435 bool match;
1436
1437 if ((map[i].flags & require) != require)
1438 continue;
1439
1440 if (map[i].flags & exclude)
1441 continue;
1442
1443 if (map[i].flags & FORCE_RESx)
1444 match = false;
1445 else if (map[i].flags & CALL_FUNC)
1446 match = map[i].match(kvm);
1447 else
1448 match = idreg_feat_match(kvm, &map[i]);
1449
1450 if (map[i].flags & REQUIRES_E2H1)
1451 match &= !e2h0;
1452
1453 if (!match) {
1454 u64 bits = reg_feat_map_bits(&map[i]);
1455
1456 if ((map[i].flags & AS_RES1) ||
1457 (e2h0 && (map[i].flags & RES1_WHEN_E2H0)) ||
1458 (!e2h0 && (map[i].flags & RES1_WHEN_E2H1)))
1459 resx.res1 |= bits;
1460 else
1461 resx.res0 |= bits;
1462 }
1463 }
1464
1465 return resx;
1466 }
1467
compute_reg_resx_bits(struct kvm * kvm,const struct reg_feat_map_desc * r,unsigned long require,unsigned long exclude)1468 static struct resx compute_reg_resx_bits(struct kvm *kvm,
1469 const struct reg_feat_map_desc *r,
1470 unsigned long require,
1471 unsigned long exclude)
1472 {
1473 struct resx resx;
1474
1475 resx = compute_resx_bits(kvm, r->bit_feat_map, r->bit_feat_map_sz,
1476 require, exclude);
1477
1478 if (r->feat_map.flags & MASKS_POINTER) {
1479 resx.res0 |= r->feat_map.masks->res0;
1480 resx.res1 |= r->feat_map.masks->res1;
1481 }
1482
1483 /*
1484 * If the register itself was not valid, all the non-RESx bits are
1485 * now considered RES0 (this matches the behaviour of registers such
1486 * as SCTLR2 and TCR2). Weed out any potential (though unlikely)
1487 * overlap with RES1 bits coming from the previous computation.
1488 */
1489 resx.res0 |= compute_resx_bits(kvm, &r->feat_map, 1, require, exclude).res0;
1490 resx.res1 &= ~resx.res0;
1491
1492 return resx;
1493 }
1494
compute_fgu_bits(struct kvm * kvm,const struct reg_feat_map_desc * r)1495 static u64 compute_fgu_bits(struct kvm *kvm, const struct reg_feat_map_desc *r)
1496 {
1497 struct resx resx;
1498
1499 /*
1500 * If computing FGUs, we collect the unsupported feature bits as
1501 * RESx bits, but don't take the actual RESx bits or register
1502 * existence into account -- we're not computing bits for the
1503 * register itself.
1504 */
1505 resx = compute_resx_bits(kvm, r->bit_feat_map, r->bit_feat_map_sz,
1506 0, NEVER_FGU);
1507
1508 return resx.res0 | resx.res1;
1509 }
1510
compute_fgu(struct kvm * kvm,enum fgt_group_id fgt)1511 void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt)
1512 {
1513 u64 val = 0;
1514
1515 switch (fgt) {
1516 case HFGRTR_GROUP:
1517 val |= compute_fgu_bits(kvm, &hfgrtr_desc);
1518 val |= compute_fgu_bits(kvm, &hfgwtr_desc);
1519 break;
1520 case HFGITR_GROUP:
1521 val |= compute_fgu_bits(kvm, &hfgitr_desc);
1522 break;
1523 case HDFGRTR_GROUP:
1524 val |= compute_fgu_bits(kvm, &hdfgrtr_desc);
1525 val |= compute_fgu_bits(kvm, &hdfgwtr_desc);
1526 break;
1527 case HAFGRTR_GROUP:
1528 val |= compute_fgu_bits(kvm, &hafgrtr_desc);
1529 break;
1530 case HFGRTR2_GROUP:
1531 val |= compute_fgu_bits(kvm, &hfgrtr2_desc);
1532 val |= compute_fgu_bits(kvm, &hfgwtr2_desc);
1533 break;
1534 case HFGITR2_GROUP:
1535 val |= compute_fgu_bits(kvm, &hfgitr2_desc);
1536 break;
1537 case HDFGRTR2_GROUP:
1538 val |= compute_fgu_bits(kvm, &hdfgrtr2_desc);
1539 val |= compute_fgu_bits(kvm, &hdfgwtr2_desc);
1540 break;
1541 case ICH_HFGRTR_GROUP:
1542 val |= compute_fgu_bits(kvm, &ich_hfgrtr_desc);
1543 val |= compute_fgu_bits(kvm, &ich_hfgwtr_desc);
1544 break;
1545 case ICH_HFGITR_GROUP:
1546 val |= compute_fgu_bits(kvm, &ich_hfgitr_desc);
1547 break;
1548 default:
1549 BUG();
1550 }
1551
1552 kvm->arch.fgu[fgt] = val;
1553 }
1554
get_reg_fixed_bits(struct kvm * kvm,enum vcpu_sysreg reg)1555 struct resx get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg)
1556 {
1557 struct resx resx;
1558
1559 switch (reg) {
1560 case HFGRTR_EL2:
1561 resx = compute_reg_resx_bits(kvm, &hfgrtr_desc, 0, 0);
1562 break;
1563 case HFGWTR_EL2:
1564 resx = compute_reg_resx_bits(kvm, &hfgwtr_desc, 0, 0);
1565 break;
1566 case HFGITR_EL2:
1567 resx = compute_reg_resx_bits(kvm, &hfgitr_desc, 0, 0);
1568 break;
1569 case HDFGRTR_EL2:
1570 resx = compute_reg_resx_bits(kvm, &hdfgrtr_desc, 0, 0);
1571 break;
1572 case HDFGWTR_EL2:
1573 resx = compute_reg_resx_bits(kvm, &hdfgwtr_desc, 0, 0);
1574 break;
1575 case HAFGRTR_EL2:
1576 resx = compute_reg_resx_bits(kvm, &hafgrtr_desc, 0, 0);
1577 break;
1578 case HFGRTR2_EL2:
1579 resx = compute_reg_resx_bits(kvm, &hfgrtr2_desc, 0, 0);
1580 break;
1581 case HFGWTR2_EL2:
1582 resx = compute_reg_resx_bits(kvm, &hfgwtr2_desc, 0, 0);
1583 break;
1584 case HFGITR2_EL2:
1585 resx = compute_reg_resx_bits(kvm, &hfgitr2_desc, 0, 0);
1586 break;
1587 case HDFGRTR2_EL2:
1588 resx = compute_reg_resx_bits(kvm, &hdfgrtr2_desc, 0, 0);
1589 break;
1590 case HDFGWTR2_EL2:
1591 resx = compute_reg_resx_bits(kvm, &hdfgwtr2_desc, 0, 0);
1592 break;
1593 case HCRX_EL2:
1594 resx = compute_reg_resx_bits(kvm, &hcrx_desc, 0, 0);
1595 break;
1596 case HCR_EL2:
1597 resx = compute_reg_resx_bits(kvm, &hcr_desc, 0, 0);
1598 break;
1599 case NVHCR_EL2:
1600 /*
1601 * Only apply sanitisation if we do have FEAT_NV3.
1602 * Otherwise, the register aliases with HCR_EL2 in VNCR,
1603 * and we're better off relying on data transfers between
1604 * NVHCR_EL2 and HCR_EL2 to sanitise things.
1605 */
1606 resx = (kvm_has_nv3(kvm) ?
1607 compute_reg_resx_bits(kvm, &nvhcr_desc, 0, 0) :
1608 (typeof(resx)){});
1609 break;
1610 case SCTLR2_EL1:
1611 case SCTLR2_EL2:
1612 resx = compute_reg_resx_bits(kvm, &sctlr2_desc, 0, 0);
1613 break;
1614 case TCR2_EL2:
1615 resx = compute_reg_resx_bits(kvm, &tcr2_el2_desc, 0, 0);
1616 break;
1617 case SCTLR_EL1:
1618 resx = compute_reg_resx_bits(kvm, &sctlr_el1_desc, 0, 0);
1619 break;
1620 case SCTLR_EL2:
1621 resx = compute_reg_resx_bits(kvm, &sctlr_el2_desc, 0, 0);
1622 break;
1623 case MDCR_EL2:
1624 resx = compute_reg_resx_bits(kvm, &mdcr_el2_desc, 0, 0);
1625 break;
1626 case VTCR_EL2:
1627 resx = compute_reg_resx_bits(kvm, &vtcr_el2_desc, 0, 0);
1628 break;
1629 case ICH_HFGRTR_EL2:
1630 resx = compute_reg_resx_bits(kvm, &ich_hfgrtr_desc, 0, 0);
1631 break;
1632 case ICH_HFGWTR_EL2:
1633 resx = compute_reg_resx_bits(kvm, &ich_hfgwtr_desc, 0, 0);
1634 break;
1635 case ICH_HFGITR_EL2:
1636 resx = compute_reg_resx_bits(kvm, &ich_hfgitr_desc, 0, 0);
1637 break;
1638 default:
1639 WARN_ON_ONCE(1);
1640 resx = (typeof(resx)){};
1641 break;
1642 }
1643
1644 return resx;
1645 }
1646
__fgt_reg_to_masks(enum vcpu_sysreg reg)1647 static __always_inline struct fgt_masks *__fgt_reg_to_masks(enum vcpu_sysreg reg)
1648 {
1649 switch (reg) {
1650 case HFGRTR_EL2:
1651 return &hfgrtr_masks;
1652 case HFGWTR_EL2:
1653 return &hfgwtr_masks;
1654 case HFGITR_EL2:
1655 return &hfgitr_masks;
1656 case HDFGRTR_EL2:
1657 return &hdfgrtr_masks;
1658 case HDFGWTR_EL2:
1659 return &hdfgwtr_masks;
1660 case HAFGRTR_EL2:
1661 return &hafgrtr_masks;
1662 case HFGRTR2_EL2:
1663 return &hfgrtr2_masks;
1664 case HFGWTR2_EL2:
1665 return &hfgwtr2_masks;
1666 case HFGITR2_EL2:
1667 return &hfgitr2_masks;
1668 case HDFGRTR2_EL2:
1669 return &hdfgrtr2_masks;
1670 case HDFGWTR2_EL2:
1671 return &hdfgwtr2_masks;
1672 case ICH_HFGRTR_EL2:
1673 return &ich_hfgrtr_masks;
1674 case ICH_HFGWTR_EL2:
1675 return &ich_hfgwtr_masks;
1676 case ICH_HFGITR_EL2:
1677 return &ich_hfgitr_masks;
1678 default:
1679 BUILD_BUG_ON(1);
1680 }
1681 }
1682
__compute_fgt(struct kvm_vcpu * vcpu,enum vcpu_sysreg reg)1683 static __always_inline void __compute_fgt(struct kvm_vcpu *vcpu, enum vcpu_sysreg reg)
1684 {
1685 u64 fgu = vcpu->kvm->arch.fgu[__fgt_reg_to_group_id(reg)];
1686 struct fgt_masks *m = __fgt_reg_to_masks(reg);
1687 u64 clear = 0, set = 0, val = m->nmask;
1688
1689 set |= fgu & m->mask;
1690 clear |= fgu & m->nmask;
1691
1692 if (is_nested_ctxt(vcpu)) {
1693 u64 nested = __vcpu_sys_reg(vcpu, reg);
1694 set |= nested & m->mask;
1695 clear |= ~nested & m->nmask;
1696 }
1697
1698 val |= set | m->res1;
1699 val &= ~(clear | m->res0);
1700 *vcpu_fgt(vcpu, reg) = val;
1701 }
1702
__compute_hfgwtr(struct kvm_vcpu * vcpu)1703 static void __compute_hfgwtr(struct kvm_vcpu *vcpu)
1704 {
1705 __compute_fgt(vcpu, HFGWTR_EL2);
1706
1707 if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38))
1708 *vcpu_fgt(vcpu, HFGWTR_EL2) |= HFGWTR_EL2_TCR_EL1;
1709 }
1710
__compute_hdfgwtr(struct kvm_vcpu * vcpu)1711 static void __compute_hdfgwtr(struct kvm_vcpu *vcpu)
1712 {
1713 __compute_fgt(vcpu, HDFGWTR_EL2);
1714
1715 if (is_hyp_ctxt(vcpu))
1716 *vcpu_fgt(vcpu, HDFGWTR_EL2) |= HDFGWTR_EL2_MDSCR_EL1;
1717 }
1718
__compute_ich_hfgrtr(struct kvm_vcpu * vcpu)1719 static void __compute_ich_hfgrtr(struct kvm_vcpu *vcpu)
1720 {
1721 __compute_fgt(vcpu, ICH_HFGRTR_EL2);
1722
1723 /*
1724 * ICC_IAFFIDR_EL1 *always* needs to be trapped when running a guest.
1725 *
1726 * We also trap accesses to ICC_IDR0_EL1 to allow us to completely hide
1727 * FEAT_GCIE_LEGACY from the guest, and to (potentially) present fewer
1728 * ID bits than the host supports.
1729 */
1730 *vcpu_fgt(vcpu, ICH_HFGRTR_EL2) &= ~(ICH_HFGRTR_EL2_ICC_IAFFIDR_EL1 |
1731 ICH_HFGRTR_EL2_ICC_IDRn_EL1);
1732 }
1733
__compute_ich_hfgwtr(struct kvm_vcpu * vcpu)1734 static void __compute_ich_hfgwtr(struct kvm_vcpu *vcpu)
1735 {
1736 __compute_fgt(vcpu, ICH_HFGWTR_EL2);
1737
1738 /*
1739 * We present a different subset of PPIs the guest from what
1740 * exist in real hardware. We only trap writes, not reads.
1741 */
1742 *vcpu_fgt(vcpu, ICH_HFGWTR_EL2) &= ~(ICH_HFGWTR_EL2_ICC_PPI_ENABLERn_EL1);
1743 }
1744
kvm_vcpu_load_fgt(struct kvm_vcpu * vcpu)1745 void kvm_vcpu_load_fgt(struct kvm_vcpu *vcpu)
1746 {
1747 if (!cpus_have_final_cap(ARM64_HAS_FGT))
1748 return;
1749
1750 __compute_fgt(vcpu, HFGRTR_EL2);
1751 __compute_hfgwtr(vcpu);
1752 __compute_fgt(vcpu, HFGITR_EL2);
1753 __compute_fgt(vcpu, HDFGRTR_EL2);
1754 __compute_hdfgwtr(vcpu);
1755 __compute_fgt(vcpu, HAFGRTR_EL2);
1756
1757 if (cpus_have_final_cap(ARM64_HAS_FGT2)) {
1758 __compute_fgt(vcpu, HFGRTR2_EL2);
1759 __compute_fgt(vcpu, HFGWTR2_EL2);
1760 __compute_fgt(vcpu, HFGITR2_EL2);
1761 __compute_fgt(vcpu, HDFGRTR2_EL2);
1762 __compute_fgt(vcpu, HDFGWTR2_EL2);
1763 }
1764
1765 if (cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF)) {
1766 __compute_ich_hfgrtr(vcpu);
1767 __compute_ich_hfgwtr(vcpu);
1768 __compute_fgt(vcpu, ICH_HFGITR_EL2);
1769 }
1770 }
1771