1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright (c) 2014 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
5 *
6 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
8 *
9 * based on
10 *
11 * samsung/clk.h
12 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
13 * Copyright (c) 2013 Linaro Ltd.
14 * Author: Thomas Abraham <thomas.ab@samsung.com>
15 */
16
17 #ifndef CLK_ROCKCHIP_CLK_H
18 #define CLK_ROCKCHIP_CLK_H
19
20 #include <linux/io.h>
21 #include <linux/clk-provider.h>
22 #include <linux/hashtable.h>
23
24 struct clk;
25
26 #define HIWORD_UPDATE(val, mask, shift) \
27 ((val) << (shift) | (mask) << ((shift) + 16))
28
29 /* register positions shared by PX30, RV1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */
30 #define BOOST_PLL_H_CON(x) ((x) * 0x4)
31 #define BOOST_CLK_CON 0x0008
32 #define BOOST_BOOST_CON 0x000c
33 #define BOOST_SWITCH_CNT 0x0010
34 #define BOOST_HIGH_PERF_CNT0 0x0014
35 #define BOOST_HIGH_PERF_CNT1 0x0018
36 #define BOOST_STATIS_THRESHOLD 0x001c
37 #define BOOST_SHORT_SWITCH_CNT 0x0020
38 #define BOOST_SWITCH_THRESHOLD 0x0024
39 #define BOOST_FSM_STATUS 0x0028
40 #define BOOST_PLL_L_CON(x) ((x) * 0x4 + 0x2c)
41 #define BOOST_RECOVERY_MASK 0x1
42 #define BOOST_RECOVERY_SHIFT 1
43 #define BOOST_SW_CTRL_MASK 0x1
44 #define BOOST_SW_CTRL_SHIFT 2
45 #define BOOST_LOW_FREQ_EN_MASK 0x1
46 #define BOOST_LOW_FREQ_EN_SHIFT 3
47 #define BOOST_BUSY_STATE BIT(8)
48
49 #define PX30_PLL_CON(x) ((x) * 0x4)
50 #define PX30_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
51 #define PX30_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
52 #define PX30_GLB_SRST_FST 0xb8
53 #define PX30_GLB_SRST_SND 0xbc
54 #define PX30_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
55 #define PX30_MODE_CON 0xa0
56 #define PX30_MISC_CON 0xa4
57 #define PX30_SDMMC_CON0 0x380
58 #define PX30_SDMMC_CON1 0x384
59 #define PX30_SDIO_CON0 0x388
60 #define PX30_SDIO_CON1 0x38c
61 #define PX30_EMMC_CON0 0x390
62 #define PX30_EMMC_CON1 0x394
63
64 #define PX30_PMU_PLL_CON(x) ((x) * 0x4)
65 #define PX30_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x40)
66 #define PX30_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x80)
67 #define PX30_PMU_MODE 0x0020
68
69 #define RV1108_PLL_CON(x) ((x) * 0x4)
70 #define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
71 #define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
72 #define RV1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180)
73 #define RV1108_GLB_SRST_FST 0x1c0
74 #define RV1108_GLB_SRST_SND 0x1c4
75 #define RV1108_MISC_CON 0x1cc
76 #define RV1108_SDMMC_CON0 0x1d8
77 #define RV1108_SDMMC_CON1 0x1dc
78 #define RV1108_SDIO_CON0 0x1e0
79 #define RV1108_SDIO_CON1 0x1e4
80 #define RV1108_EMMC_CON0 0x1e8
81 #define RV1108_EMMC_CON1 0x1ec
82
83 #define RV1126_PMU_MODE 0x0
84 #define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10)
85 #define RV1126_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
86 #define RV1126_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
87 #define RV1126_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
88 #define RV1126_PLL_CON(x) ((x) * 0x4)
89 #define RV1126_MODE_CON 0x90
90 #define RV1126_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
91 #define RV1126_CLKGATE_CON(x) ((x) * 0x4 + 0x280)
92 #define RV1126_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
93 #define RV1126_GLB_SRST_FST 0x408
94 #define RV1126_GLB_SRST_SND 0x40c
95 #define RV1126_SDMMC_CON0 0x440
96 #define RV1126_SDMMC_CON1 0x444
97 #define RV1126_SDIO_CON0 0x448
98 #define RV1126_SDIO_CON1 0x44c
99 #define RV1126_EMMC_CON0 0x450
100 #define RV1126_EMMC_CON1 0x454
101
102 #define RK2928_PLL_CON(x) ((x) * 0x4)
103 #define RK2928_MODE_CON 0x40
104 #define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
105 #define RK2928_CLKGATE_CON(x) ((x) * 0x4 + 0xd0)
106 #define RK2928_GLB_SRST_FST 0x100
107 #define RK2928_GLB_SRST_SND 0x104
108 #define RK2928_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
109 #define RK2928_MISC_CON 0x134
110
111 #define RK3036_SDMMC_CON0 0x144
112 #define RK3036_SDMMC_CON1 0x148
113 #define RK3036_SDIO_CON0 0x14c
114 #define RK3036_SDIO_CON1 0x150
115 #define RK3036_EMMC_CON0 0x154
116 #define RK3036_EMMC_CON1 0x158
117
118 #define RK3228_GLB_SRST_FST 0x1f0
119 #define RK3228_GLB_SRST_SND 0x1f4
120 #define RK3228_SDMMC_CON0 0x1c0
121 #define RK3228_SDMMC_CON1 0x1c4
122 #define RK3228_SDIO_CON0 0x1c8
123 #define RK3228_SDIO_CON1 0x1cc
124 #define RK3228_EMMC_CON0 0x1d8
125 #define RK3228_EMMC_CON1 0x1dc
126
127 #define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
128 #define RK3288_MODE_CON 0x50
129 #define RK3288_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
130 #define RK3288_CLKGATE_CON(x) ((x) * 0x4 + 0x160)
131 #define RK3288_GLB_SRST_FST 0x1b0
132 #define RK3288_GLB_SRST_SND 0x1b4
133 #define RK3288_SOFTRST_CON(x) ((x) * 0x4 + 0x1b8)
134 #define RK3288_MISC_CON 0x1e8
135 #define RK3288_SDMMC_CON0 0x200
136 #define RK3288_SDMMC_CON1 0x204
137 #define RK3288_SDIO0_CON0 0x208
138 #define RK3288_SDIO0_CON1 0x20c
139 #define RK3288_SDIO1_CON0 0x210
140 #define RK3288_SDIO1_CON1 0x214
141 #define RK3288_EMMC_CON0 0x218
142 #define RK3288_EMMC_CON1 0x21c
143
144 #define RK3308_PLL_CON(x) RK2928_PLL_CON(x)
145 #define RK3308_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
146 #define RK3308_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
147 #define RK3308_GLB_SRST_FST 0xb8
148 #define RK3308_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
149 #define RK3308_MODE_CON 0xa0
150 #define RK3308_SDMMC_CON0 0x480
151 #define RK3308_SDMMC_CON1 0x484
152 #define RK3308_SDIO_CON0 0x488
153 #define RK3308_SDIO_CON1 0x48c
154 #define RK3308_EMMC_CON0 0x490
155 #define RK3308_EMMC_CON1 0x494
156
157 #define RK3328_PLL_CON(x) RK2928_PLL_CON(x)
158 #define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
159 #define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
160 #define RK3328_GRFCLKSEL_CON(x) ((x) * 0x4 + 0x100)
161 #define RK3328_GLB_SRST_FST 0x9c
162 #define RK3328_GLB_SRST_SND 0x98
163 #define RK3328_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
164 #define RK3328_MODE_CON 0x80
165 #define RK3328_MISC_CON 0x84
166 #define RK3328_SDMMC_CON0 0x380
167 #define RK3328_SDMMC_CON1 0x384
168 #define RK3328_SDIO_CON0 0x388
169 #define RK3328_SDIO_CON1 0x38c
170 #define RK3328_EMMC_CON0 0x390
171 #define RK3328_EMMC_CON1 0x394
172 #define RK3328_SDMMC_EXT_CON0 0x398
173 #define RK3328_SDMMC_EXT_CON1 0x39C
174
175 #define RK3368_PLL_CON(x) RK2928_PLL_CON(x)
176 #define RK3368_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
177 #define RK3368_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
178 #define RK3368_GLB_SRST_FST 0x280
179 #define RK3368_GLB_SRST_SND 0x284
180 #define RK3368_SOFTRST_CON(x) ((x) * 0x4 + 0x300)
181 #define RK3368_MISC_CON 0x380
182 #define RK3368_SDMMC_CON0 0x400
183 #define RK3368_SDMMC_CON1 0x404
184 #define RK3368_SDIO0_CON0 0x408
185 #define RK3368_SDIO0_CON1 0x40c
186 #define RK3368_SDIO1_CON0 0x410
187 #define RK3368_SDIO1_CON1 0x414
188 #define RK3368_EMMC_CON0 0x418
189 #define RK3368_EMMC_CON1 0x41c
190
191 #define RK3399_PLL_CON(x) RK2928_PLL_CON(x)
192 #define RK3399_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
193 #define RK3399_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
194 #define RK3399_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
195 #define RK3399_GLB_SRST_FST 0x500
196 #define RK3399_GLB_SRST_SND 0x504
197 #define RK3399_GLB_CNT_TH 0x508
198 #define RK3399_MISC_CON 0x50c
199 #define RK3399_RST_CON 0x510
200 #define RK3399_RST_ST 0x514
201 #define RK3399_SDMMC_CON0 0x580
202 #define RK3399_SDMMC_CON1 0x584
203 #define RK3399_SDIO_CON0 0x588
204 #define RK3399_SDIO_CON1 0x58c
205
206 #define RK3399_PMU_PLL_CON(x) RK2928_PLL_CON(x)
207 #define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
208 #define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
209 #define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
210
211 #define RK3528_PMU_CRU_BASE 0x10000
212 #define RK3528_PCIE_CRU_BASE 0x20000
213 #define RK3528_DDRPHY_CRU_BASE 0x28000
214 #define RK3528_PLL_CON(x) RK2928_PLL_CON(x)
215 #define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
216 #define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
217 #define RK3528_MODE_CON 0x280
218 #define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
219 #define RK3528_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
220 #define RK3528_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
221 #define RK3528_SDMMC_CON(x) ((x) * 0x4 + 0x24)
222 #define RK3528_SDIO0_CON(x) ((x) * 0x4 + 0x4)
223 #define RK3528_SDIO1_CON(x) ((x) * 0x4 + 0xc)
224 #define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
225 #define RK3528_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE)
226 #define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
227 #define RK3528_PCIE_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE)
228 #define RK3528_DDRPHY_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE)
229 #define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
230 #define RK3528_GLB_CNT_TH 0xc00
231 #define RK3528_GLB_SRST_FST 0xc08
232 #define RK3528_GLB_SRST_SND 0xc0c
233
234 #define RK3562_PMU0_CRU_BASE 0x10000
235 #define RK3562_PMU1_CRU_BASE 0x18000
236 #define RK3562_DDR_CRU_BASE 0x20000
237 #define RK3562_SUBDDR_CRU_BASE 0x28000
238 #define RK3562_PERI_CRU_BASE 0x30000
239
240 #define RK3562_PLL_CON(x) RK2928_PLL_CON(x)
241 #define RK3562_PMU1_PLL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x40)
242 #define RK3562_SUBDDR_PLL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x20)
243 #define RK3562_MODE_CON 0x600
244 #define RK3562_PMU1_MODE_CON (RK3562_PMU1_CRU_BASE + 0x380)
245 #define RK3562_SUBDDR_MODE_CON (RK3562_SUBDDR_CRU_BASE + 0x380)
246 #define RK3562_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
247 #define RK3562_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
248 #define RK3562_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
249 #define RK3562_DDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x100)
250 #define RK3562_DDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x180)
251 #define RK3562_DDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_DDR_CRU_BASE + 0x200)
252 #define RK3562_SUBDDR_CLKSEL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x100)
253 #define RK3562_SUBDDR_CLKGATE_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x180)
254 #define RK3562_SUBDDR_SOFTRST_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x200)
255 #define RK3562_PERI_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x100)
256 #define RK3562_PERI_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x300)
257 #define RK3562_PERI_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PERI_CRU_BASE + 0x400)
258 #define RK3562_PMU0_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x100)
259 #define RK3562_PMU0_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x180)
260 #define RK3562_PMU0_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU0_CRU_BASE + 0x200)
261 #define RK3562_PMU1_CLKSEL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x100)
262 #define RK3562_PMU1_CLKGATE_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x180)
263 #define RK3562_PMU1_SOFTRST_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x200)
264 #define RK3562_GLB_SRST_FST 0x614
265 #define RK3562_GLB_SRST_SND 0x618
266 #define RK3562_GLB_RST_CON 0x61c
267 #define RK3562_GLB_RST_ST 0x620
268 #define RK3562_SDMMC0_CON0 0x624
269 #define RK3562_SDMMC0_CON1 0x628
270 #define RK3562_SDMMC1_CON0 0x62c
271 #define RK3562_SDMMC1_CON1 0x630
272
273 #define RK3568_PLL_CON(x) RK2928_PLL_CON(x)
274 #define RK3568_MODE_CON0 0xc0
275 #define RK3568_MISC_CON0 0xc4
276 #define RK3568_MISC_CON1 0xc8
277 #define RK3568_MISC_CON2 0xcc
278 #define RK3568_GLB_CNT_TH 0xd0
279 #define RK3568_GLB_SRST_FST 0xd4
280 #define RK3568_GLB_SRST_SND 0xd8
281 #define RK3568_GLB_RST_CON 0xdc
282 #define RK3568_GLB_RST_ST 0xe0
283 #define RK3568_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
284 #define RK3568_CLKGATE_CON(x) ((x) * 0x4 + 0x300)
285 #define RK3568_SOFTRST_CON(x) ((x) * 0x4 + 0x400)
286 #define RK3568_SDMMC0_CON0 0x580
287 #define RK3568_SDMMC0_CON1 0x584
288 #define RK3568_SDMMC1_CON0 0x588
289 #define RK3568_SDMMC1_CON1 0x58c
290 #define RK3568_SDMMC2_CON0 0x590
291 #define RK3568_SDMMC2_CON1 0x594
292 #define RK3568_EMMC_CON0 0x598
293 #define RK3568_EMMC_CON1 0x59c
294
295 #define RK3568_PMU_PLL_CON(x) RK2928_PLL_CON(x)
296 #define RK3568_PMU_MODE_CON0 0x80
297 #define RK3568_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
298 #define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180)
299 #define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200)
300
301 #define RK3576_PHP_CRU_BASE 0x8000
302 #define RK3576_SECURE_NS_CRU_BASE 0x10000
303 #define RK3576_PMU_CRU_BASE 0x20000
304 #define RK3576_BIGCORE_CRU_BASE 0x38000
305 #define RK3576_LITCORE_CRU_BASE 0x40000
306 #define RK3576_CCI_CRU_BASE 0x48000
307
308 #define RK3576_PLL_CON(x) RK2928_PLL_CON(x)
309 #define RK3576_MODE_CON0 0x280
310 #define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280)
311 #define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280)
312 #define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280)
313 #define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
314 #define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
315 #define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
316 #define RK3576_GLB_CNT_TH 0xc00
317 #define RK3576_GLB_SRST_FST 0xc08
318 #define RK3576_GLB_SRST_SND 0xc0c
319 #define RK3576_GLB_RST_CON 0xc10
320 #define RK3576_GLB_RST_ST 0xc04
321 #define RK3576_SDIO_CON0 0xC24
322 #define RK3576_SDIO_CON1 0xC28
323 #define RK3576_SDMMC_CON0 0xC30
324 #define RK3576_SDMMC_CON1 0xC34
325
326 #define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300)
327 #define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800)
328 #define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00)
329
330 #define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE)
331 #define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300)
332 #define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800)
333 #define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00)
334
335 #define RK3576_SECURE_NS_CLKSEL_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x300)
336 #define RK3576_SECURE_NS_CLKGATE_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x800)
337 #define RK3576_SECURE_NS_SOFTRST_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0xa00)
338
339 #define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300)
340 #define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800)
341 #define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00)
342
343 #define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE)
344 #define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300)
345 #define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800)
346 #define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00)
347 #define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE)
348 #define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300)
349 #define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800)
350 #define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00)
351 #define RK3576_NON_SECURE_GATING_CON00 0xc48
352
353 #define RK3588_PHP_CRU_BASE 0x8000
354 #define RK3588_PMU_CRU_BASE 0x30000
355 #define RK3588_BIGCORE0_CRU_BASE 0x50000
356 #define RK3588_BIGCORE1_CRU_BASE 0x52000
357 #define RK3588_DSU_CRU_BASE 0x58000
358
359 #define RK3588_PLL_CON(x) RK2928_PLL_CON(x)
360 #define RK3588_MODE_CON0 0x280
361 #define RK3588_B0_PLL_MODE_CON0 (RK3588_BIGCORE0_CRU_BASE + 0x280)
362 #define RK3588_B1_PLL_MODE_CON0 (RK3588_BIGCORE1_CRU_BASE + 0x280)
363 #define RK3588_LPLL_MODE_CON0 (RK3588_DSU_CRU_BASE + 0x280)
364 #define RK3588_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
365 #define RK3588_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
366 #define RK3588_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
367 #define RK3588_GLB_CNT_TH 0xc00
368 #define RK3588_GLB_SRST_FST 0xc08
369 #define RK3588_GLB_SRST_SND 0xc0c
370 #define RK3588_GLB_RST_CON 0xc10
371 #define RK3588_GLB_RST_ST 0xc04
372 #define RK3588_SDIO_CON0 0xC24
373 #define RK3588_SDIO_CON1 0xC28
374 #define RK3588_SDMMC_CON0 0xC30
375 #define RK3588_SDMMC_CON1 0xC34
376
377 #define RK3588_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800)
378 #define RK3588_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00)
379
380 #define RK3588_PMU_PLL_CON(x) ((x) * 0x4 + RK3588_PHP_CRU_BASE)
381 #define RK3588_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300)
382 #define RK3588_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800)
383 #define RK3588_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00)
384
385 #define RK3588_B0_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE)
386 #define RK3588_BIGCORE0_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300)
387 #define RK3588_BIGCORE0_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800)
388 #define RK3588_BIGCORE0_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00)
389 #define RK3588_B1_PLL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE)
390 #define RK3588_BIGCORE1_CLKSEL_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300)
391 #define RK3588_BIGCORE1_CLKGATE_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800)
392 #define RK3588_BIGCORE1_SOFTRST_CON(x) ((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00)
393 #define RK3588_LPLL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE)
394 #define RK3588_DSU_CLKSEL_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300)
395 #define RK3588_DSU_CLKGATE_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
396 #define RK3588_DSU_SOFTRST_CON(x) ((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)
397
398 enum rockchip_pll_type {
399 pll_rk3036,
400 pll_rk3066,
401 pll_rk3328,
402 pll_rk3399,
403 pll_rk3588,
404 pll_rk3588_core,
405 pll_rk3588_ddr,
406 };
407
408 #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
409 _postdiv2, _dsmpd, _frac) \
410 { \
411 .rate = _rate##U, \
412 .fbdiv = _fbdiv, \
413 .postdiv1 = _postdiv1, \
414 .refdiv = _refdiv, \
415 .postdiv2 = _postdiv2, \
416 .dsmpd = _dsmpd, \
417 .frac = _frac, \
418 }
419
420 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
421 { \
422 .rate = _rate##U, \
423 .nr = _nr, \
424 .nf = _nf, \
425 .no = _no, \
426 .nb = ((_nf) < 2) ? 1 : (_nf) >> 1, \
427 }
428
429 #define RK3066_PLL_RATE_NB(_rate, _nr, _nf, _no, _nb) \
430 { \
431 .rate = _rate##U, \
432 .nr = _nr, \
433 .nf = _nf, \
434 .no = _no, \
435 .nb = _nb, \
436 }
437
438 #define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \
439 { \
440 .rate = _rate##U, \
441 .p = _p, \
442 .m = _m, \
443 .s = _s, \
444 .k = _k, \
445 }
446
447 enum rockchip_grf_type {
448 grf_type_sys = 0,
449 grf_type_pmu0,
450 grf_type_pmu1,
451 grf_type_ioc,
452 grf_type_vo,
453 grf_type_vpu,
454 };
455
456 /* ceil(sqrt(enums in rockchip_grf_type - 1)) */
457 #define GRF_HASH_ORDER 2
458
459 /**
460 * struct rockchip_aux_grf - entry for the aux_grf_table hashtable
461 * @grf: pointer to the grf this entry references
462 * @type: what type of GRF this is
463 * @node: hlist node
464 */
465 struct rockchip_aux_grf {
466 struct regmap *grf;
467 enum rockchip_grf_type type;
468 struct hlist_node node;
469 };
470
471 /**
472 * struct rockchip_clk_provider - information about clock provider
473 * @reg_base: virtual address for the register base.
474 * @clk_data: holds clock related data like clk* and number of clocks.
475 * @cru_node: device-node of the clock-provider
476 * @grf: regmap of the general-register-files syscon
477 * @aux_grf_table: hashtable of auxiliary GRF regmaps, indexed by grf_type
478 * @lock: maintains exclusion between callbacks for a given clock-provider.
479 */
480 struct rockchip_clk_provider {
481 void __iomem *reg_base;
482 struct clk_onecell_data clk_data;
483 struct device_node *cru_node;
484 struct regmap *grf;
485 DECLARE_HASHTABLE(aux_grf_table, GRF_HASH_ORDER);
486 spinlock_t lock;
487 };
488
489 struct rockchip_pll_rate_table {
490 unsigned long rate;
491 union {
492 struct {
493 /* for RK3066 */
494 unsigned int nr;
495 unsigned int nf;
496 unsigned int no;
497 unsigned int nb;
498 };
499 struct {
500 /* for RK3036/RK3399 */
501 unsigned int fbdiv;
502 unsigned int postdiv1;
503 unsigned int refdiv;
504 unsigned int postdiv2;
505 unsigned int dsmpd;
506 unsigned int frac;
507 };
508 struct {
509 /* for RK3588 */
510 unsigned int m;
511 unsigned int p;
512 unsigned int s;
513 unsigned int k;
514 };
515 };
516 };
517
518 /**
519 * struct rockchip_pll_clock - information about pll clock
520 * @id: platform specific id of the clock.
521 * @name: name of this pll clock.
522 * @parent_names: name of the parent clock.
523 * @num_parents: number of parents
524 * @flags: optional flags for basic clock.
525 * @con_offset: offset of the register for configuring the PLL.
526 * @mode_offset: offset of the register for configuring the PLL-mode.
527 * @mode_shift: offset inside the mode-register for the mode of this pll.
528 * @lock_shift: offset inside the lock register for the lock status.
529 * @type: Type of PLL to be registered.
530 * @pll_flags: hardware-specific flags
531 * @rate_table: Table of usable pll rates
532 *
533 * Flags:
534 * ROCKCHIP_PLL_SYNC_RATE - check rate parameters to match against the
535 * rate_table parameters and ajust them if necessary.
536 * ROCKCHIP_PLL_FIXED_MODE - the pll operates in normal mode only
537 */
538 struct rockchip_pll_clock {
539 unsigned int id;
540 const char *name;
541 const char *const *parent_names;
542 u8 num_parents;
543 unsigned long flags;
544 int con_offset;
545 int mode_offset;
546 int mode_shift;
547 int lock_shift;
548 enum rockchip_pll_type type;
549 u8 pll_flags;
550 struct rockchip_pll_rate_table *rate_table;
551 };
552
553 #define ROCKCHIP_PLL_SYNC_RATE BIT(0)
554 #define ROCKCHIP_PLL_FIXED_MODE BIT(1)
555
556 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
557 _lshift, _pflags, _rtable) \
558 { \
559 .id = _id, \
560 .type = _type, \
561 .name = _name, \
562 .parent_names = _pnames, \
563 .num_parents = ARRAY_SIZE(_pnames), \
564 .flags = CLK_GET_RATE_NOCACHE | _flags, \
565 .con_offset = _con, \
566 .mode_offset = _mode, \
567 .mode_shift = _mshift, \
568 .lock_shift = _lshift, \
569 .pll_flags = _pflags, \
570 .rate_table = _rtable, \
571 }
572
573 struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
574 enum rockchip_pll_type pll_type,
575 const char *name, const char *const *parent_names,
576 u8 num_parents, int con_offset, int grf_lock_offset,
577 int lock_shift, int mode_offset, int mode_shift,
578 struct rockchip_pll_rate_table *rate_table,
579 unsigned long flags, u8 clk_pll_flags);
580
581 struct rockchip_cpuclk_clksel {
582 int reg;
583 u32 val;
584 };
585
586 #define ROCKCHIP_CPUCLK_NUM_DIVIDERS 6
587 #define ROCKCHIP_CPUCLK_MAX_CORES 4
588 struct rockchip_cpuclk_rate_table {
589 unsigned long prate;
590 struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
591 struct rockchip_cpuclk_clksel pre_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
592 struct rockchip_cpuclk_clksel post_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
593 };
594
595 /**
596 * struct rockchip_cpuclk_reg_data - register offsets and masks of the cpuclock
597 * @core_reg[]: register offset of the cores setting register
598 * @div_core_shift[]: cores divider offset used to divide the pll value
599 * @div_core_mask[]: cores divider mask
600 * @num_cores: number of cpu cores
601 * @mux_core_reg: register offset of the cores select parent
602 * @mux_core_alt: mux value to select alternate parent
603 * @mux_core_main: mux value to select main parent of core
604 * @mux_core_shift: offset of the core multiplexer
605 * @mux_core_mask: core multiplexer mask
606 */
607 struct rockchip_cpuclk_reg_data {
608 int core_reg[ROCKCHIP_CPUCLK_MAX_CORES];
609 u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES];
610 u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES];
611 int num_cores;
612 int mux_core_reg;
613 u8 mux_core_alt;
614 u8 mux_core_main;
615 u8 mux_core_shift;
616 u32 mux_core_mask;
617 };
618
619 struct clk *rockchip_clk_register_cpuclk(const char *name,
620 const char *const *parent_names, u8 num_parents,
621 const struct rockchip_cpuclk_reg_data *reg_data,
622 const struct rockchip_cpuclk_rate_table *rates,
623 int nrates, void __iomem *reg_base, spinlock_t *lock);
624
625 struct clk *rockchip_clk_register_mmc(const char *name,
626 const char *const *parent_names, u8 num_parents,
627 void __iomem *reg,
628 struct regmap *grf, int grf_reg,
629 int shift);
630
631 /*
632 * DDRCLK flags, including method of setting the rate
633 * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
634 */
635 #define ROCKCHIP_DDRCLK_SIP BIT(0)
636
637 struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
638 const char *const *parent_names,
639 u8 num_parents, int mux_offset,
640 int mux_shift, int mux_width,
641 int div_shift, int div_width,
642 int ddr_flags, void __iomem *reg_base,
643 spinlock_t *lock);
644
645 #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
646
647 struct clk *rockchip_clk_register_inverter(const char *name,
648 const char *const *parent_names, u8 num_parents,
649 void __iomem *reg, int shift, int flags,
650 spinlock_t *lock);
651
652 struct clk *rockchip_clk_register_muxgrf(const char *name,
653 const char *const *parent_names, u8 num_parents,
654 int flags, struct regmap *grf, int reg,
655 int shift, int width, int mux_flags);
656
657 struct clk *rockchip_clk_register_gate_grf(const char *name,
658 const char *parent_name, unsigned long flags,
659 struct regmap *regmap, unsigned int reg,
660 unsigned int shift, u8 gate_flags);
661
662 #define PNAME(x) static const char *const x[] __initconst
663
664 enum rockchip_clk_branch_type {
665 branch_composite,
666 branch_mux,
667 branch_grf_mux,
668 branch_divider,
669 branch_fraction_divider,
670 branch_gate,
671 branch_grf_gate,
672 branch_linked_gate,
673 branch_mmc,
674 branch_grf_mmc,
675 branch_inverter,
676 branch_factor,
677 branch_ddrclk,
678 branch_half_divider,
679 };
680
681 struct rockchip_clk_branch {
682 unsigned int id;
683 enum rockchip_clk_branch_type branch_type;
684 const char *name;
685 const char *const *parent_names;
686 u8 num_parents;
687 unsigned long flags;
688 int muxdiv_offset;
689 u8 mux_shift;
690 u8 mux_width;
691 u8 mux_flags;
692 u32 *mux_table;
693 int div_offset;
694 u8 div_shift;
695 u8 div_width;
696 u8 div_flags;
697 struct clk_div_table *div_table;
698 int gate_offset;
699 u8 gate_shift;
700 u8 gate_flags;
701 unsigned int linked_clk_id;
702 enum rockchip_grf_type grf_type;
703 struct rockchip_clk_branch *child;
704 };
705
706 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
707 df, go, gs, gf) \
708 { \
709 .id = _id, \
710 .branch_type = branch_composite, \
711 .name = cname, \
712 .parent_names = pnames, \
713 .num_parents = ARRAY_SIZE(pnames), \
714 .flags = f, \
715 .muxdiv_offset = mo, \
716 .mux_shift = ms, \
717 .mux_width = mw, \
718 .mux_flags = mf, \
719 .div_shift = ds, \
720 .div_width = dw, \
721 .div_flags = df, \
722 .gate_offset = go, \
723 .gate_shift = gs, \
724 .gate_flags = gf, \
725 }
726
727 #define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \
728 mf, do, ds, dw, df, go, gs, gf) \
729 { \
730 .id = _id, \
731 .branch_type = branch_composite, \
732 .name = cname, \
733 .parent_names = pnames, \
734 .num_parents = ARRAY_SIZE(pnames), \
735 .flags = f, \
736 .muxdiv_offset = mo, \
737 .mux_shift = ms, \
738 .mux_width = mw, \
739 .mux_flags = mf, \
740 .div_offset = do, \
741 .div_shift = ds, \
742 .div_width = dw, \
743 .div_flags = df, \
744 .gate_offset = go, \
745 .gate_shift = gs, \
746 .gate_flags = gf, \
747 }
748
749 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
750 go, gs, gf) \
751 { \
752 .id = _id, \
753 .branch_type = branch_composite, \
754 .name = cname, \
755 .parent_names = (const char *[]){ pname }, \
756 .num_parents = 1, \
757 .flags = f, \
758 .muxdiv_offset = mo, \
759 .div_shift = ds, \
760 .div_width = dw, \
761 .div_flags = df, \
762 .gate_offset = go, \
763 .gate_shift = gs, \
764 .gate_flags = gf, \
765 }
766
767 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
768 df, dt, go, gs, gf) \
769 { \
770 .id = _id, \
771 .branch_type = branch_composite, \
772 .name = cname, \
773 .parent_names = (const char *[]){ pname }, \
774 .num_parents = 1, \
775 .flags = f, \
776 .muxdiv_offset = mo, \
777 .div_shift = ds, \
778 .div_width = dw, \
779 .div_flags = df, \
780 .div_table = dt, \
781 .gate_offset = go, \
782 .gate_shift = gs, \
783 .gate_flags = gf, \
784 }
785
786 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
787 go, gs, gf) \
788 { \
789 .id = _id, \
790 .branch_type = branch_composite, \
791 .name = cname, \
792 .parent_names = pnames, \
793 .num_parents = ARRAY_SIZE(pnames), \
794 .flags = f, \
795 .muxdiv_offset = mo, \
796 .mux_shift = ms, \
797 .mux_width = mw, \
798 .mux_flags = mf, \
799 .gate_offset = go, \
800 .gate_shift = gs, \
801 .gate_flags = gf, \
802 }
803
804 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
805 ds, dw, df) \
806 { \
807 .id = _id, \
808 .branch_type = branch_composite, \
809 .name = cname, \
810 .parent_names = pnames, \
811 .num_parents = ARRAY_SIZE(pnames), \
812 .flags = f, \
813 .muxdiv_offset = mo, \
814 .mux_shift = ms, \
815 .mux_width = mw, \
816 .mux_flags = mf, \
817 .div_shift = ds, \
818 .div_width = dw, \
819 .div_flags = df, \
820 .gate_offset = -1, \
821 }
822
823 #define COMPOSITE_NOGATE_DIVTBL(_id, cname, pnames, f, mo, ms, \
824 mw, mf, ds, dw, df, dt) \
825 { \
826 .id = _id, \
827 .branch_type = branch_composite, \
828 .name = cname, \
829 .parent_names = pnames, \
830 .num_parents = ARRAY_SIZE(pnames), \
831 .flags = f, \
832 .muxdiv_offset = mo, \
833 .mux_shift = ms, \
834 .mux_width = mw, \
835 .mux_flags = mf, \
836 .div_shift = ds, \
837 .div_width = dw, \
838 .div_flags = df, \
839 .div_table = dt, \
840 .gate_offset = -1, \
841 }
842
843 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
844 { \
845 .id = _id, \
846 .branch_type = branch_fraction_divider, \
847 .name = cname, \
848 .parent_names = (const char *[]){ pname }, \
849 .num_parents = 1, \
850 .flags = f, \
851 .muxdiv_offset = mo, \
852 .div_shift = 16, \
853 .div_width = 16, \
854 .div_flags = df, \
855 .gate_offset = go, \
856 .gate_shift = gs, \
857 .gate_flags = gf, \
858 }
859
860 #define COMPOSITE_FRACMUX(_id, cname, pname, f, mo, df, go, gs, gf, ch) \
861 { \
862 .id = _id, \
863 .branch_type = branch_fraction_divider, \
864 .name = cname, \
865 .parent_names = (const char *[]){ pname }, \
866 .num_parents = 1, \
867 .flags = f, \
868 .muxdiv_offset = mo, \
869 .div_shift = 16, \
870 .div_width = 16, \
871 .div_flags = df, \
872 .gate_offset = go, \
873 .gate_shift = gs, \
874 .gate_flags = gf, \
875 .child = ch, \
876 }
877
878 #define COMPOSITE_FRACMUX_NOGATE(_id, cname, pname, f, mo, df, ch) \
879 { \
880 .id = _id, \
881 .branch_type = branch_fraction_divider, \
882 .name = cname, \
883 .parent_names = (const char *[]){ pname }, \
884 .num_parents = 1, \
885 .flags = f, \
886 .muxdiv_offset = mo, \
887 .div_shift = 16, \
888 .div_width = 16, \
889 .div_flags = df, \
890 .gate_offset = -1, \
891 .child = ch, \
892 }
893
894 #define COMPOSITE_DDRCLK(_id, cname, pnames, f, mo, ms, mw, \
895 ds, dw, df) \
896 { \
897 .id = _id, \
898 .branch_type = branch_ddrclk, \
899 .name = cname, \
900 .parent_names = pnames, \
901 .num_parents = ARRAY_SIZE(pnames), \
902 .flags = f, \
903 .muxdiv_offset = mo, \
904 .mux_shift = ms, \
905 .mux_width = mw, \
906 .div_shift = ds, \
907 .div_width = dw, \
908 .div_flags = df, \
909 .gate_offset = -1, \
910 }
911
912 #define MUX(_id, cname, pnames, f, o, s, w, mf) \
913 { \
914 .id = _id, \
915 .branch_type = branch_mux, \
916 .name = cname, \
917 .parent_names = pnames, \
918 .num_parents = ARRAY_SIZE(pnames), \
919 .flags = f, \
920 .muxdiv_offset = o, \
921 .mux_shift = s, \
922 .mux_width = w, \
923 .mux_flags = mf, \
924 .gate_offset = -1, \
925 }
926
927 #define MUXTBL(_id, cname, pnames, f, o, s, w, mf, mt) \
928 { \
929 .id = _id, \
930 .branch_type = branch_mux, \
931 .name = cname, \
932 .parent_names = pnames, \
933 .num_parents = ARRAY_SIZE(pnames), \
934 .flags = f, \
935 .muxdiv_offset = o, \
936 .mux_shift = s, \
937 .mux_width = w, \
938 .mux_flags = mf, \
939 .gate_offset = -1, \
940 .mux_table = mt, \
941 }
942
943 #define MUXGRF(_id, cname, pnames, f, o, s, w, mf, gt) \
944 { \
945 .id = _id, \
946 .branch_type = branch_grf_mux, \
947 .name = cname, \
948 .parent_names = pnames, \
949 .num_parents = ARRAY_SIZE(pnames), \
950 .flags = f, \
951 .muxdiv_offset = o, \
952 .mux_shift = s, \
953 .mux_width = w, \
954 .mux_flags = mf, \
955 .gate_offset = -1, \
956 .grf_type = gt, \
957 }
958
959 #define DIV(_id, cname, pname, f, o, s, w, df) \
960 { \
961 .id = _id, \
962 .branch_type = branch_divider, \
963 .name = cname, \
964 .parent_names = (const char *[]){ pname }, \
965 .num_parents = 1, \
966 .flags = f, \
967 .muxdiv_offset = o, \
968 .div_shift = s, \
969 .div_width = w, \
970 .div_flags = df, \
971 .gate_offset = -1, \
972 }
973
974 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
975 { \
976 .id = _id, \
977 .branch_type = branch_divider, \
978 .name = cname, \
979 .parent_names = (const char *[]){ pname }, \
980 .num_parents = 1, \
981 .flags = f, \
982 .muxdiv_offset = o, \
983 .div_shift = s, \
984 .div_width = w, \
985 .div_flags = df, \
986 .div_table = dt, \
987 }
988
989 #define GATE(_id, cname, pname, f, o, b, gf) \
990 { \
991 .id = _id, \
992 .branch_type = branch_gate, \
993 .name = cname, \
994 .parent_names = (const char *[]){ pname }, \
995 .num_parents = 1, \
996 .flags = f, \
997 .gate_offset = o, \
998 .gate_shift = b, \
999 .gate_flags = gf, \
1000 }
1001
1002 #define GATE_GRF(_id, cname, pname, f, o, b, gf, gt) \
1003 { \
1004 .id = _id, \
1005 .branch_type = branch_grf_gate, \
1006 .name = cname, \
1007 .parent_names = (const char *[]){ pname }, \
1008 .num_parents = 1, \
1009 .flags = f, \
1010 .gate_offset = o, \
1011 .gate_shift = b, \
1012 .gate_flags = gf, \
1013 .grf_type = gt, \
1014 }
1015
1016 #define GATE_LINK(_id, cname, pname, linkedclk, f, o, b, gf) \
1017 { \
1018 .id = _id, \
1019 .branch_type = branch_linked_gate, \
1020 .name = cname, \
1021 .parent_names = (const char *[]){ pname }, \
1022 .linked_clk_id = linkedclk, \
1023 .num_parents = 1, \
1024 .flags = f, \
1025 .gate_offset = o, \
1026 .gate_shift = b, \
1027 .gate_flags = gf, \
1028 }
1029
1030 #define MMC(_id, cname, pname, offset, shift) \
1031 { \
1032 .id = _id, \
1033 .branch_type = branch_mmc, \
1034 .name = cname, \
1035 .parent_names = (const char *[]){ pname }, \
1036 .num_parents = 1, \
1037 .muxdiv_offset = offset, \
1038 .div_shift = shift, \
1039 }
1040
1041 #define MMC_GRF(_id, cname, pname, offset, shift, grftype) \
1042 { \
1043 .id = _id, \
1044 .branch_type = branch_grf_mmc, \
1045 .name = cname, \
1046 .parent_names = (const char *[]){ pname }, \
1047 .num_parents = 1, \
1048 .muxdiv_offset = offset, \
1049 .div_shift = shift, \
1050 .grf_type = grftype, \
1051 }
1052
1053 #define INVERTER(_id, cname, pname, io, is, if) \
1054 { \
1055 .id = _id, \
1056 .branch_type = branch_inverter, \
1057 .name = cname, \
1058 .parent_names = (const char *[]){ pname }, \
1059 .num_parents = 1, \
1060 .muxdiv_offset = io, \
1061 .div_shift = is, \
1062 .div_flags = if, \
1063 }
1064
1065 #define FACTOR(_id, cname, pname, f, fm, fd) \
1066 { \
1067 .id = _id, \
1068 .branch_type = branch_factor, \
1069 .name = cname, \
1070 .parent_names = (const char *[]){ pname }, \
1071 .num_parents = 1, \
1072 .flags = f, \
1073 .div_shift = fm, \
1074 .div_width = fd, \
1075 }
1076
1077 #define FACTOR_GATE(_id, cname, pname, f, fm, fd, go, gb, gf) \
1078 { \
1079 .id = _id, \
1080 .branch_type = branch_factor, \
1081 .name = cname, \
1082 .parent_names = (const char *[]){ pname }, \
1083 .num_parents = 1, \
1084 .flags = f, \
1085 .div_shift = fm, \
1086 .div_width = fd, \
1087 .gate_offset = go, \
1088 .gate_shift = gb, \
1089 .gate_flags = gf, \
1090 }
1091
1092 #define COMPOSITE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
1093 df, go, gs, gf) \
1094 { \
1095 .id = _id, \
1096 .branch_type = branch_half_divider, \
1097 .name = cname, \
1098 .parent_names = pnames, \
1099 .num_parents = ARRAY_SIZE(pnames), \
1100 .flags = f, \
1101 .muxdiv_offset = mo, \
1102 .mux_shift = ms, \
1103 .mux_width = mw, \
1104 .mux_flags = mf, \
1105 .div_shift = ds, \
1106 .div_width = dw, \
1107 .div_flags = df, \
1108 .gate_offset = go, \
1109 .gate_shift = gs, \
1110 .gate_flags = gf, \
1111 }
1112
1113 #define COMPOSITE_NOGATE_HALFDIV(_id, cname, pnames, f, mo, ms, mw, mf, \
1114 ds, dw, df) \
1115 { \
1116 .id = _id, \
1117 .branch_type = branch_half_divider, \
1118 .name = cname, \
1119 .parent_names = pnames, \
1120 .num_parents = ARRAY_SIZE(pnames), \
1121 .flags = f, \
1122 .muxdiv_offset = mo, \
1123 .mux_shift = ms, \
1124 .mux_width = mw, \
1125 .mux_flags = mf, \
1126 .div_shift = ds, \
1127 .div_width = dw, \
1128 .div_flags = df, \
1129 .gate_offset = -1, \
1130 }
1131
1132 #define COMPOSITE_NOMUX_HALFDIV(_id, cname, pname, f, mo, ds, dw, df, \
1133 go, gs, gf) \
1134 { \
1135 .id = _id, \
1136 .branch_type = branch_half_divider, \
1137 .name = cname, \
1138 .parent_names = (const char *[]){ pname }, \
1139 .num_parents = 1, \
1140 .flags = f, \
1141 .muxdiv_offset = mo, \
1142 .div_shift = ds, \
1143 .div_width = dw, \
1144 .div_flags = df, \
1145 .gate_offset = go, \
1146 .gate_shift = gs, \
1147 .gate_flags = gf, \
1148 }
1149
1150 #define DIV_HALF(_id, cname, pname, f, o, s, w, df) \
1151 { \
1152 .id = _id, \
1153 .branch_type = branch_half_divider, \
1154 .name = cname, \
1155 .parent_names = (const char *[]){ pname }, \
1156 .num_parents = 1, \
1157 .flags = f, \
1158 .muxdiv_offset = o, \
1159 .div_shift = s, \
1160 .div_width = w, \
1161 .div_flags = df, \
1162 .gate_offset = -1, \
1163 }
1164
1165 /* SGRF clocks are only accessible from secure mode, so not controllable */
1166 #define SGRF_GATE(_id, cname, pname) \
1167 FACTOR(_id, cname, pname, 0, 1, 1)
1168
rockchip_clk_get_lookup(struct rockchip_clk_provider * ctx,unsigned int id)1169 static inline struct clk *rockchip_clk_get_lookup(struct rockchip_clk_provider *ctx,
1170 unsigned int id)
1171 {
1172 return ctx->clk_data.clks[id];
1173 }
1174
rockchip_clk_set_lookup(struct rockchip_clk_provider * ctx,struct clk * clk,unsigned int id)1175 static inline void rockchip_clk_set_lookup(struct rockchip_clk_provider *ctx,
1176 struct clk *clk, unsigned int id)
1177 {
1178 ctx->clk_data.clks[id] = clk;
1179 }
1180
1181 struct rockchip_gate_link_platdata {
1182 struct rockchip_clk_provider *ctx;
1183 struct rockchip_clk_branch *clkbr;
1184 };
1185
1186 struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
1187 void __iomem *base, unsigned long nr_clks);
1188 struct rockchip_clk_provider *rockchip_clk_init_early(struct device_node *np,
1189 void __iomem *base, unsigned long nr_clks);
1190 void rockchip_clk_finalize(struct rockchip_clk_provider *ctx);
1191 void rockchip_clk_of_add_provider(struct device_node *np,
1192 struct rockchip_clk_provider *ctx);
1193 unsigned long rockchip_clk_find_max_clk_id(struct rockchip_clk_branch *list,
1194 unsigned int nr_clk);
1195 void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
1196 struct rockchip_clk_branch *list,
1197 unsigned int nr_clk);
1198 void rockchip_clk_register_late_branches(struct device *dev,
1199 struct rockchip_clk_provider *ctx,
1200 struct rockchip_clk_branch *list,
1201 unsigned int nr_clk);
1202 void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
1203 struct rockchip_pll_clock *pll_list,
1204 unsigned int nr_pll, int grf_lock_offset);
1205 void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
1206 unsigned int lookup_id, const char *name,
1207 const char *const *parent_names, u8 num_parents,
1208 const struct rockchip_cpuclk_reg_data *reg_data,
1209 const struct rockchip_cpuclk_rate_table *rates,
1210 int nrates);
1211 void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
1212 void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
1213 unsigned int reg, void (*cb)(void));
1214
1215 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
1216
1217 struct clk *rockchip_clk_register_halfdiv(const char *name,
1218 const char *const *parent_names,
1219 u8 num_parents, void __iomem *base,
1220 int muxdiv_offset, u8 mux_shift,
1221 u8 mux_width, u8 mux_flags,
1222 u8 div_shift, u8 div_width,
1223 u8 div_flags, int gate_offset,
1224 u8 gate_shift, u8 gate_flags,
1225 unsigned long flags,
1226 spinlock_t *lock);
1227
1228 #ifdef CONFIG_RESET_CONTROLLER
1229 void rockchip_register_softrst_lut(struct device_node *np,
1230 const int *lookup_table,
1231 unsigned int num_regs,
1232 void __iomem *base, u8 flags);
1233 #else
rockchip_register_softrst_lut(struct device_node * np,const int * lookup_table,unsigned int num_regs,void __iomem * base,u8 flags)1234 static inline void rockchip_register_softrst_lut(struct device_node *np,
1235 const int *lookup_table,
1236 unsigned int num_regs,
1237 void __iomem *base, u8 flags)
1238 {
1239 }
1240 #endif
1241
rockchip_register_softrst(struct device_node * np,unsigned int num_regs,void __iomem * base,u8 flags)1242 static inline void rockchip_register_softrst(struct device_node *np,
1243 unsigned int num_regs,
1244 void __iomem *base, u8 flags)
1245 {
1246 return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags);
1247 }
1248
1249 void rk3528_rst_init(struct device_node *np, void __iomem *reg_base);
1250 void rk3562_rst_init(struct device_node *np, void __iomem *reg_base);
1251 void rk3576_rst_init(struct device_node *np, void __iomem *reg_base);
1252 void rk3588_rst_init(struct device_node *np, void __iomem *reg_base);
1253
1254 #endif
1255