1 // SPDX-License-Identifier: GPL-2.0 2 // tscs42xx.c -- TSCS42xx ALSA SoC Audio driver 3 // Copyright 2017 Tempo Semiconductor, Inc. 4 // Author: Steven Eckhoff <steven.eckhoff.opensource@gmail.com> 5 6 #include <linux/kernel.h> 7 #include <linux/device.h> 8 #include <linux/regmap.h> 9 #include <linux/i2c.h> 10 #include <linux/err.h> 11 #include <linux/string.h> 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/mutex.h> 15 #include <linux/cleanup.h> 16 #include <linux/clk.h> 17 #include <sound/tlv.h> 18 #include <sound/pcm_params.h> 19 #include <sound/soc.h> 20 #include <sound/soc-dapm.h> 21 22 #include "tscs42xx.h" 23 24 #define COEFF_SIZE 3 25 #define BIQUAD_COEFF_COUNT 5 26 #define BIQUAD_SIZE (COEFF_SIZE * BIQUAD_COEFF_COUNT) 27 28 #define COEFF_RAM_MAX_ADDR 0xcd 29 #define COEFF_RAM_COEFF_COUNT (COEFF_RAM_MAX_ADDR + 1) 30 #define COEFF_RAM_SIZE (COEFF_SIZE * COEFF_RAM_COEFF_COUNT) 31 32 struct tscs42xx { 33 34 int bclk_ratio; 35 int samplerate; 36 struct mutex audio_params_lock; 37 38 u8 coeff_ram[COEFF_RAM_SIZE]; 39 bool coeff_ram_synced; 40 struct mutex coeff_ram_lock; 41 42 struct mutex pll_lock; 43 44 struct regmap *regmap; 45 46 struct clk *sysclk; 47 int sysclk_src_id; 48 }; 49 50 struct coeff_ram_ctl { 51 unsigned int addr; 52 struct soc_bytes_ext bytes_ext; 53 }; 54 55 static bool tscs42xx_volatile(struct device *dev, unsigned int reg) 56 { 57 switch (reg) { 58 case R_DACCRWRL: 59 case R_DACCRWRM: 60 case R_DACCRWRH: 61 case R_DACCRRDL: 62 case R_DACCRRDM: 63 case R_DACCRRDH: 64 case R_DACCRSTAT: 65 case R_DACCRADDR: 66 case R_PLLCTL0: 67 return true; 68 default: 69 return false; 70 } 71 } 72 73 static bool tscs42xx_precious(struct device *dev, unsigned int reg) 74 { 75 switch (reg) { 76 case R_DACCRWRL: 77 case R_DACCRWRM: 78 case R_DACCRWRH: 79 case R_DACCRRDL: 80 case R_DACCRRDM: 81 case R_DACCRRDH: 82 return true; 83 default: 84 return false; 85 } 86 } 87 88 static const struct regmap_config tscs42xx_regmap = { 89 .reg_bits = 8, 90 .val_bits = 8, 91 92 .volatile_reg = tscs42xx_volatile, 93 .precious_reg = tscs42xx_precious, 94 .max_register = R_DACMBCREL3H, 95 96 .cache_type = REGCACHE_RBTREE, 97 .can_multi_write = true, 98 }; 99 100 #define MAX_PLL_LOCK_20MS_WAITS 1 101 static bool plls_locked(struct snd_soc_component *component) 102 { 103 int ret; 104 int count = MAX_PLL_LOCK_20MS_WAITS; 105 106 do { 107 ret = snd_soc_component_read(component, R_PLLCTL0); 108 if (ret < 0) { 109 dev_err(component->dev, 110 "Failed to read PLL lock status (%d)\n", ret); 111 return false; 112 } else if (ret > 0) { 113 return true; 114 } 115 msleep(20); 116 } while (count--); 117 118 return false; 119 } 120 121 static int sample_rate_to_pll_freq_out(int sample_rate) 122 { 123 switch (sample_rate) { 124 case 11025: 125 case 22050: 126 case 44100: 127 case 88200: 128 return 112896000; 129 case 8000: 130 case 16000: 131 case 32000: 132 case 48000: 133 case 96000: 134 return 122880000; 135 default: 136 return -EINVAL; 137 } 138 } 139 140 #define DACCRSTAT_MAX_TRYS 10 141 static int write_coeff_ram(struct snd_soc_component *component, u8 *coeff_ram, 142 unsigned int addr, unsigned int coeff_cnt) 143 { 144 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 145 int cnt; 146 int trys; 147 int ret; 148 149 for (cnt = 0; cnt < coeff_cnt; cnt++, addr++) { 150 151 for (trys = 0; trys < DACCRSTAT_MAX_TRYS; trys++) { 152 ret = snd_soc_component_read(component, R_DACCRSTAT); 153 if (ret < 0) { 154 dev_err(component->dev, 155 "Failed to read stat (%d)\n", ret); 156 return ret; 157 } 158 if (!ret) 159 break; 160 } 161 162 if (trys == DACCRSTAT_MAX_TRYS) { 163 ret = -EIO; 164 dev_err(component->dev, 165 "dac coefficient write error (%d)\n", ret); 166 return ret; 167 } 168 169 ret = regmap_write(tscs42xx->regmap, R_DACCRADDR, addr); 170 if (ret < 0) { 171 dev_err(component->dev, 172 "Failed to write dac ram address (%d)\n", ret); 173 return ret; 174 } 175 176 ret = regmap_bulk_write(tscs42xx->regmap, R_DACCRWRL, 177 &coeff_ram[addr * COEFF_SIZE], 178 COEFF_SIZE); 179 if (ret < 0) { 180 dev_err(component->dev, 181 "Failed to write dac ram (%d)\n", ret); 182 return ret; 183 } 184 } 185 186 return 0; 187 } 188 189 static int power_up_audio_plls(struct snd_soc_component *component) 190 { 191 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 192 int freq_out; 193 int ret; 194 unsigned int mask; 195 unsigned int val; 196 197 freq_out = sample_rate_to_pll_freq_out(tscs42xx->samplerate); 198 switch (freq_out) { 199 case 122880000: /* 48k */ 200 mask = RM_PLLCTL1C_PDB_PLL1; 201 val = RV_PLLCTL1C_PDB_PLL1_ENABLE; 202 break; 203 case 112896000: /* 44.1k */ 204 mask = RM_PLLCTL1C_PDB_PLL2; 205 val = RV_PLLCTL1C_PDB_PLL2_ENABLE; 206 break; 207 default: 208 ret = -EINVAL; 209 dev_err(component->dev, 210 "Unrecognized PLL output freq (%d)\n", ret); 211 return ret; 212 } 213 214 guard(mutex)(&tscs42xx->pll_lock); 215 216 ret = snd_soc_component_update_bits(component, R_PLLCTL1C, mask, val); 217 if (ret < 0) { 218 dev_err(component->dev, "Failed to turn PLL on (%d)\n", ret); 219 return ret; 220 } 221 222 if (!plls_locked(component)) { 223 dev_err(component->dev, "Failed to lock plls\n"); 224 ret = -ENOMSG; 225 return ret; 226 } 227 228 return 0; 229 } 230 231 static int power_down_audio_plls(struct snd_soc_component *component) 232 { 233 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 234 int ret; 235 236 guard(mutex)(&tscs42xx->pll_lock); 237 238 ret = snd_soc_component_update_bits(component, R_PLLCTL1C, 239 RM_PLLCTL1C_PDB_PLL1, 240 RV_PLLCTL1C_PDB_PLL1_DISABLE); 241 if (ret < 0) { 242 dev_err(component->dev, "Failed to turn PLL off (%d)\n", ret); 243 return ret; 244 } 245 ret = snd_soc_component_update_bits(component, R_PLLCTL1C, 246 RM_PLLCTL1C_PDB_PLL2, 247 RV_PLLCTL1C_PDB_PLL2_DISABLE); 248 if (ret < 0) { 249 dev_err(component->dev, "Failed to turn PLL off (%d)\n", ret); 250 return ret; 251 } 252 253 return 0; 254 } 255 256 static int coeff_ram_get(struct snd_kcontrol *kcontrol, 257 struct snd_ctl_elem_value *ucontrol) 258 { 259 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 260 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 261 struct coeff_ram_ctl *ctl = 262 (struct coeff_ram_ctl *)kcontrol->private_value; 263 struct soc_bytes_ext *params = &ctl->bytes_ext; 264 265 guard(mutex)(&tscs42xx->coeff_ram_lock); 266 267 memcpy(ucontrol->value.bytes.data, 268 &tscs42xx->coeff_ram[ctl->addr * COEFF_SIZE], params->max); 269 270 return 0; 271 } 272 273 static int coeff_ram_put(struct snd_kcontrol *kcontrol, 274 struct snd_ctl_elem_value *ucontrol) 275 { 276 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 277 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 278 struct coeff_ram_ctl *ctl = 279 (struct coeff_ram_ctl *)kcontrol->private_value; 280 struct soc_bytes_ext *params = &ctl->bytes_ext; 281 unsigned int coeff_cnt = params->max / COEFF_SIZE; 282 int ret; 283 284 guard(mutex)(&tscs42xx->coeff_ram_lock); 285 286 tscs42xx->coeff_ram_synced = false; 287 288 memcpy(&tscs42xx->coeff_ram[ctl->addr * COEFF_SIZE], 289 ucontrol->value.bytes.data, params->max); 290 291 guard(mutex)(&tscs42xx->pll_lock); 292 293 if (plls_locked(component)) { 294 ret = write_coeff_ram(component, tscs42xx->coeff_ram, 295 ctl->addr, coeff_cnt); 296 if (ret < 0) { 297 dev_err(component->dev, 298 "Failed to flush coeff ram cache (%d)\n", ret); 299 return ret; 300 } 301 tscs42xx->coeff_ram_synced = true; 302 } 303 304 return 0; 305 } 306 307 /* Input L Capture Route */ 308 static char const * const input_select_text[] = { 309 "Line 1", "Line 2", "Line 3", "D2S" 310 }; 311 312 static const struct soc_enum left_input_select_enum = 313 SOC_ENUM_SINGLE(R_INSELL, FB_INSELL, ARRAY_SIZE(input_select_text), 314 input_select_text); 315 316 static const struct snd_kcontrol_new left_input_select = 317 SOC_DAPM_ENUM("LEFT_INPUT_SELECT_ENUM", left_input_select_enum); 318 319 /* Input R Capture Route */ 320 static const struct soc_enum right_input_select_enum = 321 SOC_ENUM_SINGLE(R_INSELR, FB_INSELR, ARRAY_SIZE(input_select_text), 322 input_select_text); 323 324 static const struct snd_kcontrol_new right_input_select = 325 SOC_DAPM_ENUM("RIGHT_INPUT_SELECT_ENUM", right_input_select_enum); 326 327 /* Input Channel Mapping */ 328 static char const * const ch_map_select_text[] = { 329 "Normal", "Left to Right", "Right to Left", "Swap" 330 }; 331 332 static const struct soc_enum ch_map_select_enum = 333 SOC_ENUM_SINGLE(R_AIC2, FB_AIC2_ADCDSEL, ARRAY_SIZE(ch_map_select_text), 334 ch_map_select_text); 335 336 static int dapm_vref_event(struct snd_soc_dapm_widget *w, 337 struct snd_kcontrol *kcontrol, int event) 338 { 339 msleep(20); 340 return 0; 341 } 342 343 static int dapm_micb_event(struct snd_soc_dapm_widget *w, 344 struct snd_kcontrol *kcontrol, int event) 345 { 346 msleep(20); 347 return 0; 348 } 349 350 static int pll_event(struct snd_soc_dapm_widget *w, 351 struct snd_kcontrol *kcontrol, int event) 352 { 353 struct snd_soc_component *component = 354 snd_soc_dapm_to_component(w->dapm); 355 int ret; 356 357 if (SND_SOC_DAPM_EVENT_ON(event)) 358 ret = power_up_audio_plls(component); 359 else 360 ret = power_down_audio_plls(component); 361 362 return ret; 363 } 364 365 static int dac_event(struct snd_soc_dapm_widget *w, 366 struct snd_kcontrol *kcontrol, int event) 367 { 368 struct snd_soc_component *component = 369 snd_soc_dapm_to_component(w->dapm); 370 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 371 int ret; 372 373 guard(mutex)(&tscs42xx->coeff_ram_lock); 374 375 if (!tscs42xx->coeff_ram_synced) { 376 ret = write_coeff_ram(component, tscs42xx->coeff_ram, 0x00, 377 COEFF_RAM_COEFF_COUNT); 378 if (ret < 0) 379 return ret; 380 tscs42xx->coeff_ram_synced = true; 381 } 382 383 return 0; 384 } 385 386 static const struct snd_soc_dapm_widget tscs42xx_dapm_widgets[] = { 387 /* Vref */ 388 SND_SOC_DAPM_SUPPLY_S("Vref", 1, R_PWRM2, FB_PWRM2_VREF, 0, 389 dapm_vref_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 390 391 /* PLL */ 392 SND_SOC_DAPM_SUPPLY("PLL", SND_SOC_NOPM, 0, 0, pll_event, 393 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 394 395 /* Headphone */ 396 SND_SOC_DAPM_DAC_E("DAC L", "HiFi Playback", R_PWRM2, FB_PWRM2_HPL, 0, 397 dac_event, SND_SOC_DAPM_POST_PMU), 398 SND_SOC_DAPM_DAC_E("DAC R", "HiFi Playback", R_PWRM2, FB_PWRM2_HPR, 0, 399 dac_event, SND_SOC_DAPM_POST_PMU), 400 SND_SOC_DAPM_OUTPUT("Headphone L"), 401 SND_SOC_DAPM_OUTPUT("Headphone R"), 402 403 /* Speaker */ 404 SND_SOC_DAPM_DAC_E("ClassD L", "HiFi Playback", 405 R_PWRM2, FB_PWRM2_SPKL, 0, 406 dac_event, SND_SOC_DAPM_POST_PMU), 407 SND_SOC_DAPM_DAC_E("ClassD R", "HiFi Playback", 408 R_PWRM2, FB_PWRM2_SPKR, 0, 409 dac_event, SND_SOC_DAPM_POST_PMU), 410 SND_SOC_DAPM_OUTPUT("Speaker L"), 411 SND_SOC_DAPM_OUTPUT("Speaker R"), 412 413 /* Capture */ 414 SND_SOC_DAPM_PGA("Analog In PGA L", R_PWRM1, FB_PWRM1_PGAL, 0, NULL, 0), 415 SND_SOC_DAPM_PGA("Analog In PGA R", R_PWRM1, FB_PWRM1_PGAR, 0, NULL, 0), 416 SND_SOC_DAPM_PGA("Analog Boost L", R_PWRM1, FB_PWRM1_BSTL, 0, NULL, 0), 417 SND_SOC_DAPM_PGA("Analog Boost R", R_PWRM1, FB_PWRM1_BSTR, 0, NULL, 0), 418 SND_SOC_DAPM_PGA("ADC Mute", R_CNVRTR0, FB_CNVRTR0_HPOR, true, NULL, 0), 419 SND_SOC_DAPM_ADC("ADC L", "HiFi Capture", R_PWRM1, FB_PWRM1_ADCL, 0), 420 SND_SOC_DAPM_ADC("ADC R", "HiFi Capture", R_PWRM1, FB_PWRM1_ADCR, 0), 421 422 /* Capture Input */ 423 SND_SOC_DAPM_MUX("Input L Capture Route", R_PWRM2, 424 FB_PWRM2_INSELL, 0, &left_input_select), 425 SND_SOC_DAPM_MUX("Input R Capture Route", R_PWRM2, 426 FB_PWRM2_INSELR, 0, &right_input_select), 427 428 /* Digital Mic */ 429 SND_SOC_DAPM_SUPPLY_S("Digital Mic Enable", 2, R_DMICCTL, 430 FB_DMICCTL_DMICEN, 0, NULL, 431 SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 432 433 /* Analog Mic */ 434 SND_SOC_DAPM_SUPPLY_S("Mic Bias", 2, R_PWRM1, FB_PWRM1_MICB, 435 0, dapm_micb_event, SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_PRE_PMD), 436 437 /* Line In */ 438 SND_SOC_DAPM_INPUT("Line In 1 L"), 439 SND_SOC_DAPM_INPUT("Line In 1 R"), 440 SND_SOC_DAPM_INPUT("Line In 2 L"), 441 SND_SOC_DAPM_INPUT("Line In 2 R"), 442 SND_SOC_DAPM_INPUT("Line In 3 L"), 443 SND_SOC_DAPM_INPUT("Line In 3 R"), 444 }; 445 446 static const struct snd_soc_dapm_route tscs42xx_intercon[] = { 447 {"DAC L", NULL, "PLL"}, 448 {"DAC R", NULL, "PLL"}, 449 {"DAC L", NULL, "Vref"}, 450 {"DAC R", NULL, "Vref"}, 451 {"Headphone L", NULL, "DAC L"}, 452 {"Headphone R", NULL, "DAC R"}, 453 454 {"ClassD L", NULL, "PLL"}, 455 {"ClassD R", NULL, "PLL"}, 456 {"ClassD L", NULL, "Vref"}, 457 {"ClassD R", NULL, "Vref"}, 458 {"Speaker L", NULL, "ClassD L"}, 459 {"Speaker R", NULL, "ClassD R"}, 460 461 {"Input L Capture Route", NULL, "Vref"}, 462 {"Input R Capture Route", NULL, "Vref"}, 463 464 {"Mic Bias", NULL, "Vref"}, 465 466 {"Input L Capture Route", "Line 1", "Line In 1 L"}, 467 {"Input R Capture Route", "Line 1", "Line In 1 R"}, 468 {"Input L Capture Route", "Line 2", "Line In 2 L"}, 469 {"Input R Capture Route", "Line 2", "Line In 2 R"}, 470 {"Input L Capture Route", "Line 3", "Line In 3 L"}, 471 {"Input R Capture Route", "Line 3", "Line In 3 R"}, 472 473 {"Analog In PGA L", NULL, "Input L Capture Route"}, 474 {"Analog In PGA R", NULL, "Input R Capture Route"}, 475 {"Analog Boost L", NULL, "Analog In PGA L"}, 476 {"Analog Boost R", NULL, "Analog In PGA R"}, 477 {"ADC Mute", NULL, "Analog Boost L"}, 478 {"ADC Mute", NULL, "Analog Boost R"}, 479 {"ADC L", NULL, "PLL"}, 480 {"ADC R", NULL, "PLL"}, 481 {"ADC L", NULL, "ADC Mute"}, 482 {"ADC R", NULL, "ADC Mute"}, 483 }; 484 485 /************ 486 * CONTROLS * 487 ************/ 488 489 static char const * const eq_band_enable_text[] = { 490 "Prescale only", 491 "Band1", 492 "Band1:2", 493 "Band1:3", 494 "Band1:4", 495 "Band1:5", 496 "Band1:6", 497 }; 498 499 static char const * const level_detection_text[] = { 500 "Average", 501 "Peak", 502 }; 503 504 static char const * const level_detection_window_text[] = { 505 "512 Samples", 506 "64 Samples", 507 }; 508 509 static char const * const compressor_ratio_text[] = { 510 "Reserved", "1.5:1", "2:1", "3:1", "4:1", "5:1", "6:1", 511 "7:1", "8:1", "9:1", "10:1", "11:1", "12:1", "13:1", "14:1", 512 "15:1", "16:1", "17:1", "18:1", "19:1", "20:1", 513 }; 514 515 static DECLARE_TLV_DB_SCALE(hpvol_scale, -8850, 75, 0); 516 static DECLARE_TLV_DB_SCALE(spkvol_scale, -7725, 75, 0); 517 static DECLARE_TLV_DB_SCALE(dacvol_scale, -9563, 38, 0); 518 static DECLARE_TLV_DB_SCALE(adcvol_scale, -7125, 38, 0); 519 static DECLARE_TLV_DB_SCALE(invol_scale, -1725, 75, 0); 520 static DECLARE_TLV_DB_SCALE(mic_boost_scale, 0, 1000, 0); 521 static DECLARE_TLV_DB_MINMAX(mugain_scale, 0, 4650); 522 static DECLARE_TLV_DB_MINMAX(compth_scale, -9562, 0); 523 524 static const struct soc_enum eq1_band_enable_enum = 525 SOC_ENUM_SINGLE(R_CONFIG1, FB_CONFIG1_EQ1_BE, 526 ARRAY_SIZE(eq_band_enable_text), eq_band_enable_text); 527 528 static const struct soc_enum eq2_band_enable_enum = 529 SOC_ENUM_SINGLE(R_CONFIG1, FB_CONFIG1_EQ2_BE, 530 ARRAY_SIZE(eq_band_enable_text), eq_band_enable_text); 531 532 static const struct soc_enum cle_level_detection_enum = 533 SOC_ENUM_SINGLE(R_CLECTL, FB_CLECTL_LVL_MODE, 534 ARRAY_SIZE(level_detection_text), 535 level_detection_text); 536 537 static const struct soc_enum cle_level_detection_window_enum = 538 SOC_ENUM_SINGLE(R_CLECTL, FB_CLECTL_WINDOWSEL, 539 ARRAY_SIZE(level_detection_window_text), 540 level_detection_window_text); 541 542 static const struct soc_enum mbc_level_detection_enums[] = { 543 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE1, 544 ARRAY_SIZE(level_detection_text), 545 level_detection_text), 546 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE2, 547 ARRAY_SIZE(level_detection_text), 548 level_detection_text), 549 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_LVLMODE3, 550 ARRAY_SIZE(level_detection_text), 551 level_detection_text), 552 }; 553 554 static const struct soc_enum mbc_level_detection_window_enums[] = { 555 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL1, 556 ARRAY_SIZE(level_detection_window_text), 557 level_detection_window_text), 558 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL2, 559 ARRAY_SIZE(level_detection_window_text), 560 level_detection_window_text), 561 SOC_ENUM_SINGLE(R_DACMBCCTL, FB_DACMBCCTL_WINSEL3, 562 ARRAY_SIZE(level_detection_window_text), 563 level_detection_window_text), 564 }; 565 566 static const struct soc_enum compressor_ratio_enum = 567 SOC_ENUM_SINGLE(R_CMPRAT, FB_CMPRAT, 568 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 569 570 static const struct soc_enum dac_mbc1_compressor_ratio_enum = 571 SOC_ENUM_SINGLE(R_DACMBCRAT1, FB_DACMBCRAT1_RATIO, 572 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 573 574 static const struct soc_enum dac_mbc2_compressor_ratio_enum = 575 SOC_ENUM_SINGLE(R_DACMBCRAT2, FB_DACMBCRAT2_RATIO, 576 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 577 578 static const struct soc_enum dac_mbc3_compressor_ratio_enum = 579 SOC_ENUM_SINGLE(R_DACMBCRAT3, FB_DACMBCRAT3_RATIO, 580 ARRAY_SIZE(compressor_ratio_text), compressor_ratio_text); 581 582 static int bytes_info_ext(struct snd_kcontrol *kcontrol, 583 struct snd_ctl_elem_info *ucontrol) 584 { 585 struct coeff_ram_ctl *ctl = 586 (struct coeff_ram_ctl *)kcontrol->private_value; 587 struct soc_bytes_ext *params = &ctl->bytes_ext; 588 589 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; 590 ucontrol->count = params->max; 591 592 return 0; 593 } 594 595 #define COEFF_RAM_CTL(xname, xcount, xaddr) \ 596 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 597 .info = bytes_info_ext, \ 598 .get = coeff_ram_get, .put = coeff_ram_put, \ 599 .private_value = (unsigned long)&(struct coeff_ram_ctl) { \ 600 .addr = xaddr, \ 601 .bytes_ext = {.max = xcount, }, \ 602 } \ 603 } 604 605 static const struct snd_kcontrol_new tscs42xx_snd_controls[] = { 606 /* Volumes */ 607 SOC_DOUBLE_R_TLV("Headphone Volume", R_HPVOLL, R_HPVOLR, 608 FB_HPVOLL, 0x7F, 0, hpvol_scale), 609 SOC_DOUBLE_R_TLV("Speaker Volume", R_SPKVOLL, R_SPKVOLR, 610 FB_SPKVOLL, 0x7F, 0, spkvol_scale), 611 SOC_DOUBLE_R_TLV("Master Volume", R_DACVOLL, R_DACVOLR, 612 FB_DACVOLL, 0xFF, 0, dacvol_scale), 613 SOC_DOUBLE_R_TLV("PCM Volume", R_ADCVOLL, R_ADCVOLR, 614 FB_ADCVOLL, 0xFF, 0, adcvol_scale), 615 SOC_DOUBLE_R_TLV("Input Volume", R_INVOLL, R_INVOLR, 616 FB_INVOLL, 0x3F, 0, invol_scale), 617 618 /* INSEL */ 619 SOC_DOUBLE_R_TLV("Mic Boost Volume", R_INSELL, R_INSELR, 620 FB_INSELL_MICBSTL, FV_INSELL_MICBSTL_30DB, 621 0, mic_boost_scale), 622 623 /* Input Channel Map */ 624 SOC_ENUM("Input Channel Map", ch_map_select_enum), 625 626 /* Mic Bias */ 627 SOC_SINGLE("Mic Bias Boost Switch", 0x71, 0x07, 1, 0), 628 629 /* Headphone Auto Switching */ 630 SOC_SINGLE("Headphone Auto Switching Switch", 631 R_CTL, FB_CTL_HPSWEN, 1, 0), 632 SOC_SINGLE("Headphone Detect Polarity Toggle Switch", 633 R_CTL, FB_CTL_HPSWPOL, 1, 0), 634 635 /* Coefficient Ram */ 636 COEFF_RAM_CTL("Cascade1L BiQuad1", BIQUAD_SIZE, 0x00), 637 COEFF_RAM_CTL("Cascade1L BiQuad2", BIQUAD_SIZE, 0x05), 638 COEFF_RAM_CTL("Cascade1L BiQuad3", BIQUAD_SIZE, 0x0a), 639 COEFF_RAM_CTL("Cascade1L BiQuad4", BIQUAD_SIZE, 0x0f), 640 COEFF_RAM_CTL("Cascade1L BiQuad5", BIQUAD_SIZE, 0x14), 641 COEFF_RAM_CTL("Cascade1L BiQuad6", BIQUAD_SIZE, 0x19), 642 643 COEFF_RAM_CTL("Cascade1R BiQuad1", BIQUAD_SIZE, 0x20), 644 COEFF_RAM_CTL("Cascade1R BiQuad2", BIQUAD_SIZE, 0x25), 645 COEFF_RAM_CTL("Cascade1R BiQuad3", BIQUAD_SIZE, 0x2a), 646 COEFF_RAM_CTL("Cascade1R BiQuad4", BIQUAD_SIZE, 0x2f), 647 COEFF_RAM_CTL("Cascade1R BiQuad5", BIQUAD_SIZE, 0x34), 648 COEFF_RAM_CTL("Cascade1R BiQuad6", BIQUAD_SIZE, 0x39), 649 650 COEFF_RAM_CTL("Cascade1L Prescale", COEFF_SIZE, 0x1f), 651 COEFF_RAM_CTL("Cascade1R Prescale", COEFF_SIZE, 0x3f), 652 653 COEFF_RAM_CTL("Cascade2L BiQuad1", BIQUAD_SIZE, 0x40), 654 COEFF_RAM_CTL("Cascade2L BiQuad2", BIQUAD_SIZE, 0x45), 655 COEFF_RAM_CTL("Cascade2L BiQuad3", BIQUAD_SIZE, 0x4a), 656 COEFF_RAM_CTL("Cascade2L BiQuad4", BIQUAD_SIZE, 0x4f), 657 COEFF_RAM_CTL("Cascade2L BiQuad5", BIQUAD_SIZE, 0x54), 658 COEFF_RAM_CTL("Cascade2L BiQuad6", BIQUAD_SIZE, 0x59), 659 660 COEFF_RAM_CTL("Cascade2R BiQuad1", BIQUAD_SIZE, 0x60), 661 COEFF_RAM_CTL("Cascade2R BiQuad2", BIQUAD_SIZE, 0x65), 662 COEFF_RAM_CTL("Cascade2R BiQuad3", BIQUAD_SIZE, 0x6a), 663 COEFF_RAM_CTL("Cascade2R BiQuad4", BIQUAD_SIZE, 0x6f), 664 COEFF_RAM_CTL("Cascade2R BiQuad5", BIQUAD_SIZE, 0x74), 665 COEFF_RAM_CTL("Cascade2R BiQuad6", BIQUAD_SIZE, 0x79), 666 667 COEFF_RAM_CTL("Cascade2L Prescale", COEFF_SIZE, 0x5f), 668 COEFF_RAM_CTL("Cascade2R Prescale", COEFF_SIZE, 0x7f), 669 670 COEFF_RAM_CTL("Bass Extraction BiQuad1", BIQUAD_SIZE, 0x80), 671 COEFF_RAM_CTL("Bass Extraction BiQuad2", BIQUAD_SIZE, 0x85), 672 673 COEFF_RAM_CTL("Bass Non Linear Function 1", COEFF_SIZE, 0x8a), 674 COEFF_RAM_CTL("Bass Non Linear Function 2", COEFF_SIZE, 0x8b), 675 676 COEFF_RAM_CTL("Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c), 677 678 COEFF_RAM_CTL("Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91), 679 680 COEFF_RAM_CTL("Bass Mix", COEFF_SIZE, 0x96), 681 682 COEFF_RAM_CTL("Treb Extraction BiQuad1", BIQUAD_SIZE, 0x97), 683 COEFF_RAM_CTL("Treb Extraction BiQuad2", BIQUAD_SIZE, 0x9c), 684 685 COEFF_RAM_CTL("Treb Non Linear Function 1", COEFF_SIZE, 0xa1), 686 COEFF_RAM_CTL("Treb Non Linear Function 2", COEFF_SIZE, 0xa2), 687 688 COEFF_RAM_CTL("Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3), 689 690 COEFF_RAM_CTL("Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8), 691 692 COEFF_RAM_CTL("Treb Mix", COEFF_SIZE, 0xad), 693 694 COEFF_RAM_CTL("3D", COEFF_SIZE, 0xae), 695 696 COEFF_RAM_CTL("3D Mix", COEFF_SIZE, 0xaf), 697 698 COEFF_RAM_CTL("MBC1 BiQuad1", BIQUAD_SIZE, 0xb0), 699 COEFF_RAM_CTL("MBC1 BiQuad2", BIQUAD_SIZE, 0xb5), 700 701 COEFF_RAM_CTL("MBC2 BiQuad1", BIQUAD_SIZE, 0xba), 702 COEFF_RAM_CTL("MBC2 BiQuad2", BIQUAD_SIZE, 0xbf), 703 704 COEFF_RAM_CTL("MBC3 BiQuad1", BIQUAD_SIZE, 0xc4), 705 COEFF_RAM_CTL("MBC3 BiQuad2", BIQUAD_SIZE, 0xc9), 706 707 /* EQ */ 708 SOC_SINGLE("EQ1 Switch", R_CONFIG1, FB_CONFIG1_EQ1_EN, 1, 0), 709 SOC_SINGLE("EQ2 Switch", R_CONFIG1, FB_CONFIG1_EQ2_EN, 1, 0), 710 SOC_ENUM("EQ1 Band Enable", eq1_band_enable_enum), 711 SOC_ENUM("EQ2 Band Enable", eq2_band_enable_enum), 712 713 /* CLE */ 714 SOC_ENUM("CLE Level Detect", 715 cle_level_detection_enum), 716 SOC_ENUM("CLE Level Detect Win", 717 cle_level_detection_window_enum), 718 SOC_SINGLE("Expander Switch", 719 R_CLECTL, FB_CLECTL_EXP_EN, 1, 0), 720 SOC_SINGLE("Limiter Switch", 721 R_CLECTL, FB_CLECTL_LIMIT_EN, 1, 0), 722 SOC_SINGLE("Comp Switch", 723 R_CLECTL, FB_CLECTL_COMP_EN, 1, 0), 724 SOC_SINGLE_TLV("CLE Make-Up Gain Volume", 725 R_MUGAIN, FB_MUGAIN_CLEMUG, 0x1f, 0, mugain_scale), 726 SOC_SINGLE_TLV("Comp Thresh Volume", 727 R_COMPTH, FB_COMPTH, 0xff, 0, compth_scale), 728 SOC_ENUM("Comp Ratio", compressor_ratio_enum), 729 SND_SOC_BYTES("Comp Atk Time", R_CATKTCL, 2), 730 731 /* Effects */ 732 SOC_SINGLE("3D Switch", R_FXCTL, FB_FXCTL_3DEN, 1, 0), 733 SOC_SINGLE("Treble Switch", R_FXCTL, FB_FXCTL_TEEN, 1, 0), 734 SOC_SINGLE("Treble Bypass Switch", R_FXCTL, FB_FXCTL_TNLFBYPASS, 1, 0), 735 SOC_SINGLE("Bass Switch", R_FXCTL, FB_FXCTL_BEEN, 1, 0), 736 SOC_SINGLE("Bass Bypass Switch", R_FXCTL, FB_FXCTL_BNLFBYPASS, 1, 0), 737 738 /* MBC */ 739 SOC_SINGLE("MBC Band1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0), 740 SOC_SINGLE("MBC Band2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0), 741 SOC_SINGLE("MBC Band3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0), 742 SOC_ENUM("MBC Band1 Level Detect", 743 mbc_level_detection_enums[0]), 744 SOC_ENUM("MBC Band2 Level Detect", 745 mbc_level_detection_enums[1]), 746 SOC_ENUM("MBC Band3 Level Detect", 747 mbc_level_detection_enums[2]), 748 SOC_ENUM("MBC Band1 Level Detect Win", 749 mbc_level_detection_window_enums[0]), 750 SOC_ENUM("MBC Band2 Level Detect Win", 751 mbc_level_detection_window_enums[1]), 752 SOC_ENUM("MBC Band3 Level Detect Win", 753 mbc_level_detection_window_enums[2]), 754 755 SOC_SINGLE("MBC1 Phase Invert Switch", 756 R_DACMBCMUG1, FB_DACMBCMUG1_PHASE, 1, 0), 757 SOC_SINGLE_TLV("DAC MBC1 Make-Up Gain Volume", 758 R_DACMBCMUG1, FB_DACMBCMUG1_MUGAIN, 0x1f, 0, mugain_scale), 759 SOC_SINGLE_TLV("DAC MBC1 Comp Thresh Volume", 760 R_DACMBCTHR1, FB_DACMBCTHR1_THRESH, 0xff, 0, compth_scale), 761 SOC_ENUM("DAC MBC1 Comp Ratio", 762 dac_mbc1_compressor_ratio_enum), 763 SND_SOC_BYTES("DAC MBC1 Comp Atk Time", R_DACMBCATK1L, 2), 764 SND_SOC_BYTES("DAC MBC1 Comp Rel Time Const", 765 R_DACMBCREL1L, 2), 766 767 SOC_SINGLE("MBC2 Phase Invert Switch", 768 R_DACMBCMUG2, FB_DACMBCMUG2_PHASE, 1, 0), 769 SOC_SINGLE_TLV("DAC MBC2 Make-Up Gain Volume", 770 R_DACMBCMUG2, FB_DACMBCMUG2_MUGAIN, 0x1f, 0, mugain_scale), 771 SOC_SINGLE_TLV("DAC MBC2 Comp Thresh Volume", 772 R_DACMBCTHR2, FB_DACMBCTHR2_THRESH, 0xff, 0, compth_scale), 773 SOC_ENUM("DAC MBC2 Comp Ratio", 774 dac_mbc2_compressor_ratio_enum), 775 SND_SOC_BYTES("DAC MBC2 Comp Atk Time", R_DACMBCATK2L, 2), 776 SND_SOC_BYTES("DAC MBC2 Comp Rel Time Const", 777 R_DACMBCREL2L, 2), 778 779 SOC_SINGLE("MBC3 Phase Invert Switch", 780 R_DACMBCMUG3, FB_DACMBCMUG3_PHASE, 1, 0), 781 SOC_SINGLE_TLV("DAC MBC3 Make-Up Gain Volume", 782 R_DACMBCMUG3, FB_DACMBCMUG3_MUGAIN, 0x1f, 0, mugain_scale), 783 SOC_SINGLE_TLV("DAC MBC3 Comp Thresh Volume", 784 R_DACMBCTHR3, FB_DACMBCTHR3_THRESH, 0xff, 0, compth_scale), 785 SOC_ENUM("DAC MBC3 Comp Ratio", 786 dac_mbc3_compressor_ratio_enum), 787 SND_SOC_BYTES("DAC MBC3 Comp Atk Time", R_DACMBCATK3L, 2), 788 SND_SOC_BYTES("DAC MBC3 Comp Rel Time Const", 789 R_DACMBCREL3L, 2), 790 }; 791 792 static int setup_sample_format(struct snd_soc_component *component, 793 snd_pcm_format_t format) 794 { 795 unsigned int width; 796 int ret; 797 798 switch (format) { 799 case SNDRV_PCM_FORMAT_S16_LE: 800 width = RV_AIC1_WL_16; 801 break; 802 case SNDRV_PCM_FORMAT_S20_3LE: 803 width = RV_AIC1_WL_20; 804 break; 805 case SNDRV_PCM_FORMAT_S24_LE: 806 width = RV_AIC1_WL_24; 807 break; 808 case SNDRV_PCM_FORMAT_S32_LE: 809 width = RV_AIC1_WL_32; 810 break; 811 default: 812 ret = -EINVAL; 813 dev_err(component->dev, "Unsupported format width (%d)\n", ret); 814 return ret; 815 } 816 ret = snd_soc_component_update_bits(component, 817 R_AIC1, RM_AIC1_WL, width); 818 if (ret < 0) { 819 dev_err(component->dev, 820 "Failed to set sample width (%d)\n", ret); 821 return ret; 822 } 823 824 return 0; 825 } 826 827 static int setup_sample_rate(struct snd_soc_component *component, 828 unsigned int rate) 829 { 830 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 831 unsigned int br, bm; 832 int ret; 833 834 switch (rate) { 835 case 8000: 836 br = RV_DACSR_DBR_32; 837 bm = RV_DACSR_DBM_PT25; 838 break; 839 case 16000: 840 br = RV_DACSR_DBR_32; 841 bm = RV_DACSR_DBM_PT5; 842 break; 843 case 24000: 844 br = RV_DACSR_DBR_48; 845 bm = RV_DACSR_DBM_PT5; 846 break; 847 case 32000: 848 br = RV_DACSR_DBR_32; 849 bm = RV_DACSR_DBM_1; 850 break; 851 case 48000: 852 br = RV_DACSR_DBR_48; 853 bm = RV_DACSR_DBM_1; 854 break; 855 case 96000: 856 br = RV_DACSR_DBR_48; 857 bm = RV_DACSR_DBM_2; 858 break; 859 case 11025: 860 br = RV_DACSR_DBR_44_1; 861 bm = RV_DACSR_DBM_PT25; 862 break; 863 case 22050: 864 br = RV_DACSR_DBR_44_1; 865 bm = RV_DACSR_DBM_PT5; 866 break; 867 case 44100: 868 br = RV_DACSR_DBR_44_1; 869 bm = RV_DACSR_DBM_1; 870 break; 871 case 88200: 872 br = RV_DACSR_DBR_44_1; 873 bm = RV_DACSR_DBM_2; 874 break; 875 default: 876 dev_err(component->dev, "Unsupported sample rate %d\n", rate); 877 return -EINVAL; 878 } 879 880 /* DAC and ADC share bit and frame clock */ 881 ret = snd_soc_component_update_bits(component, 882 R_DACSR, RM_DACSR_DBR, br); 883 if (ret < 0) { 884 dev_err(component->dev, 885 "Failed to update register (%d)\n", ret); 886 return ret; 887 } 888 ret = snd_soc_component_update_bits(component, 889 R_DACSR, RM_DACSR_DBM, bm); 890 if (ret < 0) { 891 dev_err(component->dev, 892 "Failed to update register (%d)\n", ret); 893 return ret; 894 } 895 ret = snd_soc_component_update_bits(component, 896 R_ADCSR, RM_DACSR_DBR, br); 897 if (ret < 0) { 898 dev_err(component->dev, 899 "Failed to update register (%d)\n", ret); 900 return ret; 901 } 902 ret = snd_soc_component_update_bits(component, 903 R_ADCSR, RM_DACSR_DBM, bm); 904 if (ret < 0) { 905 dev_err(component->dev, 906 "Failed to update register (%d)\n", ret); 907 return ret; 908 } 909 910 guard(mutex)(&tscs42xx->audio_params_lock); 911 912 tscs42xx->samplerate = rate; 913 914 return 0; 915 } 916 917 struct reg_setting { 918 unsigned int addr; 919 unsigned int val; 920 unsigned int mask; 921 }; 922 923 #define PLL_REG_SETTINGS_COUNT 13 924 struct pll_ctl { 925 int input_freq; 926 struct reg_setting settings[PLL_REG_SETTINGS_COUNT]; 927 }; 928 929 #define PLL_CTL(f, rt, rd, r1b_l, r9, ra, rb, \ 930 rc, r12, r1b_h, re, rf, r10, r11) \ 931 { \ 932 .input_freq = f, \ 933 .settings = { \ 934 {R_TIMEBASE, rt, 0xFF}, \ 935 {R_PLLCTLD, rd, 0xFF}, \ 936 {R_PLLCTL1B, r1b_l, 0x0F}, \ 937 {R_PLLCTL9, r9, 0xFF}, \ 938 {R_PLLCTLA, ra, 0xFF}, \ 939 {R_PLLCTLB, rb, 0xFF}, \ 940 {R_PLLCTLC, rc, 0xFF}, \ 941 {R_PLLCTL12, r12, 0xFF}, \ 942 {R_PLLCTL1B, r1b_h, 0xF0}, \ 943 {R_PLLCTLE, re, 0xFF}, \ 944 {R_PLLCTLF, rf, 0xFF}, \ 945 {R_PLLCTL10, r10, 0xFF}, \ 946 {R_PLLCTL11, r11, 0xFF}, \ 947 }, \ 948 } 949 950 static const struct pll_ctl pll_ctls[] = { 951 PLL_CTL(1411200, 0x05, 952 0x39, 0x04, 0x07, 0x02, 0xC3, 0x04, 953 0x1B, 0x10, 0x03, 0x03, 0xD0, 0x02), 954 PLL_CTL(1536000, 0x05, 955 0x1A, 0x04, 0x02, 0x03, 0xE0, 0x01, 956 0x1A, 0x10, 0x02, 0x03, 0xB9, 0x01), 957 PLL_CTL(2822400, 0x0A, 958 0x23, 0x04, 0x07, 0x04, 0xC3, 0x04, 959 0x22, 0x10, 0x05, 0x03, 0x58, 0x02), 960 PLL_CTL(3072000, 0x0B, 961 0x22, 0x04, 0x07, 0x03, 0x48, 0x03, 962 0x1A, 0x10, 0x04, 0x03, 0xB9, 0x01), 963 PLL_CTL(5644800, 0x15, 964 0x23, 0x04, 0x0E, 0x04, 0xC3, 0x04, 965 0x1A, 0x10, 0x08, 0x03, 0xE0, 0x01), 966 PLL_CTL(6144000, 0x17, 967 0x1A, 0x04, 0x08, 0x03, 0xE0, 0x01, 968 0x1A, 0x10, 0x08, 0x03, 0xB9, 0x01), 969 PLL_CTL(12000000, 0x2E, 970 0x1B, 0x04, 0x19, 0x03, 0x00, 0x03, 971 0x2A, 0x10, 0x19, 0x05, 0x98, 0x04), 972 PLL_CTL(19200000, 0x4A, 973 0x13, 0x04, 0x14, 0x03, 0x80, 0x01, 974 0x1A, 0x10, 0x19, 0x03, 0xB9, 0x01), 975 PLL_CTL(22000000, 0x55, 976 0x2A, 0x04, 0x37, 0x05, 0x00, 0x06, 977 0x22, 0x10, 0x26, 0x03, 0x49, 0x02), 978 PLL_CTL(22579200, 0x57, 979 0x22, 0x04, 0x31, 0x03, 0x20, 0x03, 980 0x1A, 0x10, 0x1D, 0x03, 0xB3, 0x01), 981 PLL_CTL(24000000, 0x5D, 982 0x13, 0x04, 0x19, 0x03, 0x80, 0x01, 983 0x1B, 0x10, 0x19, 0x05, 0x4C, 0x02), 984 PLL_CTL(24576000, 0x5F, 985 0x13, 0x04, 0x1D, 0x03, 0xB3, 0x01, 986 0x22, 0x10, 0x40, 0x03, 0x72, 0x03), 987 PLL_CTL(27000000, 0x68, 988 0x22, 0x04, 0x4B, 0x03, 0x00, 0x04, 989 0x2A, 0x10, 0x7D, 0x03, 0x20, 0x06), 990 PLL_CTL(36000000, 0x8C, 991 0x1B, 0x04, 0x4B, 0x03, 0x00, 0x03, 992 0x2A, 0x10, 0x7D, 0x03, 0x98, 0x04), 993 PLL_CTL(25000000, 0x61, 994 0x1B, 0x04, 0x37, 0x03, 0x2B, 0x03, 995 0x1A, 0x10, 0x2A, 0x03, 0x39, 0x02), 996 PLL_CTL(26000000, 0x65, 997 0x23, 0x04, 0x41, 0x05, 0x00, 0x06, 998 0x1A, 0x10, 0x26, 0x03, 0xEF, 0x01), 999 PLL_CTL(12288000, 0x2F, 1000 0x1A, 0x04, 0x12, 0x03, 0x1C, 0x02, 1001 0x22, 0x10, 0x20, 0x03, 0x72, 0x03), 1002 PLL_CTL(40000000, 0x9B, 1003 0x22, 0x08, 0x7D, 0x03, 0x80, 0x04, 1004 0x23, 0x10, 0x7D, 0x05, 0xE4, 0x06), 1005 PLL_CTL(512000, 0x01, 1006 0x22, 0x04, 0x01, 0x03, 0xD0, 0x02, 1007 0x1B, 0x10, 0x01, 0x04, 0x72, 0x03), 1008 PLL_CTL(705600, 0x02, 1009 0x22, 0x04, 0x02, 0x03, 0x15, 0x04, 1010 0x22, 0x10, 0x01, 0x04, 0x80, 0x02), 1011 PLL_CTL(1024000, 0x03, 1012 0x22, 0x04, 0x02, 0x03, 0xD0, 0x02, 1013 0x1B, 0x10, 0x02, 0x04, 0x72, 0x03), 1014 PLL_CTL(2048000, 0x07, 1015 0x22, 0x04, 0x04, 0x03, 0xD0, 0x02, 1016 0x1B, 0x10, 0x04, 0x04, 0x72, 0x03), 1017 PLL_CTL(2400000, 0x08, 1018 0x22, 0x04, 0x05, 0x03, 0x00, 0x03, 1019 0x23, 0x10, 0x05, 0x05, 0x98, 0x04), 1020 }; 1021 1022 static const struct pll_ctl *get_pll_ctl(int input_freq) 1023 { 1024 int i; 1025 const struct pll_ctl *pll_ctl = NULL; 1026 1027 for (i = 0; i < ARRAY_SIZE(pll_ctls); ++i) 1028 if (input_freq == pll_ctls[i].input_freq) { 1029 pll_ctl = &pll_ctls[i]; 1030 break; 1031 } 1032 1033 return pll_ctl; 1034 } 1035 1036 static int set_pll_ctl_from_input_freq(struct snd_soc_component *component, 1037 const int input_freq) 1038 { 1039 int ret; 1040 int i; 1041 const struct pll_ctl *pll_ctl; 1042 1043 pll_ctl = get_pll_ctl(input_freq); 1044 if (!pll_ctl) { 1045 ret = -EINVAL; 1046 dev_err(component->dev, "No PLL input entry for %d (%d)\n", 1047 input_freq, ret); 1048 return ret; 1049 } 1050 1051 for (i = 0; i < PLL_REG_SETTINGS_COUNT; ++i) { 1052 ret = snd_soc_component_update_bits(component, 1053 pll_ctl->settings[i].addr, 1054 pll_ctl->settings[i].mask, 1055 pll_ctl->settings[i].val); 1056 if (ret < 0) { 1057 dev_err(component->dev, "Failed to set pll ctl (%d)\n", 1058 ret); 1059 return ret; 1060 } 1061 } 1062 1063 return 0; 1064 } 1065 1066 static int tscs42xx_hw_params(struct snd_pcm_substream *substream, 1067 struct snd_pcm_hw_params *params, 1068 struct snd_soc_dai *codec_dai) 1069 { 1070 struct snd_soc_component *component = codec_dai->component; 1071 int ret; 1072 1073 ret = setup_sample_format(component, params_format(params)); 1074 if (ret < 0) { 1075 dev_err(component->dev, "Failed to setup sample format (%d)\n", 1076 ret); 1077 return ret; 1078 } 1079 1080 ret = setup_sample_rate(component, params_rate(params)); 1081 if (ret < 0) { 1082 dev_err(component->dev, 1083 "Failed to setup sample rate (%d)\n", ret); 1084 return ret; 1085 } 1086 1087 return 0; 1088 } 1089 1090 static inline int dac_mute(struct snd_soc_component *component) 1091 { 1092 int ret; 1093 1094 ret = snd_soc_component_update_bits(component, 1095 R_CNVRTR1, RM_CNVRTR1_DACMU, 1096 RV_CNVRTR1_DACMU_ENABLE); 1097 if (ret < 0) { 1098 dev_err(component->dev, "Failed to mute DAC (%d)\n", 1099 ret); 1100 return ret; 1101 } 1102 1103 return 0; 1104 } 1105 1106 static inline int dac_unmute(struct snd_soc_component *component) 1107 { 1108 int ret; 1109 1110 ret = snd_soc_component_update_bits(component, 1111 R_CNVRTR1, RM_CNVRTR1_DACMU, 1112 RV_CNVRTR1_DACMU_DISABLE); 1113 if (ret < 0) { 1114 dev_err(component->dev, "Failed to unmute DAC (%d)\n", 1115 ret); 1116 return ret; 1117 } 1118 1119 return 0; 1120 } 1121 1122 static inline int adc_mute(struct snd_soc_component *component) 1123 { 1124 int ret; 1125 1126 ret = snd_soc_component_update_bits(component, 1127 R_CNVRTR0, RM_CNVRTR0_ADCMU, RV_CNVRTR0_ADCMU_ENABLE); 1128 if (ret < 0) { 1129 dev_err(component->dev, "Failed to mute ADC (%d)\n", 1130 ret); 1131 return ret; 1132 } 1133 1134 return 0; 1135 } 1136 1137 static inline int adc_unmute(struct snd_soc_component *component) 1138 { 1139 int ret; 1140 1141 ret = snd_soc_component_update_bits(component, 1142 R_CNVRTR0, RM_CNVRTR0_ADCMU, RV_CNVRTR0_ADCMU_DISABLE); 1143 if (ret < 0) { 1144 dev_err(component->dev, "Failed to unmute ADC (%d)\n", 1145 ret); 1146 return ret; 1147 } 1148 1149 return 0; 1150 } 1151 1152 static int tscs42xx_mute_stream(struct snd_soc_dai *dai, int mute, int stream) 1153 { 1154 struct snd_soc_component *component = dai->component; 1155 int ret; 1156 1157 if (mute) 1158 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 1159 ret = dac_mute(component); 1160 else 1161 ret = adc_mute(component); 1162 else 1163 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 1164 ret = dac_unmute(component); 1165 else 1166 ret = adc_unmute(component); 1167 1168 return ret; 1169 } 1170 1171 static int tscs42xx_set_dai_fmt(struct snd_soc_dai *codec_dai, 1172 unsigned int fmt) 1173 { 1174 struct snd_soc_component *component = codec_dai->component; 1175 int ret; 1176 1177 /* Consumer mode not supported since it needs always-on frame clock */ 1178 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1179 case SND_SOC_DAIFMT_CBP_CFP: 1180 ret = snd_soc_component_update_bits(component, 1181 R_AIC1, RM_AIC1_MS, RV_AIC1_MS_MASTER); 1182 if (ret < 0) { 1183 dev_err(component->dev, 1184 "Failed to set codec DAI master (%d)\n", ret); 1185 return ret; 1186 } 1187 break; 1188 default: 1189 ret = -EINVAL; 1190 dev_err(component->dev, "Unsupported format (%d)\n", ret); 1191 return ret; 1192 } 1193 1194 return 0; 1195 } 1196 1197 static int tscs42xx_set_dai_bclk_ratio(struct snd_soc_dai *codec_dai, 1198 unsigned int ratio) 1199 { 1200 struct snd_soc_component *component = codec_dai->component; 1201 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 1202 unsigned int value; 1203 int ret = 0; 1204 1205 switch (ratio) { 1206 case 32: 1207 value = RV_DACSR_DBCM_32; 1208 break; 1209 case 40: 1210 value = RV_DACSR_DBCM_40; 1211 break; 1212 case 64: 1213 value = RV_DACSR_DBCM_64; 1214 break; 1215 default: 1216 dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret); 1217 return -EINVAL; 1218 } 1219 1220 ret = snd_soc_component_update_bits(component, 1221 R_DACSR, RM_DACSR_DBCM, value); 1222 if (ret < 0) { 1223 dev_err(component->dev, 1224 "Failed to set DAC BCLK ratio (%d)\n", ret); 1225 return ret; 1226 } 1227 ret = snd_soc_component_update_bits(component, 1228 R_ADCSR, RM_ADCSR_ABCM, value); 1229 if (ret < 0) { 1230 dev_err(component->dev, 1231 "Failed to set ADC BCLK ratio (%d)\n", ret); 1232 return ret; 1233 } 1234 1235 guard(mutex)(&tscs42xx->audio_params_lock); 1236 1237 tscs42xx->bclk_ratio = ratio; 1238 1239 return 0; 1240 } 1241 1242 static const struct snd_soc_dai_ops tscs42xx_dai_ops = { 1243 .hw_params = tscs42xx_hw_params, 1244 .mute_stream = tscs42xx_mute_stream, 1245 .set_fmt = tscs42xx_set_dai_fmt, 1246 .set_bclk_ratio = tscs42xx_set_dai_bclk_ratio, 1247 }; 1248 1249 static int part_is_valid(struct tscs42xx *tscs42xx) 1250 { 1251 int val; 1252 int ret; 1253 unsigned int reg; 1254 1255 ret = regmap_read(tscs42xx->regmap, R_DEVIDH, ®); 1256 if (ret < 0) 1257 return ret; 1258 1259 val = reg << 8; 1260 ret = regmap_read(tscs42xx->regmap, R_DEVIDL, ®); 1261 if (ret < 0) 1262 return ret; 1263 1264 val |= reg; 1265 1266 switch (val) { 1267 case 0x4A74: 1268 case 0x4A73: 1269 return true; 1270 default: 1271 return false; 1272 } 1273 } 1274 1275 static int set_sysclk(struct snd_soc_component *component) 1276 { 1277 struct tscs42xx *tscs42xx = snd_soc_component_get_drvdata(component); 1278 unsigned long freq; 1279 int ret; 1280 1281 switch (tscs42xx->sysclk_src_id) { 1282 case TSCS42XX_PLL_SRC_XTAL: 1283 case TSCS42XX_PLL_SRC_MCLK1: 1284 ret = snd_soc_component_write(component, R_PLLREFSEL, 1285 RV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1 | 1286 RV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1); 1287 if (ret < 0) { 1288 dev_err(component->dev, 1289 "Failed to set pll reference input (%d)\n", 1290 ret); 1291 return ret; 1292 } 1293 break; 1294 case TSCS42XX_PLL_SRC_MCLK2: 1295 ret = snd_soc_component_write(component, R_PLLREFSEL, 1296 RV_PLLREFSEL_PLL1_REF_SEL_MCLK2 | 1297 RV_PLLREFSEL_PLL2_REF_SEL_MCLK2); 1298 if (ret < 0) { 1299 dev_err(component->dev, 1300 "Failed to set PLL reference (%d)\n", ret); 1301 return ret; 1302 } 1303 break; 1304 default: 1305 dev_err(component->dev, "pll src is unsupported\n"); 1306 return -EINVAL; 1307 } 1308 1309 freq = clk_get_rate(tscs42xx->sysclk); 1310 ret = set_pll_ctl_from_input_freq(component, freq); 1311 if (ret < 0) { 1312 dev_err(component->dev, 1313 "Failed to setup PLL input freq (%d)\n", ret); 1314 return ret; 1315 } 1316 1317 return 0; 1318 } 1319 1320 static int tscs42xx_probe(struct snd_soc_component *component) 1321 { 1322 return set_sysclk(component); 1323 } 1324 1325 static const struct snd_soc_component_driver soc_codec_dev_tscs42xx = { 1326 .probe = tscs42xx_probe, 1327 .dapm_widgets = tscs42xx_dapm_widgets, 1328 .num_dapm_widgets = ARRAY_SIZE(tscs42xx_dapm_widgets), 1329 .dapm_routes = tscs42xx_intercon, 1330 .num_dapm_routes = ARRAY_SIZE(tscs42xx_intercon), 1331 .controls = tscs42xx_snd_controls, 1332 .num_controls = ARRAY_SIZE(tscs42xx_snd_controls), 1333 .idle_bias_on = 1, 1334 .use_pmdown_time = 1, 1335 .endianness = 1, 1336 }; 1337 1338 static inline void init_coeff_ram_cache(struct tscs42xx *tscs42xx) 1339 { 1340 static const u8 norm_addrs[] = { 1341 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x19, 0x1f, 0x20, 0x25, 0x2a, 1342 0x2f, 0x34, 0x39, 0x3f, 0x40, 0x45, 0x4a, 0x4f, 0x54, 0x59, 1343 0x5f, 0x60, 0x65, 0x6a, 0x6f, 0x74, 0x79, 0x7f, 0x80, 0x85, 1344 0x8c, 0x91, 0x96, 0x97, 0x9c, 0xa3, 0xa8, 0xad, 0xaf, 0xb0, 1345 0xb5, 0xba, 0xbf, 0xc4, 0xc9, 1346 }; 1347 u8 *coeff_ram = tscs42xx->coeff_ram; 1348 int i; 1349 1350 for (i = 0; i < ARRAY_SIZE(norm_addrs); i++) 1351 coeff_ram[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40; 1352 } 1353 1354 #define TSCS42XX_RATES SNDRV_PCM_RATE_8000_96000 1355 1356 #define TSCS42XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 1357 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1358 1359 static struct snd_soc_dai_driver tscs42xx_dai = { 1360 .name = "tscs42xx-HiFi", 1361 .playback = { 1362 .stream_name = "HiFi Playback", 1363 .channels_min = 2, 1364 .channels_max = 2, 1365 .rates = TSCS42XX_RATES, 1366 .formats = TSCS42XX_FORMATS,}, 1367 .capture = { 1368 .stream_name = "HiFi Capture", 1369 .channels_min = 2, 1370 .channels_max = 2, 1371 .rates = TSCS42XX_RATES, 1372 .formats = TSCS42XX_FORMATS,}, 1373 .ops = &tscs42xx_dai_ops, 1374 .symmetric_rate = 1, 1375 .symmetric_channels = 1, 1376 .symmetric_sample_bits = 1, 1377 }; 1378 1379 static const struct reg_sequence tscs42xx_patch[] = { 1380 { R_AIC2, RV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED }, 1381 }; 1382 1383 static char const * const src_names[TSCS42XX_PLL_SRC_CNT] = { 1384 "xtal", "mclk1", "mclk2"}; 1385 1386 static int tscs42xx_i2c_probe(struct i2c_client *i2c) 1387 { 1388 struct tscs42xx *tscs42xx; 1389 int src; 1390 int ret; 1391 1392 tscs42xx = devm_kzalloc(&i2c->dev, sizeof(*tscs42xx), GFP_KERNEL); 1393 if (!tscs42xx) { 1394 ret = -ENOMEM; 1395 dev_err(&i2c->dev, 1396 "Failed to allocate memory for data (%d)\n", ret); 1397 return ret; 1398 } 1399 i2c_set_clientdata(i2c, tscs42xx); 1400 1401 for (src = TSCS42XX_PLL_SRC_XTAL; src < TSCS42XX_PLL_SRC_CNT; src++) { 1402 tscs42xx->sysclk = devm_clk_get(&i2c->dev, src_names[src]); 1403 if (!IS_ERR(tscs42xx->sysclk)) { 1404 break; 1405 } else if (PTR_ERR(tscs42xx->sysclk) != -ENOENT) { 1406 ret = PTR_ERR(tscs42xx->sysclk); 1407 dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret); 1408 return ret; 1409 } 1410 } 1411 if (src == TSCS42XX_PLL_SRC_CNT) { 1412 ret = -EINVAL; 1413 dev_err(&i2c->dev, "Failed to get a valid clock name (%d)\n", 1414 ret); 1415 return ret; 1416 } 1417 tscs42xx->sysclk_src_id = src; 1418 1419 tscs42xx->regmap = devm_regmap_init_i2c(i2c, &tscs42xx_regmap); 1420 if (IS_ERR(tscs42xx->regmap)) { 1421 ret = PTR_ERR(tscs42xx->regmap); 1422 dev_err(&i2c->dev, "Failed to allocate regmap (%d)\n", ret); 1423 return ret; 1424 } 1425 1426 init_coeff_ram_cache(tscs42xx); 1427 1428 ret = part_is_valid(tscs42xx); 1429 if (ret <= 0) { 1430 dev_err(&i2c->dev, "No valid part (%d)\n", ret); 1431 ret = -ENODEV; 1432 return ret; 1433 } 1434 1435 ret = regmap_write(tscs42xx->regmap, R_RESET, RV_RESET_ENABLE); 1436 if (ret < 0) { 1437 dev_err(&i2c->dev, "Failed to reset device (%d)\n", ret); 1438 return ret; 1439 } 1440 1441 ret = regmap_register_patch(tscs42xx->regmap, tscs42xx_patch, 1442 ARRAY_SIZE(tscs42xx_patch)); 1443 if (ret < 0) { 1444 dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret); 1445 return ret; 1446 } 1447 1448 mutex_init(&tscs42xx->audio_params_lock); 1449 mutex_init(&tscs42xx->coeff_ram_lock); 1450 mutex_init(&tscs42xx->pll_lock); 1451 1452 ret = devm_snd_soc_register_component(&i2c->dev, 1453 &soc_codec_dev_tscs42xx, &tscs42xx_dai, 1); 1454 if (ret) { 1455 dev_err(&i2c->dev, "Failed to register codec (%d)\n", ret); 1456 return ret; 1457 } 1458 1459 return 0; 1460 } 1461 1462 static const struct i2c_device_id tscs42xx_i2c_id[] = { 1463 { .name = "tscs42A1" }, 1464 { .name = "tscs42A2" }, 1465 { } 1466 }; 1467 MODULE_DEVICE_TABLE(i2c, tscs42xx_i2c_id); 1468 1469 static const struct of_device_id tscs42xx_of_match[] = { 1470 { .compatible = "tempo,tscs42A1", }, 1471 { .compatible = "tempo,tscs42A2", }, 1472 { } 1473 }; 1474 MODULE_DEVICE_TABLE(of, tscs42xx_of_match); 1475 1476 static struct i2c_driver tscs42xx_i2c_driver = { 1477 .driver = { 1478 .name = "tscs42xx", 1479 .of_match_table = tscs42xx_of_match, 1480 }, 1481 .probe = tscs42xx_i2c_probe, 1482 .id_table = tscs42xx_i2c_id, 1483 }; 1484 1485 module_i2c_driver(tscs42xx_i2c_driver); 1486 1487 MODULE_AUTHOR("Tempo Semiconductor <steven.eckhoff.opensource@gmail.com"); 1488 MODULE_DESCRIPTION("ASoC TSCS42xx driver"); 1489 MODULE_LICENSE("GPL"); 1490