xref: /linux/drivers/net/ethernet/mellanox/mlxsw/spectrum.c (revision 91ec2035134982b98fab0609a9fd8480e8217dc1)
1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
3 
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/types.h>
7 #include <linux/pci.h>
8 #include <linux/netdevice.h>
9 #include <linux/etherdevice.h>
10 #include <linux/ethtool.h>
11 #include <linux/slab.h>
12 #include <linux/device.h>
13 #include <linux/skbuff.h>
14 #include <linux/if_vlan.h>
15 #include <linux/if_bridge.h>
16 #include <linux/workqueue.h>
17 #include <linux/jiffies.h>
18 #include <linux/bitops.h>
19 #include <linux/list.h>
20 #include <linux/notifier.h>
21 #include <linux/dcbnl.h>
22 #include <linux/inetdevice.h>
23 #include <linux/netlink.h>
24 #include <linux/jhash.h>
25 #include <linux/log2.h>
26 #include <linux/refcount.h>
27 #include <linux/rhashtable.h>
28 #include <net/switchdev.h>
29 #include <net/pkt_cls.h>
30 #include <net/netevent.h>
31 #include <net/addrconf.h>
32 #include <linux/ptp_classify.h>
33 
34 #include "spectrum.h"
35 #include "pci.h"
36 #include "core.h"
37 #include "core_env.h"
38 #include "reg.h"
39 #include "port.h"
40 #include "trap.h"
41 #include "txheader.h"
42 #include "spectrum_cnt.h"
43 #include "spectrum_dpipe.h"
44 #include "spectrum_acl_flex_actions.h"
45 #include "spectrum_span.h"
46 #include "spectrum_ptp.h"
47 #include "spectrum_trap.h"
48 
49 #define MLXSW_SP_FWREV_MINOR 2010
50 #define MLXSW_SP_FWREV_SUBMINOR 1006
51 
52 #define MLXSW_SP1_FWREV_MAJOR 13
53 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
54 
55 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
56 	.major = MLXSW_SP1_FWREV_MAJOR,
57 	.minor = MLXSW_SP_FWREV_MINOR,
58 	.subminor = MLXSW_SP_FWREV_SUBMINOR,
59 	.can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
60 };
61 
62 #define MLXSW_SP1_FW_FILENAME \
63 	"mellanox/mlxsw_spectrum-" __stringify(MLXSW_SP1_FWREV_MAJOR) \
64 	"." __stringify(MLXSW_SP_FWREV_MINOR) \
65 	"." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2"
66 
67 #define MLXSW_SP2_FWREV_MAJOR 29
68 
69 static const struct mlxsw_fw_rev mlxsw_sp2_fw_rev = {
70 	.major = MLXSW_SP2_FWREV_MAJOR,
71 	.minor = MLXSW_SP_FWREV_MINOR,
72 	.subminor = MLXSW_SP_FWREV_SUBMINOR,
73 };
74 
75 #define MLXSW_SP2_FW_FILENAME \
76 	"mellanox/mlxsw_spectrum2-" __stringify(MLXSW_SP2_FWREV_MAJOR) \
77 	"." __stringify(MLXSW_SP_FWREV_MINOR) \
78 	"." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2"
79 
80 #define MLXSW_SP3_FWREV_MAJOR 30
81 
82 static const struct mlxsw_fw_rev mlxsw_sp3_fw_rev = {
83 	.major = MLXSW_SP3_FWREV_MAJOR,
84 	.minor = MLXSW_SP_FWREV_MINOR,
85 	.subminor = MLXSW_SP_FWREV_SUBMINOR,
86 };
87 
88 #define MLXSW_SP3_FW_FILENAME \
89 	"mellanox/mlxsw_spectrum3-" __stringify(MLXSW_SP3_FWREV_MAJOR) \
90 	"." __stringify(MLXSW_SP_FWREV_MINOR) \
91 	"." __stringify(MLXSW_SP_FWREV_SUBMINOR) ".mfa2"
92 
93 #define MLXSW_SP_LINECARDS_INI_BUNDLE_FILENAME \
94 	"mellanox/lc_ini_bundle_" \
95 	__stringify(MLXSW_SP_FWREV_MINOR) "_" \
96 	__stringify(MLXSW_SP_FWREV_SUBMINOR) ".bin"
97 
98 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
99 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
100 static const char mlxsw_sp3_driver_name[] = "mlxsw_spectrum3";
101 static const char mlxsw_sp4_driver_name[] = "mlxsw_spectrum4";
102 
103 static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = {
104 	0xff, 0xff, 0xff, 0xff, 0xfc, 0x00
105 };
106 static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = {
107 	0xff, 0xff, 0xff, 0xff, 0xf0, 0x00
108 };
109 
mlxsw_sp_flow_counter_get(struct mlxsw_sp * mlxsw_sp,unsigned int counter_index,bool clear,u64 * packets,u64 * bytes)110 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
111 			      unsigned int counter_index, bool clear,
112 			      u64 *packets, u64 *bytes)
113 {
114 	enum mlxsw_reg_mgpc_opcode op = clear ? MLXSW_REG_MGPC_OPCODE_CLEAR :
115 						MLXSW_REG_MGPC_OPCODE_NOP;
116 	char mgpc_pl[MLXSW_REG_MGPC_LEN];
117 	int err;
118 
119 	mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, op,
120 			    MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
121 	err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
122 	if (err)
123 		return err;
124 	if (packets)
125 		*packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
126 	if (bytes)
127 		*bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
128 	return 0;
129 }
130 
mlxsw_sp_flow_counter_clear(struct mlxsw_sp * mlxsw_sp,unsigned int counter_index)131 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
132 				       unsigned int counter_index)
133 {
134 	char mgpc_pl[MLXSW_REG_MGPC_LEN];
135 
136 	mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
137 			    MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
138 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
139 }
140 
mlxsw_sp_flow_counter_alloc(struct mlxsw_sp * mlxsw_sp,unsigned int * p_counter_index)141 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
142 				unsigned int *p_counter_index)
143 {
144 	int err;
145 
146 	err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
147 				     p_counter_index);
148 	if (err)
149 		return err;
150 	err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
151 	if (err)
152 		goto err_counter_clear;
153 	return 0;
154 
155 err_counter_clear:
156 	mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
157 			      *p_counter_index);
158 	return err;
159 }
160 
mlxsw_sp_flow_counter_free(struct mlxsw_sp * mlxsw_sp,unsigned int counter_index)161 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
162 				unsigned int counter_index)
163 {
164 	 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
165 			       counter_index);
166 }
167 
mlxsw_sp_skb_requires_ts(struct sk_buff * skb)168 static bool mlxsw_sp_skb_requires_ts(struct sk_buff *skb)
169 {
170 	unsigned int type;
171 
172 	if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
173 		return false;
174 
175 	type = ptp_classify_raw(skb);
176 	return !!ptp_parse_header(skb, type);
177 }
178 
mlxsw_sp_txhdr_info_data_init(struct mlxsw_core * mlxsw_core,struct sk_buff * skb,struct mlxsw_txhdr_info * txhdr_info)179 static void mlxsw_sp_txhdr_info_data_init(struct mlxsw_core *mlxsw_core,
180 					  struct sk_buff *skb,
181 					  struct mlxsw_txhdr_info *txhdr_info)
182 {
183 	/* Resource validation was done as part of PTP init. */
184 	u16 max_fid = MLXSW_CORE_RES_GET(mlxsw_core, FID);
185 
186 	txhdr_info->data = true;
187 	txhdr_info->max_fid = max_fid;
188 }
189 
190 static struct sk_buff *
mlxsw_sp_vlan_tag_push(struct mlxsw_sp * mlxsw_sp,struct sk_buff * skb)191 mlxsw_sp_vlan_tag_push(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb)
192 {
193 	/* In some Spectrum ASICs, in order for PTP event packets to have their
194 	 * correction field correctly set on the egress port they must be
195 	 * transmitted as data packets. Such packets ingress the ASIC via the
196 	 * CPU port and must have a VLAN tag, as the CPU port is not configured
197 	 * with a PVID. Push the default VLAN (4095), which is configured as
198 	 * egress untagged on all the ports.
199 	 */
200 	if (skb_vlan_tagged(skb))
201 		return skb;
202 
203 	return vlan_insert_tag_set_proto(skb, htons(ETH_P_8021Q),
204 					 MLXSW_SP_DEFAULT_VID);
205 }
206 
207 static struct sk_buff *
mlxsw_sp_txhdr_preparations(struct mlxsw_sp * mlxsw_sp,struct sk_buff * skb,struct mlxsw_txhdr_info * txhdr_info)208 mlxsw_sp_txhdr_preparations(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
209 			    struct mlxsw_txhdr_info *txhdr_info)
210 {
211 	if (likely(!mlxsw_sp_skb_requires_ts(skb)))
212 		return skb;
213 
214 	if (!mlxsw_sp->ptp_ops->tx_as_data)
215 		return skb;
216 
217 	/* Special handling for PTP events that require a time stamp and cannot
218 	 * be transmitted as regular control packets.
219 	 */
220 	mlxsw_sp_txhdr_info_data_init(mlxsw_sp->core, skb, txhdr_info);
221 	return mlxsw_sp_vlan_tag_push(mlxsw_sp, skb);
222 }
223 
mlxsw_sp_stp_spms_state(u8 state)224 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
225 {
226 	switch (state) {
227 	case BR_STATE_FORWARDING:
228 		return MLXSW_REG_SPMS_STATE_FORWARDING;
229 	case BR_STATE_LEARNING:
230 		return MLXSW_REG_SPMS_STATE_LEARNING;
231 	case BR_STATE_LISTENING:
232 	case BR_STATE_DISABLED:
233 	case BR_STATE_BLOCKING:
234 		return MLXSW_REG_SPMS_STATE_DISCARDING;
235 	default:
236 		BUG();
237 	}
238 }
239 
mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid,u8 state)240 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
241 			      u8 state)
242 {
243 	enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
244 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
245 	char *spms_pl;
246 	int err;
247 
248 	spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
249 	if (!spms_pl)
250 		return -ENOMEM;
251 	mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
252 	mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
253 
254 	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
255 	kfree(spms_pl);
256 	return err;
257 }
258 
mlxsw_sp_base_mac_get(struct mlxsw_sp * mlxsw_sp)259 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
260 {
261 	char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
262 	int err;
263 
264 	err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
265 	if (err)
266 		return err;
267 	mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
268 	return 0;
269 }
270 
mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port * mlxsw_sp_port,bool is_up)271 int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
272 				   bool is_up)
273 {
274 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
275 	char paos_pl[MLXSW_REG_PAOS_LEN];
276 
277 	mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
278 			    is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
279 			    MLXSW_PORT_ADMIN_STATUS_DOWN);
280 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
281 }
282 
mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port * mlxsw_sp_port,const unsigned char * addr)283 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
284 				      const unsigned char *addr)
285 {
286 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
287 	char ppad_pl[MLXSW_REG_PPAD_LEN];
288 
289 	mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
290 	mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
291 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
292 }
293 
mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port * mlxsw_sp_port)294 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
295 {
296 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
297 
298 	eth_hw_addr_gen(mlxsw_sp_port->dev, mlxsw_sp->base_mac,
299 			mlxsw_sp_port->local_port);
300 	return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port,
301 					  mlxsw_sp_port->dev->dev_addr);
302 }
303 
mlxsw_sp_port_mtu_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 mtu)304 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
305 {
306 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
307 	char pmtu_pl[MLXSW_REG_PMTU_LEN];
308 
309 	mtu += MLXSW_PORT_ETH_FRAME_HDR;
310 
311 	mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
312 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
313 }
314 
mlxsw_sp_port_swid_set(struct mlxsw_sp * mlxsw_sp,u16 local_port,u8 swid)315 static int mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp,
316 				  u16 local_port, u8 swid)
317 {
318 	char pspa_pl[MLXSW_REG_PSPA_LEN];
319 
320 	mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
321 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
322 }
323 
mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port * mlxsw_sp_port,bool enable)324 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
325 {
326 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
327 	char svpe_pl[MLXSW_REG_SVPE_LEN];
328 
329 	mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
330 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
331 }
332 
mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid,bool learn_enable)333 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
334 				   bool learn_enable)
335 {
336 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
337 	char *spvmlr_pl;
338 	int err;
339 
340 	spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
341 	if (!spvmlr_pl)
342 		return -ENOMEM;
343 	mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
344 			      learn_enable);
345 	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
346 	kfree(spvmlr_pl);
347 	return err;
348 }
349 
mlxsw_sp_port_security_set(struct mlxsw_sp_port * mlxsw_sp_port,bool enable)350 int mlxsw_sp_port_security_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
351 {
352 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
353 	char spfsr_pl[MLXSW_REG_SPFSR_LEN];
354 	int err;
355 
356 	if (mlxsw_sp_port->security == enable)
357 		return 0;
358 
359 	mlxsw_reg_spfsr_pack(spfsr_pl, mlxsw_sp_port->local_port, enable);
360 	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spfsr), spfsr_pl);
361 	if (err)
362 		return err;
363 
364 	mlxsw_sp_port->security = enable;
365 	return 0;
366 }
367 
mlxsw_sp_ethtype_to_sver_type(u16 ethtype,u8 * p_sver_type)368 int mlxsw_sp_ethtype_to_sver_type(u16 ethtype, u8 *p_sver_type)
369 {
370 	switch (ethtype) {
371 	case ETH_P_8021Q:
372 		*p_sver_type = 0;
373 		break;
374 	case ETH_P_8021AD:
375 		*p_sver_type = 1;
376 		break;
377 	default:
378 		return -EINVAL;
379 	}
380 
381 	return 0;
382 }
383 
mlxsw_sp_port_egress_ethtype_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 ethtype)384 int mlxsw_sp_port_egress_ethtype_set(struct mlxsw_sp_port *mlxsw_sp_port,
385 				     u16 ethtype)
386 {
387 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
388 	char spevet_pl[MLXSW_REG_SPEVET_LEN];
389 	u8 sver_type;
390 	int err;
391 
392 	err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type);
393 	if (err)
394 		return err;
395 
396 	mlxsw_reg_spevet_pack(spevet_pl, mlxsw_sp_port->local_port, sver_type);
397 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spevet), spevet_pl);
398 }
399 
__mlxsw_sp_port_pvid_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid,u16 ethtype)400 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
401 				    u16 vid, u16 ethtype)
402 {
403 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
404 	char spvid_pl[MLXSW_REG_SPVID_LEN];
405 	u8 sver_type;
406 	int err;
407 
408 	err = mlxsw_sp_ethtype_to_sver_type(ethtype, &sver_type);
409 	if (err)
410 		return err;
411 
412 	mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid,
413 			     sver_type);
414 
415 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
416 }
417 
mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port * mlxsw_sp_port,bool allow)418 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
419 					    bool allow)
420 {
421 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
422 	char spaft_pl[MLXSW_REG_SPAFT_LEN];
423 
424 	mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
425 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
426 }
427 
mlxsw_sp_port_pvid_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid,u16 ethtype)428 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
429 			   u16 ethtype)
430 {
431 	int err;
432 
433 	if (!vid) {
434 		err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
435 		if (err)
436 			return err;
437 	} else {
438 		err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid, ethtype);
439 		if (err)
440 			return err;
441 		err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
442 		if (err)
443 			goto err_port_allow_untagged_set;
444 	}
445 
446 	mlxsw_sp_port->pvid = vid;
447 	return 0;
448 
449 err_port_allow_untagged_set:
450 	__mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid, ethtype);
451 	return err;
452 }
453 
454 static int
mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port * mlxsw_sp_port)455 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
456 {
457 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
458 	char sspr_pl[MLXSW_REG_SSPR_LEN];
459 
460 	mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
461 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
462 }
463 
464 static int
mlxsw_sp_port_module_info_parse(struct mlxsw_sp * mlxsw_sp,u16 local_port,char * pmlp_pl,struct mlxsw_sp_port_mapping * port_mapping)465 mlxsw_sp_port_module_info_parse(struct mlxsw_sp *mlxsw_sp,
466 				u16 local_port, char *pmlp_pl,
467 				struct mlxsw_sp_port_mapping *port_mapping)
468 {
469 	bool separate_rxtx;
470 	u8 first_lane;
471 	u8 slot_index;
472 	u8 module;
473 	u8 width;
474 	int i;
475 
476 	module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
477 	slot_index = mlxsw_reg_pmlp_slot_index_get(pmlp_pl, 0);
478 	width = mlxsw_reg_pmlp_width_get(pmlp_pl);
479 	separate_rxtx = mlxsw_reg_pmlp_rxtx_get(pmlp_pl);
480 	first_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
481 
482 	if (width && !is_power_of_2(width)) {
483 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: width value is not power of 2\n",
484 			local_port);
485 		return -EINVAL;
486 	}
487 
488 	for (i = 0; i < width; i++) {
489 		if (mlxsw_reg_pmlp_module_get(pmlp_pl, i) != module) {
490 			dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple modules\n",
491 				local_port);
492 			return -EINVAL;
493 		}
494 		if (mlxsw_reg_pmlp_slot_index_get(pmlp_pl, i) != slot_index) {
495 			dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: contains multiple slot indexes\n",
496 				local_port);
497 			return -EINVAL;
498 		}
499 		if (separate_rxtx &&
500 		    mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) !=
501 		    mlxsw_reg_pmlp_rx_lane_get(pmlp_pl, i)) {
502 			dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are different\n",
503 				local_port);
504 			return -EINVAL;
505 		}
506 		if (mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, i) != i + first_lane) {
507 			dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unsupported module config: TX and RX lane numbers are not sequential\n",
508 				local_port);
509 			return -EINVAL;
510 		}
511 	}
512 
513 	port_mapping->module = module;
514 	port_mapping->slot_index = slot_index;
515 	port_mapping->width = width;
516 	port_mapping->module_width = width;
517 	port_mapping->lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
518 	return 0;
519 }
520 
521 static int
mlxsw_sp_port_module_info_get(struct mlxsw_sp * mlxsw_sp,u16 local_port,struct mlxsw_sp_port_mapping * port_mapping)522 mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp, u16 local_port,
523 			      struct mlxsw_sp_port_mapping *port_mapping)
524 {
525 	char pmlp_pl[MLXSW_REG_PMLP_LEN];
526 	int err;
527 
528 	mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
529 	err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
530 	if (err)
531 		return err;
532 	return mlxsw_sp_port_module_info_parse(mlxsw_sp, local_port,
533 					       pmlp_pl, port_mapping);
534 }
535 
536 static int
mlxsw_sp_port_module_map(struct mlxsw_sp * mlxsw_sp,u16 local_port,const struct mlxsw_sp_port_mapping * port_mapping)537 mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u16 local_port,
538 			 const struct mlxsw_sp_port_mapping *port_mapping)
539 {
540 	char pmlp_pl[MLXSW_REG_PMLP_LEN];
541 	int i, err;
542 
543 	mlxsw_env_module_port_map(mlxsw_sp->core, port_mapping->slot_index,
544 				  port_mapping->module);
545 
546 	mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
547 	mlxsw_reg_pmlp_width_set(pmlp_pl, port_mapping->width);
548 	for (i = 0; i < port_mapping->width; i++) {
549 		mlxsw_reg_pmlp_slot_index_set(pmlp_pl, i,
550 					      port_mapping->slot_index);
551 		mlxsw_reg_pmlp_module_set(pmlp_pl, i, port_mapping->module);
552 		mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, port_mapping->lane + i); /* Rx & Tx */
553 	}
554 
555 	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
556 	if (err)
557 		goto err_pmlp_write;
558 	return 0;
559 
560 err_pmlp_write:
561 	mlxsw_env_module_port_unmap(mlxsw_sp->core, port_mapping->slot_index,
562 				    port_mapping->module);
563 	return err;
564 }
565 
mlxsw_sp_port_module_unmap(struct mlxsw_sp * mlxsw_sp,u16 local_port,u8 slot_index,u8 module)566 static void mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u16 local_port,
567 				       u8 slot_index, u8 module)
568 {
569 	char pmlp_pl[MLXSW_REG_PMLP_LEN];
570 
571 	mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
572 	mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
573 	mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
574 	mlxsw_env_module_port_unmap(mlxsw_sp->core, slot_index, module);
575 }
576 
mlxsw_sp_port_open(struct net_device * dev)577 static int mlxsw_sp_port_open(struct net_device *dev)
578 {
579 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
580 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
581 	int err;
582 
583 	err = mlxsw_env_module_port_up(mlxsw_sp->core,
584 				       mlxsw_sp_port->mapping.slot_index,
585 				       mlxsw_sp_port->mapping.module);
586 	if (err)
587 		return err;
588 	err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
589 	if (err)
590 		goto err_port_admin_status_set;
591 	netif_start_queue(dev);
592 	return 0;
593 
594 err_port_admin_status_set:
595 	mlxsw_env_module_port_down(mlxsw_sp->core,
596 				   mlxsw_sp_port->mapping.slot_index,
597 				   mlxsw_sp_port->mapping.module);
598 	return err;
599 }
600 
mlxsw_sp_port_stop(struct net_device * dev)601 static int mlxsw_sp_port_stop(struct net_device *dev)
602 {
603 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
604 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
605 
606 	netif_stop_queue(dev);
607 	mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
608 	mlxsw_env_module_port_down(mlxsw_sp->core,
609 				   mlxsw_sp_port->mapping.slot_index,
610 				   mlxsw_sp_port->mapping.module);
611 	return 0;
612 }
613 
mlxsw_sp_port_xmit(struct sk_buff * skb,struct net_device * dev)614 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
615 				      struct net_device *dev)
616 {
617 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
618 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
619 	struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
620 	struct mlxsw_txhdr_info txhdr_info = {
621 		.tx_info.local_port = mlxsw_sp_port->local_port,
622 		.tx_info.is_emad = false,
623 	};
624 	u64 len;
625 	int err;
626 
627 	memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb));
628 
629 	if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &txhdr_info.tx_info))
630 		return NETDEV_TX_BUSY;
631 
632 	if (eth_skb_pad(skb)) {
633 		this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
634 		return NETDEV_TX_OK;
635 	}
636 
637 	skb = mlxsw_sp_txhdr_preparations(mlxsw_sp, skb, &txhdr_info);
638 	if (!skb) {
639 		this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
640 		return NETDEV_TX_OK;
641 	}
642 
643 	/* TX header is consumed by HW on the way so we shouldn't count its
644 	 * bytes as being sent.
645 	 */
646 	len = skb->len - MLXSW_TXHDR_LEN;
647 
648 	/* Due to a race we might fail here because of a full queue. In that
649 	 * unlikely case we simply drop the packet.
650 	 */
651 	err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &txhdr_info);
652 
653 	if (!err) {
654 		pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
655 		u64_stats_update_begin(&pcpu_stats->syncp);
656 		pcpu_stats->tx_packets++;
657 		pcpu_stats->tx_bytes += len;
658 		u64_stats_update_end(&pcpu_stats->syncp);
659 	} else {
660 		this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
661 		dev_kfree_skb_any(skb);
662 	}
663 	return NETDEV_TX_OK;
664 }
665 
mlxsw_sp_set_rx_mode_async(struct net_device * dev,struct netdev_hw_addr_list * uc,struct netdev_hw_addr_list * mc)666 static int mlxsw_sp_set_rx_mode_async(struct net_device *dev,
667 				      struct netdev_hw_addr_list *uc,
668 				      struct netdev_hw_addr_list *mc)
669 {
670 	return 0;
671 }
672 
mlxsw_sp_port_set_mac_address(struct net_device * dev,void * p)673 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
674 {
675 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
676 	struct sockaddr *addr = p;
677 	int err;
678 
679 	if (!is_valid_ether_addr(addr->sa_data))
680 		return -EADDRNOTAVAIL;
681 
682 	err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
683 	if (err)
684 		return err;
685 	eth_hw_addr_set(dev, addr->sa_data);
686 	return 0;
687 }
688 
mlxsw_sp_port_change_mtu(struct net_device * dev,int mtu)689 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
690 {
691 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
692 	struct mlxsw_sp_hdroom orig_hdroom;
693 	struct mlxsw_sp_hdroom hdroom;
694 	int err;
695 
696 	orig_hdroom = *mlxsw_sp_port->hdroom;
697 
698 	hdroom = orig_hdroom;
699 	hdroom.mtu = mtu;
700 	mlxsw_sp_hdroom_bufs_reset_sizes(mlxsw_sp_port, &hdroom);
701 
702 	err = mlxsw_sp_hdroom_configure(mlxsw_sp_port, &hdroom);
703 	if (err) {
704 		netdev_err(dev, "Failed to configure port's headroom\n");
705 		return err;
706 	}
707 
708 	err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
709 	if (err)
710 		goto err_port_mtu_set;
711 	WRITE_ONCE(dev->mtu, mtu);
712 	return 0;
713 
714 err_port_mtu_set:
715 	mlxsw_sp_hdroom_configure(mlxsw_sp_port, &orig_hdroom);
716 	return err;
717 }
718 
719 static int
mlxsw_sp_port_get_sw_stats64(const struct net_device * dev,struct rtnl_link_stats64 * stats)720 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
721 			     struct rtnl_link_stats64 *stats)
722 {
723 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
724 	struct mlxsw_sp_port_pcpu_stats *p;
725 	u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
726 	u32 tx_dropped = 0;
727 	unsigned int start;
728 	int i;
729 
730 	for_each_possible_cpu(i) {
731 		p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
732 		do {
733 			start = u64_stats_fetch_begin(&p->syncp);
734 			rx_packets	= p->rx_packets;
735 			rx_bytes	= p->rx_bytes;
736 			tx_packets	= p->tx_packets;
737 			tx_bytes	= p->tx_bytes;
738 		} while (u64_stats_fetch_retry(&p->syncp, start));
739 
740 		stats->rx_packets	+= rx_packets;
741 		stats->rx_bytes		+= rx_bytes;
742 		stats->tx_packets	+= tx_packets;
743 		stats->tx_bytes		+= tx_bytes;
744 		/* tx_dropped is u32, updated without syncp protection. */
745 		tx_dropped	+= p->tx_dropped;
746 	}
747 	stats->tx_dropped	= tx_dropped;
748 	return 0;
749 }
750 
mlxsw_sp_port_has_offload_stats(const struct net_device * dev,int attr_id)751 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
752 {
753 	switch (attr_id) {
754 	case IFLA_OFFLOAD_XSTATS_CPU_HIT:
755 		return true;
756 	}
757 
758 	return false;
759 }
760 
mlxsw_sp_port_get_offload_stats(int attr_id,const struct net_device * dev,void * sp)761 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
762 					   void *sp)
763 {
764 	switch (attr_id) {
765 	case IFLA_OFFLOAD_XSTATS_CPU_HIT:
766 		return mlxsw_sp_port_get_sw_stats64(dev, sp);
767 	}
768 
769 	return -EINVAL;
770 }
771 
mlxsw_sp_port_get_stats_raw(struct net_device * dev,int grp,int prio,char * ppcnt_pl)772 int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
773 				int prio, char *ppcnt_pl)
774 {
775 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
776 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
777 
778 	mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
779 	return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
780 }
781 
mlxsw_sp_port_get_hw_stats(struct net_device * dev,struct rtnl_link_stats64 * stats)782 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
783 				      struct rtnl_link_stats64 *stats)
784 {
785 	char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
786 	int err;
787 
788 	err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
789 					  0, ppcnt_pl);
790 	if (err)
791 		goto out;
792 
793 	stats->tx_packets =
794 		mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
795 	stats->rx_packets =
796 		mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
797 	stats->tx_bytes =
798 		mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
799 	stats->rx_bytes =
800 		mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
801 	stats->multicast =
802 		mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
803 
804 	stats->rx_crc_errors =
805 		mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
806 	stats->rx_frame_errors =
807 		mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
808 
809 	stats->rx_length_errors = (
810 		mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
811 		mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
812 		mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
813 
814 	stats->rx_errors = (stats->rx_crc_errors +
815 		stats->rx_frame_errors + stats->rx_length_errors);
816 
817 out:
818 	return err;
819 }
820 
821 static void
mlxsw_sp_port_get_hw_xstats(struct net_device * dev,struct mlxsw_sp_port_xstats * xstats)822 mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
823 			    struct mlxsw_sp_port_xstats *xstats)
824 {
825 	char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
826 	int err, i;
827 
828 	err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
829 					  ppcnt_pl);
830 	if (!err)
831 		xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
832 
833 	for (i = 0; i < TC_MAX_QUEUE; i++) {
834 		err = mlxsw_sp_port_get_stats_raw(dev,
835 						  MLXSW_REG_PPCNT_TC_CONG_CNT,
836 						  i, ppcnt_pl);
837 		if (err)
838 			goto tc_cnt;
839 
840 		xstats->wred_drop[i] =
841 			mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
842 		xstats->tc_ecn[i] = mlxsw_reg_ppcnt_ecn_marked_tc_get(ppcnt_pl);
843 
844 tc_cnt:
845 		err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
846 						  i, ppcnt_pl);
847 		if (err)
848 			continue;
849 
850 		xstats->backlog[i] =
851 			mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
852 		xstats->tail_drop[i] =
853 			mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
854 	}
855 
856 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
857 		err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
858 						  i, ppcnt_pl);
859 		if (err)
860 			continue;
861 
862 		xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
863 		xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
864 	}
865 }
866 
update_stats_cache(struct work_struct * work)867 static void update_stats_cache(struct work_struct *work)
868 {
869 	struct mlxsw_sp_port *mlxsw_sp_port =
870 		container_of(work, struct mlxsw_sp_port,
871 			     periodic_hw_stats.update_dw.work);
872 
873 	if (!netif_carrier_ok(mlxsw_sp_port->dev))
874 		/* Note: mlxsw_sp_port_down_wipe_counters() clears the cache as
875 		 * necessary when port goes down.
876 		 */
877 		goto out;
878 
879 	mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
880 				   &mlxsw_sp_port->periodic_hw_stats.stats);
881 	mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
882 				    &mlxsw_sp_port->periodic_hw_stats.xstats);
883 
884 out:
885 	mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
886 			       MLXSW_HW_STATS_UPDATE_TIME);
887 }
888 
889 /* Return the stats from a cache that is updated periodically,
890  * as this function might get called in an atomic context.
891  */
892 static void
mlxsw_sp_port_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)893 mlxsw_sp_port_get_stats64(struct net_device *dev,
894 			  struct rtnl_link_stats64 *stats)
895 {
896 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
897 
898 	memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
899 }
900 
__mlxsw_sp_port_vlan_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid_begin,u16 vid_end,bool is_member,bool untagged)901 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
902 				    u16 vid_begin, u16 vid_end,
903 				    bool is_member, bool untagged)
904 {
905 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
906 	char *spvm_pl;
907 	int err;
908 
909 	spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
910 	if (!spvm_pl)
911 		return -ENOMEM;
912 
913 	mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port,	vid_begin,
914 			    vid_end, is_member, untagged);
915 	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
916 	kfree(spvm_pl);
917 	return err;
918 }
919 
mlxsw_sp_port_vlan_set(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid_begin,u16 vid_end,bool is_member,bool untagged)920 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
921 			   u16 vid_end, bool is_member, bool untagged)
922 {
923 	u16 vid, vid_e;
924 	int err;
925 
926 	for (vid = vid_begin; vid <= vid_end;
927 	     vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
928 		vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
929 			    vid_end);
930 
931 		err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
932 					       is_member, untagged);
933 		if (err)
934 			return err;
935 	}
936 
937 	return 0;
938 }
939 
mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port * mlxsw_sp_port,bool flush_default)940 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port,
941 				     bool flush_default)
942 {
943 	struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
944 
945 	list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
946 				 &mlxsw_sp_port->vlans_list, list) {
947 		if (!flush_default &&
948 		    mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID)
949 			continue;
950 		mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
951 	}
952 }
953 
954 static void
mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan * mlxsw_sp_port_vlan)955 mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
956 {
957 	if (mlxsw_sp_port_vlan->bridge_port)
958 		mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
959 	else if (mlxsw_sp_port_vlan->fid)
960 		mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
961 }
962 
963 struct mlxsw_sp_port_vlan *
mlxsw_sp_port_vlan_create(struct mlxsw_sp_port * mlxsw_sp_port,u16 vid)964 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
965 {
966 	struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
967 	bool untagged = vid == MLXSW_SP_DEFAULT_VID;
968 	int err;
969 
970 	mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
971 	if (mlxsw_sp_port_vlan)
972 		return ERR_PTR(-EEXIST);
973 
974 	err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
975 	if (err)
976 		return ERR_PTR(err);
977 
978 	mlxsw_sp_port_vlan = kzalloc_obj(*mlxsw_sp_port_vlan);
979 	if (!mlxsw_sp_port_vlan) {
980 		err = -ENOMEM;
981 		goto err_port_vlan_alloc;
982 	}
983 
984 	mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
985 	mlxsw_sp_port_vlan->vid = vid;
986 	list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
987 
988 	return mlxsw_sp_port_vlan;
989 
990 err_port_vlan_alloc:
991 	mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
992 	return ERR_PTR(err);
993 }
994 
mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan * mlxsw_sp_port_vlan)995 void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
996 {
997 	struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
998 	u16 vid = mlxsw_sp_port_vlan->vid;
999 
1000 	mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan);
1001 	list_del(&mlxsw_sp_port_vlan->list);
1002 	kfree(mlxsw_sp_port_vlan);
1003 	mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1004 }
1005 
mlxsw_sp_port_add_vid(struct net_device * dev,__be16 __always_unused proto,u16 vid)1006 static int mlxsw_sp_port_add_vid(struct net_device *dev,
1007 				 __be16 __always_unused proto, u16 vid)
1008 {
1009 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1010 
1011 	/* VLAN 0 is added to HW filter when device goes up, but it is
1012 	 * reserved in our case, so simply return.
1013 	 */
1014 	if (!vid)
1015 		return 0;
1016 
1017 	return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid));
1018 }
1019 
mlxsw_sp_port_kill_vid(struct net_device * dev,__be16 __always_unused proto,u16 vid)1020 int mlxsw_sp_port_kill_vid(struct net_device *dev,
1021 			   __be16 __always_unused proto, u16 vid)
1022 {
1023 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1024 	struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1025 
1026 	/* VLAN 0 is removed from HW filter when device goes down, but
1027 	 * it is reserved in our case, so simply return.
1028 	 */
1029 	if (!vid)
1030 		return 0;
1031 
1032 	mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1033 	if (!mlxsw_sp_port_vlan)
1034 		return 0;
1035 	mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1036 
1037 	return 0;
1038 }
1039 
mlxsw_sp_setup_tc_block(struct mlxsw_sp_port * mlxsw_sp_port,struct flow_block_offload * f)1040 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1041 				   struct flow_block_offload *f)
1042 {
1043 	switch (f->binder_type) {
1044 	case FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS:
1045 		return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, true);
1046 	case FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS:
1047 		return mlxsw_sp_setup_tc_block_clsact(mlxsw_sp_port, f, false);
1048 	case FLOW_BLOCK_BINDER_TYPE_RED_EARLY_DROP:
1049 		return mlxsw_sp_setup_tc_block_qevent_early_drop(mlxsw_sp_port, f);
1050 	case FLOW_BLOCK_BINDER_TYPE_RED_MARK:
1051 		return mlxsw_sp_setup_tc_block_qevent_mark(mlxsw_sp_port, f);
1052 	default:
1053 		return -EOPNOTSUPP;
1054 	}
1055 }
1056 
mlxsw_sp_setup_tc(struct net_device * dev,enum tc_setup_type type,void * type_data)1057 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
1058 			     void *type_data)
1059 {
1060 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1061 
1062 	switch (type) {
1063 	case TC_SETUP_BLOCK:
1064 		return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
1065 	case TC_SETUP_QDISC_RED:
1066 		return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
1067 	case TC_SETUP_QDISC_PRIO:
1068 		return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
1069 	case TC_SETUP_QDISC_ETS:
1070 		return mlxsw_sp_setup_tc_ets(mlxsw_sp_port, type_data);
1071 	case TC_SETUP_QDISC_TBF:
1072 		return mlxsw_sp_setup_tc_tbf(mlxsw_sp_port, type_data);
1073 	case TC_SETUP_QDISC_FIFO:
1074 		return mlxsw_sp_setup_tc_fifo(mlxsw_sp_port, type_data);
1075 	default:
1076 		return -EOPNOTSUPP;
1077 	}
1078 }
1079 
mlxsw_sp_feature_hw_tc(struct net_device * dev,bool enable)1080 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1081 {
1082 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1083 
1084 	if (!enable) {
1085 		if (mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->ing_flow_block) ||
1086 		    mlxsw_sp_flow_block_rule_count(mlxsw_sp_port->eg_flow_block)) {
1087 			netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1088 			return -EINVAL;
1089 		}
1090 		mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->ing_flow_block);
1091 		mlxsw_sp_flow_block_disable_inc(mlxsw_sp_port->eg_flow_block);
1092 	} else {
1093 		mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->ing_flow_block);
1094 		mlxsw_sp_flow_block_disable_dec(mlxsw_sp_port->eg_flow_block);
1095 	}
1096 	return 0;
1097 }
1098 
mlxsw_sp_feature_loopback(struct net_device * dev,bool enable)1099 static int mlxsw_sp_feature_loopback(struct net_device *dev, bool enable)
1100 {
1101 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1102 	char pplr_pl[MLXSW_REG_PPLR_LEN];
1103 	int err;
1104 
1105 	if (netif_running(dev))
1106 		mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1107 
1108 	mlxsw_reg_pplr_pack(pplr_pl, mlxsw_sp_port->local_port, enable);
1109 	err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr),
1110 			      pplr_pl);
1111 
1112 	if (netif_running(dev))
1113 		mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1114 
1115 	return err;
1116 }
1117 
1118 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1119 
mlxsw_sp_handle_feature(struct net_device * dev,netdev_features_t wanted_features,netdev_features_t feature,mlxsw_sp_feature_handler feature_handler)1120 static int mlxsw_sp_handle_feature(struct net_device *dev,
1121 				   netdev_features_t wanted_features,
1122 				   netdev_features_t feature,
1123 				   mlxsw_sp_feature_handler feature_handler)
1124 {
1125 	netdev_features_t changes = wanted_features ^ dev->features;
1126 	bool enable = !!(wanted_features & feature);
1127 	int err;
1128 
1129 	if (!(changes & feature))
1130 		return 0;
1131 
1132 	err = feature_handler(dev, enable);
1133 	if (err) {
1134 		netdev_err(dev, "%s feature %pNF failed, err %d\n",
1135 			   enable ? "Enable" : "Disable", &feature, err);
1136 		return err;
1137 	}
1138 
1139 	if (enable)
1140 		dev->features |= feature;
1141 	else
1142 		dev->features &= ~feature;
1143 
1144 	return 0;
1145 }
mlxsw_sp_set_features(struct net_device * dev,netdev_features_t features)1146 static int mlxsw_sp_set_features(struct net_device *dev,
1147 				 netdev_features_t features)
1148 {
1149 	netdev_features_t oper_features = dev->features;
1150 	int err = 0;
1151 
1152 	err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1153 				       mlxsw_sp_feature_hw_tc);
1154 	err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_LOOPBACK,
1155 				       mlxsw_sp_feature_loopback);
1156 
1157 	if (err) {
1158 		dev->features = oper_features;
1159 		return -EINVAL;
1160 	}
1161 
1162 	return 0;
1163 }
1164 
mlxsw_sp_port_hwtstamp_set(struct net_device * dev,struct kernel_hwtstamp_config * config,struct netlink_ext_ack * extack)1165 static int mlxsw_sp_port_hwtstamp_set(struct net_device *dev,
1166 				      struct kernel_hwtstamp_config *config,
1167 				      struct netlink_ext_ack *extack)
1168 {
1169 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1170 
1171 	return mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port,
1172 							      config, extack);
1173 }
1174 
mlxsw_sp_port_hwtstamp_get(struct net_device * dev,struct kernel_hwtstamp_config * config)1175 static int mlxsw_sp_port_hwtstamp_get(struct net_device *dev,
1176 				      struct kernel_hwtstamp_config *config)
1177 {
1178 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1179 
1180 	return mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port,
1181 							      config);
1182 }
1183 
mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port * mlxsw_sp_port)1184 static inline void mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port *mlxsw_sp_port)
1185 {
1186 	struct kernel_hwtstamp_config config = {};
1187 
1188 	mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config,
1189 						       NULL);
1190 }
1191 
1192 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1193 	.ndo_open		= mlxsw_sp_port_open,
1194 	.ndo_stop		= mlxsw_sp_port_stop,
1195 	.ndo_start_xmit		= mlxsw_sp_port_xmit,
1196 	.ndo_setup_tc           = mlxsw_sp_setup_tc,
1197 	.ndo_set_rx_mode_async	= mlxsw_sp_set_rx_mode_async,
1198 	.ndo_set_mac_address	= mlxsw_sp_port_set_mac_address,
1199 	.ndo_change_mtu		= mlxsw_sp_port_change_mtu,
1200 	.ndo_get_stats64	= mlxsw_sp_port_get_stats64,
1201 	.ndo_has_offload_stats	= mlxsw_sp_port_has_offload_stats,
1202 	.ndo_get_offload_stats	= mlxsw_sp_port_get_offload_stats,
1203 	.ndo_vlan_rx_add_vid	= mlxsw_sp_port_add_vid,
1204 	.ndo_vlan_rx_kill_vid	= mlxsw_sp_port_kill_vid,
1205 	.ndo_set_features	= mlxsw_sp_set_features,
1206 	.ndo_hwtstamp_get	= mlxsw_sp_port_hwtstamp_get,
1207 	.ndo_hwtstamp_set	= mlxsw_sp_port_hwtstamp_set,
1208 };
1209 
1210 static int
mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port * mlxsw_sp_port)1211 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port)
1212 {
1213 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1214 	u32 eth_proto_cap, eth_proto_admin, eth_proto_oper;
1215 	const struct mlxsw_sp_port_type_speed_ops *ops;
1216 	char ptys_pl[MLXSW_REG_PTYS_LEN];
1217 	u32 eth_proto_cap_masked;
1218 	int err;
1219 
1220 	ops = mlxsw_sp->port_type_speed_ops;
1221 
1222 	/* Set advertised speeds to speeds supported by both the driver
1223 	 * and the device.
1224 	 */
1225 	ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
1226 			       0, false);
1227 	err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1228 	if (err)
1229 		return err;
1230 
1231 	ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, &eth_proto_cap,
1232 				 &eth_proto_admin, &eth_proto_oper);
1233 	eth_proto_cap_masked = ops->ptys_proto_cap_masked_get(eth_proto_cap);
1234 	ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
1235 			       eth_proto_cap_masked,
1236 			       mlxsw_sp_port->link.autoneg);
1237 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1238 }
1239 
mlxsw_sp_port_speed_get(struct mlxsw_sp_port * mlxsw_sp_port,u32 * speed)1240 int mlxsw_sp_port_speed_get(struct mlxsw_sp_port *mlxsw_sp_port, u32 *speed)
1241 {
1242 	const struct mlxsw_sp_port_type_speed_ops *port_type_speed_ops;
1243 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1244 	char ptys_pl[MLXSW_REG_PTYS_LEN];
1245 	u32 eth_proto_oper;
1246 	int err;
1247 
1248 	port_type_speed_ops = mlxsw_sp->port_type_speed_ops;
1249 	port_type_speed_ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl,
1250 					       mlxsw_sp_port->local_port, 0,
1251 					       false);
1252 	err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1253 	if (err)
1254 		return err;
1255 	port_type_speed_ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, NULL, NULL,
1256 						 &eth_proto_oper);
1257 	*speed = port_type_speed_ops->from_ptys_speed(mlxsw_sp, eth_proto_oper);
1258 	return 0;
1259 }
1260 
mlxsw_sp_port_ets_set(struct mlxsw_sp_port * mlxsw_sp_port,enum mlxsw_reg_qeec_hr hr,u8 index,u8 next_index,bool dwrr,u8 dwrr_weight)1261 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
1262 			  enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
1263 			  bool dwrr, u8 dwrr_weight)
1264 {
1265 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1266 	char qeec_pl[MLXSW_REG_QEEC_LEN];
1267 
1268 	mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1269 			    next_index);
1270 	mlxsw_reg_qeec_de_set(qeec_pl, true);
1271 	mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
1272 	mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
1273 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1274 }
1275 
mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port * mlxsw_sp_port,enum mlxsw_reg_qeec_hr hr,u8 index,u8 next_index,u32 maxrate,u8 burst_size)1276 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
1277 				  enum mlxsw_reg_qeec_hr hr, u8 index,
1278 				  u8 next_index, u32 maxrate, u8 burst_size)
1279 {
1280 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1281 	char qeec_pl[MLXSW_REG_QEEC_LEN];
1282 
1283 	mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1284 			    next_index);
1285 	mlxsw_reg_qeec_mase_set(qeec_pl, true);
1286 	mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
1287 	mlxsw_reg_qeec_max_shaper_bs_set(qeec_pl, burst_size);
1288 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1289 }
1290 
mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port * mlxsw_sp_port,enum mlxsw_reg_qeec_hr hr,u8 index,u8 next_index,u32 minrate)1291 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port,
1292 				    enum mlxsw_reg_qeec_hr hr, u8 index,
1293 				    u8 next_index, u32 minrate)
1294 {
1295 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1296 	char qeec_pl[MLXSW_REG_QEEC_LEN];
1297 
1298 	mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1299 			    next_index);
1300 	mlxsw_reg_qeec_mise_set(qeec_pl, true);
1301 	mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate);
1302 
1303 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1304 }
1305 
mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port * mlxsw_sp_port,u8 switch_prio,u8 tclass)1306 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
1307 			      u8 switch_prio, u8 tclass)
1308 {
1309 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1310 	char qtct_pl[MLXSW_REG_QTCT_LEN];
1311 
1312 	mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
1313 			    tclass);
1314 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
1315 }
1316 
mlxsw_sp_port_ets_init(struct mlxsw_sp_port * mlxsw_sp_port)1317 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
1318 {
1319 	int err, i;
1320 
1321 	/* Setup the elements hierarcy, so that each TC is linked to
1322 	 * one subgroup, which are all member in the same group.
1323 	 */
1324 	err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1325 				    MLXSW_REG_QEEC_HR_GROUP, 0, 0, false, 0);
1326 	if (err)
1327 		return err;
1328 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1329 		err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1330 					    MLXSW_REG_QEEC_HR_SUBGROUP, i,
1331 					    0, false, 0);
1332 		if (err)
1333 			return err;
1334 	}
1335 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1336 		err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1337 					    MLXSW_REG_QEEC_HR_TC, i, i,
1338 					    false, 0);
1339 		if (err)
1340 			return err;
1341 
1342 		err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1343 					    MLXSW_REG_QEEC_HR_TC,
1344 					    i + 8, i,
1345 					    true, 100);
1346 		if (err)
1347 			return err;
1348 	}
1349 
1350 	/* Make sure the max shaper is disabled in all hierarchies that support
1351 	 * it. Note that this disables ptps (PTP shaper), but that is intended
1352 	 * for the initial configuration.
1353 	 */
1354 	err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1355 					    MLXSW_REG_QEEC_HR_PORT, 0, 0,
1356 					    MLXSW_REG_QEEC_MAS_DIS, 0);
1357 	if (err)
1358 		return err;
1359 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1360 		err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1361 						    MLXSW_REG_QEEC_HR_SUBGROUP,
1362 						    i, 0,
1363 						    MLXSW_REG_QEEC_MAS_DIS, 0);
1364 		if (err)
1365 			return err;
1366 	}
1367 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1368 		err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1369 						    MLXSW_REG_QEEC_HR_TC,
1370 						    i, i,
1371 						    MLXSW_REG_QEEC_MAS_DIS, 0);
1372 		if (err)
1373 			return err;
1374 
1375 		err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1376 						    MLXSW_REG_QEEC_HR_TC,
1377 						    i + 8, i,
1378 						    MLXSW_REG_QEEC_MAS_DIS, 0);
1379 		if (err)
1380 			return err;
1381 	}
1382 
1383 	/* Configure the min shaper for multicast TCs. */
1384 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1385 		err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port,
1386 					       MLXSW_REG_QEEC_HR_TC,
1387 					       i + 8, i,
1388 					       MLXSW_REG_QEEC_MIS_MIN);
1389 		if (err)
1390 			return err;
1391 	}
1392 
1393 	/* Map all priorities to traffic class 0. */
1394 	for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1395 		err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
1396 		if (err)
1397 			return err;
1398 	}
1399 
1400 	return 0;
1401 }
1402 
mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port * mlxsw_sp_port,bool enable)1403 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
1404 					bool enable)
1405 {
1406 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1407 	char qtctm_pl[MLXSW_REG_QTCTM_LEN];
1408 
1409 	mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
1410 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
1411 }
1412 
mlxsw_sp_port_overheat_init_val_set(struct mlxsw_sp_port * mlxsw_sp_port)1413 static int mlxsw_sp_port_overheat_init_val_set(struct mlxsw_sp_port *mlxsw_sp_port)
1414 {
1415 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1416 	u8 slot_index = mlxsw_sp_port->mapping.slot_index;
1417 	u8 module = mlxsw_sp_port->mapping.module;
1418 	u64 overheat_counter;
1419 	int err;
1420 
1421 	err = mlxsw_env_module_overheat_counter_get(mlxsw_sp->core, slot_index,
1422 						    module, &overheat_counter);
1423 	if (err)
1424 		return err;
1425 
1426 	mlxsw_sp_port->module_overheat_initial_val = overheat_counter;
1427 	return 0;
1428 }
1429 
1430 int
mlxsw_sp_port_vlan_classification_set(struct mlxsw_sp_port * mlxsw_sp_port,bool is_8021ad_tagged,bool is_8021q_tagged)1431 mlxsw_sp_port_vlan_classification_set(struct mlxsw_sp_port *mlxsw_sp_port,
1432 				      bool is_8021ad_tagged,
1433 				      bool is_8021q_tagged)
1434 {
1435 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1436 	char spvc_pl[MLXSW_REG_SPVC_LEN];
1437 
1438 	mlxsw_reg_spvc_pack(spvc_pl, mlxsw_sp_port->local_port,
1439 			    is_8021ad_tagged, is_8021q_tagged);
1440 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvc), spvc_pl);
1441 }
1442 
mlxsw_sp_port_label_info_get(struct mlxsw_sp * mlxsw_sp,u16 local_port,u8 * port_number,u8 * split_port_subnumber,u8 * slot_index)1443 static int mlxsw_sp_port_label_info_get(struct mlxsw_sp *mlxsw_sp,
1444 					u16 local_port, u8 *port_number,
1445 					u8 *split_port_subnumber,
1446 					u8 *slot_index)
1447 {
1448 	char pllp_pl[MLXSW_REG_PLLP_LEN];
1449 	int err;
1450 
1451 	mlxsw_reg_pllp_pack(pllp_pl, local_port);
1452 	err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pllp), pllp_pl);
1453 	if (err)
1454 		return err;
1455 	mlxsw_reg_pllp_unpack(pllp_pl, port_number,
1456 			      split_port_subnumber, slot_index);
1457 	return 0;
1458 }
1459 
mlxsw_sp_port_create(struct mlxsw_sp * mlxsw_sp,u16 local_port,bool split,struct mlxsw_sp_port_mapping * port_mapping)1460 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u16 local_port,
1461 				bool split,
1462 				struct mlxsw_sp_port_mapping *port_mapping)
1463 {
1464 	struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1465 	struct mlxsw_sp_port *mlxsw_sp_port;
1466 	u32 lanes = port_mapping->width;
1467 	u8 split_port_subnumber;
1468 	struct net_device *dev;
1469 	u8 port_number;
1470 	u8 slot_index;
1471 	bool splittable;
1472 	int err;
1473 
1474 	err = mlxsw_sp_port_module_map(mlxsw_sp, local_port, port_mapping);
1475 	if (err) {
1476 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
1477 			local_port);
1478 		return err;
1479 	}
1480 
1481 	err = mlxsw_sp_port_swid_set(mlxsw_sp, local_port, 0);
1482 	if (err) {
1483 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
1484 			local_port);
1485 		goto err_port_swid_set;
1486 	}
1487 
1488 	err = mlxsw_sp_port_label_info_get(mlxsw_sp, local_port, &port_number,
1489 					   &split_port_subnumber, &slot_index);
1490 	if (err) {
1491 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get port label information\n",
1492 			local_port);
1493 		goto err_port_label_info_get;
1494 	}
1495 
1496 	splittable = lanes > 1 && !split;
1497 	err = mlxsw_core_port_init(mlxsw_sp->core, local_port, slot_index,
1498 				   port_number, split, split_port_subnumber,
1499 				   splittable, lanes, mlxsw_sp->base_mac,
1500 				   sizeof(mlxsw_sp->base_mac));
1501 	if (err) {
1502 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
1503 			local_port);
1504 		goto err_core_port_init;
1505 	}
1506 
1507 	dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
1508 	if (!dev) {
1509 		err = -ENOMEM;
1510 		goto err_alloc_etherdev;
1511 	}
1512 	SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
1513 	dev_net_set(dev, mlxsw_sp_net(mlxsw_sp));
1514 	mlxsw_sp_port = netdev_priv(dev);
1515 	mlxsw_core_port_netdev_link(mlxsw_sp->core, local_port,
1516 				    mlxsw_sp_port, dev);
1517 	mlxsw_sp_port->dev = dev;
1518 	mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1519 	mlxsw_sp_port->local_port = local_port;
1520 	mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID;
1521 	mlxsw_sp_port->split = split;
1522 	mlxsw_sp_port->mapping = *port_mapping;
1523 	mlxsw_sp_port->link.autoneg = 1;
1524 	INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
1525 
1526 	mlxsw_sp_port->pcpu_stats =
1527 		netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
1528 	if (!mlxsw_sp_port->pcpu_stats) {
1529 		err = -ENOMEM;
1530 		goto err_alloc_stats;
1531 	}
1532 
1533 	INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
1534 			  &update_stats_cache);
1535 
1536 	dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
1537 	dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
1538 
1539 	err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
1540 	if (err) {
1541 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
1542 			mlxsw_sp_port->local_port);
1543 		goto err_dev_addr_init;
1544 	}
1545 
1546 	netif_carrier_off(dev);
1547 
1548 	dev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_FILTER |
1549 			 NETIF_F_HW_TC | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1550 	dev->hw_features |= NETIF_F_HW_TC | NETIF_F_LOOPBACK |
1551 			    NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1552 	dev->vlan_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1553 	dev->lltx = true;
1554 	dev->netns_immutable = true;
1555 	dev->request_ops_lock = true;
1556 
1557 	dev->min_mtu = ETH_MIN_MTU;
1558 	dev->max_mtu = MLXSW_PORT_MAX_MTU - MLXSW_PORT_ETH_FRAME_HDR;
1559 
1560 	/* Each packet needs to have a Tx header (metadata) on top all other
1561 	 * headers.
1562 	 */
1563 	dev->needed_headroom = MLXSW_TXHDR_LEN;
1564 
1565 	err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
1566 	if (err) {
1567 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1568 			mlxsw_sp_port->local_port);
1569 		goto err_port_system_port_mapping_set;
1570 	}
1571 
1572 	err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port);
1573 	if (err) {
1574 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
1575 			mlxsw_sp_port->local_port);
1576 		goto err_port_speed_by_width_set;
1577 	}
1578 
1579 	err = mlxsw_sp->port_type_speed_ops->ptys_max_speed(mlxsw_sp_port,
1580 							    &mlxsw_sp_port->max_speed);
1581 	if (err) {
1582 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to get maximum speed\n",
1583 			mlxsw_sp_port->local_port);
1584 		goto err_max_speed_get;
1585 	}
1586 
1587 	err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
1588 	if (err) {
1589 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
1590 			mlxsw_sp_port->local_port);
1591 		goto err_port_mtu_set;
1592 	}
1593 
1594 	err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1595 	if (err)
1596 		goto err_port_admin_status_set;
1597 
1598 	err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
1599 	if (err) {
1600 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
1601 			mlxsw_sp_port->local_port);
1602 		goto err_port_buffers_init;
1603 	}
1604 
1605 	err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
1606 	if (err) {
1607 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
1608 			mlxsw_sp_port->local_port);
1609 		goto err_port_ets_init;
1610 	}
1611 
1612 	err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
1613 	if (err) {
1614 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
1615 			mlxsw_sp_port->local_port);
1616 		goto err_port_tc_mc_mode;
1617 	}
1618 
1619 	/* ETS and buffers must be initialized before DCB. */
1620 	err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
1621 	if (err) {
1622 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
1623 			mlxsw_sp_port->local_port);
1624 		goto err_port_dcb_init;
1625 	}
1626 
1627 	err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
1628 	if (err) {
1629 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
1630 			mlxsw_sp_port->local_port);
1631 		goto err_port_fids_init;
1632 	}
1633 
1634 	err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
1635 	if (err) {
1636 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
1637 			mlxsw_sp_port->local_port);
1638 		goto err_port_qdiscs_init;
1639 	}
1640 
1641 	err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 0, VLAN_N_VID - 1, false,
1642 				     false);
1643 	if (err) {
1644 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n",
1645 			mlxsw_sp_port->local_port);
1646 		goto err_port_vlan_clear;
1647 	}
1648 
1649 	err = mlxsw_sp_port_nve_init(mlxsw_sp_port);
1650 	if (err) {
1651 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n",
1652 			mlxsw_sp_port->local_port);
1653 		goto err_port_nve_init;
1654 	}
1655 
1656 	err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID,
1657 				     ETH_P_8021Q);
1658 	if (err) {
1659 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n",
1660 			mlxsw_sp_port->local_port);
1661 		goto err_port_pvid_set;
1662 	}
1663 
1664 	mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port,
1665 						       MLXSW_SP_DEFAULT_VID);
1666 	if (IS_ERR(mlxsw_sp_port_vlan)) {
1667 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
1668 			mlxsw_sp_port->local_port);
1669 		err = PTR_ERR(mlxsw_sp_port_vlan);
1670 		goto err_port_vlan_create;
1671 	}
1672 	mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan;
1673 
1674 	/* Set SPVC.et0=true and SPVC.et1=false to make the local port to treat
1675 	 * only packets with 802.1q header as tagged packets.
1676 	 */
1677 	err = mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, false, true);
1678 	if (err) {
1679 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set default VLAN classification\n",
1680 			local_port);
1681 		goto err_port_vlan_classification_set;
1682 	}
1683 
1684 	INIT_DELAYED_WORK(&mlxsw_sp_port->ptp.shaper_dw,
1685 			  mlxsw_sp->ptp_ops->shaper_work);
1686 
1687 	mlxsw_sp->ports[local_port] = mlxsw_sp_port;
1688 
1689 	err = mlxsw_sp_port_overheat_init_val_set(mlxsw_sp_port);
1690 	if (err) {
1691 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set overheat initial value\n",
1692 			mlxsw_sp_port->local_port);
1693 		goto err_port_overheat_init_val_set;
1694 	}
1695 
1696 	err = register_netdev(dev);
1697 	if (err) {
1698 		dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
1699 			mlxsw_sp_port->local_port);
1700 		goto err_register_netdev;
1701 	}
1702 
1703 	mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
1704 	return 0;
1705 
1706 err_register_netdev:
1707 err_port_overheat_init_val_set:
1708 	mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true);
1709 err_port_vlan_classification_set:
1710 	mlxsw_sp->ports[local_port] = NULL;
1711 	mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1712 err_port_vlan_create:
1713 err_port_pvid_set:
1714 	mlxsw_sp_port_nve_fini(mlxsw_sp_port);
1715 err_port_nve_init:
1716 err_port_vlan_clear:
1717 	mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
1718 err_port_qdiscs_init:
1719 	mlxsw_sp_port_fids_fini(mlxsw_sp_port);
1720 err_port_fids_init:
1721 	mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
1722 err_port_dcb_init:
1723 	mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
1724 err_port_tc_mc_mode:
1725 err_port_ets_init:
1726 	mlxsw_sp_port_buffers_fini(mlxsw_sp_port);
1727 err_port_buffers_init:
1728 err_port_admin_status_set:
1729 err_port_mtu_set:
1730 err_max_speed_get:
1731 err_port_speed_by_width_set:
1732 err_port_system_port_mapping_set:
1733 err_dev_addr_init:
1734 	free_percpu(mlxsw_sp_port->pcpu_stats);
1735 err_alloc_stats:
1736 	free_netdev(dev);
1737 err_alloc_etherdev:
1738 	mlxsw_core_port_fini(mlxsw_sp->core, local_port);
1739 err_core_port_init:
1740 err_port_label_info_get:
1741 	mlxsw_sp_port_swid_set(mlxsw_sp, local_port,
1742 			       MLXSW_PORT_SWID_DISABLED_PORT);
1743 err_port_swid_set:
1744 	mlxsw_sp_port_module_unmap(mlxsw_sp, local_port,
1745 				   port_mapping->slot_index,
1746 				   port_mapping->module);
1747 	return err;
1748 }
1749 
mlxsw_sp_port_remove(struct mlxsw_sp * mlxsw_sp,u16 local_port)1750 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u16 local_port)
1751 {
1752 	struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
1753 	u8 slot_index = mlxsw_sp_port->mapping.slot_index;
1754 	u8 module = mlxsw_sp_port->mapping.module;
1755 
1756 	cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
1757 	cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw);
1758 	unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
1759 	mlxsw_sp_port_ptp_clear(mlxsw_sp_port);
1760 	mlxsw_sp_port_vlan_classification_set(mlxsw_sp_port, true, true);
1761 	mlxsw_sp->ports[local_port] = NULL;
1762 	mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true);
1763 	mlxsw_sp_port_nve_fini(mlxsw_sp_port);
1764 	mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
1765 	mlxsw_sp_port_fids_fini(mlxsw_sp_port);
1766 	mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
1767 	mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
1768 	mlxsw_sp_port_buffers_fini(mlxsw_sp_port);
1769 	free_percpu(mlxsw_sp_port->pcpu_stats);
1770 	WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
1771 	free_netdev(mlxsw_sp_port->dev);
1772 	mlxsw_core_port_fini(mlxsw_sp->core, local_port);
1773 	mlxsw_sp_port_swid_set(mlxsw_sp, local_port,
1774 			       MLXSW_PORT_SWID_DISABLED_PORT);
1775 	mlxsw_sp_port_module_unmap(mlxsw_sp, local_port, slot_index, module);
1776 }
1777 
mlxsw_sp_cpu_port_create(struct mlxsw_sp * mlxsw_sp)1778 static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp)
1779 {
1780 	struct mlxsw_sp_port *mlxsw_sp_port;
1781 	int err;
1782 
1783 	mlxsw_sp_port = kzalloc_obj(*mlxsw_sp_port);
1784 	if (!mlxsw_sp_port)
1785 		return -ENOMEM;
1786 
1787 	mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1788 	mlxsw_sp_port->local_port = MLXSW_PORT_CPU_PORT;
1789 
1790 	err = mlxsw_core_cpu_port_init(mlxsw_sp->core,
1791 				       mlxsw_sp_port,
1792 				       mlxsw_sp->base_mac,
1793 				       sizeof(mlxsw_sp->base_mac));
1794 	if (err) {
1795 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n");
1796 		goto err_core_cpu_port_init;
1797 	}
1798 
1799 	mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port;
1800 	return 0;
1801 
1802 err_core_cpu_port_init:
1803 	kfree(mlxsw_sp_port);
1804 	return err;
1805 }
1806 
mlxsw_sp_cpu_port_remove(struct mlxsw_sp * mlxsw_sp)1807 static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp)
1808 {
1809 	struct mlxsw_sp_port *mlxsw_sp_port =
1810 				mlxsw_sp->ports[MLXSW_PORT_CPU_PORT];
1811 
1812 	mlxsw_core_cpu_port_fini(mlxsw_sp->core);
1813 	mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL;
1814 	kfree(mlxsw_sp_port);
1815 }
1816 
mlxsw_sp_local_port_valid(u16 local_port)1817 static bool mlxsw_sp_local_port_valid(u16 local_port)
1818 {
1819 	return local_port != MLXSW_PORT_CPU_PORT;
1820 }
1821 
mlxsw_sp_port_created(struct mlxsw_sp * mlxsw_sp,u16 local_port)1822 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u16 local_port)
1823 {
1824 	if (!mlxsw_sp_local_port_valid(local_port))
1825 		return false;
1826 	return mlxsw_sp->ports[local_port] != NULL;
1827 }
1828 
mlxsw_sp_port_mapping_event_set(struct mlxsw_sp * mlxsw_sp,u16 local_port,bool enable)1829 static int mlxsw_sp_port_mapping_event_set(struct mlxsw_sp *mlxsw_sp,
1830 					   u16 local_port, bool enable)
1831 {
1832 	char pmecr_pl[MLXSW_REG_PMECR_LEN];
1833 
1834 	mlxsw_reg_pmecr_pack(pmecr_pl, local_port,
1835 			     enable ? MLXSW_REG_PMECR_E_GENERATE_EVENT :
1836 				      MLXSW_REG_PMECR_E_DO_NOT_GENERATE_EVENT);
1837 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmecr), pmecr_pl);
1838 }
1839 
1840 struct mlxsw_sp_port_mapping_event {
1841 	struct list_head list;
1842 	char pmlp_pl[MLXSW_REG_PMLP_LEN];
1843 };
1844 
mlxsw_sp_port_mapping_events_work(struct work_struct * work)1845 static void mlxsw_sp_port_mapping_events_work(struct work_struct *work)
1846 {
1847 	struct mlxsw_sp_port_mapping_event *event, *next_event;
1848 	struct mlxsw_sp_port_mapping_events *events;
1849 	struct mlxsw_sp_port_mapping port_mapping;
1850 	struct mlxsw_sp *mlxsw_sp;
1851 	struct devlink *devlink;
1852 	LIST_HEAD(event_queue);
1853 	u16 local_port;
1854 	int err;
1855 
1856 	events = container_of(work, struct mlxsw_sp_port_mapping_events, work);
1857 	mlxsw_sp = container_of(events, struct mlxsw_sp, port_mapping_events);
1858 	devlink = priv_to_devlink(mlxsw_sp->core);
1859 
1860 	spin_lock_bh(&events->queue_lock);
1861 	list_splice_init(&events->queue, &event_queue);
1862 	spin_unlock_bh(&events->queue_lock);
1863 
1864 	list_for_each_entry_safe(event, next_event, &event_queue, list) {
1865 		local_port = mlxsw_reg_pmlp_local_port_get(event->pmlp_pl);
1866 		err = mlxsw_sp_port_module_info_parse(mlxsw_sp, local_port,
1867 						      event->pmlp_pl, &port_mapping);
1868 		if (err)
1869 			goto out;
1870 
1871 		if (WARN_ON_ONCE(!port_mapping.width))
1872 			goto out;
1873 
1874 		devl_lock(devlink);
1875 
1876 		if (!mlxsw_sp_port_created(mlxsw_sp, local_port))
1877 			mlxsw_sp_port_create(mlxsw_sp, local_port,
1878 					     false, &port_mapping);
1879 		else
1880 			WARN_ON_ONCE(1);
1881 
1882 		devl_unlock(devlink);
1883 
1884 		mlxsw_sp->port_mapping[local_port] = port_mapping;
1885 
1886 out:
1887 		kfree(event);
1888 	}
1889 }
1890 
1891 static void
mlxsw_sp_port_mapping_listener_func(const struct mlxsw_reg_info * reg,char * pmlp_pl,void * priv)1892 mlxsw_sp_port_mapping_listener_func(const struct mlxsw_reg_info *reg,
1893 				    char *pmlp_pl, void *priv)
1894 {
1895 	struct mlxsw_sp_port_mapping_events *events;
1896 	struct mlxsw_sp_port_mapping_event *event;
1897 	struct mlxsw_sp *mlxsw_sp = priv;
1898 	u16 local_port;
1899 
1900 	local_port = mlxsw_reg_pmlp_local_port_get(pmlp_pl);
1901 	if (WARN_ON_ONCE(!mlxsw_sp_local_port_is_valid(mlxsw_sp, local_port)))
1902 		return;
1903 
1904 	events = &mlxsw_sp->port_mapping_events;
1905 	event = kmalloc_obj(*event, GFP_ATOMIC);
1906 	if (!event)
1907 		return;
1908 	memcpy(event->pmlp_pl, pmlp_pl, sizeof(event->pmlp_pl));
1909 	spin_lock(&events->queue_lock);
1910 	list_add_tail(&event->list, &events->queue);
1911 	spin_unlock(&events->queue_lock);
1912 	mlxsw_core_schedule_work(&events->work);
1913 }
1914 
1915 static void
__mlxsw_sp_port_mapping_events_cancel(struct mlxsw_sp * mlxsw_sp)1916 __mlxsw_sp_port_mapping_events_cancel(struct mlxsw_sp *mlxsw_sp)
1917 {
1918 	struct mlxsw_sp_port_mapping_event *event, *next_event;
1919 	struct mlxsw_sp_port_mapping_events *events;
1920 
1921 	events = &mlxsw_sp->port_mapping_events;
1922 
1923 	/* Caller needs to make sure that no new event is going to appear. */
1924 	cancel_work_sync(&events->work);
1925 	list_for_each_entry_safe(event, next_event, &events->queue, list) {
1926 		list_del(&event->list);
1927 		kfree(event);
1928 	}
1929 }
1930 
mlxsw_sp_ports_remove(struct mlxsw_sp * mlxsw_sp)1931 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
1932 {
1933 	unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
1934 	int i;
1935 
1936 	for (i = 1; i < max_ports; i++)
1937 		mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, false);
1938 	/* Make sure all scheduled events are processed */
1939 	__mlxsw_sp_port_mapping_events_cancel(mlxsw_sp);
1940 
1941 	for (i = 1; i < max_ports; i++)
1942 		if (mlxsw_sp_port_created(mlxsw_sp, i))
1943 			mlxsw_sp_port_remove(mlxsw_sp, i);
1944 	mlxsw_sp_cpu_port_remove(mlxsw_sp);
1945 	kfree(mlxsw_sp->ports);
1946 	mlxsw_sp->ports = NULL;
1947 }
1948 
1949 static void
mlxsw_sp_ports_remove_selected(struct mlxsw_core * mlxsw_core,bool (* selector)(void * priv,u16 local_port),void * priv)1950 mlxsw_sp_ports_remove_selected(struct mlxsw_core *mlxsw_core,
1951 			       bool (*selector)(void *priv, u16 local_port),
1952 			       void *priv)
1953 {
1954 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
1955 	unsigned int max_ports = mlxsw_core_max_ports(mlxsw_core);
1956 	int i;
1957 
1958 	for (i = 1; i < max_ports; i++)
1959 		if (mlxsw_sp_port_created(mlxsw_sp, i) && selector(priv, i))
1960 			mlxsw_sp_port_remove(mlxsw_sp, i);
1961 }
1962 
mlxsw_sp_ports_create(struct mlxsw_sp * mlxsw_sp)1963 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
1964 {
1965 	unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
1966 	struct mlxsw_sp_port_mapping_events *events;
1967 	struct mlxsw_sp_port_mapping *port_mapping;
1968 	size_t alloc_size;
1969 	int i;
1970 	int err;
1971 
1972 	alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
1973 	mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
1974 	if (!mlxsw_sp->ports)
1975 		return -ENOMEM;
1976 
1977 	events = &mlxsw_sp->port_mapping_events;
1978 	INIT_LIST_HEAD(&events->queue);
1979 	spin_lock_init(&events->queue_lock);
1980 	INIT_WORK(&events->work, mlxsw_sp_port_mapping_events_work);
1981 
1982 	for (i = 1; i < max_ports; i++) {
1983 		err = mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, true);
1984 		if (err)
1985 			goto err_event_enable;
1986 	}
1987 
1988 	err = mlxsw_sp_cpu_port_create(mlxsw_sp);
1989 	if (err)
1990 		goto err_cpu_port_create;
1991 
1992 	for (i = 1; i < max_ports; i++) {
1993 		port_mapping = &mlxsw_sp->port_mapping[i];
1994 		if (!port_mapping->width)
1995 			continue;
1996 		err = mlxsw_sp_port_create(mlxsw_sp, i, false, port_mapping);
1997 		if (err)
1998 			goto err_port_create;
1999 	}
2000 	return 0;
2001 
2002 err_port_create:
2003 	for (i--; i >= 1; i--)
2004 		if (mlxsw_sp_port_created(mlxsw_sp, i))
2005 			mlxsw_sp_port_remove(mlxsw_sp, i);
2006 	i = max_ports;
2007 	mlxsw_sp_cpu_port_remove(mlxsw_sp);
2008 err_cpu_port_create:
2009 err_event_enable:
2010 	for (i--; i >= 1; i--)
2011 		mlxsw_sp_port_mapping_event_set(mlxsw_sp, i, false);
2012 	/* Make sure all scheduled events are processed */
2013 	__mlxsw_sp_port_mapping_events_cancel(mlxsw_sp);
2014 	kfree(mlxsw_sp->ports);
2015 	mlxsw_sp->ports = NULL;
2016 	return err;
2017 }
2018 
mlxsw_sp_port_module_info_init(struct mlxsw_sp * mlxsw_sp)2019 static int mlxsw_sp_port_module_info_init(struct mlxsw_sp *mlxsw_sp)
2020 {
2021 	unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
2022 	struct mlxsw_sp_port_mapping *port_mapping;
2023 	int i;
2024 	int err;
2025 
2026 	mlxsw_sp->port_mapping = kzalloc_objs(struct mlxsw_sp_port_mapping,
2027 					      max_ports);
2028 	if (!mlxsw_sp->port_mapping)
2029 		return -ENOMEM;
2030 
2031 	for (i = 1; i < max_ports; i++) {
2032 		port_mapping = &mlxsw_sp->port_mapping[i];
2033 		err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, port_mapping);
2034 		if (err)
2035 			goto err_port_module_info_get;
2036 	}
2037 	return 0;
2038 
2039 err_port_module_info_get:
2040 	kfree(mlxsw_sp->port_mapping);
2041 	return err;
2042 }
2043 
mlxsw_sp_port_module_info_fini(struct mlxsw_sp * mlxsw_sp)2044 static void mlxsw_sp_port_module_info_fini(struct mlxsw_sp *mlxsw_sp)
2045 {
2046 	kfree(mlxsw_sp->port_mapping);
2047 }
2048 
2049 static int
mlxsw_sp_port_split_create(struct mlxsw_sp * mlxsw_sp,struct mlxsw_sp_port_mapping * port_mapping,unsigned int count,const char * pmtdb_pl)2050 mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp,
2051 			   struct mlxsw_sp_port_mapping *port_mapping,
2052 			   unsigned int count, const char *pmtdb_pl)
2053 {
2054 	struct mlxsw_sp_port_mapping split_port_mapping;
2055 	int err, i;
2056 
2057 	split_port_mapping = *port_mapping;
2058 	split_port_mapping.width /= count;
2059 	for (i = 0; i < count; i++) {
2060 		u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
2061 
2062 		if (!mlxsw_sp_local_port_valid(s_local_port))
2063 			continue;
2064 
2065 		err = mlxsw_sp_port_create(mlxsw_sp, s_local_port,
2066 					   true, &split_port_mapping);
2067 		if (err)
2068 			goto err_port_create;
2069 		split_port_mapping.lane += split_port_mapping.width;
2070 	}
2071 
2072 	return 0;
2073 
2074 err_port_create:
2075 	for (i--; i >= 0; i--) {
2076 		u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
2077 
2078 		if (mlxsw_sp_port_created(mlxsw_sp, s_local_port))
2079 			mlxsw_sp_port_remove(mlxsw_sp, s_local_port);
2080 	}
2081 	return err;
2082 }
2083 
mlxsw_sp_port_unsplit_create(struct mlxsw_sp * mlxsw_sp,unsigned int count,const char * pmtdb_pl)2084 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
2085 					 unsigned int count,
2086 					 const char *pmtdb_pl)
2087 {
2088 	struct mlxsw_sp_port_mapping *port_mapping;
2089 	int i;
2090 
2091 	/* Go over original unsplit ports in the gap and recreate them. */
2092 	for (i = 0; i < count; i++) {
2093 		u16 local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
2094 
2095 		port_mapping = &mlxsw_sp->port_mapping[local_port];
2096 		if (!port_mapping->width || !mlxsw_sp_local_port_valid(local_port))
2097 			continue;
2098 		mlxsw_sp_port_create(mlxsw_sp, local_port,
2099 				     false, port_mapping);
2100 	}
2101 }
2102 
2103 static struct mlxsw_sp_port *
mlxsw_sp_port_get_by_local_port(struct mlxsw_sp * mlxsw_sp,u16 local_port)2104 mlxsw_sp_port_get_by_local_port(struct mlxsw_sp *mlxsw_sp, u16 local_port)
2105 {
2106 	if (mlxsw_sp->ports && mlxsw_sp->ports[local_port])
2107 		return mlxsw_sp->ports[local_port];
2108 	return NULL;
2109 }
2110 
mlxsw_sp_port_split(struct mlxsw_core * mlxsw_core,u16 local_port,unsigned int count,struct netlink_ext_ack * extack)2111 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u16 local_port,
2112 			       unsigned int count,
2113 			       struct netlink_ext_ack *extack)
2114 {
2115 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2116 	struct mlxsw_sp_port_mapping port_mapping;
2117 	struct mlxsw_sp_port *mlxsw_sp_port;
2118 	enum mlxsw_reg_pmtdb_status status;
2119 	char pmtdb_pl[MLXSW_REG_PMTDB_LEN];
2120 	int i;
2121 	int err;
2122 
2123 	mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
2124 	if (!mlxsw_sp_port) {
2125 		dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2126 			local_port);
2127 		NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
2128 		return -EINVAL;
2129 	}
2130 
2131 	if (mlxsw_sp_port->split) {
2132 		NL_SET_ERR_MSG_MOD(extack, "Port is already split");
2133 		return -EINVAL;
2134 	}
2135 
2136 	mlxsw_reg_pmtdb_pack(pmtdb_pl, mlxsw_sp_port->mapping.slot_index,
2137 			     mlxsw_sp_port->mapping.module,
2138 			     mlxsw_sp_port->mapping.module_width / count,
2139 			     count);
2140 	err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl);
2141 	if (err) {
2142 		NL_SET_ERR_MSG_MOD(extack, "Failed to query split info");
2143 		return err;
2144 	}
2145 
2146 	status = mlxsw_reg_pmtdb_status_get(pmtdb_pl);
2147 	if (status != MLXSW_REG_PMTDB_STATUS_SUCCESS) {
2148 		NL_SET_ERR_MSG_MOD(extack, "Unsupported split configuration");
2149 		return -EINVAL;
2150 	}
2151 
2152 	port_mapping = mlxsw_sp_port->mapping;
2153 
2154 	for (i = 0; i < count; i++) {
2155 		u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
2156 
2157 		if (mlxsw_sp_port_created(mlxsw_sp, s_local_port))
2158 			mlxsw_sp_port_remove(mlxsw_sp, s_local_port);
2159 	}
2160 
2161 	err = mlxsw_sp_port_split_create(mlxsw_sp, &port_mapping,
2162 					 count, pmtdb_pl);
2163 	if (err) {
2164 		dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2165 		goto err_port_split_create;
2166 	}
2167 
2168 	return 0;
2169 
2170 err_port_split_create:
2171 	mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl);
2172 
2173 	return err;
2174 }
2175 
mlxsw_sp_port_unsplit(struct mlxsw_core * mlxsw_core,u16 local_port,struct netlink_ext_ack * extack)2176 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u16 local_port,
2177 				 struct netlink_ext_ack *extack)
2178 {
2179 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2180 	struct mlxsw_sp_port *mlxsw_sp_port;
2181 	char pmtdb_pl[MLXSW_REG_PMTDB_LEN];
2182 	unsigned int count;
2183 	int i;
2184 	int err;
2185 
2186 	mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
2187 	if (!mlxsw_sp_port) {
2188 		dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2189 			local_port);
2190 		NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
2191 		return -EINVAL;
2192 	}
2193 
2194 	if (!mlxsw_sp_port->split) {
2195 		NL_SET_ERR_MSG_MOD(extack, "Port was not split");
2196 		return -EINVAL;
2197 	}
2198 
2199 	count = mlxsw_sp_port->mapping.module_width /
2200 		mlxsw_sp_port->mapping.width;
2201 
2202 	mlxsw_reg_pmtdb_pack(pmtdb_pl, mlxsw_sp_port->mapping.slot_index,
2203 			     mlxsw_sp_port->mapping.module,
2204 			     mlxsw_sp_port->mapping.module_width / count,
2205 			     count);
2206 	err = mlxsw_reg_query(mlxsw_core, MLXSW_REG(pmtdb), pmtdb_pl);
2207 	if (err) {
2208 		NL_SET_ERR_MSG_MOD(extack, "Failed to query split info");
2209 		return err;
2210 	}
2211 
2212 	for (i = 0; i < count; i++) {
2213 		u16 s_local_port = mlxsw_reg_pmtdb_port_num_get(pmtdb_pl, i);
2214 
2215 		if (mlxsw_sp_port_created(mlxsw_sp, s_local_port))
2216 			mlxsw_sp_port_remove(mlxsw_sp, s_local_port);
2217 	}
2218 
2219 	mlxsw_sp_port_unsplit_create(mlxsw_sp, count, pmtdb_pl);
2220 
2221 	return 0;
2222 }
2223 
2224 static void
mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port * mlxsw_sp_port)2225 mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port *mlxsw_sp_port)
2226 {
2227 	int i;
2228 
2229 	for (i = 0; i < TC_MAX_QUEUE; i++)
2230 		mlxsw_sp_port->periodic_hw_stats.xstats.backlog[i] = 0;
2231 }
2232 
mlxsw_sp_pude_event_func(const struct mlxsw_reg_info * reg,char * pude_pl,void * priv)2233 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2234 				     char *pude_pl, void *priv)
2235 {
2236 	struct mlxsw_sp *mlxsw_sp = priv;
2237 	struct mlxsw_sp_port *mlxsw_sp_port;
2238 	enum mlxsw_reg_pude_oper_status status;
2239 	u16 local_port;
2240 
2241 	local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2242 
2243 	if (WARN_ON_ONCE(!mlxsw_sp_local_port_is_valid(mlxsw_sp, local_port)))
2244 		return;
2245 	mlxsw_sp_port = mlxsw_sp->ports[local_port];
2246 	if (!mlxsw_sp_port)
2247 		return;
2248 
2249 	status = mlxsw_reg_pude_oper_status_get(pude_pl);
2250 	if (status == MLXSW_PORT_OPER_STATUS_UP) {
2251 		netdev_info(mlxsw_sp_port->dev, "link up\n");
2252 		netif_carrier_on(mlxsw_sp_port->dev);
2253 		mlxsw_core_schedule_dw(&mlxsw_sp_port->ptp.shaper_dw, 0);
2254 	} else {
2255 		netdev_info(mlxsw_sp_port->dev, "link down\n");
2256 		netif_carrier_off(mlxsw_sp_port->dev);
2257 		mlxsw_sp_port_down_wipe_counters(mlxsw_sp_port);
2258 	}
2259 }
2260 
mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp * mlxsw_sp,char * mtpptr_pl,bool ingress)2261 static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp,
2262 					  char *mtpptr_pl, bool ingress)
2263 {
2264 	u16 local_port;
2265 	u8 num_rec;
2266 	int i;
2267 
2268 	local_port = mlxsw_reg_mtpptr_local_port_get(mtpptr_pl);
2269 	num_rec = mlxsw_reg_mtpptr_num_rec_get(mtpptr_pl);
2270 	for (i = 0; i < num_rec; i++) {
2271 		u8 domain_number;
2272 		u8 message_type;
2273 		u16 sequence_id;
2274 		u64 timestamp;
2275 
2276 		mlxsw_reg_mtpptr_unpack(mtpptr_pl, i, &message_type,
2277 					&domain_number, &sequence_id,
2278 					&timestamp);
2279 		mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port,
2280 					    message_type, domain_number,
2281 					    sequence_id, timestamp);
2282 	}
2283 }
2284 
mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info * reg,char * mtpptr_pl,void * priv)2285 static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg,
2286 					      char *mtpptr_pl, void *priv)
2287 {
2288 	struct mlxsw_sp *mlxsw_sp = priv;
2289 
2290 	mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true);
2291 }
2292 
mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info * reg,char * mtpptr_pl,void * priv)2293 static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg,
2294 					      char *mtpptr_pl, void *priv)
2295 {
2296 	struct mlxsw_sp *mlxsw_sp = priv;
2297 
2298 	mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false);
2299 }
2300 
mlxsw_sp_rx_listener_no_mark_func(struct sk_buff * skb,u16 local_port,void * priv)2301 void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
2302 				       u16 local_port, void *priv)
2303 {
2304 	struct mlxsw_sp *mlxsw_sp = priv;
2305 	struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2306 	struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2307 
2308 	if (unlikely(!mlxsw_sp_port)) {
2309 		dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2310 				     local_port);
2311 		return;
2312 	}
2313 
2314 	skb->dev = mlxsw_sp_port->dev;
2315 
2316 	pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2317 	u64_stats_update_begin(&pcpu_stats->syncp);
2318 	pcpu_stats->rx_packets++;
2319 	pcpu_stats->rx_bytes += skb->len;
2320 	u64_stats_update_end(&pcpu_stats->syncp);
2321 
2322 	skb->protocol = eth_type_trans(skb, skb->dev);
2323 	napi_gro_receive(mlxsw_skb_cb(skb)->rx_md_info.napi, skb);
2324 }
2325 
mlxsw_sp_rx_listener_mark_func(struct sk_buff * skb,u16 local_port,void * priv)2326 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u16 local_port,
2327 					   void *priv)
2328 {
2329 	skb->offload_fwd_mark = 1;
2330 	return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
2331 }
2332 
mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff * skb,u16 local_port,void * priv)2333 static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb,
2334 					      u16 local_port, void *priv)
2335 {
2336 	skb->offload_l3_fwd_mark = 1;
2337 	skb->offload_fwd_mark = 1;
2338 	return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
2339 }
2340 
mlxsw_sp_ptp_receive(struct mlxsw_sp * mlxsw_sp,struct sk_buff * skb,u16 local_port)2341 void mlxsw_sp_ptp_receive(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
2342 			  u16 local_port)
2343 {
2344 	mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port);
2345 }
2346 
2347 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl)	\
2348 	MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action,	\
2349 		  _is_ctrl, SP_##_trap_group, DISCARD)
2350 
2351 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl)	\
2352 	MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action,	\
2353 		_is_ctrl, SP_##_trap_group, DISCARD)
2354 
2355 #define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl)	\
2356 	MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action,	\
2357 		_is_ctrl, SP_##_trap_group, DISCARD)
2358 
2359 #define MLXSW_SP_EVENTL(_func, _trap_id)		\
2360 	MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
2361 
2362 static const struct mlxsw_listener mlxsw_sp_listener[] = {
2363 	/* Events */
2364 	MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
2365 	/* L2 traps */
2366 	MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, FID_MISS, false),
2367 	/* L3 traps */
2368 	MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
2369 			  false),
2370 	MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
2371 	MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
2372 			  false),
2373 	MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_CLASS_E, FORWARD,
2374 			     ROUTER_EXP, false),
2375 	MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_MC_DMAC, FORWARD,
2376 			     ROUTER_EXP, false),
2377 	MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_DIP, FORWARD,
2378 			     ROUTER_EXP, false),
2379 	MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_DIP_LINK_LOCAL, FORWARD,
2380 			     ROUTER_EXP, false),
2381 	MLXSW_SP_RXL_NO_MARK(DISCARD_ING_ROUTER_SIP_LINK_LOCAL, FORWARD,
2382 			     ROUTER_EXP, false),
2383 	/* Multicast Router Traps */
2384 	MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
2385 	MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
2386 };
2387 
2388 static const struct mlxsw_listener mlxsw_sp1_listener[] = {
2389 	/* Events */
2390 	MLXSW_EVENTL(mlxsw_sp1_ptp_egr_fifo_event_func, PTP_EGR_FIFO, SP_PTP0),
2391 	MLXSW_EVENTL(mlxsw_sp1_ptp_ing_fifo_event_func, PTP_ING_FIFO, SP_PTP0),
2392 };
2393 
2394 static const struct mlxsw_listener mlxsw_sp2_listener[] = {
2395 	/* Events */
2396 	MLXSW_SP_EVENTL(mlxsw_sp_port_mapping_listener_func, PMLPE),
2397 };
2398 
mlxsw_sp_cpu_policers_set(struct mlxsw_core * mlxsw_core)2399 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
2400 {
2401 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
2402 	char qpcr_pl[MLXSW_REG_QPCR_LEN];
2403 	enum mlxsw_reg_qpcr_ir_units ir_units;
2404 	int max_cpu_policers;
2405 	bool is_bytes;
2406 	u8 burst_size;
2407 	u32 rate;
2408 	int i, err;
2409 
2410 	if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
2411 		return -EIO;
2412 
2413 	max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
2414 
2415 	ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
2416 	for (i = 0; i < max_cpu_policers; i++) {
2417 		is_bytes = false;
2418 		switch (i) {
2419 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
2420 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
2421 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS:
2422 			rate = 1024;
2423 			burst_size = 7;
2424 			break;
2425 		default:
2426 			continue;
2427 		}
2428 
2429 		__set_bit(i, mlxsw_sp->trap->policers_usage);
2430 		mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
2431 				    burst_size);
2432 		err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
2433 		if (err)
2434 			return err;
2435 	}
2436 
2437 	return 0;
2438 }
2439 
mlxsw_sp_trap_groups_set(struct mlxsw_core * mlxsw_core)2440 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
2441 {
2442 	char htgt_pl[MLXSW_REG_HTGT_LEN];
2443 	enum mlxsw_reg_htgt_trap_group i;
2444 	int max_cpu_policers;
2445 	int max_trap_groups;
2446 	u8 priority, tc;
2447 	u16 policer_id;
2448 	int err;
2449 
2450 	if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
2451 		return -EIO;
2452 
2453 	max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
2454 	max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
2455 
2456 	for (i = 0; i < max_trap_groups; i++) {
2457 		policer_id = i;
2458 		switch (i) {
2459 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
2460 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
2461 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS:
2462 			priority = 1;
2463 			tc = 1;
2464 			break;
2465 		case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
2466 			priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
2467 			tc = MLXSW_REG_HTGT_DEFAULT_TC;
2468 			policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
2469 			break;
2470 		default:
2471 			continue;
2472 		}
2473 
2474 		if (max_cpu_policers <= policer_id &&
2475 		    policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
2476 			return -EIO;
2477 
2478 		mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
2479 		err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
2480 		if (err)
2481 			return err;
2482 	}
2483 
2484 	return 0;
2485 }
2486 
mlxsw_sp_traps_init(struct mlxsw_sp * mlxsw_sp)2487 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2488 {
2489 	struct mlxsw_sp_trap *trap;
2490 	u64 max_policers;
2491 	int err;
2492 
2493 	if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_CPU_POLICERS))
2494 		return -EIO;
2495 	max_policers = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_CPU_POLICERS);
2496 	trap = kzalloc_flex(*trap, policers_usage, BITS_TO_LONGS(max_policers));
2497 	if (!trap)
2498 		return -ENOMEM;
2499 	trap->max_policers = max_policers;
2500 	mlxsw_sp->trap = trap;
2501 
2502 	err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
2503 	if (err)
2504 		goto err_cpu_policers_set;
2505 
2506 	err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
2507 	if (err)
2508 		goto err_trap_groups_set;
2509 
2510 	err = mlxsw_core_traps_register(mlxsw_sp->core, mlxsw_sp_listener,
2511 					ARRAY_SIZE(mlxsw_sp_listener),
2512 					mlxsw_sp);
2513 	if (err)
2514 		goto err_traps_register;
2515 
2516 	err = mlxsw_core_traps_register(mlxsw_sp->core, mlxsw_sp->listeners,
2517 					mlxsw_sp->listeners_count, mlxsw_sp);
2518 	if (err)
2519 		goto err_extra_traps_init;
2520 
2521 	return 0;
2522 
2523 err_extra_traps_init:
2524 	mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp_listener,
2525 				    ARRAY_SIZE(mlxsw_sp_listener),
2526 				    mlxsw_sp);
2527 err_traps_register:
2528 err_trap_groups_set:
2529 err_cpu_policers_set:
2530 	kfree(trap);
2531 	return err;
2532 }
2533 
mlxsw_sp_traps_fini(struct mlxsw_sp * mlxsw_sp)2534 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2535 {
2536 	mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp->listeners,
2537 				    mlxsw_sp->listeners_count,
2538 				    mlxsw_sp);
2539 	mlxsw_core_traps_unregister(mlxsw_sp->core, mlxsw_sp_listener,
2540 				    ARRAY_SIZE(mlxsw_sp_listener), mlxsw_sp);
2541 	kfree(mlxsw_sp->trap);
2542 }
2543 
mlxsw_sp_lag_pgt_init(struct mlxsw_sp * mlxsw_sp)2544 static int mlxsw_sp_lag_pgt_init(struct mlxsw_sp *mlxsw_sp)
2545 {
2546 	char sgcr_pl[MLXSW_REG_SGCR_LEN];
2547 	int err;
2548 
2549 	if (mlxsw_core_lag_mode(mlxsw_sp->core) !=
2550 	    MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW)
2551 		return 0;
2552 
2553 	/* In DDD mode, which we by default use, each LAG entry is 8 PGT
2554 	 * entries. The LAG table address needs to be 8-aligned, but that ought
2555 	 * to be the case, since the LAG table is allocated first.
2556 	 */
2557 	err = mlxsw_sp_pgt_mid_alloc_range(mlxsw_sp, &mlxsw_sp->lag_pgt_base,
2558 					   mlxsw_sp->max_lag * 8);
2559 	if (err)
2560 		return err;
2561 	if (WARN_ON_ONCE(mlxsw_sp->lag_pgt_base % 8)) {
2562 		err = -EINVAL;
2563 		goto err_mid_alloc_range;
2564 	}
2565 
2566 	mlxsw_reg_sgcr_pack(sgcr_pl, mlxsw_sp->lag_pgt_base);
2567 	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sgcr), sgcr_pl);
2568 	if (err)
2569 		goto err_mid_alloc_range;
2570 
2571 	return 0;
2572 
2573 err_mid_alloc_range:
2574 	mlxsw_sp_pgt_mid_free_range(mlxsw_sp, mlxsw_sp->lag_pgt_base,
2575 				    mlxsw_sp->max_lag * 8);
2576 	return err;
2577 }
2578 
mlxsw_sp_lag_pgt_fini(struct mlxsw_sp * mlxsw_sp)2579 static void mlxsw_sp_lag_pgt_fini(struct mlxsw_sp *mlxsw_sp)
2580 {
2581 	if (mlxsw_core_lag_mode(mlxsw_sp->core) !=
2582 	    MLXSW_CMD_MBOX_CONFIG_PROFILE_LAG_MODE_SW)
2583 		return;
2584 
2585 	mlxsw_sp_pgt_mid_free_range(mlxsw_sp, mlxsw_sp->lag_pgt_base,
2586 				    mlxsw_sp->max_lag * 8);
2587 }
2588 
2589 #define MLXSW_SP_LAG_SEED_INIT 0xcafecafe
2590 
2591 struct mlxsw_sp_lag {
2592 	struct net_device *dev;
2593 	refcount_t ref_count;
2594 	u16 lag_id;
2595 };
2596 
mlxsw_sp_lag_init(struct mlxsw_sp * mlxsw_sp)2597 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2598 {
2599 	char slcr_pl[MLXSW_REG_SLCR_LEN];
2600 	u32 seed;
2601 	int err;
2602 
2603 	seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac),
2604 		     MLXSW_SP_LAG_SEED_INIT);
2605 	mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2606 				     MLXSW_REG_SLCR_LAG_HASH_DMAC |
2607 				     MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2608 				     MLXSW_REG_SLCR_LAG_HASH_VLANID |
2609 				     MLXSW_REG_SLCR_LAG_HASH_SIP |
2610 				     MLXSW_REG_SLCR_LAG_HASH_DIP |
2611 				     MLXSW_REG_SLCR_LAG_HASH_SPORT |
2612 				     MLXSW_REG_SLCR_LAG_HASH_DPORT |
2613 				     MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed);
2614 	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2615 	if (err)
2616 		return err;
2617 
2618 	err = mlxsw_core_max_lag(mlxsw_sp->core, &mlxsw_sp->max_lag);
2619 	if (err)
2620 		return err;
2621 
2622 	if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
2623 		return -EIO;
2624 
2625 	err = mlxsw_sp_lag_pgt_init(mlxsw_sp);
2626 	if (err)
2627 		return err;
2628 
2629 	mlxsw_sp->lags = kzalloc_objs(struct mlxsw_sp_lag, mlxsw_sp->max_lag);
2630 	if (!mlxsw_sp->lags) {
2631 		err = -ENOMEM;
2632 		goto err_kcalloc;
2633 	}
2634 
2635 	return 0;
2636 
2637 err_kcalloc:
2638 	mlxsw_sp_lag_pgt_fini(mlxsw_sp);
2639 	return err;
2640 }
2641 
mlxsw_sp_lag_fini(struct mlxsw_sp * mlxsw_sp)2642 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
2643 {
2644 	mlxsw_sp_lag_pgt_fini(mlxsw_sp);
2645 	kfree(mlxsw_sp->lags);
2646 }
2647 
2648 static const struct mlxsw_sp_ptp_ops mlxsw_sp1_ptp_ops = {
2649 	.clock_init	= mlxsw_sp1_ptp_clock_init,
2650 	.clock_fini	= mlxsw_sp1_ptp_clock_fini,
2651 	.init		= mlxsw_sp1_ptp_init,
2652 	.fini		= mlxsw_sp1_ptp_fini,
2653 	.receive	= mlxsw_sp1_ptp_receive,
2654 	.transmitted	= mlxsw_sp1_ptp_transmitted,
2655 	.hwtstamp_get	= mlxsw_sp1_ptp_hwtstamp_get,
2656 	.hwtstamp_set	= mlxsw_sp1_ptp_hwtstamp_set,
2657 	.shaper_work	= mlxsw_sp1_ptp_shaper_work,
2658 #if IS_REACHABLE(CONFIG_PTP_1588_CLOCK)
2659 	.get_ts_info	= mlxsw_sp1_ptp_get_ts_info,
2660 #endif
2661 	.get_stats_count = mlxsw_sp1_get_stats_count,
2662 	.get_stats_strings = mlxsw_sp1_get_stats_strings,
2663 	.get_stats	= mlxsw_sp1_get_stats,
2664 };
2665 
2666 static const struct mlxsw_sp_ptp_ops mlxsw_sp2_ptp_ops = {
2667 	.clock_init	= mlxsw_sp2_ptp_clock_init,
2668 	.clock_fini	= mlxsw_sp2_ptp_clock_fini,
2669 	.init		= mlxsw_sp2_ptp_init,
2670 	.fini		= mlxsw_sp2_ptp_fini,
2671 	.receive	= mlxsw_sp2_ptp_receive,
2672 	.transmitted	= mlxsw_sp2_ptp_transmitted,
2673 	.hwtstamp_get	= mlxsw_sp2_ptp_hwtstamp_get,
2674 	.hwtstamp_set	= mlxsw_sp2_ptp_hwtstamp_set,
2675 	.shaper_work	= mlxsw_sp2_ptp_shaper_work,
2676 #if IS_REACHABLE(CONFIG_PTP_1588_CLOCK)
2677 	.get_ts_info	= mlxsw_sp2_ptp_get_ts_info,
2678 #endif
2679 	.get_stats_count = mlxsw_sp2_get_stats_count,
2680 	.get_stats_strings = mlxsw_sp2_get_stats_strings,
2681 	.get_stats	= mlxsw_sp2_get_stats,
2682 	.tx_as_data     = true,
2683 };
2684 
2685 static const struct mlxsw_sp_ptp_ops mlxsw_sp4_ptp_ops = {
2686 	.clock_init	= mlxsw_sp2_ptp_clock_init,
2687 	.clock_fini	= mlxsw_sp2_ptp_clock_fini,
2688 	.init		= mlxsw_sp2_ptp_init,
2689 	.fini		= mlxsw_sp2_ptp_fini,
2690 	.receive	= mlxsw_sp2_ptp_receive,
2691 	.transmitted	= mlxsw_sp2_ptp_transmitted,
2692 	.hwtstamp_get	= mlxsw_sp2_ptp_hwtstamp_get,
2693 	.hwtstamp_set	= mlxsw_sp2_ptp_hwtstamp_set,
2694 	.shaper_work	= mlxsw_sp2_ptp_shaper_work,
2695 #if IS_REACHABLE(CONFIG_PTP_1588_CLOCK)
2696 	.get_ts_info	= mlxsw_sp2_ptp_get_ts_info,
2697 #endif
2698 	.get_stats_count = mlxsw_sp2_get_stats_count,
2699 	.get_stats_strings = mlxsw_sp2_get_stats_strings,
2700 	.get_stats	= mlxsw_sp2_get_stats,
2701 };
2702 
2703 struct mlxsw_sp_sample_trigger_node {
2704 	struct mlxsw_sp_sample_trigger trigger;
2705 	struct mlxsw_sp_sample_params params;
2706 	struct rhash_head ht_node;
2707 	struct rcu_head rcu;
2708 	refcount_t refcount;
2709 };
2710 
2711 static const struct rhashtable_params mlxsw_sp_sample_trigger_ht_params = {
2712 	.key_offset = offsetof(struct mlxsw_sp_sample_trigger_node, trigger),
2713 	.head_offset = offsetof(struct mlxsw_sp_sample_trigger_node, ht_node),
2714 	.key_len = sizeof(struct mlxsw_sp_sample_trigger),
2715 	.automatic_shrinking = true,
2716 };
2717 
2718 static void
mlxsw_sp_sample_trigger_key_init(struct mlxsw_sp_sample_trigger * key,const struct mlxsw_sp_sample_trigger * trigger)2719 mlxsw_sp_sample_trigger_key_init(struct mlxsw_sp_sample_trigger *key,
2720 				 const struct mlxsw_sp_sample_trigger *trigger)
2721 {
2722 	memset(key, 0, sizeof(*key));
2723 	key->type = trigger->type;
2724 	key->local_port = trigger->local_port;
2725 }
2726 
2727 /* RCU read lock must be held */
2728 struct mlxsw_sp_sample_params *
mlxsw_sp_sample_trigger_params_lookup(struct mlxsw_sp * mlxsw_sp,const struct mlxsw_sp_sample_trigger * trigger)2729 mlxsw_sp_sample_trigger_params_lookup(struct mlxsw_sp *mlxsw_sp,
2730 				      const struct mlxsw_sp_sample_trigger *trigger)
2731 {
2732 	struct mlxsw_sp_sample_trigger_node *trigger_node;
2733 	struct mlxsw_sp_sample_trigger key;
2734 
2735 	mlxsw_sp_sample_trigger_key_init(&key, trigger);
2736 	trigger_node = rhashtable_lookup(&mlxsw_sp->sample_trigger_ht, &key,
2737 					 mlxsw_sp_sample_trigger_ht_params);
2738 	if (!trigger_node)
2739 		return NULL;
2740 
2741 	return &trigger_node->params;
2742 }
2743 
2744 static int
mlxsw_sp_sample_trigger_node_init(struct mlxsw_sp * mlxsw_sp,const struct mlxsw_sp_sample_trigger * trigger,const struct mlxsw_sp_sample_params * params)2745 mlxsw_sp_sample_trigger_node_init(struct mlxsw_sp *mlxsw_sp,
2746 				  const struct mlxsw_sp_sample_trigger *trigger,
2747 				  const struct mlxsw_sp_sample_params *params)
2748 {
2749 	struct mlxsw_sp_sample_trigger_node *trigger_node;
2750 	int err;
2751 
2752 	trigger_node = kzalloc_obj(*trigger_node);
2753 	if (!trigger_node)
2754 		return -ENOMEM;
2755 
2756 	trigger_node->trigger = *trigger;
2757 	trigger_node->params = *params;
2758 	refcount_set(&trigger_node->refcount, 1);
2759 
2760 	err = rhashtable_insert_fast(&mlxsw_sp->sample_trigger_ht,
2761 				     &trigger_node->ht_node,
2762 				     mlxsw_sp_sample_trigger_ht_params);
2763 	if (err)
2764 		goto err_rhashtable_insert;
2765 
2766 	return 0;
2767 
2768 err_rhashtable_insert:
2769 	kfree(trigger_node);
2770 	return err;
2771 }
2772 
2773 static void
mlxsw_sp_sample_trigger_node_fini(struct mlxsw_sp * mlxsw_sp,struct mlxsw_sp_sample_trigger_node * trigger_node)2774 mlxsw_sp_sample_trigger_node_fini(struct mlxsw_sp *mlxsw_sp,
2775 				  struct mlxsw_sp_sample_trigger_node *trigger_node)
2776 {
2777 	rhashtable_remove_fast(&mlxsw_sp->sample_trigger_ht,
2778 			       &trigger_node->ht_node,
2779 			       mlxsw_sp_sample_trigger_ht_params);
2780 	kfree_rcu(trigger_node, rcu);
2781 }
2782 
2783 int
mlxsw_sp_sample_trigger_params_set(struct mlxsw_sp * mlxsw_sp,const struct mlxsw_sp_sample_trigger * trigger,const struct mlxsw_sp_sample_params * params,struct netlink_ext_ack * extack)2784 mlxsw_sp_sample_trigger_params_set(struct mlxsw_sp *mlxsw_sp,
2785 				   const struct mlxsw_sp_sample_trigger *trigger,
2786 				   const struct mlxsw_sp_sample_params *params,
2787 				   struct netlink_ext_ack *extack)
2788 {
2789 	struct mlxsw_sp_sample_trigger_node *trigger_node;
2790 	struct mlxsw_sp_sample_trigger key;
2791 
2792 	ASSERT_RTNL();
2793 
2794 	mlxsw_sp_sample_trigger_key_init(&key, trigger);
2795 
2796 	trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht,
2797 					      &key,
2798 					      mlxsw_sp_sample_trigger_ht_params);
2799 	if (!trigger_node)
2800 		return mlxsw_sp_sample_trigger_node_init(mlxsw_sp, &key,
2801 							 params);
2802 
2803 	if (trigger_node->trigger.local_port) {
2804 		NL_SET_ERR_MSG_MOD(extack, "Sampling already enabled on port");
2805 		return -EINVAL;
2806 	}
2807 
2808 	if (trigger_node->params.psample_group != params->psample_group ||
2809 	    trigger_node->params.truncate != params->truncate ||
2810 	    trigger_node->params.rate != params->rate ||
2811 	    trigger_node->params.trunc_size != params->trunc_size) {
2812 		NL_SET_ERR_MSG_MOD(extack, "Sampling parameters do not match for an existing sampling trigger");
2813 		return -EINVAL;
2814 	}
2815 
2816 	refcount_inc(&trigger_node->refcount);
2817 
2818 	return 0;
2819 }
2820 
2821 void
mlxsw_sp_sample_trigger_params_unset(struct mlxsw_sp * mlxsw_sp,const struct mlxsw_sp_sample_trigger * trigger)2822 mlxsw_sp_sample_trigger_params_unset(struct mlxsw_sp *mlxsw_sp,
2823 				     const struct mlxsw_sp_sample_trigger *trigger)
2824 {
2825 	struct mlxsw_sp_sample_trigger_node *trigger_node;
2826 	struct mlxsw_sp_sample_trigger key;
2827 
2828 	ASSERT_RTNL();
2829 
2830 	mlxsw_sp_sample_trigger_key_init(&key, trigger);
2831 
2832 	trigger_node = rhashtable_lookup_fast(&mlxsw_sp->sample_trigger_ht,
2833 					      &key,
2834 					      mlxsw_sp_sample_trigger_ht_params);
2835 	if (!trigger_node)
2836 		return;
2837 
2838 	if (!refcount_dec_and_test(&trigger_node->refcount))
2839 		return;
2840 
2841 	mlxsw_sp_sample_trigger_node_fini(mlxsw_sp, trigger_node);
2842 }
2843 
2844 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
2845 				    unsigned long event, void *ptr);
2846 
2847 #define MLXSW_SP_DEFAULT_PARSING_DEPTH 96
2848 #define MLXSW_SP_INCREASED_PARSING_DEPTH 128
2849 #define MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT 4789
2850 
mlxsw_sp_parsing_init(struct mlxsw_sp * mlxsw_sp)2851 static void mlxsw_sp_parsing_init(struct mlxsw_sp *mlxsw_sp)
2852 {
2853 	refcount_set(&mlxsw_sp->parsing.parsing_depth_ref, 0);
2854 	mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH;
2855 	mlxsw_sp->parsing.vxlan_udp_dport = MLXSW_SP_DEFAULT_VXLAN_UDP_DPORT;
2856 	mutex_init(&mlxsw_sp->parsing.lock);
2857 }
2858 
mlxsw_sp_parsing_fini(struct mlxsw_sp * mlxsw_sp)2859 static void mlxsw_sp_parsing_fini(struct mlxsw_sp *mlxsw_sp)
2860 {
2861 	mutex_destroy(&mlxsw_sp->parsing.lock);
2862 	WARN_ON_ONCE(refcount_read(&mlxsw_sp->parsing.parsing_depth_ref));
2863 }
2864 
2865 struct mlxsw_sp_ipv6_addr_node {
2866 	struct in6_addr key;
2867 	struct rhash_head ht_node;
2868 	u32 kvdl_index;
2869 	refcount_t refcount;
2870 };
2871 
2872 static const struct rhashtable_params mlxsw_sp_ipv6_addr_ht_params = {
2873 	.key_offset = offsetof(struct mlxsw_sp_ipv6_addr_node, key),
2874 	.head_offset = offsetof(struct mlxsw_sp_ipv6_addr_node, ht_node),
2875 	.key_len = sizeof(struct in6_addr),
2876 	.automatic_shrinking = true,
2877 };
2878 
2879 static int
mlxsw_sp_ipv6_addr_init(struct mlxsw_sp * mlxsw_sp,const struct in6_addr * addr6,u32 * p_kvdl_index)2880 mlxsw_sp_ipv6_addr_init(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6,
2881 			u32 *p_kvdl_index)
2882 {
2883 	struct mlxsw_sp_ipv6_addr_node *node;
2884 	char rips_pl[MLXSW_REG_RIPS_LEN];
2885 	int err;
2886 
2887 	err = mlxsw_sp_kvdl_alloc(mlxsw_sp,
2888 				  MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1,
2889 				  p_kvdl_index);
2890 	if (err)
2891 		return err;
2892 
2893 	mlxsw_reg_rips_pack(rips_pl, *p_kvdl_index, addr6);
2894 	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(rips), rips_pl);
2895 	if (err)
2896 		goto err_rips_write;
2897 
2898 	node = kzalloc_obj(*node);
2899 	if (!node) {
2900 		err = -ENOMEM;
2901 		goto err_node_alloc;
2902 	}
2903 
2904 	node->key = *addr6;
2905 	node->kvdl_index = *p_kvdl_index;
2906 	refcount_set(&node->refcount, 1);
2907 
2908 	err = rhashtable_insert_fast(&mlxsw_sp->ipv6_addr_ht,
2909 				     &node->ht_node,
2910 				     mlxsw_sp_ipv6_addr_ht_params);
2911 	if (err)
2912 		goto err_rhashtable_insert;
2913 
2914 	return 0;
2915 
2916 err_rhashtable_insert:
2917 	kfree(node);
2918 err_node_alloc:
2919 err_rips_write:
2920 	mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1,
2921 			   *p_kvdl_index);
2922 	return err;
2923 }
2924 
mlxsw_sp_ipv6_addr_fini(struct mlxsw_sp * mlxsw_sp,struct mlxsw_sp_ipv6_addr_node * node)2925 static void mlxsw_sp_ipv6_addr_fini(struct mlxsw_sp *mlxsw_sp,
2926 				    struct mlxsw_sp_ipv6_addr_node *node)
2927 {
2928 	u32 kvdl_index = node->kvdl_index;
2929 
2930 	rhashtable_remove_fast(&mlxsw_sp->ipv6_addr_ht, &node->ht_node,
2931 			       mlxsw_sp_ipv6_addr_ht_params);
2932 	kfree(node);
2933 	mlxsw_sp_kvdl_free(mlxsw_sp, MLXSW_SP_KVDL_ENTRY_TYPE_IPV6_ADDRESS, 1,
2934 			   kvdl_index);
2935 }
2936 
mlxsw_sp_ipv6_addr_kvdl_index_get(struct mlxsw_sp * mlxsw_sp,const struct in6_addr * addr6,u32 * p_kvdl_index)2937 int mlxsw_sp_ipv6_addr_kvdl_index_get(struct mlxsw_sp *mlxsw_sp,
2938 				      const struct in6_addr *addr6,
2939 				      u32 *p_kvdl_index)
2940 {
2941 	struct mlxsw_sp_ipv6_addr_node *node;
2942 	int err = 0;
2943 
2944 	mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock);
2945 	node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6,
2946 				      mlxsw_sp_ipv6_addr_ht_params);
2947 	if (node) {
2948 		refcount_inc(&node->refcount);
2949 		*p_kvdl_index = node->kvdl_index;
2950 		goto out_unlock;
2951 	}
2952 
2953 	err = mlxsw_sp_ipv6_addr_init(mlxsw_sp, addr6, p_kvdl_index);
2954 
2955 out_unlock:
2956 	mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock);
2957 	return err;
2958 }
2959 
2960 void
mlxsw_sp_ipv6_addr_put(struct mlxsw_sp * mlxsw_sp,const struct in6_addr * addr6)2961 mlxsw_sp_ipv6_addr_put(struct mlxsw_sp *mlxsw_sp, const struct in6_addr *addr6)
2962 {
2963 	struct mlxsw_sp_ipv6_addr_node *node;
2964 
2965 	mutex_lock(&mlxsw_sp->ipv6_addr_ht_lock);
2966 	node = rhashtable_lookup_fast(&mlxsw_sp->ipv6_addr_ht, addr6,
2967 				      mlxsw_sp_ipv6_addr_ht_params);
2968 	if (WARN_ON(!node))
2969 		goto out_unlock;
2970 
2971 	if (!refcount_dec_and_test(&node->refcount))
2972 		goto out_unlock;
2973 
2974 	mlxsw_sp_ipv6_addr_fini(mlxsw_sp, node);
2975 
2976 out_unlock:
2977 	mutex_unlock(&mlxsw_sp->ipv6_addr_ht_lock);
2978 }
2979 
mlxsw_sp_ipv6_addr_ht_init(struct mlxsw_sp * mlxsw_sp)2980 static int mlxsw_sp_ipv6_addr_ht_init(struct mlxsw_sp *mlxsw_sp)
2981 {
2982 	int err;
2983 
2984 	err = rhashtable_init(&mlxsw_sp->ipv6_addr_ht,
2985 			      &mlxsw_sp_ipv6_addr_ht_params);
2986 	if (err)
2987 		return err;
2988 
2989 	mutex_init(&mlxsw_sp->ipv6_addr_ht_lock);
2990 	return 0;
2991 }
2992 
mlxsw_sp_ipv6_addr_ht_fini(struct mlxsw_sp * mlxsw_sp)2993 static void mlxsw_sp_ipv6_addr_ht_fini(struct mlxsw_sp *mlxsw_sp)
2994 {
2995 	mutex_destroy(&mlxsw_sp->ipv6_addr_ht_lock);
2996 	rhashtable_destroy(&mlxsw_sp->ipv6_addr_ht);
2997 }
2998 
mlxsw_sp_init(struct mlxsw_core * mlxsw_core,const struct mlxsw_bus_info * mlxsw_bus_info,struct netlink_ext_ack * extack)2999 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
3000 			 const struct mlxsw_bus_info *mlxsw_bus_info,
3001 			 struct netlink_ext_ack *extack)
3002 {
3003 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3004 	int err;
3005 
3006 	mlxsw_sp->core = mlxsw_core;
3007 	mlxsw_sp->bus_info = mlxsw_bus_info;
3008 
3009 	mlxsw_sp_parsing_init(mlxsw_sp);
3010 
3011 	err = mlxsw_sp_base_mac_get(mlxsw_sp);
3012 	if (err) {
3013 		dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3014 		return err;
3015 	}
3016 
3017 	err = mlxsw_sp_kvdl_init(mlxsw_sp);
3018 	if (err) {
3019 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3020 		return err;
3021 	}
3022 
3023 	err = mlxsw_sp_pgt_init(mlxsw_sp);
3024 	if (err) {
3025 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PGT\n");
3026 		goto err_pgt_init;
3027 	}
3028 
3029 	/* Initialize before FIDs so that the LAG table is at the start of PGT
3030 	 * and 8-aligned without overallocation.
3031 	 */
3032 	err = mlxsw_sp_lag_init(mlxsw_sp);
3033 	if (err) {
3034 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3035 		goto err_lag_init;
3036 	}
3037 
3038 	err = mlxsw_sp->fid_core_ops->init(mlxsw_sp);
3039 	if (err) {
3040 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
3041 		goto err_fid_core_init;
3042 	}
3043 
3044 	err = mlxsw_sp_policers_init(mlxsw_sp);
3045 	if (err) {
3046 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize policers\n");
3047 		goto err_policers_init;
3048 	}
3049 
3050 	err = mlxsw_sp_traps_init(mlxsw_sp);
3051 	if (err) {
3052 		dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3053 		goto err_traps_init;
3054 	}
3055 
3056 	err = mlxsw_sp_devlink_traps_init(mlxsw_sp);
3057 	if (err) {
3058 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n");
3059 		goto err_devlink_traps_init;
3060 	}
3061 
3062 	err = mlxsw_sp_buffers_init(mlxsw_sp);
3063 	if (err) {
3064 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3065 		goto err_buffers_init;
3066 	}
3067 
3068 	/* Initialize SPAN before router and switchdev, so that those components
3069 	 * can call mlxsw_sp_span_respin().
3070 	 */
3071 	err = mlxsw_sp_span_init(mlxsw_sp);
3072 	if (err) {
3073 		dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3074 		goto err_span_init;
3075 	}
3076 
3077 	err = mlxsw_sp_switchdev_init(mlxsw_sp);
3078 	if (err) {
3079 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3080 		goto err_switchdev_init;
3081 	}
3082 
3083 	err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3084 	if (err) {
3085 		dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3086 		goto err_counter_pool_init;
3087 	}
3088 
3089 	err = mlxsw_sp_afa_init(mlxsw_sp);
3090 	if (err) {
3091 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3092 		goto err_afa_init;
3093 	}
3094 
3095 	err = mlxsw_sp_ipv6_addr_ht_init(mlxsw_sp);
3096 	if (err) {
3097 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize hash table for IPv6 addresses\n");
3098 		goto err_ipv6_addr_ht_init;
3099 	}
3100 
3101 	err = mlxsw_sp_nve_init(mlxsw_sp);
3102 	if (err) {
3103 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n");
3104 		goto err_nve_init;
3105 	}
3106 
3107 	err = mlxsw_sp_port_range_init(mlxsw_sp);
3108 	if (err) {
3109 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize port ranges\n");
3110 		goto err_port_range_init;
3111 	}
3112 
3113 	err = mlxsw_sp_acl_init(mlxsw_sp);
3114 	if (err) {
3115 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3116 		goto err_acl_init;
3117 	}
3118 
3119 	err = mlxsw_sp_router_init(mlxsw_sp, extack);
3120 	if (err) {
3121 		dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3122 		goto err_router_init;
3123 	}
3124 
3125 	if (mlxsw_sp->bus_info->read_clock_capable) {
3126 		/* NULL is a valid return value from clock_init */
3127 		mlxsw_sp->clock =
3128 			mlxsw_sp->ptp_ops->clock_init(mlxsw_sp,
3129 						      mlxsw_sp->bus_info->dev);
3130 		if (IS_ERR(mlxsw_sp->clock)) {
3131 			err = PTR_ERR(mlxsw_sp->clock);
3132 			dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n");
3133 			goto err_ptp_clock_init;
3134 		}
3135 	}
3136 
3137 	if (mlxsw_sp->clock) {
3138 		/* NULL is a valid return value from ptp_ops->init */
3139 		mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp);
3140 		if (IS_ERR(mlxsw_sp->ptp_state)) {
3141 			err = PTR_ERR(mlxsw_sp->ptp_state);
3142 			dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n");
3143 			goto err_ptp_init;
3144 		}
3145 	}
3146 
3147 	/* Initialize netdevice notifier after SPAN is initialized, so that the
3148 	 * event handler can call SPAN respin.
3149 	 */
3150 	mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3151 	err = register_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
3152 					      &mlxsw_sp->netdevice_nb);
3153 	if (err) {
3154 		dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3155 		goto err_netdev_notifier;
3156 	}
3157 
3158 	err = mlxsw_sp_dpipe_init(mlxsw_sp);
3159 	if (err) {
3160 		dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3161 		goto err_dpipe_init;
3162 	}
3163 
3164 	err = mlxsw_sp_port_module_info_init(mlxsw_sp);
3165 	if (err) {
3166 		dev_err(mlxsw_sp->bus_info->dev, "Failed to init port module info\n");
3167 		goto err_port_module_info_init;
3168 	}
3169 
3170 	err = rhashtable_init(&mlxsw_sp->sample_trigger_ht,
3171 			      &mlxsw_sp_sample_trigger_ht_params);
3172 	if (err) {
3173 		dev_err(mlxsw_sp->bus_info->dev, "Failed to init sampling trigger hashtable\n");
3174 		goto err_sample_trigger_init;
3175 	}
3176 
3177 	err = mlxsw_sp_ports_create(mlxsw_sp);
3178 	if (err) {
3179 		dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3180 		goto err_ports_create;
3181 	}
3182 
3183 	return 0;
3184 
3185 err_ports_create:
3186 	rhashtable_destroy(&mlxsw_sp->sample_trigger_ht);
3187 err_sample_trigger_init:
3188 	mlxsw_sp_port_module_info_fini(mlxsw_sp);
3189 err_port_module_info_init:
3190 	mlxsw_sp_dpipe_fini(mlxsw_sp);
3191 err_dpipe_init:
3192 	unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
3193 					  &mlxsw_sp->netdevice_nb);
3194 err_netdev_notifier:
3195 	if (mlxsw_sp->clock)
3196 		mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
3197 err_ptp_init:
3198 	if (mlxsw_sp->clock)
3199 		mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
3200 err_ptp_clock_init:
3201 	mlxsw_sp_router_fini(mlxsw_sp);
3202 err_router_init:
3203 	mlxsw_sp_acl_fini(mlxsw_sp);
3204 err_acl_init:
3205 	mlxsw_sp_port_range_fini(mlxsw_sp);
3206 err_port_range_init:
3207 	mlxsw_sp_nve_fini(mlxsw_sp);
3208 err_nve_init:
3209 	mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp);
3210 err_ipv6_addr_ht_init:
3211 	mlxsw_sp_afa_fini(mlxsw_sp);
3212 err_afa_init:
3213 	mlxsw_sp_counter_pool_fini(mlxsw_sp);
3214 err_counter_pool_init:
3215 	mlxsw_sp_switchdev_fini(mlxsw_sp);
3216 err_switchdev_init:
3217 	mlxsw_sp_span_fini(mlxsw_sp);
3218 err_span_init:
3219 	mlxsw_sp_buffers_fini(mlxsw_sp);
3220 err_buffers_init:
3221 	mlxsw_sp_devlink_traps_fini(mlxsw_sp);
3222 err_devlink_traps_init:
3223 	mlxsw_sp_traps_fini(mlxsw_sp);
3224 err_traps_init:
3225 	mlxsw_sp_policers_fini(mlxsw_sp);
3226 err_policers_init:
3227 	mlxsw_sp->fid_core_ops->fini(mlxsw_sp);
3228 err_fid_core_init:
3229 	mlxsw_sp_lag_fini(mlxsw_sp);
3230 err_lag_init:
3231 	mlxsw_sp_pgt_fini(mlxsw_sp);
3232 err_pgt_init:
3233 	mlxsw_sp_kvdl_fini(mlxsw_sp);
3234 	mlxsw_sp_parsing_fini(mlxsw_sp);
3235 	return err;
3236 }
3237 
mlxsw_sp1_init(struct mlxsw_core * mlxsw_core,const struct mlxsw_bus_info * mlxsw_bus_info,struct netlink_ext_ack * extack)3238 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
3239 			  const struct mlxsw_bus_info *mlxsw_bus_info,
3240 			  struct netlink_ext_ack *extack)
3241 {
3242 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3243 
3244 	mlxsw_sp->switchdev_ops = &mlxsw_sp1_switchdev_ops;
3245 	mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
3246 	mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
3247 	mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
3248 	mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
3249 	mlxsw_sp->acl_rulei_ops = &mlxsw_sp1_acl_rulei_ops;
3250 	mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
3251 	mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr;
3252 	mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask;
3253 	mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals;
3254 	mlxsw_sp->sb_ops = &mlxsw_sp1_sb_ops;
3255 	mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops;
3256 	mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops;
3257 	mlxsw_sp->span_ops = &mlxsw_sp1_span_ops;
3258 	mlxsw_sp->policer_core_ops = &mlxsw_sp1_policer_core_ops;
3259 	mlxsw_sp->trap_ops = &mlxsw_sp1_trap_ops;
3260 	mlxsw_sp->mall_ops = &mlxsw_sp1_mall_ops;
3261 	mlxsw_sp->router_ops = &mlxsw_sp1_router_ops;
3262 	mlxsw_sp->listeners = mlxsw_sp1_listener;
3263 	mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener);
3264 	mlxsw_sp->fid_core_ops = &mlxsw_sp1_fid_core_ops;
3265 	mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1;
3266 	mlxsw_sp->pgt_smpe_index_valid = true;
3267 
3268 	return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
3269 }
3270 
mlxsw_sp2_init(struct mlxsw_core * mlxsw_core,const struct mlxsw_bus_info * mlxsw_bus_info,struct netlink_ext_ack * extack)3271 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
3272 			  const struct mlxsw_bus_info *mlxsw_bus_info,
3273 			  struct netlink_ext_ack *extack)
3274 {
3275 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3276 
3277 	mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops;
3278 	mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
3279 	mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
3280 	mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
3281 	mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
3282 	mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
3283 	mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
3284 	mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops;
3285 	mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
3286 	mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
3287 	mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
3288 	mlxsw_sp->sb_ops = &mlxsw_sp2_sb_ops;
3289 	mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
3290 	mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
3291 	mlxsw_sp->span_ops = &mlxsw_sp2_span_ops;
3292 	mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
3293 	mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
3294 	mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops;
3295 	mlxsw_sp->router_ops = &mlxsw_sp2_router_ops;
3296 	mlxsw_sp->listeners = mlxsw_sp2_listener;
3297 	mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener);
3298 	mlxsw_sp->fid_core_ops = &mlxsw_sp2_fid_core_ops;
3299 	mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2;
3300 	mlxsw_sp->pgt_smpe_index_valid = false;
3301 
3302 	return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
3303 }
3304 
mlxsw_sp3_init(struct mlxsw_core * mlxsw_core,const struct mlxsw_bus_info * mlxsw_bus_info,struct netlink_ext_ack * extack)3305 static int mlxsw_sp3_init(struct mlxsw_core *mlxsw_core,
3306 			  const struct mlxsw_bus_info *mlxsw_bus_info,
3307 			  struct netlink_ext_ack *extack)
3308 {
3309 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3310 
3311 	mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops;
3312 	mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
3313 	mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
3314 	mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
3315 	mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
3316 	mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
3317 	mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
3318 	mlxsw_sp->acl_bf_ops = &mlxsw_sp2_acl_bf_ops;
3319 	mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
3320 	mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
3321 	mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
3322 	mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops;
3323 	mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
3324 	mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
3325 	mlxsw_sp->span_ops = &mlxsw_sp3_span_ops;
3326 	mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
3327 	mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
3328 	mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops;
3329 	mlxsw_sp->router_ops = &mlxsw_sp2_router_ops;
3330 	mlxsw_sp->listeners = mlxsw_sp2_listener;
3331 	mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener);
3332 	mlxsw_sp->fid_core_ops = &mlxsw_sp2_fid_core_ops;
3333 	mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3;
3334 	mlxsw_sp->pgt_smpe_index_valid = false;
3335 
3336 	return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
3337 }
3338 
mlxsw_sp4_init(struct mlxsw_core * mlxsw_core,const struct mlxsw_bus_info * mlxsw_bus_info,struct netlink_ext_ack * extack)3339 static int mlxsw_sp4_init(struct mlxsw_core *mlxsw_core,
3340 			  const struct mlxsw_bus_info *mlxsw_bus_info,
3341 			  struct netlink_ext_ack *extack)
3342 {
3343 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3344 
3345 	mlxsw_sp->switchdev_ops = &mlxsw_sp2_switchdev_ops;
3346 	mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
3347 	mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
3348 	mlxsw_sp->afk_ops = &mlxsw_sp4_afk_ops;
3349 	mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
3350 	mlxsw_sp->acl_rulei_ops = &mlxsw_sp2_acl_rulei_ops;
3351 	mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
3352 	mlxsw_sp->acl_bf_ops = &mlxsw_sp4_acl_bf_ops;
3353 	mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
3354 	mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
3355 	mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
3356 	mlxsw_sp->sb_ops = &mlxsw_sp3_sb_ops;
3357 	mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
3358 	mlxsw_sp->ptp_ops = &mlxsw_sp4_ptp_ops;
3359 	mlxsw_sp->span_ops = &mlxsw_sp3_span_ops;
3360 	mlxsw_sp->policer_core_ops = &mlxsw_sp2_policer_core_ops;
3361 	mlxsw_sp->trap_ops = &mlxsw_sp2_trap_ops;
3362 	mlxsw_sp->mall_ops = &mlxsw_sp2_mall_ops;
3363 	mlxsw_sp->router_ops = &mlxsw_sp2_router_ops;
3364 	mlxsw_sp->listeners = mlxsw_sp2_listener;
3365 	mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp2_listener);
3366 	mlxsw_sp->fid_core_ops = &mlxsw_sp2_fid_core_ops;
3367 	mlxsw_sp->lowest_shaper_bs = MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4;
3368 	mlxsw_sp->pgt_smpe_index_valid = false;
3369 
3370 	return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info, extack);
3371 }
3372 
mlxsw_sp_fini(struct mlxsw_core * mlxsw_core)3373 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
3374 {
3375 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3376 
3377 	mlxsw_sp_ports_remove(mlxsw_sp);
3378 	rhashtable_destroy(&mlxsw_sp->sample_trigger_ht);
3379 	mlxsw_sp_port_module_info_fini(mlxsw_sp);
3380 	mlxsw_sp_dpipe_fini(mlxsw_sp);
3381 	unregister_netdevice_notifier_net(mlxsw_sp_net(mlxsw_sp),
3382 					  &mlxsw_sp->netdevice_nb);
3383 	if (mlxsw_sp->clock) {
3384 		mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
3385 		mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
3386 	}
3387 	mlxsw_sp_router_fini(mlxsw_sp);
3388 	mlxsw_sp_acl_fini(mlxsw_sp);
3389 	mlxsw_sp_port_range_fini(mlxsw_sp);
3390 	mlxsw_sp_nve_fini(mlxsw_sp);
3391 	mlxsw_sp_ipv6_addr_ht_fini(mlxsw_sp);
3392 	mlxsw_sp_afa_fini(mlxsw_sp);
3393 	mlxsw_sp_counter_pool_fini(mlxsw_sp);
3394 	mlxsw_sp_switchdev_fini(mlxsw_sp);
3395 	mlxsw_sp_span_fini(mlxsw_sp);
3396 	mlxsw_sp_buffers_fini(mlxsw_sp);
3397 	mlxsw_sp_devlink_traps_fini(mlxsw_sp);
3398 	mlxsw_sp_traps_fini(mlxsw_sp);
3399 	mlxsw_sp_policers_fini(mlxsw_sp);
3400 	mlxsw_sp->fid_core_ops->fini(mlxsw_sp);
3401 	mlxsw_sp_lag_fini(mlxsw_sp);
3402 	mlxsw_sp_pgt_fini(mlxsw_sp);
3403 	mlxsw_sp_kvdl_fini(mlxsw_sp);
3404 	mlxsw_sp_parsing_fini(mlxsw_sp);
3405 }
3406 
3407 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
3408 	.used_flood_mode                = 1,
3409 	.flood_mode                     = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED,
3410 	.used_max_ib_mc			= 1,
3411 	.max_ib_mc			= 0,
3412 	.used_max_pkey			= 1,
3413 	.max_pkey			= 0,
3414 	.used_ubridge			= 1,
3415 	.ubridge			= 1,
3416 	.used_kvd_sizes			= 1,
3417 	.kvd_hash_single_parts		= 59,
3418 	.kvd_hash_double_parts		= 41,
3419 	.kvd_linear_size		= MLXSW_SP_KVD_LINEAR_SIZE,
3420 	.swid_config			= {
3421 		{
3422 			.used_type	= 1,
3423 			.type		= MLXSW_PORT_SWID_TYPE_ETH,
3424 		}
3425 	},
3426 };
3427 
3428 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
3429 	.used_flood_mode                = 1,
3430 	.flood_mode                     = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED,
3431 	.used_max_ib_mc			= 1,
3432 	.max_ib_mc			= 0,
3433 	.used_max_pkey			= 1,
3434 	.max_pkey			= 0,
3435 	.used_ubridge			= 1,
3436 	.ubridge			= 1,
3437 	.swid_config			= {
3438 		{
3439 			.used_type	= 1,
3440 			.type		= MLXSW_PORT_SWID_TYPE_ETH,
3441 		}
3442 	},
3443 	.used_cqe_time_stamp_type	= 1,
3444 	.cqe_time_stamp_type		= MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC,
3445 	.lag_mode_prefer_sw		= true,
3446 	.flood_mode_prefer_cff		= true,
3447 };
3448 
3449 /* Reduce number of LAGs from full capacity (256) to the maximum supported LAGs
3450  * in Spectrum-2/3, to avoid regression in number of free entries in the PGT
3451  * table.
3452  */
3453 #define MLXSW_SP4_CONFIG_PROFILE_MAX_LAG 128
3454 
3455 static const struct mlxsw_config_profile mlxsw_sp4_config_profile = {
3456 	.used_max_lag			= 1,
3457 	.max_lag			= MLXSW_SP4_CONFIG_PROFILE_MAX_LAG,
3458 	.used_flood_mode                = 1,
3459 	.flood_mode                     = MLXSW_CMD_MBOX_CONFIG_PROFILE_FLOOD_MODE_CONTROLLED,
3460 	.used_max_ib_mc			= 1,
3461 	.max_ib_mc			= 0,
3462 	.used_max_pkey			= 1,
3463 	.max_pkey			= 0,
3464 	.used_ubridge			= 1,
3465 	.ubridge			= 1,
3466 	.swid_config			= {
3467 		{
3468 			.used_type	= 1,
3469 			.type		= MLXSW_PORT_SWID_TYPE_ETH,
3470 		}
3471 	},
3472 	.used_cqe_time_stamp_type	= 1,
3473 	.cqe_time_stamp_type		= MLXSW_CMD_MBOX_CONFIG_PROFILE_CQE_TIME_STAMP_TYPE_UTC,
3474 	.lag_mode_prefer_sw		= true,
3475 	.flood_mode_prefer_cff		= true,
3476 };
3477 
3478 static void
mlxsw_sp_resource_size_params_prepare(struct mlxsw_core * mlxsw_core,struct devlink_resource_size_params * kvd_size_params,struct devlink_resource_size_params * linear_size_params,struct devlink_resource_size_params * hash_double_size_params,struct devlink_resource_size_params * hash_single_size_params)3479 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
3480 				      struct devlink_resource_size_params *kvd_size_params,
3481 				      struct devlink_resource_size_params *linear_size_params,
3482 				      struct devlink_resource_size_params *hash_double_size_params,
3483 				      struct devlink_resource_size_params *hash_single_size_params)
3484 {
3485 	u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3486 						 KVD_SINGLE_MIN_SIZE);
3487 	u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
3488 						 KVD_DOUBLE_MIN_SIZE);
3489 	u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3490 	u32 linear_size_min = 0;
3491 
3492 	devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
3493 					  MLXSW_SP_KVD_GRANULARITY,
3494 					  DEVLINK_RESOURCE_UNIT_ENTRY);
3495 	devlink_resource_size_params_init(linear_size_params, linear_size_min,
3496 					  kvd_size - single_size_min -
3497 					  double_size_min,
3498 					  MLXSW_SP_KVD_GRANULARITY,
3499 					  DEVLINK_RESOURCE_UNIT_ENTRY);
3500 	devlink_resource_size_params_init(hash_double_size_params,
3501 					  double_size_min,
3502 					  kvd_size - single_size_min -
3503 					  linear_size_min,
3504 					  MLXSW_SP_KVD_GRANULARITY,
3505 					  DEVLINK_RESOURCE_UNIT_ENTRY);
3506 	devlink_resource_size_params_init(hash_single_size_params,
3507 					  single_size_min,
3508 					  kvd_size - double_size_min -
3509 					  linear_size_min,
3510 					  MLXSW_SP_KVD_GRANULARITY,
3511 					  DEVLINK_RESOURCE_UNIT_ENTRY);
3512 }
3513 
mlxsw_sp1_resources_kvd_register(struct mlxsw_core * mlxsw_core)3514 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
3515 {
3516 	struct devlink *devlink = priv_to_devlink(mlxsw_core);
3517 	struct devlink_resource_size_params hash_single_size_params;
3518 	struct devlink_resource_size_params hash_double_size_params;
3519 	struct devlink_resource_size_params linear_size_params;
3520 	struct devlink_resource_size_params kvd_size_params;
3521 	u32 kvd_size, single_size, double_size, linear_size;
3522 	const struct mlxsw_config_profile *profile;
3523 	int err;
3524 
3525 	profile = &mlxsw_sp1_config_profile;
3526 	if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
3527 		return -EIO;
3528 
3529 	mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
3530 					      &linear_size_params,
3531 					      &hash_double_size_params,
3532 					      &hash_single_size_params);
3533 
3534 	kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3535 	err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
3536 				     kvd_size, MLXSW_SP_RESOURCE_KVD,
3537 				     DEVLINK_RESOURCE_ID_PARENT_TOP,
3538 				     &kvd_size_params);
3539 	if (err)
3540 		return err;
3541 
3542 	linear_size = profile->kvd_linear_size;
3543 	err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
3544 				     linear_size,
3545 				     MLXSW_SP_RESOURCE_KVD_LINEAR,
3546 				     MLXSW_SP_RESOURCE_KVD,
3547 				     &linear_size_params);
3548 	if (err)
3549 		return err;
3550 
3551 	err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
3552 	if  (err)
3553 		return err;
3554 
3555 	double_size = kvd_size - linear_size;
3556 	double_size *= profile->kvd_hash_double_parts;
3557 	double_size /= profile->kvd_hash_double_parts +
3558 		       profile->kvd_hash_single_parts;
3559 	double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
3560 	err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
3561 				     double_size,
3562 				     MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3563 				     MLXSW_SP_RESOURCE_KVD,
3564 				     &hash_double_size_params);
3565 	if (err)
3566 		return err;
3567 
3568 	single_size = kvd_size - double_size - linear_size;
3569 	err = devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
3570 				     single_size,
3571 				     MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3572 				     MLXSW_SP_RESOURCE_KVD,
3573 				     &hash_single_size_params);
3574 	if (err)
3575 		return err;
3576 
3577 	return 0;
3578 }
3579 
mlxsw_sp2_resources_kvd_register(struct mlxsw_core * mlxsw_core)3580 static int mlxsw_sp2_resources_kvd_register(struct mlxsw_core *mlxsw_core)
3581 {
3582 	struct devlink *devlink = priv_to_devlink(mlxsw_core);
3583 	struct devlink_resource_size_params kvd_size_params;
3584 	u32 kvd_size;
3585 
3586 	if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
3587 		return -EIO;
3588 
3589 	kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
3590 	devlink_resource_size_params_init(&kvd_size_params, kvd_size, kvd_size,
3591 					  MLXSW_SP_KVD_GRANULARITY,
3592 					  DEVLINK_RESOURCE_UNIT_ENTRY);
3593 
3594 	return devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
3595 				      kvd_size, MLXSW_SP_RESOURCE_KVD,
3596 				      DEVLINK_RESOURCE_ID_PARENT_TOP,
3597 				      &kvd_size_params);
3598 }
3599 
mlxsw_sp_resources_span_register(struct mlxsw_core * mlxsw_core)3600 static int mlxsw_sp_resources_span_register(struct mlxsw_core *mlxsw_core)
3601 {
3602 	struct devlink *devlink = priv_to_devlink(mlxsw_core);
3603 	struct devlink_resource_size_params span_size_params;
3604 	u32 max_span;
3605 
3606 	if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_SPAN))
3607 		return -EIO;
3608 
3609 	max_span = MLXSW_CORE_RES_GET(mlxsw_core, MAX_SPAN);
3610 	devlink_resource_size_params_init(&span_size_params, max_span, max_span,
3611 					  1, DEVLINK_RESOURCE_UNIT_ENTRY);
3612 
3613 	return devl_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_SPAN,
3614 				      max_span, MLXSW_SP_RESOURCE_SPAN,
3615 				      DEVLINK_RESOURCE_ID_PARENT_TOP,
3616 				      &span_size_params);
3617 }
3618 
3619 static int
mlxsw_sp_resources_rif_mac_profile_register(struct mlxsw_core * mlxsw_core)3620 mlxsw_sp_resources_rif_mac_profile_register(struct mlxsw_core *mlxsw_core)
3621 {
3622 	struct devlink *devlink = priv_to_devlink(mlxsw_core);
3623 	struct devlink_resource_size_params size_params;
3624 	u8 max_rif_mac_profiles;
3625 
3626 	if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_RIF_MAC_PROFILES))
3627 		max_rif_mac_profiles = 1;
3628 	else
3629 		max_rif_mac_profiles = MLXSW_CORE_RES_GET(mlxsw_core,
3630 							  MAX_RIF_MAC_PROFILES);
3631 	devlink_resource_size_params_init(&size_params, max_rif_mac_profiles,
3632 					  max_rif_mac_profiles, 1,
3633 					  DEVLINK_RESOURCE_UNIT_ENTRY);
3634 
3635 	return devl_resource_register(devlink,
3636 				      "rif_mac_profiles",
3637 				      max_rif_mac_profiles,
3638 				      MLXSW_SP_RESOURCE_RIF_MAC_PROFILES,
3639 				      DEVLINK_RESOURCE_ID_PARENT_TOP,
3640 				      &size_params);
3641 }
3642 
mlxsw_sp_resources_rifs_register(struct mlxsw_core * mlxsw_core)3643 static int mlxsw_sp_resources_rifs_register(struct mlxsw_core *mlxsw_core)
3644 {
3645 	struct devlink *devlink = priv_to_devlink(mlxsw_core);
3646 	struct devlink_resource_size_params size_params;
3647 	u64 max_rifs;
3648 
3649 	if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_RIFS))
3650 		return -EIO;
3651 
3652 	max_rifs = MLXSW_CORE_RES_GET(mlxsw_core, MAX_RIFS);
3653 	devlink_resource_size_params_init(&size_params, max_rifs, max_rifs,
3654 					  1, DEVLINK_RESOURCE_UNIT_ENTRY);
3655 
3656 	return devl_resource_register(devlink, "rifs", max_rifs,
3657 				      MLXSW_SP_RESOURCE_RIFS,
3658 				      DEVLINK_RESOURCE_ID_PARENT_TOP,
3659 				      &size_params);
3660 }
3661 
3662 static int
mlxsw_sp_resources_port_range_register(struct mlxsw_core * mlxsw_core)3663 mlxsw_sp_resources_port_range_register(struct mlxsw_core *mlxsw_core)
3664 {
3665 	struct devlink *devlink = priv_to_devlink(mlxsw_core);
3666 	struct devlink_resource_size_params size_params;
3667 	u64 max;
3668 
3669 	if (!MLXSW_CORE_RES_VALID(mlxsw_core, ACL_MAX_L4_PORT_RANGE))
3670 		return -EIO;
3671 
3672 	max = MLXSW_CORE_RES_GET(mlxsw_core, ACL_MAX_L4_PORT_RANGE);
3673 	devlink_resource_size_params_init(&size_params, max, max, 1,
3674 					  DEVLINK_RESOURCE_UNIT_ENTRY);
3675 
3676 	return devl_resource_register(devlink, "port_range_registers", max,
3677 				      MLXSW_SP_RESOURCE_PORT_RANGE_REGISTERS,
3678 				      DEVLINK_RESOURCE_ID_PARENT_TOP,
3679 				      &size_params);
3680 }
3681 
mlxsw_sp1_resources_register(struct mlxsw_core * mlxsw_core)3682 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
3683 {
3684 	int err;
3685 
3686 	err = mlxsw_sp1_resources_kvd_register(mlxsw_core);
3687 	if (err)
3688 		return err;
3689 
3690 	err = mlxsw_sp_resources_span_register(mlxsw_core);
3691 	if (err)
3692 		goto err_resources_span_register;
3693 
3694 	err = mlxsw_sp_counter_resources_register(mlxsw_core);
3695 	if (err)
3696 		goto err_resources_counter_register;
3697 
3698 	err = mlxsw_sp_policer_resources_register(mlxsw_core);
3699 	if (err)
3700 		goto err_policer_resources_register;
3701 
3702 	err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core);
3703 	if (err)
3704 		goto err_resources_rif_mac_profile_register;
3705 
3706 	err = mlxsw_sp_resources_rifs_register(mlxsw_core);
3707 	if (err)
3708 		goto err_resources_rifs_register;
3709 
3710 	err = mlxsw_sp_resources_port_range_register(mlxsw_core);
3711 	if (err)
3712 		goto err_resources_port_range_register;
3713 
3714 	return 0;
3715 
3716 err_resources_port_range_register:
3717 err_resources_rifs_register:
3718 err_resources_rif_mac_profile_register:
3719 err_policer_resources_register:
3720 err_resources_counter_register:
3721 err_resources_span_register:
3722 	devl_resources_unregister(priv_to_devlink(mlxsw_core));
3723 	return err;
3724 }
3725 
mlxsw_sp2_resources_register(struct mlxsw_core * mlxsw_core)3726 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
3727 {
3728 	int err;
3729 
3730 	err = mlxsw_sp2_resources_kvd_register(mlxsw_core);
3731 	if (err)
3732 		return err;
3733 
3734 	err = mlxsw_sp_resources_span_register(mlxsw_core);
3735 	if (err)
3736 		goto err_resources_span_register;
3737 
3738 	err = mlxsw_sp_counter_resources_register(mlxsw_core);
3739 	if (err)
3740 		goto err_resources_counter_register;
3741 
3742 	err = mlxsw_sp_policer_resources_register(mlxsw_core);
3743 	if (err)
3744 		goto err_policer_resources_register;
3745 
3746 	err = mlxsw_sp_resources_rif_mac_profile_register(mlxsw_core);
3747 	if (err)
3748 		goto err_resources_rif_mac_profile_register;
3749 
3750 	err = mlxsw_sp_resources_rifs_register(mlxsw_core);
3751 	if (err)
3752 		goto err_resources_rifs_register;
3753 
3754 	err = mlxsw_sp_resources_port_range_register(mlxsw_core);
3755 	if (err)
3756 		goto err_resources_port_range_register;
3757 
3758 	return 0;
3759 
3760 err_resources_port_range_register:
3761 err_resources_rifs_register:
3762 err_resources_rif_mac_profile_register:
3763 err_policer_resources_register:
3764 err_resources_counter_register:
3765 err_resources_span_register:
3766 	devl_resources_unregister(priv_to_devlink(mlxsw_core));
3767 	return err;
3768 }
3769 
mlxsw_sp_kvd_sizes_get(struct mlxsw_core * mlxsw_core,const struct mlxsw_config_profile * profile,u64 * p_single_size,u64 * p_double_size,u64 * p_linear_size)3770 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
3771 				  const struct mlxsw_config_profile *profile,
3772 				  u64 *p_single_size, u64 *p_double_size,
3773 				  u64 *p_linear_size)
3774 {
3775 	struct devlink *devlink = priv_to_devlink(mlxsw_core);
3776 	u32 double_size;
3777 	int err;
3778 
3779 	if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3780 	    !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
3781 		return -EIO;
3782 
3783 	/* The hash part is what left of the kvd without the
3784 	 * linear part. It is split to the single size and
3785 	 * double size by the parts ratio from the profile.
3786 	 * Both sizes must be a multiplications of the
3787 	 * granularity from the profile. In case the user
3788 	 * provided the sizes they are obtained via devlink.
3789 	 */
3790 	err = devl_resource_size_get(devlink,
3791 				     MLXSW_SP_RESOURCE_KVD_LINEAR,
3792 				     p_linear_size);
3793 	if (err)
3794 		*p_linear_size = profile->kvd_linear_size;
3795 
3796 	err = devl_resource_size_get(devlink,
3797 				     MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
3798 				     p_double_size);
3799 	if (err) {
3800 		double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3801 			      *p_linear_size;
3802 		double_size *= profile->kvd_hash_double_parts;
3803 		double_size /= profile->kvd_hash_double_parts +
3804 			       profile->kvd_hash_single_parts;
3805 		*p_double_size = rounddown(double_size,
3806 					   MLXSW_SP_KVD_GRANULARITY);
3807 	}
3808 
3809 	err = devl_resource_size_get(devlink,
3810 				     MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
3811 				     p_single_size);
3812 	if (err)
3813 		*p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
3814 				 *p_double_size - *p_linear_size;
3815 
3816 	/* Check results are legal. */
3817 	if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
3818 	    *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
3819 	    MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
3820 		return -EIO;
3821 
3822 	return 0;
3823 }
3824 
mlxsw_sp_ptp_transmitted(struct mlxsw_core * mlxsw_core,struct sk_buff * skb,u16 local_port)3825 static void mlxsw_sp_ptp_transmitted(struct mlxsw_core *mlxsw_core,
3826 				     struct sk_buff *skb, u16 local_port)
3827 {
3828 	struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
3829 
3830 	skb_pull(skb, MLXSW_TXHDR_LEN);
3831 	mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port);
3832 }
3833 
3834 static struct mlxsw_driver mlxsw_sp1_driver = {
3835 	.kind				= mlxsw_sp1_driver_name,
3836 	.priv_size			= sizeof(struct mlxsw_sp),
3837 	.fw_req_rev			= &mlxsw_sp1_fw_rev,
3838 	.fw_filename			= MLXSW_SP1_FW_FILENAME,
3839 	.init				= mlxsw_sp1_init,
3840 	.fini				= mlxsw_sp_fini,
3841 	.port_split			= mlxsw_sp_port_split,
3842 	.port_unsplit			= mlxsw_sp_port_unsplit,
3843 	.sb_pool_get			= mlxsw_sp_sb_pool_get,
3844 	.sb_pool_set			= mlxsw_sp_sb_pool_set,
3845 	.sb_port_pool_get		= mlxsw_sp_sb_port_pool_get,
3846 	.sb_port_pool_set		= mlxsw_sp_sb_port_pool_set,
3847 	.sb_tc_pool_bind_get		= mlxsw_sp_sb_tc_pool_bind_get,
3848 	.sb_tc_pool_bind_set		= mlxsw_sp_sb_tc_pool_bind_set,
3849 	.sb_occ_snapshot		= mlxsw_sp_sb_occ_snapshot,
3850 	.sb_occ_max_clear		= mlxsw_sp_sb_occ_max_clear,
3851 	.sb_occ_port_pool_get		= mlxsw_sp_sb_occ_port_pool_get,
3852 	.sb_occ_tc_port_bind_get	= mlxsw_sp_sb_occ_tc_port_bind_get,
3853 	.trap_init			= mlxsw_sp_trap_init,
3854 	.trap_fini			= mlxsw_sp_trap_fini,
3855 	.trap_action_set		= mlxsw_sp_trap_action_set,
3856 	.trap_group_init		= mlxsw_sp_trap_group_init,
3857 	.trap_group_set			= mlxsw_sp_trap_group_set,
3858 	.trap_policer_init		= mlxsw_sp_trap_policer_init,
3859 	.trap_policer_fini		= mlxsw_sp_trap_policer_fini,
3860 	.trap_policer_set		= mlxsw_sp_trap_policer_set,
3861 	.trap_policer_counter_get	= mlxsw_sp_trap_policer_counter_get,
3862 	.resources_register		= mlxsw_sp1_resources_register,
3863 	.kvd_sizes_get			= mlxsw_sp_kvd_sizes_get,
3864 	.ptp_transmitted		= mlxsw_sp_ptp_transmitted,
3865 	.profile			= &mlxsw_sp1_config_profile,
3866 	.sdq_supports_cqe_v2		= false,
3867 };
3868 
3869 static struct mlxsw_driver mlxsw_sp2_driver = {
3870 	.kind				= mlxsw_sp2_driver_name,
3871 	.priv_size			= sizeof(struct mlxsw_sp),
3872 	.fw_req_rev			= &mlxsw_sp2_fw_rev,
3873 	.fw_filename			= MLXSW_SP2_FW_FILENAME,
3874 	.init				= mlxsw_sp2_init,
3875 	.fini				= mlxsw_sp_fini,
3876 	.port_split			= mlxsw_sp_port_split,
3877 	.port_unsplit			= mlxsw_sp_port_unsplit,
3878 	.ports_remove_selected		= mlxsw_sp_ports_remove_selected,
3879 	.sb_pool_get			= mlxsw_sp_sb_pool_get,
3880 	.sb_pool_set			= mlxsw_sp_sb_pool_set,
3881 	.sb_port_pool_get		= mlxsw_sp_sb_port_pool_get,
3882 	.sb_port_pool_set		= mlxsw_sp_sb_port_pool_set,
3883 	.sb_tc_pool_bind_get		= mlxsw_sp_sb_tc_pool_bind_get,
3884 	.sb_tc_pool_bind_set		= mlxsw_sp_sb_tc_pool_bind_set,
3885 	.sb_occ_snapshot		= mlxsw_sp_sb_occ_snapshot,
3886 	.sb_occ_max_clear		= mlxsw_sp_sb_occ_max_clear,
3887 	.sb_occ_port_pool_get		= mlxsw_sp_sb_occ_port_pool_get,
3888 	.sb_occ_tc_port_bind_get	= mlxsw_sp_sb_occ_tc_port_bind_get,
3889 	.trap_init			= mlxsw_sp_trap_init,
3890 	.trap_fini			= mlxsw_sp_trap_fini,
3891 	.trap_action_set		= mlxsw_sp_trap_action_set,
3892 	.trap_group_init		= mlxsw_sp_trap_group_init,
3893 	.trap_group_set			= mlxsw_sp_trap_group_set,
3894 	.trap_policer_init		= mlxsw_sp_trap_policer_init,
3895 	.trap_policer_fini		= mlxsw_sp_trap_policer_fini,
3896 	.trap_policer_set		= mlxsw_sp_trap_policer_set,
3897 	.trap_policer_counter_get	= mlxsw_sp_trap_policer_counter_get,
3898 	.resources_register		= mlxsw_sp2_resources_register,
3899 	.ptp_transmitted		= mlxsw_sp_ptp_transmitted,
3900 	.profile			= &mlxsw_sp2_config_profile,
3901 	.sdq_supports_cqe_v2		= true,
3902 };
3903 
3904 static struct mlxsw_driver mlxsw_sp3_driver = {
3905 	.kind				= mlxsw_sp3_driver_name,
3906 	.priv_size			= sizeof(struct mlxsw_sp),
3907 	.fw_req_rev			= &mlxsw_sp3_fw_rev,
3908 	.fw_filename			= MLXSW_SP3_FW_FILENAME,
3909 	.init				= mlxsw_sp3_init,
3910 	.fini				= mlxsw_sp_fini,
3911 	.port_split			= mlxsw_sp_port_split,
3912 	.port_unsplit			= mlxsw_sp_port_unsplit,
3913 	.ports_remove_selected		= mlxsw_sp_ports_remove_selected,
3914 	.sb_pool_get			= mlxsw_sp_sb_pool_get,
3915 	.sb_pool_set			= mlxsw_sp_sb_pool_set,
3916 	.sb_port_pool_get		= mlxsw_sp_sb_port_pool_get,
3917 	.sb_port_pool_set		= mlxsw_sp_sb_port_pool_set,
3918 	.sb_tc_pool_bind_get		= mlxsw_sp_sb_tc_pool_bind_get,
3919 	.sb_tc_pool_bind_set		= mlxsw_sp_sb_tc_pool_bind_set,
3920 	.sb_occ_snapshot		= mlxsw_sp_sb_occ_snapshot,
3921 	.sb_occ_max_clear		= mlxsw_sp_sb_occ_max_clear,
3922 	.sb_occ_port_pool_get		= mlxsw_sp_sb_occ_port_pool_get,
3923 	.sb_occ_tc_port_bind_get	= mlxsw_sp_sb_occ_tc_port_bind_get,
3924 	.trap_init			= mlxsw_sp_trap_init,
3925 	.trap_fini			= mlxsw_sp_trap_fini,
3926 	.trap_action_set		= mlxsw_sp_trap_action_set,
3927 	.trap_group_init		= mlxsw_sp_trap_group_init,
3928 	.trap_group_set			= mlxsw_sp_trap_group_set,
3929 	.trap_policer_init		= mlxsw_sp_trap_policer_init,
3930 	.trap_policer_fini		= mlxsw_sp_trap_policer_fini,
3931 	.trap_policer_set		= mlxsw_sp_trap_policer_set,
3932 	.trap_policer_counter_get	= mlxsw_sp_trap_policer_counter_get,
3933 	.resources_register		= mlxsw_sp2_resources_register,
3934 	.ptp_transmitted		= mlxsw_sp_ptp_transmitted,
3935 	.profile			= &mlxsw_sp2_config_profile,
3936 	.sdq_supports_cqe_v2		= true,
3937 };
3938 
3939 static struct mlxsw_driver mlxsw_sp4_driver = {
3940 	.kind				= mlxsw_sp4_driver_name,
3941 	.priv_size			= sizeof(struct mlxsw_sp),
3942 	.init				= mlxsw_sp4_init,
3943 	.fini				= mlxsw_sp_fini,
3944 	.port_split			= mlxsw_sp_port_split,
3945 	.port_unsplit			= mlxsw_sp_port_unsplit,
3946 	.ports_remove_selected		= mlxsw_sp_ports_remove_selected,
3947 	.sb_pool_get			= mlxsw_sp_sb_pool_get,
3948 	.sb_pool_set			= mlxsw_sp_sb_pool_set,
3949 	.sb_port_pool_get		= mlxsw_sp_sb_port_pool_get,
3950 	.sb_port_pool_set		= mlxsw_sp_sb_port_pool_set,
3951 	.sb_tc_pool_bind_get		= mlxsw_sp_sb_tc_pool_bind_get,
3952 	.sb_tc_pool_bind_set		= mlxsw_sp_sb_tc_pool_bind_set,
3953 	.sb_occ_snapshot		= mlxsw_sp_sb_occ_snapshot,
3954 	.sb_occ_max_clear		= mlxsw_sp_sb_occ_max_clear,
3955 	.sb_occ_port_pool_get		= mlxsw_sp_sb_occ_port_pool_get,
3956 	.sb_occ_tc_port_bind_get	= mlxsw_sp_sb_occ_tc_port_bind_get,
3957 	.trap_init			= mlxsw_sp_trap_init,
3958 	.trap_fini			= mlxsw_sp_trap_fini,
3959 	.trap_action_set		= mlxsw_sp_trap_action_set,
3960 	.trap_group_init		= mlxsw_sp_trap_group_init,
3961 	.trap_group_set			= mlxsw_sp_trap_group_set,
3962 	.trap_policer_init		= mlxsw_sp_trap_policer_init,
3963 	.trap_policer_fini		= mlxsw_sp_trap_policer_fini,
3964 	.trap_policer_set		= mlxsw_sp_trap_policer_set,
3965 	.trap_policer_counter_get	= mlxsw_sp_trap_policer_counter_get,
3966 	.resources_register		= mlxsw_sp2_resources_register,
3967 	.ptp_transmitted		= mlxsw_sp_ptp_transmitted,
3968 	.profile			= &mlxsw_sp4_config_profile,
3969 	.sdq_supports_cqe_v2		= true,
3970 };
3971 
mlxsw_sp_port_dev_check(const struct net_device * dev)3972 bool mlxsw_sp_port_dev_check(const struct net_device *dev)
3973 {
3974 	return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3975 }
3976 
mlxsw_sp_lower_dev_walk(struct net_device * lower_dev,struct netdev_nested_priv * priv)3977 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev,
3978 				   struct netdev_nested_priv *priv)
3979 {
3980 	int ret = 0;
3981 
3982 	if (mlxsw_sp_port_dev_check(lower_dev)) {
3983 		priv->data = (void *)netdev_priv(lower_dev);
3984 		ret = 1;
3985 	}
3986 
3987 	return ret;
3988 }
3989 
mlxsw_sp_port_dev_lower_find(struct net_device * dev)3990 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
3991 {
3992 	struct netdev_nested_priv priv = {
3993 		.data = NULL,
3994 	};
3995 
3996 	if (mlxsw_sp_port_dev_check(dev))
3997 		return netdev_priv(dev);
3998 
3999 	netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &priv);
4000 
4001 	return (struct mlxsw_sp_port *)priv.data;
4002 }
4003 
mlxsw_sp_lower_get(struct net_device * dev)4004 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
4005 {
4006 	struct mlxsw_sp_port *mlxsw_sp_port;
4007 
4008 	mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4009 	return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4010 }
4011 
mlxsw_sp_port_dev_lower_find_rcu(struct net_device * dev)4012 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
4013 {
4014 	struct netdev_nested_priv priv = {
4015 		.data = NULL,
4016 	};
4017 
4018 	if (mlxsw_sp_port_dev_check(dev))
4019 		return netdev_priv(dev);
4020 
4021 	netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4022 				      &priv);
4023 
4024 	return (struct mlxsw_sp_port *)priv.data;
4025 }
4026 
mlxsw_sp_parsing_depth_inc(struct mlxsw_sp * mlxsw_sp)4027 int mlxsw_sp_parsing_depth_inc(struct mlxsw_sp *mlxsw_sp)
4028 {
4029 	char mprs_pl[MLXSW_REG_MPRS_LEN];
4030 	int err = 0;
4031 
4032 	mutex_lock(&mlxsw_sp->parsing.lock);
4033 
4034 	if (refcount_inc_not_zero(&mlxsw_sp->parsing.parsing_depth_ref))
4035 		goto out_unlock;
4036 
4037 	mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_INCREASED_PARSING_DEPTH,
4038 			    mlxsw_sp->parsing.vxlan_udp_dport);
4039 	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl);
4040 	if (err)
4041 		goto out_unlock;
4042 
4043 	mlxsw_sp->parsing.parsing_depth = MLXSW_SP_INCREASED_PARSING_DEPTH;
4044 	refcount_set(&mlxsw_sp->parsing.parsing_depth_ref, 1);
4045 
4046 out_unlock:
4047 	mutex_unlock(&mlxsw_sp->parsing.lock);
4048 	return err;
4049 }
4050 
mlxsw_sp_parsing_depth_dec(struct mlxsw_sp * mlxsw_sp)4051 void mlxsw_sp_parsing_depth_dec(struct mlxsw_sp *mlxsw_sp)
4052 {
4053 	char mprs_pl[MLXSW_REG_MPRS_LEN];
4054 
4055 	mutex_lock(&mlxsw_sp->parsing.lock);
4056 
4057 	if (!refcount_dec_and_test(&mlxsw_sp->parsing.parsing_depth_ref))
4058 		goto out_unlock;
4059 
4060 	mlxsw_reg_mprs_pack(mprs_pl, MLXSW_SP_DEFAULT_PARSING_DEPTH,
4061 			    mlxsw_sp->parsing.vxlan_udp_dport);
4062 	mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl);
4063 	mlxsw_sp->parsing.parsing_depth = MLXSW_SP_DEFAULT_PARSING_DEPTH;
4064 
4065 out_unlock:
4066 	mutex_unlock(&mlxsw_sp->parsing.lock);
4067 }
4068 
mlxsw_sp_parsing_vxlan_udp_dport_set(struct mlxsw_sp * mlxsw_sp,__be16 udp_dport)4069 int mlxsw_sp_parsing_vxlan_udp_dport_set(struct mlxsw_sp *mlxsw_sp,
4070 					 __be16 udp_dport)
4071 {
4072 	char mprs_pl[MLXSW_REG_MPRS_LEN];
4073 	int err;
4074 
4075 	mutex_lock(&mlxsw_sp->parsing.lock);
4076 
4077 	mlxsw_reg_mprs_pack(mprs_pl, mlxsw_sp->parsing.parsing_depth,
4078 			    be16_to_cpu(udp_dport));
4079 	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mprs), mprs_pl);
4080 	if (err)
4081 		goto out_unlock;
4082 
4083 	mlxsw_sp->parsing.vxlan_udp_dport = be16_to_cpu(udp_dport);
4084 
4085 out_unlock:
4086 	mutex_unlock(&mlxsw_sp->parsing.lock);
4087 	return err;
4088 }
4089 
4090 static void
mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port * mlxsw_sp_port,struct net_device * lag_dev)4091 mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port,
4092 				 struct net_device *lag_dev)
4093 {
4094 	struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev);
4095 	struct net_device *upper_dev;
4096 	struct list_head *iter;
4097 
4098 	if (netif_is_bridge_port(lag_dev))
4099 		mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev);
4100 
4101 	netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
4102 		if (!netif_is_bridge_port(upper_dev))
4103 			continue;
4104 		br_dev = netdev_master_upper_dev_get(upper_dev);
4105 		mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev);
4106 	}
4107 }
4108 
4109 static struct mlxsw_sp_lag *
mlxsw_sp_lag_create(struct mlxsw_sp * mlxsw_sp,struct net_device * lag_dev,struct netlink_ext_ack * extack)4110 mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, struct net_device *lag_dev,
4111 		    struct netlink_ext_ack *extack)
4112 {
4113 	char sldr_pl[MLXSW_REG_SLDR_LEN];
4114 	struct mlxsw_sp_lag *lag;
4115 	u16 lag_id;
4116 	int i, err;
4117 
4118 	for (i = 0; i < mlxsw_sp->max_lag; i++) {
4119 		if (!mlxsw_sp->lags[i].dev)
4120 			break;
4121 	}
4122 
4123 	if (i == mlxsw_sp->max_lag) {
4124 		NL_SET_ERR_MSG_MOD(extack,
4125 				   "Exceeded number of supported LAG devices");
4126 		return ERR_PTR(-EBUSY);
4127 	}
4128 
4129 	lag_id = i;
4130 	mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4131 	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4132 	if (err)
4133 		return ERR_PTR(err);
4134 
4135 	lag = &mlxsw_sp->lags[lag_id];
4136 	lag->lag_id = lag_id;
4137 	lag->dev = lag_dev;
4138 	refcount_set(&lag->ref_count, 1);
4139 
4140 	return lag;
4141 }
4142 
4143 static int
mlxsw_sp_lag_destroy(struct mlxsw_sp * mlxsw_sp,struct mlxsw_sp_lag * lag)4144 mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_lag *lag)
4145 {
4146 	char sldr_pl[MLXSW_REG_SLDR_LEN];
4147 
4148 	lag->dev = NULL;
4149 
4150 	mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag->lag_id);
4151 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4152 }
4153 
mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id,u8 port_index)4154 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4155 				     u16 lag_id, u8 port_index)
4156 {
4157 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4158 	char slcor_pl[MLXSW_REG_SLCOR_LEN];
4159 
4160 	mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4161 				      lag_id, port_index);
4162 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4163 }
4164 
mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)4165 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4166 					u16 lag_id)
4167 {
4168 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4169 	char slcor_pl[MLXSW_REG_SLCOR_LEN];
4170 
4171 	mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4172 					 lag_id);
4173 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4174 }
4175 
mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)4176 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4177 					u16 lag_id)
4178 {
4179 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4180 	char slcor_pl[MLXSW_REG_SLCOR_LEN];
4181 
4182 	mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4183 					lag_id);
4184 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4185 }
4186 
mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)4187 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4188 					 u16 lag_id)
4189 {
4190 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4191 	char slcor_pl[MLXSW_REG_SLCOR_LEN];
4192 
4193 	mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4194 					 lag_id);
4195 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4196 }
4197 
4198 static struct mlxsw_sp_lag *
mlxsw_sp_lag_find(struct mlxsw_sp * mlxsw_sp,struct net_device * lag_dev)4199 mlxsw_sp_lag_find(struct mlxsw_sp *mlxsw_sp, struct net_device *lag_dev)
4200 {
4201 	int i;
4202 
4203 	for (i = 0; i < mlxsw_sp->max_lag; i++) {
4204 		if (!mlxsw_sp->lags[i].dev)
4205 			continue;
4206 
4207 		if (mlxsw_sp->lags[i].dev == lag_dev)
4208 			return &mlxsw_sp->lags[i];
4209 	}
4210 
4211 	return NULL;
4212 }
4213 
4214 static struct mlxsw_sp_lag *
mlxsw_sp_lag_get(struct mlxsw_sp * mlxsw_sp,struct net_device * lag_dev,struct netlink_ext_ack * extack)4215 mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, struct net_device *lag_dev,
4216 		 struct netlink_ext_ack *extack)
4217 {
4218 	struct mlxsw_sp_lag *lag;
4219 
4220 	lag = mlxsw_sp_lag_find(mlxsw_sp, lag_dev);
4221 	if (lag) {
4222 		refcount_inc(&lag->ref_count);
4223 		return lag;
4224 	}
4225 
4226 	return mlxsw_sp_lag_create(mlxsw_sp, lag_dev, extack);
4227 }
4228 
4229 static void
mlxsw_sp_lag_put(struct mlxsw_sp * mlxsw_sp,struct mlxsw_sp_lag * lag)4230 mlxsw_sp_lag_put(struct mlxsw_sp *mlxsw_sp, struct mlxsw_sp_lag *lag)
4231 {
4232 	if (!refcount_dec_and_test(&lag->ref_count))
4233 		return;
4234 
4235 	mlxsw_sp_lag_destroy(mlxsw_sp, lag);
4236 }
4237 
4238 static bool
mlxsw_sp_master_lag_check(struct mlxsw_sp * mlxsw_sp,struct net_device * lag_dev,struct netdev_lag_upper_info * lag_upper_info,struct netlink_ext_ack * extack)4239 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4240 			  struct net_device *lag_dev,
4241 			  struct netdev_lag_upper_info *lag_upper_info,
4242 			  struct netlink_ext_ack *extack)
4243 {
4244 	if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4245 		NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
4246 		return false;
4247 	}
4248 	return true;
4249 }
4250 
mlxsw_sp_port_lag_index_get(struct mlxsw_sp * mlxsw_sp,u16 lag_id,u8 * p_port_index)4251 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4252 				       u16 lag_id, u8 *p_port_index)
4253 {
4254 	u64 max_lag_members;
4255 	int i;
4256 
4257 	max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4258 					     MAX_LAG_MEMBERS);
4259 	for (i = 0; i < max_lag_members; i++) {
4260 		if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4261 			*p_port_index = i;
4262 			return 0;
4263 		}
4264 	}
4265 	return -EBUSY;
4266 }
4267 
mlxsw_sp_lag_uppers_bridge_join(struct mlxsw_sp_port * mlxsw_sp_port,struct net_device * lag_dev,struct netlink_ext_ack * extack)4268 static int mlxsw_sp_lag_uppers_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
4269 					   struct net_device *lag_dev,
4270 					   struct netlink_ext_ack *extack)
4271 {
4272 	struct net_device *upper_dev;
4273 	struct net_device *master;
4274 	struct list_head *iter;
4275 	int done = 0;
4276 	int err;
4277 
4278 	master = netdev_master_upper_dev_get(lag_dev);
4279 	if (master && netif_is_bridge_master(master)) {
4280 		err = mlxsw_sp_port_bridge_join(mlxsw_sp_port, lag_dev, master,
4281 						extack);
4282 		if (err)
4283 			return err;
4284 	}
4285 
4286 	netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
4287 		if (!is_vlan_dev(upper_dev))
4288 			continue;
4289 
4290 		master = netdev_master_upper_dev_get(upper_dev);
4291 		if (master && netif_is_bridge_master(master)) {
4292 			err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4293 							upper_dev, master,
4294 							extack);
4295 			if (err)
4296 				goto err_port_bridge_join;
4297 		}
4298 
4299 		++done;
4300 	}
4301 
4302 	return 0;
4303 
4304 err_port_bridge_join:
4305 	netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
4306 		if (!is_vlan_dev(upper_dev))
4307 			continue;
4308 
4309 		master = netdev_master_upper_dev_get(upper_dev);
4310 		if (!master || !netif_is_bridge_master(master))
4311 			continue;
4312 
4313 		if (!done--)
4314 			break;
4315 
4316 		mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, master);
4317 	}
4318 
4319 	master = netdev_master_upper_dev_get(lag_dev);
4320 	if (master && netif_is_bridge_master(master))
4321 		mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, master);
4322 
4323 	return err;
4324 }
4325 
4326 static void
mlxsw_sp_lag_uppers_bridge_leave(struct mlxsw_sp_port * mlxsw_sp_port,struct net_device * lag_dev)4327 mlxsw_sp_lag_uppers_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4328 				 struct net_device *lag_dev)
4329 {
4330 	struct net_device *upper_dev;
4331 	struct net_device *master;
4332 	struct list_head *iter;
4333 
4334 	netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
4335 		if (!is_vlan_dev(upper_dev))
4336 			continue;
4337 
4338 		master = netdev_master_upper_dev_get(upper_dev);
4339 		if (!master)
4340 			continue;
4341 
4342 		mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, master);
4343 	}
4344 
4345 	master = netdev_master_upper_dev_get(lag_dev);
4346 	if (master)
4347 		mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, master);
4348 }
4349 
mlxsw_sp_port_lag_join(struct mlxsw_sp_port * mlxsw_sp_port,struct net_device * lag_dev,struct netlink_ext_ack * extack)4350 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4351 				  struct net_device *lag_dev,
4352 				  struct netlink_ext_ack *extack)
4353 {
4354 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4355 	struct mlxsw_sp_lag *lag;
4356 	u16 lag_id;
4357 	u8 port_index;
4358 	int err;
4359 
4360 	lag = mlxsw_sp_lag_get(mlxsw_sp, lag_dev, extack);
4361 	if (IS_ERR(lag))
4362 		return PTR_ERR(lag);
4363 
4364 	lag_id = lag->lag_id;
4365 	err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4366 	if (err)
4367 		goto err_lag_uppers_bridge_join;
4368 
4369 	err = mlxsw_sp_lag_uppers_bridge_join(mlxsw_sp_port, lag_dev,
4370 					      extack);
4371 	if (err)
4372 		goto err_lag_uppers_bridge_join;
4373 
4374 	err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4375 	if (err)
4376 		goto err_col_port_add;
4377 
4378 	mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4379 				   mlxsw_sp_port->local_port);
4380 	mlxsw_sp_port->lag_id = lag_id;
4381 	mlxsw_sp_port->lagged = 1;
4382 
4383 	err = mlxsw_sp_fid_port_join_lag(mlxsw_sp_port);
4384 	if (err)
4385 		goto err_fid_port_join_lag;
4386 
4387 	/* Port is no longer usable as a router interface */
4388 	if (mlxsw_sp_port->default_vlan->fid)
4389 		mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan);
4390 
4391 	/* Join a router interface configured on the LAG, if exists */
4392 	err = mlxsw_sp_router_port_join_lag(mlxsw_sp_port, lag_dev,
4393 					    extack);
4394 	if (err)
4395 		goto err_router_join;
4396 
4397 	err = mlxsw_sp_netdevice_enslavement_replay(mlxsw_sp, lag_dev, extack);
4398 	if (err)
4399 		goto err_replay;
4400 
4401 	return 0;
4402 
4403 err_replay:
4404 	mlxsw_sp_router_port_leave_lag(mlxsw_sp_port, lag_dev);
4405 err_router_join:
4406 	mlxsw_sp_fid_port_leave_lag(mlxsw_sp_port);
4407 err_fid_port_join_lag:
4408 	mlxsw_sp_port->lagged = 0;
4409 	mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4410 				     mlxsw_sp_port->local_port);
4411 	mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4412 err_col_port_add:
4413 	mlxsw_sp_lag_uppers_bridge_leave(mlxsw_sp_port, lag_dev);
4414 err_lag_uppers_bridge_join:
4415 	mlxsw_sp_lag_put(mlxsw_sp, lag);
4416 	return err;
4417 }
4418 
mlxsw_sp_port_lag_leave(struct mlxsw_sp_port * mlxsw_sp_port,struct net_device * lag_dev)4419 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4420 				    struct net_device *lag_dev)
4421 {
4422 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4423 	u16 lag_id = mlxsw_sp_port->lag_id;
4424 	struct mlxsw_sp_lag *lag;
4425 
4426 	if (!mlxsw_sp_port->lagged)
4427 		return;
4428 	lag = &mlxsw_sp->lags[lag_id];
4429 
4430 	mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
4431 
4432 	/* Any VLANs configured on the port are no longer valid */
4433 	mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false);
4434 	mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan);
4435 	/* Make the LAG and its directly linked uppers leave bridges they
4436 	 * are memeber in
4437 	 */
4438 	mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev);
4439 
4440 	mlxsw_sp_fid_port_leave_lag(mlxsw_sp_port);
4441 
4442 	mlxsw_sp_lag_put(mlxsw_sp, lag);
4443 
4444 	mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4445 				     mlxsw_sp_port->local_port);
4446 	mlxsw_sp_port->lagged = 0;
4447 
4448 	/* Make sure untagged frames are allowed to ingress */
4449 	mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID,
4450 			       ETH_P_8021Q);
4451 }
4452 
mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)4453 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4454 				      u16 lag_id)
4455 {
4456 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4457 	char sldr_pl[MLXSW_REG_SLDR_LEN];
4458 
4459 	mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4460 					 mlxsw_sp_port->local_port);
4461 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4462 }
4463 
mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port * mlxsw_sp_port,u16 lag_id)4464 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4465 					 u16 lag_id)
4466 {
4467 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4468 	char sldr_pl[MLXSW_REG_SLDR_LEN];
4469 
4470 	mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4471 					    mlxsw_sp_port->local_port);
4472 	return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4473 }
4474 
4475 static int
mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port * mlxsw_sp_port)4476 mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port)
4477 {
4478 	int err;
4479 
4480 	err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port,
4481 					   mlxsw_sp_port->lag_id);
4482 	if (err)
4483 		return err;
4484 
4485 	err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
4486 	if (err)
4487 		goto err_dist_port_add;
4488 
4489 	return 0;
4490 
4491 err_dist_port_add:
4492 	mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id);
4493 	return err;
4494 }
4495 
4496 static int
mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port * mlxsw_sp_port)4497 mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port)
4498 {
4499 	int err;
4500 
4501 	err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4502 					    mlxsw_sp_port->lag_id);
4503 	if (err)
4504 		return err;
4505 
4506 	err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port,
4507 					    mlxsw_sp_port->lag_id);
4508 	if (err)
4509 		goto err_col_port_disable;
4510 
4511 	return 0;
4512 
4513 err_col_port_disable:
4514 	mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
4515 	return err;
4516 }
4517 
mlxsw_sp_port_lag_changed(struct mlxsw_sp_port * mlxsw_sp_port,struct netdev_lag_lower_state_info * info)4518 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4519 				     struct netdev_lag_lower_state_info *info)
4520 {
4521 	if (info->tx_enabled)
4522 		return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port);
4523 	else
4524 		return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
4525 }
4526 
mlxsw_sp_port_stp_set(struct mlxsw_sp_port * mlxsw_sp_port,bool enable)4527 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4528 				 bool enable)
4529 {
4530 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4531 	enum mlxsw_reg_spms_state spms_state;
4532 	char *spms_pl;
4533 	u16 vid;
4534 	int err;
4535 
4536 	spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4537 			      MLXSW_REG_SPMS_STATE_DISCARDING;
4538 
4539 	spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4540 	if (!spms_pl)
4541 		return -ENOMEM;
4542 	mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4543 
4544 	for (vid = 0; vid < VLAN_N_VID; vid++)
4545 		mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4546 
4547 	err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4548 	kfree(spms_pl);
4549 	return err;
4550 }
4551 
mlxsw_sp_port_ovs_join(struct mlxsw_sp_port * mlxsw_sp_port)4552 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4553 {
4554 	u16 vid = 1;
4555 	int err;
4556 
4557 	err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
4558 	if (err)
4559 		return err;
4560 	err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4561 	if (err)
4562 		goto err_port_stp_set;
4563 	err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
4564 				     true, false);
4565 	if (err)
4566 		goto err_port_vlan_set;
4567 
4568 	for (; vid <= VLAN_N_VID - 1; vid++) {
4569 		err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4570 						     vid, false);
4571 		if (err)
4572 			goto err_vid_learning_set;
4573 	}
4574 
4575 	return 0;
4576 
4577 err_vid_learning_set:
4578 	for (vid--; vid >= 1; vid--)
4579 		mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
4580 err_port_vlan_set:
4581 	mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4582 err_port_stp_set:
4583 	mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
4584 	return err;
4585 }
4586 
mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port * mlxsw_sp_port)4587 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4588 {
4589 	u16 vid;
4590 
4591 	for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4592 		mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4593 					       vid, true);
4594 
4595 	mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
4596 			       false, false);
4597 	mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
4598 	mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
4599 }
4600 
mlxsw_sp_bridge_has_multiple_vxlans(struct net_device * br_dev)4601 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev)
4602 {
4603 	unsigned int num_vxlans = 0;
4604 	struct net_device *dev;
4605 	struct list_head *iter;
4606 
4607 	netdev_for_each_lower_dev(br_dev, dev, iter) {
4608 		if (netif_is_vxlan(dev))
4609 			num_vxlans++;
4610 	}
4611 
4612 	return num_vxlans > 1;
4613 }
4614 
mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device * br_dev)4615 static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev)
4616 {
4617 	DECLARE_BITMAP(vlans, VLAN_N_VID) = {0};
4618 	struct net_device *dev;
4619 	struct list_head *iter;
4620 
4621 	netdev_for_each_lower_dev(br_dev, dev, iter) {
4622 		u16 pvid;
4623 		int err;
4624 
4625 		if (!netif_is_vxlan(dev))
4626 			continue;
4627 
4628 		err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid);
4629 		if (err || !pvid)
4630 			continue;
4631 
4632 		if (test_and_set_bit(pvid, vlans))
4633 			return false;
4634 	}
4635 
4636 	return true;
4637 }
4638 
mlxsw_sp_bridge_vxlan_is_valid(struct net_device * br_dev,struct netlink_ext_ack * extack)4639 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev,
4640 					   struct netlink_ext_ack *extack)
4641 {
4642 	if (br_multicast_enabled(br_dev)) {
4643 		NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device");
4644 		return false;
4645 	}
4646 
4647 	if (!br_vlan_enabled(br_dev) &&
4648 	    mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) {
4649 		NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge");
4650 		return false;
4651 	}
4652 
4653 	if (br_vlan_enabled(br_dev) &&
4654 	    !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) {
4655 		NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged");
4656 		return false;
4657 	}
4658 
4659 	return true;
4660 }
4661 
mlxsw_sp_netdev_is_master(struct net_device * upper_dev,struct net_device * dev)4662 static bool mlxsw_sp_netdev_is_master(struct net_device *upper_dev,
4663 				      struct net_device *dev)
4664 {
4665 	return upper_dev == netdev_master_upper_dev_get(dev);
4666 }
4667 
4668 static int __mlxsw_sp_netdevice_event(struct mlxsw_sp *mlxsw_sp,
4669 				      unsigned long event, void *ptr,
4670 				      bool process_foreign);
4671 
mlxsw_sp_netdevice_validate_uppers(struct mlxsw_sp * mlxsw_sp,struct net_device * dev,struct netlink_ext_ack * extack)4672 static int mlxsw_sp_netdevice_validate_uppers(struct mlxsw_sp *mlxsw_sp,
4673 					      struct net_device *dev,
4674 					      struct netlink_ext_ack *extack)
4675 {
4676 	struct net_device *upper_dev;
4677 	struct list_head *iter;
4678 	int err;
4679 
4680 	netdev_for_each_upper_dev_rcu(dev, upper_dev, iter) {
4681 		struct netdev_notifier_changeupper_info info = {
4682 			.info = {
4683 				.dev = dev,
4684 				.extack = extack,
4685 			},
4686 			.master = mlxsw_sp_netdev_is_master(upper_dev, dev),
4687 			.upper_dev = upper_dev,
4688 			.linking = true,
4689 
4690 			/* upper_info is relevant for LAG devices. But we would
4691 			 * only need this if LAG were a valid upper above
4692 			 * another upper (e.g. a bridge that is a member of a
4693 			 * LAG), and that is never a valid configuration. So we
4694 			 * can keep this as NULL.
4695 			 */
4696 			.upper_info = NULL,
4697 		};
4698 
4699 		err = __mlxsw_sp_netdevice_event(mlxsw_sp,
4700 						 NETDEV_PRECHANGEUPPER,
4701 						 &info, true);
4702 		if (err)
4703 			return err;
4704 
4705 		err = mlxsw_sp_netdevice_validate_uppers(mlxsw_sp, upper_dev,
4706 							 extack);
4707 		if (err)
4708 			return err;
4709 	}
4710 
4711 	return 0;
4712 }
4713 
mlxsw_sp_netdevice_port_upper_event(struct net_device * lower_dev,struct net_device * dev,unsigned long event,void * ptr,bool replay_deslavement)4714 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4715 					       struct net_device *dev,
4716 					       unsigned long event, void *ptr,
4717 					       bool replay_deslavement)
4718 {
4719 	struct netdev_notifier_changeupper_info *info;
4720 	struct mlxsw_sp_port *mlxsw_sp_port;
4721 	struct netlink_ext_ack *extack;
4722 	struct net_device *upper_dev;
4723 	struct mlxsw_sp *mlxsw_sp;
4724 	int err = 0;
4725 	u16 proto;
4726 
4727 	mlxsw_sp_port = netdev_priv(dev);
4728 	mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4729 	info = ptr;
4730 	extack = netdev_notifier_info_to_extack(&info->info);
4731 
4732 	switch (event) {
4733 	case NETDEV_PRECHANGEUPPER:
4734 		upper_dev = info->upper_dev;
4735 		if (!is_vlan_dev(upper_dev) &&
4736 		    !netif_is_lag_master(upper_dev) &&
4737 		    !netif_is_bridge_master(upper_dev) &&
4738 		    !netif_is_ovs_master(upper_dev) &&
4739 		    !netif_is_macvlan(upper_dev) &&
4740 		    !netif_is_l3_master(upper_dev)) {
4741 			NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4742 			return -EINVAL;
4743 		}
4744 		if (!info->linking)
4745 			break;
4746 		if (netif_is_bridge_master(upper_dev) &&
4747 		    !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
4748 		    mlxsw_sp_bridge_has_vxlan(upper_dev) &&
4749 		    !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
4750 			return -EOPNOTSUPP;
4751 		if (netdev_has_any_upper_dev(upper_dev) &&
4752 		    (!netif_is_bridge_master(upper_dev) ||
4753 		     !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4754 							  upper_dev))) {
4755 			err = mlxsw_sp_netdevice_validate_uppers(mlxsw_sp,
4756 								 upper_dev,
4757 								 extack);
4758 			if (err)
4759 				return err;
4760 		}
4761 		if (netif_is_lag_master(upper_dev) &&
4762 		    !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4763 					       info->upper_info, extack))
4764 			return -EINVAL;
4765 		if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4766 			NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
4767 			return -EINVAL;
4768 		}
4769 		if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4770 		    !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4771 			NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
4772 			return -EINVAL;
4773 		}
4774 		if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4775 			NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
4776 			return -EINVAL;
4777 		}
4778 		if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4779 			NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
4780 			return -EINVAL;
4781 		}
4782 		if (netif_is_bridge_master(upper_dev)) {
4783 			br_vlan_get_proto(upper_dev, &proto);
4784 			if (br_vlan_enabled(upper_dev) &&
4785 			    proto != ETH_P_8021Q && proto != ETH_P_8021AD) {
4786 				NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a bridge with unknown VLAN protocol is not supported");
4787 				return -EOPNOTSUPP;
4788 			}
4789 			if (vlan_uses_dev(lower_dev) &&
4790 			    br_vlan_enabled(upper_dev) &&
4791 			    proto == ETH_P_8021AD) {
4792 				NL_SET_ERR_MSG_MOD(extack, "Enslaving a port that already has a VLAN upper to an 802.1ad bridge is not supported");
4793 				return -EOPNOTSUPP;
4794 			}
4795 		}
4796 		if (netif_is_bridge_port(lower_dev) && is_vlan_dev(upper_dev)) {
4797 			struct net_device *br_dev = netdev_master_upper_dev_get(lower_dev);
4798 
4799 			if (br_vlan_enabled(br_dev)) {
4800 				br_vlan_get_proto(br_dev, &proto);
4801 				if (proto == ETH_P_8021AD) {
4802 					NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are not supported on a port enslaved to an 802.1ad bridge");
4803 					return -EOPNOTSUPP;
4804 				}
4805 			}
4806 		}
4807 		if (is_vlan_dev(upper_dev) &&
4808 		    ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) {
4809 			NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol");
4810 			return -EOPNOTSUPP;
4811 		}
4812 		if (is_vlan_dev(upper_dev) && mlxsw_sp_port->security) {
4813 			NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are not supported on a locked port");
4814 			return -EOPNOTSUPP;
4815 		}
4816 		break;
4817 	case NETDEV_CHANGEUPPER:
4818 		upper_dev = info->upper_dev;
4819 		if (netif_is_bridge_master(upper_dev)) {
4820 			if (info->linking) {
4821 				err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4822 								lower_dev,
4823 								upper_dev,
4824 								extack);
4825 			} else {
4826 				mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4827 							   lower_dev,
4828 							   upper_dev);
4829 				if (!replay_deslavement)
4830 					break;
4831 				mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp,
4832 								      lower_dev);
4833 			}
4834 		} else if (netif_is_lag_master(upper_dev)) {
4835 			if (info->linking) {
4836 				err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4837 							     upper_dev, extack);
4838 			} else {
4839 				mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
4840 				mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4841 							upper_dev);
4842 				mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp,
4843 								      dev);
4844 			}
4845 		} else if (netif_is_ovs_master(upper_dev)) {
4846 			if (info->linking)
4847 				err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4848 			else
4849 				mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
4850 		} else if (netif_is_macvlan(upper_dev)) {
4851 			if (!info->linking)
4852 				mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
4853 		} else if (is_vlan_dev(upper_dev)) {
4854 			struct net_device *br_dev;
4855 
4856 			if (!netif_is_bridge_port(upper_dev))
4857 				break;
4858 			if (info->linking)
4859 				break;
4860 			br_dev = netdev_master_upper_dev_get(upper_dev);
4861 			mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev,
4862 						   br_dev);
4863 		}
4864 		break;
4865 	}
4866 
4867 	return err;
4868 }
4869 
mlxsw_sp_netdevice_port_lower_event(struct net_device * dev,unsigned long event,void * ptr)4870 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4871 					       unsigned long event, void *ptr)
4872 {
4873 	struct netdev_notifier_changelowerstate_info *info;
4874 	struct mlxsw_sp_port *mlxsw_sp_port;
4875 	int err;
4876 
4877 	mlxsw_sp_port = netdev_priv(dev);
4878 	info = ptr;
4879 
4880 	switch (event) {
4881 	case NETDEV_CHANGELOWERSTATE:
4882 		if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4883 			err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4884 							info->lower_state_info);
4885 			if (err)
4886 				netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4887 		}
4888 		break;
4889 	}
4890 
4891 	return 0;
4892 }
4893 
mlxsw_sp_netdevice_port_event(struct net_device * lower_dev,struct net_device * port_dev,unsigned long event,void * ptr,bool replay_deslavement)4894 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4895 					 struct net_device *port_dev,
4896 					 unsigned long event, void *ptr,
4897 					 bool replay_deslavement)
4898 {
4899 	switch (event) {
4900 	case NETDEV_PRECHANGEUPPER:
4901 	case NETDEV_CHANGEUPPER:
4902 		return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4903 							   event, ptr,
4904 							   replay_deslavement);
4905 	case NETDEV_CHANGELOWERSTATE:
4906 		return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4907 							   ptr);
4908 	}
4909 
4910 	return 0;
4911 }
4912 
4913 /* Called for LAG or its upper VLAN after the per-LAG-lower processing was done,
4914  * to do any per-LAG / per-LAG-upper processing.
4915  */
mlxsw_sp_netdevice_post_lag_event(struct net_device * dev,unsigned long event,void * ptr)4916 static int mlxsw_sp_netdevice_post_lag_event(struct net_device *dev,
4917 					     unsigned long event,
4918 					     void *ptr)
4919 {
4920 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(dev);
4921 	struct netdev_notifier_changeupper_info *info = ptr;
4922 
4923 	if (!mlxsw_sp)
4924 		return 0;
4925 
4926 	switch (event) {
4927 	case NETDEV_CHANGEUPPER:
4928 		if (info->linking)
4929 			break;
4930 		if (netif_is_bridge_master(info->upper_dev))
4931 			mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp, dev);
4932 		break;
4933 	}
4934 	return 0;
4935 }
4936 
mlxsw_sp_netdevice_lag_event(struct net_device * lag_dev,unsigned long event,void * ptr)4937 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4938 					unsigned long event, void *ptr)
4939 {
4940 	struct net_device *dev;
4941 	struct list_head *iter;
4942 	int ret;
4943 
4944 	netdev_for_each_lower_dev(lag_dev, dev, iter) {
4945 		if (mlxsw_sp_port_dev_check(dev)) {
4946 			ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4947 							    ptr, false);
4948 			if (ret)
4949 				return ret;
4950 		}
4951 	}
4952 
4953 	return mlxsw_sp_netdevice_post_lag_event(lag_dev, event, ptr);
4954 }
4955 
mlxsw_sp_netdevice_port_vlan_event(struct net_device * vlan_dev,struct net_device * dev,unsigned long event,void * ptr,u16 vid,bool replay_deslavement)4956 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4957 					      struct net_device *dev,
4958 					      unsigned long event, void *ptr,
4959 					      u16 vid, bool replay_deslavement)
4960 {
4961 	struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4962 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4963 	struct netdev_notifier_changeupper_info *info = ptr;
4964 	struct netlink_ext_ack *extack;
4965 	struct net_device *upper_dev;
4966 	int err = 0;
4967 
4968 	extack = netdev_notifier_info_to_extack(&info->info);
4969 
4970 	switch (event) {
4971 	case NETDEV_PRECHANGEUPPER:
4972 		upper_dev = info->upper_dev;
4973 		if (!netif_is_bridge_master(upper_dev) &&
4974 		    !netif_is_macvlan(upper_dev) &&
4975 		    !netif_is_l3_master(upper_dev)) {
4976 			NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
4977 			return -EINVAL;
4978 		}
4979 		if (!info->linking)
4980 			break;
4981 		if (netif_is_bridge_master(upper_dev) &&
4982 		    !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
4983 		    mlxsw_sp_bridge_has_vxlan(upper_dev) &&
4984 		    !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
4985 			return -EOPNOTSUPP;
4986 		if (netdev_has_any_upper_dev(upper_dev) &&
4987 		    (!netif_is_bridge_master(upper_dev) ||
4988 		     !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4989 							  upper_dev))) {
4990 			err = mlxsw_sp_netdevice_validate_uppers(mlxsw_sp,
4991 								 upper_dev,
4992 								 extack);
4993 			if (err)
4994 				return err;
4995 		}
4996 		break;
4997 	case NETDEV_CHANGEUPPER:
4998 		upper_dev = info->upper_dev;
4999 		if (netif_is_bridge_master(upper_dev)) {
5000 			if (info->linking) {
5001 				err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
5002 								vlan_dev,
5003 								upper_dev,
5004 								extack);
5005 			} else {
5006 				mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
5007 							   vlan_dev,
5008 							   upper_dev);
5009 				if (!replay_deslavement)
5010 					break;
5011 				mlxsw_sp_netdevice_deslavement_replay(mlxsw_sp,
5012 								      vlan_dev);
5013 			}
5014 		} else if (netif_is_macvlan(upper_dev)) {
5015 			if (!info->linking)
5016 				mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
5017 		}
5018 		break;
5019 	}
5020 
5021 	return err;
5022 }
5023 
mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device * vlan_dev,struct net_device * lag_dev,unsigned long event,void * ptr,u16 vid)5024 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
5025 						  struct net_device *lag_dev,
5026 						  unsigned long event,
5027 						  void *ptr, u16 vid)
5028 {
5029 	struct net_device *dev;
5030 	struct list_head *iter;
5031 	int ret;
5032 
5033 	netdev_for_each_lower_dev(lag_dev, dev, iter) {
5034 		if (mlxsw_sp_port_dev_check(dev)) {
5035 			ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
5036 								 event, ptr,
5037 								 vid, false);
5038 			if (ret)
5039 				return ret;
5040 		}
5041 	}
5042 
5043 	return mlxsw_sp_netdevice_post_lag_event(vlan_dev, event, ptr);
5044 }
5045 
mlxsw_sp_netdevice_bridge_vlan_event(struct mlxsw_sp * mlxsw_sp,struct net_device * vlan_dev,struct net_device * br_dev,unsigned long event,void * ptr,u16 vid,bool process_foreign)5046 static int mlxsw_sp_netdevice_bridge_vlan_event(struct mlxsw_sp *mlxsw_sp,
5047 						struct net_device *vlan_dev,
5048 						struct net_device *br_dev,
5049 						unsigned long event, void *ptr,
5050 						u16 vid, bool process_foreign)
5051 {
5052 	struct netdev_notifier_changeupper_info *info = ptr;
5053 	struct netlink_ext_ack *extack;
5054 	struct net_device *upper_dev;
5055 
5056 	if (!process_foreign && !mlxsw_sp_lower_get(vlan_dev))
5057 		return 0;
5058 
5059 	extack = netdev_notifier_info_to_extack(&info->info);
5060 
5061 	switch (event) {
5062 	case NETDEV_PRECHANGEUPPER:
5063 		upper_dev = info->upper_dev;
5064 		if (!netif_is_macvlan(upper_dev) &&
5065 		    !netif_is_l3_master(upper_dev)) {
5066 			NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
5067 			return -EOPNOTSUPP;
5068 		}
5069 		break;
5070 	case NETDEV_CHANGEUPPER:
5071 		upper_dev = info->upper_dev;
5072 		if (info->linking)
5073 			break;
5074 		if (netif_is_macvlan(upper_dev))
5075 			mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
5076 		break;
5077 	}
5078 
5079 	return 0;
5080 }
5081 
mlxsw_sp_netdevice_vlan_event(struct mlxsw_sp * mlxsw_sp,struct net_device * vlan_dev,unsigned long event,void * ptr,bool process_foreign)5082 static int mlxsw_sp_netdevice_vlan_event(struct mlxsw_sp *mlxsw_sp,
5083 					 struct net_device *vlan_dev,
5084 					 unsigned long event, void *ptr,
5085 					 bool process_foreign)
5086 {
5087 	struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
5088 	u16 vid = vlan_dev_vlan_id(vlan_dev);
5089 
5090 	if (mlxsw_sp_port_dev_check(real_dev))
5091 		return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
5092 							  event, ptr, vid,
5093 							  true);
5094 	else if (netif_is_lag_master(real_dev))
5095 		return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
5096 							      real_dev, event,
5097 							      ptr, vid);
5098 	else if (netif_is_bridge_master(real_dev))
5099 		return mlxsw_sp_netdevice_bridge_vlan_event(mlxsw_sp, vlan_dev,
5100 							    real_dev, event,
5101 							    ptr, vid,
5102 							    process_foreign);
5103 
5104 	return 0;
5105 }
5106 
mlxsw_sp_netdevice_bridge_event(struct mlxsw_sp * mlxsw_sp,struct net_device * br_dev,unsigned long event,void * ptr,bool process_foreign)5107 static int mlxsw_sp_netdevice_bridge_event(struct mlxsw_sp *mlxsw_sp,
5108 					   struct net_device *br_dev,
5109 					   unsigned long event, void *ptr,
5110 					   bool process_foreign)
5111 {
5112 	struct netdev_notifier_changeupper_info *info = ptr;
5113 	struct netlink_ext_ack *extack;
5114 	struct net_device *upper_dev;
5115 	u16 proto;
5116 
5117 	if (!process_foreign && !mlxsw_sp_lower_get(br_dev))
5118 		return 0;
5119 
5120 	extack = netdev_notifier_info_to_extack(&info->info);
5121 
5122 	switch (event) {
5123 	case NETDEV_PRECHANGEUPPER:
5124 		upper_dev = info->upper_dev;
5125 		if (!is_vlan_dev(upper_dev) &&
5126 		    !netif_is_macvlan(upper_dev) &&
5127 		    !netif_is_l3_master(upper_dev)) {
5128 			NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
5129 			return -EOPNOTSUPP;
5130 		}
5131 		if (!info->linking)
5132 			break;
5133 		if (br_vlan_enabled(br_dev)) {
5134 			br_vlan_get_proto(br_dev, &proto);
5135 			if (proto == ETH_P_8021AD) {
5136 				NL_SET_ERR_MSG_MOD(extack, "Upper devices are not supported on top of an 802.1ad bridge");
5137 				return -EOPNOTSUPP;
5138 			}
5139 		}
5140 		if (is_vlan_dev(upper_dev) &&
5141 		    ntohs(vlan_dev_vlan_proto(upper_dev)) != ETH_P_8021Q) {
5142 			NL_SET_ERR_MSG_MOD(extack, "VLAN uppers are only supported with 802.1q VLAN protocol");
5143 			return -EOPNOTSUPP;
5144 		}
5145 		break;
5146 	case NETDEV_CHANGEUPPER:
5147 		upper_dev = info->upper_dev;
5148 		if (info->linking)
5149 			break;
5150 		if (is_vlan_dev(upper_dev))
5151 			mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
5152 		if (netif_is_macvlan(upper_dev))
5153 			mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
5154 		break;
5155 	}
5156 
5157 	return 0;
5158 }
5159 
mlxsw_sp_netdevice_macvlan_event(struct net_device * macvlan_dev,unsigned long event,void * ptr)5160 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
5161 					    unsigned long event, void *ptr)
5162 {
5163 	struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
5164 	struct netdev_notifier_changeupper_info *info = ptr;
5165 	struct netlink_ext_ack *extack;
5166 	struct net_device *upper_dev;
5167 
5168 	if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
5169 		return 0;
5170 
5171 	extack = netdev_notifier_info_to_extack(&info->info);
5172 	upper_dev = info->upper_dev;
5173 
5174 	if (!netif_is_l3_master(upper_dev)) {
5175 		NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
5176 		return -EOPNOTSUPP;
5177 	}
5178 
5179 	return 0;
5180 }
5181 
mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp * mlxsw_sp,struct net_device * dev,unsigned long event,void * ptr)5182 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp,
5183 					  struct net_device *dev,
5184 					  unsigned long event, void *ptr)
5185 {
5186 	struct netdev_notifier_changeupper_info *cu_info;
5187 	struct netdev_notifier_info *info = ptr;
5188 	struct netlink_ext_ack *extack;
5189 	struct net_device *upper_dev;
5190 
5191 	extack = netdev_notifier_info_to_extack(info);
5192 
5193 	switch (event) {
5194 	case NETDEV_CHANGEUPPER:
5195 		cu_info = container_of(info,
5196 				       struct netdev_notifier_changeupper_info,
5197 				       info);
5198 		upper_dev = cu_info->upper_dev;
5199 		if (!netif_is_bridge_master(upper_dev))
5200 			return 0;
5201 		if (!mlxsw_sp_lower_get(upper_dev))
5202 			return 0;
5203 		if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
5204 			return -EOPNOTSUPP;
5205 		if (!netif_running(dev))
5206 			return 0;
5207 		if (cu_info->linking)
5208 			return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev,
5209 							  dev, 0, extack);
5210 		else
5211 			mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
5212 		break;
5213 	case NETDEV_PRE_UP:
5214 		upper_dev = netdev_master_upper_dev_get(dev);
5215 		if (!upper_dev)
5216 			return 0;
5217 		if (!netif_is_bridge_master(upper_dev))
5218 			return 0;
5219 		if (!mlxsw_sp_lower_get(upper_dev))
5220 			return 0;
5221 		return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0,
5222 						  extack);
5223 	case NETDEV_DOWN:
5224 		upper_dev = netdev_master_upper_dev_get(dev);
5225 		if (!upper_dev)
5226 			return 0;
5227 		if (!netif_is_bridge_master(upper_dev))
5228 			return 0;
5229 		if (!mlxsw_sp_lower_get(upper_dev))
5230 			return 0;
5231 		mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
5232 		break;
5233 	}
5234 
5235 	return 0;
5236 }
5237 
__mlxsw_sp_netdevice_event(struct mlxsw_sp * mlxsw_sp,unsigned long event,void * ptr,bool process_foreign)5238 static int __mlxsw_sp_netdevice_event(struct mlxsw_sp *mlxsw_sp,
5239 				      unsigned long event, void *ptr,
5240 				      bool process_foreign)
5241 {
5242 	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
5243 	struct mlxsw_sp_span_entry *span_entry;
5244 	int err = 0;
5245 
5246 	if (event == NETDEV_UNREGISTER) {
5247 		span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
5248 		if (span_entry)
5249 			mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
5250 	}
5251 
5252 	if (netif_is_vxlan(dev))
5253 		err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr);
5254 	else if (mlxsw_sp_port_dev_check(dev))
5255 		err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr, true);
5256 	else if (netif_is_lag_master(dev))
5257 		err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
5258 	else if (is_vlan_dev(dev))
5259 		err = mlxsw_sp_netdevice_vlan_event(mlxsw_sp, dev, event, ptr,
5260 						    process_foreign);
5261 	else if (netif_is_bridge_master(dev))
5262 		err = mlxsw_sp_netdevice_bridge_event(mlxsw_sp, dev, event, ptr,
5263 						      process_foreign);
5264 	else if (netif_is_macvlan(dev))
5265 		err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
5266 
5267 	return err;
5268 }
5269 
mlxsw_sp_netdevice_event(struct notifier_block * nb,unsigned long event,void * ptr)5270 static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
5271 				    unsigned long event, void *ptr)
5272 {
5273 	struct mlxsw_sp *mlxsw_sp;
5274 	int err;
5275 
5276 	mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
5277 	mlxsw_sp_span_respin(mlxsw_sp);
5278 	err = __mlxsw_sp_netdevice_event(mlxsw_sp, event, ptr, false);
5279 
5280 	return notifier_from_errno(err);
5281 }
5282 
5283 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
5284 	{PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM) },
5285 	{ },
5286 };
5287 
5288 static struct pci_driver mlxsw_sp1_pci_driver = {
5289 	.name = mlxsw_sp1_driver_name,
5290 	.id_table = mlxsw_sp1_pci_id_table,
5291 };
5292 
5293 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
5294 	{PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2) },
5295 	{ },
5296 };
5297 
5298 static struct pci_driver mlxsw_sp2_pci_driver = {
5299 	.name = mlxsw_sp2_driver_name,
5300 	.id_table = mlxsw_sp2_pci_id_table,
5301 };
5302 
5303 static const struct pci_device_id mlxsw_sp3_pci_id_table[] = {
5304 	{PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM3) },
5305 	{ },
5306 };
5307 
5308 static struct pci_driver mlxsw_sp3_pci_driver = {
5309 	.name = mlxsw_sp3_driver_name,
5310 	.id_table = mlxsw_sp3_pci_id_table,
5311 };
5312 
5313 static const struct pci_device_id mlxsw_sp4_pci_id_table[] = {
5314 	{PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM4) },
5315 	{ },
5316 };
5317 
5318 static struct pci_driver mlxsw_sp4_pci_driver = {
5319 	.name = mlxsw_sp4_driver_name,
5320 	.id_table = mlxsw_sp4_pci_id_table,
5321 };
5322 
mlxsw_sp_module_init(void)5323 static int __init mlxsw_sp_module_init(void)
5324 {
5325 	int err;
5326 
5327 	err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
5328 	if (err)
5329 		return err;
5330 
5331 	err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
5332 	if (err)
5333 		goto err_sp2_core_driver_register;
5334 
5335 	err = mlxsw_core_driver_register(&mlxsw_sp3_driver);
5336 	if (err)
5337 		goto err_sp3_core_driver_register;
5338 
5339 	err = mlxsw_core_driver_register(&mlxsw_sp4_driver);
5340 	if (err)
5341 		goto err_sp4_core_driver_register;
5342 
5343 	err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
5344 	if (err)
5345 		goto err_sp1_pci_driver_register;
5346 
5347 	err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
5348 	if (err)
5349 		goto err_sp2_pci_driver_register;
5350 
5351 	err = mlxsw_pci_driver_register(&mlxsw_sp3_pci_driver);
5352 	if (err)
5353 		goto err_sp3_pci_driver_register;
5354 
5355 	err = mlxsw_pci_driver_register(&mlxsw_sp4_pci_driver);
5356 	if (err)
5357 		goto err_sp4_pci_driver_register;
5358 
5359 	return 0;
5360 
5361 err_sp4_pci_driver_register:
5362 	mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver);
5363 err_sp3_pci_driver_register:
5364 	mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
5365 err_sp2_pci_driver_register:
5366 	mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
5367 err_sp1_pci_driver_register:
5368 	mlxsw_core_driver_unregister(&mlxsw_sp4_driver);
5369 err_sp4_core_driver_register:
5370 	mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
5371 err_sp3_core_driver_register:
5372 	mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
5373 err_sp2_core_driver_register:
5374 	mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
5375 	return err;
5376 }
5377 
mlxsw_sp_module_exit(void)5378 static void __exit mlxsw_sp_module_exit(void)
5379 {
5380 	mlxsw_pci_driver_unregister(&mlxsw_sp4_pci_driver);
5381 	mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver);
5382 	mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
5383 	mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
5384 	mlxsw_core_driver_unregister(&mlxsw_sp4_driver);
5385 	mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
5386 	mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
5387 	mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
5388 }
5389 
5390 module_init(mlxsw_sp_module_init);
5391 module_exit(mlxsw_sp_module_exit);
5392 
5393 MODULE_LICENSE("Dual BSD/GPL");
5394 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
5395 MODULE_DESCRIPTION("Mellanox Spectrum driver");
5396 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
5397 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
5398 MODULE_DEVICE_TABLE(pci, mlxsw_sp3_pci_id_table);
5399 MODULE_DEVICE_TABLE(pci, mlxsw_sp4_pci_id_table);
5400 MODULE_FIRMWARE(MLXSW_SP1_FW_FILENAME);
5401 MODULE_FIRMWARE(MLXSW_SP2_FW_FILENAME);
5402 MODULE_FIRMWARE(MLXSW_SP3_FW_FILENAME);
5403 MODULE_FIRMWARE(MLXSW_SP_LINECARDS_INI_BUNDLE_FILENAME);
5404