1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "pp_debug.h" 24 #include <linux/types.h> 25 #include <linux/kernel.h> 26 #include <linux/slab.h> 27 #include "atom-types.h" 28 #include "atombios.h" 29 #include "processpptables.h" 30 #include "cgs_common.h" 31 #include "smumgr.h" 32 #include "hwmgr.h" 33 #include "hardwaremanager.h" 34 #include "rv_ppsmc.h" 35 #include "smu10_hwmgr.h" 36 #include "power_state.h" 37 #include "soc15_common.h" 38 #include "smu10.h" 39 #include "asic_reg/pwr/pwr_10_0_offset.h" 40 #include "asic_reg/pwr/pwr_10_0_sh_mask.h" 41 42 #define SMU10_MAX_DEEPSLEEP_DIVIDER_ID 5 43 #define SMU10_MINIMUM_ENGINE_CLOCK 800 /* 8Mhz, the low boundary of engine clock allowed on this chip */ 44 #define SCLK_MIN_DIV_INTV_SHIFT 12 45 #define SMU10_DISPCLK_BYPASS_THRESHOLD 10000 /* 100Mhz */ 46 #define SMC_RAM_END 0x40000 47 48 static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic; 49 50 51 static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr, 52 struct pp_display_clock_request *clock_req) 53 { 54 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 55 enum amd_pp_clock_type clk_type = clock_req->clock_type; 56 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; 57 PPSMC_Msg msg; 58 59 switch (clk_type) { 60 case amd_pp_dcf_clock: 61 if (clk_freq == smu10_data->dcf_actual_hard_min_freq) 62 return 0; 63 msg = PPSMC_MSG_SetHardMinDcefclkByFreq; 64 smu10_data->dcf_actual_hard_min_freq = clk_freq; 65 break; 66 case amd_pp_soc_clock: 67 msg = PPSMC_MSG_SetHardMinSocclkByFreq; 68 break; 69 case amd_pp_f_clock: 70 if (clk_freq == smu10_data->f_actual_hard_min_freq) 71 return 0; 72 smu10_data->f_actual_hard_min_freq = clk_freq; 73 msg = PPSMC_MSG_SetHardMinFclkByFreq; 74 break; 75 default: 76 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!"); 77 return -EINVAL; 78 } 79 smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq, NULL); 80 81 return 0; 82 } 83 84 static struct smu10_power_state *cast_smu10_ps(struct pp_hw_power_state *hw_ps) 85 { 86 if (SMU10_Magic != hw_ps->magic) 87 return NULL; 88 89 return (struct smu10_power_state *)hw_ps; 90 } 91 92 static const struct smu10_power_state *cast_const_smu10_ps( 93 const struct pp_hw_power_state *hw_ps) 94 { 95 if (SMU10_Magic != hw_ps->magic) 96 return NULL; 97 98 return (struct smu10_power_state *)hw_ps; 99 } 100 101 static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr) 102 { 103 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 104 105 smu10_data->dce_slow_sclk_threshold = 30000; 106 smu10_data->thermal_auto_throttling_treshold = 0; 107 smu10_data->is_nb_dpm_enabled = 1; 108 smu10_data->dpm_flags = 1; 109 smu10_data->need_min_deep_sleep_dcefclk = true; 110 smu10_data->num_active_display = 0; 111 smu10_data->deep_sleep_dcefclk = 0; 112 113 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 114 PHM_PlatformCaps_SclkDeepSleep); 115 116 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 117 PHM_PlatformCaps_SclkThrottleLowNotification); 118 119 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 120 PHM_PlatformCaps_PowerPlaySupport); 121 return 0; 122 } 123 124 static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr, 125 struct phm_clock_and_voltage_limits *table) 126 { 127 return 0; 128 } 129 130 static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr) 131 { 132 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend; 133 134 smu10_data->sys_info.htc_hyst_lmt = 5; 135 smu10_data->sys_info.htc_tmp_lmt = 203; 136 137 if (smu10_data->thermal_auto_throttling_treshold == 0) 138 smu10_data->thermal_auto_throttling_treshold = 203; 139 140 smu10_construct_max_power_limits_table (hwmgr, 141 &hwmgr->dyn_state.max_clock_voltage_on_ac); 142 143 return 0; 144 } 145 146 static int smu10_construct_boot_state(struct pp_hwmgr *hwmgr) 147 { 148 return 0; 149 } 150 151 static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input) 152 { 153 struct PP_Clocks clocks = {0}; 154 struct pp_display_clock_request clock_req; 155 156 clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; 157 clock_req.clock_type = amd_pp_dcf_clock; 158 clock_req.clock_freq_in_khz = clocks.dcefClock * 10; 159 160 PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req), 161 "Attempt to set DCF Clock Failed!", return -EINVAL); 162 163 return 0; 164 } 165 166 static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock) 167 { 168 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 169 170 if (clock && smu10_data->deep_sleep_dcefclk != clock) { 171 smu10_data->deep_sleep_dcefclk = clock; 172 smum_send_msg_to_smc_with_parameter(hwmgr, 173 PPSMC_MSG_SetMinDeepSleepDcefclk, 174 smu10_data->deep_sleep_dcefclk, 175 NULL); 176 } 177 return 0; 178 } 179 180 static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) 181 { 182 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 183 184 if (clock && smu10_data->dcf_actual_hard_min_freq != clock) { 185 smu10_data->dcf_actual_hard_min_freq = clock; 186 smum_send_msg_to_smc_with_parameter(hwmgr, 187 PPSMC_MSG_SetHardMinDcefclkByFreq, 188 smu10_data->dcf_actual_hard_min_freq, 189 NULL); 190 } 191 return 0; 192 } 193 194 static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) 195 { 196 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 197 198 if (clock && smu10_data->f_actual_hard_min_freq != clock) { 199 smu10_data->f_actual_hard_min_freq = clock; 200 smum_send_msg_to_smc_with_parameter(hwmgr, 201 PPSMC_MSG_SetHardMinFclkByFreq, 202 smu10_data->f_actual_hard_min_freq, 203 NULL); 204 } 205 return 0; 206 } 207 208 static int smu10_set_hard_min_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) 209 { 210 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 211 212 if (clock && smu10_data->gfx_actual_soft_min_freq != clock) { 213 smu10_data->gfx_actual_soft_min_freq = clock; 214 smum_send_msg_to_smc_with_parameter(hwmgr, 215 PPSMC_MSG_SetHardMinGfxClk, 216 clock, 217 NULL); 218 } 219 return 0; 220 } 221 222 static int smu10_set_soft_max_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock) 223 { 224 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 225 226 if (clock && smu10_data->gfx_max_freq_limit != (clock * 100)) { 227 smu10_data->gfx_max_freq_limit = clock * 100; 228 smum_send_msg_to_smc_with_parameter(hwmgr, 229 PPSMC_MSG_SetSoftMaxGfxClk, 230 clock, 231 NULL); 232 } 233 return 0; 234 } 235 236 static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count) 237 { 238 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 239 240 if (smu10_data->num_active_display != count) { 241 smu10_data->num_active_display = count; 242 smum_send_msg_to_smc_with_parameter(hwmgr, 243 PPSMC_MSG_SetDisplayCount, 244 smu10_data->num_active_display, 245 NULL); 246 } 247 248 return 0; 249 } 250 251 static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) 252 { 253 return smu10_set_clock_limit(hwmgr, input); 254 } 255 256 static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr) 257 { 258 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 259 struct amdgpu_device *adev = hwmgr->adev; 260 261 smu10_data->vcn_power_gated = true; 262 smu10_data->isp_tileA_power_gated = true; 263 smu10_data->isp_tileB_power_gated = true; 264 265 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) 266 return smum_send_msg_to_smc_with_parameter(hwmgr, 267 PPSMC_MSG_SetGfxCGPG, 268 true, 269 NULL); 270 else 271 return 0; 272 } 273 274 275 static int smu10_setup_asic_task(struct pp_hwmgr *hwmgr) 276 { 277 return smu10_init_power_gate_state(hwmgr); 278 } 279 280 static int smu10_reset_cc6_data(struct pp_hwmgr *hwmgr) 281 { 282 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 283 284 smu10_data->separation_time = 0; 285 smu10_data->cc6_disable = false; 286 smu10_data->pstate_disable = false; 287 smu10_data->cc6_setting_changed = false; 288 289 return 0; 290 } 291 292 static int smu10_power_off_asic(struct pp_hwmgr *hwmgr) 293 { 294 return smu10_reset_cc6_data(hwmgr); 295 } 296 297 static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr) 298 { 299 uint32_t reg; 300 struct amdgpu_device *adev = hwmgr->adev; 301 302 reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS); 303 if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) == 304 (0x2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT)) 305 return true; 306 307 return false; 308 } 309 310 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr) 311 { 312 struct amdgpu_device *adev = hwmgr->adev; 313 314 if (adev->pm.pp_feature & PP_GFXOFF_MASK) { 315 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff, NULL); 316 317 /* confirm gfx is back to "on" state */ 318 while (!smu10_is_gfx_on(hwmgr)) 319 msleep(1); 320 } 321 322 return 0; 323 } 324 325 static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) 326 { 327 return 0; 328 } 329 330 static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr) 331 { 332 struct amdgpu_device *adev = hwmgr->adev; 333 334 if (adev->pm.pp_feature & PP_GFXOFF_MASK) 335 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff, NULL); 336 337 return 0; 338 } 339 340 static void smu10_populate_umdpstate_clocks(struct pp_hwmgr *hwmgr) 341 { 342 hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK; 343 hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK; 344 345 smum_send_msg_to_smc(hwmgr, 346 PPSMC_MSG_GetMaxGfxclkFrequency, 347 &hwmgr->pstate_sclk_peak); 348 hwmgr->pstate_mclk_peak = SMU10_UMD_PSTATE_PEAK_FCLK; 349 } 350 351 static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 352 { 353 struct amdgpu_device *adev = hwmgr->adev; 354 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 355 int ret = -EINVAL; 356 357 if (adev->in_suspend) { 358 pr_info("restore the fine grain parameters\n"); 359 360 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 361 PPSMC_MSG_SetHardMinGfxClk, 362 smu10_data->gfx_actual_soft_min_freq, 363 NULL); 364 if (ret) 365 return ret; 366 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 367 PPSMC_MSG_SetSoftMaxGfxClk, 368 smu10_data->gfx_actual_soft_max_freq, 369 NULL); 370 if (ret) 371 return ret; 372 } 373 374 smu10_populate_umdpstate_clocks(hwmgr); 375 376 return 0; 377 } 378 379 static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable) 380 { 381 if (enable) 382 return smu10_enable_gfx_off(hwmgr); 383 else 384 return smu10_disable_gfx_off(hwmgr); 385 } 386 387 static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 388 struct pp_power_state *prequest_ps, 389 const struct pp_power_state *pcurrent_ps) 390 { 391 return 0; 392 } 393 394 /* temporary hardcoded clock voltage breakdown tables */ 395 static const DpmClock_t VddDcfClk[] = { 396 { 300, 2600}, 397 { 600, 3200}, 398 { 600, 3600}, 399 }; 400 401 static const DpmClock_t VddSocClk[] = { 402 { 478, 2600}, 403 { 722, 3200}, 404 { 722, 3600}, 405 }; 406 407 static const DpmClock_t VddFClk[] = { 408 { 400, 2600}, 409 {1200, 3200}, 410 {1200, 3600}, 411 }; 412 413 static const DpmClock_t VddDispClk[] = { 414 { 435, 2600}, 415 { 661, 3200}, 416 {1086, 3600}, 417 }; 418 419 static const DpmClock_t VddDppClk[] = { 420 { 435, 2600}, 421 { 661, 3200}, 422 { 661, 3600}, 423 }; 424 425 static const DpmClock_t VddPhyClk[] = { 426 { 540, 2600}, 427 { 810, 3200}, 428 { 810, 3600}, 429 }; 430 431 static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr, 432 struct smu10_voltage_dependency_table **pptable, 433 uint32_t num_entry, const DpmClock_t *pclk_dependency_table) 434 { 435 uint32_t i; 436 struct smu10_voltage_dependency_table *ptable; 437 438 ptable = kzalloc_flex(*ptable, entries, num_entry); 439 if (NULL == ptable) 440 return -ENOMEM; 441 442 ptable->count = num_entry; 443 444 for (i = 0; i < ptable->count; i++) { 445 ptable->entries[i].clk = pclk_dependency_table->Freq * 100; 446 ptable->entries[i].vol = pclk_dependency_table->Vol; 447 pclk_dependency_table++; 448 } 449 450 *pptable = ptable; 451 452 return 0; 453 } 454 455 456 static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr) 457 { 458 uint32_t result; 459 460 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 461 DpmClocks_t *table = &(smu10_data->clock_table); 462 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info); 463 464 result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true); 465 466 PP_ASSERT_WITH_CODE((0 == result), 467 "Attempt to copy clock table from smc failed", 468 return result); 469 470 if (0 == result && table->DcefClocks[0].Freq != 0) { 471 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk, 472 NUM_DCEFCLK_DPM_LEVELS, 473 &smu10_data->clock_table.DcefClocks[0]); 474 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk, 475 NUM_SOCCLK_DPM_LEVELS, 476 &smu10_data->clock_table.SocClocks[0]); 477 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk, 478 NUM_FCLK_DPM_LEVELS, 479 &smu10_data->clock_table.FClocks[0]); 480 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk, 481 NUM_MEMCLK_DPM_LEVELS, 482 &smu10_data->clock_table.MemClocks[0]); 483 } else { 484 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk, 485 ARRAY_SIZE(VddDcfClk), 486 &VddDcfClk[0]); 487 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk, 488 ARRAY_SIZE(VddSocClk), 489 &VddSocClk[0]); 490 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk, 491 ARRAY_SIZE(VddFClk), 492 &VddFClk[0]); 493 } 494 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk, 495 ARRAY_SIZE(VddDispClk), 496 &VddDispClk[0]); 497 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk, 498 ARRAY_SIZE(VddDppClk), &VddDppClk[0]); 499 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk, 500 ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]); 501 502 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &result); 503 smu10_data->gfx_min_freq_limit = result / 10 * 1000; 504 505 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &result); 506 smu10_data->gfx_max_freq_limit = result / 10 * 1000; 507 508 return 0; 509 } 510 511 static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 512 { 513 int result = 0; 514 struct smu10_hwmgr *data; 515 516 data = kzalloc_obj(struct smu10_hwmgr); 517 if (data == NULL) 518 return -ENOMEM; 519 520 hwmgr->backend = data; 521 522 result = smu10_initialize_dpm_defaults(hwmgr); 523 if (result != 0) { 524 pr_err("smu10_initialize_dpm_defaults failed\n"); 525 return result; 526 } 527 528 smu10_populate_clock_table(hwmgr); 529 530 result = smu10_get_system_info_data(hwmgr); 531 if (result != 0) { 532 pr_err("smu10_get_system_info_data failed\n"); 533 return result; 534 } 535 536 smu10_construct_boot_state(hwmgr); 537 538 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = 539 SMU10_MAX_HARDWARE_POWERLEVELS; 540 541 hwmgr->platform_descriptor.hardwarePerformanceLevels = 542 SMU10_MAX_HARDWARE_POWERLEVELS; 543 544 hwmgr->platform_descriptor.vbiosInterruptId = 0; 545 546 hwmgr->platform_descriptor.clockStep.engineClock = 500; 547 548 hwmgr->platform_descriptor.clockStep.memoryClock = 500; 549 550 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; 551 552 /* enable the pp_od_clk_voltage sysfs file */ 553 hwmgr->od_enabled = 1; 554 /* disabled fine grain tuning function by default */ 555 data->fine_grain_enabled = 0; 556 return result; 557 } 558 559 static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) 560 { 561 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 562 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info); 563 564 kfree(pinfo->vdd_dep_on_dcefclk); 565 pinfo->vdd_dep_on_dcefclk = NULL; 566 kfree(pinfo->vdd_dep_on_socclk); 567 pinfo->vdd_dep_on_socclk = NULL; 568 kfree(pinfo->vdd_dep_on_fclk); 569 pinfo->vdd_dep_on_fclk = NULL; 570 kfree(pinfo->vdd_dep_on_dispclk); 571 pinfo->vdd_dep_on_dispclk = NULL; 572 kfree(pinfo->vdd_dep_on_dppclk); 573 pinfo->vdd_dep_on_dppclk = NULL; 574 kfree(pinfo->vdd_dep_on_phyclk); 575 pinfo->vdd_dep_on_phyclk = NULL; 576 577 kfree(hwmgr->backend); 578 hwmgr->backend = NULL; 579 580 return 0; 581 } 582 583 static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr, 584 enum amd_dpm_forced_level level) 585 { 586 struct smu10_hwmgr *data = hwmgr->backend; 587 uint32_t min_sclk = hwmgr->display_config->min_core_set_clock; 588 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100; 589 uint32_t index_fclk = data->clock_vol_info.vdd_dep_on_fclk->count - 1; 590 uint32_t index_socclk = data->clock_vol_info.vdd_dep_on_socclk->count - 1; 591 uint32_t fine_grain_min_freq = 0, fine_grain_max_freq = 0; 592 593 if (hwmgr->smu_version < 0x1E3700) { 594 pr_info("smu firmware version too old, can not set dpm level\n"); 595 return 0; 596 } 597 598 if (min_sclk < data->gfx_min_freq_limit) 599 min_sclk = data->gfx_min_freq_limit; 600 601 min_sclk /= 100; /* transfer 10KHz to MHz */ 602 if (min_mclk < data->clock_table.FClocks[0].Freq) 603 min_mclk = data->clock_table.FClocks[0].Freq; 604 605 switch (level) { 606 case AMD_DPM_FORCED_LEVEL_HIGH: 607 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 608 data->fine_grain_enabled = 0; 609 610 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq); 611 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq); 612 613 data->gfx_actual_soft_min_freq = fine_grain_min_freq; 614 data->gfx_actual_soft_max_freq = fine_grain_max_freq; 615 616 smum_send_msg_to_smc_with_parameter(hwmgr, 617 PPSMC_MSG_SetHardMinGfxClk, 618 data->gfx_max_freq_limit/100, 619 NULL); 620 smum_send_msg_to_smc_with_parameter(hwmgr, 621 PPSMC_MSG_SetHardMinFclkByFreq, 622 SMU10_UMD_PSTATE_PEAK_FCLK, 623 NULL); 624 smum_send_msg_to_smc_with_parameter(hwmgr, 625 PPSMC_MSG_SetHardMinSocclkByFreq, 626 SMU10_UMD_PSTATE_PEAK_SOCCLK, 627 NULL); 628 smum_send_msg_to_smc_with_parameter(hwmgr, 629 PPSMC_MSG_SetHardMinVcn, 630 SMU10_UMD_PSTATE_VCE, 631 NULL); 632 633 smum_send_msg_to_smc_with_parameter(hwmgr, 634 PPSMC_MSG_SetSoftMaxGfxClk, 635 data->gfx_max_freq_limit/100, 636 NULL); 637 smum_send_msg_to_smc_with_parameter(hwmgr, 638 PPSMC_MSG_SetSoftMaxFclkByFreq, 639 SMU10_UMD_PSTATE_PEAK_FCLK, 640 NULL); 641 smum_send_msg_to_smc_with_parameter(hwmgr, 642 PPSMC_MSG_SetSoftMaxSocclkByFreq, 643 SMU10_UMD_PSTATE_PEAK_SOCCLK, 644 NULL); 645 smum_send_msg_to_smc_with_parameter(hwmgr, 646 PPSMC_MSG_SetSoftMaxVcn, 647 SMU10_UMD_PSTATE_VCE, 648 NULL); 649 break; 650 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 651 data->fine_grain_enabled = 0; 652 653 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq); 654 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq); 655 656 data->gfx_actual_soft_min_freq = fine_grain_min_freq; 657 data->gfx_actual_soft_max_freq = fine_grain_max_freq; 658 659 smum_send_msg_to_smc_with_parameter(hwmgr, 660 PPSMC_MSG_SetHardMinGfxClk, 661 min_sclk, 662 NULL); 663 smum_send_msg_to_smc_with_parameter(hwmgr, 664 PPSMC_MSG_SetSoftMaxGfxClk, 665 min_sclk, 666 NULL); 667 break; 668 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 669 data->fine_grain_enabled = 0; 670 671 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq); 672 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq); 673 674 data->gfx_actual_soft_min_freq = fine_grain_min_freq; 675 data->gfx_actual_soft_max_freq = fine_grain_max_freq; 676 677 smum_send_msg_to_smc_with_parameter(hwmgr, 678 PPSMC_MSG_SetHardMinFclkByFreq, 679 min_mclk, 680 NULL); 681 smum_send_msg_to_smc_with_parameter(hwmgr, 682 PPSMC_MSG_SetSoftMaxFclkByFreq, 683 min_mclk, 684 NULL); 685 break; 686 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 687 data->fine_grain_enabled = 0; 688 689 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq); 690 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq); 691 692 data->gfx_actual_soft_min_freq = fine_grain_min_freq; 693 data->gfx_actual_soft_max_freq = fine_grain_max_freq; 694 695 smum_send_msg_to_smc_with_parameter(hwmgr, 696 PPSMC_MSG_SetHardMinGfxClk, 697 SMU10_UMD_PSTATE_GFXCLK, 698 NULL); 699 smum_send_msg_to_smc_with_parameter(hwmgr, 700 PPSMC_MSG_SetHardMinFclkByFreq, 701 SMU10_UMD_PSTATE_FCLK, 702 NULL); 703 smum_send_msg_to_smc_with_parameter(hwmgr, 704 PPSMC_MSG_SetHardMinSocclkByFreq, 705 SMU10_UMD_PSTATE_SOCCLK, 706 NULL); 707 smum_send_msg_to_smc_with_parameter(hwmgr, 708 PPSMC_MSG_SetHardMinVcn, 709 SMU10_UMD_PSTATE_PROFILE_VCE, 710 NULL); 711 712 smum_send_msg_to_smc_with_parameter(hwmgr, 713 PPSMC_MSG_SetSoftMaxGfxClk, 714 SMU10_UMD_PSTATE_GFXCLK, 715 NULL); 716 smum_send_msg_to_smc_with_parameter(hwmgr, 717 PPSMC_MSG_SetSoftMaxFclkByFreq, 718 SMU10_UMD_PSTATE_FCLK, 719 NULL); 720 smum_send_msg_to_smc_with_parameter(hwmgr, 721 PPSMC_MSG_SetSoftMaxSocclkByFreq, 722 SMU10_UMD_PSTATE_SOCCLK, 723 NULL); 724 smum_send_msg_to_smc_with_parameter(hwmgr, 725 PPSMC_MSG_SetSoftMaxVcn, 726 SMU10_UMD_PSTATE_PROFILE_VCE, 727 NULL); 728 break; 729 case AMD_DPM_FORCED_LEVEL_AUTO: 730 data->fine_grain_enabled = 0; 731 732 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq); 733 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq); 734 735 data->gfx_actual_soft_min_freq = fine_grain_min_freq; 736 data->gfx_actual_soft_max_freq = fine_grain_max_freq; 737 738 smum_send_msg_to_smc_with_parameter(hwmgr, 739 PPSMC_MSG_SetHardMinGfxClk, 740 min_sclk, 741 NULL); 742 smum_send_msg_to_smc_with_parameter(hwmgr, 743 PPSMC_MSG_SetHardMinFclkByFreq, 744 hwmgr->display_config->num_display > 3 ? 745 (data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk / 100) : 746 min_mclk, 747 NULL); 748 749 smum_send_msg_to_smc_with_parameter(hwmgr, 750 PPSMC_MSG_SetHardMinSocclkByFreq, 751 data->clock_vol_info.vdd_dep_on_socclk->entries[0].clk / 100, 752 NULL); 753 smum_send_msg_to_smc_with_parameter(hwmgr, 754 PPSMC_MSG_SetHardMinVcn, 755 SMU10_UMD_PSTATE_MIN_VCE, 756 NULL); 757 758 smum_send_msg_to_smc_with_parameter(hwmgr, 759 PPSMC_MSG_SetSoftMaxGfxClk, 760 data->gfx_max_freq_limit/100, 761 NULL); 762 smum_send_msg_to_smc_with_parameter(hwmgr, 763 PPSMC_MSG_SetSoftMaxFclkByFreq, 764 data->clock_vol_info.vdd_dep_on_fclk->entries[index_fclk].clk / 100, 765 NULL); 766 smum_send_msg_to_smc_with_parameter(hwmgr, 767 PPSMC_MSG_SetSoftMaxSocclkByFreq, 768 data->clock_vol_info.vdd_dep_on_socclk->entries[index_socclk].clk / 100, 769 NULL); 770 smum_send_msg_to_smc_with_parameter(hwmgr, 771 PPSMC_MSG_SetSoftMaxVcn, 772 SMU10_UMD_PSTATE_VCE, 773 NULL); 774 break; 775 case AMD_DPM_FORCED_LEVEL_LOW: 776 data->fine_grain_enabled = 0; 777 778 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq); 779 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq); 780 781 data->gfx_actual_soft_min_freq = fine_grain_min_freq; 782 data->gfx_actual_soft_max_freq = fine_grain_max_freq; 783 784 smum_send_msg_to_smc_with_parameter(hwmgr, 785 PPSMC_MSG_SetHardMinGfxClk, 786 data->gfx_min_freq_limit/100, 787 NULL); 788 smum_send_msg_to_smc_with_parameter(hwmgr, 789 PPSMC_MSG_SetSoftMaxGfxClk, 790 data->gfx_min_freq_limit/100, 791 NULL); 792 smum_send_msg_to_smc_with_parameter(hwmgr, 793 PPSMC_MSG_SetHardMinFclkByFreq, 794 min_mclk, 795 NULL); 796 smum_send_msg_to_smc_with_parameter(hwmgr, 797 PPSMC_MSG_SetSoftMaxFclkByFreq, 798 min_mclk, 799 NULL); 800 break; 801 case AMD_DPM_FORCED_LEVEL_MANUAL: 802 data->fine_grain_enabled = 1; 803 break; 804 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 805 default: 806 break; 807 } 808 return 0; 809 } 810 811 static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) 812 { 813 struct smu10_hwmgr *data; 814 815 if (hwmgr == NULL) 816 return -EINVAL; 817 818 data = (struct smu10_hwmgr *)(hwmgr->backend); 819 820 if (low) 821 return data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; 822 else 823 return data->clock_vol_info.vdd_dep_on_fclk->entries[ 824 data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk; 825 } 826 827 static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) 828 { 829 struct smu10_hwmgr *data; 830 831 if (hwmgr == NULL) 832 return -EINVAL; 833 834 data = (struct smu10_hwmgr *)(hwmgr->backend); 835 836 if (low) 837 return data->gfx_min_freq_limit; 838 else 839 return data->gfx_max_freq_limit; 840 } 841 842 static int smu10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, 843 struct pp_hw_power_state *hw_ps) 844 { 845 return 0; 846 } 847 848 static int smu10_dpm_get_pp_table_entry_callback( 849 struct pp_hwmgr *hwmgr, 850 struct pp_hw_power_state *hw_ps, 851 unsigned int index, 852 const void *clock_info) 853 { 854 struct smu10_power_state *smu10_ps = cast_smu10_ps(hw_ps); 855 856 smu10_ps->levels[index].engine_clock = 0; 857 858 smu10_ps->levels[index].vddc_index = 0; 859 smu10_ps->level = index + 1; 860 861 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { 862 smu10_ps->levels[index].ds_divider_index = 5; 863 smu10_ps->levels[index].ss_divider_index = 5; 864 } 865 866 return 0; 867 } 868 869 static int smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr) 870 { 871 int result; 872 unsigned long ret = 0; 873 874 result = pp_tables_get_num_of_entries(hwmgr, &ret); 875 876 return result ? 0 : ret; 877 } 878 879 static int smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr, 880 unsigned long entry, struct pp_power_state *ps) 881 { 882 int result; 883 struct smu10_power_state *smu10_ps; 884 885 ps->hardware.magic = SMU10_Magic; 886 887 smu10_ps = cast_smu10_ps(&(ps->hardware)); 888 889 result = pp_tables_get_entry(hwmgr, entry, ps, 890 smu10_dpm_get_pp_table_entry_callback); 891 892 smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK; 893 smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK; 894 895 return result; 896 } 897 898 static int smu10_get_power_state_size(struct pp_hwmgr *hwmgr) 899 { 900 return sizeof(struct smu10_power_state); 901 } 902 903 static int smu10_set_cpu_power_state(struct pp_hwmgr *hwmgr) 904 { 905 return 0; 906 } 907 908 909 static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time, 910 bool cc6_disable, bool pstate_disable, bool pstate_switch_disable) 911 { 912 struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend); 913 914 if (separation_time != data->separation_time || 915 cc6_disable != data->cc6_disable || 916 pstate_disable != data->pstate_disable) { 917 data->separation_time = separation_time; 918 data->cc6_disable = cc6_disable; 919 data->pstate_disable = pstate_disable; 920 data->cc6_setting_changed = true; 921 } 922 return 0; 923 } 924 925 static int smu10_force_clock_level(struct pp_hwmgr *hwmgr, 926 enum pp_clock_type type, uint32_t mask) 927 { 928 struct smu10_hwmgr *data = hwmgr->backend; 929 struct smu10_voltage_dependency_table *mclk_table = 930 data->clock_vol_info.vdd_dep_on_fclk; 931 uint32_t low, high; 932 933 low = mask ? (ffs(mask) - 1) : 0; 934 high = mask ? (fls(mask) - 1) : 0; 935 936 switch (type) { 937 case PP_SCLK: 938 if (low > 2 || high > 2) { 939 pr_info("Currently sclk only support 3 levels on RV\n"); 940 return -EINVAL; 941 } 942 943 smum_send_msg_to_smc_with_parameter(hwmgr, 944 PPSMC_MSG_SetHardMinGfxClk, 945 low == 2 ? data->gfx_max_freq_limit/100 : 946 low == 1 ? SMU10_UMD_PSTATE_GFXCLK : 947 data->gfx_min_freq_limit/100, 948 NULL); 949 950 smum_send_msg_to_smc_with_parameter(hwmgr, 951 PPSMC_MSG_SetSoftMaxGfxClk, 952 high == 0 ? data->gfx_min_freq_limit/100 : 953 high == 1 ? SMU10_UMD_PSTATE_GFXCLK : 954 data->gfx_max_freq_limit/100, 955 NULL); 956 break; 957 958 case PP_MCLK: 959 if (low > mclk_table->count - 1 || high > mclk_table->count - 1) 960 return -EINVAL; 961 962 smum_send_msg_to_smc_with_parameter(hwmgr, 963 PPSMC_MSG_SetHardMinFclkByFreq, 964 mclk_table->entries[low].clk/100, 965 NULL); 966 967 smum_send_msg_to_smc_with_parameter(hwmgr, 968 PPSMC_MSG_SetSoftMaxFclkByFreq, 969 mclk_table->entries[high].clk/100, 970 NULL); 971 break; 972 973 case PP_PCIE: 974 default: 975 break; 976 } 977 return 0; 978 } 979 980 static int smu10_emit_clock_levels(struct pp_hwmgr *hwmgr, 981 enum pp_clock_type type, char *buf, 982 int *offset) 983 { 984 struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend); 985 struct smu10_voltage_dependency_table *mclk_table = 986 data->clock_vol_info.vdd_dep_on_fclk; 987 uint32_t i, now, size = *offset; 988 uint32_t min_freq, max_freq = 0; 989 int ret = 0; 990 991 switch (type) { 992 case PP_SCLK: 993 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &now); 994 if (ret) 995 return ret; 996 997 /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */ 998 if (now == data->gfx_max_freq_limit/100) 999 i = 2; 1000 else if (now == data->gfx_min_freq_limit/100) 1001 i = 0; 1002 else 1003 i = 1; 1004 1005 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", 1006 data->gfx_min_freq_limit / 100, 1007 i == 0 ? "*" : ""); 1008 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n", 1009 i == 1 ? now : SMU10_UMD_PSTATE_GFXCLK, 1010 i == 1 ? "*" : ""); 1011 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", 1012 data->gfx_max_freq_limit / 100, 1013 i == 2 ? "*" : ""); 1014 break; 1015 case PP_MCLK: 1016 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &now); 1017 if (ret) 1018 return ret; 1019 1020 for (i = 0; i < mclk_table->count; i++) 1021 size += sysfs_emit_at( 1022 buf, size, "%d: %uMhz %s\n", i, 1023 mclk_table->entries[i].clk / 100, 1024 ((mclk_table->entries[i].clk / 100) == now) ? 1025 "*" : 1026 ""); 1027 break; 1028 case OD_SCLK: 1029 if (hwmgr->od_enabled) { 1030 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq); 1031 if (ret) 1032 return ret; 1033 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq); 1034 if (ret) 1035 return ret; 1036 1037 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK"); 1038 size += sysfs_emit_at( 1039 buf, size, "0: %10uMhz\n", 1040 (data->gfx_actual_soft_min_freq > 0) ? 1041 data->gfx_actual_soft_min_freq : 1042 min_freq); 1043 size += sysfs_emit_at( 1044 buf, size, "1: %10uMhz\n", 1045 (data->gfx_actual_soft_max_freq > 0) ? 1046 data->gfx_actual_soft_max_freq : 1047 max_freq); 1048 } 1049 break; 1050 case OD_RANGE: 1051 if (hwmgr->od_enabled) { 1052 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq); 1053 if (ret) 1054 return ret; 1055 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq); 1056 if (ret) 1057 return ret; 1058 1059 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE"); 1060 size += sysfs_emit_at(buf, size, 1061 "SCLK: %7uMHz %10uMHz\n", 1062 min_freq, max_freq); 1063 } 1064 break; 1065 default: 1066 break; 1067 } 1068 1069 *offset = size; 1070 1071 return 0; 1072 } 1073 1074 static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, 1075 PHM_PerformanceLevelDesignation designation, uint32_t index, 1076 PHM_PerformanceLevel *level) 1077 { 1078 struct smu10_hwmgr *data; 1079 1080 if (level == NULL || hwmgr == NULL || state == NULL) 1081 return -EINVAL; 1082 1083 data = (struct smu10_hwmgr *)(hwmgr->backend); 1084 1085 if (index == 0) { 1086 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk; 1087 level->coreClock = data->gfx_min_freq_limit; 1088 } else { 1089 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[ 1090 data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk; 1091 level->coreClock = data->gfx_max_freq_limit; 1092 } 1093 1094 level->nonLocalMemoryFreq = 0; 1095 level->nonLocalMemoryWidth = 0; 1096 1097 return 0; 1098 } 1099 1100 static int smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, 1101 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info) 1102 { 1103 const struct smu10_power_state *ps = cast_const_smu10_ps(state); 1104 1105 clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index)); 1106 clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index)); 1107 1108 return 0; 1109 } 1110 1111 #define MEM_FREQ_LOW_LATENCY 25000 1112 #define MEM_FREQ_HIGH_LATENCY 80000 1113 #define MEM_LATENCY_HIGH 245 1114 #define MEM_LATENCY_LOW 35 1115 #define MEM_LATENCY_ERR 0xFFFF 1116 1117 1118 static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr, 1119 uint32_t clock) 1120 { 1121 if (clock >= MEM_FREQ_LOW_LATENCY && 1122 clock < MEM_FREQ_HIGH_LATENCY) 1123 return MEM_LATENCY_HIGH; 1124 else if (clock >= MEM_FREQ_HIGH_LATENCY) 1125 return MEM_LATENCY_LOW; 1126 else 1127 return MEM_LATENCY_ERR; 1128 } 1129 1130 static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, 1131 enum amd_pp_clock_type type, 1132 struct pp_clock_levels_with_latency *clocks) 1133 { 1134 uint32_t i; 1135 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 1136 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info); 1137 struct smu10_voltage_dependency_table *pclk_vol_table; 1138 bool latency_required = false; 1139 1140 if (pinfo == NULL) 1141 return -EINVAL; 1142 1143 switch (type) { 1144 case amd_pp_mem_clock: 1145 pclk_vol_table = pinfo->vdd_dep_on_mclk; 1146 latency_required = true; 1147 break; 1148 case amd_pp_f_clock: 1149 pclk_vol_table = pinfo->vdd_dep_on_fclk; 1150 latency_required = true; 1151 break; 1152 case amd_pp_dcf_clock: 1153 pclk_vol_table = pinfo->vdd_dep_on_dcefclk; 1154 break; 1155 case amd_pp_disp_clock: 1156 pclk_vol_table = pinfo->vdd_dep_on_dispclk; 1157 break; 1158 case amd_pp_phy_clock: 1159 pclk_vol_table = pinfo->vdd_dep_on_phyclk; 1160 break; 1161 case amd_pp_dpp_clock: 1162 pclk_vol_table = pinfo->vdd_dep_on_dppclk; 1163 break; 1164 default: 1165 return -EINVAL; 1166 } 1167 1168 if (pclk_vol_table == NULL || pclk_vol_table->count == 0) 1169 return -EINVAL; 1170 1171 clocks->num_levels = 0; 1172 for (i = 0; i < pclk_vol_table->count; i++) { 1173 if (pclk_vol_table->entries[i].clk) { 1174 clocks->data[clocks->num_levels].clocks_in_khz = 1175 pclk_vol_table->entries[i].clk * 10; 1176 clocks->data[clocks->num_levels].latency_in_us = latency_required ? 1177 smu10_get_mem_latency(hwmgr, 1178 pclk_vol_table->entries[i].clk) : 1179 0; 1180 clocks->num_levels++; 1181 } 1182 } 1183 1184 return 0; 1185 } 1186 1187 static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, 1188 enum amd_pp_clock_type type, 1189 struct pp_clock_levels_with_voltage *clocks) 1190 { 1191 uint32_t i; 1192 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 1193 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info); 1194 struct smu10_voltage_dependency_table *pclk_vol_table = NULL; 1195 1196 if (pinfo == NULL) 1197 return -EINVAL; 1198 1199 switch (type) { 1200 case amd_pp_mem_clock: 1201 pclk_vol_table = pinfo->vdd_dep_on_mclk; 1202 break; 1203 case amd_pp_f_clock: 1204 pclk_vol_table = pinfo->vdd_dep_on_fclk; 1205 break; 1206 case amd_pp_dcf_clock: 1207 pclk_vol_table = pinfo->vdd_dep_on_dcefclk; 1208 break; 1209 case amd_pp_soc_clock: 1210 pclk_vol_table = pinfo->vdd_dep_on_socclk; 1211 break; 1212 case amd_pp_disp_clock: 1213 pclk_vol_table = pinfo->vdd_dep_on_dispclk; 1214 break; 1215 case amd_pp_phy_clock: 1216 pclk_vol_table = pinfo->vdd_dep_on_phyclk; 1217 break; 1218 default: 1219 return -EINVAL; 1220 } 1221 1222 if (pclk_vol_table == NULL || pclk_vol_table->count == 0) 1223 return -EINVAL; 1224 1225 clocks->num_levels = 0; 1226 for (i = 0; i < pclk_vol_table->count; i++) { 1227 if (pclk_vol_table->entries[i].clk) { 1228 clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk * 10; 1229 clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol; 1230 clocks->num_levels++; 1231 } 1232 } 1233 1234 return 0; 1235 } 1236 1237 1238 1239 static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) 1240 { 1241 clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */ 1242 return 0; 1243 } 1244 1245 static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr) 1246 { 1247 struct amdgpu_device *adev = hwmgr->adev; 1248 uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP); 1249 int cur_temp = 1250 (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT; 1251 1252 if (cur_temp & THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK) 1253 cur_temp = ((cur_temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 1254 else 1255 cur_temp = (cur_temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 1256 1257 return cur_temp; 1258 } 1259 1260 static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx, 1261 void *value, int *size) 1262 { 1263 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 1264 struct amdgpu_device *adev = hwmgr->adev; 1265 uint32_t sclk, mclk, activity_percent; 1266 bool has_gfx_busy; 1267 int ret = 0; 1268 1269 /* GetGfxBusy support was added on RV SMU FW 30.85.00 and PCO 4.30.59 */ 1270 if ((adev->apu_flags & AMD_APU_IS_PICASSO) && 1271 (hwmgr->smu_version >= 0x41e3b)) 1272 has_gfx_busy = true; 1273 else if ((adev->apu_flags & AMD_APU_IS_RAVEN) && 1274 (hwmgr->smu_version >= 0x1e5500)) 1275 has_gfx_busy = true; 1276 else 1277 has_gfx_busy = false; 1278 1279 switch (idx) { 1280 case AMDGPU_PP_SENSOR_GFX_SCLK: 1281 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &sclk); 1282 if (ret) 1283 break; 1284 /* in units of 10KHZ */ 1285 *((uint32_t *)value) = sclk * 100; 1286 *size = 4; 1287 break; 1288 case AMDGPU_PP_SENSOR_GFX_MCLK: 1289 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &mclk); 1290 if (ret) 1291 break; 1292 /* in units of 10KHZ */ 1293 *((uint32_t *)value) = mclk * 100; 1294 *size = 4; 1295 break; 1296 case AMDGPU_PP_SENSOR_GPU_TEMP: 1297 *((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr); 1298 break; 1299 case AMDGPU_PP_SENSOR_VCN_POWER_STATE: 1300 *(uint32_t *)value = smu10_data->vcn_power_gated ? 0 : 1; 1301 *size = 4; 1302 break; 1303 case AMDGPU_PP_SENSOR_GPU_LOAD: 1304 if (!has_gfx_busy) 1305 ret = -EOPNOTSUPP; 1306 else { 1307 ret = smum_send_msg_to_smc(hwmgr, 1308 PPSMC_MSG_GetGfxBusy, 1309 &activity_percent); 1310 if (!ret) 1311 *((uint32_t *)value) = min(activity_percent, (u32)100); 1312 else 1313 ret = -EIO; 1314 } 1315 break; 1316 default: 1317 ret = -EOPNOTSUPP; 1318 break; 1319 } 1320 1321 return ret; 1322 } 1323 1324 static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, 1325 void *clock_ranges) 1326 { 1327 struct smu10_hwmgr *data = hwmgr->backend; 1328 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; 1329 Watermarks_t *table = &(data->water_marks_table); 1330 struct amdgpu_device *adev = hwmgr->adev; 1331 int i; 1332 1333 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges); 1334 1335 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 1336 for (i = 0; i < NUM_WM_RANGES; i++) 1337 table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0; 1338 1339 for (i = 0; i < NUM_WM_RANGES; i++) 1340 table->WatermarkRow[WM_SOCCLK][i].WmType = (uint8_t)0; 1341 } 1342 1343 smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false); 1344 data->water_marks_exist = true; 1345 return 0; 1346 } 1347 1348 static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr) 1349 { 1350 1351 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SetRccPfcPmeRestoreRegister, NULL); 1352 } 1353 1354 static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr) 1355 { 1356 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub, NULL); 1357 } 1358 1359 static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate) 1360 { 1361 if (gate) 1362 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma, NULL); 1363 else 1364 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma, NULL); 1365 } 1366 1367 static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate) 1368 { 1369 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 1370 1371 if (bgate) { 1372 amdgpu_device_ip_set_powergating_state(hwmgr->adev, 1373 AMD_IP_BLOCK_TYPE_VCN, 1374 AMD_PG_STATE_GATE); 1375 smum_send_msg_to_smc_with_parameter(hwmgr, 1376 PPSMC_MSG_PowerDownVcn, 0, NULL); 1377 smu10_data->vcn_power_gated = true; 1378 } else { 1379 smum_send_msg_to_smc_with_parameter(hwmgr, 1380 PPSMC_MSG_PowerUpVcn, 0, NULL); 1381 amdgpu_device_ip_set_powergating_state(hwmgr->adev, 1382 AMD_IP_BLOCK_TYPE_VCN, 1383 AMD_PG_STATE_UNGATE); 1384 smu10_data->vcn_power_gated = false; 1385 } 1386 } 1387 1388 static int conv_power_profile_to_pplib_workload(int power_profile) 1389 { 1390 int pplib_workload = 0; 1391 1392 switch (power_profile) { 1393 case PP_SMC_POWER_PROFILE_FULLSCREEN3D: 1394 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT; 1395 break; 1396 case PP_SMC_POWER_PROFILE_VIDEO: 1397 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT; 1398 break; 1399 case PP_SMC_POWER_PROFILE_VR: 1400 pplib_workload = WORKLOAD_PPLIB_VR_BIT; 1401 break; 1402 case PP_SMC_POWER_PROFILE_COMPUTE: 1403 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT; 1404 break; 1405 case PP_SMC_POWER_PROFILE_CUSTOM: 1406 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT; 1407 break; 1408 } 1409 1410 return pplib_workload; 1411 } 1412 1413 static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 1414 { 1415 uint32_t i, size = 0; 1416 static const uint8_t 1417 profile_mode_setting[6][4] = {{70, 60, 0, 0,}, 1418 {70, 60, 1, 3,}, 1419 {90, 60, 0, 0,}, 1420 {70, 60, 0, 0,}, 1421 {70, 90, 0, 0,}, 1422 {30, 60, 0, 6,}, 1423 }; 1424 static const char *title[6] = {"NUM", 1425 "MODE_NAME", 1426 "BUSY_SET_POINT", 1427 "FPS", 1428 "USE_RLC_BUSY", 1429 "MIN_ACTIVE_LEVEL"}; 1430 1431 if (!buf) 1432 return -EINVAL; 1433 1434 phm_get_sysfs_buf(&buf, &size); 1435 1436 size += sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n", title[0], 1437 title[1], title[2], title[3], title[4], title[5]); 1438 1439 for (i = 0; i <= PP_SMC_POWER_PROFILE_COMPUTE; i++) 1440 size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n", 1441 i, amdgpu_pp_profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ", 1442 profile_mode_setting[i][0], profile_mode_setting[i][1], 1443 profile_mode_setting[i][2], profile_mode_setting[i][3]); 1444 1445 return size; 1446 } 1447 1448 static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr) 1449 { 1450 struct amdgpu_device *adev = hwmgr->adev; 1451 if ((adev->apu_flags & AMD_APU_IS_RAVEN) && 1452 (hwmgr->smu_version >= 0x41e2b)) 1453 return true; 1454 else 1455 return false; 1456 } 1457 1458 static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) 1459 { 1460 int workload_type = 0; 1461 int result = 0; 1462 1463 if (input[size] > PP_SMC_POWER_PROFILE_COMPUTE) { 1464 pr_err("Invalid power profile mode %ld\n", input[size]); 1465 return -EINVAL; 1466 } 1467 if (hwmgr->power_profile_mode == input[size]) 1468 return 0; 1469 1470 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ 1471 workload_type = 1472 conv_power_profile_to_pplib_workload(input[size]); 1473 if (workload_type && 1474 smu10_is_raven1_refresh(hwmgr) && 1475 !hwmgr->gfxoff_state_changed_by_workload) { 1476 smu10_gfx_off_control(hwmgr, false); 1477 hwmgr->gfxoff_state_changed_by_workload = true; 1478 } 1479 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ActiveProcessNotify, 1480 1 << workload_type, 1481 NULL); 1482 if (!result) 1483 hwmgr->power_profile_mode = input[size]; 1484 if (workload_type && hwmgr->gfxoff_state_changed_by_workload) { 1485 smu10_gfx_off_control(hwmgr, true); 1486 hwmgr->gfxoff_state_changed_by_workload = false; 1487 } 1488 1489 return 0; 1490 } 1491 1492 static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode) 1493 { 1494 return smum_send_msg_to_smc_with_parameter(hwmgr, 1495 PPSMC_MSG_DeviceDriverReset, 1496 mode, 1497 NULL); 1498 } 1499 1500 static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr, 1501 enum PP_OD_DPM_TABLE_COMMAND type, 1502 long *input, uint32_t size) 1503 { 1504 uint32_t min_freq, max_freq = 0; 1505 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend); 1506 int ret = 0; 1507 1508 if (!hwmgr->od_enabled) { 1509 pr_err("Fine grain not support\n"); 1510 return -EINVAL; 1511 } 1512 1513 if (!smu10_data->fine_grain_enabled) { 1514 pr_err("pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n"); 1515 return -EINVAL; 1516 } 1517 1518 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) { 1519 if (size != 2) { 1520 pr_err("Input parameter number not correct\n"); 1521 return -EINVAL; 1522 } 1523 1524 if (input[0] == 0) { 1525 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq); 1526 if (ret) 1527 return ret; 1528 1529 if (input[1] < min_freq) { 1530 pr_err("Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n", 1531 input[1], min_freq); 1532 return -EINVAL; 1533 } 1534 smu10_data->gfx_actual_soft_min_freq = input[1]; 1535 } else if (input[0] == 1) { 1536 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq); 1537 if (ret) 1538 return ret; 1539 1540 if (input[1] > max_freq) { 1541 pr_err("Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n", 1542 input[1], max_freq); 1543 return -EINVAL; 1544 } 1545 smu10_data->gfx_actual_soft_max_freq = input[1]; 1546 } else { 1547 return -EINVAL; 1548 } 1549 } else if (type == PP_OD_RESTORE_DEFAULT_TABLE) { 1550 if (size != 0) { 1551 pr_err("Input parameter number not correct\n"); 1552 return -EINVAL; 1553 } 1554 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq); 1555 if (ret) 1556 return ret; 1557 smu10_data->gfx_actual_soft_min_freq = min_freq; 1558 1559 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq); 1560 if (ret) 1561 return ret; 1562 1563 smu10_data->gfx_actual_soft_max_freq = max_freq; 1564 } else if (type == PP_OD_COMMIT_DPM_TABLE) { 1565 if (size != 0) { 1566 pr_err("Input parameter number not correct\n"); 1567 return -EINVAL; 1568 } 1569 1570 if (smu10_data->gfx_actual_soft_min_freq > smu10_data->gfx_actual_soft_max_freq) { 1571 pr_err("The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n", 1572 smu10_data->gfx_actual_soft_min_freq, smu10_data->gfx_actual_soft_max_freq); 1573 return -EINVAL; 1574 } 1575 1576 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 1577 PPSMC_MSG_SetHardMinGfxClk, 1578 smu10_data->gfx_actual_soft_min_freq, 1579 NULL); 1580 if (ret) 1581 return ret; 1582 1583 ret = smum_send_msg_to_smc_with_parameter(hwmgr, 1584 PPSMC_MSG_SetSoftMaxGfxClk, 1585 smu10_data->gfx_actual_soft_max_freq, 1586 NULL); 1587 if (ret) 1588 return ret; 1589 } else { 1590 return -EINVAL; 1591 } 1592 1593 return 0; 1594 } 1595 1596 static int smu10_gfx_state_change(struct pp_hwmgr *hwmgr, uint32_t state) 1597 { 1598 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GpuChangeState, state, NULL); 1599 1600 return 0; 1601 } 1602 1603 static const struct pp_hwmgr_func smu10_hwmgr_funcs = { 1604 .backend_init = smu10_hwmgr_backend_init, 1605 .backend_fini = smu10_hwmgr_backend_fini, 1606 .apply_state_adjust_rules = smu10_apply_state_adjust_rules, 1607 .force_dpm_level = smu10_dpm_force_dpm_level, 1608 .get_power_state_size = smu10_get_power_state_size, 1609 .powergate_uvd = smu10_powergate_vcn, 1610 .powergate_vce = NULL, 1611 .get_mclk = smu10_dpm_get_mclk, 1612 .get_sclk = smu10_dpm_get_sclk, 1613 .patch_boot_state = smu10_dpm_patch_boot_state, 1614 .get_pp_table_entry = smu10_dpm_get_pp_table_entry, 1615 .get_num_of_pp_table_entries = smu10_dpm_get_num_of_pp_table_entries, 1616 .set_cpu_power_state = smu10_set_cpu_power_state, 1617 .store_cc6_data = smu10_store_cc6_data, 1618 .force_clock_level = smu10_force_clock_level, 1619 .emit_clock_levels = smu10_emit_clock_levels, 1620 .get_performance_level = smu10_get_performance_level, 1621 .get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks, 1622 .get_clock_by_type_with_latency = smu10_get_clock_by_type_with_latency, 1623 .get_clock_by_type_with_voltage = smu10_get_clock_by_type_with_voltage, 1624 .set_watermarks_for_clocks_ranges = smu10_set_watermarks_for_clocks_ranges, 1625 .get_max_high_clocks = smu10_get_max_high_clocks, 1626 .read_sensor = smu10_read_sensor, 1627 .set_active_display_count = smu10_set_active_display_count, 1628 .set_min_deep_sleep_dcefclk = smu10_set_min_deep_sleep_dcefclk, 1629 .dynamic_state_management_enable = smu10_enable_dpm_tasks, 1630 .power_off_asic = smu10_power_off_asic, 1631 .asic_setup = smu10_setup_asic_task, 1632 .power_state_set = smu10_set_power_state_tasks, 1633 .dynamic_state_management_disable = smu10_disable_dpm_tasks, 1634 .powergate_mmhub = smu10_powergate_mmhub, 1635 .smus_notify_pwe = smu10_smus_notify_pwe, 1636 .display_clock_voltage_request = smu10_display_clock_voltage_request, 1637 .powergate_gfx = smu10_gfx_off_control, 1638 .powergate_sdma = smu10_powergate_sdma, 1639 .set_hard_min_dcefclk_by_freq = smu10_set_hard_min_dcefclk_by_freq, 1640 .set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq, 1641 .set_hard_min_gfxclk_by_freq = smu10_set_hard_min_gfxclk_by_freq, 1642 .set_soft_max_gfxclk_by_freq = smu10_set_soft_max_gfxclk_by_freq, 1643 .get_power_profile_mode = smu10_get_power_profile_mode, 1644 .set_power_profile_mode = smu10_set_power_profile_mode, 1645 .asic_reset = smu10_asic_reset, 1646 .set_fine_grain_clk_vol = smu10_set_fine_grain_clk_vol, 1647 .gfx_state_change = smu10_gfx_state_change, 1648 }; 1649 1650 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr) 1651 { 1652 hwmgr->hwmgr_func = &smu10_hwmgr_funcs; 1653 hwmgr->pptable_func = &pptable_funcs; 1654 return 0; 1655 } 1656