1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Microchip lan969x Switch driver 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. 5 */ 6 7 /* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. 8 * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b 9 */ 10 11 #include "lan969x.h" 12 13 const unsigned int lan969x_tsize[TSIZE_LAST] = { 14 [TC_DEV10G] = 10, 15 [TC_DEV2G5] = 28, 16 [TC_DEV5G] = 4, 17 [TC_PCS10G_BR] = 10, 18 [TC_PCS5G_BR] = 4, 19 }; 20 21 const unsigned int lan969x_raddr[RADDR_LAST] = { 22 [RA_CPU_PROC_CTRL] = 160, 23 [RA_GCB_SOFT_RST] = 12, 24 [RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 20, 25 }; 26 27 const unsigned int lan969x_rcnt[RCNT_LAST] = { 28 [RC_ANA_AC_OWN_UPSID] = 1, 29 [RC_ANA_ACL_VCAP_S2_CFG] = 35, 30 [RC_ANA_ACL_OWN_UPSID] = 1, 31 [RC_ANA_CL_OWN_UPSID] = 1, 32 [RC_ANA_L2_OWN_UPSID] = 1, 33 [RC_ASM_PORT_CFG] = 32, 34 [RC_DSM_BUF_CFG] = 32, 35 [RC_DSM_DEV_TX_STOP_WM_CFG] = 32, 36 [RC_DSM_RX_PAUSE_CFG] = 32, 37 [RC_DSM_MAC_CFG] = 32, 38 [RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 30, 39 [RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 30, 40 [RC_DSM_TAXI_CAL_CFG] = 6, 41 [RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 30, 42 [RC_HSCH_PORT_MODE] = 35, 43 [RC_QFWD_SWITCH_PORT_MODE] = 35, 44 [RC_QSYS_PAUSE_CFG] = 35, 45 [RC_QSYS_ATOP] = 35, 46 [RC_QSYS_FWD_PRESSURE] = 35, 47 [RC_QSYS_CAL_AUTO] = 4, 48 [RC_REW_OWN_UPSID] = 1, 49 [RC_REW_RTAG_ETAG_CTRL] = 35, 50 }; 51 52 const unsigned int lan969x_gaddr[GADDR_LAST] = { 53 [GA_ANA_AC_RAM_CTRL] = 202000, 54 [GA_ANA_AC_PS_COMMON] = 202880, 55 [GA_ANA_AC_MIRROR_PROBE] = 203232, 56 [GA_ANA_AC_SRC] = 201728, 57 [GA_ANA_AC_PGID] = 131072, 58 [GA_ANA_AC_TSN_SF] = 202028, 59 [GA_ANA_AC_TSN_SF_CFG] = 148480, 60 [GA_ANA_AC_TSN_SF_STATUS] = 147936, 61 [GA_ANA_AC_SG_ACCESS] = 202032, 62 [GA_ANA_AC_SG_CONFIG] = 202752, 63 [GA_ANA_AC_SG_STATUS] = 147952, 64 [GA_ANA_AC_SG_STATUS_STICKY] = 202044, 65 [GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 202048, 66 [GA_ANA_AC_STAT_CNT_CFG_PORT] = 204800, 67 [GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 202068, 68 [GA_ANA_ACL_COMMON] = 8192, 69 [GA_ANA_ACL_KEY_SEL] = 9204, 70 [GA_ANA_ACL_CNT_B] = 4096, 71 [GA_ANA_ACL_STICKY] = 10852, 72 [GA_ANA_AC_POL_POL_ALL_CFG] = 17504, 73 [GA_ANA_AC_POL_COMMON_BDLB] = 19464, 74 [GA_ANA_AC_POL_COMMON_BUM_SLB] = 19472, 75 [GA_ANA_AC_SDLB_LBGRP_TBL] = 31788, 76 [GA_ANA_CL_PORT] = 65536, 77 [GA_ANA_CL_COMMON] = 87040, 78 [GA_ANA_L2_COMMON] = 561928, 79 [GA_ANA_L3_COMMON] = 370752, 80 [GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 368580, 81 [GA_ASM_CFG] = 18304, 82 [GA_ASM_PFC_TIMER_CFG] = 15568, 83 [GA_ASM_LBK_WM_CFG] = 15596, 84 [GA_ASM_LBK_MISC_CFG] = 15608, 85 [GA_ASM_RAM_CTRL] = 15684, 86 [GA_EACL_ES2_KEY_SELECT_PROFILE] = 36864, 87 [GA_EACL_CNT_TBL] = 30720, 88 [GA_EACL_POL_CFG] = 38400, 89 [GA_EACL_ES2_STICKY] = 29072, 90 [GA_EACL_RAM_CTRL] = 29112, 91 [GA_GCB_SIO_CTRL] = 560, 92 [GA_HSCH_HSCH_DWRR] = 36480, 93 [GA_HSCH_HSCH_MISC] = 36608, 94 [GA_HSCH_HSCH_LEAK_LISTS] = 37256, 95 [GA_HSCH_SYSTEM] = 37384, 96 [GA_HSCH_MMGT] = 36260, 97 [GA_HSCH_TAS_CONFIG] = 37696, 98 [GA_PTP_PTP_CFG] = 512, 99 [GA_PTP_PTP_TOD_DOMAINS] = 528, 100 [GA_PTP_PHASE_DETECTOR_CTRL] = 628, 101 [GA_QSYS_CALCFG] = 2164, 102 [GA_QSYS_RAM_CTRL] = 2204, 103 [GA_REW_COMMON] = 98304, 104 [GA_REW_PORT] = 49152, 105 [GA_REW_VOE_PORT_LM_CNT] = 90112, 106 [GA_REW_RAM_CTRL] = 93992, 107 [GA_VOP_RAM_CTRL] = 16368, 108 [GA_XQS_SYSTEM] = 5744, 109 [GA_XQS_QLIMIT_SHR] = 6912, 110 }; 111 112 const unsigned int lan969x_gcnt[GCNT_LAST] = { 113 [GC_ANA_AC_SRC] = 67, 114 [GC_ANA_AC_PGID] = 1054, 115 [GC_ANA_AC_TSN_SF_CFG] = 256, 116 [GC_ANA_AC_STAT_CNT_CFG_PORT] = 35, 117 [GC_ANA_ACL_KEY_SEL] = 99, 118 [GC_ANA_ACL_CNT_A] = 1024, 119 [GC_ANA_ACL_CNT_B] = 1024, 120 [GC_ANA_AC_SDLB_LBGRP_TBL] = 5, 121 [GC_ANA_AC_SDLB_LBSET_TBL] = 496, 122 [GC_ANA_CL_PORT] = 35, 123 [GC_ANA_L2_ISDX_LIMIT] = 256, 124 [GC_ANA_L2_ISDX] = 1024, 125 [GC_ANA_L3_VLAN] = 4608, 126 [GC_ASM_DEV_STATISTICS] = 30, 127 [GC_EACL_ES2_KEY_SELECT_PROFILE] = 68, 128 [GC_EACL_CNT_TBL] = 512, 129 [GC_GCB_SIO_CTRL] = 1, 130 [GC_HSCH_HSCH_CFG] = 1120, 131 [GC_HSCH_HSCH_DWRR] = 32, 132 [GC_PTP_PTP_PINS] = 8, 133 [GC_PTP_PHASE_DETECTOR_CTRL] = 8, 134 [GC_REW_PORT] = 35, 135 [GC_REW_VOE_PORT_LM_CNT] = 240, 136 }; 137 138 const unsigned int lan969x_gsize[GSIZE_LAST] = { 139 [GW_ANA_AC_SRC] = 4, 140 [GW_ANA_L2_COMMON] = 712, 141 [GW_ASM_CFG] = 1092, 142 [GW_CPU_CPU_REGS] = 180, 143 [GW_DEV2G5_PHASE_DETECTOR_CTRL] = 12, 144 [GW_FDMA_FDMA] = 448, 145 [GW_GCB_CHIP_REGS] = 180, 146 [GW_HSCH_TAS_CONFIG] = 16, 147 [GW_PTP_PHASE_DETECTOR_CTRL] = 12, 148 [GW_QSYS_PAUSE_CFG] = 988, 149 }; 150 151 const unsigned int lan969x_fpos[FPOS_LAST] = { 152 [FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] = 7, 153 [FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] = 6, 154 [FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] = 5, 155 [FP_CPU_PROC_CTRL_BE_EXCEP_MODE] = 4, 156 [FP_CPU_PROC_CTRL_VINITHI] = 3, 157 [FP_CPU_PROC_CTRL_CFGTE] = 2, 158 [FP_CPU_PROC_CTRL_CP15S_DISABLE] = 1, 159 [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 0, 160 [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 8, 161 [FP_DEV2G5_PHAD_CTRL_PHAD_ENA] = 5, 162 [FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] = 3, 163 [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 5, 164 [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 4, 165 [FP_FDMA_CH_CFG_CH_INJ_PORT] = 3, 166 [FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] = 27, 167 [FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] = 25, 168 [FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] = 24, 169 [FP_PTP_PHAD_CTRL_PHAD_ENA] = 5, 170 [FP_PTP_PHAD_CTRL_PHAD_FAILED] = 3, 171 }; 172 173 const unsigned int lan969x_fsize[FSIZE_LAST] = { 174 [FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] = 30, 175 [FW_ANA_AC_SRC_CFG_PORT_MASK] = 30, 176 [FW_ANA_AC_PGID_CFG_PORT_MASK] = 30, 177 [FW_ANA_AC_TSN_SF_PORT_NUM] = 7, 178 [FW_ANA_AC_TSN_SF_CFG_TSN_SGID] = 8, 179 [FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] = 8, 180 [FW_ANA_AC_SG_ACCESS_CTRL_SGID] = 8, 181 [FW_ANA_AC_PORT_SGE_CFG_MASK] = 17, 182 [FW_ANA_AC_SDLB_XLB_START_LBSET_START] = 9, 183 [FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] = 3, 184 [FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] = 9, 185 [FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] = 9, 186 [FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] = 3, 187 [FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] = 9, 188 [FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] = 30, 189 [FW_ANA_L2_DLB_CFG_DLB_IDX] = 9, 190 [FW_ANA_L2_TSN_CFG_TSN_SFID] = 8, 191 [FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] = 30, 192 [FW_FDMA_CH_CFG_CH_DCB_DB_CNT] = 2, 193 [FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] = 7, 194 [FW_HSCH_SE_CFG_SE_DWRR_CNT] = 5, 195 [FW_HSCH_SE_CONNECT_SE_LEAK_LINK] = 14, 196 [FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] = 6, 197 [FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] = 11, 198 [FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] = 14, 199 [FW_HSCH_FLUSH_CTRL_FLUSH_PORT] = 6, 200 [FW_HSCH_FLUSH_CTRL_FLUSH_HIER] = 14, 201 [FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] = 13, 202 [FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] = 8, 203 [FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] = 13, 204 [FW_PTP_PTP_PIN_INTR_INTR_PTP] = 8, 205 [FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] = 8, 206 [FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] = 8, 207 [FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] = 3, 208 [FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] = 6, 209 [FW_QRES_RES_CFG_WM_HIGH] = 11, 210 [FW_QRES_RES_STAT_MAXUSE] = 19, 211 [FW_QRES_RES_STAT_CUR_INUSE] = 19, 212 [FW_QSYS_PAUSE_CFG_PAUSE_START] = 11, 213 [FW_QSYS_PAUSE_CFG_PAUSE_STOP] = 11, 214 [FW_QSYS_ATOP_ATOP] = 11, 215 [FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] = 11, 216 [FW_REW_RTAG_ETAG_CTRL_IPE_TBL] = 6, 217 [FW_XQS_STAT_CFG_STAT_VIEW] = 10, 218 [FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] = 14, 219 [FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] = 14, 220 [FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] = 14, 221 [FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] = 14, 222 }; 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