1 // SPDX-License-Identifier: GPL-2.0 2 /* Microchip LAN937X switch driver main logic 3 * Copyright (C) 2019-2024 Microchip Technology Inc. 4 */ 5 #include <linux/dsa/ksz_common.h> 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/iopoll.h> 9 #include <linux/phy.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_net.h> 12 #include <linux/if_bridge.h> 13 #include <linux/if_vlan.h> 14 #include <linux/math.h> 15 #include <net/dsa.h> 16 #include <net/switchdev.h> 17 18 #include "lan937x_reg.h" 19 #include "ksz_common.h" 20 #include "ksz_dcb.h" 21 #include "ksz9477.h" 22 #include "lan937x.h" 23 24 /* marker for ports without built-in PHY */ 25 #define LAN937X_NO_PHY U8_MAX 26 27 /* 28 * lan9370_phy_addr - Mapping of LAN9370 switch ports to PHY addresses. 29 * 30 * Each entry corresponds to a specific port on the LAN9370 switch, 31 * where ports 1-4 are connected to integrated 100BASE-T1 PHYs, and 32 * Port 5 is connected to an RGMII interface without a PHY. The values 33 * are based on the documentation (DS00003108E, section 3.3). 34 */ 35 static const u8 lan9370_phy_addr[] = { 36 [0] = 2, /* Port 1, T1 AFE0 */ 37 [1] = 3, /* Port 2, T1 AFE1 */ 38 [2] = 5, /* Port 3, T1 AFE3 */ 39 [3] = 6, /* Port 4, T1 AFE4 */ 40 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 41 }; 42 43 /* 44 * lan9371_phy_addr - Mapping of LAN9371 switch ports to PHY addresses. 45 * 46 * The values are based on the documentation (DS00003109E, section 3.3). 47 */ 48 static const u8 lan9371_phy_addr[] = { 49 [0] = 2, /* Port 1, T1 AFE0 */ 50 [1] = 3, /* Port 2, T1 AFE1 */ 51 [2] = 5, /* Port 3, T1 AFE3 */ 52 [3] = 8, /* Port 4, TX PHY */ 53 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 54 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */ 55 }; 56 57 /* 58 * lan9372_phy_addr - Mapping of LAN9372 switch ports to PHY addresses. 59 * 60 * The values are based on the documentation (DS00003110F, section 3.3). 61 */ 62 static const u8 lan9372_phy_addr[] = { 63 [0] = 2, /* Port 1, T1 AFE0 */ 64 [1] = 3, /* Port 2, T1 AFE1 */ 65 [2] = 5, /* Port 3, T1 AFE3 */ 66 [3] = 8, /* Port 4, TX PHY */ 67 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 68 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */ 69 [6] = 6, /* Port 7, T1 AFE4 */ 70 [7] = 4, /* Port 8, T1 AFE2 */ 71 }; 72 73 /* 74 * lan9373_phy_addr - Mapping of LAN9373 switch ports to PHY addresses. 75 * 76 * The values are based on the documentation (DS00003110F, section 3.3). 77 */ 78 static const u8 lan9373_phy_addr[] = { 79 [0] = 2, /* Port 1, T1 AFE0 */ 80 [1] = 3, /* Port 2, T1 AFE1 */ 81 [2] = 5, /* Port 3, T1 AFE3 */ 82 [3] = LAN937X_NO_PHY, /* Port 4, SGMII */ 83 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 84 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */ 85 [6] = 6, /* Port 7, T1 AFE4 */ 86 [7] = 4, /* Port 8, T1 AFE2 */ 87 }; 88 89 /* 90 * lan9374_phy_addr - Mapping of LAN9374 switch ports to PHY addresses. 91 * 92 * The values are based on the documentation (DS00003110F, section 3.3). 93 */ 94 static const u8 lan9374_phy_addr[] = { 95 [0] = 2, /* Port 1, T1 AFE0 */ 96 [1] = 3, /* Port 2, T1 AFE1 */ 97 [2] = 5, /* Port 3, T1 AFE3 */ 98 [3] = 7, /* Port 4, T1 AFE5 */ 99 [4] = LAN937X_NO_PHY, /* Port 5, RGMII 2 */ 100 [5] = LAN937X_NO_PHY, /* Port 6, RGMII 1 */ 101 [6] = 6, /* Port 7, T1 AFE4 */ 102 [7] = 4, /* Port 8, T1 AFE2 */ 103 }; 104 105 static int lan937x_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 106 { 107 return regmap_update_bits(ksz_regmap_8(dev), addr, bits, set ? bits : 0); 108 } 109 110 static int lan937x_port_cfg(struct ksz_device *dev, int port, int offset, 111 u8 bits, bool set) 112 { 113 return regmap_update_bits(ksz_regmap_8(dev), PORT_CTRL_ADDR(port, offset), 114 bits, set ? bits : 0); 115 } 116 117 /** 118 * lan937x_create_phy_addr_map - Create port-to-PHY address map for MDIO bus. 119 * @dev: Pointer to device structure. 120 * @side_mdio: Boolean indicating if the PHYs are accessed over a side MDIO bus. 121 * 122 * This function sets up the PHY address mapping for the LAN937x switches, 123 * which support two access modes for internal PHYs: 124 * 1. **SPI Access**: A straightforward one-to-one port-to-PHY address 125 * mapping is applied. 126 * 2. **MDIO Access**: The PHY address mapping varies based on chip variant 127 * and strap configuration. An offset is calculated based on strap settings 128 * to ensure correct PHY addresses are assigned. The offset calculation logic 129 * is based on Microchip's Article Number 000015828, available at: 130 * https://microchip.my.site.com/s/article/LAN9374-Virtual-PHY-PHY-Address-Mapping 131 * 132 * The function first checks if side MDIO access is disabled, in which case a 133 * simple direct mapping (port number = PHY address) is applied. If side MDIO 134 * access is enabled, it reads the strap configuration to determine the correct 135 * offset for PHY addresses. 136 * 137 * The appropriate mapping table is selected based on the chip ID, and the 138 * `phy_addr_map` is populated with the correct addresses for each port. Any 139 * port with no PHY is assigned a `LAN937X_NO_PHY` marker. 140 * 141 * Return: 0 on success, error code on failure. 142 */ 143 static int lan937x_create_phy_addr_map(struct ksz_device *dev, bool side_mdio) 144 { 145 static const u8 *phy_addr_map; 146 u32 strap_val; 147 u8 offset = 0; 148 size_t size; 149 int ret, i; 150 151 if (!side_mdio) { 152 /* simple direct mapping */ 153 for (i = 0; i < dev->info->port_cnt; i++) 154 dev->phy_addr_map[i] = i; 155 156 return 0; 157 } 158 159 ret = ksz_read32(dev, REG_SW_CFG_STRAP_VAL, &strap_val); 160 if (ret < 0) 161 return ret; 162 163 if (!(strap_val & SW_CASCADE_ID_CFG) && !(strap_val & SW_VPHY_ADD_CFG)) 164 offset = 0; 165 else if (!(strap_val & SW_CASCADE_ID_CFG) && (strap_val & SW_VPHY_ADD_CFG)) 166 offset = 7; 167 else if ((strap_val & SW_CASCADE_ID_CFG) && !(strap_val & SW_VPHY_ADD_CFG)) 168 offset = 15; 169 else 170 offset = 22; 171 172 switch (dev->info->chip_id) { 173 case LAN9370_CHIP_ID: 174 phy_addr_map = lan9370_phy_addr; 175 size = ARRAY_SIZE(lan9370_phy_addr); 176 break; 177 case LAN9371_CHIP_ID: 178 phy_addr_map = lan9371_phy_addr; 179 size = ARRAY_SIZE(lan9371_phy_addr); 180 break; 181 case LAN9372_CHIP_ID: 182 phy_addr_map = lan9372_phy_addr; 183 size = ARRAY_SIZE(lan9372_phy_addr); 184 break; 185 case LAN9373_CHIP_ID: 186 phy_addr_map = lan9373_phy_addr; 187 size = ARRAY_SIZE(lan9373_phy_addr); 188 break; 189 case LAN9374_CHIP_ID: 190 phy_addr_map = lan9374_phy_addr; 191 size = ARRAY_SIZE(lan9374_phy_addr); 192 break; 193 default: 194 return -EINVAL; 195 } 196 197 if (size < dev->info->port_cnt) 198 return -EINVAL; 199 200 for (i = 0; i < dev->info->port_cnt; i++) { 201 if (phy_addr_map[i] == LAN937X_NO_PHY) 202 dev->phy_addr_map[i] = phy_addr_map[i]; 203 else 204 dev->phy_addr_map[i] = phy_addr_map[i] + offset; 205 } 206 207 return 0; 208 } 209 210 /** 211 * lan937x_mdio_bus_preinit - Pre-initialize MDIO bus for accessing PHYs. 212 * @dev: Pointer to device structure. 213 * @side_mdio: Boolean indicating if the PHYs are accessed over a side MDIO bus. 214 * 215 * This function configures the LAN937x switch for PHY access either through 216 * SPI or the side MDIO bus, unlocking the necessary registers for each access 217 * mode. 218 * 219 * Operation Modes: 220 * 1. **SPI Access**: Enables SPI indirect access to address clock domain 221 * crossing issues when SPI is used for PHY access. 222 * 2. **MDIO Access**: Grants access to internal PHYs over the side MDIO bus, 223 * required when using the MDIO bus for PHY management. 224 * 225 * Return: 0 on success, error code on failure. 226 */ 227 static int lan937x_mdio_bus_preinit(struct ksz_device *dev, bool side_mdio) 228 { 229 u16 data16; 230 int ret; 231 232 /* Unlock access to the PHYs, needed for SPI and side MDIO access */ 233 ret = lan937x_cfg(dev, REG_GLOBAL_CTRL_0, SW_PHY_REG_BLOCK, false); 234 if (ret < 0) 235 goto print_error; 236 237 if (side_mdio) 238 /* Allow access to internal PHYs over MDIO bus */ 239 data16 = VPHY_MDIO_INTERNAL_ENABLE; 240 else 241 /* Enable SPI indirect access to address clock domain crossing 242 * issue 243 */ 244 data16 = VPHY_SPI_INDIRECT_ENABLE; 245 246 ret = ksz_rmw16(dev, REG_VPHY_SPECIAL_CTRL__2, 247 VPHY_SPI_INDIRECT_ENABLE | VPHY_MDIO_INTERNAL_ENABLE, 248 data16); 249 250 print_error: 251 if (ret < 0) 252 dev_err(dev->dev, "failed to preinit the MDIO bus\n"); 253 254 return ret; 255 } 256 257 static int lan937x_vphy_ind_addr_wr(struct ksz_device *dev, int addr, int reg) 258 { 259 u16 addr_base = REG_PORT_T1_PHY_CTRL_BASE; 260 u16 temp; 261 262 if (is_lan937x_tx_phy(dev, addr)) 263 addr_base = REG_PORT_TX_PHY_CTRL_BASE; 264 265 /* get register address based on the logical port */ 266 temp = PORT_CTRL_ADDR(addr, (addr_base + (reg << 2))); 267 268 return ksz_write16(dev, REG_VPHY_IND_ADDR__2, temp); 269 } 270 271 static int lan937x_internal_phy_write(struct ksz_device *dev, int addr, int reg, 272 u16 val) 273 { 274 unsigned int value; 275 int ret; 276 277 /* Check for internal phy port */ 278 if (!dev->info->internal_phy[addr]) 279 return -EOPNOTSUPP; 280 281 ret = lan937x_vphy_ind_addr_wr(dev, addr, reg); 282 if (ret < 0) 283 return ret; 284 285 /* Write the data to be written to the VPHY reg */ 286 ret = ksz_write16(dev, REG_VPHY_IND_DATA__2, val); 287 if (ret < 0) 288 return ret; 289 290 /* Write the Write En and Busy bit */ 291 ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, 292 (VPHY_IND_WRITE | VPHY_IND_BUSY)); 293 if (ret < 0) 294 return ret; 295 296 ret = regmap_read_poll_timeout(ksz_regmap_16(dev), REG_VPHY_IND_CTRL__2, 297 value, !(value & VPHY_IND_BUSY), 10, 298 1000); 299 if (ret < 0) { 300 dev_err(dev->dev, "Failed to write phy register\n"); 301 return ret; 302 } 303 304 return 0; 305 } 306 307 static int lan937x_internal_phy_read(struct ksz_device *dev, int addr, int reg, 308 u16 *val) 309 { 310 unsigned int value; 311 int ret; 312 313 /* Check for internal phy port, return 0xffff for non-existent phy */ 314 if (!dev->info->internal_phy[addr]) 315 return 0xffff; 316 317 ret = lan937x_vphy_ind_addr_wr(dev, addr, reg); 318 if (ret < 0) 319 return ret; 320 321 /* Write Read and Busy bit to start the transaction */ 322 ret = ksz_write16(dev, REG_VPHY_IND_CTRL__2, VPHY_IND_BUSY); 323 if (ret < 0) 324 return ret; 325 326 ret = regmap_read_poll_timeout(ksz_regmap_16(dev), REG_VPHY_IND_CTRL__2, 327 value, !(value & VPHY_IND_BUSY), 10, 328 1000); 329 if (ret < 0) { 330 dev_err(dev->dev, "Failed to read phy register\n"); 331 return ret; 332 } 333 334 /* Read the VPHY register which has the PHY data */ 335 return ksz_read16(dev, REG_VPHY_IND_DATA__2, val); 336 } 337 338 static int lan937x_phy_read16(struct dsa_switch *ds, int addr, int reg) 339 { 340 struct ksz_device *dev = ds->priv; 341 u16 val = 0xffff; 342 int ret; 343 344 ret = lan937x_internal_phy_read(dev, addr, reg, &val); 345 if (ret) 346 return ret; 347 348 return val; 349 } 350 351 static int lan937x_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 352 { 353 struct ksz_device *dev = ds->priv; 354 int ret; 355 356 ret = lan937x_internal_phy_write(dev, addr, reg, val); 357 if (ret) 358 return ret; 359 360 return 0; 361 } 362 363 static int lan937x_reset_switch(struct ksz_device *dev) 364 { 365 u32 data32; 366 int ret; 367 368 /* reset switch */ 369 ret = lan937x_cfg(dev, REG_SW_OPERATION, SW_RESET, true); 370 if (ret < 0) 371 return ret; 372 373 /* Enable Auto Aging */ 374 ret = lan937x_cfg(dev, REG_SW_LUE_CTRL_1, SW_LINK_AUTO_AGING, true); 375 if (ret < 0) 376 return ret; 377 378 /* disable interrupts */ 379 ret = ksz_write32(dev, REG_SW_INT_MASK__4, SWITCH_INT_MASK); 380 if (ret < 0) 381 return ret; 382 383 ret = ksz_write32(dev, REG_SW_INT_STATUS__4, POR_READY_INT); 384 if (ret < 0) 385 return ret; 386 387 ret = ksz_write32(dev, REG_SW_PORT_INT_MASK__4, 0xFF); 388 if (ret < 0) 389 return ret; 390 391 return ksz_read32(dev, REG_SW_PORT_INT_STATUS__4, &data32); 392 } 393 394 static void lan937x_port_setup(struct ksz_device *dev, int port, bool cpu_port) 395 { 396 const u32 *masks = dev->info->masks; 397 const u16 *regs = dev->info->regs; 398 struct dsa_switch *ds = dev->ds; 399 u8 member; 400 401 /* enable tag tail for host port */ 402 if (cpu_port) 403 lan937x_port_cfg(dev, port, REG_PORT_CTRL_0, 404 PORT_TAIL_TAG_ENABLE, true); 405 406 /* Enable the Port Queue split */ 407 ksz9477_port_queue_split(dev, port); 408 409 /* set back pressure for half duplex */ 410 lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_1, PORT_BACK_PRESSURE, 411 true); 412 413 /* enable 802.1p priority */ 414 lan937x_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_PRIO_ENABLE, true); 415 416 if (!dev->info->internal_phy[port]) 417 lan937x_port_cfg(dev, port, regs[P_XMII_CTRL_0], 418 masks[P_MII_TX_FLOW_CTRL] | 419 masks[P_MII_RX_FLOW_CTRL], 420 true); 421 422 if (cpu_port) 423 member = dsa_user_ports(ds); 424 else 425 member = BIT(dsa_upstream_port(ds, port)); 426 427 dev->dev_ops->cfg_port_member(dev, port, member); 428 } 429 430 static int lan937x_dsa_port_setup(struct dsa_switch *ds, int port) 431 { 432 struct ksz_device *dev = ds->priv; 433 int ret; 434 435 if (!dsa_is_user_port(ds, port)) 436 return 0; 437 438 lan937x_port_setup(dev, port, false); 439 440 ret = ksz9477_set_default_prio_queue_mapping(dev, port); 441 if (ret) 442 return ret; 443 444 return ksz_dcb_init_port(dev, port); 445 } 446 447 static void lan937x_config_cpu_port(struct dsa_switch *ds) 448 { 449 struct ksz_device *dev = ds->priv; 450 struct dsa_port *dp; 451 452 dsa_switch_for_each_cpu_port(dp, ds) { 453 if (dev->info->cpu_ports & (1 << dp->index)) { 454 dev->cpu_port = dp->index; 455 456 /* enable cpu port */ 457 lan937x_port_setup(dev, dp->index, true); 458 } 459 } 460 461 dsa_switch_for_each_user_port(dp, ds) { 462 ksz_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED); 463 } 464 } 465 466 static int lan937x_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 467 { 468 struct ksz_device *dev = ds->priv; 469 int ret; 470 471 new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN; 472 473 if (dsa_is_cpu_port(ds, port)) 474 new_mtu += LAN937X_TAG_LEN; 475 476 if (new_mtu >= FR_MIN_SIZE) 477 ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, 478 PORT_JUMBO_PACKET, true); 479 else 480 ret = lan937x_port_cfg(dev, port, REG_PORT_MAC_CTRL_0, 481 PORT_JUMBO_PACKET, false); 482 if (ret < 0) { 483 dev_err(ds->dev, "failed to enable jumbo\n"); 484 return ret; 485 } 486 487 /* Write the frame size in PORT_MAX_FR_SIZE register */ 488 ret = ksz_pwrite16(dev, port, PORT_MAX_FR_SIZE, new_mtu); 489 if (ret) { 490 dev_err(ds->dev, "failed to update mtu for port %d\n", port); 491 return ret; 492 } 493 494 return 0; 495 } 496 497 static int lan937x_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 498 { 499 struct ksz_device *dev = ds->priv; 500 u8 data, mult, value8; 501 bool in_msec = false; 502 u32 max_val, value; 503 u32 secs = msecs; 504 int ret; 505 506 #define MAX_TIMER_VAL ((1 << 20) - 1) 507 508 /* The aging timer comprises a 3-bit multiplier and a 20-bit second 509 * value. Either of them cannot be zero. The maximum timer is then 510 * 7 * 1048575 = 7340025 seconds. As this value is too large for 511 * practical use it can be interpreted as microseconds, making the 512 * maximum timer 7340 seconds with finer control. This allows for 513 * maximum 122 minutes compared to 29 minutes in KSZ9477 switch. 514 */ 515 if (msecs % 1000) 516 in_msec = true; 517 else 518 secs /= 1000; 519 if (!secs) 520 secs = 1; 521 522 /* Return error if too large. */ 523 else if (secs > 7 * MAX_TIMER_VAL) 524 return -EINVAL; 525 526 /* Configure how to interpret the number value. */ 527 ret = ksz_rmw8(dev, REG_SW_LUE_CTRL_2, SW_AGE_CNT_IN_MICROSEC, 528 in_msec ? SW_AGE_CNT_IN_MICROSEC : 0); 529 if (ret < 0) 530 return ret; 531 532 ret = ksz_read8(dev, REG_SW_LUE_CTRL_0, &value8); 533 if (ret < 0) 534 return ret; 535 536 /* Check whether there is need to update the multiplier. */ 537 mult = FIELD_GET(SW_AGE_CNT_M, value8); 538 max_val = MAX_TIMER_VAL; 539 if (mult > 0) { 540 /* Try to use the same multiplier already in the register as 541 * the hardware default uses multiplier 4 and 75 seconds for 542 * 300 seconds. 543 */ 544 max_val = DIV_ROUND_UP(secs, mult); 545 if (max_val > MAX_TIMER_VAL || max_val * mult != secs) 546 max_val = MAX_TIMER_VAL; 547 } 548 549 data = DIV_ROUND_UP(secs, max_val); 550 if (mult != data) { 551 value8 &= ~SW_AGE_CNT_M; 552 value8 |= FIELD_PREP(SW_AGE_CNT_M, data); 553 ret = ksz_write8(dev, REG_SW_LUE_CTRL_0, value8); 554 if (ret < 0) 555 return ret; 556 } 557 558 secs = DIV_ROUND_UP(secs, data); 559 560 value = FIELD_GET(SW_AGE_PERIOD_7_0_M, secs); 561 562 ret = ksz_write8(dev, REG_SW_AGE_PERIOD__1, value); 563 if (ret < 0) 564 return ret; 565 566 value = FIELD_GET(SW_AGE_PERIOD_19_8_M, secs); 567 568 return ksz_write16(dev, REG_SW_AGE_PERIOD__2, value); 569 } 570 571 static void lan937x_set_tune_adj(struct ksz_device *dev, int port, 572 u16 reg, u8 val) 573 { 574 u16 data16; 575 576 ksz_pread16(dev, port, reg, &data16); 577 578 /* Update tune Adjust */ 579 data16 &= ~PORT_TUNE_ADJ; 580 data16 |= FIELD_PREP(PORT_TUNE_ADJ, val); 581 ksz_pwrite16(dev, port, reg, data16); 582 583 /* write DLL reset to take effect */ 584 data16 |= PORT_DLL_RESET; 585 ksz_pwrite16(dev, port, reg, data16); 586 } 587 588 static void lan937x_set_rgmii_tx_delay(struct ksz_device *dev, int port) 589 { 590 u8 val; 591 592 /* Apply different codes based on the ports as per characterization 593 * results 594 */ 595 val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_TX_DELAY_2NS : 596 RGMII_2_TX_DELAY_2NS; 597 598 lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_5, val); 599 } 600 601 static void lan937x_set_rgmii_rx_delay(struct ksz_device *dev, int port) 602 { 603 u8 val; 604 605 val = (port == LAN937X_RGMII_1_PORT) ? RGMII_1_RX_DELAY_2NS : 606 RGMII_2_RX_DELAY_2NS; 607 608 lan937x_set_tune_adj(dev, port, REG_PORT_XMII_CTRL_4, val); 609 } 610 611 static void lan937x_phylink_get_caps(struct dsa_switch *ds, int port, 612 struct phylink_config *config) 613 { 614 struct ksz_device *dev = ds->priv; 615 616 config->mac_capabilities = MAC_100FD; 617 618 if (dev->info->supports_rgmii[port]) { 619 /* MII/RMII/RGMII ports */ 620 config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 621 MAC_100HD | MAC_10 | MAC_1000FD; 622 } else if (is_lan937x_tx_phy(dev, port)) { 623 config->mac_capabilities |= MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 624 MAC_100HD | MAC_10; 625 } 626 627 ksz_phylink_get_caps(ds, port, config); 628 } 629 630 static void lan937x_setup_rgmii_delay(struct ksz_device *dev, int port) 631 { 632 struct ksz_port *p = &dev->ports[port]; 633 634 if (p->rgmii_tx_val) { 635 lan937x_set_rgmii_tx_delay(dev, port); 636 dev_info(dev->dev, "Applied rgmii tx delay for the port %d\n", 637 port); 638 } 639 640 if (p->rgmii_rx_val) { 641 lan937x_set_rgmii_rx_delay(dev, port); 642 dev_info(dev->dev, "Applied rgmii rx delay for the port %d\n", 643 port); 644 } 645 } 646 647 static void lan937x_phylink_mac_config(struct phylink_config *config, 648 unsigned int mode, 649 const struct phylink_link_state *state) 650 { 651 struct dsa_port *dp = dsa_phylink_to_port(config); 652 struct ksz_device *dev = dp->ds->priv; 653 int port = dp->index; 654 655 if (ksz_phylink_need_config(config, mode)) { 656 ksz_set_xmii(dev, port, state->interface); 657 lan937x_setup_rgmii_delay(dev, port); 658 } 659 } 660 661 static int lan937x_tc_cbs_set_cinc(struct ksz_device *dev, int port, u32 val) 662 { 663 return ksz_pwrite32(dev, port, REG_PORT_MTI_CREDIT_INCREMENT, val); 664 } 665 666 static int lan937x_switch_init(struct ksz_device *dev) 667 { 668 dev->port_mask = (1 << dev->info->port_cnt) - 1; 669 670 return 0; 671 } 672 673 /** 674 * lan937x_mdio_register - Register and configure the MDIO bus for the LAN937x. 675 * @dev: Pointer to the KSZ device structure. 676 * 677 * This function sets up and registers an MDIO bus for a LAN937x switch, 678 * allowing access to its internal PHYs. If the device supports side MDIO, 679 * the function will configure the external MDIO controller specified by the 680 * "mdio-parent-bus" device tree property to directly manage internal PHYs. 681 * Otherwise, SPI or I2C access is set up for PHY access. 682 * 683 * Return: 0 on success, or a negative error code on failure. 684 */ 685 static int lan937x_mdio_register(struct ksz_device *dev) 686 { 687 struct device_node *parent_bus_node; 688 struct mii_bus *parent_bus = NULL; 689 struct dsa_switch *ds = dev->ds; 690 struct device_node *mdio_np; 691 struct mii_bus *bus; 692 int ret; 693 694 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 695 if (!mdio_np) 696 return 0; 697 698 parent_bus_node = of_parse_phandle(mdio_np, "mdio-parent-bus", 0); 699 if (parent_bus_node && !dev->info->phy_side_mdio_supported) { 700 dev_err(dev->dev, "Side MDIO bus is not supported for this HW, ignoring 'mdio-parent-bus' property.\n"); 701 ret = -EINVAL; 702 703 goto put_mdio_node; 704 } else if (parent_bus_node) { 705 parent_bus = of_mdio_find_bus(parent_bus_node); 706 if (!parent_bus) { 707 ret = -EPROBE_DEFER; 708 709 goto put_mdio_node; 710 } 711 712 dev->parent_mdio_bus = parent_bus; 713 } 714 715 bus = devm_mdiobus_alloc(ds->dev); 716 if (!bus) { 717 ret = -ENOMEM; 718 goto put_mdio_node; 719 } 720 721 ret = lan937x_mdio_bus_preinit(dev, !!parent_bus); 722 if (ret) 723 goto put_mdio_node; 724 725 ret = lan937x_create_phy_addr_map(dev, !!parent_bus); 726 if (ret) 727 goto put_mdio_node; 728 729 bus->priv = dev; 730 if (parent_bus) { 731 bus->read = ksz_parent_mdio_read; 732 bus->write = ksz_parent_mdio_write; 733 bus->name = "KSZ side MDIO"; 734 snprintf(bus->id, MII_BUS_ID_SIZE, "ksz-side-mdio-%d", 735 ds->index); 736 } else { 737 bus->read = ksz_sw_mdio_read; 738 bus->write = ksz_sw_mdio_write; 739 bus->name = "ksz user smi"; 740 if (ds->dst->index != 0) 741 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d-%d", 742 ds->dst->index, ds->index); 743 else 744 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 745 } 746 747 ret = ksz_parse_dt_phy_config(dev, bus, mdio_np); 748 if (ret) 749 goto put_mdio_node; 750 751 ds->phys_mii_mask = bus->phy_mask; 752 bus->parent = ds->dev; 753 754 ds->user_mii_bus = bus; 755 756 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 757 if (ret) 758 dev_err(ds->dev, "unable to register MDIO bus %s\n", 759 bus->id); 760 761 put_mdio_node: 762 of_node_put(mdio_np); 763 of_node_put(parent_bus_node); 764 765 return ret; 766 } 767 768 static int lan937x_setup(struct dsa_switch *ds) 769 { 770 struct ksz_device *dev = ds->priv; 771 u16 storm_mask, storm_rate; 772 struct dsa_port *dp; 773 struct ksz_port *p; 774 const u16 *regs; 775 int ret; 776 777 regs = dev->info->regs; 778 779 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 780 dev->info->num_vlans, GFP_KERNEL); 781 if (!dev->vlan_cache) 782 return -ENOMEM; 783 784 ret = lan937x_reset_switch(dev); 785 if (ret) { 786 dev_err(ds->dev, "failed to reset switch\n"); 787 return ret; 788 } 789 790 ret = ksz_parse_drive_strength(dev); 791 if (ret) 792 return ret; 793 794 /* set broadcast storm protection 10% rate */ 795 storm_mask = BROADCAST_STORM_RATE; 796 storm_rate = (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100; 797 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 798 storm_mask, storm_rate); 799 800 lan937x_config_cpu_port(ds); 801 802 ksz9477_enable_stp_addr(dev); 803 804 ds->num_tx_queues = dev->info->num_tx_queues; 805 806 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 807 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 808 809 ksz_init_mib_timer(dev); 810 811 ds->configure_vlan_while_not_filtering = false; 812 ds->dscp_prio_mapping_is_global = true; 813 814 /* The VLAN aware is a global setting. Mixed vlan 815 * filterings are not supported. 816 */ 817 ds->vlan_filtering_is_global = true; 818 819 /* Enable aggressive back off for half duplex & UNH mode */ 820 ret = lan937x_cfg(dev, REG_SW_MAC_CTRL_0, (SW_PAUSE_UNH_MODE | 821 SW_NEW_BACKOFF | 822 SW_AGGR_BACKOFF), true); 823 if (ret < 0) 824 return ret; 825 826 /* If NO_EXC_COLLISION_DROP bit is set, the switch will not drop 827 * packets when 16 or more collisions occur 828 */ 829 ret = lan937x_cfg(dev, REG_SW_MAC_CTRL_1, NO_EXC_COLLISION_DROP, true); 830 if (ret < 0) 831 return ret; 832 833 /* enable global MIB counter freeze function */ 834 ret = lan937x_cfg(dev, REG_SW_MAC_CTRL_6, SW_MIB_COUNTER_FREEZE, true); 835 if (ret < 0) 836 return ret; 837 838 /* disable CLK125 & CLK25, 1: disable, 0: enable */ 839 ret = lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, 840 (SW_CLK125_ENB | SW_CLK25_ENB), true); 841 if (ret < 0) 842 return ret; 843 844 /* Disable global VPHY support. Related to CPU interface only? */ 845 ret = ksz_rmw32(dev, REG_SW_CFG_STRAP_OVR, SW_VPHY_DISABLE, 846 SW_VPHY_DISABLE); 847 if (ret < 0) 848 return ret; 849 850 /* Start with learning disabled on standalone user ports, and enabled 851 * on the CPU port. In lack of other finer mechanisms, learning on the 852 * CPU port will avoid flooding bridge local addresses on the network 853 * in some cases. 854 */ 855 p = &dev->ports[dev->cpu_port]; 856 p->learning = true; 857 858 if (dev->irq > 0) { 859 ret = ksz_girq_setup(dev); 860 if (ret) 861 return ret; 862 863 dsa_switch_for_each_user_port(dp, dev->ds) { 864 ret = ksz_pirq_setup(dev, dp->index); 865 if (ret) 866 goto port_release; 867 868 ret = ksz_ptp_irq_setup(ds, dp->index); 869 if (ret) 870 goto pirq_release; 871 } 872 } 873 874 ret = ksz_ptp_clock_register(ds); 875 if (ret) { 876 dev_err(dev->dev, "Failed to register PTP clock: %d\n", 877 ret); 878 goto port_release; 879 } 880 881 ret = lan937x_mdio_register(dev); 882 if (ret < 0) { 883 dev_err(dev->dev, "failed to register the mdio"); 884 goto out_ptp_clock_unregister; 885 } 886 887 ret = ksz_dcb_init(dev); 888 if (ret) 889 goto out_ptp_clock_unregister; 890 891 /* start switch */ 892 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 893 SW_START, SW_START); 894 895 return 0; 896 897 out_ptp_clock_unregister: 898 ksz_ptp_clock_unregister(ds); 899 port_release: 900 if (dev->irq > 0) { 901 dsa_switch_for_each_user_port_continue_reverse(dp, dev->ds) { 902 ksz_ptp_irq_free(ds, dp->index); 903 pirq_release: 904 ksz_irq_free(&dev->ports[dp->index].pirq); 905 } 906 ksz_irq_free(&dev->girq); 907 } 908 909 return ret; 910 } 911 912 static enum dsa_tag_protocol lan937x_get_tag_protocol(struct dsa_switch *ds, 913 int port, 914 enum dsa_tag_protocol mp) 915 { 916 return DSA_TAG_PROTO_LAN937X; 917 } 918 919 static int lan937x_connect_tag_protocol(struct dsa_switch *ds, 920 enum dsa_tag_protocol proto) 921 { 922 struct ksz_tagger_data *tagger_data; 923 924 if (proto != DSA_TAG_PROTO_LAN937X) 925 return -EPROTONOSUPPORT; 926 927 tagger_data = ksz_tagger_data(ds); 928 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 929 930 return 0; 931 } 932 933 const struct phylink_mac_ops lan937x_phylink_mac_ops = { 934 .mac_config = lan937x_phylink_mac_config, 935 .mac_link_down = ksz_phylink_mac_link_down, 936 .mac_link_up = ksz9477_phylink_mac_link_up, 937 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 938 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 939 }; 940 941 const struct ksz_dev_ops lan937x_dev_ops = { 942 .get_port_addr = ksz9477_get_port_addr, 943 .cfg_port_member = ksz9477_cfg_port_member, 944 .r_mib_cnt = ksz9477_r_mib_cnt, 945 .r_mib_pkt = ksz9477_r_mib_pkt, 946 .r_mib_stat64 = ksz_r_mib_stats64, 947 .freeze_mib = ksz9477_freeze_mib, 948 .port_init_cnt = ksz9477_port_init_cnt, 949 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 950 .init = lan937x_switch_init, 951 }; 952 953 const struct dsa_switch_ops lan937x_switch_ops = { 954 .get_tag_protocol = lan937x_get_tag_protocol, 955 .connect_tag_protocol = lan937x_connect_tag_protocol, 956 .setup = lan937x_setup, 957 .teardown = ksz_teardown, 958 .phy_read = lan937x_phy_read16, 959 .phy_write = lan937x_phy_write16, 960 .phylink_get_caps = lan937x_phylink_get_caps, 961 .port_setup = lan937x_dsa_port_setup, 962 .set_ageing_time = lan937x_set_ageing_time, 963 .get_strings = ksz_get_strings, 964 .get_ethtool_stats = ksz_get_ethtool_stats, 965 .get_sset_count = ksz_sset_count, 966 .port_bridge_join = ksz_port_bridge_join, 967 .port_bridge_leave = ksz_port_bridge_leave, 968 .port_set_mac_address = ksz_port_set_mac_address, 969 .port_stp_state_set = ksz_port_stp_state_set, 970 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 971 .port_bridge_flags = ksz_port_bridge_flags, 972 .port_fast_age = ksz9477_flush_dyn_mac_table, 973 .port_vlan_filtering = ksz9477_port_vlan_filtering, 974 .port_vlan_add = ksz9477_port_vlan_add, 975 .port_vlan_del = ksz9477_port_vlan_del, 976 .port_fdb_dump = ksz9477_fdb_dump, 977 .port_fdb_add = ksz9477_fdb_add, 978 .port_fdb_del = ksz9477_fdb_del, 979 .port_mdb_add = ksz9477_mdb_add, 980 .port_mdb_del = ksz9477_mdb_del, 981 .port_mirror_add = ksz9477_port_mirror_add, 982 .port_mirror_del = ksz9477_port_mirror_del, 983 .get_stats64 = ksz_get_stats64, 984 .get_pause_stats = ksz_get_pause_stats, 985 .port_change_mtu = lan937x_change_mtu, 986 .port_max_mtu = ksz_max_mtu, 987 .suspend = ksz_suspend, 988 .resume = ksz_resume, 989 .get_ts_info = ksz_get_ts_info, 990 .port_hwtstamp_get = ksz_hwtstamp_get, 991 .port_hwtstamp_set = ksz_hwtstamp_set, 992 .port_txtstamp = ksz_port_txtstamp, 993 .port_rxtstamp = ksz_port_rxtstamp, 994 .port_setup_tc = ksz_setup_tc, 995 .port_get_default_prio = ksz_port_get_default_prio, 996 .port_set_default_prio = ksz_port_set_default_prio, 997 .port_get_dscp_prio = ksz_port_get_dscp_prio, 998 .port_add_dscp_prio = ksz_port_add_dscp_prio, 999 .port_del_dscp_prio = ksz_port_del_dscp_prio, 1000 .port_get_apptrust = ksz_port_get_apptrust, 1001 .port_set_apptrust = ksz_port_set_apptrust, 1002 }; 1003 1004 MODULE_AUTHOR("Arun Ramadoss <arun.ramadoss@microchip.com>"); 1005 MODULE_DESCRIPTION("Microchip LAN937x Series Switch DSA Driver"); 1006 MODULE_LICENSE("GPL"); 1007