1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015 Microchip Technology
4 */
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/mii.h>
8 #include <linux/ethtool.h>
9 #include <linux/phy.h>
10 #include <linux/microchipphy.h>
11 #include <linux/delay.h>
12 #include <linux/of.h>
13 #include <dt-bindings/net/microchip-lan78xx.h>
14
15 #define PHY_ID_LAN937X_TX 0x0007c190
16
17 #define LAN937X_MODE_CTRL_STATUS_REG 0x11
18 #define LAN937X_AUTOMDIX_EN BIT(7)
19 #define LAN937X_MDI_MODE BIT(6)
20
21 #define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>"
22 #define DRIVER_DESC "Microchip LAN88XX/LAN937X TX PHY driver"
23
24 struct lan88xx_priv {
25 int chip_id;
26 int chip_rev;
27 __u32 wolopts;
28 };
29
lan88xx_read_page(struct phy_device * phydev)30 static int lan88xx_read_page(struct phy_device *phydev)
31 {
32 return __phy_read(phydev, LAN88XX_EXT_PAGE_ACCESS);
33 }
34
lan88xx_write_page(struct phy_device * phydev,int page)35 static int lan88xx_write_page(struct phy_device *phydev, int page)
36 {
37 return __phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, page);
38 }
39
lan88xx_phy_config_intr(struct phy_device * phydev)40 static int lan88xx_phy_config_intr(struct phy_device *phydev)
41 {
42 int rc;
43
44 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
45 /* unmask all source and clear them before enable */
46 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF);
47 rc = phy_read(phydev, LAN88XX_INT_STS);
48 rc = phy_write(phydev, LAN88XX_INT_MASK,
49 LAN88XX_INT_MASK_MDINTPIN_EN_ |
50 LAN88XX_INT_MASK_LINK_CHANGE_);
51 } else {
52 rc = phy_write(phydev, LAN88XX_INT_MASK, 0);
53 if (rc)
54 return rc;
55
56 /* Ack interrupts after they have been disabled */
57 rc = phy_read(phydev, LAN88XX_INT_STS);
58 }
59
60 return rc < 0 ? rc : 0;
61 }
62
lan88xx_handle_interrupt(struct phy_device * phydev)63 static irqreturn_t lan88xx_handle_interrupt(struct phy_device *phydev)
64 {
65 int irq_status;
66
67 irq_status = phy_read(phydev, LAN88XX_INT_STS);
68 if (irq_status < 0) {
69 phy_error(phydev);
70 return IRQ_NONE;
71 }
72
73 if (!(irq_status & LAN88XX_INT_STS_LINK_CHANGE_))
74 return IRQ_NONE;
75
76 phy_trigger_machine(phydev);
77
78 return IRQ_HANDLED;
79 }
80
lan88xx_suspend(struct phy_device * phydev)81 static int lan88xx_suspend(struct phy_device *phydev)
82 {
83 struct lan88xx_priv *priv = phydev->priv;
84
85 /* do not power down PHY when WOL is enabled */
86 if (!priv->wolopts)
87 genphy_suspend(phydev);
88
89 return 0;
90 }
91
lan88xx_TR_reg_set(struct phy_device * phydev,u16 regaddr,u32 data)92 static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr,
93 u32 data)
94 {
95 int val, save_page, ret = 0;
96 u16 buf;
97
98 /* Save current page */
99 save_page = phy_save_page(phydev);
100 if (save_page < 0) {
101 phydev_warn(phydev, "Failed to get current page\n");
102 goto err;
103 }
104
105 /* Switch to TR page */
106 lan88xx_write_page(phydev, LAN88XX_EXT_PAGE_ACCESS_TR);
107
108 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA,
109 (data & 0xFFFF));
110 if (ret < 0) {
111 phydev_warn(phydev, "Failed to write TR low data\n");
112 goto err;
113 }
114
115 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA,
116 (data & 0x00FF0000) >> 16);
117 if (ret < 0) {
118 phydev_warn(phydev, "Failed to write TR high data\n");
119 goto err;
120 }
121
122 /* Config control bits [15:13] of register */
123 buf = (regaddr & ~(0x3 << 13));/* Clr [14:13] to write data in reg */
124 buf |= 0x8000; /* Set [15] to Packet transmit */
125
126 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf);
127 if (ret < 0) {
128 phydev_warn(phydev, "Failed to write data in reg\n");
129 goto err;
130 }
131
132 usleep_range(1000, 2000);/* Wait for Data to be written */
133 val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR);
134 if (!(val & 0x8000))
135 phydev_warn(phydev, "TR Register[0x%X] configuration failed\n",
136 regaddr);
137 err:
138 return phy_restore_page(phydev, save_page, ret);
139 }
140
lan88xx_config_TR_regs(struct phy_device * phydev)141 static void lan88xx_config_TR_regs(struct phy_device *phydev)
142 {
143 int err;
144
145 /* Get access to Channel 0x1, Node 0xF , Register 0x01.
146 * Write 24-bit value 0x12B00A to register. Setting MrvlTrFix1000Kf,
147 * MrvlTrFix1000Kp, MasterEnableTR bits.
148 */
149 err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A);
150 if (err < 0)
151 phydev_warn(phydev, "Failed to Set Register[0x0F82]\n");
152
153 /* Get access to Channel b'10, Node b'1101, Register 0x06.
154 * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv,
155 * SSTrKp1000Mas bits.
156 */
157 err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F);
158 if (err < 0)
159 phydev_warn(phydev, "Failed to Set Register[0x168C]\n");
160
161 /* Get access to Channel b'10, Node b'1111, Register 0x11.
162 * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh
163 * bits
164 */
165 err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620);
166 if (err < 0)
167 phydev_warn(phydev, "Failed to Set Register[0x17A2]\n");
168
169 /* Get access to Channel b'10, Node b'1101, Register 0x10.
170 * Write 24-bit value 0xEEFFDD to register. Setting
171 * eee_TrKp1Long_1000, eee_TrKp2Long_1000, eee_TrKp3Long_1000,
172 * eee_TrKp1Short_1000,eee_TrKp2Short_1000, eee_TrKp3Short_1000 bits.
173 */
174 err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD);
175 if (err < 0)
176 phydev_warn(phydev, "Failed to Set Register[0x16A0]\n");
177
178 /* Get access to Channel b'10, Node b'1101, Register 0x13.
179 * Write 24-bit value 0x071448 to register. Setting
180 * slv_lpi_tr_tmr_val1, slv_lpi_tr_tmr_val2 bits.
181 */
182 err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448);
183 if (err < 0)
184 phydev_warn(phydev, "Failed to Set Register[0x16A6]\n");
185
186 /* Get access to Channel b'10, Node b'1101, Register 0x12.
187 * Write 24-bit value 0x13132F to register. Setting
188 * slv_sigdet_timer_val1, slv_sigdet_timer_val2 bits.
189 */
190 err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F);
191 if (err < 0)
192 phydev_warn(phydev, "Failed to Set Register[0x16A4]\n");
193
194 /* Get access to Channel b'10, Node b'1101, Register 0x14.
195 * Write 24-bit value 0x0 to register. Setting eee_3level_delay,
196 * eee_TrKf_freeze_delay bits.
197 */
198 err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0);
199 if (err < 0)
200 phydev_warn(phydev, "Failed to Set Register[0x16A8]\n");
201
202 /* Get access to Channel b'01, Node b'1111, Register 0x34.
203 * Write 24-bit value 0x91B06C to register. Setting
204 * FastMseSearchThreshLong1000, FastMseSearchThreshShort1000,
205 * FastMseSearchUpdGain1000 bits.
206 */
207 err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C);
208 if (err < 0)
209 phydev_warn(phydev, "Failed to Set Register[0x0FE8]\n");
210
211 /* Get access to Channel b'01, Node b'1111, Register 0x3E.
212 * Write 24-bit value 0xC0A028 to register. Setting
213 * FastMseKp2ThreshLong1000, FastMseKp2ThreshShort1000,
214 * FastMseKp2UpdGain1000, FastMseKp2ExitEn1000 bits.
215 */
216 err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028);
217 if (err < 0)
218 phydev_warn(phydev, "Failed to Set Register[0x0FFC]\n");
219
220 /* Get access to Channel b'01, Node b'1111, Register 0x35.
221 * Write 24-bit value 0x041600 to register. Setting
222 * FastMseSearchPhShNum1000, FastMseSearchClksPerPh1000,
223 * FastMsePhChangeDelay1000 bits.
224 */
225 err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600);
226 if (err < 0)
227 phydev_warn(phydev, "Failed to Set Register[0x0FEA]\n");
228
229 /* Get access to Channel b'10, Node b'1101, Register 0x03.
230 * Write 24-bit value 0x000004 to register. Setting TrFreeze bits.
231 */
232 err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004);
233 if (err < 0)
234 phydev_warn(phydev, "Failed to Set Register[0x1686]\n");
235 }
236
lan88xx_probe(struct phy_device * phydev)237 static int lan88xx_probe(struct phy_device *phydev)
238 {
239 struct device *dev = &phydev->mdio.dev;
240 struct lan88xx_priv *priv;
241 u32 led_modes[4];
242 int len;
243
244 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
245 if (!priv)
246 return -ENOMEM;
247
248 priv->wolopts = 0;
249
250 len = of_property_read_variable_u32_array(dev->of_node,
251 "microchip,led-modes",
252 led_modes,
253 0,
254 ARRAY_SIZE(led_modes));
255 if (len >= 0) {
256 u32 reg = 0;
257 int i;
258
259 for (i = 0; i < len; i++) {
260 if (led_modes[i] > 15)
261 return -EINVAL;
262 reg |= led_modes[i] << (i * 4);
263 }
264 for (; i < ARRAY_SIZE(led_modes); i++)
265 reg |= LAN78XX_FORCE_LED_OFF << (i * 4);
266 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg);
267 } else if (len == -EOVERFLOW) {
268 return -EINVAL;
269 }
270
271 /* these values can be used to identify internal PHY */
272 priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID);
273 priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV);
274
275 phydev->priv = priv;
276
277 return 0;
278 }
279
lan88xx_remove(struct phy_device * phydev)280 static void lan88xx_remove(struct phy_device *phydev)
281 {
282 struct device *dev = &phydev->mdio.dev;
283 struct lan88xx_priv *priv = phydev->priv;
284
285 if (priv)
286 devm_kfree(dev, priv);
287 }
288
lan88xx_set_wol(struct phy_device * phydev,struct ethtool_wolinfo * wol)289 static int lan88xx_set_wol(struct phy_device *phydev,
290 struct ethtool_wolinfo *wol)
291 {
292 struct lan88xx_priv *priv = phydev->priv;
293
294 priv->wolopts = wol->wolopts;
295
296 return 0;
297 }
298
lan88xx_set_mdix(struct phy_device * phydev)299 static void lan88xx_set_mdix(struct phy_device *phydev)
300 {
301 int buf;
302 int val;
303
304 switch (phydev->mdix_ctrl) {
305 case ETH_TP_MDI:
306 val = LAN88XX_EXT_MODE_CTRL_MDI_;
307 break;
308 case ETH_TP_MDI_X:
309 val = LAN88XX_EXT_MODE_CTRL_MDI_X_;
310 break;
311 case ETH_TP_MDI_AUTO:
312 val = LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_;
313 break;
314 default:
315 return;
316 }
317
318 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1);
319 buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
320 buf &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
321 buf |= val;
322 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf);
323 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0);
324 }
325
lan88xx_config_init(struct phy_device * phydev)326 static int lan88xx_config_init(struct phy_device *phydev)
327 {
328 int val;
329
330 /*Zerodetect delay enable */
331 val = phy_read_mmd(phydev, MDIO_MMD_PCS,
332 PHY_ARDENNES_MMD_DEV_3_PHY_CFG);
333 val |= PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_;
334
335 phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG,
336 val);
337
338 /* Config DSP registers */
339 lan88xx_config_TR_regs(phydev);
340
341 return 0;
342 }
343
lan88xx_config_aneg(struct phy_device * phydev)344 static int lan88xx_config_aneg(struct phy_device *phydev)
345 {
346 lan88xx_set_mdix(phydev);
347
348 return genphy_config_aneg(phydev);
349 }
350
lan88xx_link_change_notify(struct phy_device * phydev)351 static void lan88xx_link_change_notify(struct phy_device *phydev)
352 {
353 int temp;
354
355 /* At forced 100 F/H mode, chip may fail to set mode correctly
356 * when cable is switched between long(~50+m) and short one.
357 * As workaround, set to 10 before setting to 100
358 * at forced 100 F/H mode.
359 */
360 if (!phydev->autoneg && phydev->speed == 100) {
361 /* disable phy interrupt */
362 temp = phy_read(phydev, LAN88XX_INT_MASK);
363 temp &= ~LAN88XX_INT_MASK_MDINTPIN_EN_;
364 phy_write(phydev, LAN88XX_INT_MASK, temp);
365
366 temp = phy_read(phydev, MII_BMCR);
367 temp &= ~(BMCR_SPEED100 | BMCR_SPEED1000);
368 phy_write(phydev, MII_BMCR, temp); /* set to 10 first */
369 temp |= BMCR_SPEED100;
370 phy_write(phydev, MII_BMCR, temp); /* set to 100 later */
371
372 /* clear pending interrupt generated while workaround */
373 temp = phy_read(phydev, LAN88XX_INT_STS);
374
375 /* enable phy interrupt back */
376 temp = phy_read(phydev, LAN88XX_INT_MASK);
377 temp |= LAN88XX_INT_MASK_MDINTPIN_EN_;
378 phy_write(phydev, LAN88XX_INT_MASK, temp);
379 }
380 }
381
382 /**
383 * lan937x_tx_read_mdix_status - Read the MDIX status for the LAN937x TX PHY.
384 * @phydev: Pointer to the phy_device structure.
385 *
386 * This function reads the MDIX status of the LAN937x TX PHY and sets the
387 * mdix_ctrl and mdix fields of the phy_device structure accordingly.
388 * Note that MDIX status is not supported in AUTO mode, and will be set
389 * to invalid in such cases.
390 *
391 * Return: 0 on success, a negative error code on failure.
392 */
lan937x_tx_read_mdix_status(struct phy_device * phydev)393 static int lan937x_tx_read_mdix_status(struct phy_device *phydev)
394 {
395 int ret;
396
397 ret = phy_read(phydev, LAN937X_MODE_CTRL_STATUS_REG);
398 if (ret < 0)
399 return ret;
400
401 if (ret & LAN937X_AUTOMDIX_EN) {
402 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
403 /* MDI/MDIX status is unknown */
404 phydev->mdix = ETH_TP_MDI_INVALID;
405 } else if (ret & LAN937X_MDI_MODE) {
406 phydev->mdix_ctrl = ETH_TP_MDI_X;
407 phydev->mdix = ETH_TP_MDI_X;
408 } else {
409 phydev->mdix_ctrl = ETH_TP_MDI;
410 phydev->mdix = ETH_TP_MDI;
411 }
412
413 return 0;
414 }
415
416 /**
417 * lan937x_tx_read_status - Read the status for the LAN937x TX PHY.
418 * @phydev: Pointer to the phy_device structure.
419 *
420 * This function reads the status of the LAN937x TX PHY and updates the
421 * phy_device structure accordingly.
422 *
423 * Return: 0 on success, a negative error code on failure.
424 */
lan937x_tx_read_status(struct phy_device * phydev)425 static int lan937x_tx_read_status(struct phy_device *phydev)
426 {
427 int ret;
428
429 ret = genphy_read_status(phydev);
430 if (ret < 0)
431 return ret;
432
433 return lan937x_tx_read_mdix_status(phydev);
434 }
435
436 /**
437 * lan937x_tx_set_mdix - Set the MDIX mode for the LAN937x TX PHY.
438 * @phydev: Pointer to the phy_device structure.
439 *
440 * This function configures the MDIX mode of the LAN937x TX PHY based on the
441 * mdix_ctrl field of the phy_device structure. The MDIX mode can be set to
442 * MDI (straight-through), MDIX (crossover), or AUTO (auto-MDIX). If the mode
443 * is not recognized, it returns 0 without making any changes.
444 *
445 * Return: 0 on success, a negative error code on failure.
446 */
lan937x_tx_set_mdix(struct phy_device * phydev)447 static int lan937x_tx_set_mdix(struct phy_device *phydev)
448 {
449 u16 val;
450
451 switch (phydev->mdix_ctrl) {
452 case ETH_TP_MDI:
453 val = 0;
454 break;
455 case ETH_TP_MDI_X:
456 val = LAN937X_MDI_MODE;
457 break;
458 case ETH_TP_MDI_AUTO:
459 val = LAN937X_AUTOMDIX_EN;
460 break;
461 default:
462 return 0;
463 }
464
465 return phy_modify(phydev, LAN937X_MODE_CTRL_STATUS_REG,
466 LAN937X_AUTOMDIX_EN | LAN937X_MDI_MODE, val);
467 }
468
469 /**
470 * lan937x_tx_config_aneg - Configure auto-negotiation and fixed modes for the
471 * LAN937x TX PHY.
472 * @phydev: Pointer to the phy_device structure.
473 *
474 * This function configures the MDIX mode for the LAN937x TX PHY and then
475 * proceeds to configure the auto-negotiation or fixed mode settings
476 * based on the phy_device structure.
477 *
478 * Return: 0 on success, a negative error code on failure.
479 */
lan937x_tx_config_aneg(struct phy_device * phydev)480 static int lan937x_tx_config_aneg(struct phy_device *phydev)
481 {
482 int ret;
483
484 ret = lan937x_tx_set_mdix(phydev);
485 if (ret < 0)
486 return ret;
487
488 return genphy_config_aneg(phydev);
489 }
490
491 static struct phy_driver microchip_phy_driver[] = {
492 {
493 .phy_id = 0x0007c132,
494 /* This mask (0xfffffff2) is to differentiate from
495 * LAN8742 (phy_id 0x0007c130 and 0x0007c131)
496 * and allows future phy_id revisions.
497 */
498 .phy_id_mask = 0xfffffff2,
499 .name = "Microchip LAN88xx",
500
501 /* PHY_GBIT_FEATURES */
502
503 .probe = lan88xx_probe,
504 .remove = lan88xx_remove,
505
506 .config_init = lan88xx_config_init,
507 .config_aneg = lan88xx_config_aneg,
508 .link_change_notify = lan88xx_link_change_notify,
509
510 .config_intr = lan88xx_phy_config_intr,
511 .handle_interrupt = lan88xx_handle_interrupt,
512
513 .suspend = lan88xx_suspend,
514 .resume = genphy_resume,
515 .set_wol = lan88xx_set_wol,
516 .read_page = lan88xx_read_page,
517 .write_page = lan88xx_write_page,
518 },
519 {
520 PHY_ID_MATCH_MODEL(PHY_ID_LAN937X_TX),
521 .name = "Microchip LAN937x TX",
522 .suspend = genphy_suspend,
523 .resume = genphy_resume,
524 .config_aneg = lan937x_tx_config_aneg,
525 .read_status = lan937x_tx_read_status,
526 } };
527
528 module_phy_driver(microchip_phy_driver);
529
530 static struct mdio_device_id __maybe_unused microchip_tbl[] = {
531 { 0x0007c132, 0xfffffff2 },
532 { PHY_ID_MATCH_MODEL(PHY_ID_LAN937X_TX) },
533 { }
534 };
535
536 MODULE_DEVICE_TABLE(mdio, microchip_tbl);
537
538 MODULE_AUTHOR(DRIVER_AUTHOR);
539 MODULE_DESCRIPTION(DRIVER_DESC);
540 MODULE_LICENSE("GPL");
541