1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2022 ROHM Semiconductors
4 *
5 * ROHM/KIONIX accelerometer driver
6 */
7
8 #include <linux/cleanup.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/mutex.h>
15 #include <linux/property.h>
16 #include <linux/regmap.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/slab.h>
19 #include <linux/string_choices.h>
20 #include <linux/types.h>
21 #include <linux/units.h>
22
23 #include <linux/iio/iio.h>
24 #include <linux/iio/sysfs.h>
25 #include <linux/iio/trigger.h>
26 #include <linux/iio/trigger_consumer.h>
27 #include <linux/iio/triggered_buffer.h>
28
29 #include "kionix-kx022a.h"
30
31 /*
32 * The KX022A has FIFO which can store 43 samples of HiRes data from 2
33 * channels. This equals to 43 (samples) * 3 (channels) * 2 (bytes/sample) to
34 * 258 bytes of sample data. The quirk to know is that the amount of bytes in
35 * the FIFO is advertised via 8 bit register (max value 255). The thing to note
36 * is that full 258 bytes of data is indicated using the max value 255.
37 */
38 #define KX022A_FIFO_LENGTH 43
39 #define KX022A_FIFO_FULL_VALUE 255
40 #define KX022A_SOFT_RESET_WAIT_TIME_US (5 * USEC_PER_MSEC)
41 #define KX022A_SOFT_RESET_TOTAL_WAIT_TIME_US (500 * USEC_PER_MSEC)
42
43 /* 3 axis, 2 bytes of data for each of the axis */
44 #define KX022A_FIFO_SAMPLES_SIZE_BYTES 6
45 #define KX022A_FIFO_MAX_BYTES \
46 (KX022A_FIFO_LENGTH * KX022A_FIFO_SAMPLES_SIZE_BYTES)
47
48 enum {
49 KX022A_STATE_SAMPLE,
50 KX022A_STATE_FIFO,
51 };
52
53 /* kx022a Regmap configs */
54 static const struct regmap_range kx022a_volatile_ranges[] = {
55 {
56 .range_min = KX022A_REG_XHP_L,
57 .range_max = KX022A_REG_COTR,
58 }, {
59 .range_min = KX022A_REG_TSCP,
60 .range_max = KX022A_REG_INT_REL,
61 }, {
62 /* The reset bit will be cleared by sensor */
63 .range_min = KX022A_REG_CNTL2,
64 .range_max = KX022A_REG_CNTL2,
65 }, {
66 .range_min = KX022A_REG_BUF_STATUS_1,
67 .range_max = KX022A_REG_BUF_READ,
68 },
69 };
70
71 static const struct regmap_access_table kx022a_volatile_regs = {
72 .yes_ranges = &kx022a_volatile_ranges[0],
73 .n_yes_ranges = ARRAY_SIZE(kx022a_volatile_ranges),
74 };
75
76 static const struct regmap_range kx022a_precious_ranges[] = {
77 {
78 .range_min = KX022A_REG_INT_REL,
79 .range_max = KX022A_REG_INT_REL,
80 },
81 };
82
83 static const struct regmap_access_table kx022a_precious_regs = {
84 .yes_ranges = &kx022a_precious_ranges[0],
85 .n_yes_ranges = ARRAY_SIZE(kx022a_precious_ranges),
86 };
87
88 /*
89 * The HW does not set WHO_AM_I reg as read-only but we don't want to write it
90 * so we still include it in the read-only ranges.
91 */
92 static const struct regmap_range kx022a_read_only_ranges[] = {
93 {
94 .range_min = KX022A_REG_XHP_L,
95 .range_max = KX022A_REG_INT_REL,
96 }, {
97 .range_min = KX022A_REG_BUF_STATUS_1,
98 .range_max = KX022A_REG_BUF_STATUS_2,
99 }, {
100 .range_min = KX022A_REG_BUF_READ,
101 .range_max = KX022A_REG_BUF_READ,
102 },
103 };
104
105 static const struct regmap_access_table kx022a_ro_regs = {
106 .no_ranges = &kx022a_read_only_ranges[0],
107 .n_no_ranges = ARRAY_SIZE(kx022a_read_only_ranges),
108 };
109
110 static const struct regmap_range kx022a_write_only_ranges[] = {
111 {
112 .range_min = KX022A_REG_BTS_WUF_TH,
113 .range_max = KX022A_REG_BTS_WUF_TH,
114 }, {
115 .range_min = KX022A_REG_MAN_WAKE,
116 .range_max = KX022A_REG_MAN_WAKE,
117 }, {
118 .range_min = KX022A_REG_SELF_TEST,
119 .range_max = KX022A_REG_SELF_TEST,
120 }, {
121 .range_min = KX022A_REG_BUF_CLEAR,
122 .range_max = KX022A_REG_BUF_CLEAR,
123 },
124 };
125
126 static const struct regmap_access_table kx022a_wo_regs = {
127 .no_ranges = &kx022a_write_only_ranges[0],
128 .n_no_ranges = ARRAY_SIZE(kx022a_write_only_ranges),
129 };
130
131 static const struct regmap_range kx022a_noinc_read_ranges[] = {
132 {
133 .range_min = KX022A_REG_BUF_READ,
134 .range_max = KX022A_REG_BUF_READ,
135 },
136 };
137
138 static const struct regmap_access_table kx022a_nir_regs = {
139 .yes_ranges = &kx022a_noinc_read_ranges[0],
140 .n_yes_ranges = ARRAY_SIZE(kx022a_noinc_read_ranges),
141 };
142
143 static const struct regmap_config kx022a_regmap_config = {
144 .reg_bits = 8,
145 .val_bits = 8,
146 .volatile_table = &kx022a_volatile_regs,
147 .rd_table = &kx022a_wo_regs,
148 .wr_table = &kx022a_ro_regs,
149 .rd_noinc_table = &kx022a_nir_regs,
150 .precious_table = &kx022a_precious_regs,
151 .max_register = KX022A_MAX_REGISTER,
152 .cache_type = REGCACHE_RBTREE,
153 };
154
155 /* Regmap configs kx132 */
156 static const struct regmap_range kx132_volatile_ranges[] = {
157 {
158 .range_min = KX132_REG_XADP_L,
159 .range_max = KX132_REG_COTR,
160 }, {
161 .range_min = KX132_REG_TSCP,
162 .range_max = KX132_REG_INT_REL,
163 }, {
164 /* The reset bit will be cleared by sensor */
165 .range_min = KX132_REG_CNTL2,
166 .range_max = KX132_REG_CNTL2,
167 }, {
168 .range_min = KX132_REG_CNTL5,
169 .range_max = KX132_REG_CNTL5,
170 }, {
171 .range_min = KX132_REG_BUF_STATUS_1,
172 .range_max = KX132_REG_BUF_READ,
173 },
174 };
175
176 static const struct regmap_access_table kx132_volatile_regs = {
177 .yes_ranges = &kx132_volatile_ranges[0],
178 .n_yes_ranges = ARRAY_SIZE(kx132_volatile_ranges),
179 };
180
181 static const struct regmap_range kx132_precious_ranges[] = {
182 {
183 .range_min = KX132_REG_INT_REL,
184 .range_max = KX132_REG_INT_REL,
185 },
186 };
187
188 static const struct regmap_access_table kx132_precious_regs = {
189 .yes_ranges = &kx132_precious_ranges[0],
190 .n_yes_ranges = ARRAY_SIZE(kx132_precious_ranges),
191 };
192
193 static const struct regmap_range kx132_read_only_ranges[] = {
194 {
195 .range_min = KX132_REG_XADP_L,
196 .range_max = KX132_REG_INT_REL,
197 }, {
198 .range_min = KX132_REG_BUF_STATUS_1,
199 .range_max = KX132_REG_BUF_STATUS_2,
200 }, {
201 .range_min = KX132_REG_BUF_READ,
202 .range_max = KX132_REG_BUF_READ,
203 }, {
204 /* Kionix reserved registers: should not be written */
205 .range_min = 0x28,
206 .range_max = 0x28,
207 }, {
208 .range_min = 0x35,
209 .range_max = 0x36,
210 }, {
211 .range_min = 0x3c,
212 .range_max = 0x48,
213 }, {
214 .range_min = 0x4e,
215 .range_max = 0x5c,
216 }, {
217 .range_min = 0x77,
218 .range_max = 0x7f,
219 },
220 };
221
222 static const struct regmap_access_table kx132_ro_regs = {
223 .no_ranges = &kx132_read_only_ranges[0],
224 .n_no_ranges = ARRAY_SIZE(kx132_read_only_ranges),
225 };
226
227 static const struct regmap_range kx132_write_only_ranges[] = {
228 {
229 .range_min = KX132_REG_SELF_TEST,
230 .range_max = KX132_REG_SELF_TEST,
231 }, {
232 .range_min = KX132_REG_BUF_CLEAR,
233 .range_max = KX132_REG_BUF_CLEAR,
234 },
235 };
236
237 static const struct regmap_access_table kx132_wo_regs = {
238 .no_ranges = &kx132_write_only_ranges[0],
239 .n_no_ranges = ARRAY_SIZE(kx132_write_only_ranges),
240 };
241
242 static const struct regmap_range kx132_noinc_read_ranges[] = {
243 {
244 .range_min = KX132_REG_BUF_READ,
245 .range_max = KX132_REG_BUF_READ,
246 },
247 };
248
249 static const struct regmap_access_table kx132_nir_regs = {
250 .yes_ranges = &kx132_noinc_read_ranges[0],
251 .n_yes_ranges = ARRAY_SIZE(kx132_noinc_read_ranges),
252 };
253
254 static const struct regmap_config kx132_regmap_config = {
255 .reg_bits = 8,
256 .val_bits = 8,
257 .volatile_table = &kx132_volatile_regs,
258 .rd_table = &kx132_wo_regs,
259 .wr_table = &kx132_ro_regs,
260 .rd_noinc_table = &kx132_nir_regs,
261 .precious_table = &kx132_precious_regs,
262 .max_register = KX132_MAX_REGISTER,
263 .cache_type = REGCACHE_RBTREE,
264 };
265
266 struct kx022a_data {
267 struct regmap *regmap;
268 const struct kx022a_chip_info *chip_info;
269 struct iio_trigger *trig;
270 struct device *dev;
271 struct iio_mount_matrix orientation;
272 int64_t timestamp, old_timestamp;
273
274 int irq;
275 int inc_reg;
276 int ien_reg;
277
278 unsigned int state;
279 unsigned int odr_ns;
280
281 bool trigger_enabled;
282 /*
283 * Prevent toggling the sensor stby/active state (PC1 bit) in the
284 * middle of a configuration, or when the fifo is enabled. Also,
285 * protect the data stored/retrieved from this structure from
286 * concurrent accesses.
287 */
288 struct mutex mutex;
289 u8 watermark;
290
291 __le16 *fifo_buffer;
292
293 /* 3 x 16bit accel data + timestamp */
294 __le16 buffer[8] __aligned(IIO_DMA_MINALIGN);
295 struct {
296 __le16 channels[3];
297 aligned_s64 ts;
298 } scan;
299 };
300
301 static const struct iio_mount_matrix *
kx022a_get_mount_matrix(const struct iio_dev * idev,const struct iio_chan_spec * chan)302 kx022a_get_mount_matrix(const struct iio_dev *idev,
303 const struct iio_chan_spec *chan)
304 {
305 struct kx022a_data *data = iio_priv(idev);
306
307 return &data->orientation;
308 }
309
310 enum {
311 AXIS_X,
312 AXIS_Y,
313 AXIS_Z,
314 AXIS_MAX
315 };
316
317 static const unsigned long kx022a_scan_masks[] = {
318 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 0
319 };
320
321 static const struct iio_chan_spec_ext_info kx022a_ext_info[] = {
322 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, kx022a_get_mount_matrix),
323 { }
324 };
325
326 #define KX022A_ACCEL_CHAN(axis, reg, index) \
327 { \
328 .type = IIO_ACCEL, \
329 .modified = 1, \
330 .channel2 = IIO_MOD_##axis, \
331 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
332 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
333 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
334 .info_mask_shared_by_type_available = \
335 BIT(IIO_CHAN_INFO_SCALE) | \
336 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
337 .ext_info = kx022a_ext_info, \
338 .address = reg, \
339 .scan_index = index, \
340 .scan_type = { \
341 .sign = 's', \
342 .realbits = 16, \
343 .storagebits = 16, \
344 .endianness = IIO_LE, \
345 }, \
346 }
347
348 static const struct iio_chan_spec kx022a_channels[] = {
349 KX022A_ACCEL_CHAN(X, KX022A_REG_XOUT_L, 0),
350 KX022A_ACCEL_CHAN(Y, KX022A_REG_YOUT_L, 1),
351 KX022A_ACCEL_CHAN(Z, KX022A_REG_ZOUT_L, 2),
352 IIO_CHAN_SOFT_TIMESTAMP(3),
353 };
354
355 static const struct iio_chan_spec kx132_channels[] = {
356 KX022A_ACCEL_CHAN(X, KX132_REG_XOUT_L, 0),
357 KX022A_ACCEL_CHAN(Y, KX132_REG_YOUT_L, 1),
358 KX022A_ACCEL_CHAN(Z, KX132_REG_ZOUT_L, 2),
359 IIO_CHAN_SOFT_TIMESTAMP(3),
360 };
361
362 /*
363 * The sensor HW can support ODR up to 1600 Hz, which is beyond what most of the
364 * Linux CPUs can handle without dropping samples. Also, the low power mode is
365 * not available for higher sample rates. Thus, the driver only supports 200 Hz
366 * and slower ODRs. The slowest is 0.78 Hz.
367 */
368 static const int kx022a_accel_samp_freq_table[][2] = {
369 { 0, 780000 },
370 { 1, 563000 },
371 { 3, 125000 },
372 { 6, 250000 },
373 { 12, 500000 },
374 { 25, 0 },
375 { 50, 0 },
376 { 100, 0 },
377 { 200, 0 },
378 };
379
380 static const unsigned int kx022a_odrs[] = {
381 1282051282,
382 639795266,
383 320 * MEGA,
384 160 * MEGA,
385 80 * MEGA,
386 40 * MEGA,
387 20 * MEGA,
388 10 * MEGA,
389 5 * MEGA,
390 };
391
392 /*
393 * range is typically +-2G/4G/8G/16G, distributed over the amount of bits.
394 * The scale table can be calculated using
395 * (range / 2^bits) * g = (range / 2^bits) * 9.80665 m/s^2
396 * => KX022A uses 16 bit (HiRes mode - assume the low 8 bits are zeroed
397 * in low-power mode(?) )
398 * => +/-2G => 4 / 2^16 * 9,80665
399 * => +/-2G - 0.000598550415
400 * +/-4G - 0.00119710083
401 * +/-8G - 0.00239420166
402 * +/-16G - 0.00478840332
403 */
404 static const int kx022a_scale_table[][2] = {
405 { 0, 598550 },
406 { 0, 1197101 },
407 { 0, 2394202 },
408 { 0, 4788403 },
409 };
410
411 /* KX134ACR-LBZ ranges are (+/-) 8, 16, 32, 64 G */
412 static const int kx134acr_lbz_scale_table[][2] = {
413 { 0, 2394202 },
414 { 0, 4788403 },
415 { 0, 9576807 },
416 { 0, 19153613 },
417 };
418
kx022a_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)419 static int kx022a_read_avail(struct iio_dev *indio_dev,
420 struct iio_chan_spec const *chan,
421 const int **vals, int *type, int *length,
422 long mask)
423 {
424 struct kx022a_data *data = iio_priv(indio_dev);
425
426 switch (mask) {
427 case IIO_CHAN_INFO_SAMP_FREQ:
428 *vals = (const int *)kx022a_accel_samp_freq_table;
429 *length = ARRAY_SIZE(kx022a_accel_samp_freq_table) *
430 ARRAY_SIZE(kx022a_accel_samp_freq_table[0]);
431 *type = IIO_VAL_INT_PLUS_MICRO;
432 return IIO_AVAIL_LIST;
433 case IIO_CHAN_INFO_SCALE:
434 *vals = (const int *)data->chip_info->scale_table;
435 *length = data->chip_info->scale_table_size;
436 *type = IIO_VAL_INT_PLUS_NANO;
437 return IIO_AVAIL_LIST;
438 default:
439 return -EINVAL;
440 }
441 }
442
443 #define KX022A_DEFAULT_PERIOD_NS (20 * NSEC_PER_MSEC)
444
kx022a_reg2freq(unsigned int val,int * val1,int * val2)445 static void kx022a_reg2freq(unsigned int val, int *val1, int *val2)
446 {
447 *val1 = kx022a_accel_samp_freq_table[val & KX022A_MASK_ODR][0];
448 *val2 = kx022a_accel_samp_freq_table[val & KX022A_MASK_ODR][1];
449 }
450
kx022a_reg2scale(struct kx022a_data * data,unsigned int val,unsigned int * val1,unsigned int * val2)451 static void kx022a_reg2scale(struct kx022a_data *data, unsigned int val,
452 unsigned int *val1, unsigned int *val2)
453 {
454 val &= KX022A_MASK_GSEL;
455 val >>= KX022A_GSEL_SHIFT;
456
457 *val1 = data->chip_info->scale_table[val][0];
458 *val2 = data->chip_info->scale_table[val][1];
459 }
460
__kx022a_turn_on_off(struct kx022a_data * data,bool on)461 static int __kx022a_turn_on_off(struct kx022a_data *data, bool on)
462 {
463 int ret;
464
465 if (on)
466 ret = regmap_set_bits(data->regmap, data->chip_info->cntl,
467 KX022A_MASK_PC1);
468 else
469 ret = regmap_clear_bits(data->regmap, data->chip_info->cntl,
470 KX022A_MASK_PC1);
471 if (ret)
472 dev_err(data->dev, "Turn %s fail %d\n", str_on_off(on), ret);
473
474 return ret;
475 }
476
kx022a_turn_off_lock(struct kx022a_data * data)477 static int kx022a_turn_off_lock(struct kx022a_data *data)
478 {
479 int ret;
480
481 mutex_lock(&data->mutex);
482 ret = __kx022a_turn_on_off(data, false);
483 if (ret)
484 mutex_unlock(&data->mutex);
485
486 return ret;
487 }
488
kx022a_turn_on_unlock(struct kx022a_data * data)489 static int kx022a_turn_on_unlock(struct kx022a_data *data)
490 {
491 int ret;
492
493 ret = __kx022a_turn_on_off(data, true);
494 mutex_unlock(&data->mutex);
495
496 return ret;
497 }
498
kx022a_write_raw_get_fmt(struct iio_dev * idev,struct iio_chan_spec const * chan,long mask)499 static int kx022a_write_raw_get_fmt(struct iio_dev *idev,
500 struct iio_chan_spec const *chan,
501 long mask)
502 {
503 switch (mask) {
504 case IIO_CHAN_INFO_SCALE:
505 return IIO_VAL_INT_PLUS_NANO;
506 case IIO_CHAN_INFO_SAMP_FREQ:
507 return IIO_VAL_INT_PLUS_MICRO;
508 default:
509 return -EINVAL;
510 }
511 }
512
kx022a_write_raw(struct iio_dev * idev,struct iio_chan_spec const * chan,int val,int val2,long mask)513 static int kx022a_write_raw(struct iio_dev *idev,
514 struct iio_chan_spec const *chan,
515 int val, int val2, long mask)
516 {
517 struct kx022a_data *data = iio_priv(idev);
518 int ret, n;
519
520 /*
521 * We should not allow changing scale or frequency when FIFO is running
522 * as it will mess the timestamp/scale for samples existing in the
523 * buffer. If this turns out to be an issue we can later change logic
524 * to internally flush the fifo before reconfiguring so the samples in
525 * fifo keep matching the freq/scale settings. (Such setup could cause
526 * issues if users trust the watermark to be reached within known
527 * time-limit).
528 */
529 ret = iio_device_claim_direct_mode(idev);
530 if (ret)
531 return ret;
532
533 switch (mask) {
534 case IIO_CHAN_INFO_SAMP_FREQ:
535 n = ARRAY_SIZE(kx022a_accel_samp_freq_table);
536
537 while (n--)
538 if (val == kx022a_accel_samp_freq_table[n][0] &&
539 val2 == kx022a_accel_samp_freq_table[n][1])
540 break;
541 if (n < 0) {
542 ret = -EINVAL;
543 goto unlock_out;
544 }
545 ret = kx022a_turn_off_lock(data);
546 if (ret)
547 break;
548
549 ret = regmap_update_bits(data->regmap,
550 data->chip_info->odcntl,
551 KX022A_MASK_ODR, n);
552 data->odr_ns = kx022a_odrs[n];
553 kx022a_turn_on_unlock(data);
554 break;
555 case IIO_CHAN_INFO_SCALE:
556 n = data->chip_info->scale_table_size / 2;
557
558 while (n-- > 0)
559 if (val == data->chip_info->scale_table[n][0] &&
560 val2 == data->chip_info->scale_table[n][1])
561 break;
562 if (n < 0) {
563 ret = -EINVAL;
564 goto unlock_out;
565 }
566
567 ret = kx022a_turn_off_lock(data);
568 if (ret)
569 break;
570
571 ret = regmap_update_bits(data->regmap, data->chip_info->cntl,
572 KX022A_MASK_GSEL,
573 n << KX022A_GSEL_SHIFT);
574 kx022a_turn_on_unlock(data);
575 break;
576 default:
577 ret = -EINVAL;
578 break;
579 }
580
581 unlock_out:
582 iio_device_release_direct_mode(idev);
583
584 return ret;
585 }
586
kx022a_fifo_set_wmi(struct kx022a_data * data)587 static int kx022a_fifo_set_wmi(struct kx022a_data *data)
588 {
589 u8 threshold;
590
591 threshold = data->watermark;
592
593 return regmap_update_bits(data->regmap, data->chip_info->buf_cntl1,
594 KX022A_MASK_WM_TH, threshold);
595 }
596
kx022a_get_axis(struct kx022a_data * data,struct iio_chan_spec const * chan,int * val)597 static int kx022a_get_axis(struct kx022a_data *data,
598 struct iio_chan_spec const *chan,
599 int *val)
600 {
601 int ret;
602
603 ret = regmap_bulk_read(data->regmap, chan->address, &data->buffer[0],
604 sizeof(__le16));
605 if (ret)
606 return ret;
607
608 *val = (s16)le16_to_cpu(data->buffer[0]);
609
610 return IIO_VAL_INT;
611 }
612
kx022a_read_raw(struct iio_dev * idev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)613 static int kx022a_read_raw(struct iio_dev *idev,
614 struct iio_chan_spec const *chan,
615 int *val, int *val2, long mask)
616 {
617 struct kx022a_data *data = iio_priv(idev);
618 unsigned int regval;
619 int ret;
620
621 switch (mask) {
622 case IIO_CHAN_INFO_RAW:
623 ret = iio_device_claim_direct_mode(idev);
624 if (ret)
625 return ret;
626
627 mutex_lock(&data->mutex);
628 ret = kx022a_get_axis(data, chan, val);
629 mutex_unlock(&data->mutex);
630
631 iio_device_release_direct_mode(idev);
632
633 return ret;
634
635 case IIO_CHAN_INFO_SAMP_FREQ:
636 ret = regmap_read(data->regmap, data->chip_info->odcntl, ®val);
637 if (ret)
638 return ret;
639
640 if ((regval & KX022A_MASK_ODR) >
641 ARRAY_SIZE(kx022a_accel_samp_freq_table)) {
642 dev_err(data->dev, "Invalid ODR\n");
643 return -EINVAL;
644 }
645
646 kx022a_reg2freq(regval, val, val2);
647
648 return IIO_VAL_INT_PLUS_MICRO;
649
650 case IIO_CHAN_INFO_SCALE:
651 ret = regmap_read(data->regmap, data->chip_info->cntl, ®val);
652 if (ret < 0)
653 return ret;
654
655 kx022a_reg2scale(data, regval, val, val2);
656
657 return IIO_VAL_INT_PLUS_NANO;
658 }
659
660 return -EINVAL;
661 };
662
kx022a_set_watermark(struct iio_dev * idev,unsigned int val)663 static int kx022a_set_watermark(struct iio_dev *idev, unsigned int val)
664 {
665 struct kx022a_data *data = iio_priv(idev);
666
667 val = min(data->chip_info->fifo_length, val);
668
669 mutex_lock(&data->mutex);
670 data->watermark = val;
671 mutex_unlock(&data->mutex);
672
673 return 0;
674 }
675
hwfifo_enabled_show(struct device * dev,struct device_attribute * attr,char * buf)676 static ssize_t hwfifo_enabled_show(struct device *dev,
677 struct device_attribute *attr,
678 char *buf)
679 {
680 struct iio_dev *idev = dev_to_iio_dev(dev);
681 struct kx022a_data *data = iio_priv(idev);
682 bool state;
683
684 mutex_lock(&data->mutex);
685 state = data->state;
686 mutex_unlock(&data->mutex);
687
688 return sysfs_emit(buf, "%d\n", state);
689 }
690
hwfifo_watermark_show(struct device * dev,struct device_attribute * attr,char * buf)691 static ssize_t hwfifo_watermark_show(struct device *dev,
692 struct device_attribute *attr,
693 char *buf)
694 {
695 struct iio_dev *idev = dev_to_iio_dev(dev);
696 struct kx022a_data *data = iio_priv(idev);
697 int wm;
698
699 mutex_lock(&data->mutex);
700 wm = data->watermark;
701 mutex_unlock(&data->mutex);
702
703 return sysfs_emit(buf, "%d\n", wm);
704 }
705
706 static IIO_DEVICE_ATTR_RO(hwfifo_enabled, 0);
707 static IIO_DEVICE_ATTR_RO(hwfifo_watermark, 0);
708
709 static const struct iio_dev_attr *kx022a_fifo_attributes[] = {
710 &iio_dev_attr_hwfifo_watermark,
711 &iio_dev_attr_hwfifo_enabled,
712 NULL
713 };
714
kx022a_drop_fifo_contents(struct kx022a_data * data)715 static int kx022a_drop_fifo_contents(struct kx022a_data *data)
716 {
717 /*
718 * We must clear the old time-stamp to avoid computing the timestamps
719 * based on samples acquired when buffer was last enabled.
720 *
721 * We don't need to protect the timestamp as long as we are only
722 * called from fifo-disable where we can guarantee the sensor is not
723 * triggering interrupts and where the mutex is locked to prevent the
724 * user-space access.
725 */
726 data->timestamp = 0;
727
728 return regmap_write(data->regmap, data->chip_info->buf_clear, 0x0);
729 }
730
kx022a_get_fifo_bytes_available(struct kx022a_data * data)731 static int kx022a_get_fifo_bytes_available(struct kx022a_data *data)
732 {
733 int ret, fifo_bytes;
734
735 ret = regmap_read(data->regmap, KX022A_REG_BUF_STATUS_1, &fifo_bytes);
736 if (ret) {
737 dev_err(data->dev, "Error reading buffer status\n");
738 return ret;
739 }
740
741 if (fifo_bytes == KX022A_FIFO_FULL_VALUE)
742 return KX022A_FIFO_MAX_BYTES;
743
744 return fifo_bytes;
745 }
746
kx132_get_fifo_bytes_available(struct kx022a_data * data)747 static int kx132_get_fifo_bytes_available(struct kx022a_data *data)
748 {
749 __le16 buf_status;
750 int ret, fifo_bytes;
751
752 ret = regmap_bulk_read(data->regmap, data->chip_info->buf_status1,
753 &buf_status, sizeof(buf_status));
754 if (ret) {
755 dev_err(data->dev, "Error reading buffer status\n");
756 return ret;
757 }
758
759 fifo_bytes = le16_to_cpu(buf_status);
760 fifo_bytes &= data->chip_info->buf_smp_lvl_mask;
761 fifo_bytes = min((unsigned int)fifo_bytes, data->chip_info->fifo_length *
762 KX022A_FIFO_SAMPLES_SIZE_BYTES);
763
764 return fifo_bytes;
765 }
766
__kx022a_fifo_flush(struct iio_dev * idev,unsigned int samples,bool irq)767 static int __kx022a_fifo_flush(struct iio_dev *idev, unsigned int samples,
768 bool irq)
769 {
770 struct kx022a_data *data = iio_priv(idev);
771 uint64_t sample_period;
772 int count, fifo_bytes;
773 bool renable = false;
774 int64_t tstamp;
775 int ret, i;
776
777 fifo_bytes = data->chip_info->get_fifo_bytes_available(data);
778
779 if (fifo_bytes % KX022A_FIFO_SAMPLES_SIZE_BYTES)
780 dev_warn(data->dev, "Bad FIFO alignment. Data may be corrupt\n");
781
782 count = fifo_bytes / KX022A_FIFO_SAMPLES_SIZE_BYTES;
783 if (!count)
784 return 0;
785
786 /*
787 * If we are being called from IRQ handler we know the stored timestamp
788 * is fairly accurate for the last stored sample. Otherwise, if we are
789 * called as a result of a read operation from userspace and hence
790 * before the watermark interrupt was triggered, take a timestamp
791 * now. We can fall anywhere in between two samples so the error in this
792 * case is at most one sample period.
793 */
794 if (!irq) {
795 /*
796 * We need to have the IRQ disabled or we risk of messing-up
797 * the timestamps. If we are ran from IRQ, then the
798 * IRQF_ONESHOT has us covered - but if we are ran by the
799 * user-space read we need to disable the IRQ to be on a safe
800 * side. We do this usng synchronous disable so that if the
801 * IRQ thread is being ran on other CPU we wait for it to be
802 * finished.
803 */
804 disable_irq(data->irq);
805 renable = true;
806
807 data->old_timestamp = data->timestamp;
808 data->timestamp = iio_get_time_ns(idev);
809 }
810
811 /*
812 * Approximate timestamps for each of the sample based on the sampling
813 * frequency, timestamp for last sample and number of samples.
814 *
815 * We'd better not use the current bandwidth settings to compute the
816 * sample period. The real sample rate varies with the device and
817 * small variation adds when we store a large number of samples.
818 *
819 * To avoid this issue we compute the actual sample period ourselves
820 * based on the timestamp delta between the last two flush operations.
821 */
822 if (data->old_timestamp) {
823 sample_period = data->timestamp - data->old_timestamp;
824 do_div(sample_period, count);
825 } else {
826 sample_period = data->odr_ns;
827 }
828 tstamp = data->timestamp - (count - 1) * sample_period;
829
830 if (samples && count > samples) {
831 /*
832 * Here we leave some old samples to the buffer. We need to
833 * adjust the timestamp to match the first sample in the buffer
834 * or we will miscalculate the sample_period at next round.
835 */
836 data->timestamp -= (count - samples) * sample_period;
837 count = samples;
838 }
839
840 fifo_bytes = count * KX022A_FIFO_SAMPLES_SIZE_BYTES;
841 ret = regmap_noinc_read(data->regmap, data->chip_info->buf_read,
842 data->fifo_buffer, fifo_bytes);
843 if (ret)
844 goto renable_out;
845
846 for (i = 0; i < count; i++) {
847 __le16 *sam = &data->fifo_buffer[i * 3];
848 __le16 *chs;
849 int bit;
850
851 chs = &data->scan.channels[0];
852 for_each_set_bit(bit, idev->active_scan_mask, AXIS_MAX)
853 chs[bit] = sam[bit];
854
855 iio_push_to_buffers_with_timestamp(idev, &data->scan, tstamp);
856
857 tstamp += sample_period;
858 }
859
860 ret = count;
861
862 renable_out:
863 if (renable)
864 enable_irq(data->irq);
865
866 return ret;
867 }
868
kx022a_fifo_flush(struct iio_dev * idev,unsigned int samples)869 static int kx022a_fifo_flush(struct iio_dev *idev, unsigned int samples)
870 {
871 struct kx022a_data *data = iio_priv(idev);
872 int ret;
873
874 mutex_lock(&data->mutex);
875 ret = __kx022a_fifo_flush(idev, samples, false);
876 mutex_unlock(&data->mutex);
877
878 return ret;
879 }
880
881 static const struct iio_info kx022a_info = {
882 .read_raw = &kx022a_read_raw,
883 .write_raw = &kx022a_write_raw,
884 .write_raw_get_fmt = &kx022a_write_raw_get_fmt,
885 .read_avail = &kx022a_read_avail,
886
887 .validate_trigger = iio_validate_own_trigger,
888 .hwfifo_set_watermark = kx022a_set_watermark,
889 .hwfifo_flush_to_buffer = kx022a_fifo_flush,
890 };
891
kx022a_set_drdy_irq(struct kx022a_data * data,bool en)892 static int kx022a_set_drdy_irq(struct kx022a_data *data, bool en)
893 {
894 if (en)
895 return regmap_set_bits(data->regmap, data->chip_info->cntl,
896 KX022A_MASK_DRDY);
897
898 return regmap_clear_bits(data->regmap, data->chip_info->cntl,
899 KX022A_MASK_DRDY);
900 }
901
kx022a_prepare_irq_pin(struct kx022a_data * data)902 static int kx022a_prepare_irq_pin(struct kx022a_data *data)
903 {
904 /* Enable IRQ1 pin. Set polarity to active low */
905 int mask = KX022A_MASK_IEN | KX022A_MASK_IPOL |
906 KX022A_MASK_ITYP;
907 int val = KX022A_MASK_IEN | KX022A_IPOL_LOW |
908 KX022A_ITYP_LEVEL;
909 int ret;
910
911 ret = regmap_update_bits(data->regmap, data->inc_reg, mask, val);
912 if (ret)
913 return ret;
914
915 /* We enable WMI to IRQ pin only at buffer_enable */
916 mask = KX022A_MASK_INS2_DRDY;
917
918 return regmap_set_bits(data->regmap, data->ien_reg, mask);
919 }
920
kx022a_fifo_disable(struct kx022a_data * data)921 static int kx022a_fifo_disable(struct kx022a_data *data)
922 {
923 int ret = 0;
924
925 guard(mutex)(&data->mutex);
926 ret = __kx022a_turn_on_off(data, false);
927 if (ret)
928 return ret;
929
930 ret = regmap_clear_bits(data->regmap, data->ien_reg, KX022A_MASK_WMI);
931 if (ret)
932 return ret;
933
934 ret = regmap_clear_bits(data->regmap, data->chip_info->buf_cntl2,
935 KX022A_MASK_BUF_EN);
936 if (ret)
937 return ret;
938
939 data->state &= ~KX022A_STATE_FIFO;
940
941 kx022a_drop_fifo_contents(data);
942
943 kfree(data->fifo_buffer);
944
945 return __kx022a_turn_on_off(data, true);
946 }
947
kx022a_buffer_predisable(struct iio_dev * idev)948 static int kx022a_buffer_predisable(struct iio_dev *idev)
949 {
950 struct kx022a_data *data = iio_priv(idev);
951
952 if (iio_device_get_current_mode(idev) == INDIO_BUFFER_TRIGGERED)
953 return 0;
954
955 return kx022a_fifo_disable(data);
956 }
957
kx022a_fifo_enable(struct kx022a_data * data)958 static int kx022a_fifo_enable(struct kx022a_data *data)
959 {
960 int ret;
961
962 data->fifo_buffer = kmalloc_array(data->chip_info->fifo_length,
963 KX022A_FIFO_SAMPLES_SIZE_BYTES,
964 GFP_KERNEL);
965 if (!data->fifo_buffer)
966 return -ENOMEM;
967
968 guard(mutex)(&data->mutex);
969 ret = __kx022a_turn_on_off(data, false);
970 if (ret)
971 return ret;
972
973 /* Update watermark to HW */
974 ret = kx022a_fifo_set_wmi(data);
975 if (ret)
976 return ret;
977
978 /* Enable buffer */
979 ret = regmap_set_bits(data->regmap, data->chip_info->buf_cntl2,
980 KX022A_MASK_BUF_EN);
981 if (ret)
982 return ret;
983
984 data->state |= KX022A_STATE_FIFO;
985 ret = regmap_set_bits(data->regmap, data->ien_reg,
986 KX022A_MASK_WMI);
987 if (ret)
988 return ret;
989
990 return __kx022a_turn_on_off(data, true);
991 }
992
kx022a_buffer_postenable(struct iio_dev * idev)993 static int kx022a_buffer_postenable(struct iio_dev *idev)
994 {
995 struct kx022a_data *data = iio_priv(idev);
996
997 /*
998 * If we use data-ready trigger, then the IRQ masks should be handled by
999 * trigger enable and the hardware buffer is not used but we just update
1000 * results to the IIO fifo when data-ready triggers.
1001 */
1002 if (iio_device_get_current_mode(idev) == INDIO_BUFFER_TRIGGERED)
1003 return 0;
1004
1005 return kx022a_fifo_enable(data);
1006 }
1007
1008 static const struct iio_buffer_setup_ops kx022a_buffer_ops = {
1009 .postenable = kx022a_buffer_postenable,
1010 .predisable = kx022a_buffer_predisable,
1011 };
1012
kx022a_trigger_handler(int irq,void * p)1013 static irqreturn_t kx022a_trigger_handler(int irq, void *p)
1014 {
1015 struct iio_poll_func *pf = p;
1016 struct iio_dev *idev = pf->indio_dev;
1017 struct kx022a_data *data = iio_priv(idev);
1018 int ret;
1019
1020 ret = regmap_bulk_read(data->regmap, data->chip_info->xout_l, data->buffer,
1021 KX022A_FIFO_SAMPLES_SIZE_BYTES);
1022 if (ret < 0)
1023 goto err_read;
1024
1025 iio_push_to_buffers_with_timestamp(idev, data->buffer, data->timestamp);
1026 err_read:
1027 iio_trigger_notify_done(idev->trig);
1028
1029 return IRQ_HANDLED;
1030 }
1031
1032 /* Get timestamps and wake the thread if we need to read data */
kx022a_irq_handler(int irq,void * private)1033 static irqreturn_t kx022a_irq_handler(int irq, void *private)
1034 {
1035 struct iio_dev *idev = private;
1036 struct kx022a_data *data = iio_priv(idev);
1037
1038 data->old_timestamp = data->timestamp;
1039 data->timestamp = iio_get_time_ns(idev);
1040
1041 if (data->state & KX022A_STATE_FIFO || data->trigger_enabled)
1042 return IRQ_WAKE_THREAD;
1043
1044 return IRQ_NONE;
1045 }
1046
1047 /*
1048 * WMI and data-ready IRQs are acked when results are read. If we add
1049 * TILT/WAKE or other IRQs - then we may need to implement the acking
1050 * (which is racy).
1051 */
kx022a_irq_thread_handler(int irq,void * private)1052 static irqreturn_t kx022a_irq_thread_handler(int irq, void *private)
1053 {
1054 struct iio_dev *idev = private;
1055 struct kx022a_data *data = iio_priv(idev);
1056 irqreturn_t ret = IRQ_NONE;
1057
1058 guard(mutex)(&data->mutex);
1059
1060 if (data->trigger_enabled) {
1061 iio_trigger_poll_nested(data->trig);
1062 ret = IRQ_HANDLED;
1063 }
1064
1065 if (data->state & KX022A_STATE_FIFO) {
1066 int ok;
1067
1068 ok = __kx022a_fifo_flush(idev, data->chip_info->fifo_length, true);
1069 if (ok > 0)
1070 ret = IRQ_HANDLED;
1071 }
1072
1073 return ret;
1074 }
1075
kx022a_trigger_set_state(struct iio_trigger * trig,bool state)1076 static int kx022a_trigger_set_state(struct iio_trigger *trig,
1077 bool state)
1078 {
1079 struct kx022a_data *data = iio_trigger_get_drvdata(trig);
1080 int ret = 0;
1081
1082 guard(mutex)(&data->mutex);
1083
1084 if (data->trigger_enabled == state)
1085 return 0;
1086
1087 if (data->state & KX022A_STATE_FIFO) {
1088 dev_warn(data->dev, "Can't set trigger when FIFO enabled\n");
1089 return -EBUSY;
1090 }
1091
1092 ret = __kx022a_turn_on_off(data, false);
1093 if (ret)
1094 return ret;
1095
1096 data->trigger_enabled = state;
1097 ret = kx022a_set_drdy_irq(data, state);
1098 if (ret)
1099 return ret;
1100
1101 return __kx022a_turn_on_off(data, true);
1102 }
1103
1104 static const struct iio_trigger_ops kx022a_trigger_ops = {
1105 .set_trigger_state = kx022a_trigger_set_state,
1106 };
1107
kx022a_chip_init(struct kx022a_data * data)1108 static int kx022a_chip_init(struct kx022a_data *data)
1109 {
1110 int ret, val;
1111
1112 /* Reset the senor */
1113 ret = regmap_write(data->regmap, data->chip_info->cntl2, KX022A_MASK_SRST);
1114 if (ret)
1115 return ret;
1116
1117 /*
1118 * According to the power-on procedure documents, there is (at least)
1119 * 2ms delay required after the software reset. This should be same for
1120 * all, KX022ACR-Z, KX132-1211, KX132ACR-LBZ and KX134ACR-LBZ.
1121 *
1122 * https://fscdn.rohm.com/kionix/en/document/AN010_KX022ACR-Z_Power-on_Procedure_E.pdf
1123 * https://fscdn.rohm.com/kionix/en/document/TN027-Power-On-Procedure.pdf
1124 * https://fscdn.rohm.com/kionix/en/document/AN011_KX134ACR-LBZ_Power-on_Procedure_E.pdf
1125 */
1126 msleep(2);
1127
1128 ret = regmap_read_poll_timeout(data->regmap, data->chip_info->cntl2, val,
1129 !(val & KX022A_MASK_SRST),
1130 KX022A_SOFT_RESET_WAIT_TIME_US,
1131 KX022A_SOFT_RESET_TOTAL_WAIT_TIME_US);
1132 if (ret) {
1133 dev_err(data->dev, "Sensor reset %s\n",
1134 val & KX022A_MASK_SRST ? "timeout" : "fail#");
1135 return ret;
1136 }
1137
1138 ret = regmap_reinit_cache(data->regmap, data->chip_info->regmap_config);
1139 if (ret) {
1140 dev_err(data->dev, "Failed to reinit reg cache\n");
1141 return ret;
1142 }
1143
1144 /* set data res 16bit */
1145 ret = regmap_set_bits(data->regmap, data->chip_info->buf_cntl2,
1146 KX022A_MASK_BRES16);
1147 if (ret) {
1148 dev_err(data->dev, "Failed to set data resolution\n");
1149 return ret;
1150 }
1151
1152 return kx022a_prepare_irq_pin(data);
1153 }
1154
1155 const struct kx022a_chip_info kx022a_chip_info = {
1156 .name = "kx022-accel",
1157 .regmap_config = &kx022a_regmap_config,
1158 .channels = kx022a_channels,
1159 .num_channels = ARRAY_SIZE(kx022a_channels),
1160 .scale_table = kx022a_scale_table,
1161 .scale_table_size = ARRAY_SIZE(kx022a_scale_table) *
1162 ARRAY_SIZE(kx022a_scale_table[0]),
1163 .fifo_length = KX022A_FIFO_LENGTH,
1164 .who = KX022A_REG_WHO,
1165 .id = KX022A_ID,
1166 .cntl = KX022A_REG_CNTL,
1167 .cntl2 = KX022A_REG_CNTL2,
1168 .odcntl = KX022A_REG_ODCNTL,
1169 .buf_cntl1 = KX022A_REG_BUF_CNTL1,
1170 .buf_cntl2 = KX022A_REG_BUF_CNTL2,
1171 .buf_clear = KX022A_REG_BUF_CLEAR,
1172 .buf_status1 = KX022A_REG_BUF_STATUS_1,
1173 .buf_read = KX022A_REG_BUF_READ,
1174 .inc1 = KX022A_REG_INC1,
1175 .inc4 = KX022A_REG_INC4,
1176 .inc5 = KX022A_REG_INC5,
1177 .inc6 = KX022A_REG_INC6,
1178 .xout_l = KX022A_REG_XOUT_L,
1179 .get_fifo_bytes_available = kx022a_get_fifo_bytes_available,
1180 };
1181 EXPORT_SYMBOL_NS_GPL(kx022a_chip_info, "IIO_KX022A");
1182
1183 const struct kx022a_chip_info kx132_chip_info = {
1184 .name = "kx132-1211",
1185 .regmap_config = &kx132_regmap_config,
1186 .channels = kx132_channels,
1187 .num_channels = ARRAY_SIZE(kx132_channels),
1188 .scale_table = kx022a_scale_table,
1189 .scale_table_size = ARRAY_SIZE(kx022a_scale_table) *
1190 ARRAY_SIZE(kx022a_scale_table[0]),
1191 .fifo_length = KX132_FIFO_LENGTH,
1192 .who = KX132_REG_WHO,
1193 .id = KX132_ID,
1194 .cntl = KX132_REG_CNTL,
1195 .cntl2 = KX132_REG_CNTL2,
1196 .odcntl = KX132_REG_ODCNTL,
1197 .buf_cntl1 = KX132_REG_BUF_CNTL1,
1198 .buf_cntl2 = KX132_REG_BUF_CNTL2,
1199 .buf_clear = KX132_REG_BUF_CLEAR,
1200 .buf_status1 = KX132_REG_BUF_STATUS_1,
1201 .buf_smp_lvl_mask = KX132_MASK_BUF_SMP_LVL,
1202 .buf_read = KX132_REG_BUF_READ,
1203 .inc1 = KX132_REG_INC1,
1204 .inc4 = KX132_REG_INC4,
1205 .inc5 = KX132_REG_INC5,
1206 .inc6 = KX132_REG_INC6,
1207 .xout_l = KX132_REG_XOUT_L,
1208 .get_fifo_bytes_available = kx132_get_fifo_bytes_available,
1209 };
1210 EXPORT_SYMBOL_NS_GPL(kx132_chip_info, "IIO_KX022A");
1211
1212 const struct kx022a_chip_info kx134_chip_info = {
1213 .name = "kx134-1211",
1214 .regmap_config = &kx132_regmap_config,
1215 .channels = kx132_channels,
1216 .num_channels = ARRAY_SIZE(kx132_channels),
1217 .scale_table = kx134acr_lbz_scale_table,
1218 .scale_table_size = ARRAY_SIZE(kx134acr_lbz_scale_table) *
1219 ARRAY_SIZE(kx134acr_lbz_scale_table[0]),
1220 .fifo_length = KX132_FIFO_LENGTH,
1221 .who = KX132_REG_WHO,
1222 .id = KX134_1211_ID,
1223 .cntl = KX132_REG_CNTL,
1224 .cntl2 = KX132_REG_CNTL2,
1225 .odcntl = KX132_REG_ODCNTL,
1226 .buf_cntl1 = KX132_REG_BUF_CNTL1,
1227 .buf_cntl2 = KX132_REG_BUF_CNTL2,
1228 .buf_clear = KX132_REG_BUF_CLEAR,
1229 .buf_status1 = KX132_REG_BUF_STATUS_1,
1230 .buf_smp_lvl_mask = KX132_MASK_BUF_SMP_LVL,
1231 .buf_read = KX132_REG_BUF_READ,
1232 .inc1 = KX132_REG_INC1,
1233 .inc4 = KX132_REG_INC4,
1234 .inc5 = KX132_REG_INC5,
1235 .inc6 = KX132_REG_INC6,
1236 .xout_l = KX132_REG_XOUT_L,
1237 .get_fifo_bytes_available = kx132_get_fifo_bytes_available,
1238 };
1239 EXPORT_SYMBOL_NS_GPL(kx134_chip_info, "IIO_KX022A");
1240
1241 /*
1242 * Despite the naming, KX132ACR-LBZ is not similar to KX132-1211 but it is
1243 * exact subset of KX022A. KX132ACR-LBZ is meant to be used for industrial
1244 * applications and the tap/double tap, free fall and tilt engines were
1245 * removed. Rest of the registers and functionalities (excluding the ID
1246 * register) are exact match to what is found in KX022.
1247 */
1248 const struct kx022a_chip_info kx132acr_chip_info = {
1249 .name = "kx132acr-lbz",
1250 .regmap_config = &kx022a_regmap_config,
1251 .channels = kx022a_channels,
1252 .num_channels = ARRAY_SIZE(kx022a_channels),
1253 .scale_table = kx022a_scale_table,
1254 .scale_table_size = ARRAY_SIZE(kx022a_scale_table) *
1255 ARRAY_SIZE(kx022a_scale_table[0]),
1256 .fifo_length = KX022A_FIFO_LENGTH,
1257 .who = KX022A_REG_WHO,
1258 .id = KX132ACR_LBZ_ID,
1259 .cntl = KX022A_REG_CNTL,
1260 .cntl2 = KX022A_REG_CNTL2,
1261 .odcntl = KX022A_REG_ODCNTL,
1262 .buf_cntl1 = KX022A_REG_BUF_CNTL1,
1263 .buf_cntl2 = KX022A_REG_BUF_CNTL2,
1264 .buf_clear = KX022A_REG_BUF_CLEAR,
1265 .buf_status1 = KX022A_REG_BUF_STATUS_1,
1266 .buf_read = KX022A_REG_BUF_READ,
1267 .inc1 = KX022A_REG_INC1,
1268 .inc4 = KX022A_REG_INC4,
1269 .inc5 = KX022A_REG_INC5,
1270 .inc6 = KX022A_REG_INC6,
1271 .xout_l = KX022A_REG_XOUT_L,
1272 .get_fifo_bytes_available = kx022a_get_fifo_bytes_available,
1273 };
1274 EXPORT_SYMBOL_NS_GPL(kx132acr_chip_info, "IIO_KX022A");
1275
1276 const struct kx022a_chip_info kx134acr_chip_info = {
1277 .name = "kx134acr-lbz",
1278 .regmap_config = &kx022a_regmap_config,
1279 .channels = kx022a_channels,
1280 .num_channels = ARRAY_SIZE(kx022a_channels),
1281 .scale_table = kx134acr_lbz_scale_table,
1282 .scale_table_size = ARRAY_SIZE(kx134acr_lbz_scale_table) *
1283 ARRAY_SIZE(kx134acr_lbz_scale_table[0]),
1284 .fifo_length = KX022A_FIFO_LENGTH,
1285 .who = KX022A_REG_WHO,
1286 .id = KX134ACR_LBZ_ID,
1287 .cntl = KX022A_REG_CNTL,
1288 .cntl2 = KX022A_REG_CNTL2,
1289 .odcntl = KX022A_REG_ODCNTL,
1290 .buf_cntl1 = KX022A_REG_BUF_CNTL1,
1291 .buf_cntl2 = KX022A_REG_BUF_CNTL2,
1292 .buf_clear = KX022A_REG_BUF_CLEAR,
1293 .buf_status1 = KX022A_REG_BUF_STATUS_1,
1294 .buf_read = KX022A_REG_BUF_READ,
1295 .inc1 = KX022A_REG_INC1,
1296 .inc4 = KX022A_REG_INC4,
1297 .inc5 = KX022A_REG_INC5,
1298 .inc6 = KX022A_REG_INC6,
1299 .xout_l = KX022A_REG_XOUT_L,
1300 .get_fifo_bytes_available = kx022a_get_fifo_bytes_available,
1301 };
1302 EXPORT_SYMBOL_NS_GPL(kx134acr_chip_info, "IIO_KX022A");
1303
kx022a_probe_internal(struct device * dev,const struct kx022a_chip_info * chip_info)1304 int kx022a_probe_internal(struct device *dev, const struct kx022a_chip_info *chip_info)
1305 {
1306 static const char * const regulator_names[] = {"io-vdd", "vdd"};
1307 struct iio_trigger *indio_trig;
1308 struct fwnode_handle *fwnode;
1309 struct kx022a_data *data;
1310 struct regmap *regmap;
1311 unsigned int chip_id;
1312 struct iio_dev *idev;
1313 int ret, irq;
1314 char *name;
1315
1316 regmap = dev_get_regmap(dev, NULL);
1317 if (!regmap) {
1318 dev_err(dev, "no regmap\n");
1319 return -EINVAL;
1320 }
1321
1322 fwnode = dev_fwnode(dev);
1323 if (!fwnode)
1324 return -ENODEV;
1325
1326 idev = devm_iio_device_alloc(dev, sizeof(*data));
1327 if (!idev)
1328 return -ENOMEM;
1329
1330 data = iio_priv(idev);
1331 data->chip_info = chip_info;
1332
1333 /*
1334 * VDD is the analog and digital domain voltage supply and
1335 * IO_VDD is the digital I/O voltage supply.
1336 */
1337 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulator_names),
1338 regulator_names);
1339 if (ret && ret != -ENODEV)
1340 return dev_err_probe(dev, ret, "failed to enable regulator\n");
1341
1342 ret = regmap_read(regmap, chip_info->who, &chip_id);
1343 if (ret)
1344 return dev_err_probe(dev, ret, "Failed to access sensor\n");
1345
1346 if (chip_id != chip_info->id)
1347 dev_warn(dev, "unknown device 0x%x\n", chip_id);
1348
1349 irq = fwnode_irq_get_byname(fwnode, "INT1");
1350 if (irq > 0) {
1351 data->inc_reg = chip_info->inc1;
1352 data->ien_reg = chip_info->inc4;
1353 } else {
1354 irq = fwnode_irq_get_byname(fwnode, "INT2");
1355 if (irq < 0)
1356 return dev_err_probe(dev, irq, "No suitable IRQ\n");
1357
1358 data->inc_reg = chip_info->inc5;
1359 data->ien_reg = chip_info->inc6;
1360 }
1361
1362 data->regmap = regmap;
1363 data->dev = dev;
1364 data->irq = irq;
1365 data->odr_ns = KX022A_DEFAULT_PERIOD_NS;
1366 mutex_init(&data->mutex);
1367
1368 idev->channels = chip_info->channels;
1369 idev->num_channels = chip_info->num_channels;
1370 idev->name = chip_info->name;
1371 idev->info = &kx022a_info;
1372 idev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
1373 idev->available_scan_masks = kx022a_scan_masks;
1374
1375 /* Read the mounting matrix, if present */
1376 ret = iio_read_mount_matrix(dev, &data->orientation);
1377 if (ret)
1378 return ret;
1379
1380 /* The sensor must be turned off for configuration */
1381 ret = kx022a_turn_off_lock(data);
1382 if (ret)
1383 return ret;
1384
1385 ret = kx022a_chip_init(data);
1386 if (ret) {
1387 mutex_unlock(&data->mutex);
1388 return ret;
1389 }
1390
1391 ret = kx022a_turn_on_unlock(data);
1392 if (ret)
1393 return ret;
1394
1395 ret = devm_iio_triggered_buffer_setup_ext(dev, idev,
1396 &iio_pollfunc_store_time,
1397 kx022a_trigger_handler,
1398 IIO_BUFFER_DIRECTION_IN,
1399 &kx022a_buffer_ops,
1400 kx022a_fifo_attributes);
1401
1402 if (ret)
1403 return dev_err_probe(data->dev, ret,
1404 "iio_triggered_buffer_setup_ext FAIL\n");
1405 indio_trig = devm_iio_trigger_alloc(dev, "%sdata-rdy-dev%d", idev->name,
1406 iio_device_id(idev));
1407 if (!indio_trig)
1408 return -ENOMEM;
1409
1410 data->trig = indio_trig;
1411
1412 indio_trig->ops = &kx022a_trigger_ops;
1413 iio_trigger_set_drvdata(indio_trig, data);
1414
1415 /*
1416 * No need to check for NULL. request_threaded_irq() defaults to
1417 * dev_name() should the alloc fail.
1418 */
1419 name = devm_kasprintf(data->dev, GFP_KERNEL, "%s-kx022a",
1420 dev_name(data->dev));
1421
1422 ret = devm_request_threaded_irq(data->dev, irq, kx022a_irq_handler,
1423 &kx022a_irq_thread_handler,
1424 IRQF_ONESHOT, name, idev);
1425 if (ret)
1426 return dev_err_probe(data->dev, ret, "Could not request IRQ\n");
1427
1428 ret = devm_iio_trigger_register(dev, indio_trig);
1429 if (ret)
1430 return dev_err_probe(data->dev, ret,
1431 "Trigger registration failed\n");
1432
1433 ret = devm_iio_device_register(data->dev, idev);
1434 if (ret < 0)
1435 return dev_err_probe(dev, ret,
1436 "Unable to register iio device\n");
1437
1438 return ret;
1439 }
1440 EXPORT_SYMBOL_NS_GPL(kx022a_probe_internal, "IIO_KX022A");
1441
1442 MODULE_DESCRIPTION("ROHM/Kionix KX022A accelerometer driver");
1443 MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
1444 MODULE_LICENSE("GPL");
1445