1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #include <hyp/switch.h>
8
9 #include <linux/arm-smccc.h>
10 #include <linux/kvm_host.h>
11 #include <linux/types.h>
12 #include <linux/jump_label.h>
13 #include <linux/percpu.h>
14 #include <uapi/linux/psci.h>
15
16 #include <kvm/arm_psci.h>
17
18 #include <asm/barrier.h>
19 #include <asm/cpufeature.h>
20 #include <asm/kprobes.h>
21 #include <asm/kvm_asm.h>
22 #include <asm/kvm_emulate.h>
23 #include <asm/kvm_hyp.h>
24 #include <asm/kvm_mmu.h>
25 #include <asm/fpsimd.h>
26 #include <asm/debug-monitors.h>
27 #include <asm/processor.h>
28 #include <asm/thread_info.h>
29 #include <asm/vectors.h>
30
31 /* VHE specific context */
32 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data);
33 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
34 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector);
35
36 /*
37 * HCR_EL2 bits that the NV guest can freely change (no RES0/RES1
38 * semantics, irrespective of the configuration), but that cannot be
39 * applied to the actual HW as things would otherwise break badly.
40 *
41 * - TGE: we want the guest to use EL1, which is incompatible with
42 * this bit being set
43 *
44 * - API/APK: they are already accounted for by vcpu_load(), and can
45 * only take effect across a load/put cycle (such as ERET)
46 */
47 #define NV_HCR_GUEST_EXCLUDE (HCR_TGE | HCR_API | HCR_APK)
48
__compute_hcr(struct kvm_vcpu * vcpu)49 static u64 __compute_hcr(struct kvm_vcpu *vcpu)
50 {
51 u64 guest_hcr = __vcpu_sys_reg(vcpu, HCR_EL2);
52 u64 hcr = vcpu->arch.hcr_el2;
53
54 if (!vcpu_has_nv(vcpu))
55 return hcr;
56
57 /*
58 * We rely on the invariant that a vcpu entered from HYP
59 * context must also exit in the same context, as only an ERET
60 * instruction can kick us out of it, and we obviously trap
61 * that sucker. PSTATE.M will get fixed-up on exit.
62 */
63 if (is_hyp_ctxt(vcpu)) {
64 host_data_set_flag(VCPU_IN_HYP_CONTEXT);
65
66 hcr |= HCR_NV | HCR_NV2 | HCR_AT | HCR_TTLB;
67
68 if (!vcpu_el2_e2h_is_set(vcpu))
69 hcr |= HCR_NV1;
70
71 write_sysreg_s(vcpu->arch.ctxt.vncr_array, SYS_VNCR_EL2);
72 } else {
73 host_data_clear_flag(VCPU_IN_HYP_CONTEXT);
74
75 if (guest_hcr & HCR_NV) {
76 u64 va = __fix_to_virt(vncr_fixmap(smp_processor_id()));
77
78 /* Inherit the low bits from the actual register */
79 va |= __vcpu_sys_reg(vcpu, VNCR_EL2) & GENMASK(PAGE_SHIFT - 1, 0);
80 write_sysreg_s(va, SYS_VNCR_EL2);
81
82 /* Force NV2 in case the guest is forgetful... */
83 guest_hcr |= HCR_NV2;
84 }
85 }
86
87 BUG_ON(host_data_test_flag(VCPU_IN_HYP_CONTEXT) &&
88 host_data_test_flag(L1_VNCR_MAPPED));
89
90 return hcr | (guest_hcr & ~NV_HCR_GUEST_EXCLUDE);
91 }
92
__activate_traps(struct kvm_vcpu * vcpu)93 static void __activate_traps(struct kvm_vcpu *vcpu)
94 {
95 u64 val;
96
97 ___activate_traps(vcpu, __compute_hcr(vcpu));
98
99 if (has_cntpoff()) {
100 struct timer_map map;
101
102 get_timer_map(vcpu, &map);
103
104 /*
105 * We're entrering the guest. Reload the correct
106 * values from memory now that TGE is clear.
107 */
108 if (map.direct_ptimer == vcpu_ptimer(vcpu))
109 val = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0);
110 if (map.direct_ptimer == vcpu_hptimer(vcpu))
111 val = __vcpu_sys_reg(vcpu, CNTHP_CVAL_EL2);
112
113 if (map.direct_ptimer) {
114 write_sysreg_el0(val, SYS_CNTP_CVAL);
115 isb();
116 }
117 }
118
119 __activate_cptr_traps(vcpu);
120
121 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1);
122 }
123 NOKPROBE_SYMBOL(__activate_traps);
124
__deactivate_traps(struct kvm_vcpu * vcpu)125 static void __deactivate_traps(struct kvm_vcpu *vcpu)
126 {
127 const char *host_vectors = vectors;
128
129 ___deactivate_traps(vcpu);
130
131 write_sysreg_hcr(HCR_HOST_VHE_FLAGS);
132
133 if (has_cntpoff()) {
134 struct timer_map map;
135 u64 val, offset;
136
137 get_timer_map(vcpu, &map);
138
139 /*
140 * We're exiting the guest. Save the latest CVAL value
141 * to memory and apply the offset now that TGE is set.
142 */
143 val = read_sysreg_el0(SYS_CNTP_CVAL);
144 if (map.direct_ptimer == vcpu_ptimer(vcpu))
145 __vcpu_assign_sys_reg(vcpu, CNTP_CVAL_EL0, val);
146 if (map.direct_ptimer == vcpu_hptimer(vcpu))
147 __vcpu_assign_sys_reg(vcpu, CNTHP_CVAL_EL2, val);
148
149 offset = read_sysreg_s(SYS_CNTPOFF_EL2);
150
151 if (map.direct_ptimer && offset) {
152 write_sysreg_el0(val + offset, SYS_CNTP_CVAL);
153 isb();
154 }
155 }
156
157 /*
158 * ARM errata 1165522 and 1530923 require the actual execution of the
159 * above before we can switch to the EL2/EL0 translation regime used by
160 * the host.
161 */
162 asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));
163
164 __deactivate_cptr_traps(vcpu);
165
166 if (!arm64_kernel_unmapped_at_el0())
167 host_vectors = __this_cpu_read(this_cpu_vector);
168 write_sysreg(host_vectors, vbar_el1);
169 }
170 NOKPROBE_SYMBOL(__deactivate_traps);
171
172 /*
173 * Disable IRQs in __vcpu_{load,put}_{activate,deactivate}_traps() to
174 * prevent a race condition between context switching of PMUSERENR_EL0
175 * in __{activate,deactivate}_traps_common() and IPIs that attempts to
176 * update PMUSERENR_EL0. See also kvm_set_pmuserenr().
177 */
__vcpu_load_activate_traps(struct kvm_vcpu * vcpu)178 static void __vcpu_load_activate_traps(struct kvm_vcpu *vcpu)
179 {
180 unsigned long flags;
181
182 local_irq_save(flags);
183 __activate_traps_common(vcpu);
184 local_irq_restore(flags);
185 }
186
__vcpu_put_deactivate_traps(struct kvm_vcpu * vcpu)187 static void __vcpu_put_deactivate_traps(struct kvm_vcpu *vcpu)
188 {
189 unsigned long flags;
190
191 local_irq_save(flags);
192 __deactivate_traps_common(vcpu);
193 local_irq_restore(flags);
194 }
195
kvm_vcpu_load_vhe(struct kvm_vcpu * vcpu)196 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu)
197 {
198 host_data_ptr(host_ctxt)->__hyp_running_vcpu = vcpu;
199
200 __vcpu_load_switch_sysregs(vcpu);
201 __vcpu_load_activate_traps(vcpu);
202 __load_stage2(vcpu->arch.hw_mmu, vcpu->arch.hw_mmu->arch);
203 }
204
kvm_vcpu_put_vhe(struct kvm_vcpu * vcpu)205 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu)
206 {
207 __vcpu_put_deactivate_traps(vcpu);
208 __vcpu_put_switch_sysregs(vcpu);
209
210 host_data_ptr(host_ctxt)->__hyp_running_vcpu = NULL;
211 }
212
compute_emulated_cntx_ctl_el0(struct kvm_vcpu * vcpu,enum vcpu_sysreg reg)213 static u64 compute_emulated_cntx_ctl_el0(struct kvm_vcpu *vcpu,
214 enum vcpu_sysreg reg)
215 {
216 unsigned long ctl;
217 u64 cval, cnt;
218 bool stat;
219
220 switch (reg) {
221 case CNTP_CTL_EL0:
222 cval = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0);
223 ctl = __vcpu_sys_reg(vcpu, CNTP_CTL_EL0);
224 cnt = compute_counter_value(vcpu_ptimer(vcpu));
225 break;
226 case CNTV_CTL_EL0:
227 cval = __vcpu_sys_reg(vcpu, CNTV_CVAL_EL0);
228 ctl = __vcpu_sys_reg(vcpu, CNTV_CTL_EL0);
229 cnt = compute_counter_value(vcpu_vtimer(vcpu));
230 break;
231 default:
232 BUG();
233 }
234
235 stat = cval <= cnt;
236 __assign_bit(__ffs(ARCH_TIMER_CTRL_IT_STAT), &ctl, stat);
237
238 return ctl;
239 }
240
kvm_hyp_handle_timer(struct kvm_vcpu * vcpu,u64 * exit_code)241 static bool kvm_hyp_handle_timer(struct kvm_vcpu *vcpu, u64 *exit_code)
242 {
243 u64 esr, val;
244
245 /*
246 * Having FEAT_ECV allows for a better quality of timer emulation.
247 * However, this comes at a huge cost in terms of traps. Try and
248 * satisfy the reads from guest's hypervisor context without
249 * returning to the kernel if we can.
250 */
251 if (!is_hyp_ctxt(vcpu))
252 return false;
253
254 esr = kvm_vcpu_get_esr(vcpu);
255 if ((esr & ESR_ELx_SYS64_ISS_DIR_MASK) != ESR_ELx_SYS64_ISS_DIR_READ)
256 return false;
257
258 switch (esr_sys64_to_sysreg(esr)) {
259 case SYS_CNTP_CTL_EL02:
260 val = compute_emulated_cntx_ctl_el0(vcpu, CNTP_CTL_EL0);
261 break;
262 case SYS_CNTP_CTL_EL0:
263 if (vcpu_el2_e2h_is_set(vcpu))
264 val = read_sysreg_el0(SYS_CNTP_CTL);
265 else
266 val = compute_emulated_cntx_ctl_el0(vcpu, CNTP_CTL_EL0);
267 break;
268 case SYS_CNTP_CVAL_EL02:
269 val = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0);
270 break;
271 case SYS_CNTP_CVAL_EL0:
272 if (vcpu_el2_e2h_is_set(vcpu)) {
273 val = read_sysreg_el0(SYS_CNTP_CVAL);
274
275 if (!has_cntpoff())
276 val -= timer_get_offset(vcpu_hptimer(vcpu));
277 } else {
278 val = __vcpu_sys_reg(vcpu, CNTP_CVAL_EL0);
279 }
280 break;
281 case SYS_CNTPCT_EL0:
282 case SYS_CNTPCTSS_EL0:
283 val = compute_counter_value(vcpu_hptimer(vcpu));
284 break;
285 case SYS_CNTV_CTL_EL02:
286 val = compute_emulated_cntx_ctl_el0(vcpu, CNTV_CTL_EL0);
287 break;
288 case SYS_CNTV_CTL_EL0:
289 if (vcpu_el2_e2h_is_set(vcpu))
290 val = read_sysreg_el0(SYS_CNTV_CTL);
291 else
292 val = compute_emulated_cntx_ctl_el0(vcpu, CNTV_CTL_EL0);
293 break;
294 case SYS_CNTV_CVAL_EL02:
295 val = __vcpu_sys_reg(vcpu, CNTV_CVAL_EL0);
296 break;
297 case SYS_CNTV_CVAL_EL0:
298 if (vcpu_el2_e2h_is_set(vcpu))
299 val = read_sysreg_el0(SYS_CNTV_CVAL);
300 else
301 val = __vcpu_sys_reg(vcpu, CNTV_CVAL_EL0);
302 break;
303 case SYS_CNTVCT_EL0:
304 case SYS_CNTVCTSS_EL0:
305 val = compute_counter_value(vcpu_hvtimer(vcpu));
306 break;
307 default:
308 return false;
309 }
310
311 vcpu_set_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu), val);
312 __kvm_skip_instr(vcpu);
313
314 return true;
315 }
316
kvm_hyp_handle_eret(struct kvm_vcpu * vcpu,u64 * exit_code)317 static bool kvm_hyp_handle_eret(struct kvm_vcpu *vcpu, u64 *exit_code)
318 {
319 u64 esr = kvm_vcpu_get_esr(vcpu);
320 u64 spsr, elr, mode;
321
322 /*
323 * Going through the whole put/load motions is a waste of time
324 * if this is a VHE guest hypervisor returning to its own
325 * userspace, or the hypervisor performing a local exception
326 * return. No need to save/restore registers, no need to
327 * switch S2 MMU. Just do the canonical ERET.
328 *
329 * Unless the trap has to be forwarded further down the line,
330 * of course...
331 */
332 if ((__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_NV) ||
333 (__vcpu_sys_reg(vcpu, HFGITR_EL2) & HFGITR_EL2_ERET))
334 return false;
335
336 spsr = read_sysreg_el1(SYS_SPSR);
337 mode = spsr & (PSR_MODE_MASK | PSR_MODE32_BIT);
338
339 switch (mode) {
340 case PSR_MODE_EL0t:
341 if (!(vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu)))
342 return false;
343 break;
344 case PSR_MODE_EL2t:
345 mode = PSR_MODE_EL1t;
346 break;
347 case PSR_MODE_EL2h:
348 mode = PSR_MODE_EL1h;
349 break;
350 default:
351 return false;
352 }
353
354 /* If ERETAx fails, take the slow path */
355 if (esr_iss_is_eretax(esr)) {
356 if (!(vcpu_has_ptrauth(vcpu) && kvm_auth_eretax(vcpu, &elr)))
357 return false;
358 } else {
359 elr = read_sysreg_el1(SYS_ELR);
360 }
361
362 spsr = (spsr & ~(PSR_MODE_MASK | PSR_MODE32_BIT)) | mode;
363
364 write_sysreg_el2(spsr, SYS_SPSR);
365 write_sysreg_el2(elr, SYS_ELR);
366
367 return true;
368 }
369
kvm_hyp_handle_tlbi_el2(struct kvm_vcpu * vcpu,u64 * exit_code)370 static bool kvm_hyp_handle_tlbi_el2(struct kvm_vcpu *vcpu, u64 *exit_code)
371 {
372 int ret = -EINVAL;
373 u32 instr;
374 u64 val;
375
376 /*
377 * Ideally, we would never trap on EL2 S1 TLB invalidations using
378 * the EL1 instructions when the guest's HCR_EL2.{E2H,TGE}=={1,1}.
379 * But "thanks" to FEAT_NV2, we don't trap writes to HCR_EL2,
380 * meaning that we can't track changes to the virtual TGE bit. So we
381 * have to leave HCR_EL2.TTLB set on the host. Oopsie...
382 *
383 * Try and handle these invalidation as quickly as possible, without
384 * fully exiting. Note that we don't need to consider any forwarding
385 * here, as having E2H+TGE set is the very definition of being
386 * InHost.
387 *
388 * For the lesser hypervisors out there that have failed to get on
389 * with the VHE program, we can also handle the nVHE style of EL2
390 * invalidation.
391 */
392 if (!(is_hyp_ctxt(vcpu)))
393 return false;
394
395 instr = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
396 val = vcpu_get_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu));
397
398 if ((kvm_supported_tlbi_s1e1_op(vcpu, instr) &&
399 vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu)) ||
400 kvm_supported_tlbi_s1e2_op (vcpu, instr))
401 ret = __kvm_tlbi_s1e2(NULL, val, instr);
402
403 if (ret)
404 return false;
405
406 /*
407 * If we have to check for any VNCR mapping being invalidated,
408 * go back to the slow path for further processing.
409 */
410 if (vcpu_el2_e2h_is_set(vcpu) && vcpu_el2_tge_is_set(vcpu) &&
411 atomic_read(&vcpu->kvm->arch.vncr_map_count))
412 return false;
413
414 __kvm_skip_instr(vcpu);
415
416 return true;
417 }
418
kvm_hyp_handle_cpacr_el1(struct kvm_vcpu * vcpu,u64 * exit_code)419 static bool kvm_hyp_handle_cpacr_el1(struct kvm_vcpu *vcpu, u64 *exit_code)
420 {
421 u64 esr = kvm_vcpu_get_esr(vcpu);
422 int rt;
423
424 if (!is_hyp_ctxt(vcpu) || esr_sys64_to_sysreg(esr) != SYS_CPACR_EL1)
425 return false;
426
427 rt = kvm_vcpu_sys_get_rt(vcpu);
428
429 if ((esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ) {
430 vcpu_set_reg(vcpu, rt, __vcpu_sys_reg(vcpu, CPTR_EL2));
431 } else {
432 vcpu_write_sys_reg(vcpu, vcpu_get_reg(vcpu, rt), CPTR_EL2);
433 __activate_cptr_traps(vcpu);
434 }
435
436 __kvm_skip_instr(vcpu);
437
438 return true;
439 }
440
kvm_hyp_handle_zcr_el2(struct kvm_vcpu * vcpu,u64 * exit_code)441 static bool kvm_hyp_handle_zcr_el2(struct kvm_vcpu *vcpu, u64 *exit_code)
442 {
443 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
444
445 if (!vcpu_has_nv(vcpu))
446 return false;
447
448 if (sysreg != SYS_ZCR_EL2)
449 return false;
450
451 if (guest_owns_fp_regs())
452 return false;
453
454 /*
455 * ZCR_EL2 traps are handled in the slow path, with the expectation
456 * that the guest's FP context has already been loaded onto the CPU.
457 *
458 * Load the guest's FP context and unconditionally forward to the
459 * slow path for handling (i.e. return false).
460 */
461 kvm_hyp_handle_fpsimd(vcpu, exit_code);
462 return false;
463 }
464
kvm_hyp_handle_sysreg_vhe(struct kvm_vcpu * vcpu,u64 * exit_code)465 static bool kvm_hyp_handle_sysreg_vhe(struct kvm_vcpu *vcpu, u64 *exit_code)
466 {
467 if (kvm_hyp_handle_tlbi_el2(vcpu, exit_code))
468 return true;
469
470 if (kvm_hyp_handle_timer(vcpu, exit_code))
471 return true;
472
473 if (kvm_hyp_handle_cpacr_el1(vcpu, exit_code))
474 return true;
475
476 if (kvm_hyp_handle_zcr_el2(vcpu, exit_code))
477 return true;
478
479 return kvm_hyp_handle_sysreg(vcpu, exit_code);
480 }
481
kvm_hyp_handle_impdef(struct kvm_vcpu * vcpu,u64 * exit_code)482 static bool kvm_hyp_handle_impdef(struct kvm_vcpu *vcpu, u64 *exit_code)
483 {
484 u64 iss;
485
486 if (!cpus_have_final_cap(ARM64_WORKAROUND_PMUV3_IMPDEF_TRAPS))
487 return false;
488
489 /*
490 * Compute a synthetic ESR for a sysreg trap. Conveniently, AFSR1_EL2
491 * is populated with a correct ISS for a sysreg trap. These fruity
492 * parts are 64bit only, so unconditionally set IL.
493 */
494 iss = ESR_ELx_ISS(read_sysreg_s(SYS_AFSR1_EL2));
495 vcpu->arch.fault.esr_el2 = FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_SYS64) |
496 FIELD_PREP(ESR_ELx_ISS_MASK, iss) |
497 ESR_ELx_IL;
498 return false;
499 }
500
501 static const exit_handler_fn hyp_exit_handlers[] = {
502 [0 ... ESR_ELx_EC_MAX] = NULL,
503 [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32,
504 [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg_vhe,
505 [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd,
506 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd,
507 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low,
508 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low,
509 [ESR_ELx_EC_WATCHPT_LOW] = kvm_hyp_handle_watchpt_low,
510 [ESR_ELx_EC_ERET] = kvm_hyp_handle_eret,
511 [ESR_ELx_EC_MOPS] = kvm_hyp_handle_mops,
512
513 /* Apple shenanigans */
514 [0x3F] = kvm_hyp_handle_impdef,
515 };
516
fixup_guest_exit(struct kvm_vcpu * vcpu,u64 * exit_code)517 static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code)
518 {
519 synchronize_vcpu_pstate(vcpu, exit_code);
520
521 /*
522 * If we were in HYP context on entry, adjust the PSTATE view
523 * so that the usual helpers work correctly. This enforces our
524 * invariant that the guest's HYP context status is preserved
525 * across a run.
526 */
527 if (vcpu_has_nv(vcpu) &&
528 unlikely(host_data_test_flag(VCPU_IN_HYP_CONTEXT))) {
529 u64 mode = *vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT);
530
531 switch (mode) {
532 case PSR_MODE_EL1t:
533 mode = PSR_MODE_EL2t;
534 break;
535 case PSR_MODE_EL1h:
536 mode = PSR_MODE_EL2h;
537 break;
538 }
539
540 *vcpu_cpsr(vcpu) &= ~(PSR_MODE_MASK | PSR_MODE32_BIT);
541 *vcpu_cpsr(vcpu) |= mode;
542 }
543
544 /* Apply extreme paranoia! */
545 BUG_ON(vcpu_has_nv(vcpu) &&
546 !!host_data_test_flag(VCPU_IN_HYP_CONTEXT) != is_hyp_ctxt(vcpu));
547
548 return __fixup_guest_exit(vcpu, exit_code, hyp_exit_handlers);
549 }
550
551 /* Switch to the guest for VHE systems running in EL2 */
__kvm_vcpu_run_vhe(struct kvm_vcpu * vcpu)552 static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
553 {
554 struct kvm_cpu_context *host_ctxt;
555 struct kvm_cpu_context *guest_ctxt;
556 u64 exit_code;
557
558 host_ctxt = host_data_ptr(host_ctxt);
559 guest_ctxt = &vcpu->arch.ctxt;
560
561 fpsimd_lazy_switch_to_guest(vcpu);
562
563 sysreg_save_host_state_vhe(host_ctxt);
564
565 /*
566 * Note that ARM erratum 1165522 requires us to configure both stage 1
567 * and stage 2 translation for the guest context before we clear
568 * HCR_EL2.TGE. The stage 1 and stage 2 guest context has already been
569 * loaded on the CPU in kvm_vcpu_load_vhe().
570 */
571 __activate_traps(vcpu);
572
573 __kvm_adjust_pc(vcpu);
574
575 sysreg_restore_guest_state_vhe(guest_ctxt);
576 __debug_switch_to_guest(vcpu);
577
578 do {
579 /* Jump in the fire! */
580 exit_code = __guest_enter(vcpu);
581
582 /* And we're baaack! */
583 } while (fixup_guest_exit(vcpu, &exit_code));
584
585 sysreg_save_guest_state_vhe(guest_ctxt);
586
587 __deactivate_traps(vcpu);
588
589 sysreg_restore_host_state_vhe(host_ctxt);
590
591 __debug_switch_to_host(vcpu);
592
593 /*
594 * Ensure that all system register writes above have taken effect
595 * before returning to the host. In VHE mode, CPTR traps for
596 * FPSIMD/SVE/SME also apply to EL2, so FPSIMD/SVE/SME state must be
597 * manipulated after the ISB.
598 */
599 isb();
600
601 fpsimd_lazy_switch_to_host(vcpu);
602
603 if (guest_owns_fp_regs())
604 __fpsimd_save_fpexc32(vcpu);
605
606 return exit_code;
607 }
608 NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe);
609
__kvm_vcpu_run(struct kvm_vcpu * vcpu)610 int __kvm_vcpu_run(struct kvm_vcpu *vcpu)
611 {
612 int ret;
613
614 local_daif_mask();
615
616 /*
617 * Having IRQs masked via PMR when entering the guest means the GIC
618 * will not signal the CPU of interrupts of lower priority, and the
619 * only way to get out will be via guest exceptions.
620 * Naturally, we want to avoid this.
621 *
622 * local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a
623 * dsb to ensure the redistributor is forwards EL2 IRQs to the CPU.
624 */
625 pmr_sync();
626
627 ret = __kvm_vcpu_run_vhe(vcpu);
628
629 /*
630 * local_daif_restore() takes care to properly restore PSTATE.DAIF
631 * and the GIC PMR if the host is using IRQ priorities.
632 */
633 local_daif_restore(DAIF_PROCCTX_NOIRQ);
634
635 return ret;
636 }
637
__hyp_call_panic(u64 spsr,u64 elr,u64 par)638 static void __noreturn __hyp_call_panic(u64 spsr, u64 elr, u64 par)
639 {
640 struct kvm_cpu_context *host_ctxt;
641 struct kvm_vcpu *vcpu;
642
643 host_ctxt = host_data_ptr(host_ctxt);
644 vcpu = host_ctxt->__hyp_running_vcpu;
645
646 __deactivate_traps(vcpu);
647 sysreg_restore_host_state_vhe(host_ctxt);
648
649 panic("HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n",
650 spsr, elr,
651 read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR),
652 read_sysreg(hpfar_el2), par, vcpu);
653 }
654 NOKPROBE_SYMBOL(__hyp_call_panic);
655
hyp_panic(void)656 void __noreturn hyp_panic(void)
657 {
658 u64 spsr = read_sysreg_el2(SYS_SPSR);
659 u64 elr = read_sysreg_el2(SYS_ELR);
660 u64 par = read_sysreg_par();
661
662 __hyp_call_panic(spsr, elr, par);
663 }
664
kvm_unexpected_el2_exception(void)665 asmlinkage void kvm_unexpected_el2_exception(void)
666 {
667 __kvm_unexpected_el2_exception();
668 }
669