1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020-2023 Loongson Technology Corporation Limited 4 */ 5 6 #include <linux/kvm_host.h> 7 #include <asm/fpu.h> 8 #include <asm/lbt.h> 9 #include <asm/loongarch.h> 10 #include <asm/setup.h> 11 #include <asm/time.h> 12 #include <asm/timex.h> 13 14 #define CREATE_TRACE_POINTS 15 #include "trace.h" 16 17 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = { 18 KVM_GENERIC_VCPU_STATS(), 19 STATS_DESC_COUNTER(VCPU, int_exits), 20 STATS_DESC_COUNTER(VCPU, idle_exits), 21 STATS_DESC_COUNTER(VCPU, cpucfg_exits), 22 STATS_DESC_COUNTER(VCPU, signal_exits), 23 STATS_DESC_COUNTER(VCPU, hypercall_exits), 24 STATS_DESC_COUNTER(VCPU, ipi_read_exits), 25 STATS_DESC_COUNTER(VCPU, ipi_write_exits), 26 STATS_DESC_COUNTER(VCPU, eiointc_read_exits), 27 STATS_DESC_COUNTER(VCPU, eiointc_write_exits), 28 STATS_DESC_COUNTER(VCPU, pch_pic_read_exits), 29 STATS_DESC_COUNTER(VCPU, pch_pic_write_exits) 30 }; 31 32 const struct kvm_stats_header kvm_vcpu_stats_header = { 33 .name_size = KVM_STATS_NAME_SIZE, 34 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc), 35 .id_offset = sizeof(struct kvm_stats_header), 36 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE, 37 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE + 38 sizeof(kvm_vcpu_stats_desc), 39 }; 40 41 static inline void kvm_save_host_pmu(struct kvm_vcpu *vcpu) 42 { 43 struct kvm_context *context; 44 45 context = this_cpu_ptr(vcpu->kvm->arch.vmcs); 46 context->perf_cntr[0] = read_csr_perfcntr0(); 47 context->perf_cntr[1] = read_csr_perfcntr1(); 48 context->perf_cntr[2] = read_csr_perfcntr2(); 49 context->perf_cntr[3] = read_csr_perfcntr3(); 50 context->perf_ctrl[0] = write_csr_perfctrl0(0); 51 context->perf_ctrl[1] = write_csr_perfctrl1(0); 52 context->perf_ctrl[2] = write_csr_perfctrl2(0); 53 context->perf_ctrl[3] = write_csr_perfctrl3(0); 54 } 55 56 static inline void kvm_restore_host_pmu(struct kvm_vcpu *vcpu) 57 { 58 struct kvm_context *context; 59 60 context = this_cpu_ptr(vcpu->kvm->arch.vmcs); 61 write_csr_perfcntr0(context->perf_cntr[0]); 62 write_csr_perfcntr1(context->perf_cntr[1]); 63 write_csr_perfcntr2(context->perf_cntr[2]); 64 write_csr_perfcntr3(context->perf_cntr[3]); 65 write_csr_perfctrl0(context->perf_ctrl[0]); 66 write_csr_perfctrl1(context->perf_ctrl[1]); 67 write_csr_perfctrl2(context->perf_ctrl[2]); 68 write_csr_perfctrl3(context->perf_ctrl[3]); 69 } 70 71 72 static inline void kvm_save_guest_pmu(struct kvm_vcpu *vcpu) 73 { 74 struct loongarch_csrs *csr = vcpu->arch.csr; 75 76 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR0); 77 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR1); 78 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR2); 79 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR3); 80 kvm_read_clear_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL0); 81 kvm_read_clear_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL1); 82 kvm_read_clear_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL2); 83 kvm_read_clear_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL3); 84 } 85 86 static inline void kvm_restore_guest_pmu(struct kvm_vcpu *vcpu) 87 { 88 struct loongarch_csrs *csr = vcpu->arch.csr; 89 90 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR0); 91 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR1); 92 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR2); 93 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PERFCNTR3); 94 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL0); 95 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL1); 96 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL2); 97 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PERFCTRL3); 98 } 99 100 static int kvm_own_pmu(struct kvm_vcpu *vcpu) 101 { 102 unsigned long val; 103 104 if (!kvm_guest_has_pmu(&vcpu->arch)) 105 return -EINVAL; 106 107 kvm_save_host_pmu(vcpu); 108 109 /* Set PM0-PM(num) to guest */ 110 val = read_csr_gcfg() & ~CSR_GCFG_GPERF; 111 val |= (kvm_get_pmu_num(&vcpu->arch) + 1) << CSR_GCFG_GPERF_SHIFT; 112 write_csr_gcfg(val); 113 114 kvm_restore_guest_pmu(vcpu); 115 116 return 0; 117 } 118 119 static void kvm_lose_pmu(struct kvm_vcpu *vcpu) 120 { 121 unsigned long val; 122 struct loongarch_csrs *csr = vcpu->arch.csr; 123 124 if (!(vcpu->arch.aux_inuse & KVM_LARCH_PMU)) 125 return; 126 127 kvm_save_guest_pmu(vcpu); 128 129 /* Disable pmu access from guest */ 130 write_csr_gcfg(read_csr_gcfg() & ~CSR_GCFG_GPERF); 131 132 /* 133 * Clear KVM_LARCH_PMU if the guest is not using PMU CSRs when 134 * exiting the guest, so that the next time trap into the guest. 135 * We don't need to deal with PMU CSRs contexts. 136 * 137 * Otherwise set the request bit KVM_REQ_PMU to restore guest PMU 138 * before entering guest VM 139 */ 140 val = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL0); 141 val |= kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL1); 142 val |= kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL2); 143 val |= kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL3); 144 if (!(val & KVM_PMU_EVENT_ENABLED)) 145 vcpu->arch.aux_inuse &= ~KVM_LARCH_PMU; 146 else 147 kvm_make_request(KVM_REQ_PMU, vcpu); 148 149 kvm_restore_host_pmu(vcpu); 150 } 151 152 static void kvm_check_pmu(struct kvm_vcpu *vcpu) 153 { 154 if (kvm_check_request(KVM_REQ_PMU, vcpu)) { 155 kvm_own_pmu(vcpu); 156 vcpu->arch.aux_inuse |= KVM_LARCH_PMU; 157 } 158 } 159 160 static void kvm_update_stolen_time(struct kvm_vcpu *vcpu) 161 { 162 u32 version; 163 u64 steal; 164 gpa_t gpa; 165 struct kvm_memslots *slots; 166 struct kvm_steal_time __user *st; 167 struct gfn_to_hva_cache *ghc; 168 169 ghc = &vcpu->arch.st.cache; 170 gpa = vcpu->arch.st.guest_addr; 171 if (!(gpa & KVM_STEAL_PHYS_VALID)) 172 return; 173 174 gpa &= KVM_STEAL_PHYS_MASK; 175 slots = kvm_memslots(vcpu->kvm); 176 if (slots->generation != ghc->generation || gpa != ghc->gpa) { 177 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st))) { 178 ghc->gpa = INVALID_GPA; 179 return; 180 } 181 } 182 183 st = (struct kvm_steal_time __user *)ghc->hva; 184 if (kvm_guest_has_pv_feature(vcpu, KVM_FEATURE_PREEMPT)) { 185 unsafe_put_user(0, &st->preempted, out); 186 vcpu->arch.st.preempted = 0; 187 } 188 189 unsafe_get_user(version, &st->version, out); 190 if (version & 1) 191 version += 1; /* first time write, random junk */ 192 193 version += 1; 194 unsafe_put_user(version, &st->version, out); 195 smp_wmb(); 196 197 unsafe_get_user(steal, &st->steal, out); 198 steal += current->sched_info.run_delay - vcpu->arch.st.last_steal; 199 vcpu->arch.st.last_steal = current->sched_info.run_delay; 200 unsafe_put_user(steal, &st->steal, out); 201 202 smp_wmb(); 203 version += 1; 204 unsafe_put_user(version, &st->version, out); 205 out: 206 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 207 } 208 209 /* 210 * kvm_check_requests - check and handle pending vCPU requests 211 * 212 * Return: RESUME_GUEST if we should enter the guest 213 * RESUME_HOST if we should exit to userspace 214 */ 215 static int kvm_check_requests(struct kvm_vcpu *vcpu) 216 { 217 if (!kvm_request_pending(vcpu)) 218 return RESUME_GUEST; 219 220 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu)) 221 vcpu->arch.vpid = 0; /* Drop vpid for this vCPU */ 222 223 if (kvm_dirty_ring_check_request(vcpu)) 224 return RESUME_HOST; 225 226 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu)) 227 kvm_update_stolen_time(vcpu); 228 229 return RESUME_GUEST; 230 } 231 232 static void kvm_late_check_requests(struct kvm_vcpu *vcpu) 233 { 234 lockdep_assert_irqs_disabled(); 235 if (kvm_check_request(KVM_REQ_TLB_FLUSH_GPA, vcpu)) 236 if (vcpu->arch.flush_gpa != INVALID_GPA) { 237 kvm_flush_tlb_gpa(vcpu, vcpu->arch.flush_gpa); 238 vcpu->arch.flush_gpa = INVALID_GPA; 239 } 240 241 if (kvm_check_request(KVM_REQ_AUX_LOAD, vcpu)) { 242 switch (vcpu->arch.aux_ldtype) { 243 case KVM_LARCH_FPU: 244 kvm_own_fpu(vcpu); 245 break; 246 case KVM_LARCH_LSX: 247 kvm_own_lsx(vcpu); 248 break; 249 case KVM_LARCH_LASX: 250 kvm_own_lasx(vcpu); 251 break; 252 case KVM_LARCH_LBT: 253 kvm_own_lbt(vcpu); 254 break; 255 default: 256 break; 257 } 258 259 vcpu->arch.aux_ldtype = 0; 260 } 261 } 262 263 /* 264 * Check and handle pending signal and vCPU requests etc 265 * Run with irq enabled and preempt enabled 266 * 267 * Return: RESUME_GUEST if we should enter the guest 268 * RESUME_HOST if we should exit to userspace 269 * < 0 if we should exit to userspace, where the return value 270 * indicates an error 271 */ 272 static int kvm_enter_guest_check(struct kvm_vcpu *vcpu) 273 { 274 int idx, ret; 275 276 /* 277 * Check conditions before entering the guest 278 */ 279 ret = kvm_xfer_to_guest_mode_handle_work(vcpu); 280 if (ret < 0) 281 return ret; 282 283 idx = srcu_read_lock(&vcpu->kvm->srcu); 284 ret = kvm_check_requests(vcpu); 285 srcu_read_unlock(&vcpu->kvm->srcu, idx); 286 287 return ret; 288 } 289 290 /* 291 * Called with irq enabled 292 * 293 * Return: RESUME_GUEST if we should enter the guest, and irq disabled 294 * Others if we should exit to userspace 295 */ 296 static int kvm_pre_enter_guest(struct kvm_vcpu *vcpu) 297 { 298 int ret; 299 300 do { 301 ret = kvm_enter_guest_check(vcpu); 302 if (ret != RESUME_GUEST) 303 break; 304 305 /* 306 * Handle vcpu timer, interrupts, check requests and 307 * check vmid before vcpu enter guest 308 */ 309 local_irq_disable(); 310 kvm_deliver_intr(vcpu); 311 kvm_deliver_exception(vcpu); 312 /* Make sure the vcpu mode has been written */ 313 smp_store_mb(vcpu->mode, IN_GUEST_MODE); 314 kvm_check_vpid(vcpu); 315 kvm_check_pmu(vcpu); 316 317 /* 318 * Called after function kvm_check_vpid() 319 * Since it updates CSR.GSTAT used by kvm_flush_tlb_gpa(), 320 * and it may also clear KVM_REQ_TLB_FLUSH_GPA pending bit 321 */ 322 kvm_late_check_requests(vcpu); 323 vcpu->arch.host_eentry = csr_read64(LOONGARCH_CSR_EENTRY); 324 /* Clear KVM_LARCH_SWCSR_LATEST as CSR will change when enter guest */ 325 vcpu->arch.aux_inuse &= ~KVM_LARCH_SWCSR_LATEST; 326 327 if (kvm_request_pending(vcpu) || xfer_to_guest_mode_work_pending()) { 328 if (vcpu->arch.aux_inuse & KVM_LARCH_PMU) { 329 kvm_lose_pmu(vcpu); 330 kvm_make_request(KVM_REQ_PMU, vcpu); 331 } 332 /* make sure the vcpu mode has been written */ 333 smp_store_mb(vcpu->mode, OUTSIDE_GUEST_MODE); 334 local_irq_enable(); 335 ret = -EAGAIN; 336 } 337 } while (ret != RESUME_GUEST); 338 339 return ret; 340 } 341 342 /* 343 * Return 1 for resume guest and "<= 0" for resume host. 344 */ 345 static int kvm_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu) 346 { 347 int ret = RESUME_GUEST; 348 unsigned long estat = vcpu->arch.host_estat; 349 u32 intr = estat & CSR_ESTAT_IS; 350 u32 ecode = (estat & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT; 351 352 vcpu->mode = OUTSIDE_GUEST_MODE; 353 354 /* Set a default exit reason */ 355 run->exit_reason = KVM_EXIT_UNKNOWN; 356 357 kvm_lose_pmu(vcpu); 358 359 guest_timing_exit_irqoff(); 360 guest_state_exit_irqoff(); 361 local_irq_enable(); 362 363 trace_kvm_exit(vcpu, ecode); 364 if (ecode) { 365 ret = kvm_handle_fault(vcpu, ecode); 366 } else { 367 WARN(!intr, "vm exiting with suspicious irq\n"); 368 ++vcpu->stat.int_exits; 369 } 370 371 if (ret == RESUME_GUEST) 372 ret = kvm_pre_enter_guest(vcpu); 373 374 if (ret != RESUME_GUEST) { 375 local_irq_disable(); 376 return ret; 377 } 378 379 guest_timing_enter_irqoff(); 380 guest_state_enter_irqoff(); 381 trace_kvm_reenter(vcpu); 382 383 return RESUME_GUEST; 384 } 385 386 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu) 387 { 388 return !!(vcpu->arch.irq_pending) && 389 vcpu->arch.mp_state.mp_state == KVM_MP_STATE_RUNNABLE; 390 } 391 392 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) 393 { 394 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE; 395 } 396 397 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu) 398 { 399 unsigned long val; 400 401 preempt_disable(); 402 val = gcsr_read(LOONGARCH_CSR_CRMD); 403 preempt_enable(); 404 405 return (val & CSR_PRMD_PPLV) == PLV_KERN; 406 } 407 408 #ifdef CONFIG_GUEST_PERF_EVENTS 409 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu) 410 { 411 return vcpu->arch.pc; 412 } 413 414 /* 415 * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event, 416 * arrived in guest context. For LoongArch64, if PMU is not passthrough to VM, 417 * any event that arrives while a vCPU is loaded is considered to be "in guest". 418 */ 419 bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu) 420 { 421 return (vcpu && !(vcpu->arch.aux_inuse & KVM_LARCH_PMU)); 422 } 423 #endif 424 425 bool kvm_arch_vcpu_preempted_in_kernel(struct kvm_vcpu *vcpu) 426 { 427 return false; 428 } 429 430 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf) 431 { 432 return VM_FAULT_SIGBUS; 433 } 434 435 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu, 436 struct kvm_translation *tr) 437 { 438 return -EINVAL; 439 } 440 441 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu) 442 { 443 int ret; 444 445 /* Protect from TOD sync and vcpu_load/put() */ 446 preempt_disable(); 447 ret = kvm_pending_timer(vcpu) || 448 kvm_read_hw_gcsr(LOONGARCH_CSR_ESTAT) & (1 << INT_TI); 449 preempt_enable(); 450 451 return ret; 452 } 453 454 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu) 455 { 456 int i; 457 458 kvm_debug("vCPU Register Dump:\n"); 459 kvm_debug("\tPC = 0x%08lx\n", vcpu->arch.pc); 460 kvm_debug("\tExceptions: %08lx\n", vcpu->arch.irq_pending); 461 462 for (i = 0; i < 32; i += 4) { 463 kvm_debug("\tGPR%02d: %08lx %08lx %08lx %08lx\n", i, 464 vcpu->arch.gprs[i], vcpu->arch.gprs[i + 1], 465 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]); 466 } 467 468 kvm_debug("\tCRMD: 0x%08lx, ESTAT: 0x%08lx\n", 469 kvm_read_hw_gcsr(LOONGARCH_CSR_CRMD), 470 kvm_read_hw_gcsr(LOONGARCH_CSR_ESTAT)); 471 472 kvm_debug("\tERA: 0x%08lx\n", kvm_read_hw_gcsr(LOONGARCH_CSR_ERA)); 473 474 return 0; 475 } 476 477 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu, 478 struct kvm_mp_state *mp_state) 479 { 480 *mp_state = vcpu->arch.mp_state; 481 482 return 0; 483 } 484 485 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu, 486 struct kvm_mp_state *mp_state) 487 { 488 int ret = 0; 489 490 switch (mp_state->mp_state) { 491 case KVM_MP_STATE_RUNNABLE: 492 vcpu->arch.mp_state = *mp_state; 493 break; 494 default: 495 ret = -EINVAL; 496 } 497 498 return ret; 499 } 500 501 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu, 502 struct kvm_guest_debug *dbg) 503 { 504 if (dbg->control & ~KVM_GUESTDBG_VALID_MASK) 505 return -EINVAL; 506 507 if (dbg->control & KVM_GUESTDBG_ENABLE) 508 vcpu->guest_debug = dbg->control; 509 else 510 vcpu->guest_debug = 0; 511 512 return 0; 513 } 514 515 static inline int kvm_set_cpuid(struct kvm_vcpu *vcpu, u64 val) 516 { 517 int cpuid; 518 struct kvm_phyid_map *map; 519 struct loongarch_csrs *csr = vcpu->arch.csr; 520 521 if (val >= KVM_MAX_PHYID) 522 return -EINVAL; 523 524 map = vcpu->kvm->arch.phyid_map; 525 cpuid = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_CPUID); 526 527 spin_lock(&vcpu->kvm->arch.phyid_map_lock); 528 if ((cpuid < KVM_MAX_PHYID) && map->phys_map[cpuid].enabled) { 529 /* Discard duplicated CPUID set operation */ 530 if (cpuid == val) { 531 spin_unlock(&vcpu->kvm->arch.phyid_map_lock); 532 return 0; 533 } 534 535 /* 536 * CPUID is already set before 537 * Forbid changing to a different CPUID at runtime 538 */ 539 spin_unlock(&vcpu->kvm->arch.phyid_map_lock); 540 return -EINVAL; 541 } 542 543 if (map->phys_map[val].enabled) { 544 /* Discard duplicated CPUID set operation */ 545 if (vcpu == map->phys_map[val].vcpu) { 546 spin_unlock(&vcpu->kvm->arch.phyid_map_lock); 547 return 0; 548 } 549 550 /* 551 * New CPUID is already set with other vcpu 552 * Forbid sharing the same CPUID between different vcpus 553 */ 554 spin_unlock(&vcpu->kvm->arch.phyid_map_lock); 555 return -EINVAL; 556 } 557 558 kvm_write_sw_gcsr(csr, LOONGARCH_CSR_CPUID, val); 559 map->phys_map[val].enabled = true; 560 map->phys_map[val].vcpu = vcpu; 561 spin_unlock(&vcpu->kvm->arch.phyid_map_lock); 562 563 return 0; 564 } 565 566 static inline void kvm_drop_cpuid(struct kvm_vcpu *vcpu) 567 { 568 int cpuid; 569 struct kvm_phyid_map *map; 570 struct loongarch_csrs *csr = vcpu->arch.csr; 571 572 map = vcpu->kvm->arch.phyid_map; 573 cpuid = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_CPUID); 574 575 if (cpuid >= KVM_MAX_PHYID) 576 return; 577 578 spin_lock(&vcpu->kvm->arch.phyid_map_lock); 579 if (map->phys_map[cpuid].enabled) { 580 map->phys_map[cpuid].vcpu = NULL; 581 map->phys_map[cpuid].enabled = false; 582 kvm_write_sw_gcsr(csr, LOONGARCH_CSR_CPUID, KVM_MAX_PHYID); 583 } 584 spin_unlock(&vcpu->kvm->arch.phyid_map_lock); 585 } 586 587 struct kvm_vcpu *kvm_get_vcpu_by_cpuid(struct kvm *kvm, int cpuid) 588 { 589 struct kvm_phyid_map *map; 590 591 if (cpuid >= KVM_MAX_PHYID) 592 return NULL; 593 594 map = kvm->arch.phyid_map; 595 if (!map->phys_map[cpuid].enabled) 596 return NULL; 597 598 return map->phys_map[cpuid].vcpu; 599 } 600 601 static int _kvm_getcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 *val) 602 { 603 unsigned long gintc; 604 struct loongarch_csrs *csr = vcpu->arch.csr; 605 606 if (get_gcsr_flag(id) & INVALID_GCSR) 607 return -EINVAL; 608 609 if (id == LOONGARCH_CSR_ESTAT) { 610 preempt_disable(); 611 vcpu_load(vcpu); 612 /* 613 * Sync pending interrupts into ESTAT so that interrupt 614 * remains during VM migration stage 615 */ 616 kvm_deliver_intr(vcpu); 617 vcpu->arch.aux_inuse &= ~KVM_LARCH_SWCSR_LATEST; 618 vcpu_put(vcpu); 619 preempt_enable(); 620 621 /* ESTAT IP0~IP7 get from GINTC */ 622 gintc = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_GINTC) & 0xff; 623 *val = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_ESTAT) | (gintc << 2); 624 return 0; 625 } 626 627 /* 628 * Get software CSR state since software state is consistent 629 * with hardware for synchronous ioctl 630 */ 631 *val = kvm_read_sw_gcsr(csr, id); 632 633 return 0; 634 } 635 636 static int _kvm_setcsr(struct kvm_vcpu *vcpu, unsigned int id, u64 val) 637 { 638 int ret = 0, gintc; 639 struct loongarch_csrs *csr = vcpu->arch.csr; 640 641 if (get_gcsr_flag(id) & INVALID_GCSR) 642 return -EINVAL; 643 644 if (id == LOONGARCH_CSR_CPUID) 645 return kvm_set_cpuid(vcpu, val); 646 647 if (id == LOONGARCH_CSR_ESTAT) { 648 /* ESTAT IP0~IP7 inject through GINTC */ 649 gintc = (val >> 2) & 0xff; 650 kvm_set_sw_gcsr(csr, LOONGARCH_CSR_GINTC, gintc); 651 652 gintc = val & ~(0xffUL << 2); 653 kvm_set_sw_gcsr(csr, LOONGARCH_CSR_ESTAT, gintc); 654 655 return ret; 656 } 657 658 kvm_write_sw_gcsr(csr, id, val); 659 660 /* 661 * After modifying the PMU CSR register value of the vcpu. 662 * If the PMU CSRs are used, we need to set KVM_REQ_PMU. 663 */ 664 if (id >= LOONGARCH_CSR_PERFCTRL0 && id <= LOONGARCH_CSR_PERFCNTR3) { 665 unsigned long val; 666 667 val = kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL0) | 668 kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL1) | 669 kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL2) | 670 kvm_read_sw_gcsr(csr, LOONGARCH_CSR_PERFCTRL3); 671 672 if (val & KVM_PMU_EVENT_ENABLED) 673 kvm_make_request(KVM_REQ_PMU, vcpu); 674 } 675 676 return ret; 677 } 678 679 static int _kvm_get_cpucfg_mask(int id, u64 *v) 680 { 681 unsigned int config; 682 683 if (id < 0 || id >= KVM_MAX_CPUCFG_REGS) 684 return -EINVAL; 685 686 switch (id) { 687 case LOONGARCH_CPUCFG0: 688 *v = GENMASK(31, 0); 689 return 0; 690 case LOONGARCH_CPUCFG1: 691 *v = GENMASK(26, 0); 692 return 0; 693 case LOONGARCH_CPUCFG2: 694 /* CPUCFG2 features unconditionally supported by KVM */ 695 *v = CPUCFG2_FP | CPUCFG2_FPSP | CPUCFG2_FPDP | 696 CPUCFG2_FPVERS | CPUCFG2_LLFTP | CPUCFG2_LLFTPREV | 697 CPUCFG2_LSPW | CPUCFG2_LAM; 698 /* 699 * For the ISA extensions listed below, if one is supported 700 * by the host, then it is also supported by KVM. 701 */ 702 if (cpu_has_lsx) 703 *v |= CPUCFG2_LSX; 704 if (cpu_has_lasx) 705 *v |= CPUCFG2_LASX; 706 if (cpu_has_lbt_x86) 707 *v |= CPUCFG2_X86BT; 708 if (cpu_has_lbt_arm) 709 *v |= CPUCFG2_ARMBT; 710 if (cpu_has_lbt_mips) 711 *v |= CPUCFG2_MIPSBT; 712 if (cpu_has_ptw) 713 *v |= CPUCFG2_PTW; 714 715 config = read_cpucfg(LOONGARCH_CPUCFG2); 716 *v |= config & (CPUCFG2_FRECIPE | CPUCFG2_DIV32 | CPUCFG2_LAM_BH); 717 *v |= config & (CPUCFG2_LAMCAS | CPUCFG2_LLACQ_SCREL | CPUCFG2_SCQ); 718 return 0; 719 case LOONGARCH_CPUCFG3: 720 *v = GENMASK(23, 0); 721 722 /* VM does not support memory order and SFB setting */ 723 config = read_cpucfg(LOONGARCH_CPUCFG3); 724 *v &= config & ~(CPUCFG3_SFB); 725 *v &= config & ~(CPUCFG3_ALDORDER_CAP | CPUCFG3_ASTORDER_CAP | CPUCFG3_SLDORDER_CAP); 726 return 0; 727 case LOONGARCH_CPUCFG4: 728 case LOONGARCH_CPUCFG5: 729 *v = GENMASK(31, 0); 730 return 0; 731 case LOONGARCH_CPUCFG6: 732 if (cpu_has_pmp) 733 *v = GENMASK(14, 0); 734 else 735 *v = 0; 736 return 0; 737 case LOONGARCH_CPUCFG16: 738 *v = GENMASK(16, 0); 739 return 0; 740 case LOONGARCH_CPUCFG17 ... LOONGARCH_CPUCFG20: 741 *v = GENMASK(30, 0); 742 return 0; 743 default: 744 /* 745 * CPUCFG bits should be zero if reserved by HW or not 746 * supported by KVM. 747 */ 748 *v = 0; 749 return 0; 750 } 751 } 752 753 static int kvm_check_cpucfg(int id, u64 val) 754 { 755 int ret; 756 u32 host; 757 u64 mask = 0; 758 759 ret = _kvm_get_cpucfg_mask(id, &mask); 760 if (ret) 761 return ret; 762 763 if (val & ~mask) 764 /* Unsupported features and/or the higher 32 bits should not be set */ 765 return -EINVAL; 766 767 switch (id) { 768 case LOONGARCH_CPUCFG1: 769 if ((val & CPUCFG1_MSGINT) && !cpu_has_msgint) 770 return -EINVAL; 771 return 0; 772 case LOONGARCH_CPUCFG2: 773 if (!(val & CPUCFG2_LLFTP)) 774 /* Guests must have a constant timer */ 775 return -EINVAL; 776 if ((val & CPUCFG2_FP) && (!(val & CPUCFG2_FPSP) || !(val & CPUCFG2_FPDP))) 777 /* Single and double float point must both be set when FP is enabled */ 778 return -EINVAL; 779 if ((val & CPUCFG2_LSX) && !(val & CPUCFG2_FP)) 780 /* LSX architecturally implies FP but val does not satisfy that */ 781 return -EINVAL; 782 if ((val & CPUCFG2_LASX) && !(val & CPUCFG2_LSX)) 783 /* LASX architecturally implies LSX and FP but val does not satisfy that */ 784 return -EINVAL; 785 return 0; 786 case LOONGARCH_CPUCFG3: 787 host = read_cpucfg(LOONGARCH_CPUCFG3); 788 if ((val & CPUCFG3_RVAMAX) > (host & CPUCFG3_RVAMAX)) 789 return -EINVAL; 790 if ((val & CPUCFG3_SPW_LVL) > (host & CPUCFG3_SPW_LVL)) 791 return -EINVAL; 792 return 0; 793 case LOONGARCH_CPUCFG6: 794 if (val & CPUCFG6_PMP) { 795 host = read_cpucfg(LOONGARCH_CPUCFG6); 796 if ((val & CPUCFG6_PMBITS) != (host & CPUCFG6_PMBITS)) 797 return -EINVAL; 798 if ((val & CPUCFG6_PMNUM) > (host & CPUCFG6_PMNUM)) 799 return -EINVAL; 800 if ((val & CPUCFG6_UPM) && !(host & CPUCFG6_UPM)) 801 return -EINVAL; 802 } 803 return 0; 804 default: 805 /* 806 * Values for the other CPUCFG IDs are not being further validated 807 * besides the mask check above. 808 */ 809 return 0; 810 } 811 } 812 813 static int kvm_get_one_reg(struct kvm_vcpu *vcpu, 814 const struct kvm_one_reg *reg, u64 *v) 815 { 816 int id, ret = 0; 817 u64 type = reg->id & KVM_REG_LOONGARCH_MASK; 818 819 switch (type) { 820 case KVM_REG_LOONGARCH_CSR: 821 id = KVM_GET_IOC_CSR_IDX(reg->id); 822 ret = _kvm_getcsr(vcpu, id, v); 823 break; 824 case KVM_REG_LOONGARCH_CPUCFG: 825 id = KVM_GET_IOC_CPUCFG_IDX(reg->id); 826 if (id >= 0 && id < KVM_MAX_CPUCFG_REGS) 827 *v = vcpu->arch.cpucfg[id]; 828 else 829 ret = -EINVAL; 830 break; 831 case KVM_REG_LOONGARCH_LBT: 832 if (!kvm_guest_has_lbt(&vcpu->arch)) 833 return -ENXIO; 834 835 switch (reg->id) { 836 case KVM_REG_LOONGARCH_LBT_SCR0: 837 *v = vcpu->arch.lbt.scr0; 838 break; 839 case KVM_REG_LOONGARCH_LBT_SCR1: 840 *v = vcpu->arch.lbt.scr1; 841 break; 842 case KVM_REG_LOONGARCH_LBT_SCR2: 843 *v = vcpu->arch.lbt.scr2; 844 break; 845 case KVM_REG_LOONGARCH_LBT_SCR3: 846 *v = vcpu->arch.lbt.scr3; 847 break; 848 case KVM_REG_LOONGARCH_LBT_EFLAGS: 849 *v = vcpu->arch.lbt.eflags; 850 break; 851 case KVM_REG_LOONGARCH_LBT_FTOP: 852 *v = vcpu->arch.fpu.ftop; 853 break; 854 default: 855 ret = -EINVAL; 856 break; 857 } 858 break; 859 case KVM_REG_LOONGARCH_KVM: 860 switch (reg->id) { 861 case KVM_REG_LOONGARCH_COUNTER: 862 *v = get_cycles() + vcpu->kvm->arch.time_offset; 863 break; 864 case KVM_REG_LOONGARCH_DEBUG_INST: 865 *v = INSN_HVCL | KVM_HCALL_SWDBG; 866 break; 867 default: 868 ret = -EINVAL; 869 break; 870 } 871 break; 872 default: 873 ret = -EINVAL; 874 break; 875 } 876 877 return ret; 878 } 879 880 static int kvm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 881 { 882 int ret = 0; 883 u64 v, size = reg->id & KVM_REG_SIZE_MASK; 884 885 switch (size) { 886 case KVM_REG_SIZE_U64: 887 ret = kvm_get_one_reg(vcpu, reg, &v); 888 if (ret) 889 return ret; 890 ret = put_user(v, (u64 __user *)(long)reg->addr); 891 break; 892 default: 893 ret = -EINVAL; 894 break; 895 } 896 897 return ret; 898 } 899 900 static int kvm_set_one_reg(struct kvm_vcpu *vcpu, 901 const struct kvm_one_reg *reg, u64 v) 902 { 903 int id, ret = 0; 904 u64 type = reg->id & KVM_REG_LOONGARCH_MASK; 905 906 switch (type) { 907 case KVM_REG_LOONGARCH_CSR: 908 id = KVM_GET_IOC_CSR_IDX(reg->id); 909 ret = _kvm_setcsr(vcpu, id, v); 910 break; 911 case KVM_REG_LOONGARCH_CPUCFG: 912 id = KVM_GET_IOC_CPUCFG_IDX(reg->id); 913 ret = kvm_check_cpucfg(id, v); 914 if (ret) 915 break; 916 vcpu->arch.cpucfg[id] = (u32)v; 917 if (id == LOONGARCH_CPUCFG6) 918 vcpu->arch.max_pmu_csrid = 919 LOONGARCH_CSR_PERFCTRL0 + 2 * kvm_get_pmu_num(&vcpu->arch) + 1; 920 break; 921 case KVM_REG_LOONGARCH_LBT: 922 if (!kvm_guest_has_lbt(&vcpu->arch)) 923 return -ENXIO; 924 925 switch (reg->id) { 926 case KVM_REG_LOONGARCH_LBT_SCR0: 927 vcpu->arch.lbt.scr0 = v; 928 break; 929 case KVM_REG_LOONGARCH_LBT_SCR1: 930 vcpu->arch.lbt.scr1 = v; 931 break; 932 case KVM_REG_LOONGARCH_LBT_SCR2: 933 vcpu->arch.lbt.scr2 = v; 934 break; 935 case KVM_REG_LOONGARCH_LBT_SCR3: 936 vcpu->arch.lbt.scr3 = v; 937 break; 938 case KVM_REG_LOONGARCH_LBT_EFLAGS: 939 vcpu->arch.lbt.eflags = v; 940 break; 941 case KVM_REG_LOONGARCH_LBT_FTOP: 942 vcpu->arch.fpu.ftop = v; 943 break; 944 default: 945 ret = -EINVAL; 946 break; 947 } 948 break; 949 case KVM_REG_LOONGARCH_KVM: 950 switch (reg->id) { 951 case KVM_REG_LOONGARCH_COUNTER: 952 /* 953 * gftoffset is relative with board, not vcpu 954 * only set for the first time for smp system 955 */ 956 if (vcpu->vcpu_id == 0) 957 vcpu->kvm->arch.time_offset = (signed long)(v - get_cycles()); 958 break; 959 case KVM_REG_LOONGARCH_VCPU_RESET: 960 vcpu->arch.st.guest_addr = 0; 961 memset(&vcpu->arch.irq_pending, 0, sizeof(vcpu->arch.irq_pending)); 962 memset(&vcpu->arch.irq_clear, 0, sizeof(vcpu->arch.irq_clear)); 963 964 /* 965 * When vCPU reset, clear the ESTAT and GINTC registers 966 * Other CSR registers are cleared with function _kvm_setcsr(). 967 */ 968 kvm_write_sw_gcsr(vcpu->arch.csr, LOONGARCH_CSR_GINTC, 0); 969 kvm_write_sw_gcsr(vcpu->arch.csr, LOONGARCH_CSR_ESTAT, 0); 970 break; 971 default: 972 ret = -EINVAL; 973 break; 974 } 975 break; 976 default: 977 ret = -EINVAL; 978 break; 979 } 980 981 return ret; 982 } 983 984 static int kvm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 985 { 986 int ret = 0; 987 u64 v, size = reg->id & KVM_REG_SIZE_MASK; 988 989 switch (size) { 990 case KVM_REG_SIZE_U64: 991 ret = get_user(v, (u64 __user *)(long)reg->addr); 992 if (ret) 993 return ret; 994 break; 995 default: 996 return -EINVAL; 997 } 998 999 return kvm_set_one_reg(vcpu, reg, v); 1000 } 1001 1002 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 1003 { 1004 return -ENOIOCTLCMD; 1005 } 1006 1007 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs) 1008 { 1009 return -ENOIOCTLCMD; 1010 } 1011 1012 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1013 { 1014 int i; 1015 1016 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1017 regs->gpr[i] = vcpu->arch.gprs[i]; 1018 1019 regs->pc = vcpu->arch.pc; 1020 1021 return 0; 1022 } 1023 1024 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) 1025 { 1026 int i; 1027 1028 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++) 1029 vcpu->arch.gprs[i] = regs->gpr[i]; 1030 1031 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */ 1032 vcpu->arch.pc = regs->pc; 1033 1034 return 0; 1035 } 1036 1037 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu, 1038 struct kvm_enable_cap *cap) 1039 { 1040 /* FPU is enabled by default, will support LSX/LASX later. */ 1041 return -EINVAL; 1042 } 1043 1044 static int kvm_loongarch_cpucfg_has_attr(struct kvm_vcpu *vcpu, 1045 struct kvm_device_attr *attr) 1046 { 1047 switch (attr->attr) { 1048 case LOONGARCH_CPUCFG2: 1049 case LOONGARCH_CPUCFG6: 1050 return 0; 1051 case CPUCFG_KVM_FEATURE: 1052 return 0; 1053 default: 1054 return -ENXIO; 1055 } 1056 1057 return -ENXIO; 1058 } 1059 1060 static int kvm_loongarch_pvtime_has_attr(struct kvm_vcpu *vcpu, 1061 struct kvm_device_attr *attr) 1062 { 1063 if (!kvm_guest_has_pv_feature(vcpu, KVM_FEATURE_STEAL_TIME) 1064 || attr->attr != KVM_LOONGARCH_VCPU_PVTIME_GPA) 1065 return -ENXIO; 1066 1067 return 0; 1068 } 1069 1070 static int kvm_loongarch_vcpu_has_attr(struct kvm_vcpu *vcpu, 1071 struct kvm_device_attr *attr) 1072 { 1073 int ret = -ENXIO; 1074 1075 switch (attr->group) { 1076 case KVM_LOONGARCH_VCPU_CPUCFG: 1077 ret = kvm_loongarch_cpucfg_has_attr(vcpu, attr); 1078 break; 1079 case KVM_LOONGARCH_VCPU_PVTIME_CTRL: 1080 ret = kvm_loongarch_pvtime_has_attr(vcpu, attr); 1081 break; 1082 default: 1083 break; 1084 } 1085 1086 return ret; 1087 } 1088 1089 static int kvm_loongarch_cpucfg_get_attr(struct kvm_vcpu *vcpu, 1090 struct kvm_device_attr *attr) 1091 { 1092 int ret = 0; 1093 uint64_t val; 1094 uint64_t __user *uaddr = (uint64_t __user *)attr->addr; 1095 1096 switch (attr->attr) { 1097 case 0 ... (KVM_MAX_CPUCFG_REGS - 1): 1098 ret = _kvm_get_cpucfg_mask(attr->attr, &val); 1099 if (ret) 1100 return ret; 1101 break; 1102 case CPUCFG_KVM_FEATURE: 1103 val = vcpu->kvm->arch.pv_features & LOONGARCH_PV_FEAT_MASK; 1104 break; 1105 default: 1106 return -ENXIO; 1107 } 1108 1109 put_user(val, uaddr); 1110 1111 return ret; 1112 } 1113 1114 static int kvm_loongarch_pvtime_get_attr(struct kvm_vcpu *vcpu, 1115 struct kvm_device_attr *attr) 1116 { 1117 u64 gpa; 1118 u64 __user *user = (u64 __user *)attr->addr; 1119 1120 if (!kvm_guest_has_pv_feature(vcpu, KVM_FEATURE_STEAL_TIME) 1121 || attr->attr != KVM_LOONGARCH_VCPU_PVTIME_GPA) 1122 return -ENXIO; 1123 1124 gpa = vcpu->arch.st.guest_addr; 1125 if (put_user(gpa, user)) 1126 return -EFAULT; 1127 1128 return 0; 1129 } 1130 1131 static int kvm_loongarch_vcpu_get_attr(struct kvm_vcpu *vcpu, 1132 struct kvm_device_attr *attr) 1133 { 1134 int ret = -ENXIO; 1135 1136 switch (attr->group) { 1137 case KVM_LOONGARCH_VCPU_CPUCFG: 1138 ret = kvm_loongarch_cpucfg_get_attr(vcpu, attr); 1139 break; 1140 case KVM_LOONGARCH_VCPU_PVTIME_CTRL: 1141 ret = kvm_loongarch_pvtime_get_attr(vcpu, attr); 1142 break; 1143 default: 1144 break; 1145 } 1146 1147 return ret; 1148 } 1149 1150 static int kvm_loongarch_cpucfg_set_attr(struct kvm_vcpu *vcpu, 1151 struct kvm_device_attr *attr) 1152 { 1153 u64 val, valid; 1154 u64 __user *user = (u64 __user *)attr->addr; 1155 struct kvm *kvm = vcpu->kvm; 1156 1157 switch (attr->attr) { 1158 case CPUCFG_KVM_FEATURE: 1159 if (get_user(val, user)) 1160 return -EFAULT; 1161 1162 valid = LOONGARCH_PV_FEAT_MASK; 1163 if (val & ~valid) 1164 return -EINVAL; 1165 1166 /* All vCPUs need set the same PV features */ 1167 if ((kvm->arch.pv_features & LOONGARCH_PV_FEAT_UPDATED) 1168 && ((kvm->arch.pv_features & valid) != val)) 1169 return -EINVAL; 1170 kvm->arch.pv_features = val | LOONGARCH_PV_FEAT_UPDATED; 1171 return 0; 1172 default: 1173 return -ENXIO; 1174 } 1175 } 1176 1177 static int kvm_loongarch_pvtime_set_attr(struct kvm_vcpu *vcpu, 1178 struct kvm_device_attr *attr) 1179 { 1180 int idx, ret = 0; 1181 u64 gpa, __user *user = (u64 __user *)attr->addr; 1182 struct kvm *kvm = vcpu->kvm; 1183 1184 if (!kvm_guest_has_pv_feature(vcpu, KVM_FEATURE_STEAL_TIME) 1185 || attr->attr != KVM_LOONGARCH_VCPU_PVTIME_GPA) 1186 return -ENXIO; 1187 1188 if (get_user(gpa, user)) 1189 return -EFAULT; 1190 1191 if (gpa & ~(KVM_STEAL_PHYS_MASK | KVM_STEAL_PHYS_VALID)) 1192 return -EINVAL; 1193 1194 if (!(gpa & KVM_STEAL_PHYS_VALID)) { 1195 vcpu->arch.st.guest_addr = gpa; 1196 return 0; 1197 } 1198 1199 /* Check the address is in a valid memslot */ 1200 idx = srcu_read_lock(&kvm->srcu); 1201 if (kvm_is_error_hva(gfn_to_hva(kvm, gpa >> PAGE_SHIFT))) 1202 ret = -EINVAL; 1203 srcu_read_unlock(&kvm->srcu, idx); 1204 1205 if (!ret) { 1206 vcpu->arch.st.guest_addr = gpa; 1207 vcpu->arch.st.last_steal = current->sched_info.run_delay; 1208 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 1209 } 1210 1211 return ret; 1212 } 1213 1214 static int kvm_loongarch_vcpu_set_attr(struct kvm_vcpu *vcpu, 1215 struct kvm_device_attr *attr) 1216 { 1217 int ret = -ENXIO; 1218 1219 switch (attr->group) { 1220 case KVM_LOONGARCH_VCPU_CPUCFG: 1221 ret = kvm_loongarch_cpucfg_set_attr(vcpu, attr); 1222 break; 1223 case KVM_LOONGARCH_VCPU_PVTIME_CTRL: 1224 ret = kvm_loongarch_pvtime_set_attr(vcpu, attr); 1225 break; 1226 default: 1227 break; 1228 } 1229 1230 return ret; 1231 } 1232 1233 long kvm_arch_vcpu_ioctl(struct file *filp, 1234 unsigned int ioctl, unsigned long arg) 1235 { 1236 long r; 1237 struct kvm_device_attr attr; 1238 void __user *argp = (void __user *)arg; 1239 struct kvm_vcpu *vcpu = filp->private_data; 1240 1241 /* 1242 * Only software CSR should be modified 1243 * 1244 * If any hardware CSR register is modified, vcpu_load/vcpu_put pair 1245 * should be used. Since CSR registers owns by this vcpu, if switch 1246 * to other vcpus, other vcpus need reload CSR registers. 1247 * 1248 * If software CSR is modified, bit KVM_LARCH_HWCSR_USABLE should 1249 * be clear in vcpu->arch.aux_inuse, and vcpu_load will check 1250 * aux_inuse flag and reload CSR registers form software. 1251 */ 1252 1253 switch (ioctl) { 1254 case KVM_SET_ONE_REG: 1255 case KVM_GET_ONE_REG: { 1256 struct kvm_one_reg reg; 1257 1258 r = -EFAULT; 1259 if (copy_from_user(®, argp, sizeof(reg))) 1260 break; 1261 if (ioctl == KVM_SET_ONE_REG) { 1262 r = kvm_set_reg(vcpu, ®); 1263 vcpu->arch.aux_inuse &= ~KVM_LARCH_HWCSR_USABLE; 1264 } else 1265 r = kvm_get_reg(vcpu, ®); 1266 break; 1267 } 1268 case KVM_ENABLE_CAP: { 1269 struct kvm_enable_cap cap; 1270 1271 r = -EFAULT; 1272 if (copy_from_user(&cap, argp, sizeof(cap))) 1273 break; 1274 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap); 1275 break; 1276 } 1277 case KVM_HAS_DEVICE_ATTR: { 1278 r = -EFAULT; 1279 if (copy_from_user(&attr, argp, sizeof(attr))) 1280 break; 1281 r = kvm_loongarch_vcpu_has_attr(vcpu, &attr); 1282 break; 1283 } 1284 case KVM_GET_DEVICE_ATTR: { 1285 r = -EFAULT; 1286 if (copy_from_user(&attr, argp, sizeof(attr))) 1287 break; 1288 r = kvm_loongarch_vcpu_get_attr(vcpu, &attr); 1289 break; 1290 } 1291 case KVM_SET_DEVICE_ATTR: { 1292 r = -EFAULT; 1293 if (copy_from_user(&attr, argp, sizeof(attr))) 1294 break; 1295 r = kvm_loongarch_vcpu_set_attr(vcpu, &attr); 1296 break; 1297 } 1298 default: 1299 r = -ENOIOCTLCMD; 1300 break; 1301 } 1302 1303 return r; 1304 } 1305 1306 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1307 { 1308 int i = 0; 1309 1310 fpu->fcc = vcpu->arch.fpu.fcc; 1311 fpu->fcsr = vcpu->arch.fpu.fcsr; 1312 for (i = 0; i < NUM_FPU_REGS; i++) 1313 memcpy(&fpu->fpr[i], &vcpu->arch.fpu.fpr[i], FPU_REG_WIDTH / 64); 1314 1315 return 0; 1316 } 1317 1318 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu) 1319 { 1320 int i = 0; 1321 1322 vcpu->arch.fpu.fcc = fpu->fcc; 1323 vcpu->arch.fpu.fcsr = fpu->fcsr; 1324 for (i = 0; i < NUM_FPU_REGS; i++) 1325 memcpy(&vcpu->arch.fpu.fpr[i], &fpu->fpr[i], FPU_REG_WIDTH / 64); 1326 1327 return 0; 1328 } 1329 1330 #ifdef CONFIG_CPU_HAS_LBT 1331 int kvm_own_lbt(struct kvm_vcpu *vcpu) 1332 { 1333 if (!(vcpu->arch.aux_inuse & KVM_LARCH_LBT)) { 1334 set_csr_euen(CSR_EUEN_LBTEN); 1335 _restore_lbt(&vcpu->arch.lbt); 1336 vcpu->arch.aux_inuse |= KVM_LARCH_LBT; 1337 } 1338 1339 return 0; 1340 } 1341 1342 static void kvm_lose_lbt(struct kvm_vcpu *vcpu) 1343 { 1344 preempt_disable(); 1345 if (vcpu->arch.aux_inuse & KVM_LARCH_LBT) { 1346 _save_lbt(&vcpu->arch.lbt); 1347 clear_csr_euen(CSR_EUEN_LBTEN); 1348 vcpu->arch.aux_inuse &= ~KVM_LARCH_LBT; 1349 } 1350 preempt_enable(); 1351 } 1352 1353 static void kvm_check_fcsr(struct kvm_vcpu *vcpu, unsigned long fcsr) 1354 { 1355 /* 1356 * If TM is enabled, top register save/restore will 1357 * cause lbt exception, here enable lbt in advance 1358 */ 1359 if (fcsr & FPU_CSR_TM) 1360 kvm_own_lbt(vcpu); 1361 } 1362 1363 static void kvm_check_fcsr_alive(struct kvm_vcpu *vcpu) 1364 { 1365 if (vcpu->arch.aux_inuse & KVM_LARCH_FPU) { 1366 if (vcpu->arch.aux_inuse & KVM_LARCH_LBT) 1367 return; 1368 kvm_check_fcsr(vcpu, read_fcsr(LOONGARCH_FCSR0)); 1369 } 1370 } 1371 #else 1372 static inline void kvm_lose_lbt(struct kvm_vcpu *vcpu) { } 1373 static inline void kvm_check_fcsr(struct kvm_vcpu *vcpu, unsigned long fcsr) { } 1374 static inline void kvm_check_fcsr_alive(struct kvm_vcpu *vcpu) { } 1375 #endif 1376 1377 /* Enable FPU and restore context */ 1378 void kvm_own_fpu(struct kvm_vcpu *vcpu) 1379 { 1380 /* 1381 * Enable FPU for guest 1382 * Set FR and FRE according to guest context 1383 */ 1384 kvm_check_fcsr(vcpu, vcpu->arch.fpu.fcsr); 1385 set_csr_euen(CSR_EUEN_FPEN); 1386 1387 kvm_restore_fpu(&vcpu->arch.fpu); 1388 vcpu->arch.aux_inuse |= KVM_LARCH_FPU; 1389 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU); 1390 } 1391 1392 #ifdef CONFIG_CPU_HAS_LSX 1393 /* Enable LSX and restore context */ 1394 int kvm_own_lsx(struct kvm_vcpu *vcpu) 1395 { 1396 /* Enable LSX for guest */ 1397 kvm_check_fcsr(vcpu, vcpu->arch.fpu.fcsr); 1398 set_csr_euen(CSR_EUEN_LSXEN | CSR_EUEN_FPEN); 1399 switch (vcpu->arch.aux_inuse & KVM_LARCH_FPU) { 1400 case KVM_LARCH_FPU: 1401 /* 1402 * Guest FPU state already loaded, 1403 * only restore upper LSX state 1404 */ 1405 _restore_lsx_upper(&vcpu->arch.fpu); 1406 break; 1407 default: 1408 /* Neither FP or LSX already active, 1409 * restore full LSX state 1410 */ 1411 kvm_restore_lsx(&vcpu->arch.fpu); 1412 break; 1413 } 1414 1415 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_LSX); 1416 vcpu->arch.aux_inuse |= KVM_LARCH_LSX | KVM_LARCH_FPU; 1417 1418 return 0; 1419 } 1420 #endif 1421 1422 #ifdef CONFIG_CPU_HAS_LASX 1423 /* Enable LASX and restore context */ 1424 int kvm_own_lasx(struct kvm_vcpu *vcpu) 1425 { 1426 kvm_check_fcsr(vcpu, vcpu->arch.fpu.fcsr); 1427 set_csr_euen(CSR_EUEN_FPEN | CSR_EUEN_LSXEN | CSR_EUEN_LASXEN); 1428 switch (vcpu->arch.aux_inuse & (KVM_LARCH_FPU | KVM_LARCH_LSX)) { 1429 case KVM_LARCH_LSX: 1430 case KVM_LARCH_LSX | KVM_LARCH_FPU: 1431 /* Guest LSX state already loaded, only restore upper LASX state */ 1432 _restore_lasx_upper(&vcpu->arch.fpu); 1433 break; 1434 case KVM_LARCH_FPU: 1435 /* Guest FP state already loaded, only restore upper LSX & LASX state */ 1436 _restore_lsx_upper(&vcpu->arch.fpu); 1437 _restore_lasx_upper(&vcpu->arch.fpu); 1438 break; 1439 default: 1440 /* Neither FP or LSX already active, restore full LASX state */ 1441 kvm_restore_lasx(&vcpu->arch.fpu); 1442 break; 1443 } 1444 1445 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_LASX); 1446 vcpu->arch.aux_inuse |= KVM_LARCH_LASX | KVM_LARCH_LSX | KVM_LARCH_FPU; 1447 1448 return 0; 1449 } 1450 #endif 1451 1452 /* Save context and disable FPU */ 1453 void kvm_lose_fpu(struct kvm_vcpu *vcpu) 1454 { 1455 preempt_disable(); 1456 1457 kvm_check_fcsr_alive(vcpu); 1458 if (vcpu->arch.aux_inuse & KVM_LARCH_LASX) { 1459 kvm_save_lasx(&vcpu->arch.fpu); 1460 vcpu->arch.aux_inuse &= ~(KVM_LARCH_LSX | KVM_LARCH_FPU | KVM_LARCH_LASX); 1461 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_LASX); 1462 1463 /* Disable LASX & LSX & FPU */ 1464 clear_csr_euen(CSR_EUEN_FPEN | CSR_EUEN_LSXEN | CSR_EUEN_LASXEN); 1465 } else if (vcpu->arch.aux_inuse & KVM_LARCH_LSX) { 1466 kvm_save_lsx(&vcpu->arch.fpu); 1467 vcpu->arch.aux_inuse &= ~(KVM_LARCH_LSX | KVM_LARCH_FPU); 1468 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_LSX); 1469 1470 /* Disable LSX & FPU */ 1471 clear_csr_euen(CSR_EUEN_FPEN | CSR_EUEN_LSXEN); 1472 } else if (vcpu->arch.aux_inuse & KVM_LARCH_FPU) { 1473 kvm_save_fpu(&vcpu->arch.fpu); 1474 vcpu->arch.aux_inuse &= ~KVM_LARCH_FPU; 1475 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU); 1476 1477 /* Disable FPU */ 1478 clear_csr_euen(CSR_EUEN_FPEN); 1479 } 1480 kvm_lose_lbt(vcpu); 1481 1482 preempt_enable(); 1483 } 1484 1485 int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu, struct kvm_interrupt *irq) 1486 { 1487 int intr = (int)irq->irq; 1488 1489 if (intr > 0) 1490 kvm_queue_irq(vcpu, intr); 1491 else if (intr < 0) 1492 kvm_dequeue_irq(vcpu, -intr); 1493 else { 1494 kvm_err("%s: invalid interrupt ioctl %d\n", __func__, irq->irq); 1495 return -EINVAL; 1496 } 1497 1498 kvm_vcpu_kick(vcpu); 1499 1500 return 0; 1501 } 1502 1503 long kvm_arch_vcpu_unlocked_ioctl(struct file *filp, unsigned int ioctl, 1504 unsigned long arg) 1505 { 1506 void __user *argp = (void __user *)arg; 1507 struct kvm_vcpu *vcpu = filp->private_data; 1508 1509 if (ioctl == KVM_INTERRUPT) { 1510 struct kvm_interrupt irq; 1511 1512 if (copy_from_user(&irq, argp, sizeof(irq))) 1513 return -EFAULT; 1514 1515 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__, irq.irq); 1516 1517 return kvm_vcpu_ioctl_interrupt(vcpu, &irq); 1518 } 1519 1520 return -ENOIOCTLCMD; 1521 } 1522 1523 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id) 1524 { 1525 return 0; 1526 } 1527 1528 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) 1529 { 1530 unsigned long timer_hz; 1531 struct loongarch_csrs *csr; 1532 1533 vcpu->arch.vpid = 0; 1534 vcpu->arch.flush_gpa = INVALID_GPA; 1535 1536 hrtimer_setup(&vcpu->arch.swtimer, kvm_swtimer_wakeup, CLOCK_MONOTONIC, 1537 HRTIMER_MODE_ABS_PINNED_HARD); 1538 1539 /* Get GPA (=HVA) of PGD for kvm hypervisor */ 1540 vcpu->arch.kvm_pgd = __pa(vcpu->kvm->arch.pgd); 1541 1542 /* 1543 * Get PGD for primary mmu, virtual address is used since there is 1544 * memory access after loading from CSR_PGD in tlb exception fast path. 1545 */ 1546 vcpu->arch.host_pgd = (unsigned long)vcpu->kvm->mm->pgd; 1547 1548 vcpu->arch.handle_exit = kvm_handle_exit; 1549 vcpu->arch.guest_eentry = (unsigned long)kvm_loongarch_ops->exc_entry; 1550 vcpu->arch.csr = kzalloc(sizeof(struct loongarch_csrs), GFP_KERNEL); 1551 if (!vcpu->arch.csr) 1552 return -ENOMEM; 1553 1554 /* 1555 * All kvm exceptions share one exception entry, and host <-> guest 1556 * switch also switch ECFG.VS field, keep host ECFG.VS info here. 1557 */ 1558 vcpu->arch.host_ecfg = (read_csr_ecfg() & CSR_ECFG_VS); 1559 1560 /* Init */ 1561 vcpu->arch.last_sched_cpu = -1; 1562 1563 /* Init ipi_state lock */ 1564 spin_lock_init(&vcpu->arch.ipi_state.lock); 1565 1566 /* 1567 * Initialize guest register state to valid architectural reset state. 1568 */ 1569 timer_hz = calc_const_freq(); 1570 kvm_init_timer(vcpu, timer_hz); 1571 1572 /* Set Initialize mode for guest */ 1573 csr = vcpu->arch.csr; 1574 kvm_write_sw_gcsr(csr, LOONGARCH_CSR_CRMD, CSR_CRMD_DA); 1575 1576 /* Set cpuid */ 1577 kvm_write_sw_gcsr(csr, LOONGARCH_CSR_TMID, vcpu->vcpu_id); 1578 kvm_write_sw_gcsr(csr, LOONGARCH_CSR_CPUID, KVM_MAX_PHYID); 1579 1580 /* Start with no pending virtual guest interrupts */ 1581 csr->csrs[LOONGARCH_CSR_GINTC] = 0; 1582 1583 return 0; 1584 } 1585 1586 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu) 1587 { 1588 } 1589 1590 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu) 1591 { 1592 int cpu; 1593 struct kvm_context *context; 1594 1595 hrtimer_cancel(&vcpu->arch.swtimer); 1596 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_cache); 1597 kvm_drop_cpuid(vcpu); 1598 kfree(vcpu->arch.csr); 1599 1600 /* 1601 * If the vCPU is freed and reused as another vCPU, we don't want the 1602 * matching pointer wrongly hanging around in last_vcpu. 1603 */ 1604 for_each_possible_cpu(cpu) { 1605 context = per_cpu_ptr(vcpu->kvm->arch.vmcs, cpu); 1606 if (context->last_vcpu == vcpu) 1607 context->last_vcpu = NULL; 1608 } 1609 } 1610 1611 static int _kvm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 1612 { 1613 bool migrated; 1614 struct kvm_context *context; 1615 struct loongarch_csrs *csr = vcpu->arch.csr; 1616 1617 /* 1618 * Have we migrated to a different CPU? 1619 * If so, any old guest TLB state may be stale. 1620 */ 1621 migrated = (vcpu->arch.last_sched_cpu != cpu); 1622 1623 /* 1624 * Was this the last vCPU to run on this CPU? 1625 * If not, any old guest state from this vCPU will have been clobbered. 1626 */ 1627 context = per_cpu_ptr(vcpu->kvm->arch.vmcs, cpu); 1628 if (migrated || (context->last_vcpu != vcpu)) 1629 vcpu->arch.aux_inuse &= ~KVM_LARCH_HWCSR_USABLE; 1630 context->last_vcpu = vcpu; 1631 1632 /* Restore timer state regardless */ 1633 kvm_restore_timer(vcpu); 1634 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); 1635 1636 /* Don't bother restoring registers multiple times unless necessary */ 1637 if (vcpu->arch.aux_inuse & KVM_LARCH_HWCSR_USABLE) 1638 return 0; 1639 1640 write_csr_gcntc((ulong)vcpu->kvm->arch.time_offset); 1641 1642 /* Restore guest CSR registers */ 1643 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_CRMD); 1644 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PRMD); 1645 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_EUEN); 1646 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_MISC); 1647 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ECFG); 1648 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ERA); 1649 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_BADV); 1650 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_BADI); 1651 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_EENTRY); 1652 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBIDX); 1653 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBEHI); 1654 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBELO0); 1655 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBELO1); 1656 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ASID); 1657 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PGDL); 1658 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PGDH); 1659 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PWCTL0); 1660 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_PWCTL1); 1661 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_STLBPGSIZE); 1662 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_RVACFG); 1663 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_CPUID); 1664 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS0); 1665 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS1); 1666 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS2); 1667 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS3); 1668 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS4); 1669 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS5); 1670 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS6); 1671 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_KS7); 1672 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TMID); 1673 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_CNTC); 1674 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRENTRY); 1675 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRBADV); 1676 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRERA); 1677 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRSAVE); 1678 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRELO0); 1679 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRELO1); 1680 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBREHI); 1681 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_TLBRPRMD); 1682 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_DMWIN0); 1683 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_DMWIN1); 1684 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_DMWIN2); 1685 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_DMWIN3); 1686 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_LLBCTL); 1687 1688 if (kvm_guest_has_msgint(&vcpu->arch)) { 1689 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_IPR); 1690 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ISR0); 1691 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ISR1); 1692 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ISR2); 1693 kvm_restore_hw_gcsr(csr, LOONGARCH_CSR_ISR3); 1694 } 1695 1696 /* Restore Root.GINTC from unused Guest.GINTC register */ 1697 write_csr_gintc(csr->csrs[LOONGARCH_CSR_GINTC]); 1698 1699 /* 1700 * We should clear linked load bit to break interrupted atomics. This 1701 * prevents a SC on the next vCPU from succeeding by matching a LL on 1702 * the previous vCPU. 1703 */ 1704 if (vcpu->kvm->created_vcpus > 1) 1705 set_gcsr_llbctl(CSR_LLBCTL_WCLLB); 1706 1707 vcpu->arch.aux_inuse |= KVM_LARCH_HWCSR_USABLE; 1708 1709 return 0; 1710 } 1711 1712 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 1713 { 1714 unsigned long flags; 1715 1716 local_irq_save(flags); 1717 /* Restore guest state to registers */ 1718 _kvm_vcpu_load(vcpu, cpu); 1719 local_irq_restore(flags); 1720 } 1721 1722 static int _kvm_vcpu_put(struct kvm_vcpu *vcpu, int cpu) 1723 { 1724 struct loongarch_csrs *csr = vcpu->arch.csr; 1725 1726 kvm_lose_fpu(vcpu); 1727 1728 /* 1729 * Update CSR state from hardware if software CSR state is stale, 1730 * most CSR registers are kept unchanged during process context 1731 * switch except CSR registers like remaining timer tick value and 1732 * injected interrupt state. 1733 */ 1734 if (vcpu->arch.aux_inuse & KVM_LARCH_SWCSR_LATEST) 1735 goto out; 1736 1737 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_CRMD); 1738 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PRMD); 1739 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_EUEN); 1740 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_MISC); 1741 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ECFG); 1742 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ERA); 1743 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_BADV); 1744 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_BADI); 1745 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_EENTRY); 1746 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBIDX); 1747 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBEHI); 1748 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBELO0); 1749 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBELO1); 1750 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ASID); 1751 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PGDL); 1752 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PGDH); 1753 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PWCTL0); 1754 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PWCTL1); 1755 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_STLBPGSIZE); 1756 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_RVACFG); 1757 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_CPUID); 1758 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PRCFG1); 1759 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PRCFG2); 1760 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_PRCFG3); 1761 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS0); 1762 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS1); 1763 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS2); 1764 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS3); 1765 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS4); 1766 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS5); 1767 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS6); 1768 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_KS7); 1769 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TMID); 1770 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_CNTC); 1771 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_LLBCTL); 1772 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRENTRY); 1773 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRBADV); 1774 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRERA); 1775 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRSAVE); 1776 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRELO0); 1777 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRELO1); 1778 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBREHI); 1779 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_TLBRPRMD); 1780 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_DMWIN0); 1781 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_DMWIN1); 1782 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_DMWIN2); 1783 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_DMWIN3); 1784 1785 if (kvm_guest_has_msgint(&vcpu->arch)) { 1786 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_IPR); 1787 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ISR0); 1788 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ISR1); 1789 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ISR2); 1790 kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ISR3); 1791 } 1792 1793 vcpu->arch.aux_inuse |= KVM_LARCH_SWCSR_LATEST; 1794 1795 out: 1796 kvm_save_timer(vcpu); 1797 /* Save Root.GINTC into unused Guest.GINTC register */ 1798 csr->csrs[LOONGARCH_CSR_GINTC] = read_csr_gintc(); 1799 1800 return 0; 1801 } 1802 1803 static void kvm_vcpu_set_pv_preempted(struct kvm_vcpu *vcpu) 1804 { 1805 gpa_t gpa; 1806 struct gfn_to_hva_cache *ghc; 1807 struct kvm_memslots *slots; 1808 struct kvm_steal_time __user *st; 1809 1810 gpa = vcpu->arch.st.guest_addr; 1811 if (!(gpa & KVM_STEAL_PHYS_VALID)) 1812 return; 1813 1814 /* vCPU may be preempted for many times */ 1815 if (vcpu->arch.st.preempted) 1816 return; 1817 1818 /* This happens on process exit */ 1819 if (unlikely(current->mm != vcpu->kvm->mm)) 1820 return; 1821 1822 gpa &= KVM_STEAL_PHYS_MASK; 1823 ghc = &vcpu->arch.st.cache; 1824 slots = kvm_memslots(vcpu->kvm); 1825 if (slots->generation != ghc->generation || gpa != ghc->gpa) { 1826 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st))) { 1827 ghc->gpa = INVALID_GPA; 1828 return; 1829 } 1830 } 1831 1832 st = (struct kvm_steal_time __user *)ghc->hva; 1833 unsafe_put_user(KVM_VCPU_PREEMPTED, &st->preempted, out); 1834 vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED; 1835 out: 1836 mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa)); 1837 } 1838 1839 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) 1840 { 1841 int cpu, idx; 1842 unsigned long flags; 1843 1844 if (vcpu->preempted && kvm_guest_has_pv_feature(vcpu, KVM_FEATURE_PREEMPT)) { 1845 /* 1846 * Take the srcu lock as memslots will be accessed to check 1847 * the gfn cache generation against the memslots generation. 1848 */ 1849 idx = srcu_read_lock(&vcpu->kvm->srcu); 1850 kvm_vcpu_set_pv_preempted(vcpu); 1851 srcu_read_unlock(&vcpu->kvm->srcu, idx); 1852 } 1853 1854 local_irq_save(flags); 1855 cpu = smp_processor_id(); 1856 vcpu->arch.last_sched_cpu = cpu; 1857 1858 /* Save guest state in registers */ 1859 _kvm_vcpu_put(vcpu, cpu); 1860 local_irq_restore(flags); 1861 } 1862 1863 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) 1864 { 1865 int r = -EINTR; 1866 struct kvm_run *run = vcpu->run; 1867 1868 if (vcpu->mmio_needed) { 1869 if (!vcpu->mmio_is_write) 1870 kvm_complete_mmio_read(vcpu, run); 1871 vcpu->mmio_needed = 0; 1872 } 1873 1874 switch (run->exit_reason) { 1875 case KVM_EXIT_HYPERCALL: 1876 kvm_complete_user_service(vcpu, run); 1877 break; 1878 case KVM_EXIT_LOONGARCH_IOCSR: 1879 if (!run->iocsr_io.is_write) 1880 kvm_complete_iocsr_read(vcpu, run); 1881 break; 1882 } 1883 1884 if (!vcpu->wants_to_run) 1885 return r; 1886 1887 /* Clear exit_reason */ 1888 run->exit_reason = KVM_EXIT_UNKNOWN; 1889 lose_fpu(1); 1890 vcpu_load(vcpu); 1891 kvm_sigset_activate(vcpu); 1892 r = kvm_pre_enter_guest(vcpu); 1893 if (r != RESUME_GUEST) 1894 goto out; 1895 1896 guest_timing_enter_irqoff(); 1897 guest_state_enter_irqoff(); 1898 trace_kvm_enter(vcpu); 1899 r = kvm_loongarch_ops->enter_guest(run, vcpu); 1900 1901 trace_kvm_out(vcpu); 1902 /* 1903 * Guest exit is already recorded at kvm_handle_exit() 1904 * return value must not be RESUME_GUEST 1905 */ 1906 local_irq_enable(); 1907 out: 1908 kvm_sigset_deactivate(vcpu); 1909 vcpu_put(vcpu); 1910 1911 return r; 1912 } 1913