1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Per core/cpu state
4 *
5 * Used to coordinate shared registers between HT threads or
6 * among events on a single PMU.
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/stddef.h>
12 #include <linux/types.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/export.h>
16 #include <linux/nmi.h>
17 #include <linux/kvm_host.h>
18
19 #include <asm/cpufeature.h>
20 #include <asm/cpuid/api.h>
21 #include <asm/debugreg.h>
22 #include <asm/hardirq.h>
23 #include <asm/intel-family.h>
24 #include <asm/intel_pt.h>
25 #include <asm/apic.h>
26 #include <asm/cpu_device_id.h>
27 #include <asm/msr.h>
28
29 #include "../perf_event.h"
30
31 /*
32 * Intel PerfMon, used on Core and later.
33 */
34 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
35 {
36 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
37 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
38 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
39 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
40 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
41 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
42 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
43 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
44 };
45
46 static struct event_constraint intel_core_event_constraints[] __read_mostly =
47 {
48 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
49 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
50 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
51 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
52 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
53 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
54 EVENT_CONSTRAINT_END
55 };
56
57 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
58 {
59 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
60 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
61 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
62 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
63 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
64 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
65 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
66 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
67 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
68 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
69 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
70 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
71 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
72 EVENT_CONSTRAINT_END
73 };
74
75 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
76 {
77 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
78 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
79 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
80 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
81 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
82 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
83 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
84 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
85 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
86 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
87 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
88 EVENT_CONSTRAINT_END
89 };
90
91 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
92 {
93 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
94 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
95 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
96 EVENT_EXTRA_END
97 };
98
99 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
100 {
101 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
102 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
103 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
104 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
105 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
106 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
107 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
108 EVENT_CONSTRAINT_END
109 };
110
111 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
112 {
113 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
114 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
115 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
116 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
117 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
118 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
119 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
120 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
121 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
122 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
123 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
124 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
125
126 /*
127 * When HT is off these events can only run on the bottom 4 counters
128 * When HT is on, they are impacted by the HT bug and require EXCL access
129 */
130 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
131 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
132 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
133 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
134
135 EVENT_CONSTRAINT_END
136 };
137
138 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
139 {
140 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
141 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
142 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
143 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
144 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMPTY */
145 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
146 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
147 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
148 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
149 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
150 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
151 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
152 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
153
154 /*
155 * When HT is off these events can only run on the bottom 4 counters
156 * When HT is on, they are impacted by the HT bug and require EXCL access
157 */
158 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
159 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
160 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
161 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
162
163 EVENT_CONSTRAINT_END
164 };
165
166 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
167 {
168 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
169 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
170 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
171 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
172 EVENT_EXTRA_END
173 };
174
175 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
176 {
177 EVENT_CONSTRAINT_END
178 };
179
180 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
181 {
182 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
183 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
184 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
185 EVENT_CONSTRAINT_END
186 };
187
188 static struct event_constraint intel_v5_gen_event_constraints[] __read_mostly =
189 {
190 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
191 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
192 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
193 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
194 FIXED_EVENT_CONSTRAINT(0x0500, 4),
195 FIXED_EVENT_CONSTRAINT(0x0600, 5),
196 FIXED_EVENT_CONSTRAINT(0x0700, 6),
197 FIXED_EVENT_CONSTRAINT(0x0800, 7),
198 FIXED_EVENT_CONSTRAINT(0x0900, 8),
199 FIXED_EVENT_CONSTRAINT(0x0a00, 9),
200 FIXED_EVENT_CONSTRAINT(0x0b00, 10),
201 FIXED_EVENT_CONSTRAINT(0x0c00, 11),
202 FIXED_EVENT_CONSTRAINT(0x0d00, 12),
203 FIXED_EVENT_CONSTRAINT(0x0e00, 13),
204 FIXED_EVENT_CONSTRAINT(0x0f00, 14),
205 FIXED_EVENT_CONSTRAINT(0x1000, 15),
206 EVENT_CONSTRAINT_END
207 };
208
209 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
210 {
211 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
212 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
213 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
214 EVENT_CONSTRAINT_END
215 };
216
217 static struct event_constraint intel_grt_event_constraints[] __read_mostly = {
218 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
219 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
220 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
221 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
222 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
223 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
224 EVENT_CONSTRAINT_END
225 };
226
227 static struct event_constraint intel_skt_event_constraints[] __read_mostly = {
228 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
229 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
230 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
231 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
232 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
233 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
234 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
235 FIXED_EVENT_CONSTRAINT(0x0500, 4), /* pseudo TOPDOWN_BAD_SPECULATION.ALL */
236 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
237 FIXED_EVENT_CONSTRAINT(0x0600, 5), /* pseudo TOPDOWN_FE_BOUND.ALL */
238 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
239 FIXED_EVENT_CONSTRAINT(0x0700, 6), /* pseudo TOPDOWN_RETIRING.ALL */
240 EVENT_CONSTRAINT_END
241 };
242
243 static struct event_constraint intel_arw_event_constraints[] __read_mostly = {
244 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
245 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
246 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
247 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
248 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
249 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
250 FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
251 FIXED_EVENT_CONSTRAINT(0x0500, 4), /* pseudo TOPDOWN_BAD_SPECULATION.ALL */
252 FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
253 FIXED_EVENT_CONSTRAINT(0x0600, 5), /* pseudo TOPDOWN_FE_BOUND.ALL */
254 FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
255 FIXED_EVENT_CONSTRAINT(0x0700, 6), /* pseudo TOPDOWN_RETIRING.ALL */
256 INTEL_UEVENT_CONSTRAINT(0x01b7, 0x1),
257 INTEL_UEVENT_CONSTRAINT(0x02b7, 0x2),
258 INTEL_UEVENT_CONSTRAINT(0x04b7, 0x4),
259 INTEL_UEVENT_CONSTRAINT(0x08b7, 0x8),
260 INTEL_UEVENT_CONSTRAINT(0x0175, 0x1),
261 INTEL_UEVENT_CONSTRAINT(0x0275, 0x2),
262 INTEL_UEVENT_CONSTRAINT(0x21d3, 0x1),
263 INTEL_UEVENT_CONSTRAINT(0x22d3, 0x1),
264 EVENT_CONSTRAINT_END
265 };
266
267 static struct event_constraint intel_skl_event_constraints[] = {
268 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
269 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
270 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
271 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
272
273 /*
274 * when HT is off, these can only run on the bottom 4 counters
275 */
276 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
277 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
278 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
279 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
280 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
281
282 EVENT_CONSTRAINT_END
283 };
284
285 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
286 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
287 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
288 EVENT_EXTRA_END
289 };
290
291 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
292 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
293 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
294 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
295 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
296 EVENT_EXTRA_END
297 };
298
299 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
300 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
301 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
302 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
303 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
304 EVENT_EXTRA_END
305 };
306
307 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
308 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
309 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
310 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
311 /*
312 * Note the low 8 bits eventsel code is not a continuous field, containing
313 * some #GPing bits. These are masked out.
314 */
315 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
316 EVENT_EXTRA_END
317 };
318
319 static struct event_constraint intel_icl_event_constraints[] = {
320 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
321 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* old INST_RETIRED.PREC_DIST */
322 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
323 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
324 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
325 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
326 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
327 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
328 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
329 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
330 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
331 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
332 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
333 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */
334 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x56, 0xf),
335 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
336 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */
337 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.CYCLES_MEM_ANY */
338 INTEL_UEVENT_CONSTRAINT(0x14a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
339 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */
340 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
341 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
342 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
343 INTEL_EVENT_CONSTRAINT(0xef, 0xf),
344 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
345 EVENT_CONSTRAINT_END
346 };
347
348 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
349 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
350 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
351 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
352 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
353 EVENT_EXTRA_END
354 };
355
356 static struct extra_reg intel_glc_extra_regs[] __read_mostly = {
357 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
358 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
359 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
360 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
361 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
362 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
363 EVENT_EXTRA_END
364 };
365
366 static struct event_constraint intel_glc_event_constraints[] = {
367 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
368 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
369 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
370 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
371 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
372 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
373 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
374 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
375 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
376 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
377 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
378 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
379 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
380 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
381 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
382
383 INTEL_EVENT_CONSTRAINT(0x2e, 0xff),
384 INTEL_EVENT_CONSTRAINT(0x3c, 0xff),
385 /*
386 * Generally event codes < 0x90 are restricted to counters 0-3.
387 * The 0x2E and 0x3C are exception, which has no restriction.
388 */
389 INTEL_EVENT_CONSTRAINT_RANGE(0x01, 0x8f, 0xf),
390
391 INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
392 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
393 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf),
394 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf),
395 INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
396 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0xf),
397 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
398 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
399 INTEL_UEVENT_CONSTRAINT(0x01cd, 0xfe),
400 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
401 INTEL_EVENT_CONSTRAINT(0xce, 0x1),
402 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
403 /*
404 * Generally event codes >= 0x90 are likely to have no restrictions.
405 * The exception are defined as above.
406 */
407 INTEL_EVENT_CONSTRAINT_RANGE(0x90, 0xfe, 0xff),
408
409 EVENT_CONSTRAINT_END
410 };
411
412 static struct extra_reg intel_rwc_extra_regs[] __read_mostly = {
413 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
414 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
415 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
416 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
417 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
418 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
419 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
420 EVENT_EXTRA_END
421 };
422
423 static struct event_constraint intel_lnc_event_constraints[] = {
424 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
425 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
426 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
427 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
428 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
429 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
430 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
431 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
432 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
433 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
434 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
435 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
436 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
437 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
438 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
439
440 INTEL_EVENT_CONSTRAINT(0x20, 0xf),
441
442 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4),
443 INTEL_UEVENT_CONSTRAINT(0x0175, 0x4),
444
445 INTEL_EVENT_CONSTRAINT(0x2e, 0x3ff),
446 INTEL_EVENT_CONSTRAINT(0x3c, 0x3ff),
447
448 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
449 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
450 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
451 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
452 INTEL_UEVENT_CONSTRAINT(0x10a4, 0x8),
453 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
454 INTEL_UEVENT_CONSTRAINT(0x01cd, 0x3fc),
455 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3),
456
457 INTEL_UEVENT_CONSTRAINT(0x87d0, 0x3ff),
458 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
459
460 EVENT_CONSTRAINT_END
461 };
462
463 static struct extra_reg intel_lnc_extra_regs[] __read_mostly = {
464 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0xfffffffffffull, RSP_0),
465 INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0xfffffffffffull, RSP_1),
466 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
467 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
468 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
469 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE),
470 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
471 EVENT_EXTRA_END
472 };
473
474 static struct event_constraint intel_pnc_event_constraints[] = {
475 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
476 FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
477 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
478 FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
479 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
480 FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
481 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* pseudo TOPDOWN.SLOTS */
482 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
483 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
484 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
485 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
486 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_HEAVY_OPS, 4),
487 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BR_MISPREDICT, 5),
488 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FETCH_LAT, 6),
489 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_MEM_BOUND, 7),
490
491 INTEL_EVENT_CONSTRAINT(0x20, 0xf),
492 INTEL_EVENT_CONSTRAINT(0x79, 0xf),
493
494 INTEL_UEVENT_CONSTRAINT(0x0275, 0xf),
495 INTEL_UEVENT_CONSTRAINT(0x0176, 0xf),
496 INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
497 INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
498 INTEL_UEVENT_CONSTRAINT(0x01cd, 0xfc),
499 INTEL_UEVENT_CONSTRAINT(0x02cd, 0x3),
500
501 INTEL_EVENT_CONSTRAINT(0xd0, 0xf),
502 INTEL_EVENT_CONSTRAINT(0xd1, 0xf),
503 INTEL_EVENT_CONSTRAINT(0xd4, 0xf),
504 INTEL_EVENT_CONSTRAINT(0xd6, 0xf),
505 INTEL_EVENT_CONSTRAINT(0xdf, 0xf),
506 INTEL_EVENT_CONSTRAINT(0xce, 0x1),
507
508 INTEL_UEVENT_CONSTRAINT(0x01b1, 0x8),
509 INTEL_UEVENT_CONSTRAINT(0x0847, 0xf),
510 INTEL_UEVENT_CONSTRAINT(0x0446, 0xf),
511 INTEL_UEVENT_CONSTRAINT(0x0846, 0xf),
512 INTEL_UEVENT_CONSTRAINT(0x0148, 0xf),
513
514 EVENT_CONSTRAINT_END
515 };
516
517 static struct extra_reg intel_pnc_extra_regs[] __read_mostly = {
518 /* must define OMR_X first, see intel_alt_er() */
519 INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OMR_0, 0x40ffffff0000ffffull, OMR_0),
520 INTEL_UEVENT_EXTRA_REG(0x022a, MSR_OMR_1, 0x40ffffff0000ffffull, OMR_1),
521 INTEL_UEVENT_EXTRA_REG(0x042a, MSR_OMR_2, 0x40ffffff0000ffffull, OMR_2),
522 INTEL_UEVENT_EXTRA_REG(0x082a, MSR_OMR_3, 0x40ffffff0000ffffull, OMR_3),
523 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
524 INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
525 INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
526 INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0xf, FE),
527 INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
528 EVENT_EXTRA_END
529 };
530
531 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
532 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
533 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
534
535 static struct attribute *nhm_mem_events_attrs[] = {
536 EVENT_PTR(mem_ld_nhm),
537 NULL,
538 };
539
540 /*
541 * topdown events for Intel Core CPUs.
542 *
543 * The events are all in slots, which is a free slot in a 4 wide
544 * pipeline. Some events are already reported in slots, for cycle
545 * events we multiply by the pipeline width (4).
546 *
547 * With Hyper Threading on, topdown metrics are either summed or averaged
548 * between the threads of a core: (count_t0 + count_t1).
549 *
550 * For the average case the metric is always scaled to pipeline width,
551 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
552 */
553
554 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
555 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
556 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
557 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
558 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
559 "event=0xe,umask=0x1"); /* uops_issued.any */
560 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
561 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
562 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
563 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
564 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
565 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
566 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
567 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
568 "4", "2");
569
570 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4");
571 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80");
572 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81");
573 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82");
574 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83");
575 EVENT_ATTR_STR(topdown-heavy-ops, td_heavy_ops, "event=0x00,umask=0x84");
576 EVENT_ATTR_STR(topdown-br-mispredict, td_br_mispredict, "event=0x00,umask=0x85");
577 EVENT_ATTR_STR(topdown-fetch-lat, td_fetch_lat, "event=0x00,umask=0x86");
578 EVENT_ATTR_STR(topdown-mem-bound, td_mem_bound, "event=0x00,umask=0x87");
579
580 static struct attribute *snb_events_attrs[] = {
581 EVENT_PTR(td_slots_issued),
582 EVENT_PTR(td_slots_retired),
583 EVENT_PTR(td_fetch_bubbles),
584 EVENT_PTR(td_total_slots),
585 EVENT_PTR(td_total_slots_scale),
586 EVENT_PTR(td_recovery_bubbles),
587 EVENT_PTR(td_recovery_bubbles_scale),
588 NULL,
589 };
590
591 static struct attribute *snb_mem_events_attrs[] = {
592 EVENT_PTR(mem_ld_snb),
593 EVENT_PTR(mem_st_snb),
594 NULL,
595 };
596
597 static struct event_constraint intel_hsw_event_constraints[] = {
598 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
599 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
600 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
601 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
602 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
603 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
604 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
605 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
606 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
607 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
608 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
609 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
610
611 /*
612 * When HT is off these events can only run on the bottom 4 counters
613 * When HT is on, they are impacted by the HT bug and require EXCL access
614 */
615 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
616 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
617 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
618 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
619
620 EVENT_CONSTRAINT_END
621 };
622
623 static struct event_constraint intel_bdw_event_constraints[] = {
624 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
625 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
626 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
627 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
628 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
629 /*
630 * when HT is off, these can only run on the bottom 4 counters
631 */
632 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
633 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
634 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
635 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
636 EVENT_CONSTRAINT_END
637 };
638
intel_pmu_event_map(int hw_event)639 static u64 intel_pmu_event_map(int hw_event)
640 {
641 return intel_perfmon_event_map[hw_event];
642 }
643
644 static __initconst const u64 glc_hw_cache_event_ids
645 [PERF_COUNT_HW_CACHE_MAX]
646 [PERF_COUNT_HW_CACHE_OP_MAX]
647 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
648 {
649 [ C(L1D ) ] = {
650 [ C(OP_READ) ] = {
651 [ C(RESULT_ACCESS) ] = 0x81d0,
652 [ C(RESULT_MISS) ] = 0xe124,
653 },
654 [ C(OP_WRITE) ] = {
655 [ C(RESULT_ACCESS) ] = 0x82d0,
656 },
657 },
658 [ C(L1I ) ] = {
659 [ C(OP_READ) ] = {
660 [ C(RESULT_MISS) ] = 0xe424,
661 },
662 [ C(OP_WRITE) ] = {
663 [ C(RESULT_ACCESS) ] = -1,
664 [ C(RESULT_MISS) ] = -1,
665 },
666 },
667 [ C(LL ) ] = {
668 [ C(OP_READ) ] = {
669 [ C(RESULT_ACCESS) ] = 0x12a,
670 [ C(RESULT_MISS) ] = 0x12a,
671 },
672 [ C(OP_WRITE) ] = {
673 [ C(RESULT_ACCESS) ] = 0x12a,
674 [ C(RESULT_MISS) ] = 0x12a,
675 },
676 },
677 [ C(DTLB) ] = {
678 [ C(OP_READ) ] = {
679 [ C(RESULT_ACCESS) ] = 0x81d0,
680 [ C(RESULT_MISS) ] = 0xe12,
681 },
682 [ C(OP_WRITE) ] = {
683 [ C(RESULT_ACCESS) ] = 0x82d0,
684 [ C(RESULT_MISS) ] = 0xe13,
685 },
686 },
687 [ C(ITLB) ] = {
688 [ C(OP_READ) ] = {
689 [ C(RESULT_ACCESS) ] = -1,
690 [ C(RESULT_MISS) ] = 0xe11,
691 },
692 [ C(OP_WRITE) ] = {
693 [ C(RESULT_ACCESS) ] = -1,
694 [ C(RESULT_MISS) ] = -1,
695 },
696 [ C(OP_PREFETCH) ] = {
697 [ C(RESULT_ACCESS) ] = -1,
698 [ C(RESULT_MISS) ] = -1,
699 },
700 },
701 [ C(BPU ) ] = {
702 [ C(OP_READ) ] = {
703 [ C(RESULT_ACCESS) ] = 0x4c4,
704 [ C(RESULT_MISS) ] = 0x4c5,
705 },
706 [ C(OP_WRITE) ] = {
707 [ C(RESULT_ACCESS) ] = -1,
708 [ C(RESULT_MISS) ] = -1,
709 },
710 [ C(OP_PREFETCH) ] = {
711 [ C(RESULT_ACCESS) ] = -1,
712 [ C(RESULT_MISS) ] = -1,
713 },
714 },
715 [ C(NODE) ] = {
716 [ C(OP_READ) ] = {
717 [ C(RESULT_ACCESS) ] = 0x12a,
718 [ C(RESULT_MISS) ] = 0x12a,
719 },
720 },
721 };
722
723 /* ADL P-core (Golden cove) specific event code. */
724 static __initconst const u64 adl_glc_hw_cache_event_ids
725 [PERF_COUNT_HW_CACHE_MAX]
726 [PERF_COUNT_HW_CACHE_OP_MAX]
727 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
728 {
729 [ C(L1D ) ] = {
730 [ C(OP_READ) ] = {
731 [ C(RESULT_ACCESS) ] = 0x81d0,
732 [ C(RESULT_MISS) ] = 0xe124,
733 },
734 [ C(OP_WRITE) ] = {
735 [ C(RESULT_ACCESS) ] = 0x82d0,
736 },
737 },
738 [ C(L1I ) ] = {
739 [ C(OP_READ) ] = {
740 [ C(RESULT_MISS) ] = 0xe424,
741 },
742 [ C(OP_WRITE) ] = {
743 [ C(RESULT_ACCESS) ] = -1,
744 [ C(RESULT_MISS) ] = -1,
745 },
746 },
747 [ C(LL ) ] = {
748 [ C(OP_READ) ] = {
749 [ C(RESULT_ACCESS) ] = 0x12a,
750 [ C(RESULT_MISS) ] = 0x12a,
751 },
752 [ C(OP_WRITE) ] = {
753 [ C(RESULT_ACCESS) ] = 0x12a,
754 [ C(RESULT_MISS) ] = 0x12a,
755 },
756 },
757 [ C(DTLB) ] = {
758 [ C(OP_READ) ] = {
759 [ C(RESULT_ACCESS) ] = 0x81d0,
760 [ C(RESULT_MISS) ] = 0xe12,
761 },
762 [ C(OP_WRITE) ] = {
763 [ C(RESULT_ACCESS) ] = 0x82d0,
764 [ C(RESULT_MISS) ] = 0xe13,
765 },
766 },
767 [ C(ITLB) ] = {
768 [ C(OP_READ) ] = {
769 [ C(RESULT_ACCESS) ] = -1,
770 [ C(RESULT_MISS) ] = 0xe11,
771 },
772 [ C(OP_WRITE) ] = {
773 [ C(RESULT_ACCESS) ] = -1,
774 [ C(RESULT_MISS) ] = -1,
775 },
776 [ C(OP_PREFETCH) ] = {
777 [ C(RESULT_ACCESS) ] = -1,
778 [ C(RESULT_MISS) ] = -1,
779 },
780 },
781 [ C(BPU ) ] = {
782 [ C(OP_READ) ] = {
783 [ C(RESULT_ACCESS) ] = 0x4c4,
784 [ C(RESULT_MISS) ] = 0x4c5,
785 },
786 [ C(OP_WRITE) ] = {
787 [ C(RESULT_ACCESS) ] = -1,
788 [ C(RESULT_MISS) ] = -1,
789 },
790 [ C(OP_PREFETCH) ] = {
791 [ C(RESULT_ACCESS) ] = -1,
792 [ C(RESULT_MISS) ] = -1,
793 },
794 },
795 };
796
797 static __initconst const u64 glc_hw_cache_extra_regs
798 [PERF_COUNT_HW_CACHE_MAX]
799 [PERF_COUNT_HW_CACHE_OP_MAX]
800 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
801 {
802 [ C(LL ) ] = {
803 [ C(OP_READ) ] = {
804 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
805 [ C(RESULT_MISS) ] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
806 },
807 [ C(OP_WRITE) ] = {
808 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
809 [ C(RESULT_MISS) ] = 0x3f3fc00002, /* OCR.DEMAND_RFO.L3_MISS */
810 },
811 },
812 [ C(NODE) ] = {
813 [ C(OP_READ) ] = {
814 [ C(RESULT_ACCESS) ] = 0x104000001, /* OCR.DEMAND_DATA_RD.LOCAL_DRAM */
815 [ C(RESULT_MISS) ] = 0x730000001, /* OCR.DEMAND_DATA_RD.REMOTE_DRAM */
816 },
817 },
818 };
819
820 /* ADL P-core (Golden cove) specific extra regs value. */
821 static __initconst const u64 adl_glc_hw_cache_extra_regs
822 [PERF_COUNT_HW_CACHE_MAX]
823 [PERF_COUNT_HW_CACHE_OP_MAX]
824 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
825 {
826 [ C(LL ) ] = {
827 [ C(OP_READ) ] = {
828 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
829 [ C(RESULT_MISS) ] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
830 },
831 [ C(OP_WRITE) ] = {
832 [ C(RESULT_ACCESS) ] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
833 [ C(RESULT_MISS) ] = 0x3fbfc00002, /* OCR.DEMAND_RFO.L3_MISS */
834 },
835 },
836 };
837
838 static __initconst const u64 lnc_hw_cache_extra_regs
839 [PERF_COUNT_HW_CACHE_MAX]
840 [PERF_COUNT_HW_CACHE_OP_MAX]
841 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
842 {
843 [ C(LL ) ] = {
844 [ C(OP_READ) ] = {
845 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
846 [ C(RESULT_MISS) ] = 0x9E7FA000001, /* OCR.DEMAND_DATA_RD.L3_MISS */
847 },
848 [ C(OP_WRITE) ] = {
849 [ C(RESULT_ACCESS) ] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
850 [ C(RESULT_MISS) ] = 0x9E7FA000002, /* OCR.DEMAND_RFO.L3_MISS */
851 },
852 },
853 };
854
855 /* ARL specific lioncove hw_cache_extra_regs[] variant. */
856 static __initconst const u64 arl_lnc_hw_cache_extra_regs
857 [PERF_COUNT_HW_CACHE_MAX]
858 [PERF_COUNT_HW_CACHE_OP_MAX]
859 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
860 {
861 [ C(LL ) ] = {
862 [ C(OP_READ) ] = {
863 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
864 [ C(RESULT_MISS) ] = 0xFE7F8000001, /* OCR.DEMAND_DATA_RD.L3_MISS */
865 },
866 [ C(OP_WRITE) ] = {
867 [ C(RESULT_ACCESS) ] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
868 [ C(RESULT_MISS) ] = 0xFE7F8000002, /* OCR.DEMAND_RFO.L3_MISS */
869 },
870 },
871 };
872
873 static __initconst const u64 pnc_hw_cache_event_ids
874 [PERF_COUNT_HW_CACHE_MAX]
875 [PERF_COUNT_HW_CACHE_OP_MAX]
876 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
877 {
878 [ C(L1D ) ] = {
879 [ C(OP_READ) ] = {
880 [ C(RESULT_ACCESS) ] = 0x81d0,
881 [ C(RESULT_MISS) ] = 0xe124,
882 },
883 [ C(OP_WRITE) ] = {
884 [ C(RESULT_ACCESS) ] = 0x82d0,
885 },
886 },
887 [ C(L1I ) ] = {
888 [ C(OP_READ) ] = {
889 [ C(RESULT_MISS) ] = 0xe424,
890 },
891 [ C(OP_WRITE) ] = {
892 [ C(RESULT_ACCESS) ] = -1,
893 [ C(RESULT_MISS) ] = -1,
894 },
895 },
896 [ C(LL ) ] = {
897 [ C(OP_READ) ] = {
898 [ C(RESULT_ACCESS) ] = 0x12a,
899 [ C(RESULT_MISS) ] = 0x12a,
900 },
901 [ C(OP_WRITE) ] = {
902 [ C(RESULT_ACCESS) ] = 0x12a,
903 [ C(RESULT_MISS) ] = 0x12a,
904 },
905 },
906 [ C(DTLB) ] = {
907 [ C(OP_READ) ] = {
908 [ C(RESULT_ACCESS) ] = 0x81d0,
909 [ C(RESULT_MISS) ] = 0xe12,
910 },
911 [ C(OP_WRITE) ] = {
912 [ C(RESULT_ACCESS) ] = 0x82d0,
913 [ C(RESULT_MISS) ] = 0xe13,
914 },
915 },
916 [ C(ITLB) ] = {
917 [ C(OP_READ) ] = {
918 [ C(RESULT_ACCESS) ] = -1,
919 [ C(RESULT_MISS) ] = 0xe11,
920 },
921 [ C(OP_WRITE) ] = {
922 [ C(RESULT_ACCESS) ] = -1,
923 [ C(RESULT_MISS) ] = -1,
924 },
925 [ C(OP_PREFETCH) ] = {
926 [ C(RESULT_ACCESS) ] = -1,
927 [ C(RESULT_MISS) ] = -1,
928 },
929 },
930 [ C(BPU ) ] = {
931 [ C(OP_READ) ] = {
932 [ C(RESULT_ACCESS) ] = 0x4c4,
933 [ C(RESULT_MISS) ] = 0x4c5,
934 },
935 [ C(OP_WRITE) ] = {
936 [ C(RESULT_ACCESS) ] = -1,
937 [ C(RESULT_MISS) ] = -1,
938 },
939 [ C(OP_PREFETCH) ] = {
940 [ C(RESULT_ACCESS) ] = -1,
941 [ C(RESULT_MISS) ] = -1,
942 },
943 },
944 [ C(NODE) ] = {
945 [ C(OP_READ) ] = {
946 [ C(RESULT_ACCESS) ] = -1,
947 [ C(RESULT_MISS) ] = -1,
948 },
949 },
950 };
951
952 static __initconst const u64 pnc_hw_cache_extra_regs
953 [PERF_COUNT_HW_CACHE_MAX]
954 [PERF_COUNT_HW_CACHE_OP_MAX]
955 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
956 {
957 [ C(LL ) ] = {
958 [ C(OP_READ) ] = {
959 [ C(RESULT_ACCESS) ] = 0x4000000000000001, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */
960 [ C(RESULT_MISS) ] = 0xFFFFF000000001, /* OMR.DEMAND_DATA_RD.L3_MISS */
961 },
962 [ C(OP_WRITE) ] = {
963 [ C(RESULT_ACCESS) ] = 0x4000000000000002, /* OMR.DEMAND_RFO.ANY_RESPONSE */
964 [ C(RESULT_MISS) ] = 0xFFFFF000000002, /* OMR.DEMAND_RFO.L3_MISS */
965 },
966 },
967 };
968
969 static __initconst const u64 cyc_hw_cache_extra_regs
970 [PERF_COUNT_HW_CACHE_MAX]
971 [PERF_COUNT_HW_CACHE_OP_MAX]
972 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
973 {
974 [ C(LL ) ] = {
975 [ C(OP_READ) ] = {
976 [ C(RESULT_ACCESS) ] = 0x4000000000000001, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */
977 [ C(RESULT_MISS) ] = 0xFF03F000000001, /* OMR.DEMAND_DATA_RD.L3_MISS */
978 },
979 [ C(OP_WRITE) ] = {
980 [ C(RESULT_ACCESS) ] = 0x4000000000000002, /* OMR.DEMAND_RFO.ANY_RESPONSE */
981 [ C(RESULT_MISS) ] = 0xFF03F000000002, /* OMR.DEMAND_RFO.L3_MISS */
982 },
983 },
984 };
985
986 /*
987 * Notes on the events:
988 * - data reads do not include code reads (comparable to earlier tables)
989 * - data counts include speculative execution (except L1 write, dtlb, bpu)
990 * - remote node access includes remote memory, remote cache, remote mmio.
991 * - prefetches are not included in the counts.
992 * - icache miss does not include decoded icache
993 */
994
995 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
996 #define SKL_DEMAND_RFO BIT_ULL(1)
997 #define SKL_ANY_RESPONSE BIT_ULL(16)
998 #define SKL_SUPPLIER_NONE BIT_ULL(17)
999 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
1000 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
1001 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
1002 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
1003 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
1004 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
1005 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
1006 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
1007 #define SKL_SPL_HIT BIT_ULL(30)
1008 #define SKL_SNOOP_NONE BIT_ULL(31)
1009 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
1010 #define SKL_SNOOP_MISS BIT_ULL(33)
1011 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
1012 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
1013 #define SKL_SNOOP_HITM BIT_ULL(36)
1014 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
1015 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
1016 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
1017 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
1018 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
1019 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
1020 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
1021 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
1022 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
1023 SKL_SNOOP_HITM|SKL_SPL_HIT)
1024 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
1025 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
1026 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
1027 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
1028 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
1029
1030 static __initconst const u64 skl_hw_cache_event_ids
1031 [PERF_COUNT_HW_CACHE_MAX]
1032 [PERF_COUNT_HW_CACHE_OP_MAX]
1033 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1034 {
1035 [ C(L1D ) ] = {
1036 [ C(OP_READ) ] = {
1037 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
1038 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
1039 },
1040 [ C(OP_WRITE) ] = {
1041 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
1042 [ C(RESULT_MISS) ] = 0x0,
1043 },
1044 [ C(OP_PREFETCH) ] = {
1045 [ C(RESULT_ACCESS) ] = 0x0,
1046 [ C(RESULT_MISS) ] = 0x0,
1047 },
1048 },
1049 [ C(L1I ) ] = {
1050 [ C(OP_READ) ] = {
1051 [ C(RESULT_ACCESS) ] = 0x0,
1052 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
1053 },
1054 [ C(OP_WRITE) ] = {
1055 [ C(RESULT_ACCESS) ] = -1,
1056 [ C(RESULT_MISS) ] = -1,
1057 },
1058 [ C(OP_PREFETCH) ] = {
1059 [ C(RESULT_ACCESS) ] = 0x0,
1060 [ C(RESULT_MISS) ] = 0x0,
1061 },
1062 },
1063 [ C(LL ) ] = {
1064 [ C(OP_READ) ] = {
1065 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1066 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1067 },
1068 [ C(OP_WRITE) ] = {
1069 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1070 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1071 },
1072 [ C(OP_PREFETCH) ] = {
1073 [ C(RESULT_ACCESS) ] = 0x0,
1074 [ C(RESULT_MISS) ] = 0x0,
1075 },
1076 },
1077 [ C(DTLB) ] = {
1078 [ C(OP_READ) ] = {
1079 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
1080 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1081 },
1082 [ C(OP_WRITE) ] = {
1083 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
1084 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
1085 },
1086 [ C(OP_PREFETCH) ] = {
1087 [ C(RESULT_ACCESS) ] = 0x0,
1088 [ C(RESULT_MISS) ] = 0x0,
1089 },
1090 },
1091 [ C(ITLB) ] = {
1092 [ C(OP_READ) ] = {
1093 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
1094 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
1095 },
1096 [ C(OP_WRITE) ] = {
1097 [ C(RESULT_ACCESS) ] = -1,
1098 [ C(RESULT_MISS) ] = -1,
1099 },
1100 [ C(OP_PREFETCH) ] = {
1101 [ C(RESULT_ACCESS) ] = -1,
1102 [ C(RESULT_MISS) ] = -1,
1103 },
1104 },
1105 [ C(BPU ) ] = {
1106 [ C(OP_READ) ] = {
1107 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
1108 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1109 },
1110 [ C(OP_WRITE) ] = {
1111 [ C(RESULT_ACCESS) ] = -1,
1112 [ C(RESULT_MISS) ] = -1,
1113 },
1114 [ C(OP_PREFETCH) ] = {
1115 [ C(RESULT_ACCESS) ] = -1,
1116 [ C(RESULT_MISS) ] = -1,
1117 },
1118 },
1119 [ C(NODE) ] = {
1120 [ C(OP_READ) ] = {
1121 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1122 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1123 },
1124 [ C(OP_WRITE) ] = {
1125 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1126 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1127 },
1128 [ C(OP_PREFETCH) ] = {
1129 [ C(RESULT_ACCESS) ] = 0x0,
1130 [ C(RESULT_MISS) ] = 0x0,
1131 },
1132 },
1133 };
1134
1135 static __initconst const u64 skl_hw_cache_extra_regs
1136 [PERF_COUNT_HW_CACHE_MAX]
1137 [PERF_COUNT_HW_CACHE_OP_MAX]
1138 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1139 {
1140 [ C(LL ) ] = {
1141 [ C(OP_READ) ] = {
1142 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
1143 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
1144 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
1145 SKL_L3_MISS|SKL_ANY_SNOOP|
1146 SKL_SUPPLIER_NONE,
1147 },
1148 [ C(OP_WRITE) ] = {
1149 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
1150 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
1151 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
1152 SKL_L3_MISS|SKL_ANY_SNOOP|
1153 SKL_SUPPLIER_NONE,
1154 },
1155 [ C(OP_PREFETCH) ] = {
1156 [ C(RESULT_ACCESS) ] = 0x0,
1157 [ C(RESULT_MISS) ] = 0x0,
1158 },
1159 },
1160 [ C(NODE) ] = {
1161 [ C(OP_READ) ] = {
1162 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
1163 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
1164 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
1165 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
1166 },
1167 [ C(OP_WRITE) ] = {
1168 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
1169 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
1170 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
1171 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
1172 },
1173 [ C(OP_PREFETCH) ] = {
1174 [ C(RESULT_ACCESS) ] = 0x0,
1175 [ C(RESULT_MISS) ] = 0x0,
1176 },
1177 },
1178 };
1179
1180 static __initconst const u64 snc_hw_cache_extra_regs
1181 [PERF_COUNT_HW_CACHE_MAX]
1182 [PERF_COUNT_HW_CACHE_OP_MAX]
1183 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1184 {
1185 [ C(LL ) ] = {
1186 [ C(OP_READ) ] = {
1187 [ C(RESULT_ACCESS) ] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
1188 [ C(RESULT_MISS) ] = 0x3FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
1189 },
1190 [ C(OP_WRITE) ] = {
1191 [ C(RESULT_ACCESS) ] = 0x3F3FFC0002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
1192 [ C(RESULT_MISS) ] = 0x3F3FC00002, /* OCR.DEMAND_RFO.L3_MISS */
1193 },
1194 [ C(OP_PREFETCH) ] = {
1195 [ C(RESULT_ACCESS) ] = 0x0,
1196 [ C(RESULT_MISS) ] = 0x0,
1197 },
1198 },
1199 [ C(NODE) ] = {
1200 [ C(OP_READ) ] = {
1201 [ C(RESULT_ACCESS) ] = 0x104000001, /* OCR.DEMAND_DATA_RD.LOCAL_DRAM */
1202 [ C(RESULT_MISS) ] = 0x730000001, /* OCR.DEMAND_DATA_RD.REMOTE_DRAM */
1203 },
1204 [ C(OP_WRITE) ] = {
1205 [ C(RESULT_ACCESS) ] = 0x104000002, /* OCR.DEMAND_RFO.LOCAL_DRAM */
1206 [ C(RESULT_MISS) ] = 0x730000002, /* OCR.DEMAND_RFO.REMOTE_DRAM */
1207 },
1208 [ C(OP_PREFETCH) ] = {
1209 [ C(RESULT_ACCESS) ] = 0x0,
1210 [ C(RESULT_MISS) ] = 0x0,
1211 },
1212 },
1213 };
1214
1215 #define SNB_DMND_DATA_RD (1ULL << 0)
1216 #define SNB_DMND_RFO (1ULL << 1)
1217 #define SNB_DMND_IFETCH (1ULL << 2)
1218 #define SNB_DMND_WB (1ULL << 3)
1219 #define SNB_PF_DATA_RD (1ULL << 4)
1220 #define SNB_PF_RFO (1ULL << 5)
1221 #define SNB_PF_IFETCH (1ULL << 6)
1222 #define SNB_LLC_DATA_RD (1ULL << 7)
1223 #define SNB_LLC_RFO (1ULL << 8)
1224 #define SNB_LLC_IFETCH (1ULL << 9)
1225 #define SNB_BUS_LOCKS (1ULL << 10)
1226 #define SNB_STRM_ST (1ULL << 11)
1227 #define SNB_OTHER (1ULL << 15)
1228 #define SNB_RESP_ANY (1ULL << 16)
1229 #define SNB_NO_SUPP (1ULL << 17)
1230 #define SNB_LLC_HITM (1ULL << 18)
1231 #define SNB_LLC_HITE (1ULL << 19)
1232 #define SNB_LLC_HITS (1ULL << 20)
1233 #define SNB_LLC_HITF (1ULL << 21)
1234 #define SNB_LOCAL (1ULL << 22)
1235 #define SNB_REMOTE (0xffULL << 23)
1236 #define SNB_SNP_NONE (1ULL << 31)
1237 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
1238 #define SNB_SNP_MISS (1ULL << 33)
1239 #define SNB_NO_FWD (1ULL << 34)
1240 #define SNB_SNP_FWD (1ULL << 35)
1241 #define SNB_HITM (1ULL << 36)
1242 #define SNB_NON_DRAM (1ULL << 37)
1243
1244 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
1245 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
1246 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1247
1248 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
1249 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
1250 SNB_HITM)
1251
1252 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
1253 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
1254
1255 #define SNB_L3_ACCESS SNB_RESP_ANY
1256 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
1257
1258 static __initconst const u64 snb_hw_cache_extra_regs
1259 [PERF_COUNT_HW_CACHE_MAX]
1260 [PERF_COUNT_HW_CACHE_OP_MAX]
1261 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1262 {
1263 [ C(LL ) ] = {
1264 [ C(OP_READ) ] = {
1265 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
1266 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
1267 },
1268 [ C(OP_WRITE) ] = {
1269 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
1270 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
1271 },
1272 [ C(OP_PREFETCH) ] = {
1273 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
1274 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
1275 },
1276 },
1277 [ C(NODE) ] = {
1278 [ C(OP_READ) ] = {
1279 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
1280 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
1281 },
1282 [ C(OP_WRITE) ] = {
1283 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
1284 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
1285 },
1286 [ C(OP_PREFETCH) ] = {
1287 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
1288 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
1289 },
1290 },
1291 };
1292
1293 static __initconst const u64 snb_hw_cache_event_ids
1294 [PERF_COUNT_HW_CACHE_MAX]
1295 [PERF_COUNT_HW_CACHE_OP_MAX]
1296 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1297 {
1298 [ C(L1D) ] = {
1299 [ C(OP_READ) ] = {
1300 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
1301 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
1302 },
1303 [ C(OP_WRITE) ] = {
1304 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
1305 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
1306 },
1307 [ C(OP_PREFETCH) ] = {
1308 [ C(RESULT_ACCESS) ] = 0x0,
1309 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
1310 },
1311 },
1312 [ C(L1I ) ] = {
1313 [ C(OP_READ) ] = {
1314 [ C(RESULT_ACCESS) ] = 0x0,
1315 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
1316 },
1317 [ C(OP_WRITE) ] = {
1318 [ C(RESULT_ACCESS) ] = -1,
1319 [ C(RESULT_MISS) ] = -1,
1320 },
1321 [ C(OP_PREFETCH) ] = {
1322 [ C(RESULT_ACCESS) ] = 0x0,
1323 [ C(RESULT_MISS) ] = 0x0,
1324 },
1325 },
1326 [ C(LL ) ] = {
1327 [ C(OP_READ) ] = {
1328 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1329 [ C(RESULT_ACCESS) ] = 0x01b7,
1330 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1331 [ C(RESULT_MISS) ] = 0x01b7,
1332 },
1333 [ C(OP_WRITE) ] = {
1334 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1335 [ C(RESULT_ACCESS) ] = 0x01b7,
1336 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1337 [ C(RESULT_MISS) ] = 0x01b7,
1338 },
1339 [ C(OP_PREFETCH) ] = {
1340 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1341 [ C(RESULT_ACCESS) ] = 0x01b7,
1342 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1343 [ C(RESULT_MISS) ] = 0x01b7,
1344 },
1345 },
1346 [ C(DTLB) ] = {
1347 [ C(OP_READ) ] = {
1348 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
1349 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
1350 },
1351 [ C(OP_WRITE) ] = {
1352 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
1353 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1354 },
1355 [ C(OP_PREFETCH) ] = {
1356 [ C(RESULT_ACCESS) ] = 0x0,
1357 [ C(RESULT_MISS) ] = 0x0,
1358 },
1359 },
1360 [ C(ITLB) ] = {
1361 [ C(OP_READ) ] = {
1362 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
1363 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
1364 },
1365 [ C(OP_WRITE) ] = {
1366 [ C(RESULT_ACCESS) ] = -1,
1367 [ C(RESULT_MISS) ] = -1,
1368 },
1369 [ C(OP_PREFETCH) ] = {
1370 [ C(RESULT_ACCESS) ] = -1,
1371 [ C(RESULT_MISS) ] = -1,
1372 },
1373 },
1374 [ C(BPU ) ] = {
1375 [ C(OP_READ) ] = {
1376 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1377 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1378 },
1379 [ C(OP_WRITE) ] = {
1380 [ C(RESULT_ACCESS) ] = -1,
1381 [ C(RESULT_MISS) ] = -1,
1382 },
1383 [ C(OP_PREFETCH) ] = {
1384 [ C(RESULT_ACCESS) ] = -1,
1385 [ C(RESULT_MISS) ] = -1,
1386 },
1387 },
1388 [ C(NODE) ] = {
1389 [ C(OP_READ) ] = {
1390 [ C(RESULT_ACCESS) ] = 0x01b7,
1391 [ C(RESULT_MISS) ] = 0x01b7,
1392 },
1393 [ C(OP_WRITE) ] = {
1394 [ C(RESULT_ACCESS) ] = 0x01b7,
1395 [ C(RESULT_MISS) ] = 0x01b7,
1396 },
1397 [ C(OP_PREFETCH) ] = {
1398 [ C(RESULT_ACCESS) ] = 0x01b7,
1399 [ C(RESULT_MISS) ] = 0x01b7,
1400 },
1401 },
1402
1403 };
1404
1405 /*
1406 * Notes on the events:
1407 * - data reads do not include code reads (comparable to earlier tables)
1408 * - data counts include speculative execution (except L1 write, dtlb, bpu)
1409 * - remote node access includes remote memory, remote cache, remote mmio.
1410 * - prefetches are not included in the counts because they are not
1411 * reliably counted.
1412 */
1413
1414 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
1415 #define HSW_DEMAND_RFO BIT_ULL(1)
1416 #define HSW_ANY_RESPONSE BIT_ULL(16)
1417 #define HSW_SUPPLIER_NONE BIT_ULL(17)
1418 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
1419 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
1420 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
1421 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
1422 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
1423 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
1424 HSW_L3_MISS_REMOTE_HOP2P)
1425 #define HSW_SNOOP_NONE BIT_ULL(31)
1426 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
1427 #define HSW_SNOOP_MISS BIT_ULL(33)
1428 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
1429 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
1430 #define HSW_SNOOP_HITM BIT_ULL(36)
1431 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
1432 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
1433 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
1434 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
1435 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
1436 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
1437 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
1438 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
1439 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
1440 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
1441 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
1442
1443 #define BDW_L3_MISS_LOCAL BIT(26)
1444 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
1445 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
1446 HSW_L3_MISS_REMOTE_HOP2P)
1447
1448
1449 static __initconst const u64 hsw_hw_cache_event_ids
1450 [PERF_COUNT_HW_CACHE_MAX]
1451 [PERF_COUNT_HW_CACHE_OP_MAX]
1452 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1453 {
1454 [ C(L1D ) ] = {
1455 [ C(OP_READ) ] = {
1456 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1457 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
1458 },
1459 [ C(OP_WRITE) ] = {
1460 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1461 [ C(RESULT_MISS) ] = 0x0,
1462 },
1463 [ C(OP_PREFETCH) ] = {
1464 [ C(RESULT_ACCESS) ] = 0x0,
1465 [ C(RESULT_MISS) ] = 0x0,
1466 },
1467 },
1468 [ C(L1I ) ] = {
1469 [ C(OP_READ) ] = {
1470 [ C(RESULT_ACCESS) ] = 0x0,
1471 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
1472 },
1473 [ C(OP_WRITE) ] = {
1474 [ C(RESULT_ACCESS) ] = -1,
1475 [ C(RESULT_MISS) ] = -1,
1476 },
1477 [ C(OP_PREFETCH) ] = {
1478 [ C(RESULT_ACCESS) ] = 0x0,
1479 [ C(RESULT_MISS) ] = 0x0,
1480 },
1481 },
1482 [ C(LL ) ] = {
1483 [ C(OP_READ) ] = {
1484 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1485 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1486 },
1487 [ C(OP_WRITE) ] = {
1488 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1489 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1490 },
1491 [ C(OP_PREFETCH) ] = {
1492 [ C(RESULT_ACCESS) ] = 0x0,
1493 [ C(RESULT_MISS) ] = 0x0,
1494 },
1495 },
1496 [ C(DTLB) ] = {
1497 [ C(OP_READ) ] = {
1498 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1499 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
1500 },
1501 [ C(OP_WRITE) ] = {
1502 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1503 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1504 },
1505 [ C(OP_PREFETCH) ] = {
1506 [ C(RESULT_ACCESS) ] = 0x0,
1507 [ C(RESULT_MISS) ] = 0x0,
1508 },
1509 },
1510 [ C(ITLB) ] = {
1511 [ C(OP_READ) ] = {
1512 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
1513 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
1514 },
1515 [ C(OP_WRITE) ] = {
1516 [ C(RESULT_ACCESS) ] = -1,
1517 [ C(RESULT_MISS) ] = -1,
1518 },
1519 [ C(OP_PREFETCH) ] = {
1520 [ C(RESULT_ACCESS) ] = -1,
1521 [ C(RESULT_MISS) ] = -1,
1522 },
1523 },
1524 [ C(BPU ) ] = {
1525 [ C(OP_READ) ] = {
1526 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
1527 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1528 },
1529 [ C(OP_WRITE) ] = {
1530 [ C(RESULT_ACCESS) ] = -1,
1531 [ C(RESULT_MISS) ] = -1,
1532 },
1533 [ C(OP_PREFETCH) ] = {
1534 [ C(RESULT_ACCESS) ] = -1,
1535 [ C(RESULT_MISS) ] = -1,
1536 },
1537 },
1538 [ C(NODE) ] = {
1539 [ C(OP_READ) ] = {
1540 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1541 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1542 },
1543 [ C(OP_WRITE) ] = {
1544 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1545 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1546 },
1547 [ C(OP_PREFETCH) ] = {
1548 [ C(RESULT_ACCESS) ] = 0x0,
1549 [ C(RESULT_MISS) ] = 0x0,
1550 },
1551 },
1552 };
1553
1554 static __initconst const u64 hsw_hw_cache_extra_regs
1555 [PERF_COUNT_HW_CACHE_MAX]
1556 [PERF_COUNT_HW_CACHE_OP_MAX]
1557 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1558 {
1559 [ C(LL ) ] = {
1560 [ C(OP_READ) ] = {
1561 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1562 HSW_LLC_ACCESS,
1563 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1564 HSW_L3_MISS|HSW_ANY_SNOOP,
1565 },
1566 [ C(OP_WRITE) ] = {
1567 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1568 HSW_LLC_ACCESS,
1569 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1570 HSW_L3_MISS|HSW_ANY_SNOOP,
1571 },
1572 [ C(OP_PREFETCH) ] = {
1573 [ C(RESULT_ACCESS) ] = 0x0,
1574 [ C(RESULT_MISS) ] = 0x0,
1575 },
1576 },
1577 [ C(NODE) ] = {
1578 [ C(OP_READ) ] = {
1579 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1580 HSW_L3_MISS_LOCAL_DRAM|
1581 HSW_SNOOP_DRAM,
1582 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1583 HSW_L3_MISS_REMOTE|
1584 HSW_SNOOP_DRAM,
1585 },
1586 [ C(OP_WRITE) ] = {
1587 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1588 HSW_L3_MISS_LOCAL_DRAM|
1589 HSW_SNOOP_DRAM,
1590 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1591 HSW_L3_MISS_REMOTE|
1592 HSW_SNOOP_DRAM,
1593 },
1594 [ C(OP_PREFETCH) ] = {
1595 [ C(RESULT_ACCESS) ] = 0x0,
1596 [ C(RESULT_MISS) ] = 0x0,
1597 },
1598 },
1599 };
1600
1601 static __initconst const u64 westmere_hw_cache_event_ids
1602 [PERF_COUNT_HW_CACHE_MAX]
1603 [PERF_COUNT_HW_CACHE_OP_MAX]
1604 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1605 {
1606 [ C(L1D) ] = {
1607 [ C(OP_READ) ] = {
1608 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1609 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1610 },
1611 [ C(OP_WRITE) ] = {
1612 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1613 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1614 },
1615 [ C(OP_PREFETCH) ] = {
1616 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1617 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1618 },
1619 },
1620 [ C(L1I ) ] = {
1621 [ C(OP_READ) ] = {
1622 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1623 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1624 },
1625 [ C(OP_WRITE) ] = {
1626 [ C(RESULT_ACCESS) ] = -1,
1627 [ C(RESULT_MISS) ] = -1,
1628 },
1629 [ C(OP_PREFETCH) ] = {
1630 [ C(RESULT_ACCESS) ] = 0x0,
1631 [ C(RESULT_MISS) ] = 0x0,
1632 },
1633 },
1634 [ C(LL ) ] = {
1635 [ C(OP_READ) ] = {
1636 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1637 [ C(RESULT_ACCESS) ] = 0x01b7,
1638 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1639 [ C(RESULT_MISS) ] = 0x01b7,
1640 },
1641 /*
1642 * Use RFO, not WRITEBACK, because a write miss would typically occur
1643 * on RFO.
1644 */
1645 [ C(OP_WRITE) ] = {
1646 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1647 [ C(RESULT_ACCESS) ] = 0x01b7,
1648 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1649 [ C(RESULT_MISS) ] = 0x01b7,
1650 },
1651 [ C(OP_PREFETCH) ] = {
1652 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1653 [ C(RESULT_ACCESS) ] = 0x01b7,
1654 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1655 [ C(RESULT_MISS) ] = 0x01b7,
1656 },
1657 },
1658 [ C(DTLB) ] = {
1659 [ C(OP_READ) ] = {
1660 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1661 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1662 },
1663 [ C(OP_WRITE) ] = {
1664 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1665 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1666 },
1667 [ C(OP_PREFETCH) ] = {
1668 [ C(RESULT_ACCESS) ] = 0x0,
1669 [ C(RESULT_MISS) ] = 0x0,
1670 },
1671 },
1672 [ C(ITLB) ] = {
1673 [ C(OP_READ) ] = {
1674 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1675 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1676 },
1677 [ C(OP_WRITE) ] = {
1678 [ C(RESULT_ACCESS) ] = -1,
1679 [ C(RESULT_MISS) ] = -1,
1680 },
1681 [ C(OP_PREFETCH) ] = {
1682 [ C(RESULT_ACCESS) ] = -1,
1683 [ C(RESULT_MISS) ] = -1,
1684 },
1685 },
1686 [ C(BPU ) ] = {
1687 [ C(OP_READ) ] = {
1688 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1689 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1690 },
1691 [ C(OP_WRITE) ] = {
1692 [ C(RESULT_ACCESS) ] = -1,
1693 [ C(RESULT_MISS) ] = -1,
1694 },
1695 [ C(OP_PREFETCH) ] = {
1696 [ C(RESULT_ACCESS) ] = -1,
1697 [ C(RESULT_MISS) ] = -1,
1698 },
1699 },
1700 [ C(NODE) ] = {
1701 [ C(OP_READ) ] = {
1702 [ C(RESULT_ACCESS) ] = 0x01b7,
1703 [ C(RESULT_MISS) ] = 0x01b7,
1704 },
1705 [ C(OP_WRITE) ] = {
1706 [ C(RESULT_ACCESS) ] = 0x01b7,
1707 [ C(RESULT_MISS) ] = 0x01b7,
1708 },
1709 [ C(OP_PREFETCH) ] = {
1710 [ C(RESULT_ACCESS) ] = 0x01b7,
1711 [ C(RESULT_MISS) ] = 0x01b7,
1712 },
1713 },
1714 };
1715
1716 /*
1717 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1718 * See IA32 SDM Vol 3B 30.6.1.3
1719 */
1720
1721 #define NHM_DMND_DATA_RD (1 << 0)
1722 #define NHM_DMND_RFO (1 << 1)
1723 #define NHM_DMND_IFETCH (1 << 2)
1724 #define NHM_DMND_WB (1 << 3)
1725 #define NHM_PF_DATA_RD (1 << 4)
1726 #define NHM_PF_DATA_RFO (1 << 5)
1727 #define NHM_PF_IFETCH (1 << 6)
1728 #define NHM_OFFCORE_OTHER (1 << 7)
1729 #define NHM_UNCORE_HIT (1 << 8)
1730 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1731 #define NHM_OTHER_CORE_HITM (1 << 10)
1732 /* reserved */
1733 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1734 #define NHM_REMOTE_DRAM (1 << 13)
1735 #define NHM_LOCAL_DRAM (1 << 14)
1736 #define NHM_NON_DRAM (1 << 15)
1737
1738 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1739 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1740
1741 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1742 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1743 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1744
1745 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1746 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1747 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1748
1749 static __initconst const u64 nehalem_hw_cache_extra_regs
1750 [PERF_COUNT_HW_CACHE_MAX]
1751 [PERF_COUNT_HW_CACHE_OP_MAX]
1752 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1753 {
1754 [ C(LL ) ] = {
1755 [ C(OP_READ) ] = {
1756 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1757 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1758 },
1759 [ C(OP_WRITE) ] = {
1760 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1761 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1762 },
1763 [ C(OP_PREFETCH) ] = {
1764 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1765 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1766 },
1767 },
1768 [ C(NODE) ] = {
1769 [ C(OP_READ) ] = {
1770 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1771 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1772 },
1773 [ C(OP_WRITE) ] = {
1774 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1775 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1776 },
1777 [ C(OP_PREFETCH) ] = {
1778 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1779 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1780 },
1781 },
1782 };
1783
1784 static __initconst const u64 nehalem_hw_cache_event_ids
1785 [PERF_COUNT_HW_CACHE_MAX]
1786 [PERF_COUNT_HW_CACHE_OP_MAX]
1787 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1788 {
1789 [ C(L1D) ] = {
1790 [ C(OP_READ) ] = {
1791 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1792 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1793 },
1794 [ C(OP_WRITE) ] = {
1795 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1796 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1797 },
1798 [ C(OP_PREFETCH) ] = {
1799 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1800 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1801 },
1802 },
1803 [ C(L1I ) ] = {
1804 [ C(OP_READ) ] = {
1805 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1806 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1807 },
1808 [ C(OP_WRITE) ] = {
1809 [ C(RESULT_ACCESS) ] = -1,
1810 [ C(RESULT_MISS) ] = -1,
1811 },
1812 [ C(OP_PREFETCH) ] = {
1813 [ C(RESULT_ACCESS) ] = 0x0,
1814 [ C(RESULT_MISS) ] = 0x0,
1815 },
1816 },
1817 [ C(LL ) ] = {
1818 [ C(OP_READ) ] = {
1819 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1820 [ C(RESULT_ACCESS) ] = 0x01b7,
1821 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1822 [ C(RESULT_MISS) ] = 0x01b7,
1823 },
1824 /*
1825 * Use RFO, not WRITEBACK, because a write miss would typically occur
1826 * on RFO.
1827 */
1828 [ C(OP_WRITE) ] = {
1829 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1830 [ C(RESULT_ACCESS) ] = 0x01b7,
1831 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1832 [ C(RESULT_MISS) ] = 0x01b7,
1833 },
1834 [ C(OP_PREFETCH) ] = {
1835 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1836 [ C(RESULT_ACCESS) ] = 0x01b7,
1837 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1838 [ C(RESULT_MISS) ] = 0x01b7,
1839 },
1840 },
1841 [ C(DTLB) ] = {
1842 [ C(OP_READ) ] = {
1843 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1844 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1845 },
1846 [ C(OP_WRITE) ] = {
1847 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1848 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1849 },
1850 [ C(OP_PREFETCH) ] = {
1851 [ C(RESULT_ACCESS) ] = 0x0,
1852 [ C(RESULT_MISS) ] = 0x0,
1853 },
1854 },
1855 [ C(ITLB) ] = {
1856 [ C(OP_READ) ] = {
1857 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1858 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1859 },
1860 [ C(OP_WRITE) ] = {
1861 [ C(RESULT_ACCESS) ] = -1,
1862 [ C(RESULT_MISS) ] = -1,
1863 },
1864 [ C(OP_PREFETCH) ] = {
1865 [ C(RESULT_ACCESS) ] = -1,
1866 [ C(RESULT_MISS) ] = -1,
1867 },
1868 },
1869 [ C(BPU ) ] = {
1870 [ C(OP_READ) ] = {
1871 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1872 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1873 },
1874 [ C(OP_WRITE) ] = {
1875 [ C(RESULT_ACCESS) ] = -1,
1876 [ C(RESULT_MISS) ] = -1,
1877 },
1878 [ C(OP_PREFETCH) ] = {
1879 [ C(RESULT_ACCESS) ] = -1,
1880 [ C(RESULT_MISS) ] = -1,
1881 },
1882 },
1883 [ C(NODE) ] = {
1884 [ C(OP_READ) ] = {
1885 [ C(RESULT_ACCESS) ] = 0x01b7,
1886 [ C(RESULT_MISS) ] = 0x01b7,
1887 },
1888 [ C(OP_WRITE) ] = {
1889 [ C(RESULT_ACCESS) ] = 0x01b7,
1890 [ C(RESULT_MISS) ] = 0x01b7,
1891 },
1892 [ C(OP_PREFETCH) ] = {
1893 [ C(RESULT_ACCESS) ] = 0x01b7,
1894 [ C(RESULT_MISS) ] = 0x01b7,
1895 },
1896 },
1897 };
1898
1899 static __initconst const u64 core2_hw_cache_event_ids
1900 [PERF_COUNT_HW_CACHE_MAX]
1901 [PERF_COUNT_HW_CACHE_OP_MAX]
1902 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1903 {
1904 [ C(L1D) ] = {
1905 [ C(OP_READ) ] = {
1906 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1907 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1908 },
1909 [ C(OP_WRITE) ] = {
1910 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1911 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1912 },
1913 [ C(OP_PREFETCH) ] = {
1914 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1915 [ C(RESULT_MISS) ] = 0,
1916 },
1917 },
1918 [ C(L1I ) ] = {
1919 [ C(OP_READ) ] = {
1920 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1921 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1922 },
1923 [ C(OP_WRITE) ] = {
1924 [ C(RESULT_ACCESS) ] = -1,
1925 [ C(RESULT_MISS) ] = -1,
1926 },
1927 [ C(OP_PREFETCH) ] = {
1928 [ C(RESULT_ACCESS) ] = 0,
1929 [ C(RESULT_MISS) ] = 0,
1930 },
1931 },
1932 [ C(LL ) ] = {
1933 [ C(OP_READ) ] = {
1934 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1935 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1936 },
1937 [ C(OP_WRITE) ] = {
1938 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1939 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1940 },
1941 [ C(OP_PREFETCH) ] = {
1942 [ C(RESULT_ACCESS) ] = 0,
1943 [ C(RESULT_MISS) ] = 0,
1944 },
1945 },
1946 [ C(DTLB) ] = {
1947 [ C(OP_READ) ] = {
1948 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1949 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1950 },
1951 [ C(OP_WRITE) ] = {
1952 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1953 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1954 },
1955 [ C(OP_PREFETCH) ] = {
1956 [ C(RESULT_ACCESS) ] = 0,
1957 [ C(RESULT_MISS) ] = 0,
1958 },
1959 },
1960 [ C(ITLB) ] = {
1961 [ C(OP_READ) ] = {
1962 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1963 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1964 },
1965 [ C(OP_WRITE) ] = {
1966 [ C(RESULT_ACCESS) ] = -1,
1967 [ C(RESULT_MISS) ] = -1,
1968 },
1969 [ C(OP_PREFETCH) ] = {
1970 [ C(RESULT_ACCESS) ] = -1,
1971 [ C(RESULT_MISS) ] = -1,
1972 },
1973 },
1974 [ C(BPU ) ] = {
1975 [ C(OP_READ) ] = {
1976 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1977 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1978 },
1979 [ C(OP_WRITE) ] = {
1980 [ C(RESULT_ACCESS) ] = -1,
1981 [ C(RESULT_MISS) ] = -1,
1982 },
1983 [ C(OP_PREFETCH) ] = {
1984 [ C(RESULT_ACCESS) ] = -1,
1985 [ C(RESULT_MISS) ] = -1,
1986 },
1987 },
1988 };
1989
1990 static __initconst const u64 atom_hw_cache_event_ids
1991 [PERF_COUNT_HW_CACHE_MAX]
1992 [PERF_COUNT_HW_CACHE_OP_MAX]
1993 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1994 {
1995 [ C(L1D) ] = {
1996 [ C(OP_READ) ] = {
1997 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1998 [ C(RESULT_MISS) ] = 0,
1999 },
2000 [ C(OP_WRITE) ] = {
2001 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
2002 [ C(RESULT_MISS) ] = 0,
2003 },
2004 [ C(OP_PREFETCH) ] = {
2005 [ C(RESULT_ACCESS) ] = 0x0,
2006 [ C(RESULT_MISS) ] = 0,
2007 },
2008 },
2009 [ C(L1I ) ] = {
2010 [ C(OP_READ) ] = {
2011 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
2012 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
2013 },
2014 [ C(OP_WRITE) ] = {
2015 [ C(RESULT_ACCESS) ] = -1,
2016 [ C(RESULT_MISS) ] = -1,
2017 },
2018 [ C(OP_PREFETCH) ] = {
2019 [ C(RESULT_ACCESS) ] = 0,
2020 [ C(RESULT_MISS) ] = 0,
2021 },
2022 },
2023 [ C(LL ) ] = {
2024 [ C(OP_READ) ] = {
2025 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
2026 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
2027 },
2028 [ C(OP_WRITE) ] = {
2029 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
2030 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
2031 },
2032 [ C(OP_PREFETCH) ] = {
2033 [ C(RESULT_ACCESS) ] = 0,
2034 [ C(RESULT_MISS) ] = 0,
2035 },
2036 },
2037 [ C(DTLB) ] = {
2038 [ C(OP_READ) ] = {
2039 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
2040 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
2041 },
2042 [ C(OP_WRITE) ] = {
2043 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
2044 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
2045 },
2046 [ C(OP_PREFETCH) ] = {
2047 [ C(RESULT_ACCESS) ] = 0,
2048 [ C(RESULT_MISS) ] = 0,
2049 },
2050 },
2051 [ C(ITLB) ] = {
2052 [ C(OP_READ) ] = {
2053 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
2054 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
2055 },
2056 [ C(OP_WRITE) ] = {
2057 [ C(RESULT_ACCESS) ] = -1,
2058 [ C(RESULT_MISS) ] = -1,
2059 },
2060 [ C(OP_PREFETCH) ] = {
2061 [ C(RESULT_ACCESS) ] = -1,
2062 [ C(RESULT_MISS) ] = -1,
2063 },
2064 },
2065 [ C(BPU ) ] = {
2066 [ C(OP_READ) ] = {
2067 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
2068 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
2069 },
2070 [ C(OP_WRITE) ] = {
2071 [ C(RESULT_ACCESS) ] = -1,
2072 [ C(RESULT_MISS) ] = -1,
2073 },
2074 [ C(OP_PREFETCH) ] = {
2075 [ C(RESULT_ACCESS) ] = -1,
2076 [ C(RESULT_MISS) ] = -1,
2077 },
2078 },
2079 };
2080
2081 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
2082 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
2083 /* no_alloc_cycles.not_delivered */
2084 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
2085 "event=0xca,umask=0x50");
2086 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
2087 /* uops_retired.all */
2088 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
2089 "event=0xc2,umask=0x10");
2090 /* uops_retired.all */
2091 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
2092 "event=0xc2,umask=0x10");
2093
2094 static struct attribute *slm_events_attrs[] = {
2095 EVENT_PTR(td_total_slots_slm),
2096 EVENT_PTR(td_total_slots_scale_slm),
2097 EVENT_PTR(td_fetch_bubbles_slm),
2098 EVENT_PTR(td_fetch_bubbles_scale_slm),
2099 EVENT_PTR(td_slots_issued_slm),
2100 EVENT_PTR(td_slots_retired_slm),
2101 NULL
2102 };
2103
2104 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
2105 {
2106 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2107 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
2108 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
2109 EVENT_EXTRA_END
2110 };
2111
2112 #define SLM_DMND_READ SNB_DMND_DATA_RD
2113 #define SLM_DMND_WRITE SNB_DMND_RFO
2114 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
2115
2116 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
2117 #define SLM_LLC_ACCESS SNB_RESP_ANY
2118 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
2119
2120 static __initconst const u64 slm_hw_cache_extra_regs
2121 [PERF_COUNT_HW_CACHE_MAX]
2122 [PERF_COUNT_HW_CACHE_OP_MAX]
2123 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
2124 {
2125 [ C(LL ) ] = {
2126 [ C(OP_READ) ] = {
2127 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
2128 [ C(RESULT_MISS) ] = 0,
2129 },
2130 [ C(OP_WRITE) ] = {
2131 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
2132 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
2133 },
2134 [ C(OP_PREFETCH) ] = {
2135 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
2136 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
2137 },
2138 },
2139 };
2140
2141 static __initconst const u64 slm_hw_cache_event_ids
2142 [PERF_COUNT_HW_CACHE_MAX]
2143 [PERF_COUNT_HW_CACHE_OP_MAX]
2144 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
2145 {
2146 [ C(L1D) ] = {
2147 [ C(OP_READ) ] = {
2148 [ C(RESULT_ACCESS) ] = 0,
2149 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
2150 },
2151 [ C(OP_WRITE) ] = {
2152 [ C(RESULT_ACCESS) ] = 0,
2153 [ C(RESULT_MISS) ] = 0,
2154 },
2155 [ C(OP_PREFETCH) ] = {
2156 [ C(RESULT_ACCESS) ] = 0,
2157 [ C(RESULT_MISS) ] = 0,
2158 },
2159 },
2160 [ C(L1I ) ] = {
2161 [ C(OP_READ) ] = {
2162 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
2163 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
2164 },
2165 [ C(OP_WRITE) ] = {
2166 [ C(RESULT_ACCESS) ] = -1,
2167 [ C(RESULT_MISS) ] = -1,
2168 },
2169 [ C(OP_PREFETCH) ] = {
2170 [ C(RESULT_ACCESS) ] = 0,
2171 [ C(RESULT_MISS) ] = 0,
2172 },
2173 },
2174 [ C(LL ) ] = {
2175 [ C(OP_READ) ] = {
2176 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
2177 [ C(RESULT_ACCESS) ] = 0x01b7,
2178 [ C(RESULT_MISS) ] = 0,
2179 },
2180 [ C(OP_WRITE) ] = {
2181 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
2182 [ C(RESULT_ACCESS) ] = 0x01b7,
2183 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
2184 [ C(RESULT_MISS) ] = 0x01b7,
2185 },
2186 [ C(OP_PREFETCH) ] = {
2187 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
2188 [ C(RESULT_ACCESS) ] = 0x01b7,
2189 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
2190 [ C(RESULT_MISS) ] = 0x01b7,
2191 },
2192 },
2193 [ C(DTLB) ] = {
2194 [ C(OP_READ) ] = {
2195 [ C(RESULT_ACCESS) ] = 0,
2196 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
2197 },
2198 [ C(OP_WRITE) ] = {
2199 [ C(RESULT_ACCESS) ] = 0,
2200 [ C(RESULT_MISS) ] = 0,
2201 },
2202 [ C(OP_PREFETCH) ] = {
2203 [ C(RESULT_ACCESS) ] = 0,
2204 [ C(RESULT_MISS) ] = 0,
2205 },
2206 },
2207 [ C(ITLB) ] = {
2208 [ C(OP_READ) ] = {
2209 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
2210 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
2211 },
2212 [ C(OP_WRITE) ] = {
2213 [ C(RESULT_ACCESS) ] = -1,
2214 [ C(RESULT_MISS) ] = -1,
2215 },
2216 [ C(OP_PREFETCH) ] = {
2217 [ C(RESULT_ACCESS) ] = -1,
2218 [ C(RESULT_MISS) ] = -1,
2219 },
2220 },
2221 [ C(BPU ) ] = {
2222 [ C(OP_READ) ] = {
2223 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
2224 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
2225 },
2226 [ C(OP_WRITE) ] = {
2227 [ C(RESULT_ACCESS) ] = -1,
2228 [ C(RESULT_MISS) ] = -1,
2229 },
2230 [ C(OP_PREFETCH) ] = {
2231 [ C(RESULT_ACCESS) ] = -1,
2232 [ C(RESULT_MISS) ] = -1,
2233 },
2234 },
2235 };
2236
2237 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
2238 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
2239 /* UOPS_NOT_DELIVERED.ANY */
2240 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
2241 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
2242 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
2243 /* UOPS_RETIRED.ANY */
2244 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
2245 /* UOPS_ISSUED.ANY */
2246 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
2247
2248 static struct attribute *glm_events_attrs[] = {
2249 EVENT_PTR(td_total_slots_glm),
2250 EVENT_PTR(td_total_slots_scale_glm),
2251 EVENT_PTR(td_fetch_bubbles_glm),
2252 EVENT_PTR(td_recovery_bubbles_glm),
2253 EVENT_PTR(td_slots_issued_glm),
2254 EVENT_PTR(td_slots_retired_glm),
2255 NULL
2256 };
2257
2258 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
2259 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2260 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
2261 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
2262 EVENT_EXTRA_END
2263 };
2264
2265 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
2266 #define GLM_DEMAND_RFO BIT_ULL(1)
2267 #define GLM_ANY_RESPONSE BIT_ULL(16)
2268 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
2269 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
2270 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
2271 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
2272 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
2273 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
2274 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
2275
2276 static __initconst const u64 glm_hw_cache_event_ids
2277 [PERF_COUNT_HW_CACHE_MAX]
2278 [PERF_COUNT_HW_CACHE_OP_MAX]
2279 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2280 [C(L1D)] = {
2281 [C(OP_READ)] = {
2282 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2283 [C(RESULT_MISS)] = 0x0,
2284 },
2285 [C(OP_WRITE)] = {
2286 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2287 [C(RESULT_MISS)] = 0x0,
2288 },
2289 [C(OP_PREFETCH)] = {
2290 [C(RESULT_ACCESS)] = 0x0,
2291 [C(RESULT_MISS)] = 0x0,
2292 },
2293 },
2294 [C(L1I)] = {
2295 [C(OP_READ)] = {
2296 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
2297 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
2298 },
2299 [C(OP_WRITE)] = {
2300 [C(RESULT_ACCESS)] = -1,
2301 [C(RESULT_MISS)] = -1,
2302 },
2303 [C(OP_PREFETCH)] = {
2304 [C(RESULT_ACCESS)] = 0x0,
2305 [C(RESULT_MISS)] = 0x0,
2306 },
2307 },
2308 [C(LL)] = {
2309 [C(OP_READ)] = {
2310 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2311 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2312 },
2313 [C(OP_WRITE)] = {
2314 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2315 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2316 },
2317 [C(OP_PREFETCH)] = {
2318 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2319 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2320 },
2321 },
2322 [C(DTLB)] = {
2323 [C(OP_READ)] = {
2324 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2325 [C(RESULT_MISS)] = 0x0,
2326 },
2327 [C(OP_WRITE)] = {
2328 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2329 [C(RESULT_MISS)] = 0x0,
2330 },
2331 [C(OP_PREFETCH)] = {
2332 [C(RESULT_ACCESS)] = 0x0,
2333 [C(RESULT_MISS)] = 0x0,
2334 },
2335 },
2336 [C(ITLB)] = {
2337 [C(OP_READ)] = {
2338 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
2339 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
2340 },
2341 [C(OP_WRITE)] = {
2342 [C(RESULT_ACCESS)] = -1,
2343 [C(RESULT_MISS)] = -1,
2344 },
2345 [C(OP_PREFETCH)] = {
2346 [C(RESULT_ACCESS)] = -1,
2347 [C(RESULT_MISS)] = -1,
2348 },
2349 },
2350 [C(BPU)] = {
2351 [C(OP_READ)] = {
2352 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
2353 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
2354 },
2355 [C(OP_WRITE)] = {
2356 [C(RESULT_ACCESS)] = -1,
2357 [C(RESULT_MISS)] = -1,
2358 },
2359 [C(OP_PREFETCH)] = {
2360 [C(RESULT_ACCESS)] = -1,
2361 [C(RESULT_MISS)] = -1,
2362 },
2363 },
2364 };
2365
2366 static __initconst const u64 glm_hw_cache_extra_regs
2367 [PERF_COUNT_HW_CACHE_MAX]
2368 [PERF_COUNT_HW_CACHE_OP_MAX]
2369 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2370 [C(LL)] = {
2371 [C(OP_READ)] = {
2372 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2373 GLM_LLC_ACCESS,
2374 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2375 GLM_LLC_MISS,
2376 },
2377 [C(OP_WRITE)] = {
2378 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2379 GLM_LLC_ACCESS,
2380 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2381 GLM_LLC_MISS,
2382 },
2383 [C(OP_PREFETCH)] = {
2384 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
2385 GLM_LLC_ACCESS,
2386 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
2387 GLM_LLC_MISS,
2388 },
2389 },
2390 };
2391
2392 static __initconst const u64 glp_hw_cache_event_ids
2393 [PERF_COUNT_HW_CACHE_MAX]
2394 [PERF_COUNT_HW_CACHE_OP_MAX]
2395 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2396 [C(L1D)] = {
2397 [C(OP_READ)] = {
2398 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2399 [C(RESULT_MISS)] = 0x0,
2400 },
2401 [C(OP_WRITE)] = {
2402 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2403 [C(RESULT_MISS)] = 0x0,
2404 },
2405 [C(OP_PREFETCH)] = {
2406 [C(RESULT_ACCESS)] = 0x0,
2407 [C(RESULT_MISS)] = 0x0,
2408 },
2409 },
2410 [C(L1I)] = {
2411 [C(OP_READ)] = {
2412 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
2413 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
2414 },
2415 [C(OP_WRITE)] = {
2416 [C(RESULT_ACCESS)] = -1,
2417 [C(RESULT_MISS)] = -1,
2418 },
2419 [C(OP_PREFETCH)] = {
2420 [C(RESULT_ACCESS)] = 0x0,
2421 [C(RESULT_MISS)] = 0x0,
2422 },
2423 },
2424 [C(LL)] = {
2425 [C(OP_READ)] = {
2426 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2427 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2428 },
2429 [C(OP_WRITE)] = {
2430 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2431 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2432 },
2433 [C(OP_PREFETCH)] = {
2434 [C(RESULT_ACCESS)] = 0x0,
2435 [C(RESULT_MISS)] = 0x0,
2436 },
2437 },
2438 [C(DTLB)] = {
2439 [C(OP_READ)] = {
2440 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2441 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
2442 },
2443 [C(OP_WRITE)] = {
2444 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2445 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
2446 },
2447 [C(OP_PREFETCH)] = {
2448 [C(RESULT_ACCESS)] = 0x0,
2449 [C(RESULT_MISS)] = 0x0,
2450 },
2451 },
2452 [C(ITLB)] = {
2453 [C(OP_READ)] = {
2454 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
2455 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
2456 },
2457 [C(OP_WRITE)] = {
2458 [C(RESULT_ACCESS)] = -1,
2459 [C(RESULT_MISS)] = -1,
2460 },
2461 [C(OP_PREFETCH)] = {
2462 [C(RESULT_ACCESS)] = -1,
2463 [C(RESULT_MISS)] = -1,
2464 },
2465 },
2466 [C(BPU)] = {
2467 [C(OP_READ)] = {
2468 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
2469 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
2470 },
2471 [C(OP_WRITE)] = {
2472 [C(RESULT_ACCESS)] = -1,
2473 [C(RESULT_MISS)] = -1,
2474 },
2475 [C(OP_PREFETCH)] = {
2476 [C(RESULT_ACCESS)] = -1,
2477 [C(RESULT_MISS)] = -1,
2478 },
2479 },
2480 };
2481
2482 static __initconst const u64 glp_hw_cache_extra_regs
2483 [PERF_COUNT_HW_CACHE_MAX]
2484 [PERF_COUNT_HW_CACHE_OP_MAX]
2485 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2486 [C(LL)] = {
2487 [C(OP_READ)] = {
2488 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2489 GLM_LLC_ACCESS,
2490 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2491 GLM_LLC_MISS,
2492 },
2493 [C(OP_WRITE)] = {
2494 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2495 GLM_LLC_ACCESS,
2496 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2497 GLM_LLC_MISS,
2498 },
2499 [C(OP_PREFETCH)] = {
2500 [C(RESULT_ACCESS)] = 0x0,
2501 [C(RESULT_MISS)] = 0x0,
2502 },
2503 },
2504 };
2505
2506 #define TNT_LOCAL_DRAM BIT_ULL(26)
2507 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD
2508 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO
2509 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE
2510 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
2511 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
2512 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
2513
2514 static __initconst const u64 tnt_hw_cache_extra_regs
2515 [PERF_COUNT_HW_CACHE_MAX]
2516 [PERF_COUNT_HW_CACHE_OP_MAX]
2517 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2518 [C(LL)] = {
2519 [C(OP_READ)] = {
2520 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
2521 TNT_LLC_ACCESS,
2522 [C(RESULT_MISS)] = TNT_DEMAND_READ|
2523 TNT_LLC_MISS,
2524 },
2525 [C(OP_WRITE)] = {
2526 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
2527 TNT_LLC_ACCESS,
2528 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
2529 TNT_LLC_MISS,
2530 },
2531 [C(OP_PREFETCH)] = {
2532 [C(RESULT_ACCESS)] = 0x0,
2533 [C(RESULT_MISS)] = 0x0,
2534 },
2535 },
2536 };
2537
2538 static __initconst const u64 grt_hw_cache_extra_regs
2539 [PERF_COUNT_HW_CACHE_MAX]
2540 [PERF_COUNT_HW_CACHE_OP_MAX]
2541 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2542 [C(LL)] = {
2543 [C(OP_READ)] = {
2544 [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
2545 [C(RESULT_MISS)] = 0x3F84400001, /* OCR.DEMAND_DATA_RD.L3_MISS */
2546 },
2547 [C(OP_WRITE)] = {
2548 [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
2549 [C(RESULT_MISS)] = 0x3F84400002, /* OCR.DEMAND_RFO.L3_MISS */
2550 },
2551 },
2552 };
2553
2554 static __initconst const u64 cmt_hw_cache_extra_regs
2555 [PERF_COUNT_HW_CACHE_MAX]
2556 [PERF_COUNT_HW_CACHE_OP_MAX]
2557 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2558 [C(LL)] = {
2559 [C(OP_READ)] = {
2560 [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
2561 [C(RESULT_MISS)] = 0x3fbfc00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
2562 },
2563 [C(OP_WRITE)] = {
2564 [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
2565 [C(RESULT_MISS)] = 0x3fbfc00002, /* OCR.DEMAND_RFO.L3_MISS */
2566 },
2567 },
2568 };
2569
2570 static __initconst const u64 skt_hw_cache_extra_regs
2571 [PERF_COUNT_HW_CACHE_MAX]
2572 [PERF_COUNT_HW_CACHE_OP_MAX]
2573 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2574 [C(LL)] = {
2575 [C(OP_READ)] = {
2576 [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
2577 [C(RESULT_MISS)] = 0x13FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
2578 },
2579 [C(OP_WRITE)] = {
2580 [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
2581 [C(RESULT_MISS)] = 0x13FBFC00002, /* OCR.DEMAND_RFO.L3_MISS */
2582 },
2583 },
2584 };
2585
2586 static __initconst const u64 dkt_hw_cache_extra_regs
2587 [PERF_COUNT_HW_CACHE_MAX]
2588 [PERF_COUNT_HW_CACHE_OP_MAX]
2589 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2590 [C(LL)] = {
2591 [C(OP_READ)] = {
2592 [C(RESULT_ACCESS)] = 0x10001, /* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
2593 [C(RESULT_MISS)] = 0x33FBFC00001, /* OCR.DEMAND_DATA_RD.L3_MISS */
2594 },
2595 [C(OP_WRITE)] = {
2596 [C(RESULT_ACCESS)] = 0x10002, /* OCR.DEMAND_RFO.ANY_RESPONSE */
2597 [C(RESULT_MISS)] = 0x33FBFC00002, /* OCR.DEMAND_RFO.L3_MISS */
2598 },
2599 },
2600 };
2601
2602 static __initconst const u64 arw_hw_cache_extra_regs
2603 [PERF_COUNT_HW_CACHE_MAX]
2604 [PERF_COUNT_HW_CACHE_OP_MAX]
2605 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2606 [C(LL)] = {
2607 [C(OP_READ)] = {
2608 [C(RESULT_ACCESS)] = 0x4000000000000009, /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */
2609 [C(RESULT_MISS)] = 0xFF03F000000009, /* OMR.DEMAND_DATA_RD.L3_MISS */
2610 },
2611 [C(OP_WRITE)] = {
2612 [C(RESULT_ACCESS)] = 0x400000000000000A, /* OMR.DEMAND_RFO.ANY_RESPONSE */
2613 [C(RESULT_MISS)] = 0xFF03F00000000A, /* OMR.DEMAND_RFO.L3_MISS */
2614 },
2615 },
2616 };
2617
2618 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_tnt, "event=0x71,umask=0x0");
2619 EVENT_ATTR_STR(topdown-retiring, td_retiring_tnt, "event=0xc2,umask=0x0");
2620 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_tnt, "event=0x73,umask=0x6");
2621 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_tnt, "event=0x74,umask=0x0");
2622
2623 static struct attribute *tnt_events_attrs[] = {
2624 EVENT_PTR(td_fe_bound_tnt),
2625 EVENT_PTR(td_retiring_tnt),
2626 EVENT_PTR(td_bad_spec_tnt),
2627 EVENT_PTR(td_be_bound_tnt),
2628 NULL,
2629 };
2630
2631 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
2632 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2633 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
2634 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
2635 EVENT_EXTRA_END
2636 };
2637
2638 EVENT_ATTR_STR(mem-loads, mem_ld_grt, "event=0xd0,umask=0x5,ldlat=3");
2639 EVENT_ATTR_STR(mem-stores, mem_st_grt, "event=0xd0,umask=0x6");
2640
2641 static struct attribute *grt_mem_attrs[] = {
2642 EVENT_PTR(mem_ld_grt),
2643 EVENT_PTR(mem_st_grt),
2644 NULL
2645 };
2646
2647 static struct extra_reg intel_grt_extra_regs[] __read_mostly = {
2648 /*
2649 * Must define OFFCORE_RSP_X first, see intel_fixup_er().
2650 * Bit 63 only valid on OFFCORE_RSP_0 MSR.
2651 */
2652 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x8003f03fffffffffull, RSP_0),
2653 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x3f03fffffffffull, RSP_1),
2654 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2655 EVENT_EXTRA_END
2656 };
2657
2658 EVENT_ATTR_STR(topdown-retiring, td_retiring_cmt, "event=0x72,umask=0x0");
2659 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec_cmt, "event=0x73,umask=0x0");
2660
2661 static struct attribute *cmt_events_attrs[] = {
2662 EVENT_PTR(td_fe_bound_tnt),
2663 EVENT_PTR(td_retiring_cmt),
2664 EVENT_PTR(td_bad_spec_cmt),
2665 EVENT_PTR(td_be_bound_tnt),
2666 NULL
2667 };
2668
2669 static struct extra_reg intel_cmt_extra_regs[] __read_mostly = {
2670 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
2671 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff3ffffffffffull, RSP_0),
2672 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff3ffffffffffull, RSP_1),
2673 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2674 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0),
2675 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1),
2676 EVENT_EXTRA_END
2677 };
2678
2679 static struct extra_reg intel_arw_extra_regs[] __read_mostly = {
2680 /* must define OMR_X first, see intel_alt_er() */
2681 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OMR_0, 0xc0ffffffffffffffull, OMR_0),
2682 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1),
2683 INTEL_UEVENT_EXTRA_REG(0x04b7, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2),
2684 INTEL_UEVENT_EXTRA_REG(0x08b7, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3),
2685 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
2686 INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0),
2687 INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1),
2688 EVENT_EXTRA_END
2689 };
2690
2691 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_skt, "event=0x9c,umask=0x01");
2692 EVENT_ATTR_STR(topdown-retiring, td_retiring_skt, "event=0xc2,umask=0x02");
2693 EVENT_ATTR_STR(topdown-be-bound, td_be_bound_skt, "event=0xa4,umask=0x02");
2694
2695 static struct attribute *skt_events_attrs[] = {
2696 EVENT_PTR(td_fe_bound_skt),
2697 EVENT_PTR(td_retiring_skt),
2698 EVENT_PTR(td_bad_spec_cmt),
2699 EVENT_PTR(td_be_bound_skt),
2700 NULL,
2701 };
2702
2703 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
2704 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
2705 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
2706 #define KNL_MCDRAM_FAR BIT_ULL(22)
2707 #define KNL_DDR_LOCAL BIT_ULL(23)
2708 #define KNL_DDR_FAR BIT_ULL(24)
2709 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
2710 KNL_DDR_LOCAL | KNL_DDR_FAR)
2711 #define KNL_L2_READ SLM_DMND_READ
2712 #define KNL_L2_WRITE SLM_DMND_WRITE
2713 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
2714 #define KNL_L2_ACCESS SLM_LLC_ACCESS
2715 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
2716 KNL_DRAM_ANY | SNB_SNP_ANY | \
2717 SNB_NON_DRAM)
2718
2719 static __initconst const u64 knl_hw_cache_extra_regs
2720 [PERF_COUNT_HW_CACHE_MAX]
2721 [PERF_COUNT_HW_CACHE_OP_MAX]
2722 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2723 [C(LL)] = {
2724 [C(OP_READ)] = {
2725 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
2726 [C(RESULT_MISS)] = 0,
2727 },
2728 [C(OP_WRITE)] = {
2729 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
2730 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
2731 },
2732 [C(OP_PREFETCH)] = {
2733 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
2734 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
2735 },
2736 },
2737 };
2738
2739 /*
2740 * Used from PMIs where the LBRs are already disabled.
2741 *
2742 * This function could be called consecutively. It is required to remain in
2743 * disabled state if called consecutively.
2744 *
2745 * During consecutive calls, the same disable value will be written to related
2746 * registers, so the PMU state remains unchanged.
2747 *
2748 * intel_bts events don't coexist with intel PMU's BTS events because of
2749 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
2750 * disabled around intel PMU's event batching etc, only inside the PMI handler.
2751 *
2752 * Avoid PEBS_ENABLE MSR access in PMIs.
2753 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore.
2754 * It doesn't matter if the PEBS is enabled or not.
2755 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to
2756 * access PEBS_ENABLE MSR in disable_all()/enable_all().
2757 * However, there are some cases which may change PEBS status, e.g. PMI
2758 * throttle. The PEBS_ENABLE should be updated where the status changes.
2759 */
__intel_pmu_disable_all(bool bts)2760 static __always_inline void __intel_pmu_disable_all(bool bts)
2761 {
2762 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2763
2764 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2765
2766 if (bts && test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
2767 intel_pmu_disable_bts();
2768 }
2769
intel_pmu_disable_all(void)2770 static __always_inline void intel_pmu_disable_all(void)
2771 {
2772 __intel_pmu_disable_all(true);
2773 static_call_cond(x86_pmu_pebs_disable_all)();
2774 intel_pmu_lbr_disable_all();
2775 }
2776
__intel_pmu_enable_all(int added,bool pmi)2777 static void __intel_pmu_enable_all(int added, bool pmi)
2778 {
2779 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2780 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
2781
2782 intel_pmu_lbr_enable_all(pmi);
2783
2784 if (cpuc->fixed_ctrl_val != cpuc->active_fixed_ctrl_val) {
2785 wrmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, cpuc->fixed_ctrl_val);
2786 cpuc->active_fixed_ctrl_val = cpuc->fixed_ctrl_val;
2787 }
2788
2789 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL,
2790 intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
2791
2792 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2793 struct perf_event *event =
2794 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
2795
2796 if (WARN_ON_ONCE(!event))
2797 return;
2798
2799 intel_pmu_enable_bts(event->hw.config);
2800 }
2801 }
2802
intel_pmu_enable_all(int added)2803 static void intel_pmu_enable_all(int added)
2804 {
2805 static_call_cond(x86_pmu_pebs_enable_all)();
2806 __intel_pmu_enable_all(added, false);
2807 }
2808
2809 static noinline int
__intel_pmu_snapshot_branch_stack(struct perf_branch_entry * entries,unsigned int cnt,unsigned long flags)2810 __intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries,
2811 unsigned int cnt, unsigned long flags)
2812 {
2813 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2814
2815 intel_pmu_lbr_read();
2816 cnt = min_t(unsigned int, cnt, x86_pmu.lbr_nr);
2817
2818 memcpy(entries, cpuc->lbr_entries, sizeof(struct perf_branch_entry) * cnt);
2819 intel_pmu_enable_all(0);
2820 local_irq_restore(flags);
2821 return cnt;
2822 }
2823
2824 static int
intel_pmu_snapshot_branch_stack(struct perf_branch_entry * entries,unsigned int cnt)2825 intel_pmu_snapshot_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2826 {
2827 unsigned long flags;
2828
2829 /* must not have branches... */
2830 local_irq_save(flags);
2831 __intel_pmu_disable_all(false); /* we don't care about BTS */
2832 __intel_pmu_lbr_disable();
2833 /* ... until here */
2834 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2835 }
2836
2837 static int
intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry * entries,unsigned int cnt)2838 intel_pmu_snapshot_arch_branch_stack(struct perf_branch_entry *entries, unsigned int cnt)
2839 {
2840 unsigned long flags;
2841
2842 /* must not have branches... */
2843 local_irq_save(flags);
2844 __intel_pmu_disable_all(false); /* we don't care about BTS */
2845 __intel_pmu_arch_lbr_disable();
2846 /* ... until here */
2847 return __intel_pmu_snapshot_branch_stack(entries, cnt, flags);
2848 }
2849
2850 /*
2851 * Workaround for:
2852 * Intel Errata AAK100 (model 26)
2853 * Intel Errata AAP53 (model 30)
2854 * Intel Errata BD53 (model 44)
2855 *
2856 * The official story:
2857 * These chips need to be 'reset' when adding counters by programming the
2858 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2859 * in sequence on the same PMC or on different PMCs.
2860 *
2861 * In practice it appears some of these events do in fact count, and
2862 * we need to program all 4 events.
2863 */
intel_pmu_nhm_workaround(void)2864 static void intel_pmu_nhm_workaround(void)
2865 {
2866 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2867 static const unsigned long nhm_magic[4] = {
2868 0x4300B5,
2869 0x4300D2,
2870 0x4300B1,
2871 0x4300B1
2872 };
2873 struct perf_event *event;
2874 int i;
2875
2876 /*
2877 * The Errata requires below steps:
2878 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2879 * 2) Configure 4 PERFEVTSELx with the magic events and clear
2880 * the corresponding PMCx;
2881 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2882 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2883 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2884 */
2885
2886 /*
2887 * The real steps we choose are a little different from above.
2888 * A) To reduce MSR operations, we don't run step 1) as they
2889 * are already cleared before this function is called;
2890 * B) Call x86_perf_event_update to save PMCx before configuring
2891 * PERFEVTSELx with magic number;
2892 * C) With step 5), we do clear only when the PERFEVTSELx is
2893 * not used currently.
2894 * D) Call x86_perf_event_set_period to restore PMCx;
2895 */
2896
2897 /* We always operate 4 pairs of PERF Counters */
2898 for (i = 0; i < 4; i++) {
2899 event = cpuc->events[i];
2900 if (event)
2901 static_call(x86_pmu_update)(event);
2902 }
2903
2904 for (i = 0; i < 4; i++) {
2905 wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2906 wrmsrq(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2907 }
2908
2909 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2910 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2911
2912 for (i = 0; i < 4; i++) {
2913 event = cpuc->events[i];
2914
2915 if (event) {
2916 static_call(x86_pmu_set_period)(event);
2917 __x86_pmu_enable_event(&event->hw,
2918 ARCH_PERFMON_EVENTSEL_ENABLE);
2919 } else
2920 wrmsrq(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2921 }
2922 }
2923
intel_pmu_nhm_enable_all(int added)2924 static void intel_pmu_nhm_enable_all(int added)
2925 {
2926 if (added)
2927 intel_pmu_nhm_workaround();
2928 intel_pmu_enable_all(added);
2929 }
2930
intel_set_tfa(struct cpu_hw_events * cpuc,bool on)2931 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2932 {
2933 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2934
2935 if (cpuc->tfa_shadow != val) {
2936 cpuc->tfa_shadow = val;
2937 wrmsrq(MSR_TSX_FORCE_ABORT, val);
2938 }
2939 }
2940
intel_tfa_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)2941 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2942 {
2943 /*
2944 * We're going to use PMC3, make sure TFA is set before we touch it.
2945 */
2946 if (cntr == 3)
2947 intel_set_tfa(cpuc, true);
2948 }
2949
intel_tfa_pmu_enable_all(int added)2950 static void intel_tfa_pmu_enable_all(int added)
2951 {
2952 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2953
2954 /*
2955 * If we find PMC3 is no longer used when we enable the PMU, we can
2956 * clear TFA.
2957 */
2958 if (!test_bit(3, cpuc->active_mask))
2959 intel_set_tfa(cpuc, false);
2960
2961 intel_pmu_enable_all(added);
2962 }
2963
intel_pmu_get_status(void)2964 static inline u64 intel_pmu_get_status(void)
2965 {
2966 u64 status;
2967
2968 rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status);
2969
2970 return status;
2971 }
2972
intel_pmu_ack_status(u64 ack)2973 static inline void intel_pmu_ack_status(u64 ack)
2974 {
2975 wrmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2976 }
2977
event_is_checkpointed(struct perf_event * event)2978 static inline bool event_is_checkpointed(struct perf_event *event)
2979 {
2980 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2981 }
2982
intel_set_masks(struct perf_event * event,int idx)2983 static inline void intel_set_masks(struct perf_event *event, int idx)
2984 {
2985 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2986
2987 if (event->attr.exclude_host)
2988 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2989 if (event->attr.exclude_guest)
2990 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2991 if (event_is_checkpointed(event))
2992 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2993 }
2994
intel_clear_masks(struct perf_event * event,int idx)2995 static inline void intel_clear_masks(struct perf_event *event, int idx)
2996 {
2997 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2998
2999 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
3000 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
3001 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
3002 }
3003
intel_pmu_disable_fixed(struct perf_event * event)3004 static void intel_pmu_disable_fixed(struct perf_event *event)
3005 {
3006 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3007 struct hw_perf_event *hwc = &event->hw;
3008 int idx = hwc->idx;
3009 u64 mask;
3010
3011 if (is_topdown_idx(idx)) {
3012 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3013
3014 /*
3015 * When there are other active TopDown events,
3016 * don't disable the fixed counter 3.
3017 */
3018 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
3019 return;
3020 idx = INTEL_PMC_IDX_FIXED_SLOTS;
3021 }
3022
3023 intel_clear_masks(event, idx);
3024
3025 mask = intel_fixed_bits_by_idx(idx - INTEL_PMC_IDX_FIXED, INTEL_FIXED_BITS_MASK);
3026 cpuc->fixed_ctrl_val &= ~mask;
3027 }
3028
__intel_pmu_update_event_ext(int idx,u64 ext)3029 static inline void __intel_pmu_update_event_ext(int idx, u64 ext)
3030 {
3031 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3032 u32 msr;
3033
3034 if (idx < INTEL_PMC_IDX_FIXED) {
3035 msr = MSR_IA32_PMC_V6_GP0_CFG_C +
3036 x86_pmu.addr_offset(idx, false);
3037 } else {
3038 msr = MSR_IA32_PMC_V6_FX0_CFG_C +
3039 x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false);
3040 }
3041
3042 cpuc->cfg_c_val[idx] = ext;
3043 wrmsrq(msr, ext);
3044 }
3045
intel_pmu_disable_event_ext(struct perf_event * event)3046 static void intel_pmu_disable_event_ext(struct perf_event *event)
3047 {
3048 /*
3049 * Only clear CFG_C MSR for PEBS counter group events,
3050 * it avoids the HW counter's value to be added into
3051 * other PEBS records incorrectly after PEBS counter
3052 * group events are disabled.
3053 *
3054 * For other events, it's unnecessary to clear CFG_C MSRs
3055 * since CFG_C doesn't take effect if counter is in
3056 * disabled state. That helps to reduce the WRMSR overhead
3057 * in context switches.
3058 */
3059 if (!is_pebs_counter_event_group(event))
3060 return;
3061
3062 __intel_pmu_update_event_ext(event->hw.idx, 0);
3063 }
3064
3065 DEFINE_STATIC_CALL_NULL(intel_pmu_disable_event_ext, intel_pmu_disable_event_ext);
3066
intel_pmu_disable_event(struct perf_event * event)3067 static void intel_pmu_disable_event(struct perf_event *event)
3068 {
3069 struct hw_perf_event *hwc = &event->hw;
3070 int idx = hwc->idx;
3071
3072 switch (idx) {
3073 case 0 ... INTEL_PMC_IDX_FIXED - 1:
3074 intel_clear_masks(event, idx);
3075 static_call_cond(intel_pmu_disable_event_ext)(event);
3076 x86_pmu_disable_event(event);
3077 break;
3078 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
3079 static_call_cond(intel_pmu_disable_event_ext)(event);
3080 fallthrough;
3081 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
3082 intel_pmu_disable_fixed(event);
3083 break;
3084 case INTEL_PMC_IDX_FIXED_BTS:
3085 intel_pmu_disable_bts();
3086 intel_pmu_drain_bts_buffer();
3087 return;
3088 case INTEL_PMC_IDX_FIXED_VLBR:
3089 intel_clear_masks(event, idx);
3090 break;
3091 default:
3092 intel_clear_masks(event, idx);
3093 pr_warn("Failed to disable the event with invalid index %d\n",
3094 idx);
3095 return;
3096 }
3097
3098 /*
3099 * Needs to be called after x86_pmu_disable_event,
3100 * so we don't trigger the event without PEBS bit set.
3101 */
3102 if (unlikely(event->attr.precise_ip))
3103 static_call(x86_pmu_pebs_disable)(event);
3104 }
3105
intel_pmu_assign_event(struct perf_event * event,int idx)3106 static void intel_pmu_assign_event(struct perf_event *event, int idx)
3107 {
3108 if (is_pebs_pt(event))
3109 perf_report_aux_output_id(event, idx);
3110 }
3111
intel_pmu_needs_branch_stack(struct perf_event * event)3112 static __always_inline bool intel_pmu_needs_branch_stack(struct perf_event *event)
3113 {
3114 return event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK;
3115 }
3116
intel_pmu_del_event(struct perf_event * event)3117 static void intel_pmu_del_event(struct perf_event *event)
3118 {
3119 if (intel_pmu_needs_branch_stack(event))
3120 intel_pmu_lbr_del(event);
3121 if (event->attr.precise_ip)
3122 intel_pmu_pebs_del(event);
3123 if (is_pebs_counter_event_group(event) ||
3124 is_acr_event_group(event))
3125 this_cpu_ptr(&cpu_hw_events)->n_late_setup--;
3126 }
3127
__intel_pmu_quiesce(void)3128 int __intel_pmu_quiesce(void)
3129 {
3130 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3131 int pmu_enabled = cpuc->enabled;
3132
3133 cpuc->enabled = 0;
3134 if (pmu_enabled)
3135 intel_pmu_disable_all();
3136
3137 return pmu_enabled;
3138 }
3139
__intel_pmu_resume(int pmu_enabled)3140 void __intel_pmu_resume(int pmu_enabled)
3141 {
3142 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3143
3144 cpuc->enabled = pmu_enabled;
3145 if (pmu_enabled)
3146 intel_pmu_enable_all(0);
3147 }
3148
icl_set_topdown_event_period(struct perf_event * event)3149 static int icl_set_topdown_event_period(struct perf_event *event)
3150 {
3151 struct hw_perf_event *hwc = &event->hw;
3152 s64 left = local64_read(&hwc->period_left);
3153
3154 /*
3155 * The values in PERF_METRICS MSR are derived from fixed counter 3.
3156 * Software should start both registers, PERF_METRICS and fixed
3157 * counter 3, from zero.
3158 * Clear PERF_METRICS and Fixed counter 3 in initialization.
3159 * After that, both MSRs will be cleared for each read.
3160 * Don't need to clear them again.
3161 */
3162 if (left == x86_pmu.max_period) {
3163 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0);
3164 wrmsrq(MSR_PERF_METRICS, 0);
3165 hwc->saved_slots = 0;
3166 hwc->saved_metric = 0;
3167 }
3168
3169 if ((hwc->saved_slots) && is_slots_event(event)) {
3170 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots);
3171 wrmsrq(MSR_PERF_METRICS, hwc->saved_metric);
3172 }
3173
3174 perf_event_update_userpage(event);
3175
3176 return 0;
3177 }
3178
3179 DEFINE_STATIC_CALL(intel_pmu_set_topdown_event_period, x86_perf_event_set_period);
3180
icl_get_metrics_event_value(u64 metric,u64 slots,int idx)3181 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx)
3182 {
3183 u32 val;
3184
3185 /*
3186 * The metric is reported as an 8bit integer fraction
3187 * summing up to 0xff.
3188 * slots-in-metric = (Metric / 0xff) * slots
3189 */
3190 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff;
3191 return mul_u64_u32_div(slots, val, 0xff);
3192 }
3193
icl_get_topdown_value(struct perf_event * event,u64 slots,u64 metrics)3194 static u64 icl_get_topdown_value(struct perf_event *event,
3195 u64 slots, u64 metrics)
3196 {
3197 int idx = event->hw.idx;
3198 u64 delta;
3199
3200 if (is_metric_idx(idx))
3201 delta = icl_get_metrics_event_value(metrics, slots, idx);
3202 else
3203 delta = slots;
3204
3205 return delta;
3206 }
3207
__icl_update_topdown_event(struct perf_event * event,u64 slots,u64 metrics,u64 last_slots,u64 last_metrics)3208 static void __icl_update_topdown_event(struct perf_event *event,
3209 u64 slots, u64 metrics,
3210 u64 last_slots, u64 last_metrics)
3211 {
3212 u64 delta, last = 0;
3213
3214 delta = icl_get_topdown_value(event, slots, metrics);
3215 if (last_slots)
3216 last = icl_get_topdown_value(event, last_slots, last_metrics);
3217
3218 /*
3219 * The 8bit integer fraction of metric may be not accurate,
3220 * especially when the changes is very small.
3221 * For example, if only a few bad_spec happens, the fraction
3222 * may be reduced from 1 to 0. If so, the bad_spec event value
3223 * will be 0 which is definitely less than the last value.
3224 * Avoid update event->count for this case.
3225 */
3226 if (delta > last) {
3227 delta -= last;
3228 local64_add(delta, &event->count);
3229 }
3230 }
3231
update_saved_topdown_regs(struct perf_event * event,u64 slots,u64 metrics,int metric_end)3232 static void update_saved_topdown_regs(struct perf_event *event, u64 slots,
3233 u64 metrics, int metric_end)
3234 {
3235 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3236 struct perf_event *other;
3237 int idx;
3238
3239 event->hw.saved_slots = slots;
3240 event->hw.saved_metric = metrics;
3241
3242 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
3243 if (!is_topdown_idx(idx))
3244 continue;
3245 other = cpuc->events[idx];
3246 other->hw.saved_slots = slots;
3247 other->hw.saved_metric = metrics;
3248 }
3249 }
3250
3251 /*
3252 * Update all active Topdown events.
3253 *
3254 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be
3255 * modify by a NMI. PMU has to be disabled before calling this function.
3256 */
3257
intel_update_topdown_event(struct perf_event * event,int metric_end,u64 * val)3258 static u64 intel_update_topdown_event(struct perf_event *event, int metric_end, u64 *val)
3259 {
3260 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3261 struct perf_event *other;
3262 u64 slots, metrics;
3263 bool reset = true;
3264 int idx;
3265
3266 if (!val) {
3267 /* read Fixed counter 3 */
3268 slots = rdpmc(3 | INTEL_PMC_FIXED_RDPMC_BASE);
3269 if (!slots)
3270 return 0;
3271
3272 /* read PERF_METRICS */
3273 metrics = rdpmc(INTEL_PMC_FIXED_RDPMC_METRICS);
3274 } else {
3275 slots = val[0];
3276 metrics = val[1];
3277 /*
3278 * Don't reset the PERF_METRICS and Fixed counter 3
3279 * for each PEBS record read. Utilize the RDPMC metrics
3280 * clear mode.
3281 */
3282 reset = false;
3283 }
3284
3285 for_each_set_bit(idx, cpuc->active_mask, metric_end + 1) {
3286 if (!is_topdown_idx(idx))
3287 continue;
3288 other = cpuc->events[idx];
3289 __icl_update_topdown_event(other, slots, metrics,
3290 event ? event->hw.saved_slots : 0,
3291 event ? event->hw.saved_metric : 0);
3292 }
3293
3294 /*
3295 * Check and update this event, which may have been cleared
3296 * in active_mask e.g. x86_pmu_stop()
3297 */
3298 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) {
3299 __icl_update_topdown_event(event, slots, metrics,
3300 event->hw.saved_slots,
3301 event->hw.saved_metric);
3302
3303 /*
3304 * In x86_pmu_stop(), the event is cleared in active_mask first,
3305 * then drain the delta, which indicates context switch for
3306 * counting.
3307 * Save metric and slots for context switch.
3308 * Don't need to reset the PERF_METRICS and Fixed counter 3.
3309 * Because the values will be restored in next schedule in.
3310 */
3311 update_saved_topdown_regs(event, slots, metrics, metric_end);
3312 reset = false;
3313 }
3314
3315 if (reset) {
3316 /* The fixed counter 3 has to be written before the PERF_METRICS. */
3317 wrmsrq(MSR_CORE_PERF_FIXED_CTR3, 0);
3318 wrmsrq(MSR_PERF_METRICS, 0);
3319 if (event)
3320 update_saved_topdown_regs(event, 0, 0, metric_end);
3321 }
3322
3323 return slots;
3324 }
3325
icl_update_topdown_event(struct perf_event * event,u64 * val)3326 static u64 icl_update_topdown_event(struct perf_event *event, u64 *val)
3327 {
3328 return intel_update_topdown_event(event, INTEL_PMC_IDX_METRIC_BASE +
3329 x86_pmu.num_topdown_events - 1,
3330 val);
3331 }
3332
3333 DEFINE_STATIC_CALL(intel_pmu_update_topdown_event, intel_pmu_topdown_event_update);
3334
intel_pmu_read_event(struct perf_event * event)3335 static void intel_pmu_read_event(struct perf_event *event)
3336 {
3337 if (event->hw.flags & (PERF_X86_EVENT_AUTO_RELOAD | PERF_X86_EVENT_TOPDOWN) ||
3338 is_pebs_counter_event_group(event)) {
3339 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3340 int pmu_enabled;
3341
3342 /* Only need to call update_topdown_event() once for group read. */
3343 if (is_metric_event(event) && (cpuc->txn_flags & PERF_PMU_TXN_READ))
3344 return;
3345
3346 pmu_enabled = __intel_pmu_quiesce();
3347 /*
3348 * If the PEBS counters snapshotting is enabled,
3349 * the topdown event is available in PEBS records.
3350 */
3351 if (is_topdown_count(event) && !is_pebs_counter_event_group(event))
3352 static_call(intel_pmu_update_topdown_event)(event, NULL);
3353 else
3354 intel_pmu_drain_pebs_buffer();
3355 __intel_pmu_resume(pmu_enabled);
3356
3357 return;
3358 }
3359
3360 x86_perf_event_update(event);
3361 }
3362
intel_pmu_enable_fixed(struct perf_event * event)3363 static void intel_pmu_enable_fixed(struct perf_event *event)
3364 {
3365 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3366 struct hw_perf_event *hwc = &event->hw;
3367 int idx = hwc->idx;
3368 u64 bits = 0;
3369
3370 if (is_topdown_idx(idx)) {
3371 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3372 /*
3373 * When there are other active TopDown events,
3374 * don't enable the fixed counter 3 again.
3375 */
3376 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
3377 return;
3378
3379 idx = INTEL_PMC_IDX_FIXED_SLOTS;
3380
3381 if (event->attr.config1 & INTEL_TD_CFG_METRIC_CLEAR)
3382 bits |= INTEL_FIXED_3_METRICS_CLEAR;
3383 }
3384
3385 intel_set_masks(event, idx);
3386
3387 /*
3388 * Enable IRQ generation (0x8), if not PEBS or self-reloaded
3389 * ACR event, and enable ring-3 counting (0x2) and ring-0
3390 * counting (0x1) if requested:
3391 */
3392 if (!event->attr.precise_ip && !is_acr_self_reload_event(event))
3393 bits |= INTEL_FIXED_0_ENABLE_PMI;
3394 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
3395 bits |= INTEL_FIXED_0_USER;
3396 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
3397 bits |= INTEL_FIXED_0_KERNEL;
3398 if (hwc->config & ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE)
3399 bits |= INTEL_FIXED_0_RDPMC_USER_DISABLE;
3400
3401 /*
3402 * ANY bit is supported in v3 and up
3403 */
3404 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
3405 bits |= INTEL_FIXED_0_ANYTHREAD;
3406
3407 idx -= INTEL_PMC_IDX_FIXED;
3408 bits = intel_fixed_bits_by_idx(idx, bits);
3409 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip)
3410 bits |= intel_fixed_bits_by_idx(idx, ICL_FIXED_0_ADAPTIVE);
3411
3412 cpuc->fixed_ctrl_val &= ~intel_fixed_bits_by_idx(idx, INTEL_FIXED_BITS_MASK);
3413 cpuc->fixed_ctrl_val |= bits;
3414 }
3415
intel_pmu_config_acr(int idx,u64 mask,u32 reload)3416 static void intel_pmu_config_acr(int idx, u64 mask, u32 reload)
3417 {
3418 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3419 int msr_b, msr_c;
3420 int msr_offset;
3421
3422 if (!mask && !cpuc->acr_cfg_b[idx])
3423 return;
3424
3425 if (idx < INTEL_PMC_IDX_FIXED) {
3426 msr_b = MSR_IA32_PMC_V6_GP0_CFG_B;
3427 msr_c = MSR_IA32_PMC_V6_GP0_CFG_C;
3428 msr_offset = x86_pmu.addr_offset(idx, false);
3429 } else {
3430 msr_b = MSR_IA32_PMC_V6_FX0_CFG_B;
3431 msr_c = MSR_IA32_PMC_V6_FX0_CFG_C;
3432 msr_offset = x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false);
3433 }
3434
3435 if (cpuc->acr_cfg_b[idx] != mask) {
3436 wrmsrq(msr_b + msr_offset, mask);
3437 cpuc->acr_cfg_b[idx] = mask;
3438 }
3439 /* Only update CFG_C reload when ACR is actively enabled (mask != 0) */
3440 if (mask && ((cpuc->cfg_c_val[idx] & ARCH_PEBS_RELOAD) != reload)) {
3441 wrmsrq(msr_c + msr_offset, reload);
3442 cpuc->cfg_c_val[idx] = reload;
3443 }
3444 }
3445
intel_pmu_enable_acr(struct perf_event * event)3446 static void intel_pmu_enable_acr(struct perf_event *event)
3447 {
3448 struct hw_perf_event *hwc = &event->hw;
3449
3450 if (!is_acr_event_group(event) || !event->attr.config2) {
3451 /*
3452 * The disable doesn't clear the ACR CFG register.
3453 * Check and clear the ACR CFG register.
3454 */
3455 intel_pmu_config_acr(hwc->idx, 0, 0);
3456 return;
3457 }
3458
3459 intel_pmu_config_acr(hwc->idx, hwc->config1, -hwc->sample_period);
3460 }
3461
3462 DEFINE_STATIC_CALL_NULL(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
3463
intel_pmu_enable_event_ext(struct perf_event * event)3464 static void intel_pmu_enable_event_ext(struct perf_event *event)
3465 {
3466 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3467 struct hw_perf_event *hwc = &event->hw;
3468 u64 ext = 0;
3469
3470 if (is_acr_event_group(event))
3471 ext |= (-hwc->sample_period) & ARCH_PEBS_RELOAD;
3472
3473 if (event->attr.precise_ip) {
3474 u64 pebs_data_cfg = intel_get_arch_pebs_data_config(event);
3475 struct arch_pebs_cap cap = hybrid(cpuc->pmu, arch_pebs_cap);
3476 union arch_pebs_index old, new;
3477
3478 ext |= ARCH_PEBS_EN;
3479 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD)
3480 ext |= (-hwc->sample_period) & ARCH_PEBS_RELOAD;
3481
3482 if (pebs_data_cfg && cap.caps) {
3483 if (pebs_data_cfg & PEBS_DATACFG_MEMINFO)
3484 ext |= ARCH_PEBS_AUX & cap.caps;
3485
3486 if (pebs_data_cfg & PEBS_DATACFG_GP)
3487 ext |= ARCH_PEBS_GPR & cap.caps;
3488
3489 if (pebs_data_cfg & PEBS_DATACFG_XMMS)
3490 ext |= ARCH_PEBS_VECR_XMM & cap.caps;
3491
3492 if (pebs_data_cfg & PEBS_DATACFG_LBRS)
3493 ext |= ARCH_PEBS_LBR & cap.caps;
3494
3495 if (pebs_data_cfg &
3496 (PEBS_DATACFG_CNTR_MASK << PEBS_DATACFG_CNTR_SHIFT))
3497 ext |= ARCH_PEBS_CNTR_GP & cap.caps;
3498
3499 if (pebs_data_cfg &
3500 (PEBS_DATACFG_FIX_MASK << PEBS_DATACFG_FIX_SHIFT))
3501 ext |= ARCH_PEBS_CNTR_FIXED & cap.caps;
3502
3503 if (pebs_data_cfg & PEBS_DATACFG_METRICS)
3504 ext |= ARCH_PEBS_CNTR_METRICS & cap.caps;
3505 }
3506
3507 if (cpuc->n_pebs == cpuc->n_large_pebs)
3508 new.thresh = ARCH_PEBS_THRESH_MULTI;
3509 else
3510 new.thresh = ARCH_PEBS_THRESH_SINGLE;
3511
3512 rdmsrq(MSR_IA32_PEBS_INDEX, old.whole);
3513 if (new.thresh != old.thresh || !old.en) {
3514 if (old.thresh == ARCH_PEBS_THRESH_MULTI && old.wr > 0) {
3515 /*
3516 * Large PEBS was enabled.
3517 * Drain PEBS buffer before applying the single PEBS.
3518 */
3519 intel_pmu_drain_pebs_buffer();
3520 } else {
3521 new.wr = 0;
3522 new.full = 0;
3523 new.en = 1;
3524 wrmsrq(MSR_IA32_PEBS_INDEX, new.whole);
3525 }
3526 }
3527 }
3528
3529 if (is_pebs_counter_event_group(event))
3530 ext |= ARCH_PEBS_CNTR_ALLOW;
3531
3532 if (cpuc->cfg_c_val[hwc->idx] != ext)
3533 __intel_pmu_update_event_ext(hwc->idx, ext);
3534 }
3535
intel_pmu_update_rdpmc_user_disable(struct perf_event * event)3536 static void intel_pmu_update_rdpmc_user_disable(struct perf_event *event)
3537 {
3538 if (!x86_pmu_has_rdpmc_user_disable(event->pmu))
3539 return;
3540
3541 /*
3542 * Counter scope's user-space rdpmc is disabled by default
3543 * except two cases.
3544 * a. rdpmc = 2 (user space rdpmc enabled unconditionally)
3545 * b. rdpmc = 1 and the event is not a system-wide event.
3546 * The count of non-system-wide events would be cleared when
3547 * context switches, so no count data is leaked.
3548 */
3549 if (x86_pmu.attr_rdpmc == X86_USER_RDPMC_ALWAYS_ENABLE ||
3550 (x86_pmu.attr_rdpmc == X86_USER_RDPMC_CONDITIONAL_ENABLE &&
3551 (event->attach_state & PERF_ATTACH_TASK)))
3552 event->hw.config &= ~ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE;
3553 else
3554 event->hw.config |= ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE;
3555 }
3556
3557 DEFINE_STATIC_CALL_NULL(intel_pmu_enable_event_ext, intel_pmu_enable_event_ext);
3558
intel_pmu_enable_event(struct perf_event * event)3559 static void intel_pmu_enable_event(struct perf_event *event)
3560 {
3561 u64 enable_mask = ARCH_PERFMON_EVENTSEL_ENABLE;
3562 struct hw_perf_event *hwc = &event->hw;
3563 int idx = hwc->idx;
3564
3565 if (unlikely(event->attr.precise_ip))
3566 static_call(x86_pmu_pebs_enable)(event);
3567
3568 switch (idx) {
3569 case 0 ... INTEL_PMC_IDX_FIXED - 1:
3570 if (branch_sample_counters(event))
3571 enable_mask |= ARCH_PERFMON_EVENTSEL_BR_CNTR;
3572 intel_set_masks(event, idx);
3573 static_call_cond(intel_pmu_enable_acr_event)(event);
3574 static_call_cond(intel_pmu_enable_event_ext)(event);
3575 /*
3576 * For self-reloaded ACR event, don't enable PMI since
3577 * HW won't set overflow bit in GLOBAL_STATUS. Otherwise,
3578 * the PMI would be recognized as a suspicious NMI.
3579 */
3580 if (is_acr_self_reload_event(event))
3581 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
3582 else if (!event->attr.precise_ip)
3583 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
3584 __x86_pmu_enable_event(hwc, enable_mask);
3585 break;
3586 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
3587 static_call_cond(intel_pmu_enable_acr_event)(event);
3588 static_call_cond(intel_pmu_enable_event_ext)(event);
3589 fallthrough;
3590 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
3591 intel_pmu_enable_fixed(event);
3592 break;
3593 case INTEL_PMC_IDX_FIXED_BTS:
3594 if (!__this_cpu_read(cpu_hw_events.enabled))
3595 return;
3596 intel_pmu_enable_bts(hwc->config);
3597 break;
3598 case INTEL_PMC_IDX_FIXED_VLBR:
3599 intel_set_masks(event, idx);
3600 break;
3601 default:
3602 pr_warn("Failed to enable the event with invalid index %d\n",
3603 idx);
3604 }
3605 }
3606
intel_pmu_acr_late_setup(struct cpu_hw_events * cpuc)3607 static void intel_pmu_acr_late_setup(struct cpu_hw_events *cpuc)
3608 {
3609 struct perf_event *event, *leader;
3610 int i, j, k, bit, idx;
3611
3612 /*
3613 * FIXME: ACR mask parsing relies on cpuc->event_list[] (active events only).
3614 * Disabling an ACR event causes bit-shifting errors in the acr_mask of
3615 * remaining group members. As ACR sampling requires all events to be active,
3616 * this limitation is acceptable for now. Revisit if independent event toggling
3617 * is required.
3618 */
3619 for (i = 0; i < cpuc->n_events; i++) {
3620 leader = cpuc->event_list[i];
3621 if (!is_acr_event_group(leader))
3622 continue;
3623
3624 /* Find the last event of the ACR group. */
3625 for (j = i; j < cpuc->n_events; j++) {
3626 event = cpuc->event_list[j];
3627 if (event->group_leader != leader->group_leader)
3628 break;
3629 }
3630
3631 /*
3632 * Translate the user-space ACR mask (attr.config2) into the physical
3633 * counter bitmask (hw.config1) for each ACR event in the group.
3634 * NOTE: ACR event contiguity is guaranteed by intel_pmu_hw_config().
3635 */
3636 for (k = i; k < j; k++) {
3637 event = cpuc->event_list[k];
3638 event->hw.config1 = 0;
3639 for_each_set_bit(bit, (unsigned long *)&event->attr.config2, X86_PMC_IDX_MAX) {
3640 idx = i + bit;
3641 /* Event index of ACR group must locate in [i, j). */
3642 if (idx >= j || !is_acr_event_group(cpuc->event_list[idx]))
3643 continue;
3644 __set_bit(cpuc->assign[idx], (unsigned long *)&event->hw.config1);
3645 }
3646 }
3647 i = j - 1;
3648 }
3649 }
3650
intel_pmu_late_setup(void)3651 void intel_pmu_late_setup(void)
3652 {
3653 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3654
3655 if (!cpuc->n_late_setup)
3656 return;
3657
3658 intel_pmu_pebs_late_setup(cpuc);
3659 intel_pmu_acr_late_setup(cpuc);
3660 }
3661
intel_pmu_add_event(struct perf_event * event)3662 static void intel_pmu_add_event(struct perf_event *event)
3663 {
3664 if (event->attr.precise_ip)
3665 intel_pmu_pebs_add(event);
3666 if (intel_pmu_needs_branch_stack(event))
3667 intel_pmu_lbr_add(event);
3668 if (is_pebs_counter_event_group(event) ||
3669 is_acr_event_group(event))
3670 this_cpu_ptr(&cpu_hw_events)->n_late_setup++;
3671 }
3672
3673 /*
3674 * Save and restart an expired event. Called by NMI contexts,
3675 * so it has to be careful about preempting normal event ops:
3676 */
intel_pmu_save_and_restart(struct perf_event * event)3677 int intel_pmu_save_and_restart(struct perf_event *event)
3678 {
3679 static_call(x86_pmu_update)(event);
3680 /*
3681 * For a checkpointed counter always reset back to 0. This
3682 * avoids a situation where the counter overflows, aborts the
3683 * transaction and is then set back to shortly before the
3684 * overflow, and overflows and aborts again.
3685 */
3686 if (unlikely(event_is_checkpointed(event))) {
3687 /* No race with NMIs because the counter should not be armed */
3688 wrmsrq(event->hw.event_base, 0);
3689 local64_set(&event->hw.prev_count, 0);
3690 }
3691 return static_call(x86_pmu_set_period)(event);
3692 }
3693
intel_pmu_set_period(struct perf_event * event)3694 static int intel_pmu_set_period(struct perf_event *event)
3695 {
3696 if (unlikely(is_topdown_count(event)))
3697 return static_call(intel_pmu_set_topdown_event_period)(event);
3698
3699 return x86_perf_event_set_period(event);
3700 }
3701
intel_pmu_update(struct perf_event * event)3702 static u64 intel_pmu_update(struct perf_event *event)
3703 {
3704 if (unlikely(is_topdown_count(event)))
3705 return static_call(intel_pmu_update_topdown_event)(event, NULL);
3706
3707 return x86_perf_event_update(event);
3708 }
3709
intel_pmu_reset(void)3710 static void intel_pmu_reset(void)
3711 {
3712 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
3713 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3714 unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask);
3715 unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask);
3716 unsigned long flags;
3717 int idx;
3718
3719 if (!*(u64 *)cntr_mask)
3720 return;
3721
3722 local_irq_save(flags);
3723
3724 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
3725
3726 for_each_set_bit(idx, cntr_mask, INTEL_PMC_MAX_GENERIC) {
3727 wrmsrq_safe(x86_pmu_config_addr(idx), 0ull);
3728 wrmsrq_safe(x86_pmu_event_addr(idx), 0ull);
3729 }
3730 for_each_set_bit(idx, fixed_cntr_mask, INTEL_PMC_MAX_FIXED) {
3731 wrmsrq_safe(x86_pmu_fixed_ctr_addr(idx), 0ull);
3732 }
3733
3734 if (ds)
3735 ds->bts_index = ds->bts_buffer_base;
3736
3737 /* Ack all overflows and disable fixed counters */
3738 if (x86_pmu.version >= 2) {
3739 intel_pmu_ack_status(intel_pmu_get_status());
3740 wrmsrq(MSR_CORE_PERF_GLOBAL_CTRL, 0);
3741 }
3742
3743 /* Reset LBRs and LBR freezing */
3744 if (x86_pmu.lbr_nr) {
3745 update_debugctlmsr(get_debugctlmsr() &
3746 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
3747 }
3748
3749 local_irq_restore(flags);
3750 }
3751
3752 /*
3753 * We may be running with guest PEBS events created by KVM, and the
3754 * PEBS records are logged into the guest's DS and invisible to host.
3755 *
3756 * In the case of guest PEBS overflow, we only trigger a fake event
3757 * to emulate the PEBS overflow PMI for guest PEBS counters in KVM.
3758 * The guest will then vm-entry and check the guest DS area to read
3759 * the guest PEBS records.
3760 *
3761 * The contents and other behavior of the guest event do not matter.
3762 */
x86_pmu_handle_guest_pebs(struct pt_regs * regs,struct perf_sample_data * data)3763 static void x86_pmu_handle_guest_pebs(struct pt_regs *regs,
3764 struct perf_sample_data *data)
3765 {
3766 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3767 u64 guest_pebs_idxs = cpuc->pebs_enabled & ~cpuc->intel_ctrl_host_mask;
3768 struct perf_event *event = NULL;
3769 int bit;
3770
3771 if (!unlikely(perf_guest_state()))
3772 return;
3773
3774 if (!x86_pmu.pebs_ept || !x86_pmu.pebs_active ||
3775 !guest_pebs_idxs)
3776 return;
3777
3778 for_each_set_bit(bit, (unsigned long *)&guest_pebs_idxs, X86_PMC_IDX_MAX) {
3779 event = cpuc->events[bit];
3780 if (!event->attr.precise_ip)
3781 continue;
3782
3783 perf_sample_data_init(data, 0, event->hw.last_period);
3784 perf_event_overflow(event, data, regs);
3785
3786 /* Inject one fake event is enough. */
3787 break;
3788 }
3789 }
3790
handle_pmi_common(struct pt_regs * regs,u64 status)3791 static int handle_pmi_common(struct pt_regs *regs, u64 status)
3792 {
3793 struct perf_sample_data data;
3794 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3795 int bit;
3796 int handled = 0;
3797
3798 inc_perf_irq_stat();
3799
3800 /*
3801 * Ignore a range of extra bits in status that do not indicate
3802 * overflow by themselves.
3803 */
3804 status &= ~(GLOBAL_STATUS_COND_CHG |
3805 GLOBAL_STATUS_ASIF |
3806 GLOBAL_STATUS_LBRS_FROZEN);
3807 if (!status)
3808 return 0;
3809 /*
3810 * In case multiple PEBS events are sampled at the same time,
3811 * it is possible to have GLOBAL_STATUS bit 62 set indicating
3812 * PEBS buffer overflow and also seeing at most 3 PEBS counters
3813 * having their bits set in the status register. This is a sign
3814 * that there was at least one PEBS record pending at the time
3815 * of the PMU interrupt. PEBS counters must only be processed
3816 * via the drain_pebs() calls and not via the regular sample
3817 * processing loop coming after that the function, otherwise
3818 * phony regular samples may be generated in the sampling buffer
3819 * not marked with the EXACT tag. Another possibility is to have
3820 * one PEBS event and at least one non-PEBS event which overflows
3821 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
3822 * not be set, yet the overflow status bit for the PEBS counter will
3823 * be on Skylake.
3824 *
3825 * To avoid this problem, we systematically ignore the PEBS-enabled
3826 * counters from the GLOBAL_STATUS mask and we always process PEBS
3827 * events via drain_pebs().
3828 */
3829 status &= ~(cpuc->pebs_enabled & x86_pmu.pebs_capable);
3830
3831 /*
3832 * PEBS overflow sets bit 62 in the global status register
3833 */
3834 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {
3835 u64 pebs_enabled = cpuc->pebs_enabled;
3836
3837 handled++;
3838 x86_pmu_handle_guest_pebs(regs, &data);
3839 static_call(x86_pmu_drain_pebs)(regs, &data);
3840
3841 /*
3842 * PMI throttle may be triggered, which stops the PEBS event.
3843 * Although cpuc->pebs_enabled is updated accordingly, the
3844 * MSR_IA32_PEBS_ENABLE is not updated. Because the
3845 * cpuc->enabled has been forced to 0 in PMI.
3846 * Update the MSR if pebs_enabled is changed.
3847 */
3848 if (pebs_enabled != cpuc->pebs_enabled)
3849 wrmsrq(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
3850
3851 /*
3852 * Above PEBS handler (PEBS counters snapshotting) has updated fixed
3853 * counter 3 and perf metrics counts if they are in counter group,
3854 * unnecessary to update again.
3855 */
3856 if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] &&
3857 is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS]))
3858 status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT;
3859 }
3860
3861 /*
3862 * Arch PEBS sets bit 54 in the global status register
3863 */
3864 if (__test_and_clear_bit(GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT,
3865 (unsigned long *)&status)) {
3866 handled++;
3867 static_call(x86_pmu_drain_pebs)(regs, &data);
3868
3869 if (cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS] &&
3870 is_pebs_counter_event_group(cpuc->events[INTEL_PMC_IDX_FIXED_SLOTS]))
3871 status &= ~GLOBAL_STATUS_PERF_METRICS_OVF_BIT;
3872 }
3873
3874 /*
3875 * Intel PT
3876 */
3877 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {
3878 handled++;
3879 if (!perf_guest_handle_intel_pt_intr())
3880 intel_pt_interrupt();
3881 }
3882
3883 /*
3884 * Intel Perf metrics
3885 */
3886 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) {
3887 handled++;
3888 static_call(intel_pmu_update_topdown_event)(NULL, NULL);
3889 }
3890
3891 status &= hybrid(cpuc->pmu, intel_ctrl);
3892
3893 /*
3894 * Checkpointed counters can lead to 'spurious' PMIs because the
3895 * rollback caused by the PMI will have cleared the overflow status
3896 * bit. Therefore always force probe these counters.
3897 */
3898 status |= cpuc->intel_cp_status;
3899
3900 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
3901 struct perf_event *event = cpuc->events[bit];
3902 u64 last_period;
3903
3904 handled++;
3905
3906 if (!test_bit(bit, cpuc->active_mask))
3907 continue;
3908 /* Event may have already been cleared: */
3909 if (!event)
3910 continue;
3911
3912 /*
3913 * There may be unprocessed PEBS records in the PEBS buffer,
3914 * which still stores the previous values.
3915 * Process those records first before handling the latest value.
3916 * For example,
3917 * A is a regular counter
3918 * B is a PEBS event which reads A
3919 * C is a PEBS event
3920 *
3921 * The following can happen:
3922 * B-assist A=1
3923 * C A=2
3924 * B-assist A=3
3925 * A-overflow-PMI A=4
3926 * C-assist-PMI (PEBS buffer) A=5
3927 *
3928 * The PEBS buffer has to be drained before handling the A-PMI
3929 */
3930 if (is_pebs_counter_event_group(event))
3931 static_call(x86_pmu_drain_pebs)(regs, &data);
3932
3933 last_period = event->hw.last_period;
3934
3935 if (!intel_pmu_save_and_restart(event))
3936 continue;
3937
3938 perf_sample_data_init(&data, 0, last_period);
3939
3940 if (has_branch_stack(event))
3941 intel_pmu_lbr_save_brstack(&data, cpuc, event);
3942
3943 perf_event_overflow(event, &data, regs);
3944 }
3945
3946 return handled;
3947 }
3948
3949 /*
3950 * This handler is triggered by the local APIC, so the APIC IRQ handling
3951 * rules apply:
3952 */
intel_pmu_handle_irq(struct pt_regs * regs)3953 static int intel_pmu_handle_irq(struct pt_regs *regs)
3954 {
3955 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3956 bool late_ack = hybrid_bit(cpuc->pmu, late_ack);
3957 bool mid_ack = hybrid_bit(cpuc->pmu, mid_ack);
3958 int loops;
3959 u64 status;
3960 int handled;
3961 int pmu_enabled;
3962
3963 /*
3964 * Save the PMU state.
3965 * It needs to be restored when leaving the handler.
3966 */
3967 pmu_enabled = cpuc->enabled;
3968 /*
3969 * In general, the early ACK is only applied for old platforms.
3970 * For the big core starts from Haswell, the late ACK should be
3971 * applied.
3972 * For the small core after Tremont, we have to do the ACK right
3973 * before re-enabling counters, which is in the middle of the
3974 * NMI handler.
3975 */
3976 if (!late_ack && !mid_ack)
3977 apic_write(APIC_LVTPC, APIC_DM_NMI);
3978 intel_bts_disable_local();
3979 cpuc->enabled = 0;
3980 __intel_pmu_disable_all(true);
3981 handled = intel_pmu_drain_bts_buffer();
3982 handled += intel_bts_interrupt();
3983 status = intel_pmu_get_status();
3984 if (!status)
3985 goto done;
3986
3987 loops = 0;
3988 again:
3989 intel_pmu_lbr_read();
3990 intel_pmu_ack_status(status);
3991 if (++loops > 100) {
3992 static bool warned;
3993
3994 if (!warned) {
3995 WARN(1, "perfevents: irq loop stuck!\n");
3996 perf_event_print_debug();
3997 warned = true;
3998 }
3999 intel_pmu_reset();
4000 goto done;
4001 }
4002
4003 handled += handle_pmi_common(regs, status);
4004
4005 /*
4006 * Repeat if there is more work to be done:
4007 */
4008 status = intel_pmu_get_status();
4009 if (status)
4010 goto again;
4011
4012 done:
4013 if (mid_ack)
4014 apic_write(APIC_LVTPC, APIC_DM_NMI);
4015 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
4016 cpuc->enabled = pmu_enabled;
4017 if (pmu_enabled)
4018 __intel_pmu_enable_all(0, true);
4019 intel_bts_enable_local();
4020
4021 /*
4022 * Only unmask the NMI after the overflow counters
4023 * have been reset. This avoids spurious NMIs on
4024 * Haswell CPUs.
4025 */
4026 if (late_ack)
4027 apic_write(APIC_LVTPC, APIC_DM_NMI);
4028 return handled;
4029 }
4030
4031 static struct event_constraint *
intel_bts_constraints(struct perf_event * event)4032 intel_bts_constraints(struct perf_event *event)
4033 {
4034 if (unlikely(intel_pmu_has_bts(event)))
4035 return &bts_constraint;
4036
4037 return NULL;
4038 }
4039
4040 /*
4041 * Note: matches a fake event, like Fixed2.
4042 */
4043 static struct event_constraint *
intel_vlbr_constraints(struct perf_event * event)4044 intel_vlbr_constraints(struct perf_event *event)
4045 {
4046 struct event_constraint *c = &vlbr_constraint;
4047
4048 if (unlikely(constraint_match(c, event->hw.config))) {
4049 event->hw.flags |= c->flags;
4050 return c;
4051 }
4052
4053 return NULL;
4054 }
4055
intel_alt_er(struct cpu_hw_events * cpuc,int idx,u64 config)4056 static int intel_alt_er(struct cpu_hw_events *cpuc,
4057 int idx, u64 config)
4058 {
4059 struct extra_reg *extra_regs = hybrid(cpuc->pmu, extra_regs);
4060 int alt_idx = idx;
4061
4062 switch (idx) {
4063 case EXTRA_REG_RSP_0 ... EXTRA_REG_RSP_1:
4064 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
4065 return idx;
4066 if (++alt_idx > EXTRA_REG_RSP_1)
4067 alt_idx = EXTRA_REG_RSP_0;
4068 if (config & ~extra_regs[alt_idx].valid_mask)
4069 return idx;
4070 break;
4071
4072 case EXTRA_REG_OMR_0 ... EXTRA_REG_OMR_3:
4073 if (!(x86_pmu.flags & PMU_FL_HAS_OMR))
4074 return idx;
4075 if (++alt_idx > EXTRA_REG_OMR_3)
4076 alt_idx = EXTRA_REG_OMR_0;
4077 /*
4078 * Subtracting EXTRA_REG_OMR_0 ensures to get correct
4079 * OMR extra_reg entries which start from 0.
4080 */
4081 if (config & ~extra_regs[alt_idx - EXTRA_REG_OMR_0].valid_mask)
4082 return idx;
4083 break;
4084
4085 default:
4086 break;
4087 }
4088
4089 return alt_idx;
4090 }
4091
intel_fixup_er(struct perf_event * event,int idx)4092 static void intel_fixup_er(struct perf_event *event, int idx)
4093 {
4094 struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs);
4095 int er_idx;
4096
4097 event->hw.extra_reg.idx = idx;
4098 switch (idx) {
4099 case EXTRA_REG_RSP_0 ... EXTRA_REG_RSP_1:
4100 er_idx = idx - EXTRA_REG_RSP_0;
4101 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
4102 event->hw.config |= extra_regs[er_idx].event;
4103 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0 + er_idx;
4104 break;
4105
4106 case EXTRA_REG_OMR_0 ... EXTRA_REG_OMR_3:
4107 er_idx = idx - EXTRA_REG_OMR_0;
4108 event->hw.config &= ~ARCH_PERFMON_EVENTSEL_UMASK;
4109 event->hw.config |= 1ULL << (8 + er_idx);
4110 event->hw.extra_reg.reg = MSR_OMR_0 + er_idx;
4111 break;
4112
4113 default:
4114 pr_warn("The extra reg idx %d is not supported.\n", idx);
4115 }
4116 }
4117
4118 /*
4119 * manage allocation of shared extra msr for certain events
4120 *
4121 * sharing can be:
4122 * per-cpu: to be shared between the various events on a single PMU
4123 * per-core: per-cpu + shared by HT threads
4124 */
4125 static struct event_constraint *
__intel_shared_reg_get_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,struct hw_perf_event_extra * reg)4126 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
4127 struct perf_event *event,
4128 struct hw_perf_event_extra *reg)
4129 {
4130 struct event_constraint *c = &emptyconstraint;
4131 struct er_account *era;
4132 unsigned long flags;
4133 int idx = reg->idx;
4134
4135 /*
4136 * reg->alloc can be set due to existing state, so for fake cpuc we
4137 * need to ignore this, otherwise we might fail to allocate proper fake
4138 * state for this extra reg constraint. Also see the comment below.
4139 */
4140 if (reg->alloc && !cpuc->is_fake)
4141 return NULL; /* call x86_get_event_constraint() */
4142
4143 again:
4144 era = &cpuc->shared_regs->regs[idx];
4145 /*
4146 * we use spin_lock_irqsave() to avoid lockdep issues when
4147 * passing a fake cpuc
4148 */
4149 raw_spin_lock_irqsave(&era->lock, flags);
4150
4151 if (!atomic_read(&era->ref) || era->config == reg->config) {
4152
4153 /*
4154 * If its a fake cpuc -- as per validate_{group,event}() we
4155 * shouldn't touch event state and we can avoid doing so
4156 * since both will only call get_event_constraints() once
4157 * on each event, this avoids the need for reg->alloc.
4158 *
4159 * Not doing the ER fixup will only result in era->reg being
4160 * wrong, but since we won't actually try and program hardware
4161 * this isn't a problem either.
4162 */
4163 if (!cpuc->is_fake) {
4164 if (idx != reg->idx)
4165 intel_fixup_er(event, idx);
4166
4167 /*
4168 * x86_schedule_events() can call get_event_constraints()
4169 * multiple times on events in the case of incremental
4170 * scheduling(). reg->alloc ensures we only do the ER
4171 * allocation once.
4172 */
4173 reg->alloc = 1;
4174 }
4175
4176 /* lock in msr value */
4177 era->config = reg->config;
4178 era->reg = reg->reg;
4179
4180 /* one more user */
4181 atomic_inc(&era->ref);
4182
4183 /*
4184 * need to call x86_get_event_constraint()
4185 * to check if associated event has constraints
4186 */
4187 c = NULL;
4188 } else {
4189 idx = intel_alt_er(cpuc, idx, reg->config);
4190 if (idx != reg->idx) {
4191 raw_spin_unlock_irqrestore(&era->lock, flags);
4192 goto again;
4193 }
4194 }
4195 raw_spin_unlock_irqrestore(&era->lock, flags);
4196
4197 return c;
4198 }
4199
4200 static void
__intel_shared_reg_put_constraints(struct cpu_hw_events * cpuc,struct hw_perf_event_extra * reg)4201 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
4202 struct hw_perf_event_extra *reg)
4203 {
4204 struct er_account *era;
4205
4206 /*
4207 * Only put constraint if extra reg was actually allocated. Also takes
4208 * care of event which do not use an extra shared reg.
4209 *
4210 * Also, if this is a fake cpuc we shouldn't touch any event state
4211 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
4212 * either since it'll be thrown out.
4213 */
4214 if (!reg->alloc || cpuc->is_fake)
4215 return;
4216
4217 era = &cpuc->shared_regs->regs[reg->idx];
4218
4219 /* one fewer user */
4220 atomic_dec(&era->ref);
4221
4222 /* allocate again next time */
4223 reg->alloc = 0;
4224 }
4225
4226 static struct event_constraint *
intel_shared_regs_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)4227 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
4228 struct perf_event *event)
4229 {
4230 struct event_constraint *c = NULL, *d;
4231 struct hw_perf_event_extra *xreg, *breg;
4232
4233 xreg = &event->hw.extra_reg;
4234 if (xreg->idx != EXTRA_REG_NONE) {
4235 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
4236 if (c == &emptyconstraint)
4237 return c;
4238 }
4239 breg = &event->hw.branch_reg;
4240 if (breg->idx != EXTRA_REG_NONE) {
4241 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
4242 if (d == &emptyconstraint) {
4243 __intel_shared_reg_put_constraints(cpuc, xreg);
4244 c = d;
4245 }
4246 }
4247 return c;
4248 }
4249
4250 struct event_constraint *
x86_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4251 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4252 struct perf_event *event)
4253 {
4254 struct event_constraint *event_constraints = hybrid(cpuc->pmu, event_constraints);
4255 struct event_constraint *c;
4256
4257 if (event_constraints) {
4258 for_each_event_constraint(c, event_constraints) {
4259 if (constraint_match(c, event->hw.config)) {
4260 event->hw.flags |= c->flags;
4261 return c;
4262 }
4263 }
4264 }
4265
4266 return &hybrid_var(cpuc->pmu, unconstrained);
4267 }
4268
4269 static struct event_constraint *
__intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4270 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4271 struct perf_event *event)
4272 {
4273 struct event_constraint *c;
4274
4275 c = intel_vlbr_constraints(event);
4276 if (c)
4277 return c;
4278
4279 c = intel_bts_constraints(event);
4280 if (c)
4281 return c;
4282
4283 c = intel_shared_regs_constraints(cpuc, event);
4284 if (c)
4285 return c;
4286
4287 c = intel_pebs_constraints(event);
4288 if (c)
4289 return c;
4290
4291 return x86_get_event_constraints(cpuc, idx, event);
4292 }
4293
4294 static void
intel_start_scheduling(struct cpu_hw_events * cpuc)4295 intel_start_scheduling(struct cpu_hw_events *cpuc)
4296 {
4297 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
4298 struct intel_excl_states *xl;
4299 int tid = cpuc->excl_thread_id;
4300
4301 /*
4302 * nothing needed if in group validation mode
4303 */
4304 if (cpuc->is_fake || !is_ht_workaround_enabled())
4305 return;
4306
4307 /*
4308 * no exclusion needed
4309 */
4310 if (WARN_ON_ONCE(!excl_cntrs))
4311 return;
4312
4313 xl = &excl_cntrs->states[tid];
4314
4315 xl->sched_started = true;
4316 /*
4317 * lock shared state until we are done scheduling
4318 * in stop_event_scheduling()
4319 * makes scheduling appear as a transaction
4320 */
4321 raw_spin_lock(&excl_cntrs->lock);
4322 }
4323
intel_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)4324 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
4325 {
4326 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
4327 struct event_constraint *c = cpuc->event_constraint[idx];
4328 struct intel_excl_states *xl;
4329 int tid = cpuc->excl_thread_id;
4330
4331 if (cpuc->is_fake || !is_ht_workaround_enabled())
4332 return;
4333
4334 if (WARN_ON_ONCE(!excl_cntrs))
4335 return;
4336
4337 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
4338 return;
4339
4340 xl = &excl_cntrs->states[tid];
4341
4342 lockdep_assert_held(&excl_cntrs->lock);
4343
4344 if (c->flags & PERF_X86_EVENT_EXCL)
4345 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
4346 else
4347 xl->state[cntr] = INTEL_EXCL_SHARED;
4348 }
4349
4350 static void
intel_stop_scheduling(struct cpu_hw_events * cpuc)4351 intel_stop_scheduling(struct cpu_hw_events *cpuc)
4352 {
4353 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
4354 struct intel_excl_states *xl;
4355 int tid = cpuc->excl_thread_id;
4356
4357 /*
4358 * nothing needed if in group validation mode
4359 */
4360 if (cpuc->is_fake || !is_ht_workaround_enabled())
4361 return;
4362 /*
4363 * no exclusion needed
4364 */
4365 if (WARN_ON_ONCE(!excl_cntrs))
4366 return;
4367
4368 xl = &excl_cntrs->states[tid];
4369
4370 xl->sched_started = false;
4371 /*
4372 * release shared state lock (acquired in intel_start_scheduling())
4373 */
4374 raw_spin_unlock(&excl_cntrs->lock);
4375 }
4376
4377 static struct event_constraint *
dyn_constraint(struct cpu_hw_events * cpuc,struct event_constraint * c,int idx)4378 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
4379 {
4380 WARN_ON_ONCE(!cpuc->constraint_list);
4381
4382 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
4383 struct event_constraint *cx;
4384
4385 /*
4386 * grab pre-allocated constraint entry
4387 */
4388 cx = &cpuc->constraint_list[idx];
4389
4390 /*
4391 * initialize dynamic constraint
4392 * with static constraint
4393 */
4394 *cx = *c;
4395
4396 /*
4397 * mark constraint as dynamic
4398 */
4399 cx->flags |= PERF_X86_EVENT_DYNAMIC;
4400 c = cx;
4401 }
4402
4403 return c;
4404 }
4405
4406 static struct event_constraint *
intel_get_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,int idx,struct event_constraint * c)4407 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
4408 int idx, struct event_constraint *c)
4409 {
4410 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
4411 struct intel_excl_states *xlo;
4412 int tid = cpuc->excl_thread_id;
4413 int is_excl, i, w;
4414
4415 /*
4416 * validating a group does not require
4417 * enforcing cross-thread exclusion
4418 */
4419 if (cpuc->is_fake || !is_ht_workaround_enabled())
4420 return c;
4421
4422 /*
4423 * no exclusion needed
4424 */
4425 if (WARN_ON_ONCE(!excl_cntrs))
4426 return c;
4427
4428 /*
4429 * because we modify the constraint, we need
4430 * to make a copy. Static constraints come
4431 * from static const tables.
4432 *
4433 * only needed when constraint has not yet
4434 * been cloned (marked dynamic)
4435 */
4436 c = dyn_constraint(cpuc, c, idx);
4437
4438 /*
4439 * From here on, the constraint is dynamic.
4440 * Either it was just allocated above, or it
4441 * was allocated during a earlier invocation
4442 * of this function
4443 */
4444
4445 /*
4446 * state of sibling HT
4447 */
4448 xlo = &excl_cntrs->states[tid ^ 1];
4449
4450 /*
4451 * event requires exclusive counter access
4452 * across HT threads
4453 */
4454 is_excl = c->flags & PERF_X86_EVENT_EXCL;
4455 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
4456 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
4457 if (!cpuc->n_excl++)
4458 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
4459 }
4460
4461 /*
4462 * Modify static constraint with current dynamic
4463 * state of thread
4464 *
4465 * EXCLUSIVE: sibling counter measuring exclusive event
4466 * SHARED : sibling counter measuring non-exclusive event
4467 * UNUSED : sibling counter unused
4468 */
4469 w = c->weight;
4470 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
4471 /*
4472 * exclusive event in sibling counter
4473 * our corresponding counter cannot be used
4474 * regardless of our event
4475 */
4476 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
4477 __clear_bit(i, c->idxmsk);
4478 w--;
4479 continue;
4480 }
4481 /*
4482 * if measuring an exclusive event, sibling
4483 * measuring non-exclusive, then counter cannot
4484 * be used
4485 */
4486 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
4487 __clear_bit(i, c->idxmsk);
4488 w--;
4489 continue;
4490 }
4491 }
4492
4493 /*
4494 * if we return an empty mask, then switch
4495 * back to static empty constraint to avoid
4496 * the cost of freeing later on
4497 */
4498 if (!w)
4499 c = &emptyconstraint;
4500
4501 c->weight = w;
4502
4503 return c;
4504 }
4505
4506 static struct event_constraint *
intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)4507 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
4508 struct perf_event *event)
4509 {
4510 struct event_constraint *c1, *c2;
4511
4512 c1 = cpuc->event_constraint[idx];
4513
4514 /*
4515 * first time only
4516 * - static constraint: no change across incremental scheduling calls
4517 * - dynamic constraint: handled by intel_get_excl_constraints()
4518 */
4519 c2 = __intel_get_event_constraints(cpuc, idx, event);
4520 if (c1) {
4521 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
4522 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
4523 c1->weight = c2->weight;
4524 c2 = c1;
4525 }
4526
4527 if (cpuc->excl_cntrs)
4528 return intel_get_excl_constraints(cpuc, event, idx, c2);
4529
4530 if (event->hw.dyn_constraint != ~0ULL) {
4531 c2 = dyn_constraint(cpuc, c2, idx);
4532 c2->idxmsk64 &= event->hw.dyn_constraint;
4533 c2->weight = hweight64(c2->idxmsk64);
4534 }
4535
4536 return c2;
4537 }
4538
intel_put_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)4539 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
4540 struct perf_event *event)
4541 {
4542 struct hw_perf_event *hwc = &event->hw;
4543 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
4544 int tid = cpuc->excl_thread_id;
4545 struct intel_excl_states *xl;
4546
4547 /*
4548 * nothing needed if in group validation mode
4549 */
4550 if (cpuc->is_fake)
4551 return;
4552
4553 if (WARN_ON_ONCE(!excl_cntrs))
4554 return;
4555
4556 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
4557 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
4558 if (!--cpuc->n_excl)
4559 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
4560 }
4561
4562 /*
4563 * If event was actually assigned, then mark the counter state as
4564 * unused now.
4565 */
4566 if (hwc->idx >= 0) {
4567 xl = &excl_cntrs->states[tid];
4568
4569 /*
4570 * put_constraint may be called from x86_schedule_events()
4571 * which already has the lock held so here make locking
4572 * conditional.
4573 */
4574 if (!xl->sched_started)
4575 raw_spin_lock(&excl_cntrs->lock);
4576
4577 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
4578
4579 if (!xl->sched_started)
4580 raw_spin_unlock(&excl_cntrs->lock);
4581 }
4582 }
4583
4584 static void
intel_put_shared_regs_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)4585 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
4586 struct perf_event *event)
4587 {
4588 struct hw_perf_event_extra *reg;
4589
4590 reg = &event->hw.extra_reg;
4591 if (reg->idx != EXTRA_REG_NONE)
4592 __intel_shared_reg_put_constraints(cpuc, reg);
4593
4594 reg = &event->hw.branch_reg;
4595 if (reg->idx != EXTRA_REG_NONE)
4596 __intel_shared_reg_put_constraints(cpuc, reg);
4597 }
4598
intel_put_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)4599 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
4600 struct perf_event *event)
4601 {
4602 intel_put_shared_regs_event_constraints(cpuc, event);
4603
4604 /*
4605 * is PMU has exclusive counter restrictions, then
4606 * all events are subject to and must call the
4607 * put_excl_constraints() routine
4608 */
4609 if (cpuc->excl_cntrs)
4610 intel_put_excl_constraints(cpuc, event);
4611 }
4612
intel_pebs_aliases_core2(struct perf_event * event)4613 static void intel_pebs_aliases_core2(struct perf_event *event)
4614 {
4615 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
4616 /*
4617 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
4618 * (0x003c) so that we can use it with PEBS.
4619 *
4620 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
4621 * PEBS capable. However we can use INST_RETIRED.ANY_P
4622 * (0x00c0), which is a PEBS capable event, to get the same
4623 * count.
4624 *
4625 * INST_RETIRED.ANY_P counts the number of cycles that retires
4626 * CNTMASK instructions. By setting CNTMASK to a value (16)
4627 * larger than the maximum number of instructions that can be
4628 * retired per cycle (4) and then inverting the condition, we
4629 * count all cycles that retire 16 or less instructions, which
4630 * is every cycle.
4631 *
4632 * Thereby we gain a PEBS capable cycle counter.
4633 */
4634 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
4635
4636 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
4637 event->hw.config = alt_config;
4638 }
4639 }
4640
intel_pebs_aliases_snb(struct perf_event * event)4641 static void intel_pebs_aliases_snb(struct perf_event *event)
4642 {
4643 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
4644 /*
4645 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
4646 * (0x003c) so that we can use it with PEBS.
4647 *
4648 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
4649 * PEBS capable. However we can use UOPS_RETIRED.ALL
4650 * (0x01c2), which is a PEBS capable event, to get the same
4651 * count.
4652 *
4653 * UOPS_RETIRED.ALL counts the number of cycles that retires
4654 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
4655 * larger than the maximum number of micro-ops that can be
4656 * retired per cycle (4) and then inverting the condition, we
4657 * count all cycles that retire 16 or less micro-ops, which
4658 * is every cycle.
4659 *
4660 * Thereby we gain a PEBS capable cycle counter.
4661 */
4662 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
4663
4664 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
4665 event->hw.config = alt_config;
4666 }
4667 }
4668
intel_pebs_aliases_precdist(struct perf_event * event)4669 static void intel_pebs_aliases_precdist(struct perf_event *event)
4670 {
4671 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
4672 /*
4673 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
4674 * (0x003c) so that we can use it with PEBS.
4675 *
4676 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
4677 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
4678 * (0x01c0), which is a PEBS capable event, to get the same
4679 * count.
4680 *
4681 * The PREC_DIST event has special support to minimize sample
4682 * shadowing effects. One drawback is that it can be
4683 * only programmed on counter 1, but that seems like an
4684 * acceptable trade off.
4685 */
4686 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
4687
4688 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
4689 event->hw.config = alt_config;
4690 }
4691 }
4692
intel_pebs_aliases_ivb(struct perf_event * event)4693 static void intel_pebs_aliases_ivb(struct perf_event *event)
4694 {
4695 if (event->attr.precise_ip < 3)
4696 return intel_pebs_aliases_snb(event);
4697 return intel_pebs_aliases_precdist(event);
4698 }
4699
intel_pebs_aliases_skl(struct perf_event * event)4700 static void intel_pebs_aliases_skl(struct perf_event *event)
4701 {
4702 if (event->attr.precise_ip < 3)
4703 return intel_pebs_aliases_core2(event);
4704 return intel_pebs_aliases_precdist(event);
4705 }
4706
intel_pmu_large_pebs_flags(struct perf_event * event)4707 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
4708 {
4709 unsigned long flags = x86_pmu.large_pebs_flags;
4710
4711 if (event->attr.use_clockid)
4712 flags &= ~PERF_SAMPLE_TIME;
4713 if (!event->attr.exclude_kernel)
4714 flags &= ~PERF_SAMPLE_REGS_USER;
4715 if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
4716 flags &= ~PERF_SAMPLE_REGS_USER;
4717 if (event->attr.sample_regs_intr & ~PEBS_GP_REGS)
4718 flags &= ~PERF_SAMPLE_REGS_INTR;
4719 return flags;
4720 }
4721
intel_pmu_bts_config(struct perf_event * event)4722 static int intel_pmu_bts_config(struct perf_event *event)
4723 {
4724 struct perf_event_attr *attr = &event->attr;
4725
4726 if (unlikely(intel_pmu_has_bts(event))) {
4727 /* BTS is not supported by this architecture. */
4728 if (!x86_pmu.bts_active)
4729 return -EOPNOTSUPP;
4730
4731 /* BTS is currently only allowed for user-mode. */
4732 if (!attr->exclude_kernel)
4733 return -EOPNOTSUPP;
4734
4735 /* BTS is not allowed for precise events. */
4736 if (attr->precise_ip)
4737 return -EOPNOTSUPP;
4738
4739 /* disallow bts if conflicting events are present */
4740 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
4741 return -EBUSY;
4742
4743 event->destroy = hw_perf_lbr_event_destroy;
4744 }
4745
4746 return 0;
4747 }
4748
core_pmu_hw_config(struct perf_event * event)4749 static int core_pmu_hw_config(struct perf_event *event)
4750 {
4751 int ret = x86_pmu_hw_config(event);
4752
4753 if (ret)
4754 return ret;
4755
4756 return intel_pmu_bts_config(event);
4757 }
4758
4759 #define INTEL_TD_METRIC_AVAILABLE_MAX (INTEL_TD_METRIC_RETIRING + \
4760 ((x86_pmu.num_topdown_events - 1) << 8))
4761
is_available_metric_event(struct perf_event * event)4762 static bool is_available_metric_event(struct perf_event *event)
4763 {
4764 return is_metric_event(event) &&
4765 event->attr.config <= INTEL_TD_METRIC_AVAILABLE_MAX;
4766 }
4767
is_mem_loads_event(struct perf_event * event)4768 static inline bool is_mem_loads_event(struct perf_event *event)
4769 {
4770 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0xcd, .umask=0x01);
4771 }
4772
is_mem_loads_aux_event(struct perf_event * event)4773 static inline bool is_mem_loads_aux_event(struct perf_event *event)
4774 {
4775 return (event->attr.config & INTEL_ARCH_EVENT_MASK) == X86_CONFIG(.event=0x03, .umask=0x82);
4776 }
4777
require_mem_loads_aux_event(struct perf_event * event)4778 static inline bool require_mem_loads_aux_event(struct perf_event *event)
4779 {
4780 if (!(x86_pmu.flags & PMU_FL_MEM_LOADS_AUX))
4781 return false;
4782
4783 if (is_hybrid())
4784 return hybrid_pmu(event->pmu)->pmu_type == hybrid_big;
4785
4786 return true;
4787 }
4788
intel_pmu_has_cap(struct perf_event * event,int idx)4789 static inline bool intel_pmu_has_cap(struct perf_event *event, int idx)
4790 {
4791 union perf_capabilities *intel_cap = &hybrid(event->pmu, intel_cap);
4792
4793 return test_bit(idx, (unsigned long *)&intel_cap->capabilities);
4794 }
4795
intel_pmu_freq_start_period(struct perf_event * event)4796 static u64 intel_pmu_freq_start_period(struct perf_event *event)
4797 {
4798 int type = event->attr.type;
4799 u64 config, factor;
4800 s64 start;
4801
4802 /*
4803 * The 127 is the lowest possible recommended SAV (sample after value)
4804 * for a 4000 freq (default freq), according to the event list JSON file.
4805 * Also, assume the workload is idle 50% time.
4806 */
4807 factor = 64 * 4000;
4808 if (type != PERF_TYPE_HARDWARE && type != PERF_TYPE_HW_CACHE)
4809 goto end;
4810
4811 /*
4812 * The estimation of the start period in the freq mode is
4813 * based on the below assumption.
4814 *
4815 * For a cycles or an instructions event, 1GHZ of the
4816 * underlying platform, 1 IPC. The workload is idle 50% time.
4817 * The start period = 1,000,000,000 * 1 / freq / 2.
4818 * = 500,000,000 / freq
4819 *
4820 * Usually, the branch-related events occur less than the
4821 * instructions event. According to the Intel event list JSON
4822 * file, the SAV (sample after value) of a branch-related event
4823 * is usually 1/4 of an instruction event.
4824 * The start period of branch-related events = 125,000,000 / freq.
4825 *
4826 * The cache-related events occurs even less. The SAV is usually
4827 * 1/20 of an instruction event.
4828 * The start period of cache-related events = 25,000,000 / freq.
4829 */
4830 config = event->attr.config & PERF_HW_EVENT_MASK;
4831 if (type == PERF_TYPE_HARDWARE) {
4832 switch (config) {
4833 case PERF_COUNT_HW_CPU_CYCLES:
4834 case PERF_COUNT_HW_INSTRUCTIONS:
4835 case PERF_COUNT_HW_BUS_CYCLES:
4836 case PERF_COUNT_HW_STALLED_CYCLES_FRONTEND:
4837 case PERF_COUNT_HW_STALLED_CYCLES_BACKEND:
4838 case PERF_COUNT_HW_REF_CPU_CYCLES:
4839 factor = 500000000;
4840 break;
4841 case PERF_COUNT_HW_BRANCH_INSTRUCTIONS:
4842 case PERF_COUNT_HW_BRANCH_MISSES:
4843 factor = 125000000;
4844 break;
4845 case PERF_COUNT_HW_CACHE_REFERENCES:
4846 case PERF_COUNT_HW_CACHE_MISSES:
4847 factor = 25000000;
4848 break;
4849 default:
4850 goto end;
4851 }
4852 }
4853
4854 if (type == PERF_TYPE_HW_CACHE)
4855 factor = 25000000;
4856 end:
4857 /*
4858 * Usually, a prime or a number with less factors (close to prime)
4859 * is chosen as an SAV, which makes it less likely that the sampling
4860 * period synchronizes with some periodic event in the workload.
4861 * Minus 1 to make it at least avoiding values near power of twos
4862 * for the default freq.
4863 */
4864 start = DIV_ROUND_UP_ULL(factor, event->attr.sample_freq) - 1;
4865
4866 if (start > x86_pmu.max_period)
4867 start = x86_pmu.max_period;
4868
4869 if (x86_pmu.limit_period)
4870 x86_pmu.limit_period(event, &start);
4871
4872 return start;
4873 }
4874
intel_pmu_has_acr(struct pmu * pmu)4875 static inline bool intel_pmu_has_acr(struct pmu *pmu)
4876 {
4877 return !!hybrid(pmu, acr_cause_mask64);
4878 }
4879
intel_pmu_is_acr_group(struct perf_event * event)4880 static bool intel_pmu_is_acr_group(struct perf_event *event)
4881 {
4882 /* The group leader has the ACR flag set */
4883 if (is_acr_event_group(event))
4884 return true;
4885
4886 /* The acr_mask is set */
4887 if (event->attr.config2)
4888 return true;
4889
4890 return false;
4891 }
4892
intel_pmu_has_pebs_counter_group(struct pmu * pmu)4893 static inline bool intel_pmu_has_pebs_counter_group(struct pmu *pmu)
4894 {
4895 u64 caps;
4896
4897 if (x86_pmu.intel_cap.pebs_format >= 6 && x86_pmu.intel_cap.pebs_baseline)
4898 return true;
4899
4900 caps = hybrid(pmu, arch_pebs_cap).caps;
4901 if (x86_pmu.arch_pebs && (caps & ARCH_PEBS_CNTR_MASK))
4902 return true;
4903
4904 return false;
4905 }
4906
intel_pmu_set_acr_cntr_constr(struct perf_event * event,u64 * cause_mask,int * num)4907 static inline void intel_pmu_set_acr_cntr_constr(struct perf_event *event,
4908 u64 *cause_mask, int *num)
4909 {
4910 event->hw.dyn_constraint &= hybrid(event->pmu, acr_cntr_mask64);
4911 *cause_mask |= event->attr.config2;
4912 *num += 1;
4913 }
4914
intel_pmu_set_acr_caused_constr(struct perf_event * event,int idx,u64 cause_mask)4915 static inline void intel_pmu_set_acr_caused_constr(struct perf_event *event,
4916 int idx, u64 cause_mask)
4917 {
4918 if (test_bit(idx, (unsigned long *)&cause_mask))
4919 event->hw.dyn_constraint &= hybrid(event->pmu, acr_cause_mask64);
4920 }
4921
intel_set_branch_counter_constr(struct perf_event * event,int * num)4922 static inline int intel_set_branch_counter_constr(struct perf_event *event,
4923 int *num)
4924 {
4925 if (branch_sample_call_stack(event))
4926 return -EINVAL;
4927 if (branch_sample_counters(event)) {
4928 (*num)++;
4929 event->hw.dyn_constraint &= x86_pmu.lbr_counters;
4930 }
4931
4932 return 0;
4933 }
4934
intel_pmu_hw_config(struct perf_event * event)4935 static int intel_pmu_hw_config(struct perf_event *event)
4936 {
4937 int ret = x86_pmu_hw_config(event);
4938
4939 if (ret)
4940 return ret;
4941
4942 ret = intel_pmu_bts_config(event);
4943 if (ret)
4944 return ret;
4945
4946 if (event->attr.freq && event->attr.sample_freq) {
4947 event->hw.sample_period = intel_pmu_freq_start_period(event);
4948 event->hw.last_period = event->hw.sample_period;
4949 local64_set(&event->hw.period_left, event->hw.sample_period);
4950 }
4951
4952 if (event->attr.precise_ip) {
4953 struct arch_pebs_cap pebs_cap = hybrid(event->pmu, arch_pebs_cap);
4954
4955 if ((event->attr.config & INTEL_ARCH_EVENT_MASK) == INTEL_FIXED_VLBR_EVENT)
4956 return -EINVAL;
4957
4958 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
4959 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
4960 if (!(event->attr.sample_type & ~intel_pmu_large_pebs_flags(event)) &&
4961 !has_aux_action(event)) {
4962 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
4963 event->attach_state |= PERF_ATTACH_SCHED_CB;
4964 }
4965 }
4966 if (x86_pmu.pebs_aliases)
4967 x86_pmu.pebs_aliases(event);
4968
4969 if (x86_pmu.arch_pebs) {
4970 u64 cntr_mask = hybrid(event->pmu, intel_ctrl) &
4971 ~GLOBAL_CTRL_EN_PERF_METRICS;
4972 u64 pebs_mask = event->attr.precise_ip >= 3 ?
4973 pebs_cap.pdists : pebs_cap.counters;
4974 if (cntr_mask != pebs_mask)
4975 event->hw.dyn_constraint &= pebs_mask;
4976 }
4977 }
4978
4979 if (needs_branch_stack(event)) {
4980 /* Avoid branch stack setup for counting events in SAMPLE READ */
4981 if (is_sampling_event(event) ||
4982 !(event->attr.sample_type & PERF_SAMPLE_READ))
4983 event->hw.flags |= PERF_X86_EVENT_NEEDS_BRANCH_STACK;
4984 }
4985
4986 if (branch_sample_counters(event)) {
4987 struct perf_event *leader, *sibling;
4988 int num = 0;
4989
4990 if (!(x86_pmu.flags & PMU_FL_BR_CNTR) ||
4991 (event->attr.config & ~INTEL_ARCH_EVENT_MASK))
4992 return -EINVAL;
4993
4994 /*
4995 * The branch counter logging is not supported in the call stack
4996 * mode yet, since we cannot simply flush the LBR during e.g.,
4997 * multiplexing. Also, there is no obvious usage with the call
4998 * stack mode. Simply forbids it for now.
4999 *
5000 * If any events in the group enable the branch counter logging
5001 * feature, the group is treated as a branch counter logging
5002 * group, which requires the extra space to store the counters.
5003 */
5004 leader = event->group_leader;
5005 if (intel_set_branch_counter_constr(leader, &num))
5006 return -EINVAL;
5007 leader->hw.flags |= PERF_X86_EVENT_BRANCH_COUNTERS;
5008
5009 for_each_sibling_event(sibling, leader) {
5010 if (intel_set_branch_counter_constr(sibling, &num))
5011 return -EINVAL;
5012 }
5013
5014 /* event isn't installed as a sibling yet. */
5015 if (event != leader) {
5016 if (intel_set_branch_counter_constr(event, &num))
5017 return -EINVAL;
5018 }
5019
5020 if (num > fls(x86_pmu.lbr_counters))
5021 return -EINVAL;
5022 /*
5023 * Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't
5024 * require any branch stack setup.
5025 * Clear the bit to avoid unnecessary branch stack setup.
5026 */
5027 if (0 == (event->attr.branch_sample_type &
5028 ~(PERF_SAMPLE_BRANCH_PLM_ALL |
5029 PERF_SAMPLE_BRANCH_COUNTERS)))
5030 event->hw.flags &= ~PERF_X86_EVENT_NEEDS_BRANCH_STACK;
5031
5032 /*
5033 * Force the leader to be a LBR event. So LBRs can be reset
5034 * with the leader event. See intel_pmu_lbr_del() for details.
5035 */
5036 if (!intel_pmu_needs_branch_stack(leader))
5037 return -EINVAL;
5038 }
5039
5040 if (intel_pmu_needs_branch_stack(event)) {
5041 ret = intel_pmu_setup_lbr_filter(event);
5042 if (ret)
5043 return ret;
5044 event->attach_state |= PERF_ATTACH_SCHED_CB;
5045
5046 /*
5047 * BTS is set up earlier in this path, so don't account twice
5048 */
5049 if (!unlikely(intel_pmu_has_bts(event))) {
5050 /* disallow lbr if conflicting events are present */
5051 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
5052 return -EBUSY;
5053
5054 event->destroy = hw_perf_lbr_event_destroy;
5055 }
5056 }
5057
5058 if (event->attr.aux_output) {
5059 if (!event->attr.precise_ip)
5060 return -EINVAL;
5061
5062 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
5063 }
5064
5065 if ((event->attr.sample_type & PERF_SAMPLE_READ) &&
5066 intel_pmu_has_pebs_counter_group(event->pmu) &&
5067 is_sampling_event(event) &&
5068 event->attr.precise_ip)
5069 event->group_leader->hw.flags |= PERF_X86_EVENT_PEBS_CNTR;
5070
5071 if (intel_pmu_has_acr(event->pmu) && intel_pmu_is_acr_group(event)) {
5072 struct perf_event *sibling, *leader = event->group_leader;
5073 struct pmu *pmu = event->pmu;
5074 bool has_sw_event = false;
5075 int num = 0, idx = 0;
5076 u64 cause_mask = 0;
5077
5078 /* Not support perf metrics */
5079 if (is_metric_event(event))
5080 return -EINVAL;
5081
5082 /* Not support freq mode */
5083 if (event->attr.freq)
5084 return -EINVAL;
5085
5086 /* PDist is not supported */
5087 if (event->attr.config2 && event->attr.precise_ip > 2)
5088 return -EINVAL;
5089
5090 /* The reload value cannot exceeds the max period */
5091 if (event->attr.sample_period > x86_pmu.max_period)
5092 return -EINVAL;
5093 /*
5094 * The counter-constraints of each event cannot be finalized
5095 * unless the whole group is scanned. However, it's hard
5096 * to know whether the event is the last one of the group.
5097 * Recalculate the counter-constraints for each event when
5098 * adding a new event.
5099 *
5100 * The group is traversed twice, which may be optimized later.
5101 * In the first round,
5102 * - Find all events which do reload when other events
5103 * overflow and set the corresponding counter-constraints
5104 * - Add all events, which can cause other events reload,
5105 * in the cause_mask
5106 * - Error out if the number of events exceeds the HW limit
5107 * - The ACR events must be contiguous.
5108 * Error out if there are non-X86 events between ACR events.
5109 * This is not a HW limit, but a SW limit.
5110 * With the assumption, the intel_pmu_acr_late_setup() can
5111 * easily convert the event idx to counter idx without
5112 * traversing the whole event list.
5113 */
5114 if (!is_x86_event(leader))
5115 return -EINVAL;
5116
5117 if (leader->attr.config2)
5118 intel_pmu_set_acr_cntr_constr(leader, &cause_mask, &num);
5119
5120 if (leader->nr_siblings) {
5121 for_each_sibling_event(sibling, leader) {
5122 if (!is_x86_event(sibling)) {
5123 has_sw_event = true;
5124 continue;
5125 }
5126 if (!sibling->attr.config2)
5127 continue;
5128 if (has_sw_event)
5129 return -EINVAL;
5130 intel_pmu_set_acr_cntr_constr(sibling, &cause_mask, &num);
5131 }
5132 }
5133 if (leader != event && event->attr.config2) {
5134 if (has_sw_event)
5135 return -EINVAL;
5136 intel_pmu_set_acr_cntr_constr(event, &cause_mask, &num);
5137 }
5138
5139 if (hweight64(cause_mask) > hweight64(hybrid(pmu, acr_cause_mask64)) ||
5140 num > hweight64(hybrid(event->pmu, acr_cntr_mask64)))
5141 return -EINVAL;
5142 /*
5143 * In the second round, apply the counter-constraints for
5144 * the events which can cause other events reload.
5145 */
5146 intel_pmu_set_acr_caused_constr(leader, idx++, cause_mask);
5147
5148 if (leader->nr_siblings) {
5149 for_each_sibling_event(sibling, leader) {
5150 if (is_x86_event(sibling))
5151 intel_pmu_set_acr_caused_constr(sibling, idx++, cause_mask);
5152 }
5153 }
5154
5155 if (leader != event)
5156 intel_pmu_set_acr_caused_constr(event, idx, cause_mask);
5157
5158 leader->hw.flags |= PERF_X86_EVENT_ACR;
5159 }
5160
5161 intel_pmu_update_rdpmc_user_disable(event);
5162
5163 if ((event->attr.type == PERF_TYPE_HARDWARE) ||
5164 (event->attr.type == PERF_TYPE_HW_CACHE))
5165 return 0;
5166
5167 /*
5168 * Config Topdown slots and metric events
5169 *
5170 * The slots event on Fixed Counter 3 can support sampling,
5171 * which will be handled normally in x86_perf_event_update().
5172 *
5173 * Metric events don't support sampling and require being paired
5174 * with a slots event as group leader. When the slots event
5175 * is used in a metrics group, it too cannot support sampling.
5176 */
5177 if (intel_pmu_has_cap(event, PERF_CAP_METRICS_IDX) && is_topdown_event(event)) {
5178 /* The metrics_clear can only be set for the slots event */
5179 if (event->attr.config1 &&
5180 (!is_slots_event(event) || (event->attr.config1 & ~INTEL_TD_CFG_METRIC_CLEAR)))
5181 return -EINVAL;
5182
5183 if (event->attr.config2)
5184 return -EINVAL;
5185
5186 /*
5187 * The TopDown metrics events and slots event don't
5188 * support any filters.
5189 */
5190 if (event->attr.config & X86_ALL_EVENT_FLAGS)
5191 return -EINVAL;
5192
5193 if (is_available_metric_event(event)) {
5194 struct perf_event *leader = event->group_leader;
5195
5196 /* The metric events don't support sampling. */
5197 if (is_sampling_event(event))
5198 return -EINVAL;
5199
5200 /* The metric events require a slots group leader. */
5201 if (!is_slots_event(leader))
5202 return -EINVAL;
5203
5204 /*
5205 * The leader/SLOTS must not be a sampling event for
5206 * metric use; hardware requires it starts at 0 when used
5207 * in conjunction with MSR_PERF_METRICS.
5208 */
5209 if (is_sampling_event(leader))
5210 return -EINVAL;
5211
5212 event->event_caps |= PERF_EV_CAP_SIBLING;
5213 /*
5214 * Only once we have a METRICs sibling do we
5215 * need TopDown magic.
5216 */
5217 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
5218 event->hw.flags |= PERF_X86_EVENT_TOPDOWN;
5219 }
5220 }
5221
5222 /*
5223 * The load latency event X86_CONFIG(.event=0xcd, .umask=0x01) on SPR
5224 * doesn't function quite right. As a work-around it needs to always be
5225 * co-scheduled with a auxiliary event X86_CONFIG(.event=0x03, .umask=0x82).
5226 * The actual count of this second event is irrelevant it just needs
5227 * to be active to make the first event function correctly.
5228 *
5229 * In a group, the auxiliary event must be in front of the load latency
5230 * event. The rule is to simplify the implementation of the check.
5231 * That's because perf cannot have a complete group at the moment.
5232 */
5233 if (require_mem_loads_aux_event(event) &&
5234 (event->attr.sample_type & PERF_SAMPLE_DATA_SRC) &&
5235 is_mem_loads_event(event)) {
5236 struct perf_event *leader = event->group_leader;
5237 struct perf_event *sibling = NULL;
5238
5239 /*
5240 * When this memload event is also the first event (no group
5241 * exists yet), then there is no aux event before it.
5242 */
5243 if (leader == event)
5244 return -ENODATA;
5245
5246 if (!is_mem_loads_aux_event(leader)) {
5247 for_each_sibling_event(sibling, leader) {
5248 if (is_mem_loads_aux_event(sibling))
5249 break;
5250 }
5251 if (list_entry_is_head(sibling, &leader->sibling_list, sibling_list))
5252 return -ENODATA;
5253 }
5254 }
5255
5256 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
5257 return 0;
5258
5259 if (x86_pmu.version < 3)
5260 return -EINVAL;
5261
5262 ret = perf_allow_cpu();
5263 if (ret)
5264 return ret;
5265
5266 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
5267
5268 return 0;
5269 }
5270
5271 /*
5272 * Currently, the only caller of this function is the atomic_switch_perf_msrs().
5273 * The host perf context helps to prepare the values of the real hardware for
5274 * a set of msrs that need to be switched atomically in a vmx transaction.
5275 *
5276 * For example, the pseudocode needed to add a new msr should look like:
5277 *
5278 * arr[(*nr)++] = (struct perf_guest_switch_msr){
5279 * .msr = the hardware msr address,
5280 * .host = the value the hardware has when it doesn't run a guest,
5281 * .guest = the value the hardware has when it runs a guest,
5282 * };
5283 *
5284 * These values have nothing to do with the emulated values the guest sees
5285 * when it uses {RD,WR}MSR, which should be handled by the KVM context,
5286 * specifically in the intel_pmu_{get,set}_msr().
5287 */
intel_guest_get_msrs(int * nr,void * data)5288 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
5289 {
5290 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
5291 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
5292 struct kvm_pmu *kvm_pmu = (struct kvm_pmu *)data;
5293 u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
5294 u64 pebs_mask = cpuc->pebs_enabled & x86_pmu.pebs_capable;
5295 int global_ctrl, pebs_enable;
5296
5297 /*
5298 * In addition to obeying exclude_guest/exclude_host, remove bits being
5299 * used for PEBS when running a guest, because PEBS writes to virtual
5300 * addresses (not physical addresses).
5301 */
5302 *nr = 0;
5303 global_ctrl = (*nr)++;
5304 arr[global_ctrl] = (struct perf_guest_switch_msr){
5305 .msr = MSR_CORE_PERF_GLOBAL_CTRL,
5306 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask,
5307 .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask,
5308 };
5309
5310 if (!x86_pmu.ds_pebs)
5311 return arr;
5312
5313 /*
5314 * If PMU counter has PEBS enabled it is not enough to
5315 * disable counter on a guest entry since PEBS memory
5316 * write can overshoot guest entry and corrupt guest
5317 * memory. Disabling PEBS solves the problem.
5318 *
5319 * Don't do this if the CPU already enforces it.
5320 */
5321 if (x86_pmu.pebs_no_isolation) {
5322 arr[(*nr)++] = (struct perf_guest_switch_msr){
5323 .msr = MSR_IA32_PEBS_ENABLE,
5324 .host = cpuc->pebs_enabled,
5325 .guest = 0,
5326 };
5327 return arr;
5328 }
5329
5330 if (!kvm_pmu || !x86_pmu.pebs_ept)
5331 return arr;
5332
5333 arr[(*nr)++] = (struct perf_guest_switch_msr){
5334 .msr = MSR_IA32_DS_AREA,
5335 .host = (unsigned long)cpuc->ds,
5336 .guest = kvm_pmu->ds_area,
5337 };
5338
5339 if (x86_pmu.intel_cap.pebs_baseline) {
5340 arr[(*nr)++] = (struct perf_guest_switch_msr){
5341 .msr = MSR_PEBS_DATA_CFG,
5342 .host = cpuc->active_pebs_data_cfg,
5343 .guest = kvm_pmu->pebs_data_cfg,
5344 };
5345 }
5346
5347 pebs_enable = (*nr)++;
5348 arr[pebs_enable] = (struct perf_guest_switch_msr){
5349 .msr = MSR_IA32_PEBS_ENABLE,
5350 .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask,
5351 .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask & kvm_pmu->pebs_enable,
5352 };
5353
5354 if (arr[pebs_enable].host) {
5355 /* Disable guest PEBS if host PEBS is enabled. */
5356 arr[pebs_enable].guest = 0;
5357 } else {
5358 /* Disable guest PEBS thoroughly for cross-mapped PEBS counters. */
5359 arr[pebs_enable].guest &= ~kvm_pmu->host_cross_mapped_mask;
5360 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask;
5361 /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */
5362 arr[global_ctrl].guest |= arr[pebs_enable].guest;
5363 }
5364
5365 return arr;
5366 }
5367
core_guest_get_msrs(int * nr,void * data)5368 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr, void *data)
5369 {
5370 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
5371 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
5372 int idx;
5373
5374 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
5375 struct perf_event *event = cpuc->events[idx];
5376
5377 arr[idx].msr = x86_pmu_config_addr(idx);
5378 arr[idx].host = arr[idx].guest = 0;
5379
5380 if (!test_bit(idx, cpuc->active_mask))
5381 continue;
5382
5383 arr[idx].host = arr[idx].guest =
5384 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
5385
5386 if (event->attr.exclude_host)
5387 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
5388 else if (event->attr.exclude_guest)
5389 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
5390 }
5391
5392 *nr = x86_pmu_max_num_counters(cpuc->pmu);
5393 return arr;
5394 }
5395
core_pmu_enable_event(struct perf_event * event)5396 static void core_pmu_enable_event(struct perf_event *event)
5397 {
5398 if (!event->attr.exclude_host)
5399 x86_pmu_enable_event(event);
5400 }
5401
core_pmu_enable_all(int added)5402 static void core_pmu_enable_all(int added)
5403 {
5404 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
5405 int idx;
5406
5407 for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) {
5408 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
5409
5410 if (!test_bit(idx, cpuc->active_mask) ||
5411 cpuc->events[idx]->attr.exclude_host)
5412 continue;
5413
5414 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
5415 }
5416 }
5417
hsw_hw_config(struct perf_event * event)5418 static int hsw_hw_config(struct perf_event *event)
5419 {
5420 int ret = intel_pmu_hw_config(event);
5421
5422 if (ret)
5423 return ret;
5424 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
5425 return 0;
5426 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
5427
5428 /*
5429 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
5430 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
5431 * this combination.
5432 */
5433 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
5434 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
5435 event->attr.precise_ip > 0))
5436 return -EOPNOTSUPP;
5437
5438 if (event_is_checkpointed(event)) {
5439 /*
5440 * Sampling of checkpointed events can cause situations where
5441 * the CPU constantly aborts because of a overflow, which is
5442 * then checkpointed back and ignored. Forbid checkpointing
5443 * for sampling.
5444 *
5445 * But still allow a long sampling period, so that perf stat
5446 * from KVM works.
5447 */
5448 if (event->attr.sample_period > 0 &&
5449 event->attr.sample_period < 0x7fffffff)
5450 return -EOPNOTSUPP;
5451 }
5452 return 0;
5453 }
5454
5455 static struct event_constraint counter0_constraint =
5456 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
5457
5458 static struct event_constraint counter1_constraint =
5459 INTEL_ALL_EVENT_CONSTRAINT(0, 0x2);
5460
5461 static struct event_constraint counter0_1_constraint =
5462 INTEL_ALL_EVENT_CONSTRAINT(0, 0x3);
5463
5464 static struct event_constraint counter2_constraint =
5465 EVENT_CONSTRAINT(0, 0x4, 0);
5466
5467 static struct event_constraint fixed0_constraint =
5468 FIXED_EVENT_CONSTRAINT(0x00c0, 0);
5469
5470 static struct event_constraint fixed0_counter0_constraint =
5471 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
5472
5473 static struct event_constraint fixed0_counter0_1_constraint =
5474 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000003ULL);
5475
5476 static struct event_constraint counters_1_7_constraint =
5477 INTEL_ALL_EVENT_CONSTRAINT(0, 0xfeULL);
5478
5479 static struct event_constraint *
hsw_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5480 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5481 struct perf_event *event)
5482 {
5483 struct event_constraint *c;
5484
5485 c = intel_get_event_constraints(cpuc, idx, event);
5486
5487 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
5488 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
5489 if (c->idxmsk64 & (1U << 2))
5490 return &counter2_constraint;
5491 return &emptyconstraint;
5492 }
5493
5494 return c;
5495 }
5496
5497 static struct event_constraint *
icl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5498 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5499 struct perf_event *event)
5500 {
5501 /*
5502 * Fixed counter 0 has less skid.
5503 * Force instruction:ppp in Fixed counter 0
5504 */
5505 if ((event->attr.precise_ip == 3) &&
5506 constraint_match(&fixed0_constraint, event->hw.config))
5507 return &fixed0_constraint;
5508
5509 return hsw_get_event_constraints(cpuc, idx, event);
5510 }
5511
5512 static struct event_constraint *
glc_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5513 glc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5514 struct perf_event *event)
5515 {
5516 struct event_constraint *c;
5517
5518 c = icl_get_event_constraints(cpuc, idx, event);
5519
5520 /*
5521 * The :ppp indicates the Precise Distribution (PDist) facility, which
5522 * is only supported on the GP counter 0. If a :ppp event which is not
5523 * available on the GP counter 0, error out.
5524 * Exception: Instruction PDIR is only available on the fixed counter 0.
5525 */
5526 if ((event->attr.precise_ip == 3) &&
5527 !constraint_match(&fixed0_constraint, event->hw.config)) {
5528 if (c->idxmsk64 & BIT_ULL(0))
5529 return &counter0_constraint;
5530
5531 return &emptyconstraint;
5532 }
5533
5534 return c;
5535 }
5536
5537 static struct event_constraint *
glp_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5538 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5539 struct perf_event *event)
5540 {
5541 struct event_constraint *c;
5542
5543 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
5544 if (event->attr.precise_ip == 3)
5545 return &counter0_constraint;
5546
5547 c = intel_get_event_constraints(cpuc, idx, event);
5548
5549 return c;
5550 }
5551
5552 static struct event_constraint *
tnt_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5553 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5554 struct perf_event *event)
5555 {
5556 struct event_constraint *c;
5557
5558 c = intel_get_event_constraints(cpuc, idx, event);
5559
5560 /*
5561 * :ppp means to do reduced skid PEBS,
5562 * which is available on PMC0 and fixed counter 0.
5563 */
5564 if (event->attr.precise_ip == 3) {
5565 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
5566 if (constraint_match(&fixed0_constraint, event->hw.config))
5567 return &fixed0_counter0_constraint;
5568
5569 return &counter0_constraint;
5570 }
5571
5572 return c;
5573 }
5574
5575 static bool allow_tsx_force_abort = true;
5576
5577 static struct event_constraint *
tfa_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5578 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5579 struct perf_event *event)
5580 {
5581 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
5582
5583 /*
5584 * Without TFA we must not use PMC3.
5585 */
5586 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
5587 c = dyn_constraint(cpuc, c, idx);
5588 c->idxmsk64 &= ~(1ULL << 3);
5589 c->weight--;
5590 }
5591
5592 return c;
5593 }
5594
5595 static struct event_constraint *
adl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5596 adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5597 struct perf_event *event)
5598 {
5599 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5600
5601 if (pmu->pmu_type == hybrid_big)
5602 return glc_get_event_constraints(cpuc, idx, event);
5603 else if (pmu->pmu_type == hybrid_small)
5604 return tnt_get_event_constraints(cpuc, idx, event);
5605
5606 WARN_ON(1);
5607 return &emptyconstraint;
5608 }
5609
5610 static struct event_constraint *
cmt_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5611 cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5612 struct perf_event *event)
5613 {
5614 struct event_constraint *c;
5615
5616 c = intel_get_event_constraints(cpuc, idx, event);
5617
5618 /*
5619 * The :ppp indicates the Precise Distribution (PDist) facility, which
5620 * is only supported on the GP counter 0 & 1 and Fixed counter 0.
5621 * If a :ppp event which is not available on the above eligible counters,
5622 * error out.
5623 */
5624 if (event->attr.precise_ip == 3) {
5625 /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */
5626 if (constraint_match(&fixed0_constraint, event->hw.config)) {
5627 /* The fixed counter 0 doesn't support LBR event logging. */
5628 if (branch_sample_counters(event))
5629 return &counter0_1_constraint;
5630 else
5631 return &fixed0_counter0_1_constraint;
5632 }
5633
5634 switch (c->idxmsk64 & 0x3ull) {
5635 case 0x1:
5636 return &counter0_constraint;
5637 case 0x2:
5638 return &counter1_constraint;
5639 case 0x3:
5640 return &counter0_1_constraint;
5641 }
5642 return &emptyconstraint;
5643 }
5644
5645 return c;
5646 }
5647
5648 static struct event_constraint *
rwc_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5649 rwc_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5650 struct perf_event *event)
5651 {
5652 struct event_constraint *c;
5653
5654 c = glc_get_event_constraints(cpuc, idx, event);
5655
5656 /* The Retire Latency is not supported by the fixed counter 0. */
5657 if (event->attr.precise_ip &&
5658 (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
5659 constraint_match(&fixed0_constraint, event->hw.config)) {
5660 /*
5661 * The Instruction PDIR is only available
5662 * on the fixed counter 0. Error out for this case.
5663 */
5664 if (event->attr.precise_ip == 3)
5665 return &emptyconstraint;
5666 return &counters_1_7_constraint;
5667 }
5668
5669 return c;
5670 }
5671
5672 static struct event_constraint *
mtl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5673 mtl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5674 struct perf_event *event)
5675 {
5676 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5677
5678 if (pmu->pmu_type == hybrid_big)
5679 return rwc_get_event_constraints(cpuc, idx, event);
5680 if (pmu->pmu_type == hybrid_small)
5681 return cmt_get_event_constraints(cpuc, idx, event);
5682
5683 WARN_ON(1);
5684 return &emptyconstraint;
5685 }
5686
adl_hw_config(struct perf_event * event)5687 static int adl_hw_config(struct perf_event *event)
5688 {
5689 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5690
5691 if (pmu->pmu_type == hybrid_big)
5692 return hsw_hw_config(event);
5693 else if (pmu->pmu_type == hybrid_small)
5694 return intel_pmu_hw_config(event);
5695
5696 WARN_ON(1);
5697 return -EOPNOTSUPP;
5698 }
5699
adl_get_hybrid_cpu_type(void)5700 static enum intel_cpu_type adl_get_hybrid_cpu_type(void)
5701 {
5702 return INTEL_CPU_TYPE_CORE;
5703 }
5704
erratum_hsw11(struct perf_event * event)5705 static inline bool erratum_hsw11(struct perf_event *event)
5706 {
5707 return (event->hw.config & INTEL_ARCH_EVENT_MASK) ==
5708 X86_CONFIG(.event=0xc0, .umask=0x01);
5709 }
5710
5711 static struct event_constraint *
arl_h_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)5712 arl_h_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
5713 struct perf_event *event)
5714 {
5715 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5716
5717 if (pmu->pmu_type == hybrid_tiny)
5718 return cmt_get_event_constraints(cpuc, idx, event);
5719
5720 return mtl_get_event_constraints(cpuc, idx, event);
5721 }
5722
arl_h_hw_config(struct perf_event * event)5723 static int arl_h_hw_config(struct perf_event *event)
5724 {
5725 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu);
5726
5727 if (pmu->pmu_type == hybrid_tiny)
5728 return intel_pmu_hw_config(event);
5729
5730 return adl_hw_config(event);
5731 }
5732
5733 /*
5734 * The HSW11 requires a period larger than 100 which is the same as the BDM11.
5735 * A minimum period of 128 is enforced as well for the INST_RETIRED.ALL.
5736 *
5737 * The message 'interrupt took too long' can be observed on any counter which
5738 * was armed with a period < 32 and two events expired in the same NMI.
5739 * A minimum period of 32 is enforced for the rest of the events.
5740 */
hsw_limit_period(struct perf_event * event,s64 * left)5741 static void hsw_limit_period(struct perf_event *event, s64 *left)
5742 {
5743 *left = max(*left, erratum_hsw11(event) ? 128 : 32);
5744 }
5745
5746 /*
5747 * Broadwell:
5748 *
5749 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
5750 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
5751 * the two to enforce a minimum period of 128 (the smallest value that has bits
5752 * 0-5 cleared and >= 100).
5753 *
5754 * Because of how the code in x86_perf_event_set_period() works, the truncation
5755 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
5756 * to make up for the 'lost' events due to carrying the 'error' in period_left.
5757 *
5758 * Therefore the effective (average) period matches the requested period,
5759 * despite coarser hardware granularity.
5760 */
bdw_limit_period(struct perf_event * event,s64 * left)5761 static void bdw_limit_period(struct perf_event *event, s64 *left)
5762 {
5763 if (erratum_hsw11(event)) {
5764 if (*left < 128)
5765 *left = 128;
5766 *left &= ~0x3fULL;
5767 }
5768 }
5769
nhm_limit_period(struct perf_event * event,s64 * left)5770 static void nhm_limit_period(struct perf_event *event, s64 *left)
5771 {
5772 *left = max(*left, 32LL);
5773 }
5774
glc_limit_period(struct perf_event * event,s64 * left)5775 static void glc_limit_period(struct perf_event *event, s64 *left)
5776 {
5777 if (event->attr.precise_ip == 3)
5778 *left = max(*left, 128LL);
5779 }
5780
5781 PMU_FORMAT_ATTR(event, "config:0-7" );
5782 PMU_FORMAT_ATTR(umask, "config:8-15" );
5783 PMU_FORMAT_ATTR(edge, "config:18" );
5784 PMU_FORMAT_ATTR(pc, "config:19" );
5785 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
5786 PMU_FORMAT_ATTR(inv, "config:23" );
5787 PMU_FORMAT_ATTR(cmask, "config:24-31" );
5788 PMU_FORMAT_ATTR(in_tx, "config:32" );
5789 PMU_FORMAT_ATTR(in_tx_cp, "config:33" );
5790 PMU_FORMAT_ATTR(eq, "config:36" ); /* v6 + */
5791
5792 PMU_FORMAT_ATTR(metrics_clear, "config1:0"); /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */
5793
umask2_show(struct device * dev,struct device_attribute * attr,char * page)5794 static ssize_t umask2_show(struct device *dev,
5795 struct device_attribute *attr,
5796 char *page)
5797 {
5798 u64 mask = hybrid(dev_get_drvdata(dev), config_mask) & ARCH_PERFMON_EVENTSEL_UMASK2;
5799
5800 if (mask == ARCH_PERFMON_EVENTSEL_UMASK2)
5801 return sprintf(page, "config:8-15,40-47\n");
5802
5803 /* Roll back to the old format if umask2 is not supported. */
5804 return sprintf(page, "config:8-15\n");
5805 }
5806
5807 static struct device_attribute format_attr_umask2 =
5808 __ATTR(umask, 0444, umask2_show, NULL);
5809
5810 static struct attribute *format_evtsel_ext_attrs[] = {
5811 &format_attr_umask2.attr,
5812 &format_attr_eq.attr,
5813 &format_attr_metrics_clear.attr,
5814 NULL
5815 };
5816
5817 static umode_t
evtsel_ext_is_visible(struct kobject * kobj,struct attribute * attr,int i)5818 evtsel_ext_is_visible(struct kobject *kobj, struct attribute *attr, int i)
5819 {
5820 struct device *dev = kobj_to_dev(kobj);
5821 u64 mask;
5822
5823 /*
5824 * The umask and umask2 have different formats but share the
5825 * same attr name. In update mode, the previous value of the
5826 * umask is unconditionally removed before is_visible. If
5827 * umask2 format is not enumerated, it's impossible to roll
5828 * back to the old format.
5829 * Does the check in umask2_show rather than is_visible.
5830 */
5831 if (i == 0)
5832 return attr->mode;
5833
5834 mask = hybrid(dev_get_drvdata(dev), config_mask);
5835 if (i == 1)
5836 return (mask & ARCH_PERFMON_EVENTSEL_EQ) ? attr->mode : 0;
5837
5838 /* PERF_CAPABILITIES.RDPMC_METRICS_CLEAR */
5839 if (i == 2) {
5840 union perf_capabilities intel_cap = hybrid(dev_get_drvdata(dev), intel_cap);
5841
5842 return intel_cap.rdpmc_metrics_clear ? attr->mode : 0;
5843 }
5844
5845 return 0;
5846 }
5847
5848 static struct attribute *intel_arch_formats_attr[] = {
5849 &format_attr_event.attr,
5850 &format_attr_umask.attr,
5851 &format_attr_edge.attr,
5852 &format_attr_pc.attr,
5853 &format_attr_inv.attr,
5854 &format_attr_cmask.attr,
5855 NULL,
5856 };
5857
intel_event_sysfs_show(char * page,u64 config)5858 ssize_t intel_event_sysfs_show(char *page, u64 config)
5859 {
5860 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
5861
5862 return x86_event_sysfs_show(page, config, event);
5863 }
5864
allocate_shared_regs(int cpu)5865 static struct intel_shared_regs *allocate_shared_regs(int cpu)
5866 {
5867 struct intel_shared_regs *regs;
5868 int i;
5869
5870 regs = kzalloc_node(sizeof(struct intel_shared_regs),
5871 GFP_KERNEL, cpu_to_node(cpu));
5872 if (regs) {
5873 /*
5874 * initialize the locks to keep lockdep happy
5875 */
5876 for (i = 0; i < EXTRA_REG_MAX; i++)
5877 raw_spin_lock_init(®s->regs[i].lock);
5878
5879 regs->core_id = -1;
5880 }
5881 return regs;
5882 }
5883
allocate_excl_cntrs(int cpu)5884 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
5885 {
5886 struct intel_excl_cntrs *c;
5887
5888 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
5889 GFP_KERNEL, cpu_to_node(cpu));
5890 if (c) {
5891 raw_spin_lock_init(&c->lock);
5892 c->core_id = -1;
5893 }
5894 return c;
5895 }
5896
5897
intel_cpuc_prepare(struct cpu_hw_events * cpuc,int cpu)5898 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
5899 {
5900 cpuc->pebs_record_size = x86_pmu.pebs_record_size;
5901
5902 if (is_hybrid() || x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
5903 cpuc->shared_regs = allocate_shared_regs(cpu);
5904 if (!cpuc->shared_regs)
5905 goto err;
5906 }
5907
5908 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA | PMU_FL_DYN_CONSTRAINT)) {
5909 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
5910
5911 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
5912 if (!cpuc->constraint_list)
5913 goto err_shared_regs;
5914 }
5915
5916 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
5917 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
5918 if (!cpuc->excl_cntrs)
5919 goto err_constraint_list;
5920
5921 cpuc->excl_thread_id = 0;
5922 }
5923
5924 return 0;
5925
5926 err_constraint_list:
5927 kfree(cpuc->constraint_list);
5928 cpuc->constraint_list = NULL;
5929
5930 err_shared_regs:
5931 kfree(cpuc->shared_regs);
5932 cpuc->shared_regs = NULL;
5933
5934 err:
5935 return -ENOMEM;
5936 }
5937
intel_pmu_cpu_prepare(int cpu)5938 static int intel_pmu_cpu_prepare(int cpu)
5939 {
5940 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
5941 int ret;
5942
5943 ret = intel_cpuc_prepare(cpuc, cpu);
5944 if (ret)
5945 return ret;
5946
5947 ret = alloc_arch_pebs_buf_on_cpu(cpu);
5948 if (ret) {
5949 intel_cpuc_finish(cpuc);
5950 return ret;
5951 }
5952
5953 return 0;
5954 }
5955
flip_smm_bit(void * data)5956 static void flip_smm_bit(void *data)
5957 {
5958 unsigned long set = *(unsigned long *)data;
5959
5960 if (set > 0) {
5961 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
5962 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
5963 } else {
5964 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
5965 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
5966 }
5967 }
5968
intel_pmu_check_counters_mask(u64 * cntr_mask,u64 * fixed_cntr_mask,u64 * intel_ctrl)5969 static void intel_pmu_check_counters_mask(u64 *cntr_mask,
5970 u64 *fixed_cntr_mask,
5971 u64 *intel_ctrl)
5972 {
5973 unsigned int bit;
5974
5975 bit = fls64(*cntr_mask);
5976 if (bit > INTEL_PMC_MAX_GENERIC) {
5977 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
5978 bit, INTEL_PMC_MAX_GENERIC);
5979 *cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0);
5980 }
5981 *intel_ctrl = *cntr_mask;
5982
5983 bit = fls64(*fixed_cntr_mask);
5984 if (bit > INTEL_PMC_MAX_FIXED) {
5985 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
5986 bit, INTEL_PMC_MAX_FIXED);
5987 *fixed_cntr_mask &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0);
5988 }
5989
5990 *intel_ctrl |= *fixed_cntr_mask << INTEL_PMC_IDX_FIXED;
5991 }
5992
5993 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
5994 u64 cntr_mask,
5995 u64 fixed_cntr_mask,
5996 u64 intel_ctrl);
5997
5998 enum dyn_constr_type {
5999 DYN_CONSTR_NONE,
6000 DYN_CONSTR_BR_CNTR,
6001 DYN_CONSTR_ACR_CNTR,
6002 DYN_CONSTR_ACR_CAUSE,
6003 DYN_CONSTR_PEBS,
6004 DYN_CONSTR_PDIST,
6005
6006 DYN_CONSTR_MAX,
6007 };
6008
6009 static const char * const dyn_constr_type_name[] = {
6010 [DYN_CONSTR_NONE] = "a normal event",
6011 [DYN_CONSTR_BR_CNTR] = "a branch counter logging event",
6012 [DYN_CONSTR_ACR_CNTR] = "an auto-counter reload event",
6013 [DYN_CONSTR_ACR_CAUSE] = "an auto-counter reload cause event",
6014 [DYN_CONSTR_PEBS] = "a PEBS event",
6015 [DYN_CONSTR_PDIST] = "a PEBS PDIST event",
6016 };
6017
__intel_pmu_check_dyn_constr(struct event_constraint * constr,enum dyn_constr_type type,u64 mask)6018 static void __intel_pmu_check_dyn_constr(struct event_constraint *constr,
6019 enum dyn_constr_type type, u64 mask)
6020 {
6021 struct event_constraint *c1, *c2;
6022 int new_weight, check_weight;
6023 u64 new_mask, check_mask;
6024
6025 for_each_event_constraint(c1, constr) {
6026 new_mask = c1->idxmsk64 & mask;
6027 new_weight = hweight64(new_mask);
6028
6029 /* ignore topdown perf metrics event */
6030 if (c1->idxmsk64 & INTEL_PMC_MSK_TOPDOWN)
6031 continue;
6032
6033 if (!new_weight && fls64(c1->idxmsk64) < INTEL_PMC_IDX_FIXED) {
6034 pr_info("The event 0x%llx is not supported as %s.\n",
6035 c1->code, dyn_constr_type_name[type]);
6036 }
6037
6038 if (new_weight <= 1)
6039 continue;
6040
6041 for_each_event_constraint(c2, c1 + 1) {
6042 bool check_fail = false;
6043
6044 check_mask = c2->idxmsk64 & mask;
6045 check_weight = hweight64(check_mask);
6046
6047 if (c2->idxmsk64 & INTEL_PMC_MSK_TOPDOWN ||
6048 !check_weight)
6049 continue;
6050
6051 /* The same constraints or no overlap */
6052 if (new_mask == check_mask ||
6053 (new_mask ^ check_mask) == (new_mask | check_mask))
6054 continue;
6055
6056 /*
6057 * A scheduler issue may be triggered in the following cases.
6058 * - Two overlap constraints have the same weight.
6059 * E.g., A constraints: 0x3, B constraints: 0x6
6060 * event counter failure case
6061 * B PMC[2:1] 1
6062 * A PMC[1:0] 0
6063 * A PMC[1:0] FAIL
6064 * - Two overlap constraints have different weight.
6065 * The constraint has a low weight, but has high last bit.
6066 * E.g., A constraints: 0x7, B constraints: 0xC
6067 * event counter failure case
6068 * B PMC[3:2] 2
6069 * A PMC[2:0] 0
6070 * A PMC[2:0] 1
6071 * A PMC[2:0] FAIL
6072 */
6073 if (new_weight == check_weight) {
6074 check_fail = true;
6075 } else if (new_weight < check_weight) {
6076 if ((new_mask | check_mask) != check_mask &&
6077 fls64(new_mask) > fls64(check_mask))
6078 check_fail = true;
6079 } else {
6080 if ((new_mask | check_mask) != new_mask &&
6081 fls64(new_mask) < fls64(check_mask))
6082 check_fail = true;
6083 }
6084
6085 if (check_fail) {
6086 pr_warn("The two events 0x%llx and 0x%llx may not be "
6087 "fully scheduled under some circumstances as "
6088 "%s.\n",
6089 c1->code, c2->code, dyn_constr_type_name[type]);
6090 }
6091 }
6092 }
6093 }
6094
intel_pmu_check_dyn_constr(struct pmu * pmu,struct event_constraint * constr,u64 cntr_mask)6095 static void intel_pmu_check_dyn_constr(struct pmu *pmu,
6096 struct event_constraint *constr,
6097 u64 cntr_mask)
6098 {
6099 u64 gp_mask = GENMASK_ULL(INTEL_PMC_MAX_GENERIC - 1, 0);
6100 enum dyn_constr_type i;
6101 u64 mask;
6102
6103 for (i = DYN_CONSTR_NONE; i < DYN_CONSTR_MAX; i++) {
6104 mask = 0;
6105 switch (i) {
6106 case DYN_CONSTR_NONE:
6107 mask = cntr_mask;
6108 break;
6109 case DYN_CONSTR_BR_CNTR:
6110 if (x86_pmu.flags & PMU_FL_BR_CNTR)
6111 mask = x86_pmu.lbr_counters;
6112 break;
6113 case DYN_CONSTR_ACR_CNTR:
6114 mask = hybrid(pmu, acr_cntr_mask64) & gp_mask;
6115 break;
6116 case DYN_CONSTR_ACR_CAUSE:
6117 if (hybrid(pmu, acr_cntr_mask64) ==
6118 hybrid(pmu, acr_cause_mask64))
6119 continue;
6120 mask = hybrid(pmu, acr_cause_mask64) & gp_mask;
6121 break;
6122 case DYN_CONSTR_PEBS:
6123 if (x86_pmu.arch_pebs) {
6124 mask = hybrid(pmu, arch_pebs_cap).counters &
6125 gp_mask;
6126 }
6127 break;
6128 case DYN_CONSTR_PDIST:
6129 if (x86_pmu.arch_pebs) {
6130 mask = hybrid(pmu, arch_pebs_cap).pdists &
6131 gp_mask;
6132 }
6133 break;
6134 default:
6135 pr_warn("Unsupported dynamic constraint type %d\n", i);
6136 }
6137
6138 if (mask)
6139 __intel_pmu_check_dyn_constr(constr, i, mask);
6140 }
6141 }
6142
intel_pmu_check_event_constraints_all(struct pmu * pmu)6143 static void intel_pmu_check_event_constraints_all(struct pmu *pmu)
6144 {
6145 struct event_constraint *event_constraints = hybrid(pmu, event_constraints);
6146 struct event_constraint *pebs_constraints = hybrid(pmu, pebs_constraints);
6147 u64 cntr_mask = hybrid(pmu, cntr_mask64);
6148 u64 fixed_cntr_mask = hybrid(pmu, fixed_cntr_mask64);
6149 u64 intel_ctrl = hybrid(pmu, intel_ctrl);
6150
6151 intel_pmu_check_event_constraints(event_constraints, cntr_mask,
6152 fixed_cntr_mask, intel_ctrl);
6153
6154 if (event_constraints)
6155 intel_pmu_check_dyn_constr(pmu, event_constraints, cntr_mask);
6156
6157 if (pebs_constraints)
6158 intel_pmu_check_dyn_constr(pmu, pebs_constraints, cntr_mask);
6159 }
6160
6161 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs);
6162
intel_pmu_broken_perf_cap(void)6163 static inline bool intel_pmu_broken_perf_cap(void)
6164 {
6165 /*
6166 * The Perf Metric (Bit 15) is always cleared on P-core of
6167 * RPL and MTL. Details can be found in RPL018 erratum.
6168 */
6169 if (boot_cpu_data.x86_vfm == INTEL_RAPTORLAKE ||
6170 boot_cpu_data.x86_vfm == INTEL_RAPTORLAKE_P ||
6171 boot_cpu_data.x86_vfm == INTEL_RAPTORLAKE_S ||
6172 boot_cpu_data.x86_vfm == INTEL_METEORLAKE ||
6173 boot_cpu_data.x86_vfm == INTEL_METEORLAKE_L)
6174 return true;
6175
6176 return false;
6177 }
6178
__intel_update_pmu_caps(struct pmu * pmu)6179 static inline void __intel_update_pmu_caps(struct pmu *pmu)
6180 {
6181 struct pmu *dest_pmu = pmu ? pmu : x86_get_pmu(smp_processor_id());
6182
6183 if (hybrid(pmu, arch_pebs_cap).caps & ARCH_PEBS_VECR_XMM)
6184 dest_pmu->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
6185 }
6186
__intel_update_large_pebs_flags(struct pmu * pmu)6187 static inline void __intel_update_large_pebs_flags(struct pmu *pmu)
6188 {
6189 u64 caps = hybrid(pmu, arch_pebs_cap).caps;
6190
6191 x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
6192 if (caps & ARCH_PEBS_LBR)
6193 x86_pmu.large_pebs_flags |= PERF_SAMPLE_BRANCH_STACK;
6194 if (caps & ARCH_PEBS_CNTR_MASK)
6195 x86_pmu.large_pebs_flags |= PERF_SAMPLE_READ;
6196
6197 if (!(caps & ARCH_PEBS_AUX))
6198 x86_pmu.large_pebs_flags &= ~PERF_SAMPLE_DATA_SRC;
6199 if (!(caps & ARCH_PEBS_GPR)) {
6200 x86_pmu.large_pebs_flags &=
6201 ~(PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER);
6202 }
6203 }
6204
6205 #define counter_mask(_gp, _fixed) ((_gp) | ((u64)(_fixed) << INTEL_PMC_IDX_FIXED))
6206
update_pmu_cap_from_perfmonext(struct pmu * pmu)6207 static void update_pmu_cap_from_perfmonext(struct pmu *pmu)
6208 {
6209 unsigned int eax, ebx, ecx, edx;
6210 union cpuid35_eax eax_0;
6211 union cpuid35_ebx ebx_0;
6212 u64 cntrs_mask = 0;
6213 u64 pebs_mask = 0;
6214 u64 pdists_mask = 0;
6215
6216 cpuid(ARCH_PERFMON_EXT_LEAF, &eax_0.full, &ebx_0.full, &ecx, &edx);
6217
6218 if (ebx_0.split.umask2)
6219 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_UMASK2;
6220 if (ebx_0.split.eq)
6221 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_EQ;
6222 if (ebx_0.split.rdpmc_user_disable)
6223 hybrid(pmu, config_mask) |= ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE;
6224
6225 if (eax_0.split.cntr_subleaf) {
6226 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF,
6227 &eax, &ebx, &ecx, &edx);
6228 hybrid(pmu, cntr_mask64) = eax;
6229 hybrid(pmu, fixed_cntr_mask64) = ebx;
6230 cntrs_mask = counter_mask(eax, ebx);
6231 }
6232
6233 if (eax_0.split.acr_subleaf) {
6234 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_ACR_LEAF,
6235 &eax, &ebx, &ecx, &edx);
6236 /* The mask of the counters which can be reloaded */
6237 hybrid(pmu, acr_cntr_mask64) = counter_mask(eax, ebx);
6238 /* The mask of the counters which can cause a reload of reloadable counters */
6239 hybrid(pmu, acr_cause_mask64) = counter_mask(ecx, edx);
6240 }
6241
6242 /* Bits[5:4] should be set simultaneously if arch-PEBS is supported */
6243 if (eax_0.split.pebs_caps_subleaf && eax_0.split.pebs_cnts_subleaf) {
6244 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_CAP_LEAF,
6245 &eax, &ebx, &ecx, &edx);
6246 hybrid(pmu, arch_pebs_cap).caps = (u64)ebx << 32;
6247
6248 cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_COUNTER_LEAF,
6249 &eax, &ebx, &ecx, &edx);
6250 pebs_mask = counter_mask(eax, ecx);
6251 pdists_mask = counter_mask(ebx, edx);
6252 hybrid(pmu, arch_pebs_cap).counters = pebs_mask;
6253 hybrid(pmu, arch_pebs_cap).pdists = pdists_mask;
6254
6255 if (WARN_ON((pebs_mask | pdists_mask) & ~cntrs_mask)) {
6256 x86_pmu.arch_pebs = 0;
6257 } else {
6258 __intel_update_pmu_caps(pmu);
6259 __intel_update_large_pebs_flags(pmu);
6260 }
6261 } else {
6262 WARN_ON(x86_pmu.arch_pebs == 1);
6263 x86_pmu.arch_pebs = 0;
6264 }
6265 }
6266
intel_update_pmu_caps(struct pmu * pmu)6267 static void intel_update_pmu_caps(struct pmu *pmu)
6268 {
6269 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT))
6270 update_pmu_cap_from_perfmonext(pmu);
6271
6272 if (is_hybrid() && this_cpu_has(X86_FEATURE_PDCM)) {
6273 rdmsrq(MSR_IA32_PERF_CAPABILITIES,
6274 hybrid(pmu, intel_cap).capabilities);
6275
6276 /*
6277 * Restore perf_metrics on platforms with broken
6278 * perf_capablities.
6279 */
6280 if (intel_pmu_broken_perf_cap() &&
6281 hybrid_pmu(pmu)->pmu_type == hybrid_big)
6282 hybrid(pmu, intel_cap).perf_metrics = 1;
6283 }
6284 }
6285
intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu * pmu)6286 static void intel_pmu_check_hybrid_pmus(struct x86_hybrid_pmu *pmu)
6287 {
6288 intel_pmu_check_counters_mask(&pmu->cntr_mask64, &pmu->fixed_cntr_mask64,
6289 &pmu->intel_ctrl);
6290 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
6291 pmu->unconstrained = (struct event_constraint)
6292 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
6293 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
6294
6295 if (pmu->intel_cap.perf_metrics)
6296 pmu->intel_ctrl |= GLOBAL_CTRL_EN_PERF_METRICS;
6297 else
6298 pmu->intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS;
6299
6300 pmu->pmu.capabilities |= PERF_PMU_CAP_MEDIATED_VPMU;
6301
6302 intel_pmu_check_event_constraints_all(&pmu->pmu);
6303
6304 intel_pmu_check_extra_regs(pmu->extra_regs);
6305 }
6306
find_hybrid_pmu_for_cpu(void)6307 static struct x86_hybrid_pmu *find_hybrid_pmu_for_cpu(void)
6308 {
6309 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
6310 enum intel_cpu_type cpu_type = c->topo.intel_type;
6311 int i;
6312
6313 /*
6314 * This is running on a CPU model that is known to have hybrid
6315 * configurations. But the CPU told us it is not hybrid, shame
6316 * on it. There should be a fixup function provided for these
6317 * troublesome CPUs (->get_hybrid_cpu_type).
6318 */
6319 if (cpu_type == INTEL_CPU_TYPE_UNKNOWN) {
6320 if (x86_pmu.get_hybrid_cpu_type)
6321 cpu_type = x86_pmu.get_hybrid_cpu_type();
6322 else
6323 return NULL;
6324 }
6325
6326 /*
6327 * This essentially just maps between the 'hybrid_cpu_type'
6328 * and 'hybrid_pmu_type' enums except for ARL-H processor
6329 * which needs to compare atom uarch native id since ARL-H
6330 * contains two different atom uarchs.
6331 */
6332 for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {
6333 enum hybrid_pmu_type pmu_type = x86_pmu.hybrid_pmu[i].pmu_type;
6334 u32 native_id;
6335
6336 if (cpu_type == INTEL_CPU_TYPE_CORE && pmu_type == hybrid_big)
6337 return &x86_pmu.hybrid_pmu[i];
6338 if (cpu_type == INTEL_CPU_TYPE_ATOM) {
6339 if (x86_pmu.num_hybrid_pmus == 2 && pmu_type == hybrid_small)
6340 return &x86_pmu.hybrid_pmu[i];
6341
6342 native_id = c->topo.intel_native_model_id;
6343 if (native_id == INTEL_ATOM_SKT_NATIVE_ID && pmu_type == hybrid_small)
6344 return &x86_pmu.hybrid_pmu[i];
6345 if (native_id == INTEL_ATOM_CMT_NATIVE_ID && pmu_type == hybrid_tiny)
6346 return &x86_pmu.hybrid_pmu[i];
6347 }
6348 }
6349
6350 return NULL;
6351 }
6352
init_hybrid_pmu(int cpu)6353 static bool init_hybrid_pmu(int cpu)
6354 {
6355 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
6356 struct x86_hybrid_pmu *pmu = find_hybrid_pmu_for_cpu();
6357
6358 if (WARN_ON_ONCE(!pmu || (pmu->pmu.type == -1))) {
6359 cpuc->pmu = NULL;
6360 return false;
6361 }
6362
6363 /* Only check and dump the PMU information for the first CPU */
6364 if (!cpumask_empty(&pmu->supported_cpus))
6365 goto end;
6366
6367 intel_update_pmu_caps(&pmu->pmu);
6368 intel_pmu_check_hybrid_pmus(pmu);
6369
6370 if (!check_hw_exists(pmu->cntr_mask, pmu->fixed_cntr_mask)) {
6371 cpuc->pmu = NULL;
6372 return false;
6373 }
6374
6375 pr_info("%s PMU driver: ", pmu->name);
6376
6377 pr_cont("\n");
6378
6379 x86_pmu_show_pmu_cap(&pmu->pmu);
6380
6381 end:
6382 cpumask_set_cpu(cpu, &pmu->supported_cpus);
6383 cpuc->pmu = &pmu->pmu;
6384
6385 return true;
6386 }
6387
intel_pmu_cpu_starting(int cpu)6388 static void intel_pmu_cpu_starting(int cpu)
6389 {
6390 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
6391 int core_id = topology_core_id(cpu);
6392 int i;
6393
6394 if (is_hybrid() && !init_hybrid_pmu(cpu))
6395 return;
6396
6397 init_debug_store_on_cpu(cpu);
6398 init_arch_pebs_on_cpu(cpu);
6399 /*
6400 * Deal with CPUs that don't clear their LBRs on power-up, and that may
6401 * even boot with LBRs enabled.
6402 */
6403 if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR) && x86_pmu.lbr_nr)
6404 msr_clear_bit(MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_LBR_BIT);
6405 intel_pmu_lbr_reset();
6406
6407 cpuc->lbr_sel = NULL;
6408
6409 if (x86_pmu.flags & PMU_FL_TFA) {
6410 WARN_ON_ONCE(cpuc->tfa_shadow);
6411 cpuc->tfa_shadow = ~0ULL;
6412 intel_set_tfa(cpuc, false);
6413 }
6414
6415 if (x86_pmu.version > 1)
6416 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
6417
6418 /*
6419 * Disable perf metrics if any added CPU doesn't support it.
6420 *
6421 * Turn off the check for a hybrid architecture, because the
6422 * architecture MSR, MSR_IA32_PERF_CAPABILITIES, only indicate
6423 * the architecture features. The perf metrics is a model-specific
6424 * feature for now. The corresponding bit should always be 0 on
6425 * a hybrid platform, e.g., Alder Lake.
6426 */
6427 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics) {
6428 union perf_capabilities perf_cap;
6429
6430 rdmsrq(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
6431 if (!perf_cap.perf_metrics) {
6432 x86_pmu.intel_cap.perf_metrics = 0;
6433 x86_pmu.intel_ctrl &= ~GLOBAL_CTRL_EN_PERF_METRICS;
6434 }
6435 }
6436
6437 __intel_update_pmu_caps(cpuc->pmu);
6438
6439 if (!cpuc->shared_regs)
6440 return;
6441
6442 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
6443 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
6444 struct intel_shared_regs *pc;
6445
6446 pc = per_cpu(cpu_hw_events, i).shared_regs;
6447 if (pc && pc->core_id == core_id) {
6448 cpuc->kfree_on_online[0] = cpuc->shared_regs;
6449 cpuc->shared_regs = pc;
6450 break;
6451 }
6452 }
6453 cpuc->shared_regs->core_id = core_id;
6454 cpuc->shared_regs->refcnt++;
6455 }
6456
6457 if (x86_pmu.lbr_sel_map)
6458 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
6459
6460 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
6461 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
6462 struct cpu_hw_events *sibling;
6463 struct intel_excl_cntrs *c;
6464
6465 sibling = &per_cpu(cpu_hw_events, i);
6466 c = sibling->excl_cntrs;
6467 if (c && c->core_id == core_id) {
6468 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
6469 cpuc->excl_cntrs = c;
6470 if (!sibling->excl_thread_id)
6471 cpuc->excl_thread_id = 1;
6472 break;
6473 }
6474 }
6475 cpuc->excl_cntrs->core_id = core_id;
6476 cpuc->excl_cntrs->refcnt++;
6477 }
6478 }
6479
free_excl_cntrs(struct cpu_hw_events * cpuc)6480 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
6481 {
6482 struct intel_excl_cntrs *c;
6483
6484 c = cpuc->excl_cntrs;
6485 if (c) {
6486 if (c->core_id == -1 || --c->refcnt == 0)
6487 kfree(c);
6488 cpuc->excl_cntrs = NULL;
6489 }
6490
6491 kfree(cpuc->constraint_list);
6492 cpuc->constraint_list = NULL;
6493 }
6494
intel_pmu_cpu_dying(int cpu)6495 static void intel_pmu_cpu_dying(int cpu)
6496 {
6497 fini_debug_store_on_cpu(cpu);
6498 fini_arch_pebs_on_cpu(cpu);
6499 }
6500
intel_cpuc_finish(struct cpu_hw_events * cpuc)6501 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
6502 {
6503 struct intel_shared_regs *pc;
6504
6505 pc = cpuc->shared_regs;
6506 if (pc) {
6507 if (pc->core_id == -1 || --pc->refcnt == 0)
6508 kfree(pc);
6509 cpuc->shared_regs = NULL;
6510 }
6511
6512 free_excl_cntrs(cpuc);
6513 }
6514
intel_pmu_cpu_dead(int cpu)6515 static void intel_pmu_cpu_dead(int cpu)
6516 {
6517 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
6518 struct pmu *pmu = x86_get_static_pmu();
6519
6520 release_arch_pebs_buf_on_cpu(cpu);
6521 intel_cpuc_finish(cpuc);
6522
6523 if (is_hybrid() && cpuc->pmu && cpuc->pmu != pmu)
6524 cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus);
6525 }
6526
intel_pmu_sched_task(struct perf_event_pmu_context * pmu_ctx,struct task_struct * task,bool sched_in)6527 static void intel_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx,
6528 struct task_struct *task, bool sched_in)
6529 {
6530 intel_pmu_pebs_sched_task(pmu_ctx, sched_in);
6531 intel_pmu_lbr_sched_task(pmu_ctx, task, sched_in);
6532 }
6533
intel_pmu_check_period(struct perf_event * event,u64 value)6534 static int intel_pmu_check_period(struct perf_event *event, u64 value)
6535 {
6536 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
6537 }
6538
intel_aux_output_init(void)6539 static void intel_aux_output_init(void)
6540 {
6541 /* Refer also intel_pmu_aux_output_match() */
6542 if (x86_pmu.intel_cap.pebs_output_pt_available)
6543 x86_pmu.assign = intel_pmu_assign_event;
6544 }
6545
intel_pmu_aux_output_match(struct perf_event * event)6546 static int intel_pmu_aux_output_match(struct perf_event *event)
6547 {
6548 /* intel_pmu_assign_event() is needed, refer intel_aux_output_init() */
6549 if (!x86_pmu.intel_cap.pebs_output_pt_available)
6550 return 0;
6551
6552 return is_intel_pt_event(event);
6553 }
6554
intel_pmu_filter(struct pmu * pmu,int cpu,bool * ret)6555 static void intel_pmu_filter(struct pmu *pmu, int cpu, bool *ret)
6556 {
6557 struct x86_hybrid_pmu *hpmu = hybrid_pmu(pmu);
6558
6559 *ret = !cpumask_test_cpu(cpu, &hpmu->supported_cpus);
6560 }
6561
6562 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
6563
6564 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
6565
6566 PMU_FORMAT_ATTR(frontend, "config1:0-23");
6567
6568 PMU_FORMAT_ATTR(snoop_rsp, "config1:0-63");
6569
6570 static struct attribute *intel_arch3_formats_attr[] = {
6571 &format_attr_event.attr,
6572 &format_attr_umask.attr,
6573 &format_attr_edge.attr,
6574 &format_attr_pc.attr,
6575 &format_attr_any.attr,
6576 &format_attr_inv.attr,
6577 &format_attr_cmask.attr,
6578 NULL,
6579 };
6580
6581 static struct attribute *hsw_format_attr[] = {
6582 &format_attr_in_tx.attr,
6583 &format_attr_in_tx_cp.attr,
6584 &format_attr_offcore_rsp.attr,
6585 &format_attr_ldlat.attr,
6586 NULL
6587 };
6588
6589 static struct attribute *nhm_format_attr[] = {
6590 &format_attr_offcore_rsp.attr,
6591 &format_attr_ldlat.attr,
6592 NULL
6593 };
6594
6595 static struct attribute *slm_format_attr[] = {
6596 &format_attr_offcore_rsp.attr,
6597 NULL
6598 };
6599
6600 static struct attribute *cmt_format_attr[] = {
6601 &format_attr_offcore_rsp.attr,
6602 &format_attr_ldlat.attr,
6603 &format_attr_snoop_rsp.attr,
6604 NULL
6605 };
6606
6607 static struct attribute *skl_format_attr[] = {
6608 &format_attr_frontend.attr,
6609 NULL,
6610 };
6611
6612 static __initconst const struct x86_pmu core_pmu = {
6613 .name = "core",
6614 .handle_irq = x86_pmu_handle_irq,
6615 .disable_all = x86_pmu_disable_all,
6616 .enable_all = core_pmu_enable_all,
6617 .enable = core_pmu_enable_event,
6618 .disable = x86_pmu_disable_event,
6619 .hw_config = core_pmu_hw_config,
6620 .schedule_events = x86_schedule_events,
6621 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
6622 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
6623 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0,
6624 .event_map = intel_pmu_event_map,
6625 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
6626 .apic = 1,
6627 .large_pebs_flags = LARGE_PEBS_FLAGS,
6628
6629 /*
6630 * Intel PMCs cannot be accessed sanely above 32-bit width,
6631 * so we install an artificial 1<<31 period regardless of
6632 * the generic event period:
6633 */
6634 .max_period = (1ULL<<31) - 1,
6635 .get_event_constraints = intel_get_event_constraints,
6636 .put_event_constraints = intel_put_event_constraints,
6637 .event_constraints = intel_core_event_constraints,
6638 .guest_get_msrs = core_guest_get_msrs,
6639 .format_attrs = intel_arch_formats_attr,
6640 .events_sysfs_show = intel_event_sysfs_show,
6641
6642 /*
6643 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
6644 * together with PMU version 1 and thus be using core_pmu with
6645 * shared_regs. We need following callbacks here to allocate
6646 * it properly.
6647 */
6648 .cpu_prepare = intel_pmu_cpu_prepare,
6649 .cpu_starting = intel_pmu_cpu_starting,
6650 .cpu_dying = intel_pmu_cpu_dying,
6651 .cpu_dead = intel_pmu_cpu_dead,
6652
6653 .check_period = intel_pmu_check_period,
6654
6655 .lbr_reset = intel_pmu_lbr_reset_64,
6656 .lbr_read = intel_pmu_lbr_read_64,
6657 .lbr_save = intel_pmu_lbr_save,
6658 .lbr_restore = intel_pmu_lbr_restore,
6659 };
6660
6661 static __initconst const struct x86_pmu intel_pmu = {
6662 .name = "Intel",
6663 .handle_irq = intel_pmu_handle_irq,
6664 .disable_all = intel_pmu_disable_all,
6665 .enable_all = intel_pmu_enable_all,
6666 .enable = intel_pmu_enable_event,
6667 .disable = intel_pmu_disable_event,
6668 .add = intel_pmu_add_event,
6669 .del = intel_pmu_del_event,
6670 .read = intel_pmu_read_event,
6671 .set_period = intel_pmu_set_period,
6672 .update = intel_pmu_update,
6673 .hw_config = intel_pmu_hw_config,
6674 .schedule_events = x86_schedule_events,
6675 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
6676 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
6677 .fixedctr = MSR_ARCH_PERFMON_FIXED_CTR0,
6678 .event_map = intel_pmu_event_map,
6679 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
6680 .apic = 1,
6681 .large_pebs_flags = LARGE_PEBS_FLAGS,
6682 /*
6683 * Intel PMCs cannot be accessed sanely above 32 bit width,
6684 * so we install an artificial 1<<31 period regardless of
6685 * the generic event period:
6686 */
6687 .max_period = (1ULL << 31) - 1,
6688 .get_event_constraints = intel_get_event_constraints,
6689 .put_event_constraints = intel_put_event_constraints,
6690 .pebs_aliases = intel_pebs_aliases_core2,
6691
6692 .format_attrs = intel_arch3_formats_attr,
6693 .events_sysfs_show = intel_event_sysfs_show,
6694
6695 .cpu_prepare = intel_pmu_cpu_prepare,
6696 .cpu_starting = intel_pmu_cpu_starting,
6697 .cpu_dying = intel_pmu_cpu_dying,
6698 .cpu_dead = intel_pmu_cpu_dead,
6699
6700 .guest_get_msrs = intel_guest_get_msrs,
6701 .sched_task = intel_pmu_sched_task,
6702
6703 .check_period = intel_pmu_check_period,
6704
6705 .aux_output_match = intel_pmu_aux_output_match,
6706
6707 .lbr_reset = intel_pmu_lbr_reset_64,
6708 .lbr_read = intel_pmu_lbr_read_64,
6709 .lbr_save = intel_pmu_lbr_save,
6710 .lbr_restore = intel_pmu_lbr_restore,
6711
6712 /*
6713 * SMM has access to all 4 rings and while traditionally SMM code only
6714 * ran in CPL0, 2021-era firmware is starting to make use of CPL3 in SMM.
6715 *
6716 * Since the EVENTSEL.{USR,OS} CPL filtering makes no distinction
6717 * between SMM or not, this results in what should be pure userspace
6718 * counters including SMM data.
6719 *
6720 * This is a clear privilege issue, therefore globally disable
6721 * counting SMM by default.
6722 */
6723 .attr_freeze_on_smi = 1,
6724 };
6725
intel_clovertown_quirk(void)6726 static __init void intel_clovertown_quirk(void)
6727 {
6728 /*
6729 * PEBS is unreliable due to:
6730 *
6731 * AJ67 - PEBS may experience CPL leaks
6732 * AJ68 - PEBS PMI may be delayed by one event
6733 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
6734 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
6735 *
6736 * AJ67 could be worked around by restricting the OS/USR flags.
6737 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
6738 *
6739 * AJ106 could possibly be worked around by not allowing LBR
6740 * usage from PEBS, including the fixup.
6741 * AJ68 could possibly be worked around by always programming
6742 * a pebs_event_reset[0] value and coping with the lost events.
6743 *
6744 * But taken together it might just make sense to not enable PEBS on
6745 * these chips.
6746 */
6747 pr_warn("PEBS disabled due to CPU errata\n");
6748 x86_pmu.ds_pebs = 0;
6749 x86_pmu.pebs_constraints = NULL;
6750 }
6751
6752 static const struct x86_cpu_id isolation_ucodes[] = {
6753 X86_MATCH_VFM_STEPS(INTEL_HASWELL, 3, 3, 0x0000001f),
6754 X86_MATCH_VFM_STEPS(INTEL_HASWELL_L, 1, 1, 0x0000001e),
6755 X86_MATCH_VFM_STEPS(INTEL_HASWELL_G, 1, 1, 0x00000015),
6756 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 2, 2, 0x00000037),
6757 X86_MATCH_VFM_STEPS(INTEL_HASWELL_X, 4, 4, 0x0000000a),
6758 X86_MATCH_VFM_STEPS(INTEL_BROADWELL, 4, 4, 0x00000023),
6759 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_G, 1, 1, 0x00000014),
6760 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 2, 2, 0x00000010),
6761 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 3, 3, 0x07000009),
6762 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 4, 4, 0x0f000009),
6763 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D, 5, 5, 0x0e000002),
6764 X86_MATCH_VFM_STEPS(INTEL_BROADWELL_X, 1, 1, 0x0b000014),
6765 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 3, 3, 0x00000021),
6766 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 4, 7, 0x00000000),
6767 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X, 11, 11, 0x00000000),
6768 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_L, 3, 3, 0x0000007c),
6769 X86_MATCH_VFM_STEPS(INTEL_SKYLAKE, 3, 3, 0x0000007c),
6770 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE, 9, 13, 0x0000004e),
6771 X86_MATCH_VFM_STEPS(INTEL_KABYLAKE_L, 9, 12, 0x0000004e),
6772 {}
6773 };
6774
intel_check_pebs_isolation(void)6775 static void intel_check_pebs_isolation(void)
6776 {
6777 x86_pmu.pebs_no_isolation = !x86_match_min_microcode_rev(isolation_ucodes);
6778 }
6779
intel_pebs_isolation_quirk(void)6780 static __init void intel_pebs_isolation_quirk(void)
6781 {
6782 WARN_ON_ONCE(x86_pmu.check_microcode);
6783 x86_pmu.check_microcode = intel_check_pebs_isolation;
6784 intel_check_pebs_isolation();
6785 }
6786
6787 static const struct x86_cpu_id pebs_ucodes[] = {
6788 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE, 7, 7, 0x00000028),
6789 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 6, 6, 0x00000618),
6790 X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X, 7, 7, 0x0000070c),
6791 {}
6792 };
6793
intel_snb_pebs_broken(void)6794 static bool intel_snb_pebs_broken(void)
6795 {
6796 return !x86_match_min_microcode_rev(pebs_ucodes);
6797 }
6798
intel_snb_check_microcode(void)6799 static void intel_snb_check_microcode(void)
6800 {
6801 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
6802 return;
6803
6804 /*
6805 * Serialized by the microcode lock..
6806 */
6807 if (x86_pmu.pebs_broken) {
6808 pr_info("PEBS enabled due to microcode update\n");
6809 x86_pmu.pebs_broken = 0;
6810 } else {
6811 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
6812 x86_pmu.pebs_broken = 1;
6813 }
6814 }
6815
is_lbr_from(unsigned long msr)6816 static bool is_lbr_from(unsigned long msr)
6817 {
6818 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
6819
6820 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
6821 }
6822
6823 /*
6824 * Under certain circumstances, access certain MSR may cause #GP.
6825 * The function tests if the input MSR can be safely accessed.
6826 */
check_msr(unsigned long msr,u64 mask)6827 static bool check_msr(unsigned long msr, u64 mask)
6828 {
6829 u64 val_old, val_new, val_tmp;
6830
6831 /*
6832 * Disable the check for real HW, so we don't
6833 * mess with potentially enabled registers:
6834 */
6835 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
6836 return true;
6837
6838 /*
6839 * Read the current value, change it and read it back to see if it
6840 * matches, this is needed to detect certain hardware emulators
6841 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
6842 */
6843 if (rdmsrq_safe(msr, &val_old))
6844 return false;
6845
6846 /*
6847 * Only change the bits which can be updated by wrmsrq.
6848 */
6849 val_tmp = val_old ^ mask;
6850
6851 if (is_lbr_from(msr))
6852 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
6853
6854 if (wrmsrq_safe(msr, val_tmp) ||
6855 rdmsrq_safe(msr, &val_new))
6856 return false;
6857
6858 /*
6859 * Quirk only affects validation in wrmsr(), so wrmsrq()'s value
6860 * should equal rdmsrq()'s even with the quirk.
6861 */
6862 if (val_new != val_tmp)
6863 return false;
6864
6865 if (is_lbr_from(msr))
6866 val_old = lbr_from_signext_quirk_wr(val_old);
6867
6868 /* Here it's sure that the MSR can be safely accessed.
6869 * Restore the old value and return.
6870 */
6871 wrmsrq(msr, val_old);
6872
6873 return true;
6874 }
6875
intel_sandybridge_quirk(void)6876 static __init void intel_sandybridge_quirk(void)
6877 {
6878 x86_pmu.check_microcode = intel_snb_check_microcode;
6879 cpus_read_lock();
6880 intel_snb_check_microcode();
6881 cpus_read_unlock();
6882 }
6883
6884 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
6885 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
6886 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
6887 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
6888 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
6889 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
6890 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
6891 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
6892 };
6893
intel_arch_events_quirk(void)6894 static __init void intel_arch_events_quirk(void)
6895 {
6896 int bit;
6897
6898 /* disable event that reported as not present by cpuid */
6899 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
6900 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
6901 pr_warn("CPUID marked event: \'%s\' unavailable\n",
6902 intel_arch_events_map[bit].name);
6903 }
6904 }
6905
intel_nehalem_quirk(void)6906 static __init void intel_nehalem_quirk(void)
6907 {
6908 union cpuid10_ebx ebx;
6909
6910 ebx.full = x86_pmu.events_maskl;
6911 if (ebx.split.no_branch_misses_retired) {
6912 /*
6913 * Erratum AAJ80 detected, we work it around by using
6914 * the BR_MISP_EXEC.ANY event. This will over-count
6915 * branch-misses, but it's still much better than the
6916 * architectural event which is often completely bogus:
6917 */
6918 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
6919 ebx.split.no_branch_misses_retired = 0;
6920 x86_pmu.events_maskl = ebx.full;
6921 pr_info("CPU erratum AAJ80 worked around\n");
6922 }
6923 }
6924
6925 /*
6926 * enable software workaround for errata:
6927 * SNB: BJ122
6928 * IVB: BV98
6929 * HSW: HSD29
6930 *
6931 * Only needed when HT is enabled. However detecting
6932 * if HT is enabled is difficult (model specific). So instead,
6933 * we enable the workaround in the early boot, and verify if
6934 * it is needed in a later initcall phase once we have valid
6935 * topology information to check if HT is actually enabled
6936 */
intel_ht_bug(void)6937 static __init void intel_ht_bug(void)
6938 {
6939 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
6940
6941 x86_pmu.start_scheduling = intel_start_scheduling;
6942 x86_pmu.commit_scheduling = intel_commit_scheduling;
6943 x86_pmu.stop_scheduling = intel_stop_scheduling;
6944 }
6945
6946 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
6947 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
6948
6949 /* Haswell special events */
6950 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
6951 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
6952 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
6953 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
6954 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
6955 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
6956 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
6957 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
6958 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
6959 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
6960 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
6961 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
6962
6963 static struct attribute *hsw_events_attrs[] = {
6964 EVENT_PTR(td_slots_issued),
6965 EVENT_PTR(td_slots_retired),
6966 EVENT_PTR(td_fetch_bubbles),
6967 EVENT_PTR(td_total_slots),
6968 EVENT_PTR(td_total_slots_scale),
6969 EVENT_PTR(td_recovery_bubbles),
6970 EVENT_PTR(td_recovery_bubbles_scale),
6971 NULL
6972 };
6973
6974 static struct attribute *hsw_mem_events_attrs[] = {
6975 EVENT_PTR(mem_ld_hsw),
6976 EVENT_PTR(mem_st_hsw),
6977 NULL,
6978 };
6979
6980 static struct attribute *hsw_tsx_events_attrs[] = {
6981 EVENT_PTR(tx_start),
6982 EVENT_PTR(tx_commit),
6983 EVENT_PTR(tx_abort),
6984 EVENT_PTR(tx_capacity),
6985 EVENT_PTR(tx_conflict),
6986 EVENT_PTR(el_start),
6987 EVENT_PTR(el_commit),
6988 EVENT_PTR(el_abort),
6989 EVENT_PTR(el_capacity),
6990 EVENT_PTR(el_conflict),
6991 EVENT_PTR(cycles_t),
6992 EVENT_PTR(cycles_ct),
6993 NULL
6994 };
6995
6996 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80");
6997 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
6998 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80");
6999 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
7000
7001 static struct attribute *icl_events_attrs[] = {
7002 EVENT_PTR(mem_ld_hsw),
7003 EVENT_PTR(mem_st_hsw),
7004 NULL,
7005 };
7006
7007 static struct attribute *icl_td_events_attrs[] = {
7008 EVENT_PTR(slots),
7009 EVENT_PTR(td_retiring),
7010 EVENT_PTR(td_bad_spec),
7011 EVENT_PTR(td_fe_bound),
7012 EVENT_PTR(td_be_bound),
7013 NULL,
7014 };
7015
7016 static struct attribute *icl_tsx_events_attrs[] = {
7017 EVENT_PTR(tx_start),
7018 EVENT_PTR(tx_abort),
7019 EVENT_PTR(tx_commit),
7020 EVENT_PTR(tx_capacity_read),
7021 EVENT_PTR(tx_capacity_write),
7022 EVENT_PTR(tx_conflict),
7023 EVENT_PTR(el_start),
7024 EVENT_PTR(el_abort),
7025 EVENT_PTR(el_commit),
7026 EVENT_PTR(el_capacity_read),
7027 EVENT_PTR(el_capacity_write),
7028 EVENT_PTR(el_conflict),
7029 EVENT_PTR(cycles_t),
7030 EVENT_PTR(cycles_ct),
7031 NULL,
7032 };
7033
7034
7035 EVENT_ATTR_STR(mem-stores, mem_st_spr, "event=0xcd,umask=0x2");
7036 EVENT_ATTR_STR(mem-loads-aux, mem_ld_aux, "event=0x03,umask=0x82");
7037
7038 static struct attribute *glc_events_attrs[] = {
7039 EVENT_PTR(mem_ld_hsw),
7040 EVENT_PTR(mem_st_spr),
7041 EVENT_PTR(mem_ld_aux),
7042 NULL,
7043 };
7044
7045 static struct attribute *glc_td_events_attrs[] = {
7046 EVENT_PTR(slots),
7047 EVENT_PTR(td_retiring),
7048 EVENT_PTR(td_bad_spec),
7049 EVENT_PTR(td_fe_bound),
7050 EVENT_PTR(td_be_bound),
7051 EVENT_PTR(td_heavy_ops),
7052 EVENT_PTR(td_br_mispredict),
7053 EVENT_PTR(td_fetch_lat),
7054 EVENT_PTR(td_mem_bound),
7055 NULL,
7056 };
7057
7058 static struct attribute *glc_tsx_events_attrs[] = {
7059 EVENT_PTR(tx_start),
7060 EVENT_PTR(tx_abort),
7061 EVENT_PTR(tx_commit),
7062 EVENT_PTR(tx_capacity_read),
7063 EVENT_PTR(tx_capacity_write),
7064 EVENT_PTR(tx_conflict),
7065 EVENT_PTR(cycles_t),
7066 EVENT_PTR(cycles_ct),
7067 NULL,
7068 };
7069
freeze_on_smi_show(struct device * cdev,struct device_attribute * attr,char * buf)7070 static ssize_t freeze_on_smi_show(struct device *cdev,
7071 struct device_attribute *attr,
7072 char *buf)
7073 {
7074 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
7075 }
7076
7077 static DEFINE_MUTEX(freeze_on_smi_mutex);
7078
freeze_on_smi_store(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)7079 static ssize_t freeze_on_smi_store(struct device *cdev,
7080 struct device_attribute *attr,
7081 const char *buf, size_t count)
7082 {
7083 unsigned long val;
7084 ssize_t ret;
7085
7086 ret = kstrtoul(buf, 0, &val);
7087 if (ret)
7088 return ret;
7089
7090 if (val > 1)
7091 return -EINVAL;
7092
7093 mutex_lock(&freeze_on_smi_mutex);
7094
7095 if (x86_pmu.attr_freeze_on_smi == val)
7096 goto done;
7097
7098 x86_pmu.attr_freeze_on_smi = val;
7099
7100 cpus_read_lock();
7101 on_each_cpu(flip_smm_bit, &val, 1);
7102 cpus_read_unlock();
7103 done:
7104 mutex_unlock(&freeze_on_smi_mutex);
7105
7106 return count;
7107 }
7108
update_tfa_sched(void * ignored)7109 static void update_tfa_sched(void *ignored)
7110 {
7111 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
7112
7113 /*
7114 * check if PMC3 is used
7115 * and if so force schedule out for all event types all contexts
7116 */
7117 if (test_bit(3, cpuc->active_mask))
7118 perf_pmu_resched(x86_get_pmu(smp_processor_id()));
7119 }
7120
show_sysctl_tfa(struct device * cdev,struct device_attribute * attr,char * buf)7121 static ssize_t show_sysctl_tfa(struct device *cdev,
7122 struct device_attribute *attr,
7123 char *buf)
7124 {
7125 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
7126 }
7127
set_sysctl_tfa(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)7128 static ssize_t set_sysctl_tfa(struct device *cdev,
7129 struct device_attribute *attr,
7130 const char *buf, size_t count)
7131 {
7132 bool val;
7133 ssize_t ret;
7134
7135 ret = kstrtobool(buf, &val);
7136 if (ret)
7137 return ret;
7138
7139 /* no change */
7140 if (val == allow_tsx_force_abort)
7141 return count;
7142
7143 allow_tsx_force_abort = val;
7144
7145 cpus_read_lock();
7146 on_each_cpu(update_tfa_sched, NULL, 1);
7147 cpus_read_unlock();
7148
7149 return count;
7150 }
7151
7152
7153 static DEVICE_ATTR_RW(freeze_on_smi);
7154
branches_show(struct device * cdev,struct device_attribute * attr,char * buf)7155 static ssize_t branches_show(struct device *cdev,
7156 struct device_attribute *attr,
7157 char *buf)
7158 {
7159 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
7160 }
7161
7162 static DEVICE_ATTR_RO(branches);
7163
branch_counter_nr_show(struct device * cdev,struct device_attribute * attr,char * buf)7164 static ssize_t branch_counter_nr_show(struct device *cdev,
7165 struct device_attribute *attr,
7166 char *buf)
7167 {
7168 return snprintf(buf, PAGE_SIZE, "%d\n", fls(x86_pmu.lbr_counters));
7169 }
7170
7171 static DEVICE_ATTR_RO(branch_counter_nr);
7172
branch_counter_width_show(struct device * cdev,struct device_attribute * attr,char * buf)7173 static ssize_t branch_counter_width_show(struct device *cdev,
7174 struct device_attribute *attr,
7175 char *buf)
7176 {
7177 return snprintf(buf, PAGE_SIZE, "%d\n", LBR_INFO_BR_CNTR_BITS);
7178 }
7179
7180 static DEVICE_ATTR_RO(branch_counter_width);
7181
7182 static struct attribute *lbr_attrs[] = {
7183 &dev_attr_branches.attr,
7184 &dev_attr_branch_counter_nr.attr,
7185 &dev_attr_branch_counter_width.attr,
7186 NULL
7187 };
7188
7189 static umode_t
lbr_is_visible(struct kobject * kobj,struct attribute * attr,int i)7190 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7191 {
7192 /* branches */
7193 if (i == 0)
7194 return x86_pmu.lbr_nr ? attr->mode : 0;
7195
7196 return (x86_pmu.flags & PMU_FL_BR_CNTR) ? attr->mode : 0;
7197 }
7198
7199 static char pmu_name_str[30];
7200
7201 static DEVICE_STRING_ATTR_RO(pmu_name, 0444, pmu_name_str);
7202
7203 static struct attribute *intel_pmu_caps_attrs[] = {
7204 &dev_attr_pmu_name.attr.attr,
7205 NULL
7206 };
7207
7208 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
7209 show_sysctl_tfa,
7210 set_sysctl_tfa);
7211
7212 static struct attribute *intel_pmu_attrs[] = {
7213 &dev_attr_freeze_on_smi.attr,
7214 &dev_attr_allow_tsx_force_abort.attr,
7215 NULL,
7216 };
7217
7218 static umode_t
default_is_visible(struct kobject * kobj,struct attribute * attr,int i)7219 default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7220 {
7221 if (attr == &dev_attr_allow_tsx_force_abort.attr)
7222 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
7223
7224 return attr->mode;
7225 }
7226
7227 static umode_t
tsx_is_visible(struct kobject * kobj,struct attribute * attr,int i)7228 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7229 {
7230 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
7231 }
7232
7233 static umode_t
pebs_is_visible(struct kobject * kobj,struct attribute * attr,int i)7234 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7235 {
7236 return intel_pmu_has_pebs() ? attr->mode : 0;
7237 }
7238
7239 static umode_t
mem_is_visible(struct kobject * kobj,struct attribute * attr,int i)7240 mem_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7241 {
7242 if (attr == &event_attr_mem_ld_aux.attr.attr)
7243 return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0;
7244
7245 return pebs_is_visible(kobj, attr, i);
7246 }
7247
7248 static umode_t
exra_is_visible(struct kobject * kobj,struct attribute * attr,int i)7249 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7250 {
7251 return x86_pmu.version >= 2 ? attr->mode : 0;
7252 }
7253
7254 static umode_t
td_is_visible(struct kobject * kobj,struct attribute * attr,int i)7255 td_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7256 {
7257 /*
7258 * Hide the perf metrics topdown events
7259 * if the feature is not enumerated.
7260 */
7261 if (x86_pmu.num_topdown_events)
7262 return x86_pmu.intel_cap.perf_metrics ? attr->mode : 0;
7263
7264 return attr->mode;
7265 }
7266
7267 PMU_FORMAT_ATTR(acr_mask, "config2:0-63");
7268
7269 static struct attribute *format_acr_attrs[] = {
7270 &format_attr_acr_mask.attr,
7271 NULL
7272 };
7273
7274 static umode_t
acr_is_visible(struct kobject * kobj,struct attribute * attr,int i)7275 acr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
7276 {
7277 struct device *dev = kobj_to_dev(kobj);
7278
7279 return intel_pmu_has_acr(dev_get_drvdata(dev)) ? attr->mode : 0;
7280 }
7281
7282 static struct attribute_group group_events_td = {
7283 .name = "events",
7284 .is_visible = td_is_visible,
7285 };
7286
7287 static struct attribute_group group_events_mem = {
7288 .name = "events",
7289 .is_visible = mem_is_visible,
7290 };
7291
7292 static struct attribute_group group_events_tsx = {
7293 .name = "events",
7294 .is_visible = tsx_is_visible,
7295 };
7296
7297 static struct attribute_group group_caps_gen = {
7298 .name = "caps",
7299 .attrs = intel_pmu_caps_attrs,
7300 };
7301
7302 static struct attribute_group group_caps_lbr = {
7303 .name = "caps",
7304 .attrs = lbr_attrs,
7305 .is_visible = lbr_is_visible,
7306 };
7307
7308 static struct attribute_group group_format_extra = {
7309 .name = "format",
7310 .is_visible = exra_is_visible,
7311 };
7312
7313 static struct attribute_group group_format_extra_skl = {
7314 .name = "format",
7315 .is_visible = exra_is_visible,
7316 };
7317
7318 static struct attribute_group group_format_evtsel_ext = {
7319 .name = "format",
7320 .attrs = format_evtsel_ext_attrs,
7321 .is_visible = evtsel_ext_is_visible,
7322 };
7323
7324 static struct attribute_group group_format_acr = {
7325 .name = "format",
7326 .attrs = format_acr_attrs,
7327 .is_visible = acr_is_visible,
7328 };
7329
7330 static struct attribute_group group_default = {
7331 .attrs = intel_pmu_attrs,
7332 .is_visible = default_is_visible,
7333 };
7334
7335 static const struct attribute_group *attr_update[] = {
7336 &group_events_td,
7337 &group_events_mem,
7338 &group_events_tsx,
7339 &group_caps_gen,
7340 &group_caps_lbr,
7341 &group_format_extra,
7342 &group_format_extra_skl,
7343 &group_format_evtsel_ext,
7344 &group_format_acr,
7345 &group_default,
7346 NULL,
7347 };
7348
7349 EVENT_ATTR_STR_HYBRID(slots, slots_adl, "event=0x00,umask=0x4", hybrid_big);
7350 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_adl, "event=0xc2,umask=0x0;event=0x00,umask=0x80", hybrid_big_small);
7351 EVENT_ATTR_STR_HYBRID(topdown-bad-spec, td_bad_spec_adl, "event=0x73,umask=0x0;event=0x00,umask=0x81", hybrid_big_small);
7352 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_adl, "event=0x71,umask=0x0;event=0x00,umask=0x82", hybrid_big_small);
7353 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_adl, "event=0x74,umask=0x0;event=0x00,umask=0x83", hybrid_big_small);
7354 EVENT_ATTR_STR_HYBRID(topdown-heavy-ops, td_heavy_ops_adl, "event=0x00,umask=0x84", hybrid_big);
7355 EVENT_ATTR_STR_HYBRID(topdown-br-mispredict, td_br_mis_adl, "event=0x00,umask=0x85", hybrid_big);
7356 EVENT_ATTR_STR_HYBRID(topdown-fetch-lat, td_fetch_lat_adl, "event=0x00,umask=0x86", hybrid_big);
7357 EVENT_ATTR_STR_HYBRID(topdown-mem-bound, td_mem_bound_adl, "event=0x00,umask=0x87", hybrid_big);
7358
7359 static struct attribute *adl_hybrid_events_attrs[] = {
7360 EVENT_PTR(slots_adl),
7361 EVENT_PTR(td_retiring_adl),
7362 EVENT_PTR(td_bad_spec_adl),
7363 EVENT_PTR(td_fe_bound_adl),
7364 EVENT_PTR(td_be_bound_adl),
7365 EVENT_PTR(td_heavy_ops_adl),
7366 EVENT_PTR(td_br_mis_adl),
7367 EVENT_PTR(td_fetch_lat_adl),
7368 EVENT_PTR(td_mem_bound_adl),
7369 NULL,
7370 };
7371
7372 EVENT_ATTR_STR_HYBRID(topdown-retiring, td_retiring_lnl, "event=0xc2,umask=0x02;event=0x00,umask=0x80", hybrid_big_small);
7373 EVENT_ATTR_STR_HYBRID(topdown-fe-bound, td_fe_bound_lnl, "event=0x9c,umask=0x01;event=0x00,umask=0x82", hybrid_big_small);
7374 EVENT_ATTR_STR_HYBRID(topdown-be-bound, td_be_bound_lnl, "event=0xa4,umask=0x02;event=0x00,umask=0x83", hybrid_big_small);
7375
7376 static struct attribute *lnl_hybrid_events_attrs[] = {
7377 EVENT_PTR(slots_adl),
7378 EVENT_PTR(td_retiring_lnl),
7379 EVENT_PTR(td_bad_spec_adl),
7380 EVENT_PTR(td_fe_bound_lnl),
7381 EVENT_PTR(td_be_bound_lnl),
7382 EVENT_PTR(td_heavy_ops_adl),
7383 EVENT_PTR(td_br_mis_adl),
7384 EVENT_PTR(td_fetch_lat_adl),
7385 EVENT_PTR(td_mem_bound_adl),
7386 NULL
7387 };
7388
7389 /* The event string must be in PMU IDX order. */
7390 EVENT_ATTR_STR_HYBRID(topdown-retiring,
7391 td_retiring_arl_h,
7392 "event=0xc2,umask=0x02;event=0x00,umask=0x80;event=0xc2,umask=0x0",
7393 hybrid_big_small_tiny);
7394 EVENT_ATTR_STR_HYBRID(topdown-bad-spec,
7395 td_bad_spec_arl_h,
7396 "event=0x73,umask=0x0;event=0x00,umask=0x81;event=0x73,umask=0x0",
7397 hybrid_big_small_tiny);
7398 EVENT_ATTR_STR_HYBRID(topdown-fe-bound,
7399 td_fe_bound_arl_h,
7400 "event=0x9c,umask=0x01;event=0x00,umask=0x82;event=0x71,umask=0x0",
7401 hybrid_big_small_tiny);
7402 EVENT_ATTR_STR_HYBRID(topdown-be-bound,
7403 td_be_bound_arl_h,
7404 "event=0xa4,umask=0x02;event=0x00,umask=0x83;event=0x74,umask=0x0",
7405 hybrid_big_small_tiny);
7406
7407 static struct attribute *arl_h_hybrid_events_attrs[] = {
7408 EVENT_PTR(slots_adl),
7409 EVENT_PTR(td_retiring_arl_h),
7410 EVENT_PTR(td_bad_spec_arl_h),
7411 EVENT_PTR(td_fe_bound_arl_h),
7412 EVENT_PTR(td_be_bound_arl_h),
7413 EVENT_PTR(td_heavy_ops_adl),
7414 EVENT_PTR(td_br_mis_adl),
7415 EVENT_PTR(td_fetch_lat_adl),
7416 EVENT_PTR(td_mem_bound_adl),
7417 NULL,
7418 };
7419
7420 /* Must be in IDX order */
7421 EVENT_ATTR_STR_HYBRID(mem-loads, mem_ld_adl, "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3", hybrid_big_small);
7422 EVENT_ATTR_STR_HYBRID(mem-stores, mem_st_adl, "event=0xd0,umask=0x6;event=0xcd,umask=0x2", hybrid_big_small);
7423 EVENT_ATTR_STR_HYBRID(mem-loads-aux, mem_ld_aux_adl, "event=0x03,umask=0x82", hybrid_big);
7424
7425 static struct attribute *adl_hybrid_mem_attrs[] = {
7426 EVENT_PTR(mem_ld_adl),
7427 EVENT_PTR(mem_st_adl),
7428 EVENT_PTR(mem_ld_aux_adl),
7429 NULL,
7430 };
7431
7432 static struct attribute *mtl_hybrid_mem_attrs[] = {
7433 EVENT_PTR(mem_ld_adl),
7434 EVENT_PTR(mem_st_adl),
7435 NULL
7436 };
7437
7438 EVENT_ATTR_STR_HYBRID(mem-loads,
7439 mem_ld_arl_h,
7440 "event=0xd0,umask=0x5,ldlat=3;event=0xcd,umask=0x1,ldlat=3;event=0xd0,umask=0x5,ldlat=3",
7441 hybrid_big_small_tiny);
7442 EVENT_ATTR_STR_HYBRID(mem-stores,
7443 mem_st_arl_h,
7444 "event=0xd0,umask=0x6;event=0xcd,umask=0x2;event=0xd0,umask=0x6",
7445 hybrid_big_small_tiny);
7446
7447 static struct attribute *arl_h_hybrid_mem_attrs[] = {
7448 EVENT_PTR(mem_ld_arl_h),
7449 EVENT_PTR(mem_st_arl_h),
7450 NULL,
7451 };
7452
7453 EVENT_ATTR_STR_HYBRID(tx-start, tx_start_adl, "event=0xc9,umask=0x1", hybrid_big);
7454 EVENT_ATTR_STR_HYBRID(tx-commit, tx_commit_adl, "event=0xc9,umask=0x2", hybrid_big);
7455 EVENT_ATTR_STR_HYBRID(tx-abort, tx_abort_adl, "event=0xc9,umask=0x4", hybrid_big);
7456 EVENT_ATTR_STR_HYBRID(tx-conflict, tx_conflict_adl, "event=0x54,umask=0x1", hybrid_big);
7457 EVENT_ATTR_STR_HYBRID(cycles-t, cycles_t_adl, "event=0x3c,in_tx=1", hybrid_big);
7458 EVENT_ATTR_STR_HYBRID(cycles-ct, cycles_ct_adl, "event=0x3c,in_tx=1,in_tx_cp=1", hybrid_big);
7459 EVENT_ATTR_STR_HYBRID(tx-capacity-read, tx_capacity_read_adl, "event=0x54,umask=0x80", hybrid_big);
7460 EVENT_ATTR_STR_HYBRID(tx-capacity-write, tx_capacity_write_adl, "event=0x54,umask=0x2", hybrid_big);
7461
7462 static struct attribute *adl_hybrid_tsx_attrs[] = {
7463 EVENT_PTR(tx_start_adl),
7464 EVENT_PTR(tx_abort_adl),
7465 EVENT_PTR(tx_commit_adl),
7466 EVENT_PTR(tx_capacity_read_adl),
7467 EVENT_PTR(tx_capacity_write_adl),
7468 EVENT_PTR(tx_conflict_adl),
7469 EVENT_PTR(cycles_t_adl),
7470 EVENT_PTR(cycles_ct_adl),
7471 NULL,
7472 };
7473
7474 FORMAT_ATTR_HYBRID(in_tx, hybrid_big);
7475 FORMAT_ATTR_HYBRID(in_tx_cp, hybrid_big);
7476 FORMAT_ATTR_HYBRID(offcore_rsp, hybrid_big_small_tiny);
7477 FORMAT_ATTR_HYBRID(ldlat, hybrid_big_small_tiny);
7478 FORMAT_ATTR_HYBRID(frontend, hybrid_big);
7479
7480 #define ADL_HYBRID_RTM_FORMAT_ATTR \
7481 FORMAT_HYBRID_PTR(in_tx), \
7482 FORMAT_HYBRID_PTR(in_tx_cp)
7483
7484 #define ADL_HYBRID_FORMAT_ATTR \
7485 FORMAT_HYBRID_PTR(offcore_rsp), \
7486 FORMAT_HYBRID_PTR(ldlat), \
7487 FORMAT_HYBRID_PTR(frontend)
7488
7489 static struct attribute *adl_hybrid_extra_attr_rtm[] = {
7490 ADL_HYBRID_RTM_FORMAT_ATTR,
7491 ADL_HYBRID_FORMAT_ATTR,
7492 NULL
7493 };
7494
7495 static struct attribute *adl_hybrid_extra_attr[] = {
7496 ADL_HYBRID_FORMAT_ATTR,
7497 NULL
7498 };
7499
7500 FORMAT_ATTR_HYBRID(snoop_rsp, hybrid_small_tiny);
7501
7502 static struct attribute *mtl_hybrid_extra_attr_rtm[] = {
7503 ADL_HYBRID_RTM_FORMAT_ATTR,
7504 ADL_HYBRID_FORMAT_ATTR,
7505 FORMAT_HYBRID_PTR(snoop_rsp),
7506 NULL
7507 };
7508
7509 static struct attribute *mtl_hybrid_extra_attr[] = {
7510 ADL_HYBRID_FORMAT_ATTR,
7511 FORMAT_HYBRID_PTR(snoop_rsp),
7512 NULL
7513 };
7514
is_attr_for_this_pmu(struct kobject * kobj,struct attribute * attr)7515 static bool is_attr_for_this_pmu(struct kobject *kobj, struct attribute *attr)
7516 {
7517 struct device *dev = kobj_to_dev(kobj);
7518 struct x86_hybrid_pmu *pmu =
7519 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
7520 struct perf_pmu_events_hybrid_attr *pmu_attr =
7521 container_of(attr, struct perf_pmu_events_hybrid_attr, attr.attr);
7522
7523 return pmu->pmu_type & pmu_attr->pmu_type;
7524 }
7525
hybrid_events_is_visible(struct kobject * kobj,struct attribute * attr,int i)7526 static umode_t hybrid_events_is_visible(struct kobject *kobj,
7527 struct attribute *attr, int i)
7528 {
7529 return is_attr_for_this_pmu(kobj, attr) ? attr->mode : 0;
7530 }
7531
hybrid_find_supported_cpu(struct x86_hybrid_pmu * pmu)7532 static inline int hybrid_find_supported_cpu(struct x86_hybrid_pmu *pmu)
7533 {
7534 int cpu = cpumask_first(&pmu->supported_cpus);
7535
7536 return (cpu >= nr_cpu_ids) ? -1 : cpu;
7537 }
7538
hybrid_tsx_is_visible(struct kobject * kobj,struct attribute * attr,int i)7539 static umode_t hybrid_tsx_is_visible(struct kobject *kobj,
7540 struct attribute *attr, int i)
7541 {
7542 struct device *dev = kobj_to_dev(kobj);
7543 struct x86_hybrid_pmu *pmu =
7544 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
7545 int cpu = hybrid_find_supported_cpu(pmu);
7546
7547 return (cpu >= 0) && is_attr_for_this_pmu(kobj, attr) && cpu_has(&cpu_data(cpu), X86_FEATURE_RTM) ? attr->mode : 0;
7548 }
7549
hybrid_format_is_visible(struct kobject * kobj,struct attribute * attr,int i)7550 static umode_t hybrid_format_is_visible(struct kobject *kobj,
7551 struct attribute *attr, int i)
7552 {
7553 struct device *dev = kobj_to_dev(kobj);
7554 struct x86_hybrid_pmu *pmu =
7555 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
7556 struct perf_pmu_format_hybrid_attr *pmu_attr =
7557 container_of(attr, struct perf_pmu_format_hybrid_attr, attr.attr);
7558 int cpu = hybrid_find_supported_cpu(pmu);
7559
7560 return (cpu >= 0) && (pmu->pmu_type & pmu_attr->pmu_type) ? attr->mode : 0;
7561 }
7562
hybrid_td_is_visible(struct kobject * kobj,struct attribute * attr,int i)7563 static umode_t hybrid_td_is_visible(struct kobject *kobj,
7564 struct attribute *attr, int i)
7565 {
7566 struct device *dev = kobj_to_dev(kobj);
7567 struct x86_hybrid_pmu *pmu =
7568 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
7569
7570 if (!is_attr_for_this_pmu(kobj, attr))
7571 return 0;
7572
7573
7574 /* Only the big core supports perf metrics */
7575 if (pmu->pmu_type == hybrid_big)
7576 return pmu->intel_cap.perf_metrics ? attr->mode : 0;
7577
7578 return attr->mode;
7579 }
7580
7581 static struct attribute_group hybrid_group_events_td = {
7582 .name = "events",
7583 .is_visible = hybrid_td_is_visible,
7584 };
7585
7586 static struct attribute_group hybrid_group_events_mem = {
7587 .name = "events",
7588 .is_visible = hybrid_events_is_visible,
7589 };
7590
7591 static struct attribute_group hybrid_group_events_tsx = {
7592 .name = "events",
7593 .is_visible = hybrid_tsx_is_visible,
7594 };
7595
7596 static struct attribute_group hybrid_group_format_extra = {
7597 .name = "format",
7598 .is_visible = hybrid_format_is_visible,
7599 };
7600
intel_hybrid_get_attr_cpus(struct device * dev,struct device_attribute * attr,char * buf)7601 static ssize_t intel_hybrid_get_attr_cpus(struct device *dev,
7602 struct device_attribute *attr,
7603 char *buf)
7604 {
7605 struct x86_hybrid_pmu *pmu =
7606 container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu);
7607
7608 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(&pmu->supported_cpus));
7609 }
7610
7611 static DEVICE_ATTR(cpus, S_IRUGO, intel_hybrid_get_attr_cpus, NULL);
7612 static struct attribute *intel_hybrid_cpus_attrs[] = {
7613 &dev_attr_cpus.attr,
7614 NULL,
7615 };
7616
7617 static struct attribute_group hybrid_group_cpus = {
7618 .attrs = intel_hybrid_cpus_attrs,
7619 };
7620
7621 static const struct attribute_group *hybrid_attr_update[] = {
7622 &hybrid_group_events_td,
7623 &hybrid_group_events_mem,
7624 &hybrid_group_events_tsx,
7625 &group_caps_gen,
7626 &group_caps_lbr,
7627 &hybrid_group_format_extra,
7628 &group_format_evtsel_ext,
7629 &group_format_acr,
7630 &group_default,
7631 &hybrid_group_cpus,
7632 NULL,
7633 };
7634
7635 static struct attribute *empty_attrs;
7636
intel_pmu_check_event_constraints(struct event_constraint * event_constraints,u64 cntr_mask,u64 fixed_cntr_mask,u64 intel_ctrl)7637 static void intel_pmu_check_event_constraints(struct event_constraint *event_constraints,
7638 u64 cntr_mask,
7639 u64 fixed_cntr_mask,
7640 u64 intel_ctrl)
7641 {
7642 struct event_constraint *c;
7643
7644 if (!event_constraints)
7645 return;
7646
7647 /*
7648 * event on fixed counter2 (REF_CYCLES) only works on this
7649 * counter, so do not extend mask to generic counters
7650 */
7651 for_each_event_constraint(c, event_constraints) {
7652 /*
7653 * Don't extend the topdown slots and metrics
7654 * events to the generic counters.
7655 */
7656 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) {
7657 /*
7658 * Disable topdown slots and metrics events,
7659 * if slots event is not in CPUID.
7660 */
7661 if (!(INTEL_PMC_MSK_FIXED_SLOTS & intel_ctrl))
7662 c->idxmsk64 = 0;
7663 c->weight = hweight64(c->idxmsk64);
7664 continue;
7665 }
7666
7667 if (c->cmask == FIXED_EVENT_FLAGS) {
7668 /* Disabled fixed counters which are not in CPUID */
7669 c->idxmsk64 &= intel_ctrl;
7670
7671 /*
7672 * Don't extend the pseudo-encoding to the
7673 * generic counters
7674 */
7675 if (!use_fixed_pseudo_encoding(c->code))
7676 c->idxmsk64 |= cntr_mask;
7677 }
7678 c->idxmsk64 &= cntr_mask | (fixed_cntr_mask << INTEL_PMC_IDX_FIXED);
7679 c->weight = hweight64(c->idxmsk64);
7680 }
7681 }
7682
intel_pmu_check_extra_regs(struct extra_reg * extra_regs)7683 static void intel_pmu_check_extra_regs(struct extra_reg *extra_regs)
7684 {
7685 struct extra_reg *er;
7686
7687 /*
7688 * Access extra MSR may cause #GP under certain circumstances.
7689 * E.g. KVM doesn't support offcore event
7690 * Check all extra_regs here.
7691 */
7692 if (!extra_regs)
7693 return;
7694
7695 for (er = extra_regs; er->msr; er++) {
7696 er->extra_msr_access = check_msr(er->msr, 0x11UL);
7697 /* Disable LBR select mapping */
7698 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
7699 x86_pmu.lbr_sel_map = NULL;
7700 }
7701 }
7702
intel_pmu_v6_addr_offset(int index,bool eventsel)7703 static inline int intel_pmu_v6_addr_offset(int index, bool eventsel)
7704 {
7705 return MSR_IA32_PMC_V6_STEP * index;
7706 }
7707
7708 static const struct { enum hybrid_pmu_type id; char *name; } intel_hybrid_pmu_type_map[] __initconst = {
7709 { hybrid_small, "cpu_atom" },
7710 { hybrid_big, "cpu_core" },
7711 { hybrid_tiny, "cpu_lowpower" },
7712 };
7713
intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)7714 static __always_inline int intel_pmu_init_hybrid(enum hybrid_pmu_type pmus)
7715 {
7716 unsigned long pmus_mask = pmus;
7717 struct x86_hybrid_pmu *pmu;
7718 int idx = 0, bit;
7719
7720 x86_pmu.num_hybrid_pmus = hweight_long(pmus_mask);
7721 x86_pmu.hybrid_pmu = kzalloc_objs(struct x86_hybrid_pmu,
7722 x86_pmu.num_hybrid_pmus);
7723 if (!x86_pmu.hybrid_pmu) {
7724 x86_pmu.num_hybrid_pmus = 0;
7725 return -ENOMEM;
7726 }
7727
7728 static_branch_enable(&perf_is_hybrid);
7729 x86_pmu.filter = intel_pmu_filter;
7730
7731 for_each_set_bit(bit, &pmus_mask, ARRAY_SIZE(intel_hybrid_pmu_type_map)) {
7732 pmu = &x86_pmu.hybrid_pmu[idx++];
7733 pmu->pmu_type = intel_hybrid_pmu_type_map[bit].id;
7734 pmu->name = intel_hybrid_pmu_type_map[bit].name;
7735
7736 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
7737 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
7738 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
7739 pmu->config_mask = X86_RAW_EVENT_MASK;
7740 pmu->unconstrained = (struct event_constraint)
7741 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
7742 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
7743
7744 pmu->intel_cap.capabilities = x86_pmu.intel_cap.capabilities;
7745 if (pmu->pmu_type & hybrid_small_tiny) {
7746 pmu->intel_cap.perf_metrics = 0;
7747 pmu->mid_ack = true;
7748 } else if (pmu->pmu_type & hybrid_big) {
7749 pmu->intel_cap.perf_metrics = 1;
7750 pmu->late_ack = true;
7751 }
7752 }
7753
7754 return 0;
7755 }
7756
intel_pmu_ref_cycles_ext(void)7757 static __always_inline void intel_pmu_ref_cycles_ext(void)
7758 {
7759 if (!(x86_pmu.events_maskl & (INTEL_PMC_MSK_FIXED_REF_CYCLES >> INTEL_PMC_IDX_FIXED)))
7760 intel_perfmon_event_map[PERF_COUNT_HW_REF_CPU_CYCLES] = 0x013c;
7761 }
7762
intel_pmu_init_glc(struct pmu * pmu)7763 static __always_inline void intel_pmu_init_glc(struct pmu *pmu)
7764 {
7765 x86_pmu.late_ack = true;
7766 x86_pmu.limit_period = glc_limit_period;
7767 x86_pmu.pebs_aliases = NULL;
7768 x86_pmu.pebs_prec_dist = true;
7769 x86_pmu.pebs_block = true;
7770 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7771 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
7772 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
7773 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
7774 x86_pmu.lbr_pt_coexist = true;
7775 x86_pmu.num_topdown_events = 8;
7776 static_call_update(intel_pmu_update_topdown_event,
7777 &icl_update_topdown_event);
7778 static_call_update(intel_pmu_set_topdown_event_period,
7779 &icl_set_topdown_event_period);
7780
7781 memcpy(hybrid_var(pmu, hw_cache_event_ids), glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7782 memcpy(hybrid_var(pmu, hw_cache_extra_regs), glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7783 hybrid(pmu, event_constraints) = intel_glc_event_constraints;
7784 hybrid(pmu, pebs_constraints) = intel_glc_pebs_event_constraints;
7785
7786 intel_pmu_ref_cycles_ext();
7787 }
7788
intel_pmu_init_glc_hybrid(struct pmu * pmu)7789 static __always_inline void intel_pmu_init_glc_hybrid(struct pmu *pmu)
7790 {
7791 intel_pmu_init_glc(pmu);
7792
7793 /* ADL has different extra MSR values from Server for the L3 or node OCR/OMR events. */
7794 memcpy(hybrid_var(pmu, hw_cache_event_ids), adl_glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7795 memcpy(hybrid_var(pmu, hw_cache_extra_regs), adl_glc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7796 }
7797
intel_pmu_init_grt(struct pmu * pmu)7798 static __always_inline void intel_pmu_init_grt(struct pmu *pmu)
7799 {
7800 x86_pmu.mid_ack = true;
7801 x86_pmu.limit_period = glc_limit_period;
7802 x86_pmu.pebs_aliases = NULL;
7803 x86_pmu.pebs_prec_dist = true;
7804 x86_pmu.pebs_block = true;
7805 x86_pmu.lbr_pt_coexist = true;
7806 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
7807 x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
7808
7809 memcpy(hybrid_var(pmu, hw_cache_event_ids), glp_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7810 memcpy(hybrid_var(pmu, hw_cache_extra_regs), grt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7811 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
7812 hybrid(pmu, event_constraints) = intel_grt_event_constraints;
7813 hybrid(pmu, pebs_constraints) = intel_grt_pebs_event_constraints;
7814 hybrid(pmu, extra_regs) = intel_grt_extra_regs;
7815
7816 intel_pmu_ref_cycles_ext();
7817 }
7818
intel_pmu_init_cmt(struct pmu * pmu)7819 static __always_inline void intel_pmu_init_cmt(struct pmu *pmu)
7820 {
7821 intel_pmu_init_grt(pmu);
7822 memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7823 cmt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7824 hybrid(pmu, pebs_constraints) = intel_cmt_pebs_event_constraints;
7825 hybrid(pmu, extra_regs) = intel_cmt_extra_regs;
7826 }
7827
intel_pmu_init_lnc(struct pmu * pmu)7828 static __always_inline void intel_pmu_init_lnc(struct pmu *pmu)
7829 {
7830 intel_pmu_init_glc(pmu);
7831 hybrid(pmu, event_constraints) = intel_lnc_event_constraints;
7832 hybrid(pmu, pebs_constraints) = intel_lnc_pebs_event_constraints;
7833 hybrid(pmu, extra_regs) = intel_lnc_extra_regs;
7834
7835 memcpy(hybrid_var(pmu, hw_cache_event_ids), adl_glc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7836 memcpy(hybrid_var(pmu, hw_cache_extra_regs), lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7837 }
7838
intel_pmu_init_pnc(struct pmu * pmu)7839 static __always_inline void intel_pmu_init_pnc(struct pmu *pmu)
7840 {
7841 intel_pmu_init_glc(pmu);
7842 x86_pmu.flags &= ~PMU_FL_HAS_RSP_1;
7843 x86_pmu.flags |= PMU_FL_HAS_OMR;
7844 memcpy(hybrid_var(pmu, hw_cache_event_ids),
7845 pnc_hw_cache_event_ids, sizeof(hw_cache_event_ids));
7846 memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7847 pnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7848 hybrid(pmu, event_constraints) = intel_pnc_event_constraints;
7849 hybrid(pmu, pebs_constraints) = intel_pnc_pebs_event_constraints;
7850 hybrid(pmu, extra_regs) = intel_pnc_extra_regs;
7851 static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
7852 }
7853
intel_pmu_init_cyc(struct pmu * pmu)7854 static __always_inline void intel_pmu_init_cyc(struct pmu *pmu)
7855 {
7856 intel_pmu_init_pnc(pmu);
7857 memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7858 cyc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7859 }
7860
intel_pmu_init_skt(struct pmu * pmu)7861 static __always_inline void intel_pmu_init_skt(struct pmu *pmu)
7862 {
7863 intel_pmu_init_cmt(pmu);
7864 hybrid(pmu, event_constraints) = intel_skt_event_constraints;
7865 memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7866 skt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7867 static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
7868 }
7869
7870 /* Hybrid client variant. */
intel_pmu_init_dkt_hybrid(struct pmu * pmu)7871 static __always_inline void intel_pmu_init_dkt_hybrid(struct pmu *pmu)
7872 {
7873 intel_pmu_init_skt(pmu);
7874 hybrid(pmu, pebs_constraints) = intel_dkt_pebs_event_constraints;
7875 }
7876
7877 /*
7878 * Darkmont is used by the CWF and PTL E-cores, but their L3 OCR
7879 * events require different extra MSR values. Keep a separate init
7880 * function for the non-hybrid server variant.
7881 */
intel_pmu_init_dkt(struct pmu * pmu)7882 static __always_inline void intel_pmu_init_dkt(struct pmu *pmu)
7883 {
7884 intel_pmu_init_dkt_hybrid(pmu);
7885 memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7886 dkt_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7887 }
7888
intel_pmu_init_arw(struct pmu * pmu)7889 static __always_inline void intel_pmu_init_arw(struct pmu *pmu)
7890 {
7891 intel_pmu_init_grt(pmu);
7892 x86_pmu.flags &= ~PMU_FL_HAS_RSP_1;
7893 x86_pmu.flags |= PMU_FL_HAS_OMR;
7894 memcpy(hybrid_var(pmu, hw_cache_extra_regs),
7895 arw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
7896 hybrid(pmu, event_constraints) = intel_arw_event_constraints;
7897 hybrid(pmu, pebs_constraints) = intel_dkt_pebs_event_constraints;
7898 hybrid(pmu, extra_regs) = intel_arw_extra_regs;
7899 static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
7900 }
7901
intel_pmu_init(void)7902 __init int intel_pmu_init(void)
7903 {
7904 struct attribute **extra_skl_attr = &empty_attrs;
7905 struct attribute **extra_attr = &empty_attrs;
7906 struct attribute **td_attr = &empty_attrs;
7907 struct attribute **mem_attr = &empty_attrs;
7908 struct attribute **tsx_attr = &empty_attrs;
7909 struct x86_hybrid_pmu *pmu;
7910 unsigned int fixed_mask;
7911 union cpuid10_edx edx;
7912 union cpuid10_eax eax;
7913 union cpuid10_ebx ebx;
7914 int version, i, ret;
7915 bool pmem = false;
7916 char *name;
7917
7918 /* Architectural Perfmon was introduced starting with Core "Yonah" */
7919 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
7920 switch (boot_cpu_data.x86) {
7921 case 6:
7922 if (boot_cpu_data.x86_vfm < INTEL_CORE_YONAH)
7923 return p6_pmu_init();
7924 break;
7925 case 11:
7926 return knc_pmu_init();
7927 case 15:
7928 return p4_pmu_init();
7929 }
7930
7931 pr_cont("unsupported CPU family %d model %d ",
7932 boot_cpu_data.x86, boot_cpu_data.x86_model);
7933 return -ENODEV;
7934 }
7935
7936 /*
7937 * Check whether the Architectural PerfMon supports
7938 * Branch Misses Retired hw_event or not.
7939 */
7940 cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full);
7941 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
7942 return -ENODEV;
7943
7944 version = eax.split.version_id;
7945 if (version < 2)
7946 x86_pmu = core_pmu;
7947 else
7948 x86_pmu = intel_pmu;
7949
7950 x86_pmu.version = version;
7951 x86_pmu.cntr_mask64 = GENMASK_ULL(eax.split.num_counters - 1, 0);
7952 x86_pmu.cntval_bits = eax.split.bit_width;
7953 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
7954
7955 x86_pmu.events_maskl = ebx.full;
7956 x86_pmu.events_mask_len = eax.split.mask_length;
7957
7958 x86_pmu.pebs_events_mask = intel_pmu_pebs_mask(x86_pmu.cntr_mask64);
7959 x86_pmu.pebs_capable = PEBS_COUNTER_MASK;
7960 x86_pmu.config_mask = X86_RAW_EVENT_MASK;
7961
7962 /*
7963 * Quirk: v2 perfmon does not report fixed-purpose events, so
7964 * assume at least 3 events, when not running in a hypervisor:
7965 */
7966 if (version > 1 && version < 5) {
7967 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
7968
7969 x86_pmu.fixed_cntr_mask64 =
7970 GENMASK_ULL(max((int)edx.split.num_counters_fixed, assume) - 1, 0);
7971 } else if (version >= 5)
7972 x86_pmu.fixed_cntr_mask64 = fixed_mask;
7973
7974 if (boot_cpu_has(X86_FEATURE_PDCM)) {
7975 u64 capabilities;
7976
7977 rdmsrq(MSR_IA32_PERF_CAPABILITIES, capabilities);
7978 x86_pmu.intel_cap.capabilities = capabilities;
7979 }
7980
7981 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
7982 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
7983 x86_pmu.lbr_read = intel_pmu_lbr_read_32;
7984 }
7985
7986 intel_pebs_init();
7987
7988 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
7989
7990 /* The perf side of core PMU is ready to support the mediated vPMU. */
7991 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_MEDIATED_VPMU;
7992
7993 /*
7994 * Many features on and after V6 require dynamic constraint,
7995 * e.g., Arch PEBS, ACR.
7996 */
7997 if (version >= 6) {
7998 x86_pmu.flags |= PMU_FL_DYN_CONSTRAINT;
7999 x86_pmu.late_setup = intel_pmu_late_setup;
8000 }
8001
8002 /*
8003 * Install the hw-cache-events table:
8004 */
8005 switch (boot_cpu_data.x86_vfm) {
8006 case INTEL_CORE_YONAH:
8007 pr_cont("Core events, ");
8008 name = "core";
8009 break;
8010
8011 case INTEL_CORE2_MEROM:
8012 x86_add_quirk(intel_clovertown_quirk);
8013 fallthrough;
8014
8015 case INTEL_CORE2_MEROM_L:
8016 case INTEL_CORE2_PENRYN:
8017 case INTEL_CORE2_DUNNINGTON:
8018 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
8019 sizeof(hw_cache_event_ids));
8020
8021 intel_pmu_lbr_init_core();
8022
8023 x86_pmu.event_constraints = intel_core2_event_constraints;
8024 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
8025 pr_cont("Core2 events, ");
8026 name = "core2";
8027 break;
8028
8029 case INTEL_NEHALEM:
8030 case INTEL_NEHALEM_EP:
8031 case INTEL_NEHALEM_EX:
8032 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
8033 sizeof(hw_cache_event_ids));
8034 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
8035 sizeof(hw_cache_extra_regs));
8036
8037 intel_pmu_lbr_init_nhm();
8038
8039 x86_pmu.event_constraints = intel_nehalem_event_constraints;
8040 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
8041 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
8042 x86_pmu.extra_regs = intel_nehalem_extra_regs;
8043 x86_pmu.limit_period = nhm_limit_period;
8044
8045 mem_attr = nhm_mem_events_attrs;
8046
8047 /* UOPS_ISSUED.STALLED_CYCLES */
8048 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
8049 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
8050 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
8051 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
8052 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
8053
8054 intel_pmu_pebs_data_source_nhm();
8055 x86_add_quirk(intel_nehalem_quirk);
8056 x86_pmu.pebs_no_tlb = 1;
8057 extra_attr = nhm_format_attr;
8058
8059 pr_cont("Nehalem events, ");
8060 name = "nehalem";
8061 break;
8062
8063 case INTEL_ATOM_BONNELL:
8064 case INTEL_ATOM_BONNELL_MID:
8065 case INTEL_ATOM_SALTWELL:
8066 case INTEL_ATOM_SALTWELL_MID:
8067 case INTEL_ATOM_SALTWELL_TABLET:
8068 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
8069 sizeof(hw_cache_event_ids));
8070
8071 intel_pmu_lbr_init_atom();
8072
8073 x86_pmu.event_constraints = intel_gen_event_constraints;
8074 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
8075 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
8076 pr_cont("Atom events, ");
8077 name = "bonnell";
8078 break;
8079
8080 case INTEL_ATOM_SILVERMONT:
8081 case INTEL_ATOM_SILVERMONT_D:
8082 case INTEL_ATOM_SILVERMONT_MID:
8083 case INTEL_ATOM_AIRMONT:
8084 case INTEL_ATOM_AIRMONT_NP:
8085 case INTEL_ATOM_SILVERMONT_MID2:
8086 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
8087 sizeof(hw_cache_event_ids));
8088 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
8089 sizeof(hw_cache_extra_regs));
8090
8091 intel_pmu_lbr_init_slm();
8092
8093 x86_pmu.event_constraints = intel_slm_event_constraints;
8094 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
8095 x86_pmu.extra_regs = intel_slm_extra_regs;
8096 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8097 td_attr = slm_events_attrs;
8098 extra_attr = slm_format_attr;
8099 pr_cont("Silvermont events, ");
8100 name = "silvermont";
8101 break;
8102
8103 case INTEL_ATOM_GOLDMONT:
8104 case INTEL_ATOM_GOLDMONT_D:
8105 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
8106 sizeof(hw_cache_event_ids));
8107 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
8108 sizeof(hw_cache_extra_regs));
8109
8110 intel_pmu_lbr_init_skl();
8111
8112 x86_pmu.event_constraints = intel_slm_event_constraints;
8113 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
8114 x86_pmu.extra_regs = intel_glm_extra_regs;
8115 /*
8116 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
8117 * for precise cycles.
8118 * :pp is identical to :ppp
8119 */
8120 x86_pmu.pebs_aliases = NULL;
8121 x86_pmu.pebs_prec_dist = true;
8122 x86_pmu.lbr_pt_coexist = true;
8123 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8124 td_attr = glm_events_attrs;
8125 extra_attr = slm_format_attr;
8126 pr_cont("Goldmont events, ");
8127 name = "goldmont";
8128 break;
8129
8130 case INTEL_ATOM_GOLDMONT_PLUS:
8131 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
8132 sizeof(hw_cache_event_ids));
8133 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
8134 sizeof(hw_cache_extra_regs));
8135
8136 intel_pmu_lbr_init_skl();
8137
8138 x86_pmu.event_constraints = intel_slm_event_constraints;
8139 x86_pmu.extra_regs = intel_glm_extra_regs;
8140 /*
8141 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
8142 * for precise cycles.
8143 */
8144 x86_pmu.pebs_aliases = NULL;
8145 x86_pmu.pebs_prec_dist = true;
8146 x86_pmu.lbr_pt_coexist = true;
8147 x86_pmu.pebs_capable = ~0ULL;
8148 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8149 x86_pmu.flags |= PMU_FL_PEBS_ALL;
8150 x86_pmu.get_event_constraints = glp_get_event_constraints;
8151 td_attr = glm_events_attrs;
8152 /* Goldmont Plus has 4-wide pipeline */
8153 event_attr_td_total_slots_scale_glm.event_str = "4";
8154 extra_attr = slm_format_attr;
8155 pr_cont("Goldmont plus events, ");
8156 name = "goldmont_plus";
8157 break;
8158
8159 case INTEL_ATOM_TREMONT_D:
8160 case INTEL_ATOM_TREMONT:
8161 case INTEL_ATOM_TREMONT_L:
8162 x86_pmu.late_ack = true;
8163 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
8164 sizeof(hw_cache_event_ids));
8165 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
8166 sizeof(hw_cache_extra_regs));
8167 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
8168
8169 intel_pmu_lbr_init_skl();
8170
8171 x86_pmu.event_constraints = intel_slm_event_constraints;
8172 x86_pmu.extra_regs = intel_tnt_extra_regs;
8173 /*
8174 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
8175 * for precise cycles.
8176 */
8177 x86_pmu.pebs_aliases = NULL;
8178 x86_pmu.pebs_prec_dist = true;
8179 x86_pmu.lbr_pt_coexist = true;
8180 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8181 x86_pmu.get_event_constraints = tnt_get_event_constraints;
8182 td_attr = tnt_events_attrs;
8183 extra_attr = slm_format_attr;
8184 pr_cont("Tremont events, ");
8185 name = "Tremont";
8186 break;
8187
8188 case INTEL_ATOM_GRACEMONT:
8189 intel_pmu_init_grt(NULL);
8190 intel_pmu_pebs_data_source_grt();
8191 x86_pmu.pebs_latency_data = grt_latency_data;
8192 x86_pmu.get_event_constraints = tnt_get_event_constraints;
8193 td_attr = tnt_events_attrs;
8194 mem_attr = grt_mem_attrs;
8195 extra_attr = nhm_format_attr;
8196 pr_cont("Gracemont events, ");
8197 name = "gracemont";
8198 break;
8199
8200 case INTEL_ATOM_CRESTMONT:
8201 case INTEL_ATOM_CRESTMONT_X:
8202 intel_pmu_init_cmt(NULL);
8203 intel_pmu_pebs_data_source_cmt();
8204 x86_pmu.pebs_latency_data = cmt_latency_data;
8205 x86_pmu.get_event_constraints = cmt_get_event_constraints;
8206 td_attr = cmt_events_attrs;
8207 mem_attr = grt_mem_attrs;
8208 extra_attr = cmt_format_attr;
8209 pr_cont("Crestmont events, ");
8210 name = "crestmont";
8211 break;
8212
8213 case INTEL_ATOM_DARKMONT_X:
8214 intel_pmu_init_dkt(NULL);
8215 intel_pmu_pebs_data_source_cmt();
8216 x86_pmu.pebs_latency_data = cmt_latency_data;
8217 x86_pmu.get_event_constraints = cmt_get_event_constraints;
8218 td_attr = skt_events_attrs;
8219 mem_attr = grt_mem_attrs;
8220 extra_attr = cmt_format_attr;
8221 pr_cont("Darkmont events, ");
8222 name = "darkmont";
8223 break;
8224
8225 case INTEL_WESTMERE:
8226 case INTEL_WESTMERE_EP:
8227 case INTEL_WESTMERE_EX:
8228 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
8229 sizeof(hw_cache_event_ids));
8230 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
8231 sizeof(hw_cache_extra_regs));
8232
8233 intel_pmu_lbr_init_nhm();
8234
8235 x86_pmu.event_constraints = intel_westmere_event_constraints;
8236 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
8237 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
8238 x86_pmu.extra_regs = intel_westmere_extra_regs;
8239 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8240
8241 mem_attr = nhm_mem_events_attrs;
8242
8243 /* UOPS_ISSUED.STALLED_CYCLES */
8244 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
8245 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
8246 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
8247 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
8248 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
8249
8250 intel_pmu_pebs_data_source_nhm();
8251 extra_attr = nhm_format_attr;
8252 pr_cont("Westmere events, ");
8253 name = "westmere";
8254 break;
8255
8256 case INTEL_SANDYBRIDGE:
8257 case INTEL_SANDYBRIDGE_X:
8258 x86_add_quirk(intel_sandybridge_quirk);
8259 x86_add_quirk(intel_ht_bug);
8260 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
8261 sizeof(hw_cache_event_ids));
8262 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
8263 sizeof(hw_cache_extra_regs));
8264
8265 intel_pmu_lbr_init_snb();
8266
8267 x86_pmu.event_constraints = intel_snb_event_constraints;
8268 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
8269 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
8270 if (boot_cpu_data.x86_vfm == INTEL_SANDYBRIDGE_X)
8271 x86_pmu.extra_regs = intel_snbep_extra_regs;
8272 else
8273 x86_pmu.extra_regs = intel_snb_extra_regs;
8274
8275
8276 /* all extra regs are per-cpu when HT is on */
8277 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8278 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8279
8280 td_attr = snb_events_attrs;
8281 mem_attr = snb_mem_events_attrs;
8282
8283 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
8284 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
8285 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
8286 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
8287 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
8288 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
8289
8290 extra_attr = nhm_format_attr;
8291
8292 pr_cont("SandyBridge events, ");
8293 name = "sandybridge";
8294 break;
8295
8296 case INTEL_IVYBRIDGE:
8297 case INTEL_IVYBRIDGE_X:
8298 x86_add_quirk(intel_ht_bug);
8299 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
8300 sizeof(hw_cache_event_ids));
8301 /* dTLB-load-misses on IVB is different than SNB */
8302 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
8303
8304 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
8305 sizeof(hw_cache_extra_regs));
8306
8307 intel_pmu_lbr_init_snb();
8308
8309 x86_pmu.event_constraints = intel_ivb_event_constraints;
8310 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
8311 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
8312 x86_pmu.pebs_prec_dist = true;
8313 if (boot_cpu_data.x86_vfm == INTEL_IVYBRIDGE_X)
8314 x86_pmu.extra_regs = intel_snbep_extra_regs;
8315 else
8316 x86_pmu.extra_regs = intel_snb_extra_regs;
8317 /* all extra regs are per-cpu when HT is on */
8318 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8319 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8320
8321 td_attr = snb_events_attrs;
8322 mem_attr = snb_mem_events_attrs;
8323
8324 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
8325 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
8326 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
8327
8328 extra_attr = nhm_format_attr;
8329
8330 pr_cont("IvyBridge events, ");
8331 name = "ivybridge";
8332 break;
8333
8334
8335 case INTEL_HASWELL:
8336 case INTEL_HASWELL_X:
8337 case INTEL_HASWELL_L:
8338 case INTEL_HASWELL_G:
8339 x86_add_quirk(intel_ht_bug);
8340 x86_add_quirk(intel_pebs_isolation_quirk);
8341 x86_pmu.late_ack = true;
8342 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
8343 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8344
8345 intel_pmu_lbr_init_hsw();
8346
8347 x86_pmu.event_constraints = intel_hsw_event_constraints;
8348 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
8349 x86_pmu.extra_regs = intel_snbep_extra_regs;
8350 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
8351 x86_pmu.pebs_prec_dist = true;
8352 /* all extra regs are per-cpu when HT is on */
8353 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8354 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8355
8356 x86_pmu.hw_config = hsw_hw_config;
8357 x86_pmu.get_event_constraints = hsw_get_event_constraints;
8358 x86_pmu.limit_period = hsw_limit_period;
8359 x86_pmu.lbr_double_abort = true;
8360 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8361 hsw_format_attr : nhm_format_attr;
8362 td_attr = hsw_events_attrs;
8363 mem_attr = hsw_mem_events_attrs;
8364 tsx_attr = hsw_tsx_events_attrs;
8365 pr_cont("Haswell events, ");
8366 name = "haswell";
8367 break;
8368
8369 case INTEL_BROADWELL:
8370 case INTEL_BROADWELL_D:
8371 case INTEL_BROADWELL_G:
8372 case INTEL_BROADWELL_X:
8373 x86_add_quirk(intel_pebs_isolation_quirk);
8374 x86_pmu.late_ack = true;
8375 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
8376 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8377
8378 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
8379 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
8380 BDW_L3_MISS|HSW_SNOOP_DRAM;
8381 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
8382 HSW_SNOOP_DRAM;
8383 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
8384 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
8385 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
8386 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
8387
8388 intel_pmu_lbr_init_hsw();
8389
8390 x86_pmu.event_constraints = intel_bdw_event_constraints;
8391 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
8392 x86_pmu.extra_regs = intel_snbep_extra_regs;
8393 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
8394 x86_pmu.pebs_prec_dist = true;
8395 /* all extra regs are per-cpu when HT is on */
8396 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8397 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8398
8399 x86_pmu.hw_config = hsw_hw_config;
8400 x86_pmu.get_event_constraints = hsw_get_event_constraints;
8401 x86_pmu.limit_period = bdw_limit_period;
8402 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8403 hsw_format_attr : nhm_format_attr;
8404 td_attr = hsw_events_attrs;
8405 mem_attr = hsw_mem_events_attrs;
8406 tsx_attr = hsw_tsx_events_attrs;
8407 pr_cont("Broadwell events, ");
8408 name = "broadwell";
8409 break;
8410
8411 case INTEL_XEON_PHI_KNL:
8412 case INTEL_XEON_PHI_KNM:
8413 memcpy(hw_cache_event_ids,
8414 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
8415 memcpy(hw_cache_extra_regs,
8416 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8417 intel_pmu_lbr_init_knl();
8418
8419 x86_pmu.event_constraints = intel_slm_event_constraints;
8420 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
8421 x86_pmu.extra_regs = intel_knl_extra_regs;
8422
8423 /* all extra regs are per-cpu when HT is on */
8424 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8425 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8426 extra_attr = slm_format_attr;
8427 pr_cont("Knights Landing/Mill events, ");
8428 name = "knights-landing";
8429 break;
8430
8431 case INTEL_SKYLAKE_X:
8432 pmem = true;
8433 fallthrough;
8434 case INTEL_SKYLAKE_L:
8435 case INTEL_SKYLAKE:
8436 case INTEL_KABYLAKE_L:
8437 case INTEL_KABYLAKE:
8438 case INTEL_COMETLAKE_L:
8439 case INTEL_COMETLAKE:
8440 x86_add_quirk(intel_pebs_isolation_quirk);
8441 x86_pmu.late_ack = true;
8442 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
8443 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8444 intel_pmu_lbr_init_skl();
8445
8446 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
8447 event_attr_td_recovery_bubbles.event_str_noht =
8448 "event=0xd,umask=0x1,cmask=1";
8449 event_attr_td_recovery_bubbles.event_str_ht =
8450 "event=0xd,umask=0x1,cmask=1,any=1";
8451
8452 x86_pmu.event_constraints = intel_skl_event_constraints;
8453 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
8454 x86_pmu.extra_regs = intel_skl_extra_regs;
8455 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
8456 x86_pmu.pebs_prec_dist = true;
8457 /* all extra regs are per-cpu when HT is on */
8458 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8459 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8460
8461 x86_pmu.hw_config = hsw_hw_config;
8462 x86_pmu.get_event_constraints = hsw_get_event_constraints;
8463 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8464 hsw_format_attr : nhm_format_attr;
8465 extra_skl_attr = skl_format_attr;
8466 td_attr = hsw_events_attrs;
8467 mem_attr = hsw_mem_events_attrs;
8468 tsx_attr = hsw_tsx_events_attrs;
8469 intel_pmu_pebs_data_source_skl(pmem);
8470
8471 /*
8472 * Processors with CPUID.RTM_ALWAYS_ABORT have TSX deprecated by default.
8473 * TSX force abort hooks are not required on these systems. Only deploy
8474 * workaround when microcode has not enabled X86_FEATURE_RTM_ALWAYS_ABORT.
8475 */
8476 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) &&
8477 !boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT)) {
8478 x86_pmu.flags |= PMU_FL_TFA;
8479 x86_pmu.get_event_constraints = tfa_get_event_constraints;
8480 x86_pmu.enable_all = intel_tfa_pmu_enable_all;
8481 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
8482 }
8483
8484 pr_cont("Skylake events, ");
8485 name = "skylake";
8486 break;
8487
8488 case INTEL_ICELAKE_X:
8489 case INTEL_ICELAKE_D:
8490 memcpy(hw_cache_extra_regs, snc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8491 x86_pmu.pebs_ept = 1;
8492 pmem = true;
8493 goto snc_common;
8494 case INTEL_ICELAKE_L:
8495 case INTEL_ICELAKE:
8496 case INTEL_TIGERLAKE_L:
8497 case INTEL_TIGERLAKE:
8498 case INTEL_ROCKETLAKE:
8499 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8500 snc_common:
8501 x86_pmu.late_ack = true;
8502 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
8503 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
8504 intel_pmu_lbr_init_skl();
8505
8506 x86_pmu.event_constraints = intel_icl_event_constraints;
8507 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
8508 x86_pmu.extra_regs = intel_icl_extra_regs;
8509 x86_pmu.pebs_aliases = NULL;
8510 x86_pmu.pebs_prec_dist = true;
8511 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
8512 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
8513
8514 x86_pmu.hw_config = hsw_hw_config;
8515 x86_pmu.get_event_constraints = icl_get_event_constraints;
8516 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8517 hsw_format_attr : nhm_format_attr;
8518 extra_skl_attr = skl_format_attr;
8519 mem_attr = icl_events_attrs;
8520 td_attr = icl_td_events_attrs;
8521 tsx_attr = icl_tsx_events_attrs;
8522 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xc9, .umask=0x04);
8523 x86_pmu.lbr_pt_coexist = true;
8524 intel_pmu_pebs_data_source_skl(pmem);
8525 x86_pmu.num_topdown_events = 4;
8526 static_call_update(intel_pmu_update_topdown_event,
8527 &icl_update_topdown_event);
8528 static_call_update(intel_pmu_set_topdown_event_period,
8529 &icl_set_topdown_event_period);
8530 pr_cont("Icelake events, ");
8531 name = "icelake";
8532 break;
8533
8534 case INTEL_SAPPHIRERAPIDS_X:
8535 case INTEL_EMERALDRAPIDS_X:
8536 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
8537 x86_pmu.extra_regs = intel_glc_extra_regs;
8538 pr_cont("Sapphire Rapids events, ");
8539 name = "sapphire_rapids";
8540 goto glc_common;
8541
8542 case INTEL_GRANITERAPIDS_X:
8543 case INTEL_GRANITERAPIDS_D:
8544 x86_pmu.extra_regs = intel_rwc_extra_regs;
8545 pr_cont("Granite Rapids events, ");
8546 name = "granite_rapids";
8547 goto glc_common;
8548
8549 case INTEL_DIAMONDRAPIDS_X:
8550 intel_pmu_init_pnc(NULL);
8551 x86_pmu.pebs_latency_data = pnc_latency_data;
8552
8553 pr_cont("Panthercove events, ");
8554 name = "panthercove";
8555 goto glc_base;
8556
8557 glc_common:
8558 intel_pmu_init_glc(NULL);
8559 intel_pmu_pebs_data_source_skl(true);
8560
8561 glc_base:
8562 x86_pmu.pebs_ept = 1;
8563 x86_pmu.hw_config = hsw_hw_config;
8564 x86_pmu.get_event_constraints = glc_get_event_constraints;
8565 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8566 hsw_format_attr : nhm_format_attr;
8567 extra_skl_attr = skl_format_attr;
8568 mem_attr = glc_events_attrs;
8569 td_attr = glc_td_events_attrs;
8570 tsx_attr = glc_tsx_events_attrs;
8571 break;
8572
8573 case INTEL_ALDERLAKE:
8574 case INTEL_ALDERLAKE_L:
8575 case INTEL_RAPTORLAKE:
8576 case INTEL_RAPTORLAKE_P:
8577 case INTEL_RAPTORLAKE_S:
8578 /*
8579 * Alder Lake has 2 types of CPU, core and atom.
8580 *
8581 * Initialize the common PerfMon capabilities here.
8582 */
8583 ret = intel_pmu_init_hybrid(hybrid_big_small);
8584 if (ret)
8585 return ret;
8586
8587 x86_pmu.pebs_latency_data = grt_latency_data;
8588 x86_pmu.get_event_constraints = adl_get_event_constraints;
8589 x86_pmu.hw_config = adl_hw_config;
8590 x86_pmu.get_hybrid_cpu_type = adl_get_hybrid_cpu_type;
8591
8592 td_attr = adl_hybrid_events_attrs;
8593 mem_attr = adl_hybrid_mem_attrs;
8594 tsx_attr = adl_hybrid_tsx_attrs;
8595 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8596 adl_hybrid_extra_attr_rtm : adl_hybrid_extra_attr;
8597
8598 /* Initialize big core specific PerfMon capabilities.*/
8599 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8600 intel_pmu_init_glc_hybrid(&pmu->pmu);
8601 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) {
8602 pmu->cntr_mask64 <<= 2;
8603 pmu->cntr_mask64 |= 0x3;
8604 pmu->fixed_cntr_mask64 <<= 1;
8605 pmu->fixed_cntr_mask64 |= 0x1;
8606 } else {
8607 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
8608 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
8609 }
8610
8611 /*
8612 * Quirk: For some Alder Lake machine, when all E-cores are disabled in
8613 * a BIOS, the leaf 0xA will enumerate all counters of P-cores. However,
8614 * the X86_FEATURE_HYBRID_CPU is still set. The above codes will
8615 * mistakenly add extra counters for P-cores. Correct the number of
8616 * counters here.
8617 */
8618 if ((x86_pmu_num_counters(&pmu->pmu) > 8) || (x86_pmu_num_counters_fixed(&pmu->pmu) > 4)) {
8619 pmu->cntr_mask64 = x86_pmu.cntr_mask64;
8620 pmu->fixed_cntr_mask64 = x86_pmu.fixed_cntr_mask64;
8621 }
8622
8623 pmu->pebs_events_mask = intel_pmu_pebs_mask(pmu->cntr_mask64);
8624 pmu->unconstrained = (struct event_constraint)
8625 __EVENT_CONSTRAINT(0, pmu->cntr_mask64,
8626 0, x86_pmu_num_counters(&pmu->pmu), 0, 0);
8627
8628 pmu->extra_regs = intel_glc_extra_regs;
8629
8630 /* Initialize Atom core specific PerfMon capabilities.*/
8631 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8632 intel_pmu_init_grt(&pmu->pmu);
8633
8634 x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
8635 intel_pmu_pebs_data_source_adl();
8636 pr_cont("Alderlake Hybrid events, ");
8637 name = "alderlake_hybrid";
8638 break;
8639
8640 case INTEL_METEORLAKE:
8641 case INTEL_METEORLAKE_L:
8642 case INTEL_ARROWLAKE_U:
8643 ret = intel_pmu_init_hybrid(hybrid_big_small);
8644 if (ret)
8645 return ret;
8646
8647 x86_pmu.pebs_latency_data = cmt_latency_data;
8648 x86_pmu.get_event_constraints = mtl_get_event_constraints;
8649 x86_pmu.hw_config = adl_hw_config;
8650
8651 td_attr = adl_hybrid_events_attrs;
8652 mem_attr = mtl_hybrid_mem_attrs;
8653 tsx_attr = adl_hybrid_tsx_attrs;
8654 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8655 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
8656
8657 /* Initialize big core specific PerfMon capabilities.*/
8658 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8659 intel_pmu_init_glc_hybrid(&pmu->pmu);
8660 pmu->extra_regs = intel_rwc_extra_regs;
8661
8662 /* Initialize Atom core specific PerfMon capabilities.*/
8663 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8664 intel_pmu_init_cmt(&pmu->pmu);
8665
8666 intel_pmu_pebs_data_source_mtl();
8667 pr_cont("Meteorlake Hybrid events, ");
8668 name = "meteorlake_hybrid";
8669 break;
8670
8671 case INTEL_PANTHERLAKE_L:
8672 case INTEL_WILDCATLAKE_L:
8673 pr_cont("Pantherlake Hybrid events, ");
8674 name = "pantherlake_hybrid";
8675
8676 ret = intel_pmu_init_hybrid(hybrid_big_small);
8677 if (ret)
8678 return ret;
8679
8680 /* Initialize big core specific PerfMon capabilities.*/
8681 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8682 intel_pmu_init_lnc(&pmu->pmu);
8683 /* Initialize Atom core specific PerfMon capabilities.*/
8684 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8685 intel_pmu_init_dkt_hybrid(&pmu->pmu);
8686
8687 goto lnl_common;
8688
8689 case INTEL_ARROWLAKE:
8690 pr_cont("Arrowlake Hybrid events, ");
8691 name = "arrowlake_hybrid";
8692
8693 ret = intel_pmu_init_hybrid(hybrid_big_small);
8694 if (ret)
8695 return ret;
8696
8697 /* Initialize big core specific PerfMon capabilities.*/
8698 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8699 intel_pmu_init_lnc(&pmu->pmu);
8700 memcpy(hybrid_var(&pmu->pmu, hw_cache_extra_regs),
8701 arl_lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8702 /* Initialize Atom core specific PerfMon capabilities.*/
8703 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8704 intel_pmu_init_skt(&pmu->pmu);
8705
8706 goto lnl_common;
8707
8708 case INTEL_LUNARLAKE_M:
8709 pr_cont("Lunarlake Hybrid events, ");
8710 name = "lunarlake_hybrid";
8711
8712 ret = intel_pmu_init_hybrid(hybrid_big_small);
8713 if (ret)
8714 return ret;
8715
8716 /* Initialize big core specific PerfMon capabilities.*/
8717 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8718 intel_pmu_init_lnc(&pmu->pmu);
8719 /* Initialize Atom core specific PerfMon capabilities.*/
8720 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8721 intel_pmu_init_skt(&pmu->pmu);
8722
8723 lnl_common:
8724
8725 x86_pmu.pebs_latency_data = lnl_latency_data;
8726 x86_pmu.get_event_constraints = mtl_get_event_constraints;
8727 x86_pmu.hw_config = adl_hw_config;
8728
8729 td_attr = lnl_hybrid_events_attrs;
8730 mem_attr = mtl_hybrid_mem_attrs;
8731 tsx_attr = adl_hybrid_tsx_attrs;
8732 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8733 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
8734
8735 intel_pmu_pebs_data_source_lnl();
8736 break;
8737
8738 case INTEL_ARROWLAKE_H:
8739 ret = intel_pmu_init_hybrid(hybrid_big_small_tiny);
8740 if (ret)
8741 return ret;
8742
8743 x86_pmu.pebs_latency_data = arl_h_latency_data;
8744 x86_pmu.get_event_constraints = arl_h_get_event_constraints;
8745 x86_pmu.hw_config = arl_h_hw_config;
8746
8747 td_attr = arl_h_hybrid_events_attrs;
8748 mem_attr = arl_h_hybrid_mem_attrs;
8749 tsx_attr = adl_hybrid_tsx_attrs;
8750 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8751 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
8752
8753 /* Initialize big core specific PerfMon capabilities. */
8754 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8755 intel_pmu_init_lnc(&pmu->pmu);
8756 memcpy(hybrid_var(&pmu->pmu, hw_cache_extra_regs),
8757 arl_lnc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
8758
8759 /* Initialize Atom core specific PerfMon capabilities. */
8760 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8761 intel_pmu_init_skt(&pmu->pmu);
8762
8763 /* Initialize Lower Power Atom specific PerfMon capabilities. */
8764 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_TINY_IDX];
8765 intel_pmu_init_cmt(&pmu->pmu);
8766
8767 intel_pmu_pebs_data_source_arl_h();
8768 pr_cont("ArrowLake-H Hybrid events, ");
8769 name = "arrowlake_h_hybrid";
8770 break;
8771
8772 case INTEL_NOVALAKE:
8773 case INTEL_NOVALAKE_L:
8774 pr_cont("Novalake Hybrid events, ");
8775 name = "novalake_hybrid";
8776 ret = intel_pmu_init_hybrid(hybrid_big_small);
8777 if (ret)
8778 return ret;
8779
8780 x86_pmu.pebs_latency_data = nvl_latency_data;
8781 x86_pmu.get_event_constraints = mtl_get_event_constraints;
8782 x86_pmu.hw_config = adl_hw_config;
8783
8784 td_attr = lnl_hybrid_events_attrs;
8785 mem_attr = mtl_hybrid_mem_attrs;
8786 tsx_attr = adl_hybrid_tsx_attrs;
8787 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
8788 mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
8789
8790 /* Initialize big core specific PerfMon capabilities.*/
8791 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
8792 intel_pmu_init_cyc(&pmu->pmu);
8793
8794 /* Initialize Atom core specific PerfMon capabilities.*/
8795 pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];
8796 intel_pmu_init_arw(&pmu->pmu);
8797
8798 intel_pmu_pebs_data_source_lnl();
8799 break;
8800
8801 default:
8802 switch (x86_pmu.version) {
8803 case 1:
8804 x86_pmu.event_constraints = intel_v1_event_constraints;
8805 pr_cont("generic architected perfmon v1, ");
8806 name = "generic_arch_v1";
8807 break;
8808 case 2:
8809 case 3:
8810 case 4:
8811 /*
8812 * default constraints for v2 and up
8813 */
8814 x86_pmu.event_constraints = intel_gen_event_constraints;
8815 pr_cont("generic architected perfmon, ");
8816 name = "generic_arch_v2+";
8817 break;
8818 default:
8819 /*
8820 * The default constraints for v5 and up can support up to
8821 * 16 fixed counters. For the fixed counters 4 and later,
8822 * the pseudo-encoding is applied.
8823 * The constraints may be cut according to the CPUID enumeration
8824 * by inserting the EVENT_CONSTRAINT_END.
8825 */
8826 if (fls64(x86_pmu.fixed_cntr_mask64) > INTEL_PMC_MAX_FIXED)
8827 x86_pmu.fixed_cntr_mask64 &= GENMASK_ULL(INTEL_PMC_MAX_FIXED - 1, 0);
8828 intel_v5_gen_event_constraints[fls64(x86_pmu.fixed_cntr_mask64)].weight = -1;
8829 x86_pmu.event_constraints = intel_v5_gen_event_constraints;
8830 pr_cont("generic architected perfmon, ");
8831 name = "generic_arch_v5+";
8832 break;
8833 }
8834 }
8835
8836 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
8837
8838 if (!is_hybrid()) {
8839 group_events_td.attrs = td_attr;
8840 group_events_mem.attrs = mem_attr;
8841 group_events_tsx.attrs = tsx_attr;
8842 group_format_extra.attrs = extra_attr;
8843 group_format_extra_skl.attrs = extra_skl_attr;
8844
8845 x86_pmu.attr_update = attr_update;
8846 } else {
8847 hybrid_group_events_td.attrs = td_attr;
8848 hybrid_group_events_mem.attrs = mem_attr;
8849 hybrid_group_events_tsx.attrs = tsx_attr;
8850 hybrid_group_format_extra.attrs = extra_attr;
8851
8852 x86_pmu.attr_update = hybrid_attr_update;
8853 }
8854
8855 /*
8856 * The archPerfmonExt (0x23) includes an enhanced enumeration of
8857 * PMU architectural features with a per-core view. For non-hybrid,
8858 * each core has the same PMU capabilities. It's good enough to
8859 * update the x86_pmu from the booting CPU. For hybrid, the x86_pmu
8860 * is used to keep the common capabilities. Still keep the values
8861 * from the leaf 0xa. The core specific update will be done later
8862 * when a new type is online.
8863 */
8864 if (!is_hybrid())
8865 intel_update_pmu_caps(NULL);
8866
8867 if (x86_pmu.arch_pebs) {
8868 static_call_update(intel_pmu_disable_event_ext,
8869 intel_pmu_disable_event_ext);
8870 static_call_update(intel_pmu_enable_event_ext,
8871 intel_pmu_enable_event_ext);
8872 pr_cont("Architectural PEBS, ");
8873 }
8874
8875 intel_pmu_check_counters_mask(&x86_pmu.cntr_mask64,
8876 &x86_pmu.fixed_cntr_mask64,
8877 &x86_pmu.intel_ctrl);
8878
8879 /* AnyThread may be deprecated on arch perfmon v5 or later */
8880 if (version >= 5 && edx.split.anythread_deprecated) {
8881 x86_pmu.format_attrs = intel_arch_formats_attr;
8882 pr_cont("AnyThread deprecated, ");
8883 }
8884
8885 if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
8886 intel_pmu_arch_lbr_init();
8887
8888 intel_pmu_check_event_constraints_all(NULL);
8889
8890 /*
8891 * Access LBR MSR may cause #GP under certain circumstances.
8892 * Check all LBR MSR here.
8893 * Disable LBR access if any LBR MSRs can not be accessed.
8894 */
8895 if (x86_pmu.lbr_tos && !check_msr(x86_pmu.lbr_tos, 0x3UL))
8896 x86_pmu.lbr_nr = 0;
8897 for (i = 0; i < x86_pmu.lbr_nr; i++) {
8898 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
8899 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
8900 x86_pmu.lbr_nr = 0;
8901 }
8902
8903 if (x86_pmu.lbr_nr) {
8904 intel_pmu_lbr_init();
8905
8906 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
8907
8908 /* only support branch_stack snapshot for perfmon >= v2 */
8909 if (x86_pmu.disable_all == intel_pmu_disable_all) {
8910 if (boot_cpu_has(X86_FEATURE_ARCH_LBR)) {
8911 static_call_update(perf_snapshot_branch_stack,
8912 intel_pmu_snapshot_arch_branch_stack);
8913 } else {
8914 static_call_update(perf_snapshot_branch_stack,
8915 intel_pmu_snapshot_branch_stack);
8916 }
8917 }
8918 }
8919
8920 intel_pmu_check_extra_regs(x86_pmu.extra_regs);
8921
8922 /* Support full width counters using alternative MSR range */
8923 if (x86_pmu.intel_cap.full_width_write) {
8924 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
8925 x86_pmu.perfctr = MSR_IA32_PMC0;
8926 pr_cont("full-width counters, ");
8927 }
8928
8929 /* Support V6+ MSR Aliasing */
8930 if (x86_pmu.version >= 6) {
8931 x86_pmu.perfctr = MSR_IA32_PMC_V6_GP0_CTR;
8932 x86_pmu.eventsel = MSR_IA32_PMC_V6_GP0_CFG_A;
8933 x86_pmu.fixedctr = MSR_IA32_PMC_V6_FX0_CTR;
8934 x86_pmu.addr_offset = intel_pmu_v6_addr_offset;
8935 }
8936
8937 if (!is_hybrid() && x86_pmu.intel_cap.perf_metrics)
8938 x86_pmu.intel_ctrl |= GLOBAL_CTRL_EN_PERF_METRICS;
8939
8940 if (x86_pmu.intel_cap.pebs_timing_info)
8941 x86_pmu.flags |= PMU_FL_RETIRE_LATENCY;
8942
8943 intel_aux_output_init();
8944
8945 return 0;
8946 }
8947
8948 /*
8949 * HT bug: phase 2 init
8950 * Called once we have valid topology information to check
8951 * whether or not HT is enabled
8952 * If HT is off, then we disable the workaround
8953 */
fixup_ht_bug(void)8954 static __init int fixup_ht_bug(void)
8955 {
8956 int c;
8957 /*
8958 * problem not present on this CPU model, nothing to do
8959 */
8960 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
8961 return 0;
8962
8963 if (topology_max_smt_threads() > 1) {
8964 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
8965 return 0;
8966 }
8967
8968 cpus_read_lock();
8969
8970 hardlockup_detector_perf_stop();
8971
8972 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
8973
8974 x86_pmu.start_scheduling = NULL;
8975 x86_pmu.commit_scheduling = NULL;
8976 x86_pmu.stop_scheduling = NULL;
8977
8978 hardlockup_detector_perf_restart();
8979
8980 for_each_online_cpu(c)
8981 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
8982
8983 cpus_read_unlock();
8984 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
8985 return 0;
8986 }
8987 subsys_initcall(fixup_ht_bug)
8988