1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2020-2023 Loongson Technology Corporation Limited
4 */
5
6 #include <linux/err.h>
7 #include <linux/module.h>
8 #include <linux/mod_devicetable.h>
9 #include <linux/kvm_host.h>
10 #include <asm/cacheflush.h>
11 #include <asm/cpufeature.h>
12 #include <asm/kvm_csr.h>
13 #include <asm/kvm_eiointc.h>
14 #include <asm/kvm_pch_pic.h>
15 #include "trace.h"
16
17 unsigned long vpid_mask;
18 struct kvm_world_switch *kvm_loongarch_ops;
19 static int gcsr_flag[CSR_MAX_NUMS];
20 static struct kvm_context __percpu *vmcs;
21
get_gcsr_flag(int csr)22 int get_gcsr_flag(int csr)
23 {
24 if (csr < CSR_MAX_NUMS)
25 return gcsr_flag[csr];
26
27 return INVALID_GCSR;
28 }
29
set_gcsr_sw_flag(int csr)30 static inline void set_gcsr_sw_flag(int csr)
31 {
32 if (csr < CSR_MAX_NUMS)
33 gcsr_flag[csr] |= SW_GCSR;
34 }
35
set_gcsr_hw_flag(int csr)36 static inline void set_gcsr_hw_flag(int csr)
37 {
38 if (csr < CSR_MAX_NUMS)
39 gcsr_flag[csr] |= HW_GCSR;
40 }
41
42 /*
43 * The default value of gcsr_flag[CSR] is 0, and we use this
44 * function to set the flag to 1 (SW_GCSR) or 2 (HW_GCSR) if the
45 * gcsr is software or hardware. It will be used by get/set_gcsr,
46 * if gcsr_flag is HW we should use gcsrrd/gcsrwr to access it,
47 * else use software csr to emulate it.
48 */
kvm_init_gcsr_flag(void)49 static void kvm_init_gcsr_flag(void)
50 {
51 set_gcsr_hw_flag(LOONGARCH_CSR_CRMD);
52 set_gcsr_hw_flag(LOONGARCH_CSR_PRMD);
53 set_gcsr_hw_flag(LOONGARCH_CSR_EUEN);
54 set_gcsr_hw_flag(LOONGARCH_CSR_MISC);
55 set_gcsr_hw_flag(LOONGARCH_CSR_ECFG);
56 set_gcsr_hw_flag(LOONGARCH_CSR_ESTAT);
57 set_gcsr_hw_flag(LOONGARCH_CSR_ERA);
58 set_gcsr_hw_flag(LOONGARCH_CSR_BADV);
59 set_gcsr_hw_flag(LOONGARCH_CSR_BADI);
60 set_gcsr_hw_flag(LOONGARCH_CSR_EENTRY);
61 set_gcsr_hw_flag(LOONGARCH_CSR_TLBIDX);
62 set_gcsr_hw_flag(LOONGARCH_CSR_TLBEHI);
63 set_gcsr_hw_flag(LOONGARCH_CSR_TLBELO0);
64 set_gcsr_hw_flag(LOONGARCH_CSR_TLBELO1);
65 set_gcsr_hw_flag(LOONGARCH_CSR_ASID);
66 set_gcsr_hw_flag(LOONGARCH_CSR_PGDL);
67 set_gcsr_hw_flag(LOONGARCH_CSR_PGDH);
68 set_gcsr_hw_flag(LOONGARCH_CSR_PGD);
69 set_gcsr_hw_flag(LOONGARCH_CSR_PWCTL0);
70 set_gcsr_hw_flag(LOONGARCH_CSR_PWCTL1);
71 set_gcsr_hw_flag(LOONGARCH_CSR_STLBPGSIZE);
72 set_gcsr_hw_flag(LOONGARCH_CSR_RVACFG);
73 set_gcsr_hw_flag(LOONGARCH_CSR_CPUID);
74 set_gcsr_hw_flag(LOONGARCH_CSR_PRCFG1);
75 set_gcsr_hw_flag(LOONGARCH_CSR_PRCFG2);
76 set_gcsr_hw_flag(LOONGARCH_CSR_PRCFG3);
77 set_gcsr_hw_flag(LOONGARCH_CSR_KS0);
78 set_gcsr_hw_flag(LOONGARCH_CSR_KS1);
79 set_gcsr_hw_flag(LOONGARCH_CSR_KS2);
80 set_gcsr_hw_flag(LOONGARCH_CSR_KS3);
81 set_gcsr_hw_flag(LOONGARCH_CSR_KS4);
82 set_gcsr_hw_flag(LOONGARCH_CSR_KS5);
83 set_gcsr_hw_flag(LOONGARCH_CSR_KS6);
84 set_gcsr_hw_flag(LOONGARCH_CSR_KS7);
85 set_gcsr_hw_flag(LOONGARCH_CSR_TMID);
86 set_gcsr_hw_flag(LOONGARCH_CSR_TCFG);
87 set_gcsr_hw_flag(LOONGARCH_CSR_TVAL);
88 set_gcsr_hw_flag(LOONGARCH_CSR_TINTCLR);
89 set_gcsr_hw_flag(LOONGARCH_CSR_CNTC);
90 set_gcsr_hw_flag(LOONGARCH_CSR_LLBCTL);
91 set_gcsr_hw_flag(LOONGARCH_CSR_TLBRENTRY);
92 set_gcsr_hw_flag(LOONGARCH_CSR_TLBRBADV);
93 set_gcsr_hw_flag(LOONGARCH_CSR_TLBRERA);
94 set_gcsr_hw_flag(LOONGARCH_CSR_TLBRSAVE);
95 set_gcsr_hw_flag(LOONGARCH_CSR_TLBRELO0);
96 set_gcsr_hw_flag(LOONGARCH_CSR_TLBRELO1);
97 set_gcsr_hw_flag(LOONGARCH_CSR_TLBREHI);
98 set_gcsr_hw_flag(LOONGARCH_CSR_TLBRPRMD);
99 set_gcsr_hw_flag(LOONGARCH_CSR_DMWIN0);
100 set_gcsr_hw_flag(LOONGARCH_CSR_DMWIN1);
101 set_gcsr_hw_flag(LOONGARCH_CSR_DMWIN2);
102 set_gcsr_hw_flag(LOONGARCH_CSR_DMWIN3);
103
104 set_gcsr_sw_flag(LOONGARCH_CSR_IMPCTL1);
105 set_gcsr_sw_flag(LOONGARCH_CSR_IMPCTL2);
106 set_gcsr_sw_flag(LOONGARCH_CSR_MERRCTL);
107 set_gcsr_sw_flag(LOONGARCH_CSR_MERRINFO1);
108 set_gcsr_sw_flag(LOONGARCH_CSR_MERRINFO2);
109 set_gcsr_sw_flag(LOONGARCH_CSR_MERRENTRY);
110 set_gcsr_sw_flag(LOONGARCH_CSR_MERRERA);
111 set_gcsr_sw_flag(LOONGARCH_CSR_MERRSAVE);
112 set_gcsr_sw_flag(LOONGARCH_CSR_CTAG);
113 set_gcsr_sw_flag(LOONGARCH_CSR_DEBUG);
114 set_gcsr_sw_flag(LOONGARCH_CSR_DERA);
115 set_gcsr_sw_flag(LOONGARCH_CSR_DESAVE);
116
117 set_gcsr_sw_flag(LOONGARCH_CSR_FWPC);
118 set_gcsr_sw_flag(LOONGARCH_CSR_FWPS);
119 set_gcsr_sw_flag(LOONGARCH_CSR_MWPC);
120 set_gcsr_sw_flag(LOONGARCH_CSR_MWPS);
121
122 set_gcsr_sw_flag(LOONGARCH_CSR_DB0ADDR);
123 set_gcsr_sw_flag(LOONGARCH_CSR_DB0MASK);
124 set_gcsr_sw_flag(LOONGARCH_CSR_DB0CTRL);
125 set_gcsr_sw_flag(LOONGARCH_CSR_DB0ASID);
126 set_gcsr_sw_flag(LOONGARCH_CSR_DB1ADDR);
127 set_gcsr_sw_flag(LOONGARCH_CSR_DB1MASK);
128 set_gcsr_sw_flag(LOONGARCH_CSR_DB1CTRL);
129 set_gcsr_sw_flag(LOONGARCH_CSR_DB1ASID);
130 set_gcsr_sw_flag(LOONGARCH_CSR_DB2ADDR);
131 set_gcsr_sw_flag(LOONGARCH_CSR_DB2MASK);
132 set_gcsr_sw_flag(LOONGARCH_CSR_DB2CTRL);
133 set_gcsr_sw_flag(LOONGARCH_CSR_DB2ASID);
134 set_gcsr_sw_flag(LOONGARCH_CSR_DB3ADDR);
135 set_gcsr_sw_flag(LOONGARCH_CSR_DB3MASK);
136 set_gcsr_sw_flag(LOONGARCH_CSR_DB3CTRL);
137 set_gcsr_sw_flag(LOONGARCH_CSR_DB3ASID);
138 set_gcsr_sw_flag(LOONGARCH_CSR_DB4ADDR);
139 set_gcsr_sw_flag(LOONGARCH_CSR_DB4MASK);
140 set_gcsr_sw_flag(LOONGARCH_CSR_DB4CTRL);
141 set_gcsr_sw_flag(LOONGARCH_CSR_DB4ASID);
142 set_gcsr_sw_flag(LOONGARCH_CSR_DB5ADDR);
143 set_gcsr_sw_flag(LOONGARCH_CSR_DB5MASK);
144 set_gcsr_sw_flag(LOONGARCH_CSR_DB5CTRL);
145 set_gcsr_sw_flag(LOONGARCH_CSR_DB5ASID);
146 set_gcsr_sw_flag(LOONGARCH_CSR_DB6ADDR);
147 set_gcsr_sw_flag(LOONGARCH_CSR_DB6MASK);
148 set_gcsr_sw_flag(LOONGARCH_CSR_DB6CTRL);
149 set_gcsr_sw_flag(LOONGARCH_CSR_DB6ASID);
150 set_gcsr_sw_flag(LOONGARCH_CSR_DB7ADDR);
151 set_gcsr_sw_flag(LOONGARCH_CSR_DB7MASK);
152 set_gcsr_sw_flag(LOONGARCH_CSR_DB7CTRL);
153 set_gcsr_sw_flag(LOONGARCH_CSR_DB7ASID);
154
155 set_gcsr_sw_flag(LOONGARCH_CSR_IB0ADDR);
156 set_gcsr_sw_flag(LOONGARCH_CSR_IB0MASK);
157 set_gcsr_sw_flag(LOONGARCH_CSR_IB0CTRL);
158 set_gcsr_sw_flag(LOONGARCH_CSR_IB0ASID);
159 set_gcsr_sw_flag(LOONGARCH_CSR_IB1ADDR);
160 set_gcsr_sw_flag(LOONGARCH_CSR_IB1MASK);
161 set_gcsr_sw_flag(LOONGARCH_CSR_IB1CTRL);
162 set_gcsr_sw_flag(LOONGARCH_CSR_IB1ASID);
163 set_gcsr_sw_flag(LOONGARCH_CSR_IB2ADDR);
164 set_gcsr_sw_flag(LOONGARCH_CSR_IB2MASK);
165 set_gcsr_sw_flag(LOONGARCH_CSR_IB2CTRL);
166 set_gcsr_sw_flag(LOONGARCH_CSR_IB2ASID);
167 set_gcsr_sw_flag(LOONGARCH_CSR_IB3ADDR);
168 set_gcsr_sw_flag(LOONGARCH_CSR_IB3MASK);
169 set_gcsr_sw_flag(LOONGARCH_CSR_IB3CTRL);
170 set_gcsr_sw_flag(LOONGARCH_CSR_IB3ASID);
171 set_gcsr_sw_flag(LOONGARCH_CSR_IB4ADDR);
172 set_gcsr_sw_flag(LOONGARCH_CSR_IB4MASK);
173 set_gcsr_sw_flag(LOONGARCH_CSR_IB4CTRL);
174 set_gcsr_sw_flag(LOONGARCH_CSR_IB4ASID);
175 set_gcsr_sw_flag(LOONGARCH_CSR_IB5ADDR);
176 set_gcsr_sw_flag(LOONGARCH_CSR_IB5MASK);
177 set_gcsr_sw_flag(LOONGARCH_CSR_IB5CTRL);
178 set_gcsr_sw_flag(LOONGARCH_CSR_IB5ASID);
179 set_gcsr_sw_flag(LOONGARCH_CSR_IB6ADDR);
180 set_gcsr_sw_flag(LOONGARCH_CSR_IB6MASK);
181 set_gcsr_sw_flag(LOONGARCH_CSR_IB6CTRL);
182 set_gcsr_sw_flag(LOONGARCH_CSR_IB6ASID);
183 set_gcsr_sw_flag(LOONGARCH_CSR_IB7ADDR);
184 set_gcsr_sw_flag(LOONGARCH_CSR_IB7MASK);
185 set_gcsr_sw_flag(LOONGARCH_CSR_IB7CTRL);
186 set_gcsr_sw_flag(LOONGARCH_CSR_IB7ASID);
187
188 set_gcsr_sw_flag(LOONGARCH_CSR_PERFCTRL0);
189 set_gcsr_sw_flag(LOONGARCH_CSR_PERFCNTR0);
190 set_gcsr_sw_flag(LOONGARCH_CSR_PERFCTRL1);
191 set_gcsr_sw_flag(LOONGARCH_CSR_PERFCNTR1);
192 set_gcsr_sw_flag(LOONGARCH_CSR_PERFCTRL2);
193 set_gcsr_sw_flag(LOONGARCH_CSR_PERFCNTR2);
194 set_gcsr_sw_flag(LOONGARCH_CSR_PERFCTRL3);
195 set_gcsr_sw_flag(LOONGARCH_CSR_PERFCNTR3);
196
197 if (cpu_has_msgint) {
198 set_gcsr_hw_flag(LOONGARCH_CSR_IPR);
199 set_gcsr_hw_flag(LOONGARCH_CSR_ISR0);
200 set_gcsr_hw_flag(LOONGARCH_CSR_ISR1);
201 set_gcsr_hw_flag(LOONGARCH_CSR_ISR2);
202 set_gcsr_hw_flag(LOONGARCH_CSR_ISR3);
203 }
204 }
205
kvm_update_vpid(struct kvm_vcpu * vcpu,int cpu)206 static void kvm_update_vpid(struct kvm_vcpu *vcpu, int cpu)
207 {
208 unsigned long vpid;
209 struct kvm_context *context;
210
211 context = per_cpu_ptr(vcpu->kvm->arch.vmcs, cpu);
212 vpid = context->vpid_cache + 1;
213 if (!(vpid & vpid_mask)) {
214 /* finish round of vpid loop */
215 if (unlikely(!vpid))
216 vpid = vpid_mask + 1;
217
218 ++vpid; /* vpid 0 reserved for root */
219
220 /* start new vpid cycle */
221 kvm_flush_tlb_all();
222 }
223
224 context->vpid_cache = vpid;
225 vcpu->arch.vpid = vpid;
226 }
227
kvm_check_vpid(struct kvm_vcpu * vcpu)228 void kvm_check_vpid(struct kvm_vcpu *vcpu)
229 {
230 int cpu;
231 bool migrated;
232 unsigned long ver, old, vpid;
233 struct kvm_context *context;
234
235 cpu = smp_processor_id();
236 /*
237 * Are we entering guest context on a different CPU to last time?
238 * If so, the vCPU's guest TLB state on this CPU may be stale.
239 */
240 context = per_cpu_ptr(vcpu->kvm->arch.vmcs, cpu);
241 migrated = (vcpu->cpu != cpu);
242
243 /*
244 * Check if our vpid is of an older version
245 *
246 * We also discard the stored vpid if we've executed on
247 * another CPU, as the guest mappings may have changed without
248 * hypervisor knowledge.
249 */
250 ver = vcpu->arch.vpid & ~vpid_mask;
251 old = context->vpid_cache & ~vpid_mask;
252 if (migrated || (ver != old)) {
253 kvm_update_vpid(vcpu, cpu);
254 trace_kvm_vpid_change(vcpu, vcpu->arch.vpid);
255 vcpu->cpu = cpu;
256 kvm_clear_request(KVM_REQ_TLB_FLUSH_GPA, vcpu);
257
258 /*
259 * LLBCTL is a separated guest CSR register from host, a general
260 * exception ERET instruction clears the host LLBCTL register in
261 * host mode, and clears the guest LLBCTL register in guest mode.
262 * ERET in tlb refill exception does not clear LLBCTL register.
263 *
264 * When secondary mmu mapping is changed, guest OS does not know
265 * even if the content is changed after mapping is changed.
266 *
267 * Here clear WCLLB of the guest LLBCTL register when mapping is
268 * changed. Otherwise, if mmu mapping is changed while guest is
269 * executing LL/SC pair, LL loads with the old address and set
270 * the LLBCTL flag, SC checks the LLBCTL flag and will store the
271 * new address successfully since LLBCTL_WCLLB is on, even if
272 * memory with new address is changed on other VCPUs.
273 */
274 set_gcsr_llbctl(CSR_LLBCTL_WCLLB);
275
276 /* Restore GSTAT(0x50).vpid */
277 vpid = (vcpu->arch.vpid & vpid_mask) << CSR_GSTAT_GID_SHIFT;
278 change_csr_gstat(vpid_mask << CSR_GSTAT_GID_SHIFT, vpid);
279 }
280 }
281
kvm_init_vmcs(struct kvm * kvm)282 void kvm_init_vmcs(struct kvm *kvm)
283 {
284 kvm->arch.vmcs = vmcs;
285 }
286
kvm_arch_dev_ioctl(struct file * filp,unsigned int ioctl,unsigned long arg)287 long kvm_arch_dev_ioctl(struct file *filp,
288 unsigned int ioctl, unsigned long arg)
289 {
290 return -ENOIOCTLCMD;
291 }
292
kvm_arch_enable_virtualization_cpu(void)293 int kvm_arch_enable_virtualization_cpu(void)
294 {
295 unsigned long env, gcfg = 0;
296
297 env = read_csr_gcfg();
298
299 /* First init gcfg, gstat, gintc, gtlbc. All guest use the same config */
300 write_csr_gcfg(0);
301 write_csr_gstat(0);
302 write_csr_gintc(0);
303 clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI);
304
305 /*
306 * Enable virtualization features granting guest direct control of
307 * certain features:
308 * GCI=2: Trap on init or unimplemented cache instruction.
309 * TORU=0: Trap on Root Unimplement.
310 * CACTRL=1: Root control cache.
311 * TOP=0: Trap on Privilege.
312 * TOE=0: Trap on Exception.
313 * TIT=0: Trap on Timer.
314 */
315 if (env & CSR_GCFG_GCIP_SECURE)
316 gcfg |= CSR_GCFG_GCI_SECURE;
317 if (env & CSR_GCFG_MATP_ROOT)
318 gcfg |= CSR_GCFG_MATC_ROOT;
319
320 write_csr_gcfg(gcfg);
321
322 kvm_flush_tlb_all();
323
324 /* Enable using TGID */
325 set_csr_gtlbc(CSR_GTLBC_USETGID);
326 kvm_debug("GCFG:%lx GSTAT:%lx GINTC:%lx GTLBC:%lx",
327 read_csr_gcfg(), read_csr_gstat(), read_csr_gintc(), read_csr_gtlbc());
328
329 /*
330 * HW Guest CSR registers are lost after CPU suspend and resume.
331 * Clear last_vcpu so that Guest CSR registers forced to reload
332 * from vCPU SW state.
333 */
334 this_cpu_ptr(vmcs)->last_vcpu = NULL;
335
336 return 0;
337 }
338
kvm_arch_disable_virtualization_cpu(void)339 void kvm_arch_disable_virtualization_cpu(void)
340 {
341 write_csr_gcfg(0);
342 write_csr_gstat(0);
343 write_csr_gintc(0);
344 clear_csr_gtlbc(CSR_GTLBC_USETGID | CSR_GTLBC_TOTI);
345
346 /* Flush any remaining guest TLB entries */
347 kvm_flush_tlb_all();
348 }
349
kvm_loongarch_env_init(void)350 static int kvm_loongarch_env_init(void)
351 {
352 int cpu, ret;
353 struct kvm_context *context;
354
355 vmcs = alloc_percpu(struct kvm_context);
356 if (!vmcs) {
357 pr_err("kvm: failed to allocate percpu kvm_context\n");
358 return -ENOMEM;
359 }
360
361 kvm_loongarch_ops = kzalloc_obj(*kvm_loongarch_ops);
362 if (!kvm_loongarch_ops) {
363 free_percpu(vmcs);
364 vmcs = NULL;
365 return -ENOMEM;
366 }
367
368 kvm_loongarch_ops->exc_entry = (void *)kvm_exc_entry;
369 kvm_loongarch_ops->enter_guest = (void *)kvm_enter_guest;
370
371 vpid_mask = read_csr_gstat();
372 vpid_mask = (vpid_mask & CSR_GSTAT_GIDBIT) >> CSR_GSTAT_GIDBIT_SHIFT;
373 if (vpid_mask)
374 vpid_mask = GENMASK(vpid_mask - 1, 0);
375
376 for_each_possible_cpu(cpu) {
377 context = per_cpu_ptr(vmcs, cpu);
378 context->vpid_cache = vpid_mask + 1;
379 context->last_vcpu = NULL;
380 }
381
382 kvm_init_gcsr_flag();
383 kvm_register_perf_callbacks();
384
385 /* Register LoongArch IPI interrupt controller interface. */
386 ret = kvm_loongarch_register_ipi_device();
387 if (ret)
388 goto err_env;
389
390 /* Register LoongArch EIOINTC interrupt controller interface. */
391 ret = kvm_loongarch_register_eiointc_device();
392 if (ret)
393 goto err_ipi;
394
395 /* Register LoongArch PCH-PIC interrupt controller interface. */
396 ret = kvm_loongarch_register_pch_pic_device();
397 if (ret)
398 goto err_eiointc;
399
400 /* Register LoongArch DMSINTC interrupt contrroller interface */
401 if (cpu_has_msgint) {
402 ret = kvm_loongarch_register_dmsintc_device();
403 if (ret)
404 goto err_pch_pic;
405 }
406
407 return 0;
408
409 err_pch_pic:
410 kvm_loongarch_unregister_pch_pic_device();
411 err_eiointc:
412 kvm_loongarch_unregister_eiointc_device();
413 err_ipi:
414 kvm_loongarch_unregister_ipi_device();
415 err_env:
416 kvm_unregister_perf_callbacks();
417 kfree(kvm_loongarch_ops);
418 kvm_loongarch_ops = NULL;
419 free_percpu(vmcs);
420 vmcs = NULL;
421
422 return ret;
423 }
424
kvm_loongarch_env_exit(void)425 static void kvm_loongarch_env_exit(void)
426 {
427 if (cpu_has_msgint)
428 kvm_loongarch_unregister_dmsintc_device();
429
430 kvm_loongarch_unregister_pch_pic_device();
431 kvm_loongarch_unregister_eiointc_device();
432 kvm_loongarch_unregister_ipi_device();
433
434 if (vmcs)
435 free_percpu(vmcs);
436
437 if (kvm_loongarch_ops) {
438 kfree(kvm_loongarch_ops);
439 }
440
441 kvm_unregister_perf_callbacks();
442 }
443
kvm_loongarch_init(void)444 static int kvm_loongarch_init(void)
445 {
446 int r;
447
448 if (!cpu_has_lvz) {
449 kvm_info("Hardware virtualization not available\n");
450 return -ENODEV;
451 }
452 r = kvm_loongarch_env_init();
453 if (r)
454 return r;
455
456 r = kvm_init(sizeof(struct kvm_vcpu), 0, THIS_MODULE);
457 if (r)
458 kvm_loongarch_env_exit();
459
460 return r;
461 }
462
kvm_loongarch_exit(void)463 static void kvm_loongarch_exit(void)
464 {
465 kvm_exit();
466 kvm_loongarch_env_exit();
467 }
468
469 module_init(kvm_loongarch_init);
470 module_exit(kvm_loongarch_exit);
471
472 #ifdef MODULE
473 static const struct cpu_feature kvm_feature[] = {
474 { .feature = cpu_feature(LOONGARCH_LVZ) },
475 {},
476 };
477 MODULE_DEVICE_TABLE(cpu, kvm_feature);
478 #endif
479