xref: /linux/arch/arm64/include/asm/kvm_host.h (revision c924c5e9b8c65b3a479a90e5e37d74cc8cd9fe0a)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2012,2013 - ARM Ltd
4  * Author: Marc Zyngier <marc.zyngier@arm.com>
5  *
6  * Derived from arch/arm/include/asm/kvm_host.h:
7  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8  * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9  */
10 
11 #ifndef __ARM64_KVM_HOST_H__
12 #define __ARM64_KVM_HOST_H__
13 
14 #include <linux/arm-smccc.h>
15 #include <linux/bitmap.h>
16 #include <linux/types.h>
17 #include <linux/jump_label.h>
18 #include <linux/kvm_types.h>
19 #include <linux/maple_tree.h>
20 #include <linux/percpu.h>
21 #include <linux/psci.h>
22 #include <asm/arch_gicv3.h>
23 #include <asm/barrier.h>
24 #include <asm/cpufeature.h>
25 #include <asm/cputype.h>
26 #include <asm/daifflags.h>
27 #include <asm/fpsimd.h>
28 #include <asm/kvm.h>
29 #include <asm/kvm_asm.h>
30 #include <asm/vncr_mapping.h>
31 
32 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
33 
34 #define KVM_HALT_POLL_NS_DEFAULT 500000
35 
36 #include <kvm/arm_vgic.h>
37 #include <kvm/arm_arch_timer.h>
38 #include <kvm/arm_pmu.h>
39 
40 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
41 
42 #define KVM_VCPU_MAX_FEATURES 7
43 #define KVM_VCPU_VALID_FEATURES	(BIT(KVM_VCPU_MAX_FEATURES) - 1)
44 
45 #define KVM_REQ_SLEEP \
46 	KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
47 #define KVM_REQ_IRQ_PENDING		KVM_ARCH_REQ(1)
48 #define KVM_REQ_VCPU_RESET		KVM_ARCH_REQ(2)
49 #define KVM_REQ_RECORD_STEAL		KVM_ARCH_REQ(3)
50 #define KVM_REQ_RELOAD_GICv4		KVM_ARCH_REQ(4)
51 #define KVM_REQ_RELOAD_PMU		KVM_ARCH_REQ(5)
52 #define KVM_REQ_SUSPEND			KVM_ARCH_REQ(6)
53 #define KVM_REQ_RESYNC_PMU_EL0		KVM_ARCH_REQ(7)
54 #define KVM_REQ_NESTED_S2_UNMAP		KVM_ARCH_REQ(8)
55 #define KVM_REQ_GUEST_HYP_IRQ_PENDING	KVM_ARCH_REQ(9)
56 
57 #define KVM_DIRTY_LOG_MANUAL_CAPS   (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \
58 				     KVM_DIRTY_LOG_INITIALLY_SET)
59 
60 #define KVM_HAVE_MMU_RWLOCK
61 
62 /*
63  * Mode of operation configurable with kvm-arm.mode early param.
64  * See Documentation/admin-guide/kernel-parameters.txt for more information.
65  */
66 enum kvm_mode {
67 	KVM_MODE_DEFAULT,
68 	KVM_MODE_PROTECTED,
69 	KVM_MODE_NV,
70 	KVM_MODE_NONE,
71 };
72 #ifdef CONFIG_KVM
73 enum kvm_mode kvm_get_mode(void);
74 #else
kvm_get_mode(void)75 static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; };
76 #endif
77 
78 extern unsigned int __ro_after_init kvm_sve_max_vl;
79 extern unsigned int __ro_after_init kvm_host_sve_max_vl;
80 int __init kvm_arm_init_sve(void);
81 
82 u32 __attribute_const__ kvm_target_cpu(void);
83 void kvm_reset_vcpu(struct kvm_vcpu *vcpu);
84 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu);
85 
86 struct kvm_hyp_memcache {
87 	phys_addr_t head;
88 	unsigned long nr_pages;
89 	struct pkvm_mapping *mapping; /* only used from EL1 */
90 
91 #define	HYP_MEMCACHE_ACCOUNT_STAGE2	BIT(1)
92 	unsigned long flags;
93 };
94 
push_hyp_memcache(struct kvm_hyp_memcache * mc,phys_addr_t * p,phys_addr_t (* to_pa)(void * virt))95 static inline void push_hyp_memcache(struct kvm_hyp_memcache *mc,
96 				     phys_addr_t *p,
97 				     phys_addr_t (*to_pa)(void *virt))
98 {
99 	*p = mc->head;
100 	mc->head = to_pa(p);
101 	mc->nr_pages++;
102 }
103 
pop_hyp_memcache(struct kvm_hyp_memcache * mc,void * (* to_va)(phys_addr_t phys))104 static inline void *pop_hyp_memcache(struct kvm_hyp_memcache *mc,
105 				     void *(*to_va)(phys_addr_t phys))
106 {
107 	phys_addr_t *p = to_va(mc->head & PAGE_MASK);
108 
109 	if (!mc->nr_pages)
110 		return NULL;
111 
112 	mc->head = *p;
113 	mc->nr_pages--;
114 
115 	return p;
116 }
117 
__topup_hyp_memcache(struct kvm_hyp_memcache * mc,unsigned long min_pages,void * (* alloc_fn)(void * arg),phys_addr_t (* to_pa)(void * virt),void * arg)118 static inline int __topup_hyp_memcache(struct kvm_hyp_memcache *mc,
119 				       unsigned long min_pages,
120 				       void *(*alloc_fn)(void *arg),
121 				       phys_addr_t (*to_pa)(void *virt),
122 				       void *arg)
123 {
124 	while (mc->nr_pages < min_pages) {
125 		phys_addr_t *p = alloc_fn(arg);
126 
127 		if (!p)
128 			return -ENOMEM;
129 		push_hyp_memcache(mc, p, to_pa);
130 	}
131 
132 	return 0;
133 }
134 
__free_hyp_memcache(struct kvm_hyp_memcache * mc,void (* free_fn)(void * virt,void * arg),void * (* to_va)(phys_addr_t phys),void * arg)135 static inline void __free_hyp_memcache(struct kvm_hyp_memcache *mc,
136 				       void (*free_fn)(void *virt, void *arg),
137 				       void *(*to_va)(phys_addr_t phys),
138 				       void *arg)
139 {
140 	while (mc->nr_pages)
141 		free_fn(pop_hyp_memcache(mc, to_va), arg);
142 }
143 
144 void free_hyp_memcache(struct kvm_hyp_memcache *mc);
145 int topup_hyp_memcache(struct kvm_hyp_memcache *mc, unsigned long min_pages);
146 
147 struct kvm_vmid {
148 	atomic64_t id;
149 };
150 
151 struct kvm_s2_mmu {
152 	struct kvm_vmid vmid;
153 
154 	/*
155 	 * stage2 entry level table
156 	 *
157 	 * Two kvm_s2_mmu structures in the same VM can point to the same
158 	 * pgd here.  This happens when running a guest using a
159 	 * translation regime that isn't affected by its own stage-2
160 	 * translation, such as a non-VHE hypervisor running at vEL2, or
161 	 * for vEL1/EL0 with vHCR_EL2.VM == 0.  In that case, we use the
162 	 * canonical stage-2 page tables.
163 	 */
164 	phys_addr_t	pgd_phys;
165 	struct kvm_pgtable *pgt;
166 
167 	/*
168 	 * VTCR value used on the host. For a non-NV guest (or a NV
169 	 * guest that runs in a context where its own S2 doesn't
170 	 * apply), its T0SZ value reflects that of the IPA size.
171 	 *
172 	 * For a shadow S2 MMU, T0SZ reflects the PARange exposed to
173 	 * the guest.
174 	 */
175 	u64	vtcr;
176 
177 	/* The last vcpu id that ran on each physical CPU */
178 	int __percpu *last_vcpu_ran;
179 
180 #define KVM_ARM_EAGER_SPLIT_CHUNK_SIZE_DEFAULT 0
181 	/*
182 	 * Memory cache used to split
183 	 * KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE worth of huge pages. It
184 	 * is used to allocate stage2 page tables while splitting huge
185 	 * pages. The choice of KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE
186 	 * influences both the capacity of the split page cache, and
187 	 * how often KVM reschedules. Be wary of raising CHUNK_SIZE
188 	 * too high.
189 	 *
190 	 * Protected by kvm->slots_lock.
191 	 */
192 	struct kvm_mmu_memory_cache split_page_cache;
193 	uint64_t split_page_chunk_size;
194 
195 	struct kvm_arch *arch;
196 
197 	/*
198 	 * For a shadow stage-2 MMU, the virtual vttbr used by the
199 	 * host to parse the guest S2.
200 	 * This either contains:
201 	 * - the virtual VTTBR programmed by the guest hypervisor with
202          *   CnP cleared
203 	 * - The value 1 (VMID=0, BADDR=0, CnP=1) if invalid
204 	 *
205 	 * We also cache the full VTCR which gets used for TLB invalidation,
206 	 * taking the ARM ARM's "Any of the bits in VTCR_EL2 are permitted
207 	 * to be cached in a TLB" to the letter.
208 	 */
209 	u64	tlb_vttbr;
210 	u64	tlb_vtcr;
211 
212 	/*
213 	 * true when this represents a nested context where virtual
214 	 * HCR_EL2.VM == 1
215 	 */
216 	bool	nested_stage2_enabled;
217 
218 	/*
219 	 * true when this MMU needs to be unmapped before being used for a new
220 	 * purpose.
221 	 */
222 	bool	pending_unmap;
223 
224 	/*
225 	 *  0: Nobody is currently using this, check vttbr for validity
226 	 * >0: Somebody is actively using this.
227 	 */
228 	atomic_t refcnt;
229 };
230 
231 struct kvm_arch_memory_slot {
232 };
233 
234 /**
235  * struct kvm_smccc_features: Descriptor of the hypercall services exposed to the guests
236  *
237  * @std_bmap: Bitmap of standard secure service calls
238  * @std_hyp_bmap: Bitmap of standard hypervisor service calls
239  * @vendor_hyp_bmap: Bitmap of vendor specific hypervisor service calls
240  */
241 struct kvm_smccc_features {
242 	unsigned long std_bmap;
243 	unsigned long std_hyp_bmap;
244 	unsigned long vendor_hyp_bmap; /* Function numbers 0-63 */
245 	unsigned long vendor_hyp_bmap_2; /* Function numbers 64-127 */
246 };
247 
248 typedef unsigned int pkvm_handle_t;
249 
250 struct kvm_protected_vm {
251 	pkvm_handle_t handle;
252 	struct kvm_hyp_memcache teardown_mc;
253 	struct kvm_hyp_memcache stage2_teardown_mc;
254 	bool enabled;
255 };
256 
257 struct kvm_mpidr_data {
258 	u64			mpidr_mask;
259 	DECLARE_FLEX_ARRAY(u16, cmpidr_to_idx);
260 };
261 
kvm_mpidr_index(struct kvm_mpidr_data * data,u64 mpidr)262 static inline u16 kvm_mpidr_index(struct kvm_mpidr_data *data, u64 mpidr)
263 {
264 	unsigned long index = 0, mask = data->mpidr_mask;
265 	unsigned long aff = mpidr & MPIDR_HWID_BITMASK;
266 
267 	bitmap_gather(&index, &aff, &mask, fls(mask));
268 
269 	return index;
270 }
271 
272 struct kvm_sysreg_masks;
273 
274 enum fgt_group_id {
275 	__NO_FGT_GROUP__,
276 	HFGxTR_GROUP,
277 	HDFGRTR_GROUP,
278 	HDFGWTR_GROUP = HDFGRTR_GROUP,
279 	HFGITR_GROUP,
280 	HAFGRTR_GROUP,
281 
282 	/* Must be last */
283 	__NR_FGT_GROUP_IDS__
284 };
285 
286 struct kvm_arch {
287 	struct kvm_s2_mmu mmu;
288 
289 	/*
290 	 * Fine-Grained UNDEF, mimicking the FGT layout defined by the
291 	 * architecture. We track them globally, as we present the
292 	 * same feature-set to all vcpus.
293 	 *
294 	 * Index 0 is currently spare.
295 	 */
296 	u64 fgu[__NR_FGT_GROUP_IDS__];
297 
298 	/*
299 	 * Stage 2 paging state for VMs with nested S2 using a virtual
300 	 * VMID.
301 	 */
302 	struct kvm_s2_mmu *nested_mmus;
303 	size_t nested_mmus_size;
304 	int nested_mmus_next;
305 
306 	/* Interrupt controller */
307 	struct vgic_dist	vgic;
308 
309 	/* Timers */
310 	struct arch_timer_vm_data timer_data;
311 
312 	/* Mandated version of PSCI */
313 	u32 psci_version;
314 
315 	/* Protects VM-scoped configuration data */
316 	struct mutex config_lock;
317 
318 	/*
319 	 * If we encounter a data abort without valid instruction syndrome
320 	 * information, report this to user space.  User space can (and
321 	 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is
322 	 * supported.
323 	 */
324 #define KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER	0
325 	/* Memory Tagging Extension enabled for the guest */
326 #define KVM_ARCH_FLAG_MTE_ENABLED			1
327 	/* At least one vCPU has ran in the VM */
328 #define KVM_ARCH_FLAG_HAS_RAN_ONCE			2
329 	/* The vCPU feature set for the VM is configured */
330 #define KVM_ARCH_FLAG_VCPU_FEATURES_CONFIGURED		3
331 	/* PSCI SYSTEM_SUSPEND enabled for the guest */
332 #define KVM_ARCH_FLAG_SYSTEM_SUSPEND_ENABLED		4
333 	/* VM counter offset */
334 #define KVM_ARCH_FLAG_VM_COUNTER_OFFSET			5
335 	/* Timer PPIs made immutable */
336 #define KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE		6
337 	/* Initial ID reg values loaded */
338 #define KVM_ARCH_FLAG_ID_REGS_INITIALIZED		7
339 	/* Fine-Grained UNDEF initialised */
340 #define KVM_ARCH_FLAG_FGU_INITIALIZED			8
341 	/* SVE exposed to guest */
342 #define KVM_ARCH_FLAG_GUEST_HAS_SVE			9
343 	/* MIDR_EL1, REVIDR_EL1, and AIDR_EL1 are writable from userspace */
344 #define KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS		10
345 	unsigned long flags;
346 
347 	/* VM-wide vCPU feature set */
348 	DECLARE_BITMAP(vcpu_features, KVM_VCPU_MAX_FEATURES);
349 
350 	/* MPIDR to vcpu index mapping, optional */
351 	struct kvm_mpidr_data *mpidr_data;
352 
353 	/*
354 	 * VM-wide PMU filter, implemented as a bitmap and big enough for
355 	 * up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+).
356 	 */
357 	unsigned long *pmu_filter;
358 	struct arm_pmu *arm_pmu;
359 
360 	cpumask_var_t supported_cpus;
361 
362 	/* PMCR_EL0.N value for the guest */
363 	u8 pmcr_n;
364 
365 	/* Iterator for idreg debugfs */
366 	u8	idreg_debugfs_iter;
367 
368 	/* Hypercall features firmware registers' descriptor */
369 	struct kvm_smccc_features smccc_feat;
370 	struct maple_tree smccc_filter;
371 
372 	/*
373 	 * Emulated CPU ID registers per VM
374 	 * (Op0, Op1, CRn, CRm, Op2) of the ID registers to be saved in it
375 	 * is (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8.
376 	 *
377 	 * These emulated idregs are VM-wide, but accessed from the context of a vCPU.
378 	 * Atomic access to multiple idregs are guarded by kvm_arch.config_lock.
379 	 */
380 #define IDREG_IDX(id)		(((sys_reg_CRm(id) - 1) << 3) | sys_reg_Op2(id))
381 #define KVM_ARM_ID_REG_NUM	(IDREG_IDX(sys_reg(3, 0, 0, 7, 7)) + 1)
382 	u64 id_regs[KVM_ARM_ID_REG_NUM];
383 
384 	u64 midr_el1;
385 	u64 revidr_el1;
386 	u64 aidr_el1;
387 	u64 ctr_el0;
388 
389 	/* Masks for VNCR-backed and general EL2 sysregs */
390 	struct kvm_sysreg_masks	*sysreg_masks;
391 
392 	/*
393 	 * For an untrusted host VM, 'pkvm.handle' is used to lookup
394 	 * the associated pKVM instance in the hypervisor.
395 	 */
396 	struct kvm_protected_vm pkvm;
397 };
398 
399 struct kvm_vcpu_fault_info {
400 	u64 esr_el2;		/* Hyp Syndrom Register */
401 	u64 far_el2;		/* Hyp Fault Address Register */
402 	u64 hpfar_el2;		/* Hyp IPA Fault Address Register */
403 	u64 disr_el1;		/* Deferred [SError] Status Register */
404 };
405 
406 /*
407  * VNCR() just places the VNCR_capable registers in the enum after
408  * __VNCR_START__, and the value (after correction) to be an 8-byte offset
409  * from the VNCR base. As we don't require the enum to be otherwise ordered,
410  * we need the terrible hack below to ensure that we correctly size the
411  * sys_regs array, no matter what.
412  *
413  * The __MAX__ macro has been lifted from Sean Eron Anderson's wonderful
414  * treasure trove of bit hacks:
415  * https://graphics.stanford.edu/~seander/bithacks.html#IntegerMinOrMax
416  */
417 #define __MAX__(x,y)	((x) ^ (((x) ^ (y)) & -((x) < (y))))
418 #define VNCR(r)						\
419 	__before_##r,					\
420 	r = __VNCR_START__ + ((VNCR_ ## r) / 8),	\
421 	__after_##r = __MAX__(__before_##r - 1, r)
422 
423 #define MARKER(m)				\
424 	m, __after_##m = m - 1
425 
426 enum vcpu_sysreg {
427 	__INVALID_SYSREG__,   /* 0 is reserved as an invalid value */
428 	MPIDR_EL1,	/* MultiProcessor Affinity Register */
429 	CLIDR_EL1,	/* Cache Level ID Register */
430 	CSSELR_EL1,	/* Cache Size Selection Register */
431 	TPIDR_EL0,	/* Thread ID, User R/W */
432 	TPIDRRO_EL0,	/* Thread ID, User R/O */
433 	TPIDR_EL1,	/* Thread ID, Privileged */
434 	CNTKCTL_EL1,	/* Timer Control Register (EL1) */
435 	PAR_EL1,	/* Physical Address Register */
436 	MDCCINT_EL1,	/* Monitor Debug Comms Channel Interrupt Enable Reg */
437 	OSLSR_EL1,	/* OS Lock Status Register */
438 	DISR_EL1,	/* Deferred Interrupt Status Register */
439 
440 	/* Performance Monitors Registers */
441 	PMCR_EL0,	/* Control Register */
442 	PMSELR_EL0,	/* Event Counter Selection Register */
443 	PMEVCNTR0_EL0,	/* Event Counter Register (0-30) */
444 	PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
445 	PMCCNTR_EL0,	/* Cycle Counter Register */
446 	PMEVTYPER0_EL0,	/* Event Type Register (0-30) */
447 	PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
448 	PMCCFILTR_EL0,	/* Cycle Count Filter Register */
449 	PMCNTENSET_EL0,	/* Count Enable Set Register */
450 	PMINTENSET_EL1,	/* Interrupt Enable Set Register */
451 	PMOVSSET_EL0,	/* Overflow Flag Status Set Register */
452 	PMUSERENR_EL0,	/* User Enable Register */
453 
454 	/* Pointer Authentication Registers in a strict increasing order. */
455 	APIAKEYLO_EL1,
456 	APIAKEYHI_EL1,
457 	APIBKEYLO_EL1,
458 	APIBKEYHI_EL1,
459 	APDAKEYLO_EL1,
460 	APDAKEYHI_EL1,
461 	APDBKEYLO_EL1,
462 	APDBKEYHI_EL1,
463 	APGAKEYLO_EL1,
464 	APGAKEYHI_EL1,
465 
466 	/* Memory Tagging Extension registers */
467 	RGSR_EL1,	/* Random Allocation Tag Seed Register */
468 	GCR_EL1,	/* Tag Control Register */
469 	TFSRE0_EL1,	/* Tag Fault Status Register (EL0) */
470 
471 	POR_EL0,	/* Permission Overlay Register 0 (EL0) */
472 
473 	/* FP/SIMD/SVE */
474 	SVCR,
475 	FPMR,
476 
477 	/* 32bit specific registers. */
478 	DACR32_EL2,	/* Domain Access Control Register */
479 	IFSR32_EL2,	/* Instruction Fault Status Register */
480 	FPEXC32_EL2,	/* Floating-Point Exception Control Register */
481 	DBGVCR32_EL2,	/* Debug Vector Catch Register */
482 
483 	/* EL2 registers */
484 	SCTLR_EL2,	/* System Control Register (EL2) */
485 	ACTLR_EL2,	/* Auxiliary Control Register (EL2) */
486 	CPTR_EL2,	/* Architectural Feature Trap Register (EL2) */
487 	HACR_EL2,	/* Hypervisor Auxiliary Control Register */
488 	ZCR_EL2,	/* SVE Control Register (EL2) */
489 	TTBR0_EL2,	/* Translation Table Base Register 0 (EL2) */
490 	TTBR1_EL2,	/* Translation Table Base Register 1 (EL2) */
491 	TCR_EL2,	/* Translation Control Register (EL2) */
492 	PIRE0_EL2,	/* Permission Indirection Register 0 (EL2) */
493 	PIR_EL2,	/* Permission Indirection Register 1 (EL2) */
494 	POR_EL2,	/* Permission Overlay Register 2 (EL2) */
495 	SPSR_EL2,	/* EL2 saved program status register */
496 	ELR_EL2,	/* EL2 exception link register */
497 	AFSR0_EL2,	/* Auxiliary Fault Status Register 0 (EL2) */
498 	AFSR1_EL2,	/* Auxiliary Fault Status Register 1 (EL2) */
499 	ESR_EL2,	/* Exception Syndrome Register (EL2) */
500 	FAR_EL2,	/* Fault Address Register (EL2) */
501 	HPFAR_EL2,	/* Hypervisor IPA Fault Address Register */
502 	MAIR_EL2,	/* Memory Attribute Indirection Register (EL2) */
503 	AMAIR_EL2,	/* Auxiliary Memory Attribute Indirection Register (EL2) */
504 	VBAR_EL2,	/* Vector Base Address Register (EL2) */
505 	RVBAR_EL2,	/* Reset Vector Base Address Register */
506 	CONTEXTIDR_EL2,	/* Context ID Register (EL2) */
507 	SP_EL2,		/* EL2 Stack Pointer */
508 	CNTHP_CTL_EL2,
509 	CNTHP_CVAL_EL2,
510 	CNTHV_CTL_EL2,
511 	CNTHV_CVAL_EL2,
512 
513 	/* Anything from this can be RES0/RES1 sanitised */
514 	MARKER(__SANITISED_REG_START__),
515 	TCR2_EL2,	/* Extended Translation Control Register (EL2) */
516 	MDCR_EL2,	/* Monitor Debug Configuration Register (EL2) */
517 	CNTHCTL_EL2,	/* Counter-timer Hypervisor Control register */
518 
519 	/* Any VNCR-capable reg goes after this point */
520 	MARKER(__VNCR_START__),
521 
522 	VNCR(SCTLR_EL1),/* System Control Register */
523 	VNCR(ACTLR_EL1),/* Auxiliary Control Register */
524 	VNCR(CPACR_EL1),/* Coprocessor Access Control */
525 	VNCR(ZCR_EL1),	/* SVE Control */
526 	VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */
527 	VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */
528 	VNCR(TCR_EL1),	/* Translation Control Register */
529 	VNCR(TCR2_EL1),	/* Extended Translation Control Register */
530 	VNCR(ESR_EL1),	/* Exception Syndrome Register */
531 	VNCR(AFSR0_EL1),/* Auxiliary Fault Status Register 0 */
532 	VNCR(AFSR1_EL1),/* Auxiliary Fault Status Register 1 */
533 	VNCR(FAR_EL1),	/* Fault Address Register */
534 	VNCR(MAIR_EL1),	/* Memory Attribute Indirection Register */
535 	VNCR(VBAR_EL1),	/* Vector Base Address Register */
536 	VNCR(CONTEXTIDR_EL1),	/* Context ID Register */
537 	VNCR(AMAIR_EL1),/* Aux Memory Attribute Indirection Register */
538 	VNCR(MDSCR_EL1),/* Monitor Debug System Control Register */
539 	VNCR(ELR_EL1),
540 	VNCR(SP_EL1),
541 	VNCR(SPSR_EL1),
542 	VNCR(TFSR_EL1),	/* Tag Fault Status Register (EL1) */
543 	VNCR(VPIDR_EL2),/* Virtualization Processor ID Register */
544 	VNCR(VMPIDR_EL2),/* Virtualization Multiprocessor ID Register */
545 	VNCR(HCR_EL2),	/* Hypervisor Configuration Register */
546 	VNCR(HSTR_EL2),	/* Hypervisor System Trap Register */
547 	VNCR(VTTBR_EL2),/* Virtualization Translation Table Base Register */
548 	VNCR(VTCR_EL2),	/* Virtualization Translation Control Register */
549 	VNCR(TPIDR_EL2),/* EL2 Software Thread ID Register */
550 	VNCR(HCRX_EL2),	/* Extended Hypervisor Configuration Register */
551 
552 	/* Permission Indirection Extension registers */
553 	VNCR(PIR_EL1),	 /* Permission Indirection Register 1 (EL1) */
554 	VNCR(PIRE0_EL1), /*  Permission Indirection Register 0 (EL1) */
555 
556 	VNCR(POR_EL1),	/* Permission Overlay Register 1 (EL1) */
557 
558 	VNCR(HFGRTR_EL2),
559 	VNCR(HFGWTR_EL2),
560 	VNCR(HFGITR_EL2),
561 	VNCR(HDFGRTR_EL2),
562 	VNCR(HDFGWTR_EL2),
563 	VNCR(HAFGRTR_EL2),
564 
565 	VNCR(CNTVOFF_EL2),
566 	VNCR(CNTV_CVAL_EL0),
567 	VNCR(CNTV_CTL_EL0),
568 	VNCR(CNTP_CVAL_EL0),
569 	VNCR(CNTP_CTL_EL0),
570 
571 	VNCR(ICH_LR0_EL2),
572 	VNCR(ICH_LR1_EL2),
573 	VNCR(ICH_LR2_EL2),
574 	VNCR(ICH_LR3_EL2),
575 	VNCR(ICH_LR4_EL2),
576 	VNCR(ICH_LR5_EL2),
577 	VNCR(ICH_LR6_EL2),
578 	VNCR(ICH_LR7_EL2),
579 	VNCR(ICH_LR8_EL2),
580 	VNCR(ICH_LR9_EL2),
581 	VNCR(ICH_LR10_EL2),
582 	VNCR(ICH_LR11_EL2),
583 	VNCR(ICH_LR12_EL2),
584 	VNCR(ICH_LR13_EL2),
585 	VNCR(ICH_LR14_EL2),
586 	VNCR(ICH_LR15_EL2),
587 
588 	VNCR(ICH_AP0R0_EL2),
589 	VNCR(ICH_AP0R1_EL2),
590 	VNCR(ICH_AP0R2_EL2),
591 	VNCR(ICH_AP0R3_EL2),
592 	VNCR(ICH_AP1R0_EL2),
593 	VNCR(ICH_AP1R1_EL2),
594 	VNCR(ICH_AP1R2_EL2),
595 	VNCR(ICH_AP1R3_EL2),
596 	VNCR(ICH_HCR_EL2),
597 	VNCR(ICH_VMCR_EL2),
598 
599 	NR_SYS_REGS	/* Nothing after this line! */
600 };
601 
602 struct kvm_sysreg_masks {
603 	struct {
604 		u64	res0;
605 		u64	res1;
606 	} mask[NR_SYS_REGS - __SANITISED_REG_START__];
607 };
608 
609 struct kvm_cpu_context {
610 	struct user_pt_regs regs;	/* sp = sp_el0 */
611 
612 	u64	spsr_abt;
613 	u64	spsr_und;
614 	u64	spsr_irq;
615 	u64	spsr_fiq;
616 
617 	struct user_fpsimd_state fp_regs;
618 
619 	u64 sys_regs[NR_SYS_REGS];
620 
621 	struct kvm_vcpu *__hyp_running_vcpu;
622 
623 	/* This pointer has to be 4kB aligned. */
624 	u64 *vncr_array;
625 };
626 
627 struct cpu_sve_state {
628 	__u64 zcr_el1;
629 
630 	/*
631 	 * Ordering is important since __sve_save_state/__sve_restore_state
632 	 * relies on it.
633 	 */
634 	__u32 fpsr;
635 	__u32 fpcr;
636 
637 	/* Must be SVE_VQ_BYTES (128 bit) aligned. */
638 	__u8 sve_regs[];
639 };
640 
641 /*
642  * This structure is instantiated on a per-CPU basis, and contains
643  * data that is:
644  *
645  * - tied to a single physical CPU, and
646  * - either have a lifetime that does not extend past vcpu_put()
647  * - or is an invariant for the lifetime of the system
648  *
649  * Use host_data_ptr(field) as a way to access a pointer to such a
650  * field.
651  */
652 struct kvm_host_data {
653 #define KVM_HOST_DATA_FLAG_HAS_SPE			0
654 #define KVM_HOST_DATA_FLAG_HAS_TRBE			1
655 #define KVM_HOST_DATA_FLAG_TRBE_ENABLED			4
656 #define KVM_HOST_DATA_FLAG_EL1_TRACING_CONFIGURED	5
657 	unsigned long flags;
658 
659 	struct kvm_cpu_context host_ctxt;
660 
661 	/*
662 	 * Hyp VA.
663 	 * sve_state is only used in pKVM and if system_supports_sve().
664 	 */
665 	struct cpu_sve_state *sve_state;
666 
667 	/* Used by pKVM only. */
668 	u64	fpmr;
669 
670 	/* Ownership of the FP regs */
671 	enum {
672 		FP_STATE_FREE,
673 		FP_STATE_HOST_OWNED,
674 		FP_STATE_GUEST_OWNED,
675 	} fp_owner;
676 
677 	/*
678 	 * host_debug_state contains the host registers which are
679 	 * saved and restored during world switches.
680 	 */
681 	struct {
682 		/* {Break,watch}point registers */
683 		struct kvm_guest_debug_arch regs;
684 		/* Statistical profiling extension */
685 		u64 pmscr_el1;
686 		/* Self-hosted trace */
687 		u64 trfcr_el1;
688 		/* Values of trap registers for the host before guest entry. */
689 		u64 mdcr_el2;
690 	} host_debug_state;
691 
692 	/* Guest trace filter value */
693 	u64 trfcr_while_in_guest;
694 
695 	/* Number of programmable event counters (PMCR_EL0.N) for this CPU */
696 	unsigned int nr_event_counters;
697 
698 	/* Number of debug breakpoints/watchpoints for this CPU (minus 1) */
699 	unsigned int debug_brps;
700 	unsigned int debug_wrps;
701 };
702 
703 struct kvm_host_psci_config {
704 	/* PSCI version used by host. */
705 	u32 version;
706 	u32 smccc_version;
707 
708 	/* Function IDs used by host if version is v0.1. */
709 	struct psci_0_1_function_ids function_ids_0_1;
710 
711 	bool psci_0_1_cpu_suspend_implemented;
712 	bool psci_0_1_cpu_on_implemented;
713 	bool psci_0_1_cpu_off_implemented;
714 	bool psci_0_1_migrate_implemented;
715 };
716 
717 extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config);
718 #define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config)
719 
720 extern s64 kvm_nvhe_sym(hyp_physvirt_offset);
721 #define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset)
722 
723 extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS];
724 #define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map)
725 
726 struct vcpu_reset_state {
727 	unsigned long	pc;
728 	unsigned long	r0;
729 	bool		be;
730 	bool		reset;
731 };
732 
733 struct kvm_vcpu_arch {
734 	struct kvm_cpu_context ctxt;
735 
736 	/*
737 	 * Guest floating point state
738 	 *
739 	 * The architecture has two main floating point extensions,
740 	 * the original FPSIMD and SVE.  These have overlapping
741 	 * register views, with the FPSIMD V registers occupying the
742 	 * low 128 bits of the SVE Z registers.  When the core
743 	 * floating point code saves the register state of a task it
744 	 * records which view it saved in fp_type.
745 	 */
746 	void *sve_state;
747 	enum fp_type fp_type;
748 	unsigned int sve_max_vl;
749 
750 	/* Stage 2 paging state used by the hardware on next switch */
751 	struct kvm_s2_mmu *hw_mmu;
752 
753 	/* Values of trap registers for the guest. */
754 	u64 hcr_el2;
755 	u64 hcrx_el2;
756 	u64 mdcr_el2;
757 
758 	/* Exception Information */
759 	struct kvm_vcpu_fault_info fault;
760 
761 	/* Configuration flags, set once and for all before the vcpu can run */
762 	u8 cflags;
763 
764 	/* Input flags to the hypervisor code, potentially cleared after use */
765 	u8 iflags;
766 
767 	/* State flags for kernel bookkeeping, unused by the hypervisor code */
768 	u8 sflags;
769 
770 	/*
771 	 * Don't run the guest (internal implementation need).
772 	 *
773 	 * Contrary to the flags above, this is set/cleared outside of
774 	 * a vcpu context, and thus cannot be mixed with the flags
775 	 * themselves (or the flag accesses need to be made atomic).
776 	 */
777 	bool pause;
778 
779 	/*
780 	 * We maintain more than a single set of debug registers to support
781 	 * debugging the guest from the host and to maintain separate host and
782 	 * guest state during world switches. vcpu_debug_state are the debug
783 	 * registers of the vcpu as the guest sees them.
784 	 *
785 	 * external_debug_state contains the debug values we want to debug the
786 	 * guest. This is set via the KVM_SET_GUEST_DEBUG ioctl.
787 	 */
788 	struct kvm_guest_debug_arch vcpu_debug_state;
789 	struct kvm_guest_debug_arch external_debug_state;
790 	u64 external_mdscr_el1;
791 
792 	enum {
793 		VCPU_DEBUG_FREE,
794 		VCPU_DEBUG_HOST_OWNED,
795 		VCPU_DEBUG_GUEST_OWNED,
796 	} debug_owner;
797 
798 	/* VGIC state */
799 	struct vgic_cpu vgic_cpu;
800 	struct arch_timer_cpu timer_cpu;
801 	struct kvm_pmu pmu;
802 
803 	/* vcpu power state */
804 	struct kvm_mp_state mp_state;
805 	spinlock_t mp_state_lock;
806 
807 	/* Cache some mmu pages needed inside spinlock regions */
808 	struct kvm_mmu_memory_cache mmu_page_cache;
809 
810 	/* Pages to top-up the pKVM/EL2 guest pool */
811 	struct kvm_hyp_memcache pkvm_memcache;
812 
813 	/* Virtual SError ESR to restore when HCR_EL2.VSE is set */
814 	u64 vsesr_el2;
815 
816 	/* Additional reset state */
817 	struct vcpu_reset_state	reset_state;
818 
819 	/* Guest PV state */
820 	struct {
821 		u64 last_steal;
822 		gpa_t base;
823 	} steal;
824 
825 	/* Per-vcpu CCSIDR override or NULL */
826 	u32 *ccsidr;
827 };
828 
829 /*
830  * Each 'flag' is composed of a comma-separated triplet:
831  *
832  * - the flag-set it belongs to in the vcpu->arch structure
833  * - the value for that flag
834  * - the mask for that flag
835  *
836  *  __vcpu_single_flag() builds such a triplet for a single-bit flag.
837  * unpack_vcpu_flag() extract the flag value from the triplet for
838  * direct use outside of the flag accessors.
839  */
840 #define __vcpu_single_flag(_set, _f)	_set, (_f), (_f)
841 
842 #define __unpack_flag(_set, _f, _m)	_f
843 #define unpack_vcpu_flag(...)		__unpack_flag(__VA_ARGS__)
844 
845 #define __build_check_flag(v, flagset, f, m)			\
846 	do {							\
847 		typeof(v->arch.flagset) *_fset;			\
848 								\
849 		/* Check that the flags fit in the mask */	\
850 		BUILD_BUG_ON(HWEIGHT(m) != HWEIGHT((f) | (m)));	\
851 		/* Check that the flags fit in the type */	\
852 		BUILD_BUG_ON((sizeof(*_fset) * 8) <= __fls(m));	\
853 	} while (0)
854 
855 #define __vcpu_get_flag(v, flagset, f, m)			\
856 	({							\
857 		__build_check_flag(v, flagset, f, m);		\
858 								\
859 		READ_ONCE(v->arch.flagset) & (m);		\
860 	})
861 
862 /*
863  * Note that the set/clear accessors must be preempt-safe in order to
864  * avoid nesting them with load/put which also manipulate flags...
865  */
866 #ifdef __KVM_NVHE_HYPERVISOR__
867 /* the nVHE hypervisor is always non-preemptible */
868 #define __vcpu_flags_preempt_disable()
869 #define __vcpu_flags_preempt_enable()
870 #else
871 #define __vcpu_flags_preempt_disable()	preempt_disable()
872 #define __vcpu_flags_preempt_enable()	preempt_enable()
873 #endif
874 
875 #define __vcpu_set_flag(v, flagset, f, m)			\
876 	do {							\
877 		typeof(v->arch.flagset) *fset;			\
878 								\
879 		__build_check_flag(v, flagset, f, m);		\
880 								\
881 		fset = &v->arch.flagset;			\
882 		__vcpu_flags_preempt_disable();			\
883 		if (HWEIGHT(m) > 1)				\
884 			*fset &= ~(m);				\
885 		*fset |= (f);					\
886 		__vcpu_flags_preempt_enable();			\
887 	} while (0)
888 
889 #define __vcpu_clear_flag(v, flagset, f, m)			\
890 	do {							\
891 		typeof(v->arch.flagset) *fset;			\
892 								\
893 		__build_check_flag(v, flagset, f, m);		\
894 								\
895 		fset = &v->arch.flagset;			\
896 		__vcpu_flags_preempt_disable();			\
897 		*fset &= ~(m);					\
898 		__vcpu_flags_preempt_enable();			\
899 	} while (0)
900 
901 #define vcpu_get_flag(v, ...)	__vcpu_get_flag((v), __VA_ARGS__)
902 #define vcpu_set_flag(v, ...)	__vcpu_set_flag((v), __VA_ARGS__)
903 #define vcpu_clear_flag(v, ...)	__vcpu_clear_flag((v), __VA_ARGS__)
904 
905 /* KVM_ARM_VCPU_INIT completed */
906 #define VCPU_INITIALIZED	__vcpu_single_flag(cflags, BIT(0))
907 /* SVE config completed */
908 #define VCPU_SVE_FINALIZED	__vcpu_single_flag(cflags, BIT(1))
909 /* pKVM VCPU setup completed */
910 #define VCPU_PKVM_FINALIZED	__vcpu_single_flag(cflags, BIT(2))
911 
912 /* Exception pending */
913 #define PENDING_EXCEPTION	__vcpu_single_flag(iflags, BIT(0))
914 /*
915  * PC increment. Overlaps with EXCEPT_MASK on purpose so that it can't
916  * be set together with an exception...
917  */
918 #define INCREMENT_PC		__vcpu_single_flag(iflags, BIT(1))
919 /* Target EL/MODE (not a single flag, but let's abuse the macro) */
920 #define EXCEPT_MASK		__vcpu_single_flag(iflags, GENMASK(3, 1))
921 
922 /* Helpers to encode exceptions with minimum fuss */
923 #define __EXCEPT_MASK_VAL	unpack_vcpu_flag(EXCEPT_MASK)
924 #define __EXCEPT_SHIFT		__builtin_ctzl(__EXCEPT_MASK_VAL)
925 #define __vcpu_except_flags(_f)	iflags, (_f << __EXCEPT_SHIFT), __EXCEPT_MASK_VAL
926 
927 /*
928  * When PENDING_EXCEPTION is set, EXCEPT_MASK can take the following
929  * values:
930  *
931  * For AArch32 EL1:
932  */
933 #define EXCEPT_AA32_UND		__vcpu_except_flags(0)
934 #define EXCEPT_AA32_IABT	__vcpu_except_flags(1)
935 #define EXCEPT_AA32_DABT	__vcpu_except_flags(2)
936 /* For AArch64: */
937 #define EXCEPT_AA64_EL1_SYNC	__vcpu_except_flags(0)
938 #define EXCEPT_AA64_EL1_IRQ	__vcpu_except_flags(1)
939 #define EXCEPT_AA64_EL1_FIQ	__vcpu_except_flags(2)
940 #define EXCEPT_AA64_EL1_SERR	__vcpu_except_flags(3)
941 /* For AArch64 with NV: */
942 #define EXCEPT_AA64_EL2_SYNC	__vcpu_except_flags(4)
943 #define EXCEPT_AA64_EL2_IRQ	__vcpu_except_flags(5)
944 #define EXCEPT_AA64_EL2_FIQ	__vcpu_except_flags(6)
945 #define EXCEPT_AA64_EL2_SERR	__vcpu_except_flags(7)
946 
947 /* Physical CPU not in supported_cpus */
948 #define ON_UNSUPPORTED_CPU	__vcpu_single_flag(sflags, BIT(0))
949 /* WFIT instruction trapped */
950 #define IN_WFIT			__vcpu_single_flag(sflags, BIT(1))
951 /* vcpu system registers loaded on physical CPU */
952 #define SYSREGS_ON_CPU		__vcpu_single_flag(sflags, BIT(2))
953 /* Software step state is Active-pending for external debug */
954 #define HOST_SS_ACTIVE_PENDING	__vcpu_single_flag(sflags, BIT(3))
955 /* Software step state is Active pending for guest debug */
956 #define GUEST_SS_ACTIVE_PENDING __vcpu_single_flag(sflags, BIT(4))
957 /* PMUSERENR for the guest EL0 is on physical CPU */
958 #define PMUSERENR_ON_CPU	__vcpu_single_flag(sflags, BIT(5))
959 /* WFI instruction trapped */
960 #define IN_WFI			__vcpu_single_flag(sflags, BIT(6))
961 /* KVM is currently emulating a nested ERET */
962 #define IN_NESTED_ERET		__vcpu_single_flag(sflags, BIT(7))
963 
964 
965 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */
966 #define vcpu_sve_pffr(vcpu) (kern_hyp_va((vcpu)->arch.sve_state) +	\
967 			     sve_ffr_offset((vcpu)->arch.sve_max_vl))
968 
969 #define vcpu_sve_max_vq(vcpu)	sve_vq_from_vl((vcpu)->arch.sve_max_vl)
970 
971 #define vcpu_sve_zcr_elx(vcpu)						\
972 	(unlikely(is_hyp_ctxt(vcpu)) ? ZCR_EL2 : ZCR_EL1)
973 
974 #define vcpu_sve_state_size(vcpu) ({					\
975 	size_t __size_ret;						\
976 	unsigned int __vcpu_vq;						\
977 									\
978 	if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) {		\
979 		__size_ret = 0;						\
980 	} else {							\
981 		__vcpu_vq = vcpu_sve_max_vq(vcpu);			\
982 		__size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq);		\
983 	}								\
984 									\
985 	__size_ret;							\
986 })
987 
988 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \
989 				 KVM_GUESTDBG_USE_SW_BP | \
990 				 KVM_GUESTDBG_USE_HW | \
991 				 KVM_GUESTDBG_SINGLESTEP)
992 
993 #define kvm_has_sve(kvm)	(system_supports_sve() &&		\
994 				 test_bit(KVM_ARCH_FLAG_GUEST_HAS_SVE, &(kvm)->arch.flags))
995 
996 #ifdef __KVM_NVHE_HYPERVISOR__
997 #define vcpu_has_sve(vcpu)	kvm_has_sve(kern_hyp_va((vcpu)->kvm))
998 #else
999 #define vcpu_has_sve(vcpu)	kvm_has_sve((vcpu)->kvm)
1000 #endif
1001 
1002 #ifdef CONFIG_ARM64_PTR_AUTH
1003 #define vcpu_has_ptrauth(vcpu)						\
1004 	((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) ||		\
1005 	  cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) &&		\
1006 	 (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_ADDRESS) ||       \
1007 	  vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_GENERIC)))
1008 #else
1009 #define vcpu_has_ptrauth(vcpu)		false
1010 #endif
1011 
1012 #define vcpu_on_unsupported_cpu(vcpu)					\
1013 	vcpu_get_flag(vcpu, ON_UNSUPPORTED_CPU)
1014 
1015 #define vcpu_set_on_unsupported_cpu(vcpu)				\
1016 	vcpu_set_flag(vcpu, ON_UNSUPPORTED_CPU)
1017 
1018 #define vcpu_clear_on_unsupported_cpu(vcpu)				\
1019 	vcpu_clear_flag(vcpu, ON_UNSUPPORTED_CPU)
1020 
1021 #define vcpu_gp_regs(v)		(&(v)->arch.ctxt.regs)
1022 
1023 /*
1024  * Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the
1025  * memory backed version of a register, and not the one most recently
1026  * accessed by a running VCPU.  For example, for userspace access or
1027  * for system registers that are never context switched, but only
1028  * emulated.
1029  *
1030  * Don't bother with VNCR-based accesses in the nVHE code, it has no
1031  * business dealing with NV.
1032  */
___ctxt_sys_reg(const struct kvm_cpu_context * ctxt,int r)1033 static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r)
1034 {
1035 #if !defined (__KVM_NVHE_HYPERVISOR__)
1036 	if (unlikely(cpus_have_final_cap(ARM64_HAS_NESTED_VIRT) &&
1037 		     r >= __VNCR_START__ && ctxt->vncr_array))
1038 		return &ctxt->vncr_array[r - __VNCR_START__];
1039 #endif
1040 	return (u64 *)&ctxt->sys_regs[r];
1041 }
1042 
1043 #define __ctxt_sys_reg(c,r)						\
1044 	({								\
1045 		BUILD_BUG_ON(__builtin_constant_p(r) &&			\
1046 			     (r) >= NR_SYS_REGS);			\
1047 		___ctxt_sys_reg(c, r);					\
1048 	})
1049 
1050 #define ctxt_sys_reg(c,r)	(*__ctxt_sys_reg(c,r))
1051 
1052 u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64);
1053 #define __vcpu_sys_reg(v,r)						\
1054 	(*({								\
1055 		const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt;	\
1056 		u64 *__r = __ctxt_sys_reg(ctxt, (r));			\
1057 		if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__)	\
1058 			*__r = kvm_vcpu_apply_reg_masks((v), (r), *__r);\
1059 		__r;							\
1060 	}))
1061 
1062 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);
1063 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
1064 
__vcpu_read_sys_reg_from_cpu(int reg,u64 * val)1065 static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val)
1066 {
1067 	/*
1068 	 * *** VHE ONLY ***
1069 	 *
1070 	 * System registers listed in the switch are not saved on every
1071 	 * exit from the guest but are only saved on vcpu_put.
1072 	 *
1073 	 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
1074 	 * should never be listed below, because the guest cannot modify its
1075 	 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
1076 	 * thread when emulating cross-VCPU communication.
1077 	 */
1078 	if (!has_vhe())
1079 		return false;
1080 
1081 	switch (reg) {
1082 	case SCTLR_EL1:		*val = read_sysreg_s(SYS_SCTLR_EL12);	break;
1083 	case CPACR_EL1:		*val = read_sysreg_s(SYS_CPACR_EL12);	break;
1084 	case TTBR0_EL1:		*val = read_sysreg_s(SYS_TTBR0_EL12);	break;
1085 	case TTBR1_EL1:		*val = read_sysreg_s(SYS_TTBR1_EL12);	break;
1086 	case TCR_EL1:		*val = read_sysreg_s(SYS_TCR_EL12);	break;
1087 	case TCR2_EL1:		*val = read_sysreg_s(SYS_TCR2_EL12);	break;
1088 	case PIR_EL1:		*val = read_sysreg_s(SYS_PIR_EL12);	break;
1089 	case PIRE0_EL1:		*val = read_sysreg_s(SYS_PIRE0_EL12);	break;
1090 	case POR_EL1:		*val = read_sysreg_s(SYS_POR_EL12);	break;
1091 	case ESR_EL1:		*val = read_sysreg_s(SYS_ESR_EL12);	break;
1092 	case AFSR0_EL1:		*val = read_sysreg_s(SYS_AFSR0_EL12);	break;
1093 	case AFSR1_EL1:		*val = read_sysreg_s(SYS_AFSR1_EL12);	break;
1094 	case FAR_EL1:		*val = read_sysreg_s(SYS_FAR_EL12);	break;
1095 	case MAIR_EL1:		*val = read_sysreg_s(SYS_MAIR_EL12);	break;
1096 	case VBAR_EL1:		*val = read_sysreg_s(SYS_VBAR_EL12);	break;
1097 	case CONTEXTIDR_EL1:	*val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break;
1098 	case TPIDR_EL0:		*val = read_sysreg_s(SYS_TPIDR_EL0);	break;
1099 	case TPIDRRO_EL0:	*val = read_sysreg_s(SYS_TPIDRRO_EL0);	break;
1100 	case TPIDR_EL1:		*val = read_sysreg_s(SYS_TPIDR_EL1);	break;
1101 	case AMAIR_EL1:		*val = read_sysreg_s(SYS_AMAIR_EL12);	break;
1102 	case CNTKCTL_EL1:	*val = read_sysreg_s(SYS_CNTKCTL_EL12);	break;
1103 	case ELR_EL1:		*val = read_sysreg_s(SYS_ELR_EL12);	break;
1104 	case SPSR_EL1:		*val = read_sysreg_s(SYS_SPSR_EL12);	break;
1105 	case PAR_EL1:		*val = read_sysreg_par();		break;
1106 	case DACR32_EL2:	*val = read_sysreg_s(SYS_DACR32_EL2);	break;
1107 	case IFSR32_EL2:	*val = read_sysreg_s(SYS_IFSR32_EL2);	break;
1108 	case DBGVCR32_EL2:	*val = read_sysreg_s(SYS_DBGVCR32_EL2);	break;
1109 	case ZCR_EL1:		*val = read_sysreg_s(SYS_ZCR_EL12);	break;
1110 	default:		return false;
1111 	}
1112 
1113 	return true;
1114 }
1115 
__vcpu_write_sys_reg_to_cpu(u64 val,int reg)1116 static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg)
1117 {
1118 	/*
1119 	 * *** VHE ONLY ***
1120 	 *
1121 	 * System registers listed in the switch are not restored on every
1122 	 * entry to the guest but are only restored on vcpu_load.
1123 	 *
1124 	 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
1125 	 * should never be listed below, because the MPIDR should only be set
1126 	 * once, before running the VCPU, and never changed later.
1127 	 */
1128 	if (!has_vhe())
1129 		return false;
1130 
1131 	switch (reg) {
1132 	case SCTLR_EL1:		write_sysreg_s(val, SYS_SCTLR_EL12);	break;
1133 	case CPACR_EL1:		write_sysreg_s(val, SYS_CPACR_EL12);	break;
1134 	case TTBR0_EL1:		write_sysreg_s(val, SYS_TTBR0_EL12);	break;
1135 	case TTBR1_EL1:		write_sysreg_s(val, SYS_TTBR1_EL12);	break;
1136 	case TCR_EL1:		write_sysreg_s(val, SYS_TCR_EL12);	break;
1137 	case TCR2_EL1:		write_sysreg_s(val, SYS_TCR2_EL12);	break;
1138 	case PIR_EL1:		write_sysreg_s(val, SYS_PIR_EL12);	break;
1139 	case PIRE0_EL1:		write_sysreg_s(val, SYS_PIRE0_EL12);	break;
1140 	case POR_EL1:		write_sysreg_s(val, SYS_POR_EL12);	break;
1141 	case ESR_EL1:		write_sysreg_s(val, SYS_ESR_EL12);	break;
1142 	case AFSR0_EL1:		write_sysreg_s(val, SYS_AFSR0_EL12);	break;
1143 	case AFSR1_EL1:		write_sysreg_s(val, SYS_AFSR1_EL12);	break;
1144 	case FAR_EL1:		write_sysreg_s(val, SYS_FAR_EL12);	break;
1145 	case MAIR_EL1:		write_sysreg_s(val, SYS_MAIR_EL12);	break;
1146 	case VBAR_EL1:		write_sysreg_s(val, SYS_VBAR_EL12);	break;
1147 	case CONTEXTIDR_EL1:	write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break;
1148 	case TPIDR_EL0:		write_sysreg_s(val, SYS_TPIDR_EL0);	break;
1149 	case TPIDRRO_EL0:	write_sysreg_s(val, SYS_TPIDRRO_EL0);	break;
1150 	case TPIDR_EL1:		write_sysreg_s(val, SYS_TPIDR_EL1);	break;
1151 	case AMAIR_EL1:		write_sysreg_s(val, SYS_AMAIR_EL12);	break;
1152 	case CNTKCTL_EL1:	write_sysreg_s(val, SYS_CNTKCTL_EL12);	break;
1153 	case ELR_EL1:		write_sysreg_s(val, SYS_ELR_EL12);	break;
1154 	case SPSR_EL1:		write_sysreg_s(val, SYS_SPSR_EL12);	break;
1155 	case PAR_EL1:		write_sysreg_s(val, SYS_PAR_EL1);	break;
1156 	case DACR32_EL2:	write_sysreg_s(val, SYS_DACR32_EL2);	break;
1157 	case IFSR32_EL2:	write_sysreg_s(val, SYS_IFSR32_EL2);	break;
1158 	case DBGVCR32_EL2:	write_sysreg_s(val, SYS_DBGVCR32_EL2);	break;
1159 	case ZCR_EL1:		write_sysreg_s(val, SYS_ZCR_EL12);	break;
1160 	default:		return false;
1161 	}
1162 
1163 	return true;
1164 }
1165 
1166 struct kvm_vm_stat {
1167 	struct kvm_vm_stat_generic generic;
1168 };
1169 
1170 struct kvm_vcpu_stat {
1171 	struct kvm_vcpu_stat_generic generic;
1172 	u64 hvc_exit_stat;
1173 	u64 wfe_exit_stat;
1174 	u64 wfi_exit_stat;
1175 	u64 mmio_exit_user;
1176 	u64 mmio_exit_kernel;
1177 	u64 signal_exits;
1178 	u64 exits;
1179 };
1180 
1181 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
1182 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
1183 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
1184 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
1185 
1186 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu);
1187 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
1188 
1189 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
1190 			      struct kvm_vcpu_events *events);
1191 
1192 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
1193 			      struct kvm_vcpu_events *events);
1194 
1195 void kvm_arm_halt_guest(struct kvm *kvm);
1196 void kvm_arm_resume_guest(struct kvm *kvm);
1197 
1198 #define vcpu_has_run_once(vcpu)	(!!READ_ONCE((vcpu)->pid))
1199 
1200 #ifndef __KVM_NVHE_HYPERVISOR__
1201 #define kvm_call_hyp_nvhe(f, ...)						\
1202 	({								\
1203 		struct arm_smccc_res res;				\
1204 									\
1205 		arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f),		\
1206 				  ##__VA_ARGS__, &res);			\
1207 		WARN_ON(res.a0 != SMCCC_RET_SUCCESS);			\
1208 									\
1209 		res.a1;							\
1210 	})
1211 
1212 /*
1213  * The couple of isb() below are there to guarantee the same behaviour
1214  * on VHE as on !VHE, where the eret to EL1 acts as a context
1215  * synchronization event.
1216  */
1217 #define kvm_call_hyp(f, ...)						\
1218 	do {								\
1219 		if (has_vhe()) {					\
1220 			f(__VA_ARGS__);					\
1221 			isb();						\
1222 		} else {						\
1223 			kvm_call_hyp_nvhe(f, ##__VA_ARGS__);		\
1224 		}							\
1225 	} while(0)
1226 
1227 #define kvm_call_hyp_ret(f, ...)					\
1228 	({								\
1229 		typeof(f(__VA_ARGS__)) ret;				\
1230 									\
1231 		if (has_vhe()) {					\
1232 			ret = f(__VA_ARGS__);				\
1233 			isb();						\
1234 		} else {						\
1235 			ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__);	\
1236 		}							\
1237 									\
1238 		ret;							\
1239 	})
1240 #else /* __KVM_NVHE_HYPERVISOR__ */
1241 #define kvm_call_hyp(f, ...) f(__VA_ARGS__)
1242 #define kvm_call_hyp_ret(f, ...) f(__VA_ARGS__)
1243 #define kvm_call_hyp_nvhe(f, ...) f(__VA_ARGS__)
1244 #endif /* __KVM_NVHE_HYPERVISOR__ */
1245 
1246 int handle_exit(struct kvm_vcpu *vcpu, int exception_index);
1247 void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index);
1248 
1249 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu);
1250 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu);
1251 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu);
1252 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu);
1253 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu);
1254 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu);
1255 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu);
1256 
1257 void kvm_sys_regs_create_debugfs(struct kvm *kvm);
1258 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
1259 
1260 int __init kvm_sys_reg_table_init(void);
1261 struct sys_reg_desc;
1262 int __init populate_sysreg_config(const struct sys_reg_desc *sr,
1263 				  unsigned int idx);
1264 int __init populate_nv_trap_config(void);
1265 
1266 bool lock_all_vcpus(struct kvm *kvm);
1267 void unlock_all_vcpus(struct kvm *kvm);
1268 
1269 void kvm_calculate_traps(struct kvm_vcpu *vcpu);
1270 
1271 /* MMIO helpers */
1272 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data);
1273 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len);
1274 
1275 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu);
1276 int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa);
1277 
1278 /*
1279  * Returns true if a Performance Monitoring Interrupt (PMI), a.k.a. perf event,
1280  * arrived in guest context.  For arm64, any event that arrives while a vCPU is
1281  * loaded is considered to be "in guest".
1282  */
kvm_arch_pmi_in_guest(struct kvm_vcpu * vcpu)1283 static inline bool kvm_arch_pmi_in_guest(struct kvm_vcpu *vcpu)
1284 {
1285 	return IS_ENABLED(CONFIG_GUEST_PERF_EVENTS) && !!vcpu;
1286 }
1287 
1288 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu);
1289 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu);
1290 void kvm_update_stolen_time(struct kvm_vcpu *vcpu);
1291 
1292 bool kvm_arm_pvtime_supported(void);
1293 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu,
1294 			    struct kvm_device_attr *attr);
1295 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu,
1296 			    struct kvm_device_attr *attr);
1297 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu,
1298 			    struct kvm_device_attr *attr);
1299 
1300 extern unsigned int __ro_after_init kvm_arm_vmid_bits;
1301 int __init kvm_arm_vmid_alloc_init(void);
1302 void __init kvm_arm_vmid_alloc_free(void);
1303 void kvm_arm_vmid_update(struct kvm_vmid *kvm_vmid);
1304 void kvm_arm_vmid_clear_active(void);
1305 
kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch * vcpu_arch)1306 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch)
1307 {
1308 	vcpu_arch->steal.base = INVALID_GPA;
1309 }
1310 
kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch * vcpu_arch)1311 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch)
1312 {
1313 	return (vcpu_arch->steal.base != INVALID_GPA);
1314 }
1315 
1316 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
1317 
1318 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
1319 
1320 DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data);
1321 
1322 /*
1323  * How we access per-CPU host data depends on the where we access it from,
1324  * and the mode we're in:
1325  *
1326  * - VHE and nVHE hypervisor bits use their locally defined instance
1327  *
1328  * - the rest of the kernel use either the VHE or nVHE one, depending on
1329  *   the mode we're running in.
1330  *
1331  *   Unless we're in protected mode, fully deprivileged, and the nVHE
1332  *   per-CPU stuff is exclusively accessible to the protected EL2 code.
1333  *   In this case, the EL1 code uses the *VHE* data as its private state
1334  *   (which makes sense in a way as there shouldn't be any shared state
1335  *   between the host and the hypervisor).
1336  *
1337  * Yes, this is all totally trivial. Shoot me now.
1338  */
1339 #if defined(__KVM_NVHE_HYPERVISOR__) || defined(__KVM_VHE_HYPERVISOR__)
1340 #define host_data_ptr(f)	(&this_cpu_ptr(&kvm_host_data)->f)
1341 #else
1342 #define host_data_ptr(f)						\
1343 	(static_branch_unlikely(&kvm_protected_mode_initialized) ?	\
1344 	 &this_cpu_ptr(&kvm_host_data)->f :				\
1345 	 &this_cpu_ptr_hyp_sym(kvm_host_data)->f)
1346 #endif
1347 
1348 #define host_data_test_flag(flag)					\
1349 	(test_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags)))
1350 #define host_data_set_flag(flag)					\
1351 	set_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags))
1352 #define host_data_clear_flag(flag)					\
1353 	clear_bit(KVM_HOST_DATA_FLAG_##flag, host_data_ptr(flags))
1354 
1355 /* Check whether the FP regs are owned by the guest */
guest_owns_fp_regs(void)1356 static inline bool guest_owns_fp_regs(void)
1357 {
1358 	return *host_data_ptr(fp_owner) == FP_STATE_GUEST_OWNED;
1359 }
1360 
1361 /* Check whether the FP regs are owned by the host */
host_owns_fp_regs(void)1362 static inline bool host_owns_fp_regs(void)
1363 {
1364 	return *host_data_ptr(fp_owner) == FP_STATE_HOST_OWNED;
1365 }
1366 
kvm_init_host_cpu_context(struct kvm_cpu_context * cpu_ctxt)1367 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt)
1368 {
1369 	/* The host's MPIDR is immutable, so let's set it up at boot time */
1370 	ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr();
1371 }
1372 
kvm_system_needs_idmapped_vectors(void)1373 static inline bool kvm_system_needs_idmapped_vectors(void)
1374 {
1375 	return cpus_have_final_cap(ARM64_SPECTRE_V3A);
1376 }
1377 
1378 void kvm_init_host_debug_data(void);
1379 void kvm_vcpu_load_debug(struct kvm_vcpu *vcpu);
1380 void kvm_vcpu_put_debug(struct kvm_vcpu *vcpu);
1381 void kvm_debug_set_guest_ownership(struct kvm_vcpu *vcpu);
1382 void kvm_debug_handle_oslar(struct kvm_vcpu *vcpu, u64 val);
1383 
1384 #define kvm_vcpu_os_lock_enabled(vcpu)		\
1385 	(!!(__vcpu_sys_reg(vcpu, OSLSR_EL1) & OSLSR_EL1_OSLK))
1386 
1387 #define kvm_debug_regs_in_use(vcpu)		\
1388 	((vcpu)->arch.debug_owner != VCPU_DEBUG_FREE)
1389 #define kvm_host_owns_debug_regs(vcpu)		\
1390 	((vcpu)->arch.debug_owner == VCPU_DEBUG_HOST_OWNED)
1391 #define kvm_guest_owns_debug_regs(vcpu)		\
1392 	((vcpu)->arch.debug_owner == VCPU_DEBUG_GUEST_OWNED)
1393 
1394 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
1395 			       struct kvm_device_attr *attr);
1396 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
1397 			       struct kvm_device_attr *attr);
1398 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
1399 			       struct kvm_device_attr *attr);
1400 
1401 int kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
1402 			       struct kvm_arm_copy_mte_tags *copy_tags);
1403 int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm,
1404 				    struct kvm_arm_counter_offset *offset);
1405 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm,
1406 					struct reg_mask_range *range);
1407 
1408 /* Guest/host FPSIMD coordination helpers */
1409 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
1410 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
1411 void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu);
1412 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
1413 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
1414 
kvm_pmu_counter_deferred(struct perf_event_attr * attr)1415 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr)
1416 {
1417 	return (!has_vhe() && attr->exclude_host);
1418 }
1419 
1420 #ifdef CONFIG_KVM
1421 void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr);
1422 void kvm_clr_pmu_events(u64 clr);
1423 bool kvm_set_pmuserenr(u64 val);
1424 void kvm_enable_trbe(void);
1425 void kvm_disable_trbe(void);
1426 void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest);
1427 #else
kvm_set_pmu_events(u64 set,struct perf_event_attr * attr)1428 static inline void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr) {}
kvm_clr_pmu_events(u64 clr)1429 static inline void kvm_clr_pmu_events(u64 clr) {}
kvm_set_pmuserenr(u64 val)1430 static inline bool kvm_set_pmuserenr(u64 val)
1431 {
1432 	return false;
1433 }
kvm_enable_trbe(void)1434 static inline void kvm_enable_trbe(void) {}
kvm_disable_trbe(void)1435 static inline void kvm_disable_trbe(void) {}
kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest)1436 static inline void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest) {}
1437 #endif
1438 
1439 void kvm_vcpu_load_vhe(struct kvm_vcpu *vcpu);
1440 void kvm_vcpu_put_vhe(struct kvm_vcpu *vcpu);
1441 
1442 int __init kvm_set_ipa_limit(void);
1443 u32 kvm_get_pa_bits(struct kvm *kvm);
1444 
1445 #define __KVM_HAVE_ARCH_VM_ALLOC
1446 struct kvm *kvm_arch_alloc_vm(void);
1447 
1448 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS
1449 
1450 #define __KVM_HAVE_ARCH_FLUSH_REMOTE_TLBS_RANGE
1451 
1452 #define kvm_vm_is_protected(kvm)	(is_protected_kvm_enabled() && (kvm)->arch.pkvm.enabled)
1453 
1454 #define vcpu_is_protected(vcpu)		kvm_vm_is_protected((vcpu)->kvm)
1455 
1456 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature);
1457 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
1458 
1459 #define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINALIZED)
1460 
1461 #define kvm_has_mte(kvm)					\
1462 	(system_supports_mte() &&				\
1463 	 test_bit(KVM_ARCH_FLAG_MTE_ENABLED, &(kvm)->arch.flags))
1464 
1465 #define kvm_supports_32bit_el0()				\
1466 	(system_supports_32bit_el0() &&				\
1467 	 !static_branch_unlikely(&arm64_mismatched_32bit_el0))
1468 
1469 #define kvm_vm_has_ran_once(kvm)					\
1470 	(test_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &(kvm)->arch.flags))
1471 
__vcpu_has_feature(const struct kvm_arch * ka,int feature)1472 static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature)
1473 {
1474 	return test_bit(feature, ka->vcpu_features);
1475 }
1476 
1477 #define kvm_vcpu_has_feature(k, f)	__vcpu_has_feature(&(k)->arch, (f))
1478 #define vcpu_has_feature(v, f)	__vcpu_has_feature(&(v)->kvm->arch, (f))
1479 
1480 #define kvm_vcpu_initialized(v) vcpu_get_flag(vcpu, VCPU_INITIALIZED)
1481 
1482 int kvm_trng_call(struct kvm_vcpu *vcpu);
1483 #ifdef CONFIG_KVM
1484 extern phys_addr_t hyp_mem_base;
1485 extern phys_addr_t hyp_mem_size;
1486 void __init kvm_hyp_reserve(void);
1487 #else
kvm_hyp_reserve(void)1488 static inline void kvm_hyp_reserve(void) { }
1489 #endif
1490 
1491 void kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu);
1492 bool kvm_arm_vcpu_stopped(struct kvm_vcpu *vcpu);
1493 
__vm_id_reg(struct kvm_arch * ka,u32 reg)1494 static inline u64 *__vm_id_reg(struct kvm_arch *ka, u32 reg)
1495 {
1496 	switch (reg) {
1497 	case sys_reg(3, 0, 0, 1, 0) ... sys_reg(3, 0, 0, 7, 7):
1498 		return &ka->id_regs[IDREG_IDX(reg)];
1499 	case SYS_CTR_EL0:
1500 		return &ka->ctr_el0;
1501 	case SYS_MIDR_EL1:
1502 		return &ka->midr_el1;
1503 	case SYS_REVIDR_EL1:
1504 		return &ka->revidr_el1;
1505 	case SYS_AIDR_EL1:
1506 		return &ka->aidr_el1;
1507 	default:
1508 		WARN_ON_ONCE(1);
1509 		return NULL;
1510 	}
1511 }
1512 
1513 #define kvm_read_vm_id_reg(kvm, reg)					\
1514 	({ u64 __val = *__vm_id_reg(&(kvm)->arch, reg); __val; })
1515 
1516 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val);
1517 
1518 #define __expand_field_sign_unsigned(id, fld, val)			\
1519 	((u64)SYS_FIELD_VALUE(id, fld, val))
1520 
1521 #define __expand_field_sign_signed(id, fld, val)			\
1522 	({								\
1523 		u64 __val = SYS_FIELD_VALUE(id, fld, val);		\
1524 		sign_extend64(__val, id##_##fld##_WIDTH - 1);		\
1525 	})
1526 
1527 #define get_idreg_field_unsigned(kvm, id, fld)				\
1528 	({								\
1529 		u64 __val = kvm_read_vm_id_reg((kvm), SYS_##id);	\
1530 		FIELD_GET(id##_##fld##_MASK, __val);			\
1531 	})
1532 
1533 #define get_idreg_field_signed(kvm, id, fld)				\
1534 	({								\
1535 		u64 __val = get_idreg_field_unsigned(kvm, id, fld);	\
1536 		sign_extend64(__val, id##_##fld##_WIDTH - 1);		\
1537 	})
1538 
1539 #define get_idreg_field_enum(kvm, id, fld)				\
1540 	get_idreg_field_unsigned(kvm, id, fld)
1541 
1542 #define kvm_cmp_feat_signed(kvm, id, fld, op, limit)			\
1543 	(get_idreg_field_signed((kvm), id, fld) op __expand_field_sign_signed(id, fld, limit))
1544 
1545 #define kvm_cmp_feat_unsigned(kvm, id, fld, op, limit)			\
1546 	(get_idreg_field_unsigned((kvm), id, fld) op __expand_field_sign_unsigned(id, fld, limit))
1547 
1548 #define kvm_cmp_feat(kvm, id, fld, op, limit)				\
1549 	(id##_##fld##_SIGNED ?						\
1550 	 kvm_cmp_feat_signed(kvm, id, fld, op, limit) :			\
1551 	 kvm_cmp_feat_unsigned(kvm, id, fld, op, limit))
1552 
1553 #define kvm_has_feat(kvm, id, fld, limit)				\
1554 	kvm_cmp_feat(kvm, id, fld, >=, limit)
1555 
1556 #define kvm_has_feat_enum(kvm, id, fld, val)				\
1557 	kvm_cmp_feat_unsigned(kvm, id, fld, ==, val)
1558 
1559 #define kvm_has_feat_range(kvm, id, fld, min, max)			\
1560 	(kvm_cmp_feat(kvm, id, fld, >=, min) &&				\
1561 	kvm_cmp_feat(kvm, id, fld, <=, max))
1562 
1563 /* Check for a given level of PAuth support */
1564 #define kvm_has_pauth(k, l)						\
1565 	({								\
1566 		bool pa, pi, pa3;					\
1567 									\
1568 		pa  = kvm_has_feat((k), ID_AA64ISAR1_EL1, APA, l);	\
1569 		pa &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPA, IMP);	\
1570 		pi  = kvm_has_feat((k), ID_AA64ISAR1_EL1, API, l);	\
1571 		pi &= kvm_has_feat((k), ID_AA64ISAR1_EL1, GPI, IMP);	\
1572 		pa3  = kvm_has_feat((k), ID_AA64ISAR2_EL1, APA3, l);	\
1573 		pa3 &= kvm_has_feat((k), ID_AA64ISAR2_EL1, GPA3, IMP);	\
1574 									\
1575 		(pa + pi + pa3) == 1;					\
1576 	})
1577 
1578 #define kvm_has_fpmr(k)					\
1579 	(system_supports_fpmr() &&			\
1580 	 kvm_has_feat((k), ID_AA64PFR2_EL1, FPMR, IMP))
1581 
1582 #define kvm_has_tcr2(k)				\
1583 	(kvm_has_feat((k), ID_AA64MMFR3_EL1, TCRX, IMP))
1584 
1585 #define kvm_has_s1pie(k)				\
1586 	(kvm_has_feat((k), ID_AA64MMFR3_EL1, S1PIE, IMP))
1587 
1588 #define kvm_has_s1poe(k)				\
1589 	(kvm_has_feat((k), ID_AA64MMFR3_EL1, S1POE, IMP))
1590 
1591 #endif /* __ARM64_KVM_HOST_H__ */
1592