1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #include <hyp/switch.h> 8 #include <hyp/sysreg-sr.h> 9 10 #include <linux/kvm_host.h> 11 #include <linux/types.h> 12 #include <linux/jump_label.h> 13 #include <uapi/linux/psci.h> 14 15 #include <kvm/arm_psci.h> 16 17 #include <asm/barrier.h> 18 #include <asm/cpufeature.h> 19 #include <asm/kprobes.h> 20 #include <asm/kvm_asm.h> 21 #include <asm/kvm_emulate.h> 22 #include <asm/kvm_hyp.h> 23 #include <asm/kvm_hypevents.h> 24 #include <asm/kvm_mmu.h> 25 #include <asm/fpsimd.h> 26 #include <asm/debug-monitors.h> 27 #include <asm/processor.h> 28 29 #include <nvhe/mem_protect.h> 30 31 /* Non-VHE specific context */ 32 DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); 33 DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); 34 DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); 35 36 struct fgt_masks hfgrtr_masks; 37 struct fgt_masks hfgwtr_masks; 38 struct fgt_masks hfgitr_masks; 39 struct fgt_masks hdfgrtr_masks; 40 struct fgt_masks hdfgwtr_masks; 41 struct fgt_masks hafgrtr_masks; 42 struct fgt_masks hfgrtr2_masks; 43 struct fgt_masks hfgwtr2_masks; 44 struct fgt_masks hfgitr2_masks; 45 struct fgt_masks hdfgrtr2_masks; 46 struct fgt_masks hdfgwtr2_masks; 47 struct fgt_masks ich_hfgrtr_masks; 48 struct fgt_masks ich_hfgwtr_masks; 49 struct fgt_masks ich_hfgitr_masks; 50 51 extern void kvm_nvhe_prepare_backtrace(unsigned long fp, unsigned long pc); 52 53 static void __activate_traps(struct kvm_vcpu *vcpu) 54 { 55 ___activate_traps(vcpu, vcpu->arch.hcr_el2); 56 57 *host_data_ptr(host_debug_state.mdcr_el2) = read_sysreg(mdcr_el2); 58 write_sysreg(vcpu->arch.mdcr_el2, mdcr_el2); 59 60 __activate_traps_common(vcpu); 61 __activate_cptr_traps(vcpu); 62 63 write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el2); 64 65 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { 66 struct kvm_cpu_context *ctxt = &vcpu->arch.ctxt; 67 68 isb(); 69 /* 70 * At this stage, and thanks to the above isb(), S2 is 71 * configured and enabled. We can now restore the guest's S1 72 * configuration: SCTLR, and only then TCR. 73 */ 74 write_sysreg_el1(ctxt_sys_reg(ctxt, SCTLR_EL1), SYS_SCTLR); 75 isb(); 76 write_sysreg_el1(ctxt_sys_reg(ctxt, TCR_EL1), SYS_TCR); 77 } 78 } 79 80 static void __deactivate_traps(struct kvm_vcpu *vcpu) 81 { 82 extern char __kvm_hyp_host_vector[]; 83 84 ___deactivate_traps(vcpu); 85 86 if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { 87 u64 val; 88 89 /* 90 * Set the TCR and SCTLR registers in the exact opposite 91 * sequence as __activate_traps (first prevent walks, 92 * then force the MMU on). A generous sprinkling of isb() 93 * ensure that things happen in this exact order. 94 */ 95 val = read_sysreg_el1(SYS_TCR); 96 write_sysreg_el1(val | TCR_EPD1_MASK | TCR_EPD0_MASK, SYS_TCR); 97 isb(); 98 val = read_sysreg_el1(SYS_SCTLR); 99 write_sysreg_el1(val | SCTLR_ELx_M, SYS_SCTLR); 100 isb(); 101 } 102 103 write_sysreg(*host_data_ptr(host_debug_state.mdcr_el2), mdcr_el2); 104 105 __deactivate_traps_common(vcpu); 106 107 write_sysreg_hcr(this_cpu_ptr(&kvm_init_params)->hcr_el2); 108 109 __deactivate_cptr_traps(vcpu); 110 write_sysreg(__kvm_hyp_host_vector, vbar_el2); 111 } 112 113 /* Save VGICv3 state on non-VHE systems */ 114 static void __hyp_vgic_save_state(struct kvm_vcpu *vcpu) 115 { 116 if (vgic_is_v5(kern_hyp_va(vcpu->kvm))) { 117 __vgic_v5_save_state(&vcpu->arch.vgic_cpu.vgic_v5); 118 __vgic_v5_save_ppi_state(&vcpu->arch.vgic_cpu.vgic_v5); 119 return; 120 } 121 122 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) { 123 __vgic_v3_save_state(&vcpu->arch.vgic_cpu.vgic_v3); 124 __vgic_v3_deactivate_traps(&vcpu->arch.vgic_cpu.vgic_v3); 125 } 126 } 127 128 /* Restore VGICv3 state on non-VHE systems */ 129 static void __hyp_vgic_restore_state(struct kvm_vcpu *vcpu) 130 { 131 if (vgic_is_v5(kern_hyp_va(vcpu->kvm))) { 132 __vgic_v5_restore_state(&vcpu->arch.vgic_cpu.vgic_v5); 133 __vgic_v5_restore_ppi_state(&vcpu->arch.vgic_cpu.vgic_v5); 134 return; 135 } 136 137 if (static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) { 138 __vgic_v3_activate_traps(&vcpu->arch.vgic_cpu.vgic_v3); 139 __vgic_v3_restore_state(&vcpu->arch.vgic_cpu.vgic_v3); 140 } 141 } 142 143 /* 144 * Disable host events, enable guest events 145 */ 146 #ifdef CONFIG_HW_PERF_EVENTS 147 static bool __pmu_switch_to_guest(struct kvm_vcpu *vcpu) 148 { 149 struct kvm_pmu_events *pmu = &vcpu->arch.pmu.events; 150 151 if (pmu->events_host) 152 write_sysreg(pmu->events_host, pmcntenclr_el0); 153 154 if (pmu->events_guest) 155 write_sysreg(pmu->events_guest, pmcntenset_el0); 156 157 return (pmu->events_host || pmu->events_guest); 158 } 159 160 /* 161 * Disable guest events, enable host events 162 */ 163 static void __pmu_switch_to_host(struct kvm_vcpu *vcpu) 164 { 165 struct kvm_pmu_events *pmu = &vcpu->arch.pmu.events; 166 167 if (pmu->events_guest) 168 write_sysreg(pmu->events_guest, pmcntenclr_el0); 169 170 if (pmu->events_host) 171 write_sysreg(pmu->events_host, pmcntenset_el0); 172 } 173 #else 174 #define __pmu_switch_to_guest(v) ({ false; }) 175 #define __pmu_switch_to_host(v) do {} while (0) 176 #endif 177 178 /* 179 * Handler for protected VM MSR, MRS or System instruction execution in AArch64. 180 * 181 * Returns true if the hypervisor has handled the exit, and control should go 182 * back to the guest, or false if it hasn't. 183 */ 184 static bool kvm_handle_pvm_sys64(struct kvm_vcpu *vcpu, u64 *exit_code) 185 { 186 /* 187 * Make sure we handle the exit for workarounds before the pKVM 188 * handling, as the latter could decide to UNDEF. 189 */ 190 return (kvm_hyp_handle_sysreg(vcpu, exit_code) || 191 kvm_handle_pvm_sysreg(vcpu, exit_code)); 192 } 193 194 static const exit_handler_fn hyp_exit_handlers[] = { 195 [0 ... ESR_ELx_EC_MAX] = NULL, 196 [ESR_ELx_EC_CP15_32] = kvm_hyp_handle_cp15_32, 197 [ESR_ELx_EC_SYS64] = kvm_hyp_handle_sysreg, 198 [ESR_ELx_EC_SVE] = kvm_hyp_handle_fpsimd, 199 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd, 200 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low, 201 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low, 202 [ESR_ELx_EC_WATCHPT_LOW] = kvm_hyp_handle_watchpt_low, 203 [ESR_ELx_EC_MOPS] = kvm_hyp_handle_mops, 204 }; 205 206 static const exit_handler_fn pvm_exit_handlers[] = { 207 [0 ... ESR_ELx_EC_MAX] = NULL, 208 [ESR_ELx_EC_HVC64] = kvm_handle_pvm_hvc64, 209 [ESR_ELx_EC_SYS64] = kvm_handle_pvm_sys64, 210 [ESR_ELx_EC_SVE] = kvm_handle_pvm_restricted, 211 [ESR_ELx_EC_FP_ASIMD] = kvm_hyp_handle_fpsimd, 212 [ESR_ELx_EC_IABT_LOW] = kvm_hyp_handle_iabt_low, 213 [ESR_ELx_EC_DABT_LOW] = kvm_hyp_handle_dabt_low, 214 [ESR_ELx_EC_WATCHPT_LOW] = kvm_hyp_handle_watchpt_low, 215 [ESR_ELx_EC_MOPS] = kvm_hyp_handle_mops, 216 }; 217 218 static const exit_handler_fn *kvm_get_exit_handler_array(struct kvm_vcpu *vcpu) 219 { 220 if (unlikely(vcpu_is_protected(vcpu))) 221 return pvm_exit_handlers; 222 223 return hyp_exit_handlers; 224 } 225 226 static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code) 227 { 228 const exit_handler_fn *handlers = kvm_get_exit_handler_array(vcpu); 229 230 synchronize_vcpu_pstate(vcpu); 231 232 /* 233 * Some guests (e.g., protected VMs) are not be allowed to run in 234 * AArch32. The ARMv8 architecture does not give the hypervisor a 235 * mechanism to prevent a guest from dropping to AArch32 EL0 if 236 * implemented by the CPU. If the hypervisor spots a guest in such a 237 * state ensure it is handled, and don't trust the host to spot or fix 238 * it. The check below is based on the one in 239 * kvm_arch_vcpu_ioctl_run(). 240 */ 241 if (unlikely(vcpu_is_protected(vcpu) && vcpu_mode_is_32bit(vcpu))) { 242 /* 243 * As we have caught the guest red-handed, decide that it isn't 244 * fit for purpose anymore by making the vcpu invalid. The VMM 245 * can try and fix it by re-initializing the vcpu with 246 * KVM_ARM_VCPU_INIT, however, this is likely not possible for 247 * protected VMs. 248 */ 249 vcpu_clear_flag(vcpu, VCPU_INITIALIZED); 250 *exit_code &= BIT(ARM_EXIT_WITH_SERROR_BIT); 251 *exit_code |= ARM_EXCEPTION_IL; 252 } 253 254 return __fixup_guest_exit(vcpu, exit_code, handlers); 255 } 256 257 /* Switch to the guest for legacy non-VHE systems */ 258 int __kvm_vcpu_run(struct kvm_vcpu *vcpu) 259 { 260 struct kvm_cpu_context *host_ctxt; 261 struct kvm_cpu_context *guest_ctxt; 262 struct kvm_s2_mmu *mmu; 263 bool pmu_switch_needed; 264 u64 exit_code; 265 266 /* 267 * Having IRQs masked via PMR when entering the guest means the GIC 268 * will not signal the CPU of interrupts of lower priority, and the 269 * only way to get out will be via guest exceptions. 270 * Naturally, we want to avoid this. 271 */ 272 if (system_uses_irq_prio_masking()) { 273 gic_write_pmr(GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET); 274 pmr_sync(); 275 } 276 277 host_ctxt = host_data_ptr(host_ctxt); 278 host_ctxt->__hyp_running_vcpu = vcpu; 279 guest_ctxt = &vcpu->arch.ctxt; 280 281 pmu_switch_needed = __pmu_switch_to_guest(vcpu); 282 283 __sysreg_save_state_nvhe(host_ctxt); 284 /* 285 * We must flush and disable the SPE buffer for nVHE, as 286 * the translation regime(EL1&0) is going to be loaded with 287 * that of the guest. And we must do this before we change the 288 * translation regime to EL2 (via MDCR_EL2_E2PB == 0) and 289 * before we load guest Stage1. 290 */ 291 __debug_save_host_buffers_nvhe(vcpu); 292 293 /* 294 * We're about to restore some new MMU state. Make sure 295 * ongoing page-table walks that have started before we 296 * trapped to EL2 have completed. This also synchronises the 297 * above disabling of BRBE. 298 * 299 * See DDI0487I.a D8.1.5 "Out-of-context translation regimes", 300 * rule R_LFHQG and subsequent information statements. 301 */ 302 dsb(nsh); 303 304 __kvm_adjust_pc(vcpu); 305 306 /* 307 * We must restore the 32-bit state before the sysregs, thanks 308 * to erratum #852523 (Cortex-A57) or #853709 (Cortex-A72). 309 * 310 * Also, and in order to be able to deal with erratum #1319537 (A57) 311 * and #1319367 (A72), we must ensure that all VM-related sysreg are 312 * restored before we enable S2 translation. 313 */ 314 __sysreg32_restore_state(vcpu); 315 __sysreg_restore_state_nvhe(guest_ctxt); 316 317 mmu = kern_hyp_va(vcpu->arch.hw_mmu); 318 __load_stage2(mmu, kern_hyp_va(mmu->arch)); 319 __activate_traps(vcpu); 320 321 __hyp_vgic_restore_state(vcpu); 322 __timer_enable_traps(vcpu); 323 324 __debug_switch_to_guest(vcpu); 325 326 do { 327 trace_hyp_exit(host_ctxt, HYP_REASON_ERET_GUEST); 328 329 /* Jump in the fire! */ 330 exit_code = __guest_enter(vcpu); 331 332 /* And we're baaack! */ 333 trace_hyp_enter(host_ctxt, HYP_REASON_GUEST_EXIT); 334 } while (fixup_guest_exit(vcpu, &exit_code)); 335 336 __sysreg_save_state_nvhe(guest_ctxt); 337 __sysreg32_save_state(vcpu); 338 __timer_disable_traps(vcpu); 339 __hyp_vgic_save_state(vcpu); 340 341 /* 342 * Same thing as before the guest run: we're about to switch 343 * the MMU context, so let's make sure we don't have any 344 * ongoing EL1&0 translations. 345 */ 346 dsb(nsh); 347 348 __deactivate_traps(vcpu); 349 __load_host_stage2(); 350 351 __sysreg_restore_state_nvhe(host_ctxt); 352 353 if (guest_owns_fp_regs()) 354 __fpsimd_save_fpexc32(vcpu); 355 356 __debug_switch_to_host(vcpu); 357 /* 358 * This must come after restoring the host sysregs, since a non-VHE 359 * system may enable SPE here and make use of the TTBRs. 360 */ 361 __debug_restore_host_buffers_nvhe(vcpu); 362 363 if (pmu_switch_needed) 364 __pmu_switch_to_host(vcpu); 365 366 /* Returning to host will clear PSR.I, remask PMR if needed */ 367 if (system_uses_irq_prio_masking()) 368 gic_write_pmr(GIC_PRIO_IRQOFF); 369 370 host_ctxt->__hyp_running_vcpu = NULL; 371 372 return exit_code; 373 } 374 375 asmlinkage void __noreturn hyp_panic(void) 376 { 377 u64 spsr = read_sysreg_el2(SYS_SPSR); 378 u64 elr = read_sysreg_el2(SYS_ELR); 379 u64 par = read_sysreg_par(); 380 struct kvm_cpu_context *host_ctxt; 381 struct kvm_vcpu *vcpu; 382 383 host_ctxt = host_data_ptr(host_ctxt); 384 vcpu = host_ctxt->__hyp_running_vcpu; 385 386 if (vcpu) { 387 __timer_disable_traps(vcpu); 388 __deactivate_traps(vcpu); 389 __load_host_stage2(); 390 __sysreg_restore_state_nvhe(host_ctxt); 391 } 392 393 /* Prepare to dump kvm nvhe hyp stacktrace */ 394 kvm_nvhe_prepare_backtrace((unsigned long)__builtin_frame_address(0), 395 _THIS_IP_); 396 397 __hyp_do_panic(host_ctxt, spsr, elr, par); 398 unreachable(); 399 } 400 401 asmlinkage void __noreturn hyp_panic_bad_stack(void) 402 { 403 hyp_panic(); 404 } 405 406 asmlinkage void kvm_unexpected_el2_exception(void) 407 { 408 __kvm_unexpected_el2_exception(); 409 } 410