1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Microchip switch driver main logic
4 *
5 * Copyright (C) 2017-2025 Microchip Technology Inc.
6 */
7
8 #include <linux/delay.h>
9 #include <linux/dsa/ksz_common.h>
10 #include <linux/export.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/platform_data/microchip-ksz.h>
15 #include <linux/phy.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_bridge.h>
18 #include <linux/if_vlan.h>
19 #include <linux/if_hsr.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/of.h>
23 #include <linux/of_mdio.h>
24 #include <linux/of_net.h>
25 #include <linux/micrel_phy.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <net/dsa.h>
28 #include <net/ieee8021q.h>
29 #include <net/pkt_cls.h>
30 #include <net/switchdev.h>
31
32 #include "ksz_common.h"
33 #include "ksz_dcb.h"
34 #include "ksz_ptp.h"
35 #include "ksz8.h"
36 #include "ksz9477.h"
37 #include "lan937x.h"
38
39 #define MIB_COUNTER_NUM 0x20
40
41 struct ksz_stats_raw {
42 u64 rx_hi;
43 u64 rx_undersize;
44 u64 rx_fragments;
45 u64 rx_oversize;
46 u64 rx_jabbers;
47 u64 rx_symbol_err;
48 u64 rx_crc_err;
49 u64 rx_align_err;
50 u64 rx_mac_ctrl;
51 u64 rx_pause;
52 u64 rx_bcast;
53 u64 rx_mcast;
54 u64 rx_ucast;
55 u64 rx_64_or_less;
56 u64 rx_65_127;
57 u64 rx_128_255;
58 u64 rx_256_511;
59 u64 rx_512_1023;
60 u64 rx_1024_1522;
61 u64 rx_1523_2000;
62 u64 rx_2001;
63 u64 tx_hi;
64 u64 tx_late_col;
65 u64 tx_pause;
66 u64 tx_bcast;
67 u64 tx_mcast;
68 u64 tx_ucast;
69 u64 tx_deferred;
70 u64 tx_total_col;
71 u64 tx_exc_col;
72 u64 tx_single_col;
73 u64 tx_mult_col;
74 u64 rx_total;
75 u64 tx_total;
76 u64 rx_discards;
77 u64 tx_discards;
78 };
79
80 struct ksz88xx_stats_raw {
81 u64 rx;
82 u64 rx_hi;
83 u64 rx_undersize;
84 u64 rx_fragments;
85 u64 rx_oversize;
86 u64 rx_jabbers;
87 u64 rx_symbol_err;
88 u64 rx_crc_err;
89 u64 rx_align_err;
90 u64 rx_mac_ctrl;
91 u64 rx_pause;
92 u64 rx_bcast;
93 u64 rx_mcast;
94 u64 rx_ucast;
95 u64 rx_64_or_less;
96 u64 rx_65_127;
97 u64 rx_128_255;
98 u64 rx_256_511;
99 u64 rx_512_1023;
100 u64 rx_1024_1522;
101 u64 tx;
102 u64 tx_hi;
103 u64 tx_late_col;
104 u64 tx_pause;
105 u64 tx_bcast;
106 u64 tx_mcast;
107 u64 tx_ucast;
108 u64 tx_deferred;
109 u64 tx_total_col;
110 u64 tx_exc_col;
111 u64 tx_single_col;
112 u64 tx_mult_col;
113 u64 rx_discards;
114 u64 tx_discards;
115 };
116
117 static const struct ksz_mib_names ksz88xx_mib_names[] = {
118 { 0x00, "rx" },
119 { 0x01, "rx_hi" },
120 { 0x02, "rx_undersize" },
121 { 0x03, "rx_fragments" },
122 { 0x04, "rx_oversize" },
123 { 0x05, "rx_jabbers" },
124 { 0x06, "rx_symbol_err" },
125 { 0x07, "rx_crc_err" },
126 { 0x08, "rx_align_err" },
127 { 0x09, "rx_mac_ctrl" },
128 { 0x0a, "rx_pause" },
129 { 0x0b, "rx_bcast" },
130 { 0x0c, "rx_mcast" },
131 { 0x0d, "rx_ucast" },
132 { 0x0e, "rx_64_or_less" },
133 { 0x0f, "rx_65_127" },
134 { 0x10, "rx_128_255" },
135 { 0x11, "rx_256_511" },
136 { 0x12, "rx_512_1023" },
137 { 0x13, "rx_1024_1522" },
138 { 0x14, "tx" },
139 { 0x15, "tx_hi" },
140 { 0x16, "tx_late_col" },
141 { 0x17, "tx_pause" },
142 { 0x18, "tx_bcast" },
143 { 0x19, "tx_mcast" },
144 { 0x1a, "tx_ucast" },
145 { 0x1b, "tx_deferred" },
146 { 0x1c, "tx_total_col" },
147 { 0x1d, "tx_exc_col" },
148 { 0x1e, "tx_single_col" },
149 { 0x1f, "tx_mult_col" },
150 { 0x100, "rx_discards" },
151 { 0x101, "tx_discards" },
152 };
153
154 static const struct ksz_mib_names ksz9477_mib_names[] = {
155 { 0x00, "rx_hi" },
156 { 0x01, "rx_undersize" },
157 { 0x02, "rx_fragments" },
158 { 0x03, "rx_oversize" },
159 { 0x04, "rx_jabbers" },
160 { 0x05, "rx_symbol_err" },
161 { 0x06, "rx_crc_err" },
162 { 0x07, "rx_align_err" },
163 { 0x08, "rx_mac_ctrl" },
164 { 0x09, "rx_pause" },
165 { 0x0A, "rx_bcast" },
166 { 0x0B, "rx_mcast" },
167 { 0x0C, "rx_ucast" },
168 { 0x0D, "rx_64_or_less" },
169 { 0x0E, "rx_65_127" },
170 { 0x0F, "rx_128_255" },
171 { 0x10, "rx_256_511" },
172 { 0x11, "rx_512_1023" },
173 { 0x12, "rx_1024_1522" },
174 { 0x13, "rx_1523_2000" },
175 { 0x14, "rx_2001" },
176 { 0x15, "tx_hi" },
177 { 0x16, "tx_late_col" },
178 { 0x17, "tx_pause" },
179 { 0x18, "tx_bcast" },
180 { 0x19, "tx_mcast" },
181 { 0x1A, "tx_ucast" },
182 { 0x1B, "tx_deferred" },
183 { 0x1C, "tx_total_col" },
184 { 0x1D, "tx_exc_col" },
185 { 0x1E, "tx_single_col" },
186 { 0x1F, "tx_mult_col" },
187 { 0x80, "rx_total" },
188 { 0x81, "tx_total" },
189 { 0x82, "rx_discards" },
190 { 0x83, "tx_discards" },
191 };
192
193 struct ksz_driver_strength_prop {
194 const char *name;
195 int offset;
196 int value;
197 };
198
199 enum ksz_driver_strength_type {
200 KSZ_DRIVER_STRENGTH_HI,
201 KSZ_DRIVER_STRENGTH_LO,
202 KSZ_DRIVER_STRENGTH_IO,
203 };
204
205 /**
206 * struct ksz_drive_strength - drive strength mapping
207 * @reg_val: register value
208 * @microamp: microamp value
209 */
210 struct ksz_drive_strength {
211 u32 reg_val;
212 u32 microamp;
213 };
214
215 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants
216 *
217 * This values are not documented in KSZ9477 variants but confirmed by
218 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893
219 * and KSZ8563 are using same register (drive strength) settings like KSZ8795.
220 *
221 * Documentation in KSZ8795CLX provides more information with some
222 * recommendations:
223 * - for high speed signals
224 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using
225 * 2.5V or 3.3V VDDIO.
226 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with
227 * using 1.8V VDDIO.
228 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V
229 * or 3.3V VDDIO.
230 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO.
231 * 5. In same interface, the heavy loading should use higher one of the
232 * drive current strength.
233 * - for low speed signals
234 * 1. 3.3V VDDIO, use either 4 mA or 8 mA.
235 * 2. 2.5V VDDIO, use either 8 mA or 12 mA.
236 * 3. 1.8V VDDIO, use either 12 mA or 16 mA.
237 * 4. If it is heavy loading, can use higher drive current strength.
238 */
239 static const struct ksz_drive_strength ksz9477_drive_strengths[] = {
240 { SW_DRIVE_STRENGTH_2MA, 2000 },
241 { SW_DRIVE_STRENGTH_4MA, 4000 },
242 { SW_DRIVE_STRENGTH_8MA, 8000 },
243 { SW_DRIVE_STRENGTH_12MA, 12000 },
244 { SW_DRIVE_STRENGTH_16MA, 16000 },
245 { SW_DRIVE_STRENGTH_20MA, 20000 },
246 { SW_DRIVE_STRENGTH_24MA, 24000 },
247 { SW_DRIVE_STRENGTH_28MA, 28000 },
248 };
249
250 /* ksz88x3_drive_strengths - Drive strength mapping for KSZ8863, KSZ8873, ..
251 * variants.
252 * This values are documented in KSZ8873 and KSZ8863 datasheets.
253 */
254 static const struct ksz_drive_strength ksz88x3_drive_strengths[] = {
255 { 0, 8000 },
256 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 },
257 };
258
259 static void ksz88x3_phylink_mac_config(struct phylink_config *config,
260 unsigned int mode,
261 const struct phylink_link_state *state);
262 static void ksz_phylink_mac_config(struct phylink_config *config,
263 unsigned int mode,
264 const struct phylink_link_state *state);
265 static void ksz_phylink_mac_link_down(struct phylink_config *config,
266 unsigned int mode,
267 phy_interface_t interface);
268
269 /**
270 * ksz_phylink_mac_disable_tx_lpi() - Callback to signal LPI support (Dummy)
271 * @config: phylink config structure
272 *
273 * This function is a dummy handler. See ksz_phylink_mac_enable_tx_lpi() for
274 * a detailed explanation of EEE/LPI handling in KSZ switches.
275 */
ksz_phylink_mac_disable_tx_lpi(struct phylink_config * config)276 static void ksz_phylink_mac_disable_tx_lpi(struct phylink_config *config)
277 {
278 }
279
280 /**
281 * ksz_phylink_mac_enable_tx_lpi() - Callback to signal LPI support (Dummy)
282 * @config: phylink config structure
283 * @timer: timer value before entering LPI (unused)
284 * @tx_clock_stop: whether to stop the TX clock in LPI mode (unused)
285 *
286 * This function signals to phylink that the driver architecture supports
287 * LPI management, enabling phylink to control EEE advertisement during
288 * negotiation according to IEEE Std 802.3 (Clause 78).
289 *
290 * Hardware Management of EEE/LPI State:
291 * For KSZ switch ports with integrated PHYs (e.g., KSZ9893R ports 1-2),
292 * observation and testing suggest that the actual EEE / Low Power Idle (LPI)
293 * state transitions are managed autonomously by the hardware based on
294 * the auto-negotiation results. (Note: While the datasheet describes EEE
295 * operation based on negotiation, it doesn't explicitly detail the internal
296 * MAC/PHY interaction, so autonomous hardware management of the MAC state
297 * for LPI is inferred from observed behavior).
298 * This hardware control, consistent with the switch's ability to operate
299 * autonomously via strapping, means MAC-level software intervention is not
300 * required or exposed for managing the LPI state once EEE is negotiated.
301 * (Ref: KSZ9893R Data Sheet DS00002420D, primarily Section 4.7.5 explaining
302 * EEE, also Sections 4.1.7 on Auto-Negotiation and 3.2.1 on Configuration
303 * Straps).
304 *
305 * Additionally, ports configured as MAC interfaces (e.g., KSZ9893R port 3)
306 * lack documented MAC-level LPI control.
307 *
308 * Therefore, this callback performs no action and serves primarily to inform
309 * phylink of LPI awareness and to document the inferred hardware behavior.
310 *
311 * Returns: 0 (Always success)
312 */
ksz_phylink_mac_enable_tx_lpi(struct phylink_config * config,u32 timer,bool tx_clock_stop)313 static int ksz_phylink_mac_enable_tx_lpi(struct phylink_config *config,
314 u32 timer, bool tx_clock_stop)
315 {
316 return 0;
317 }
318
319 static const struct phylink_mac_ops ksz88x3_phylink_mac_ops = {
320 .mac_config = ksz88x3_phylink_mac_config,
321 .mac_link_down = ksz_phylink_mac_link_down,
322 .mac_link_up = ksz8_phylink_mac_link_up,
323 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi,
324 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi,
325 };
326
327 static const struct phylink_mac_ops ksz8_phylink_mac_ops = {
328 .mac_config = ksz_phylink_mac_config,
329 .mac_link_down = ksz_phylink_mac_link_down,
330 .mac_link_up = ksz8_phylink_mac_link_up,
331 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi,
332 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi,
333 };
334
335 static const struct ksz_dev_ops ksz8463_dev_ops = {
336 .setup = ksz8_setup,
337 .get_port_addr = ksz8463_get_port_addr,
338 .cfg_port_member = ksz8_cfg_port_member,
339 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
340 .port_setup = ksz8_port_setup,
341 .r_phy = ksz8463_r_phy,
342 .w_phy = ksz8463_w_phy,
343 .r_mib_cnt = ksz8_r_mib_cnt,
344 .r_mib_pkt = ksz8_r_mib_pkt,
345 .r_mib_stat64 = ksz88xx_r_mib_stats64,
346 .freeze_mib = ksz8_freeze_mib,
347 .port_init_cnt = ksz8_port_init_cnt,
348 .fdb_dump = ksz8_fdb_dump,
349 .fdb_add = ksz8_fdb_add,
350 .fdb_del = ksz8_fdb_del,
351 .mdb_add = ksz8_mdb_add,
352 .mdb_del = ksz8_mdb_del,
353 .vlan_filtering = ksz8_port_vlan_filtering,
354 .vlan_add = ksz8_port_vlan_add,
355 .vlan_del = ksz8_port_vlan_del,
356 .mirror_add = ksz8_port_mirror_add,
357 .mirror_del = ksz8_port_mirror_del,
358 .get_caps = ksz8_get_caps,
359 .config_cpu_port = ksz8_config_cpu_port,
360 .enable_stp_addr = ksz8_enable_stp_addr,
361 .reset = ksz8_reset_switch,
362 .init = ksz8_switch_init,
363 .exit = ksz8_switch_exit,
364 .change_mtu = ksz8_change_mtu,
365 };
366
367 static const struct ksz_dev_ops ksz88xx_dev_ops = {
368 .setup = ksz8_setup,
369 .get_port_addr = ksz8_get_port_addr,
370 .cfg_port_member = ksz8_cfg_port_member,
371 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
372 .port_setup = ksz8_port_setup,
373 .r_phy = ksz8_r_phy,
374 .w_phy = ksz8_w_phy,
375 .r_mib_cnt = ksz8_r_mib_cnt,
376 .r_mib_pkt = ksz8_r_mib_pkt,
377 .r_mib_stat64 = ksz88xx_r_mib_stats64,
378 .freeze_mib = ksz8_freeze_mib,
379 .port_init_cnt = ksz8_port_init_cnt,
380 .fdb_dump = ksz8_fdb_dump,
381 .fdb_add = ksz8_fdb_add,
382 .fdb_del = ksz8_fdb_del,
383 .mdb_add = ksz8_mdb_add,
384 .mdb_del = ksz8_mdb_del,
385 .vlan_filtering = ksz8_port_vlan_filtering,
386 .vlan_add = ksz8_port_vlan_add,
387 .vlan_del = ksz8_port_vlan_del,
388 .mirror_add = ksz8_port_mirror_add,
389 .mirror_del = ksz8_port_mirror_del,
390 .get_caps = ksz8_get_caps,
391 .config_cpu_port = ksz8_config_cpu_port,
392 .enable_stp_addr = ksz8_enable_stp_addr,
393 .reset = ksz8_reset_switch,
394 .init = ksz8_switch_init,
395 .exit = ksz8_switch_exit,
396 .change_mtu = ksz8_change_mtu,
397 .pme_write8 = ksz8_pme_write8,
398 .pme_pread8 = ksz8_pme_pread8,
399 .pme_pwrite8 = ksz8_pme_pwrite8,
400 };
401
402 static const struct ksz_dev_ops ksz87xx_dev_ops = {
403 .setup = ksz8_setup,
404 .get_port_addr = ksz8_get_port_addr,
405 .cfg_port_member = ksz8_cfg_port_member,
406 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
407 .port_setup = ksz8_port_setup,
408 .r_phy = ksz8_r_phy,
409 .w_phy = ksz8_w_phy,
410 .r_mib_cnt = ksz8_r_mib_cnt,
411 .r_mib_pkt = ksz8_r_mib_pkt,
412 .r_mib_stat64 = ksz_r_mib_stats64,
413 .freeze_mib = ksz8_freeze_mib,
414 .port_init_cnt = ksz8_port_init_cnt,
415 .fdb_dump = ksz8_fdb_dump,
416 .fdb_add = ksz8_fdb_add,
417 .fdb_del = ksz8_fdb_del,
418 .mdb_add = ksz8_mdb_add,
419 .mdb_del = ksz8_mdb_del,
420 .vlan_filtering = ksz8_port_vlan_filtering,
421 .vlan_add = ksz8_port_vlan_add,
422 .vlan_del = ksz8_port_vlan_del,
423 .mirror_add = ksz8_port_mirror_add,
424 .mirror_del = ksz8_port_mirror_del,
425 .get_caps = ksz8_get_caps,
426 .config_cpu_port = ksz8_config_cpu_port,
427 .enable_stp_addr = ksz8_enable_stp_addr,
428 .reset = ksz8_reset_switch,
429 .init = ksz8_switch_init,
430 .exit = ksz8_switch_exit,
431 .change_mtu = ksz8_change_mtu,
432 .pme_write8 = ksz8_pme_write8,
433 .pme_pread8 = ksz8_pme_pread8,
434 .pme_pwrite8 = ksz8_pme_pwrite8,
435 };
436
437 static void ksz9477_phylink_mac_link_up(struct phylink_config *config,
438 struct phy_device *phydev,
439 unsigned int mode,
440 phy_interface_t interface,
441 int speed, int duplex, bool tx_pause,
442 bool rx_pause);
443
444 static struct phylink_pcs *
ksz_phylink_mac_select_pcs(struct phylink_config * config,phy_interface_t interface)445 ksz_phylink_mac_select_pcs(struct phylink_config *config,
446 phy_interface_t interface)
447 {
448 struct dsa_port *dp = dsa_phylink_to_port(config);
449 struct ksz_device *dev = dp->ds->priv;
450 struct ksz_port *p = &dev->ports[dp->index];
451
452 if (ksz_is_sgmii_port(dev, dp->index) &&
453 (interface == PHY_INTERFACE_MODE_SGMII ||
454 interface == PHY_INTERFACE_MODE_1000BASEX))
455 return p->pcs;
456
457 return NULL;
458 }
459
460 static const struct phylink_mac_ops ksz9477_phylink_mac_ops = {
461 .mac_config = ksz_phylink_mac_config,
462 .mac_link_down = ksz_phylink_mac_link_down,
463 .mac_link_up = ksz9477_phylink_mac_link_up,
464 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi,
465 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi,
466 .mac_select_pcs = ksz_phylink_mac_select_pcs,
467 };
468
469 static const struct ksz_dev_ops ksz9477_dev_ops = {
470 .setup = ksz9477_setup,
471 .get_port_addr = ksz9477_get_port_addr,
472 .cfg_port_member = ksz9477_cfg_port_member,
473 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
474 .port_setup = ksz9477_port_setup,
475 .set_ageing_time = ksz9477_set_ageing_time,
476 .r_phy = ksz9477_r_phy,
477 .w_phy = ksz9477_w_phy,
478 .r_mib_cnt = ksz9477_r_mib_cnt,
479 .r_mib_pkt = ksz9477_r_mib_pkt,
480 .r_mib_stat64 = ksz_r_mib_stats64,
481 .freeze_mib = ksz9477_freeze_mib,
482 .port_init_cnt = ksz9477_port_init_cnt,
483 .vlan_filtering = ksz9477_port_vlan_filtering,
484 .vlan_add = ksz9477_port_vlan_add,
485 .vlan_del = ksz9477_port_vlan_del,
486 .mirror_add = ksz9477_port_mirror_add,
487 .mirror_del = ksz9477_port_mirror_del,
488 .get_caps = ksz9477_get_caps,
489 .fdb_dump = ksz9477_fdb_dump,
490 .fdb_add = ksz9477_fdb_add,
491 .fdb_del = ksz9477_fdb_del,
492 .mdb_add = ksz9477_mdb_add,
493 .mdb_del = ksz9477_mdb_del,
494 .change_mtu = ksz9477_change_mtu,
495 .pme_write8 = ksz_write8,
496 .pme_pread8 = ksz_pread8,
497 .pme_pwrite8 = ksz_pwrite8,
498 .config_cpu_port = ksz9477_config_cpu_port,
499 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc,
500 .enable_stp_addr = ksz9477_enable_stp_addr,
501 .reset = ksz9477_reset_switch,
502 .init = ksz9477_switch_init,
503 .exit = ksz9477_switch_exit,
504 .pcs_create = ksz9477_pcs_create,
505 };
506
507 static const struct phylink_mac_ops lan937x_phylink_mac_ops = {
508 .mac_config = ksz_phylink_mac_config,
509 .mac_link_down = ksz_phylink_mac_link_down,
510 .mac_link_up = ksz9477_phylink_mac_link_up,
511 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi,
512 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi,
513 };
514
515 static const struct ksz_dev_ops lan937x_dev_ops = {
516 .setup = lan937x_setup,
517 .teardown = lan937x_teardown,
518 .get_port_addr = ksz9477_get_port_addr,
519 .cfg_port_member = ksz9477_cfg_port_member,
520 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
521 .port_setup = lan937x_port_setup,
522 .set_ageing_time = lan937x_set_ageing_time,
523 .mdio_bus_preinit = lan937x_mdio_bus_preinit,
524 .create_phy_addr_map = lan937x_create_phy_addr_map,
525 .r_phy = lan937x_r_phy,
526 .w_phy = lan937x_w_phy,
527 .r_mib_cnt = ksz9477_r_mib_cnt,
528 .r_mib_pkt = ksz9477_r_mib_pkt,
529 .r_mib_stat64 = ksz_r_mib_stats64,
530 .freeze_mib = ksz9477_freeze_mib,
531 .port_init_cnt = ksz9477_port_init_cnt,
532 .vlan_filtering = ksz9477_port_vlan_filtering,
533 .vlan_add = ksz9477_port_vlan_add,
534 .vlan_del = ksz9477_port_vlan_del,
535 .mirror_add = ksz9477_port_mirror_add,
536 .mirror_del = ksz9477_port_mirror_del,
537 .get_caps = lan937x_phylink_get_caps,
538 .setup_rgmii_delay = lan937x_setup_rgmii_delay,
539 .fdb_dump = ksz9477_fdb_dump,
540 .fdb_add = ksz9477_fdb_add,
541 .fdb_del = ksz9477_fdb_del,
542 .mdb_add = ksz9477_mdb_add,
543 .mdb_del = ksz9477_mdb_del,
544 .change_mtu = lan937x_change_mtu,
545 .config_cpu_port = lan937x_config_cpu_port,
546 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc,
547 .enable_stp_addr = ksz9477_enable_stp_addr,
548 .reset = lan937x_reset_switch,
549 .init = lan937x_switch_init,
550 .exit = lan937x_switch_exit,
551 };
552
553 static const u16 ksz8463_regs[] = {
554 [REG_SW_MAC_ADDR] = 0x10,
555 [REG_IND_CTRL_0] = 0x30,
556 [REG_IND_DATA_8] = 0x26,
557 [REG_IND_DATA_CHECK] = 0x26,
558 [REG_IND_DATA_HI] = 0x28,
559 [REG_IND_DATA_LO] = 0x2C,
560 [REG_IND_MIB_CHECK] = 0x2F,
561 [P_FORCE_CTRL] = 0x0C,
562 [P_LINK_STATUS] = 0x0E,
563 [P_LOCAL_CTRL] = 0x0C,
564 [P_NEG_RESTART_CTRL] = 0x0D,
565 [P_REMOTE_STATUS] = 0x0E,
566 [P_SPEED_STATUS] = 0x0F,
567 [S_TAIL_TAG_CTRL] = 0xAD,
568 [P_STP_CTRL] = 0x6F,
569 [S_START_CTRL] = 0x01,
570 [S_BROADCAST_CTRL] = 0x06,
571 [S_MULTICAST_CTRL] = 0x04,
572 };
573
574 static const u32 ksz8463_masks[] = {
575 [PORT_802_1P_REMAPPING] = BIT(3),
576 [SW_TAIL_TAG_ENABLE] = BIT(0),
577 [MIB_COUNTER_OVERFLOW] = BIT(7),
578 [MIB_COUNTER_VALID] = BIT(6),
579 [VLAN_TABLE_FID] = GENMASK(15, 12),
580 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
581 [VLAN_TABLE_VALID] = BIT(19),
582 [STATIC_MAC_TABLE_VALID] = BIT(19),
583 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
584 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22),
585 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
586 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
587 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),
588 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2),
589 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
590 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),
591 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
592 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
593 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
594 };
595
596 static u8 ksz8463_shifts[] = {
597 [VLAN_TABLE_MEMBERSHIP_S] = 16,
598 [STATIC_MAC_FWD_PORTS] = 16,
599 [STATIC_MAC_FID] = 22,
600 [DYNAMIC_MAC_ENTRIES_H] = 8,
601 [DYNAMIC_MAC_ENTRIES] = 24,
602 [DYNAMIC_MAC_FID] = 16,
603 [DYNAMIC_MAC_TIMESTAMP] = 22,
604 [DYNAMIC_MAC_SRC_PORT] = 20,
605 };
606
607 static const u16 ksz8795_regs[] = {
608 [REG_SW_MAC_ADDR] = 0x68,
609 [REG_IND_CTRL_0] = 0x6E,
610 [REG_IND_DATA_8] = 0x70,
611 [REG_IND_DATA_CHECK] = 0x72,
612 [REG_IND_DATA_HI] = 0x71,
613 [REG_IND_DATA_LO] = 0x75,
614 [REG_IND_MIB_CHECK] = 0x74,
615 [REG_IND_BYTE] = 0xA0,
616 [P_FORCE_CTRL] = 0x0C,
617 [P_LINK_STATUS] = 0x0E,
618 [P_LOCAL_CTRL] = 0x07,
619 [P_NEG_RESTART_CTRL] = 0x0D,
620 [P_REMOTE_STATUS] = 0x08,
621 [P_SPEED_STATUS] = 0x09,
622 [S_TAIL_TAG_CTRL] = 0x0C,
623 [P_STP_CTRL] = 0x02,
624 [S_START_CTRL] = 0x01,
625 [S_BROADCAST_CTRL] = 0x06,
626 [S_MULTICAST_CTRL] = 0x04,
627 [P_XMII_CTRL_0] = 0x06,
628 [P_XMII_CTRL_1] = 0x06,
629 [REG_SW_PME_CTRL] = 0x8003,
630 [REG_PORT_PME_STATUS] = 0x8003,
631 [REG_PORT_PME_CTRL] = 0x8007,
632 };
633
634 static const u32 ksz8795_masks[] = {
635 [PORT_802_1P_REMAPPING] = BIT(7),
636 [SW_TAIL_TAG_ENABLE] = BIT(1),
637 [MIB_COUNTER_OVERFLOW] = BIT(6),
638 [MIB_COUNTER_VALID] = BIT(5),
639 [VLAN_TABLE_FID] = GENMASK(6, 0),
640 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
641 [VLAN_TABLE_VALID] = BIT(12),
642 [STATIC_MAC_TABLE_VALID] = BIT(21),
643 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
644 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
645 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
646 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
647 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
648 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
649 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
650 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
651 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
652 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
653 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
654 [P_MII_TX_FLOW_CTRL] = BIT(5),
655 [P_MII_RX_FLOW_CTRL] = BIT(5),
656 };
657
658 static const u8 ksz8795_xmii_ctrl0[] = {
659 [P_MII_100MBIT] = 0,
660 [P_MII_10MBIT] = 1,
661 [P_MII_FULL_DUPLEX] = 0,
662 [P_MII_HALF_DUPLEX] = 1,
663 };
664
665 static const u8 ksz8795_xmii_ctrl1[] = {
666 [P_RGMII_SEL] = 3,
667 [P_GMII_SEL] = 2,
668 [P_RMII_SEL] = 1,
669 [P_MII_SEL] = 0,
670 [P_GMII_1GBIT] = 1,
671 [P_GMII_NOT_1GBIT] = 0,
672 };
673
674 static const u8 ksz8795_shifts[] = {
675 [VLAN_TABLE_MEMBERSHIP_S] = 7,
676 [VLAN_TABLE] = 16,
677 [STATIC_MAC_FWD_PORTS] = 16,
678 [STATIC_MAC_FID] = 24,
679 [DYNAMIC_MAC_ENTRIES_H] = 3,
680 [DYNAMIC_MAC_ENTRIES] = 29,
681 [DYNAMIC_MAC_FID] = 16,
682 [DYNAMIC_MAC_TIMESTAMP] = 27,
683 [DYNAMIC_MAC_SRC_PORT] = 24,
684 };
685
686 static const u16 ksz8863_regs[] = {
687 [REG_SW_MAC_ADDR] = 0x70,
688 [REG_IND_CTRL_0] = 0x79,
689 [REG_IND_DATA_8] = 0x7B,
690 [REG_IND_DATA_CHECK] = 0x7B,
691 [REG_IND_DATA_HI] = 0x7C,
692 [REG_IND_DATA_LO] = 0x80,
693 [REG_IND_MIB_CHECK] = 0x80,
694 [P_FORCE_CTRL] = 0x0C,
695 [P_LINK_STATUS] = 0x0E,
696 [P_LOCAL_CTRL] = 0x0C,
697 [P_NEG_RESTART_CTRL] = 0x0D,
698 [P_REMOTE_STATUS] = 0x0E,
699 [P_SPEED_STATUS] = 0x0F,
700 [S_TAIL_TAG_CTRL] = 0x03,
701 [P_STP_CTRL] = 0x02,
702 [S_START_CTRL] = 0x01,
703 [S_BROADCAST_CTRL] = 0x06,
704 [S_MULTICAST_CTRL] = 0x04,
705 };
706
707 static const u32 ksz8863_masks[] = {
708 [PORT_802_1P_REMAPPING] = BIT(3),
709 [SW_TAIL_TAG_ENABLE] = BIT(6),
710 [MIB_COUNTER_OVERFLOW] = BIT(7),
711 [MIB_COUNTER_VALID] = BIT(6),
712 [VLAN_TABLE_FID] = GENMASK(15, 12),
713 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
714 [VLAN_TABLE_VALID] = BIT(19),
715 [STATIC_MAC_TABLE_VALID] = BIT(19),
716 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
717 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22),
718 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
719 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
720 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),
721 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2),
722 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
723 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),
724 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
725 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
726 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
727 };
728
729 static u8 ksz8863_shifts[] = {
730 [VLAN_TABLE_MEMBERSHIP_S] = 16,
731 [STATIC_MAC_FWD_PORTS] = 16,
732 [STATIC_MAC_FID] = 22,
733 [DYNAMIC_MAC_ENTRIES_H] = 8,
734 [DYNAMIC_MAC_ENTRIES] = 24,
735 [DYNAMIC_MAC_FID] = 16,
736 [DYNAMIC_MAC_TIMESTAMP] = 22,
737 [DYNAMIC_MAC_SRC_PORT] = 20,
738 };
739
740 static const u16 ksz8895_regs[] = {
741 [REG_SW_MAC_ADDR] = 0x68,
742 [REG_IND_CTRL_0] = 0x6E,
743 [REG_IND_DATA_8] = 0x70,
744 [REG_IND_DATA_CHECK] = 0x72,
745 [REG_IND_DATA_HI] = 0x71,
746 [REG_IND_DATA_LO] = 0x75,
747 [REG_IND_MIB_CHECK] = 0x75,
748 [P_FORCE_CTRL] = 0x0C,
749 [P_LINK_STATUS] = 0x0E,
750 [P_LOCAL_CTRL] = 0x0C,
751 [P_NEG_RESTART_CTRL] = 0x0D,
752 [P_REMOTE_STATUS] = 0x0E,
753 [P_SPEED_STATUS] = 0x09,
754 [S_TAIL_TAG_CTRL] = 0x0C,
755 [P_STP_CTRL] = 0x02,
756 [S_START_CTRL] = 0x01,
757 [S_BROADCAST_CTRL] = 0x06,
758 [S_MULTICAST_CTRL] = 0x04,
759 };
760
761 static const u32 ksz8895_masks[] = {
762 [PORT_802_1P_REMAPPING] = BIT(7),
763 [SW_TAIL_TAG_ENABLE] = BIT(1),
764 [MIB_COUNTER_OVERFLOW] = BIT(7),
765 [MIB_COUNTER_VALID] = BIT(6),
766 [VLAN_TABLE_FID] = GENMASK(6, 0),
767 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
768 [VLAN_TABLE_VALID] = BIT(12),
769 [STATIC_MAC_TABLE_VALID] = BIT(21),
770 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
771 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
772 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
773 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
774 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
775 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
776 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
777 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
778 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
779 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
780 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
781 };
782
783 static const u8 ksz8895_shifts[] = {
784 [VLAN_TABLE_MEMBERSHIP_S] = 7,
785 [VLAN_TABLE] = 13,
786 [STATIC_MAC_FWD_PORTS] = 16,
787 [STATIC_MAC_FID] = 24,
788 [DYNAMIC_MAC_ENTRIES_H] = 3,
789 [DYNAMIC_MAC_ENTRIES] = 29,
790 [DYNAMIC_MAC_FID] = 16,
791 [DYNAMIC_MAC_TIMESTAMP] = 27,
792 [DYNAMIC_MAC_SRC_PORT] = 24,
793 };
794
795 static const u16 ksz9477_regs[] = {
796 [REG_SW_MAC_ADDR] = 0x0302,
797 [P_STP_CTRL] = 0x0B04,
798 [S_START_CTRL] = 0x0300,
799 [S_BROADCAST_CTRL] = 0x0332,
800 [S_MULTICAST_CTRL] = 0x0331,
801 [P_XMII_CTRL_0] = 0x0300,
802 [P_XMII_CTRL_1] = 0x0301,
803 [REG_SW_PME_CTRL] = 0x0006,
804 [REG_PORT_PME_STATUS] = 0x0013,
805 [REG_PORT_PME_CTRL] = 0x0017,
806 };
807
808 static const u32 ksz9477_masks[] = {
809 [ALU_STAT_WRITE] = 0,
810 [ALU_STAT_READ] = 1,
811 [ALU_STAT_DIRECT] = 0,
812 [ALU_RESV_MCAST_ADDR] = BIT(1),
813 [P_MII_TX_FLOW_CTRL] = BIT(5),
814 [P_MII_RX_FLOW_CTRL] = BIT(3),
815 };
816
817 static const u8 ksz9477_shifts[] = {
818 [ALU_STAT_INDEX] = 16,
819 };
820
821 static const u8 ksz9477_xmii_ctrl0[] = {
822 [P_MII_100MBIT] = 1,
823 [P_MII_10MBIT] = 0,
824 [P_MII_FULL_DUPLEX] = 1,
825 [P_MII_HALF_DUPLEX] = 0,
826 };
827
828 static const u8 ksz9477_xmii_ctrl1[] = {
829 [P_RGMII_SEL] = 0,
830 [P_RMII_SEL] = 1,
831 [P_GMII_SEL] = 2,
832 [P_MII_SEL] = 3,
833 [P_GMII_1GBIT] = 0,
834 [P_GMII_NOT_1GBIT] = 1,
835 };
836
837 static const u32 lan937x_masks[] = {
838 [ALU_STAT_WRITE] = 1,
839 [ALU_STAT_READ] = 2,
840 [ALU_STAT_DIRECT] = BIT(3),
841 [ALU_RESV_MCAST_ADDR] = BIT(2),
842 [P_MII_TX_FLOW_CTRL] = BIT(5),
843 [P_MII_RX_FLOW_CTRL] = BIT(3),
844 };
845
846 static const u8 lan937x_shifts[] = {
847 [ALU_STAT_INDEX] = 8,
848 };
849
850 static const struct regmap_range ksz8563_valid_regs[] = {
851 regmap_reg_range(0x0000, 0x0003),
852 regmap_reg_range(0x0006, 0x0006),
853 regmap_reg_range(0x000f, 0x001f),
854 regmap_reg_range(0x0100, 0x0100),
855 regmap_reg_range(0x0104, 0x0107),
856 regmap_reg_range(0x010d, 0x010d),
857 regmap_reg_range(0x0110, 0x0113),
858 regmap_reg_range(0x0120, 0x012b),
859 regmap_reg_range(0x0201, 0x0201),
860 regmap_reg_range(0x0210, 0x0213),
861 regmap_reg_range(0x0300, 0x0300),
862 regmap_reg_range(0x0302, 0x031b),
863 regmap_reg_range(0x0320, 0x032b),
864 regmap_reg_range(0x0330, 0x0336),
865 regmap_reg_range(0x0338, 0x033e),
866 regmap_reg_range(0x0340, 0x035f),
867 regmap_reg_range(0x0370, 0x0370),
868 regmap_reg_range(0x0378, 0x0378),
869 regmap_reg_range(0x037c, 0x037d),
870 regmap_reg_range(0x0390, 0x0393),
871 regmap_reg_range(0x0400, 0x040e),
872 regmap_reg_range(0x0410, 0x042f),
873 regmap_reg_range(0x0500, 0x0519),
874 regmap_reg_range(0x0520, 0x054b),
875 regmap_reg_range(0x0550, 0x05b3),
876
877 /* port 1 */
878 regmap_reg_range(0x1000, 0x1001),
879 regmap_reg_range(0x1004, 0x100b),
880 regmap_reg_range(0x1013, 0x1013),
881 regmap_reg_range(0x1017, 0x1017),
882 regmap_reg_range(0x101b, 0x101b),
883 regmap_reg_range(0x101f, 0x1021),
884 regmap_reg_range(0x1030, 0x1030),
885 regmap_reg_range(0x1100, 0x1111),
886 regmap_reg_range(0x111a, 0x111d),
887 regmap_reg_range(0x1122, 0x1127),
888 regmap_reg_range(0x112a, 0x112b),
889 regmap_reg_range(0x1136, 0x1139),
890 regmap_reg_range(0x113e, 0x113f),
891 regmap_reg_range(0x1400, 0x1401),
892 regmap_reg_range(0x1403, 0x1403),
893 regmap_reg_range(0x1410, 0x1417),
894 regmap_reg_range(0x1420, 0x1423),
895 regmap_reg_range(0x1500, 0x1507),
896 regmap_reg_range(0x1600, 0x1612),
897 regmap_reg_range(0x1800, 0x180f),
898 regmap_reg_range(0x1900, 0x1907),
899 regmap_reg_range(0x1914, 0x191b),
900 regmap_reg_range(0x1a00, 0x1a03),
901 regmap_reg_range(0x1a04, 0x1a08),
902 regmap_reg_range(0x1b00, 0x1b01),
903 regmap_reg_range(0x1b04, 0x1b04),
904 regmap_reg_range(0x1c00, 0x1c05),
905 regmap_reg_range(0x1c08, 0x1c1b),
906
907 /* port 2 */
908 regmap_reg_range(0x2000, 0x2001),
909 regmap_reg_range(0x2004, 0x200b),
910 regmap_reg_range(0x2013, 0x2013),
911 regmap_reg_range(0x2017, 0x2017),
912 regmap_reg_range(0x201b, 0x201b),
913 regmap_reg_range(0x201f, 0x2021),
914 regmap_reg_range(0x2030, 0x2030),
915 regmap_reg_range(0x2100, 0x2111),
916 regmap_reg_range(0x211a, 0x211d),
917 regmap_reg_range(0x2122, 0x2127),
918 regmap_reg_range(0x212a, 0x212b),
919 regmap_reg_range(0x2136, 0x2139),
920 regmap_reg_range(0x213e, 0x213f),
921 regmap_reg_range(0x2400, 0x2401),
922 regmap_reg_range(0x2403, 0x2403),
923 regmap_reg_range(0x2410, 0x2417),
924 regmap_reg_range(0x2420, 0x2423),
925 regmap_reg_range(0x2500, 0x2507),
926 regmap_reg_range(0x2600, 0x2612),
927 regmap_reg_range(0x2800, 0x280f),
928 regmap_reg_range(0x2900, 0x2907),
929 regmap_reg_range(0x2914, 0x291b),
930 regmap_reg_range(0x2a00, 0x2a03),
931 regmap_reg_range(0x2a04, 0x2a08),
932 regmap_reg_range(0x2b00, 0x2b01),
933 regmap_reg_range(0x2b04, 0x2b04),
934 regmap_reg_range(0x2c00, 0x2c05),
935 regmap_reg_range(0x2c08, 0x2c1b),
936
937 /* port 3 */
938 regmap_reg_range(0x3000, 0x3001),
939 regmap_reg_range(0x3004, 0x300b),
940 regmap_reg_range(0x3013, 0x3013),
941 regmap_reg_range(0x3017, 0x3017),
942 regmap_reg_range(0x301b, 0x301b),
943 regmap_reg_range(0x301f, 0x3021),
944 regmap_reg_range(0x3030, 0x3030),
945 regmap_reg_range(0x3300, 0x3301),
946 regmap_reg_range(0x3303, 0x3303),
947 regmap_reg_range(0x3400, 0x3401),
948 regmap_reg_range(0x3403, 0x3403),
949 regmap_reg_range(0x3410, 0x3417),
950 regmap_reg_range(0x3420, 0x3423),
951 regmap_reg_range(0x3500, 0x3507),
952 regmap_reg_range(0x3600, 0x3612),
953 regmap_reg_range(0x3800, 0x380f),
954 regmap_reg_range(0x3900, 0x3907),
955 regmap_reg_range(0x3914, 0x391b),
956 regmap_reg_range(0x3a00, 0x3a03),
957 regmap_reg_range(0x3a04, 0x3a08),
958 regmap_reg_range(0x3b00, 0x3b01),
959 regmap_reg_range(0x3b04, 0x3b04),
960 regmap_reg_range(0x3c00, 0x3c05),
961 regmap_reg_range(0x3c08, 0x3c1b),
962 };
963
964 static const struct regmap_access_table ksz8563_register_set = {
965 .yes_ranges = ksz8563_valid_regs,
966 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
967 };
968
969 static const struct regmap_range ksz9477_valid_regs[] = {
970 regmap_reg_range(0x0000, 0x0003),
971 regmap_reg_range(0x0006, 0x0006),
972 regmap_reg_range(0x0010, 0x001f),
973 regmap_reg_range(0x0100, 0x0100),
974 regmap_reg_range(0x0103, 0x0107),
975 regmap_reg_range(0x010d, 0x010d),
976 regmap_reg_range(0x0110, 0x0113),
977 regmap_reg_range(0x0120, 0x012b),
978 regmap_reg_range(0x0201, 0x0201),
979 regmap_reg_range(0x0210, 0x0213),
980 regmap_reg_range(0x0300, 0x0300),
981 regmap_reg_range(0x0302, 0x031b),
982 regmap_reg_range(0x0320, 0x032b),
983 regmap_reg_range(0x0330, 0x0336),
984 regmap_reg_range(0x0338, 0x033b),
985 regmap_reg_range(0x033e, 0x033e),
986 regmap_reg_range(0x0340, 0x035f),
987 regmap_reg_range(0x0370, 0x0370),
988 regmap_reg_range(0x0378, 0x0378),
989 regmap_reg_range(0x037c, 0x037d),
990 regmap_reg_range(0x0390, 0x0393),
991 regmap_reg_range(0x0400, 0x040e),
992 regmap_reg_range(0x0410, 0x042f),
993 regmap_reg_range(0x0444, 0x044b),
994 regmap_reg_range(0x0450, 0x046f),
995 regmap_reg_range(0x0500, 0x0519),
996 regmap_reg_range(0x0520, 0x054b),
997 regmap_reg_range(0x0550, 0x05b3),
998 regmap_reg_range(0x0604, 0x060b),
999 regmap_reg_range(0x0610, 0x0612),
1000 regmap_reg_range(0x0614, 0x062c),
1001 regmap_reg_range(0x0640, 0x0645),
1002 regmap_reg_range(0x0648, 0x064d),
1003
1004 /* port 1 */
1005 regmap_reg_range(0x1000, 0x1001),
1006 regmap_reg_range(0x1013, 0x1013),
1007 regmap_reg_range(0x1017, 0x1017),
1008 regmap_reg_range(0x101b, 0x101b),
1009 regmap_reg_range(0x101f, 0x1020),
1010 regmap_reg_range(0x1030, 0x1030),
1011 regmap_reg_range(0x1100, 0x1115),
1012 regmap_reg_range(0x111a, 0x111f),
1013 regmap_reg_range(0x1120, 0x112b),
1014 regmap_reg_range(0x1134, 0x113b),
1015 regmap_reg_range(0x113c, 0x113f),
1016 regmap_reg_range(0x1400, 0x1401),
1017 regmap_reg_range(0x1403, 0x1403),
1018 regmap_reg_range(0x1410, 0x1417),
1019 regmap_reg_range(0x1420, 0x1423),
1020 regmap_reg_range(0x1500, 0x1507),
1021 regmap_reg_range(0x1600, 0x1613),
1022 regmap_reg_range(0x1800, 0x180f),
1023 regmap_reg_range(0x1820, 0x1827),
1024 regmap_reg_range(0x1830, 0x1837),
1025 regmap_reg_range(0x1840, 0x184b),
1026 regmap_reg_range(0x1900, 0x1907),
1027 regmap_reg_range(0x1914, 0x191b),
1028 regmap_reg_range(0x1920, 0x1920),
1029 regmap_reg_range(0x1923, 0x1927),
1030 regmap_reg_range(0x1a00, 0x1a03),
1031 regmap_reg_range(0x1a04, 0x1a07),
1032 regmap_reg_range(0x1b00, 0x1b01),
1033 regmap_reg_range(0x1b04, 0x1b04),
1034 regmap_reg_range(0x1c00, 0x1c05),
1035 regmap_reg_range(0x1c08, 0x1c1b),
1036
1037 /* port 2 */
1038 regmap_reg_range(0x2000, 0x2001),
1039 regmap_reg_range(0x2013, 0x2013),
1040 regmap_reg_range(0x2017, 0x2017),
1041 regmap_reg_range(0x201b, 0x201b),
1042 regmap_reg_range(0x201f, 0x2020),
1043 regmap_reg_range(0x2030, 0x2030),
1044 regmap_reg_range(0x2100, 0x2115),
1045 regmap_reg_range(0x211a, 0x211f),
1046 regmap_reg_range(0x2120, 0x212b),
1047 regmap_reg_range(0x2134, 0x213b),
1048 regmap_reg_range(0x213c, 0x213f),
1049 regmap_reg_range(0x2400, 0x2401),
1050 regmap_reg_range(0x2403, 0x2403),
1051 regmap_reg_range(0x2410, 0x2417),
1052 regmap_reg_range(0x2420, 0x2423),
1053 regmap_reg_range(0x2500, 0x2507),
1054 regmap_reg_range(0x2600, 0x2613),
1055 regmap_reg_range(0x2800, 0x280f),
1056 regmap_reg_range(0x2820, 0x2827),
1057 regmap_reg_range(0x2830, 0x2837),
1058 regmap_reg_range(0x2840, 0x284b),
1059 regmap_reg_range(0x2900, 0x2907),
1060 regmap_reg_range(0x2914, 0x291b),
1061 regmap_reg_range(0x2920, 0x2920),
1062 regmap_reg_range(0x2923, 0x2927),
1063 regmap_reg_range(0x2a00, 0x2a03),
1064 regmap_reg_range(0x2a04, 0x2a07),
1065 regmap_reg_range(0x2b00, 0x2b01),
1066 regmap_reg_range(0x2b04, 0x2b04),
1067 regmap_reg_range(0x2c00, 0x2c05),
1068 regmap_reg_range(0x2c08, 0x2c1b),
1069
1070 /* port 3 */
1071 regmap_reg_range(0x3000, 0x3001),
1072 regmap_reg_range(0x3013, 0x3013),
1073 regmap_reg_range(0x3017, 0x3017),
1074 regmap_reg_range(0x301b, 0x301b),
1075 regmap_reg_range(0x301f, 0x3020),
1076 regmap_reg_range(0x3030, 0x3030),
1077 regmap_reg_range(0x3100, 0x3115),
1078 regmap_reg_range(0x311a, 0x311f),
1079 regmap_reg_range(0x3120, 0x312b),
1080 regmap_reg_range(0x3134, 0x313b),
1081 regmap_reg_range(0x313c, 0x313f),
1082 regmap_reg_range(0x3400, 0x3401),
1083 regmap_reg_range(0x3403, 0x3403),
1084 regmap_reg_range(0x3410, 0x3417),
1085 regmap_reg_range(0x3420, 0x3423),
1086 regmap_reg_range(0x3500, 0x3507),
1087 regmap_reg_range(0x3600, 0x3613),
1088 regmap_reg_range(0x3800, 0x380f),
1089 regmap_reg_range(0x3820, 0x3827),
1090 regmap_reg_range(0x3830, 0x3837),
1091 regmap_reg_range(0x3840, 0x384b),
1092 regmap_reg_range(0x3900, 0x3907),
1093 regmap_reg_range(0x3914, 0x391b),
1094 regmap_reg_range(0x3920, 0x3920),
1095 regmap_reg_range(0x3923, 0x3927),
1096 regmap_reg_range(0x3a00, 0x3a03),
1097 regmap_reg_range(0x3a04, 0x3a07),
1098 regmap_reg_range(0x3b00, 0x3b01),
1099 regmap_reg_range(0x3b04, 0x3b04),
1100 regmap_reg_range(0x3c00, 0x3c05),
1101 regmap_reg_range(0x3c08, 0x3c1b),
1102
1103 /* port 4 */
1104 regmap_reg_range(0x4000, 0x4001),
1105 regmap_reg_range(0x4013, 0x4013),
1106 regmap_reg_range(0x4017, 0x4017),
1107 regmap_reg_range(0x401b, 0x401b),
1108 regmap_reg_range(0x401f, 0x4020),
1109 regmap_reg_range(0x4030, 0x4030),
1110 regmap_reg_range(0x4100, 0x4115),
1111 regmap_reg_range(0x411a, 0x411f),
1112 regmap_reg_range(0x4120, 0x412b),
1113 regmap_reg_range(0x4134, 0x413b),
1114 regmap_reg_range(0x413c, 0x413f),
1115 regmap_reg_range(0x4400, 0x4401),
1116 regmap_reg_range(0x4403, 0x4403),
1117 regmap_reg_range(0x4410, 0x4417),
1118 regmap_reg_range(0x4420, 0x4423),
1119 regmap_reg_range(0x4500, 0x4507),
1120 regmap_reg_range(0x4600, 0x4613),
1121 regmap_reg_range(0x4800, 0x480f),
1122 regmap_reg_range(0x4820, 0x4827),
1123 regmap_reg_range(0x4830, 0x4837),
1124 regmap_reg_range(0x4840, 0x484b),
1125 regmap_reg_range(0x4900, 0x4907),
1126 regmap_reg_range(0x4914, 0x491b),
1127 regmap_reg_range(0x4920, 0x4920),
1128 regmap_reg_range(0x4923, 0x4927),
1129 regmap_reg_range(0x4a00, 0x4a03),
1130 regmap_reg_range(0x4a04, 0x4a07),
1131 regmap_reg_range(0x4b00, 0x4b01),
1132 regmap_reg_range(0x4b04, 0x4b04),
1133 regmap_reg_range(0x4c00, 0x4c05),
1134 regmap_reg_range(0x4c08, 0x4c1b),
1135
1136 /* port 5 */
1137 regmap_reg_range(0x5000, 0x5001),
1138 regmap_reg_range(0x5013, 0x5013),
1139 regmap_reg_range(0x5017, 0x5017),
1140 regmap_reg_range(0x501b, 0x501b),
1141 regmap_reg_range(0x501f, 0x5020),
1142 regmap_reg_range(0x5030, 0x5030),
1143 regmap_reg_range(0x5100, 0x5115),
1144 regmap_reg_range(0x511a, 0x511f),
1145 regmap_reg_range(0x5120, 0x512b),
1146 regmap_reg_range(0x5134, 0x513b),
1147 regmap_reg_range(0x513c, 0x513f),
1148 regmap_reg_range(0x5400, 0x5401),
1149 regmap_reg_range(0x5403, 0x5403),
1150 regmap_reg_range(0x5410, 0x5417),
1151 regmap_reg_range(0x5420, 0x5423),
1152 regmap_reg_range(0x5500, 0x5507),
1153 regmap_reg_range(0x5600, 0x5613),
1154 regmap_reg_range(0x5800, 0x580f),
1155 regmap_reg_range(0x5820, 0x5827),
1156 regmap_reg_range(0x5830, 0x5837),
1157 regmap_reg_range(0x5840, 0x584b),
1158 regmap_reg_range(0x5900, 0x5907),
1159 regmap_reg_range(0x5914, 0x591b),
1160 regmap_reg_range(0x5920, 0x5920),
1161 regmap_reg_range(0x5923, 0x5927),
1162 regmap_reg_range(0x5a00, 0x5a03),
1163 regmap_reg_range(0x5a04, 0x5a07),
1164 regmap_reg_range(0x5b00, 0x5b01),
1165 regmap_reg_range(0x5b04, 0x5b04),
1166 regmap_reg_range(0x5c00, 0x5c05),
1167 regmap_reg_range(0x5c08, 0x5c1b),
1168
1169 /* port 6 */
1170 regmap_reg_range(0x6000, 0x6001),
1171 regmap_reg_range(0x6013, 0x6013),
1172 regmap_reg_range(0x6017, 0x6017),
1173 regmap_reg_range(0x601b, 0x601b),
1174 regmap_reg_range(0x601f, 0x6020),
1175 regmap_reg_range(0x6030, 0x6030),
1176 regmap_reg_range(0x6300, 0x6301),
1177 regmap_reg_range(0x6400, 0x6401),
1178 regmap_reg_range(0x6403, 0x6403),
1179 regmap_reg_range(0x6410, 0x6417),
1180 regmap_reg_range(0x6420, 0x6423),
1181 regmap_reg_range(0x6500, 0x6507),
1182 regmap_reg_range(0x6600, 0x6613),
1183 regmap_reg_range(0x6800, 0x680f),
1184 regmap_reg_range(0x6820, 0x6827),
1185 regmap_reg_range(0x6830, 0x6837),
1186 regmap_reg_range(0x6840, 0x684b),
1187 regmap_reg_range(0x6900, 0x6907),
1188 regmap_reg_range(0x6914, 0x691b),
1189 regmap_reg_range(0x6920, 0x6920),
1190 regmap_reg_range(0x6923, 0x6927),
1191 regmap_reg_range(0x6a00, 0x6a03),
1192 regmap_reg_range(0x6a04, 0x6a07),
1193 regmap_reg_range(0x6b00, 0x6b01),
1194 regmap_reg_range(0x6b04, 0x6b04),
1195 regmap_reg_range(0x6c00, 0x6c05),
1196 regmap_reg_range(0x6c08, 0x6c1b),
1197
1198 /* port 7 */
1199 regmap_reg_range(0x7000, 0x7001),
1200 regmap_reg_range(0x7013, 0x7013),
1201 regmap_reg_range(0x7017, 0x7017),
1202 regmap_reg_range(0x701b, 0x701b),
1203 regmap_reg_range(0x701f, 0x7020),
1204 regmap_reg_range(0x7030, 0x7030),
1205 regmap_reg_range(0x7200, 0x7207),
1206 regmap_reg_range(0x7300, 0x7301),
1207 regmap_reg_range(0x7400, 0x7401),
1208 regmap_reg_range(0x7403, 0x7403),
1209 regmap_reg_range(0x7410, 0x7417),
1210 regmap_reg_range(0x7420, 0x7423),
1211 regmap_reg_range(0x7500, 0x7507),
1212 regmap_reg_range(0x7600, 0x7613),
1213 regmap_reg_range(0x7800, 0x780f),
1214 regmap_reg_range(0x7820, 0x7827),
1215 regmap_reg_range(0x7830, 0x7837),
1216 regmap_reg_range(0x7840, 0x784b),
1217 regmap_reg_range(0x7900, 0x7907),
1218 regmap_reg_range(0x7914, 0x791b),
1219 regmap_reg_range(0x7920, 0x7920),
1220 regmap_reg_range(0x7923, 0x7927),
1221 regmap_reg_range(0x7a00, 0x7a03),
1222 regmap_reg_range(0x7a04, 0x7a07),
1223 regmap_reg_range(0x7b00, 0x7b01),
1224 regmap_reg_range(0x7b04, 0x7b04),
1225 regmap_reg_range(0x7c00, 0x7c05),
1226 regmap_reg_range(0x7c08, 0x7c1b),
1227 };
1228
1229 static const struct regmap_access_table ksz9477_register_set = {
1230 .yes_ranges = ksz9477_valid_regs,
1231 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
1232 };
1233
1234 static const struct regmap_range ksz9896_valid_regs[] = {
1235 regmap_reg_range(0x0000, 0x0003),
1236 regmap_reg_range(0x0006, 0x0006),
1237 regmap_reg_range(0x0010, 0x001f),
1238 regmap_reg_range(0x0100, 0x0100),
1239 regmap_reg_range(0x0103, 0x0107),
1240 regmap_reg_range(0x010d, 0x010d),
1241 regmap_reg_range(0x0110, 0x0113),
1242 regmap_reg_range(0x0120, 0x0127),
1243 regmap_reg_range(0x0201, 0x0201),
1244 regmap_reg_range(0x0210, 0x0213),
1245 regmap_reg_range(0x0300, 0x0300),
1246 regmap_reg_range(0x0302, 0x030b),
1247 regmap_reg_range(0x0310, 0x031b),
1248 regmap_reg_range(0x0320, 0x032b),
1249 regmap_reg_range(0x0330, 0x0336),
1250 regmap_reg_range(0x0338, 0x033b),
1251 regmap_reg_range(0x033e, 0x033e),
1252 regmap_reg_range(0x0340, 0x035f),
1253 regmap_reg_range(0x0370, 0x0370),
1254 regmap_reg_range(0x0378, 0x0378),
1255 regmap_reg_range(0x037c, 0x037d),
1256 regmap_reg_range(0x0390, 0x0393),
1257 regmap_reg_range(0x0400, 0x040e),
1258 regmap_reg_range(0x0410, 0x042f),
1259
1260 /* port 1 */
1261 regmap_reg_range(0x1000, 0x1001),
1262 regmap_reg_range(0x1013, 0x1013),
1263 regmap_reg_range(0x1017, 0x1017),
1264 regmap_reg_range(0x101b, 0x101b),
1265 regmap_reg_range(0x101f, 0x1020),
1266 regmap_reg_range(0x1030, 0x1030),
1267 regmap_reg_range(0x1100, 0x1115),
1268 regmap_reg_range(0x111a, 0x111f),
1269 regmap_reg_range(0x1120, 0x112b),
1270 regmap_reg_range(0x1134, 0x113b),
1271 regmap_reg_range(0x113c, 0x113f),
1272 regmap_reg_range(0x1400, 0x1401),
1273 regmap_reg_range(0x1403, 0x1403),
1274 regmap_reg_range(0x1410, 0x1417),
1275 regmap_reg_range(0x1420, 0x1423),
1276 regmap_reg_range(0x1500, 0x1507),
1277 regmap_reg_range(0x1600, 0x1612),
1278 regmap_reg_range(0x1800, 0x180f),
1279 regmap_reg_range(0x1820, 0x1827),
1280 regmap_reg_range(0x1830, 0x1837),
1281 regmap_reg_range(0x1840, 0x184b),
1282 regmap_reg_range(0x1900, 0x1907),
1283 regmap_reg_range(0x1914, 0x1915),
1284 regmap_reg_range(0x1a00, 0x1a03),
1285 regmap_reg_range(0x1a04, 0x1a07),
1286 regmap_reg_range(0x1b00, 0x1b01),
1287 regmap_reg_range(0x1b04, 0x1b04),
1288
1289 /* port 2 */
1290 regmap_reg_range(0x2000, 0x2001),
1291 regmap_reg_range(0x2013, 0x2013),
1292 regmap_reg_range(0x2017, 0x2017),
1293 regmap_reg_range(0x201b, 0x201b),
1294 regmap_reg_range(0x201f, 0x2020),
1295 regmap_reg_range(0x2030, 0x2030),
1296 regmap_reg_range(0x2100, 0x2115),
1297 regmap_reg_range(0x211a, 0x211f),
1298 regmap_reg_range(0x2120, 0x212b),
1299 regmap_reg_range(0x2134, 0x213b),
1300 regmap_reg_range(0x213c, 0x213f),
1301 regmap_reg_range(0x2400, 0x2401),
1302 regmap_reg_range(0x2403, 0x2403),
1303 regmap_reg_range(0x2410, 0x2417),
1304 regmap_reg_range(0x2420, 0x2423),
1305 regmap_reg_range(0x2500, 0x2507),
1306 regmap_reg_range(0x2600, 0x2612),
1307 regmap_reg_range(0x2800, 0x280f),
1308 regmap_reg_range(0x2820, 0x2827),
1309 regmap_reg_range(0x2830, 0x2837),
1310 regmap_reg_range(0x2840, 0x284b),
1311 regmap_reg_range(0x2900, 0x2907),
1312 regmap_reg_range(0x2914, 0x2915),
1313 regmap_reg_range(0x2a00, 0x2a03),
1314 regmap_reg_range(0x2a04, 0x2a07),
1315 regmap_reg_range(0x2b00, 0x2b01),
1316 regmap_reg_range(0x2b04, 0x2b04),
1317
1318 /* port 3 */
1319 regmap_reg_range(0x3000, 0x3001),
1320 regmap_reg_range(0x3013, 0x3013),
1321 regmap_reg_range(0x3017, 0x3017),
1322 regmap_reg_range(0x301b, 0x301b),
1323 regmap_reg_range(0x301f, 0x3020),
1324 regmap_reg_range(0x3030, 0x3030),
1325 regmap_reg_range(0x3100, 0x3115),
1326 regmap_reg_range(0x311a, 0x311f),
1327 regmap_reg_range(0x3120, 0x312b),
1328 regmap_reg_range(0x3134, 0x313b),
1329 regmap_reg_range(0x313c, 0x313f),
1330 regmap_reg_range(0x3400, 0x3401),
1331 regmap_reg_range(0x3403, 0x3403),
1332 regmap_reg_range(0x3410, 0x3417),
1333 regmap_reg_range(0x3420, 0x3423),
1334 regmap_reg_range(0x3500, 0x3507),
1335 regmap_reg_range(0x3600, 0x3612),
1336 regmap_reg_range(0x3800, 0x380f),
1337 regmap_reg_range(0x3820, 0x3827),
1338 regmap_reg_range(0x3830, 0x3837),
1339 regmap_reg_range(0x3840, 0x384b),
1340 regmap_reg_range(0x3900, 0x3907),
1341 regmap_reg_range(0x3914, 0x3915),
1342 regmap_reg_range(0x3a00, 0x3a03),
1343 regmap_reg_range(0x3a04, 0x3a07),
1344 regmap_reg_range(0x3b00, 0x3b01),
1345 regmap_reg_range(0x3b04, 0x3b04),
1346
1347 /* port 4 */
1348 regmap_reg_range(0x4000, 0x4001),
1349 regmap_reg_range(0x4013, 0x4013),
1350 regmap_reg_range(0x4017, 0x4017),
1351 regmap_reg_range(0x401b, 0x401b),
1352 regmap_reg_range(0x401f, 0x4020),
1353 regmap_reg_range(0x4030, 0x4030),
1354 regmap_reg_range(0x4100, 0x4115),
1355 regmap_reg_range(0x411a, 0x411f),
1356 regmap_reg_range(0x4120, 0x412b),
1357 regmap_reg_range(0x4134, 0x413b),
1358 regmap_reg_range(0x413c, 0x413f),
1359 regmap_reg_range(0x4400, 0x4401),
1360 regmap_reg_range(0x4403, 0x4403),
1361 regmap_reg_range(0x4410, 0x4417),
1362 regmap_reg_range(0x4420, 0x4423),
1363 regmap_reg_range(0x4500, 0x4507),
1364 regmap_reg_range(0x4600, 0x4612),
1365 regmap_reg_range(0x4800, 0x480f),
1366 regmap_reg_range(0x4820, 0x4827),
1367 regmap_reg_range(0x4830, 0x4837),
1368 regmap_reg_range(0x4840, 0x484b),
1369 regmap_reg_range(0x4900, 0x4907),
1370 regmap_reg_range(0x4914, 0x4915),
1371 regmap_reg_range(0x4a00, 0x4a03),
1372 regmap_reg_range(0x4a04, 0x4a07),
1373 regmap_reg_range(0x4b00, 0x4b01),
1374 regmap_reg_range(0x4b04, 0x4b04),
1375
1376 /* port 5 */
1377 regmap_reg_range(0x5000, 0x5001),
1378 regmap_reg_range(0x5013, 0x5013),
1379 regmap_reg_range(0x5017, 0x5017),
1380 regmap_reg_range(0x501b, 0x501b),
1381 regmap_reg_range(0x501f, 0x5020),
1382 regmap_reg_range(0x5030, 0x5030),
1383 regmap_reg_range(0x5100, 0x5115),
1384 regmap_reg_range(0x511a, 0x511f),
1385 regmap_reg_range(0x5120, 0x512b),
1386 regmap_reg_range(0x5134, 0x513b),
1387 regmap_reg_range(0x513c, 0x513f),
1388 regmap_reg_range(0x5400, 0x5401),
1389 regmap_reg_range(0x5403, 0x5403),
1390 regmap_reg_range(0x5410, 0x5417),
1391 regmap_reg_range(0x5420, 0x5423),
1392 regmap_reg_range(0x5500, 0x5507),
1393 regmap_reg_range(0x5600, 0x5612),
1394 regmap_reg_range(0x5800, 0x580f),
1395 regmap_reg_range(0x5820, 0x5827),
1396 regmap_reg_range(0x5830, 0x5837),
1397 regmap_reg_range(0x5840, 0x584b),
1398 regmap_reg_range(0x5900, 0x5907),
1399 regmap_reg_range(0x5914, 0x5915),
1400 regmap_reg_range(0x5a00, 0x5a03),
1401 regmap_reg_range(0x5a04, 0x5a07),
1402 regmap_reg_range(0x5b00, 0x5b01),
1403 regmap_reg_range(0x5b04, 0x5b04),
1404
1405 /* port 6 */
1406 regmap_reg_range(0x6000, 0x6001),
1407 regmap_reg_range(0x6013, 0x6013),
1408 regmap_reg_range(0x6017, 0x6017),
1409 regmap_reg_range(0x601b, 0x601b),
1410 regmap_reg_range(0x601f, 0x6020),
1411 regmap_reg_range(0x6030, 0x6030),
1412 regmap_reg_range(0x6100, 0x6115),
1413 regmap_reg_range(0x611a, 0x611f),
1414 regmap_reg_range(0x6120, 0x612b),
1415 regmap_reg_range(0x6134, 0x613b),
1416 regmap_reg_range(0x613c, 0x613f),
1417 regmap_reg_range(0x6300, 0x6301),
1418 regmap_reg_range(0x6400, 0x6401),
1419 regmap_reg_range(0x6403, 0x6403),
1420 regmap_reg_range(0x6410, 0x6417),
1421 regmap_reg_range(0x6420, 0x6423),
1422 regmap_reg_range(0x6500, 0x6507),
1423 regmap_reg_range(0x6600, 0x6612),
1424 regmap_reg_range(0x6800, 0x680f),
1425 regmap_reg_range(0x6820, 0x6827),
1426 regmap_reg_range(0x6830, 0x6837),
1427 regmap_reg_range(0x6840, 0x684b),
1428 regmap_reg_range(0x6900, 0x6907),
1429 regmap_reg_range(0x6914, 0x6915),
1430 regmap_reg_range(0x6a00, 0x6a03),
1431 regmap_reg_range(0x6a04, 0x6a07),
1432 regmap_reg_range(0x6b00, 0x6b01),
1433 regmap_reg_range(0x6b04, 0x6b04),
1434 };
1435
1436 static const struct regmap_access_table ksz9896_register_set = {
1437 .yes_ranges = ksz9896_valid_regs,
1438 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1439 };
1440
1441 static const struct regmap_range ksz8873_valid_regs[] = {
1442 regmap_reg_range(0x00, 0x01),
1443 /* global control register */
1444 regmap_reg_range(0x02, 0x0f),
1445
1446 /* port registers */
1447 regmap_reg_range(0x10, 0x1d),
1448 regmap_reg_range(0x1e, 0x1f),
1449 regmap_reg_range(0x20, 0x2d),
1450 regmap_reg_range(0x2e, 0x2f),
1451 regmap_reg_range(0x30, 0x39),
1452 regmap_reg_range(0x3f, 0x3f),
1453
1454 /* advanced control registers */
1455 regmap_reg_range(0x43, 0x43),
1456 regmap_reg_range(0x60, 0x6f),
1457 regmap_reg_range(0x70, 0x75),
1458 regmap_reg_range(0x76, 0x78),
1459 regmap_reg_range(0x79, 0x7a),
1460 regmap_reg_range(0x7b, 0x83),
1461 regmap_reg_range(0x8e, 0x99),
1462 regmap_reg_range(0x9a, 0xa5),
1463 regmap_reg_range(0xa6, 0xa6),
1464 regmap_reg_range(0xa7, 0xaa),
1465 regmap_reg_range(0xab, 0xae),
1466 regmap_reg_range(0xaf, 0xba),
1467 regmap_reg_range(0xbb, 0xbc),
1468 regmap_reg_range(0xbd, 0xbd),
1469 regmap_reg_range(0xc0, 0xc0),
1470 regmap_reg_range(0xc2, 0xc2),
1471 regmap_reg_range(0xc3, 0xc3),
1472 regmap_reg_range(0xc4, 0xc4),
1473 regmap_reg_range(0xc6, 0xc6),
1474 };
1475
1476 static const struct regmap_access_table ksz8873_register_set = {
1477 .yes_ranges = ksz8873_valid_regs,
1478 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs),
1479 };
1480
1481 const struct ksz_chip_data ksz_switch_chips[] = {
1482 [KSZ8463] = {
1483 .chip_id = KSZ8463_CHIP_ID,
1484 .dev_name = "KSZ8463",
1485 .num_vlans = 16,
1486 .num_alus = 0,
1487 .num_statics = 8,
1488 .cpu_ports = 0x4, /* can be configured as cpu port */
1489 .port_cnt = 3,
1490 .num_tx_queues = 4,
1491 .num_ipms = 4,
1492 .ops = &ksz8463_dev_ops,
1493 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1494 .mib_names = ksz88xx_mib_names,
1495 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1496 .reg_mib_cnt = MIB_COUNTER_NUM,
1497 .regs = ksz8463_regs,
1498 .masks = ksz8463_masks,
1499 .shifts = ksz8463_shifts,
1500 .supports_mii = {false, false, true},
1501 .supports_rmii = {false, false, true},
1502 .internal_phy = {true, true, false},
1503 },
1504
1505 [KSZ8563] = {
1506 .chip_id = KSZ8563_CHIP_ID,
1507 .dev_name = "KSZ8563",
1508 .num_vlans = 4096,
1509 .num_alus = 4096,
1510 .num_statics = 16,
1511 .cpu_ports = 0x07, /* can be configured as cpu port */
1512 .port_cnt = 3, /* total port count */
1513 .port_nirqs = 3,
1514 .num_tx_queues = 4,
1515 .num_ipms = 8,
1516 .tc_cbs_supported = true,
1517 .ops = &ksz9477_dev_ops,
1518 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1519 .mib_names = ksz9477_mib_names,
1520 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1521 .reg_mib_cnt = MIB_COUNTER_NUM,
1522 .regs = ksz9477_regs,
1523 .masks = ksz9477_masks,
1524 .shifts = ksz9477_shifts,
1525 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1526 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1527 .supports_mii = {false, false, true},
1528 .supports_rmii = {false, false, true},
1529 .supports_rgmii = {false, false, true},
1530 .internal_phy = {true, true, false},
1531 .gbit_capable = {false, false, true},
1532 .ptp_capable = true,
1533 .wr_table = &ksz8563_register_set,
1534 .rd_table = &ksz8563_register_set,
1535 },
1536
1537 [KSZ8795] = {
1538 .chip_id = KSZ8795_CHIP_ID,
1539 .dev_name = "KSZ8795",
1540 .num_vlans = 4096,
1541 .num_alus = 0,
1542 .num_statics = 32,
1543 .cpu_ports = 0x10, /* can be configured as cpu port */
1544 .port_cnt = 5, /* total cpu and user ports */
1545 .num_tx_queues = 4,
1546 .num_ipms = 4,
1547 .ops = &ksz87xx_dev_ops,
1548 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1549 .ksz87xx_eee_link_erratum = true,
1550 .mib_names = ksz9477_mib_names,
1551 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1552 .reg_mib_cnt = MIB_COUNTER_NUM,
1553 .regs = ksz8795_regs,
1554 .masks = ksz8795_masks,
1555 .shifts = ksz8795_shifts,
1556 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1557 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1558 .supports_mii = {false, false, false, false, true},
1559 .supports_rmii = {false, false, false, false, true},
1560 .supports_rgmii = {false, false, false, false, true},
1561 .internal_phy = {true, true, true, true, false},
1562 },
1563
1564 [KSZ8794] = {
1565 /* WARNING
1566 * =======
1567 * KSZ8794 is similar to KSZ8795, except the port map
1568 * contains a gap between external and CPU ports, the
1569 * port map is NOT continuous. The per-port register
1570 * map is shifted accordingly too, i.e. registers at
1571 * offset 0x40 are NOT used on KSZ8794 and they ARE
1572 * used on KSZ8795 for external port 3.
1573 * external cpu
1574 * KSZ8794 0,1,2 4
1575 * KSZ8795 0,1,2,3 4
1576 * KSZ8765 0,1,2,3 4
1577 * port_cnt is configured as 5, even though it is 4
1578 */
1579 .chip_id = KSZ8794_CHIP_ID,
1580 .dev_name = "KSZ8794",
1581 .num_vlans = 4096,
1582 .num_alus = 0,
1583 .num_statics = 32,
1584 .cpu_ports = 0x10, /* can be configured as cpu port */
1585 .port_cnt = 5, /* total cpu and user ports */
1586 .num_tx_queues = 4,
1587 .num_ipms = 4,
1588 .ops = &ksz87xx_dev_ops,
1589 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1590 .ksz87xx_eee_link_erratum = true,
1591 .mib_names = ksz9477_mib_names,
1592 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1593 .reg_mib_cnt = MIB_COUNTER_NUM,
1594 .regs = ksz8795_regs,
1595 .masks = ksz8795_masks,
1596 .shifts = ksz8795_shifts,
1597 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1598 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1599 .supports_mii = {false, false, false, false, true},
1600 .supports_rmii = {false, false, false, false, true},
1601 .supports_rgmii = {false, false, false, false, true},
1602 .internal_phy = {true, true, true, false, false},
1603 },
1604
1605 [KSZ8765] = {
1606 .chip_id = KSZ8765_CHIP_ID,
1607 .dev_name = "KSZ8765",
1608 .num_vlans = 4096,
1609 .num_alus = 0,
1610 .num_statics = 32,
1611 .cpu_ports = 0x10, /* can be configured as cpu port */
1612 .port_cnt = 5, /* total cpu and user ports */
1613 .num_tx_queues = 4,
1614 .num_ipms = 4,
1615 .ops = &ksz87xx_dev_ops,
1616 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1617 .ksz87xx_eee_link_erratum = true,
1618 .mib_names = ksz9477_mib_names,
1619 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1620 .reg_mib_cnt = MIB_COUNTER_NUM,
1621 .regs = ksz8795_regs,
1622 .masks = ksz8795_masks,
1623 .shifts = ksz8795_shifts,
1624 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1625 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1626 .supports_mii = {false, false, false, false, true},
1627 .supports_rmii = {false, false, false, false, true},
1628 .supports_rgmii = {false, false, false, false, true},
1629 .internal_phy = {true, true, true, true, false},
1630 },
1631
1632 [KSZ88X3] = {
1633 .chip_id = KSZ88X3_CHIP_ID,
1634 .dev_name = "KSZ8863/KSZ8873",
1635 .num_vlans = 16,
1636 .num_alus = 0,
1637 .num_statics = 8,
1638 .cpu_ports = 0x4, /* can be configured as cpu port */
1639 .port_cnt = 3,
1640 .num_tx_queues = 4,
1641 .num_ipms = 4,
1642 .ops = &ksz88xx_dev_ops,
1643 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1644 .mib_names = ksz88xx_mib_names,
1645 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1646 .reg_mib_cnt = MIB_COUNTER_NUM,
1647 .regs = ksz8863_regs,
1648 .masks = ksz8863_masks,
1649 .shifts = ksz8863_shifts,
1650 .supports_mii = {false, false, true},
1651 .supports_rmii = {false, false, true},
1652 .internal_phy = {true, true, false},
1653 .wr_table = &ksz8873_register_set,
1654 .rd_table = &ksz8873_register_set,
1655 },
1656
1657 [KSZ8864] = {
1658 /* WARNING
1659 * =======
1660 * KSZ8864 is similar to KSZ8895, except the first port
1661 * does not exist.
1662 * external cpu
1663 * KSZ8864 1,2,3 4
1664 * KSZ8895 0,1,2,3 4
1665 * port_cnt is configured as 5, even though it is 4
1666 */
1667 .chip_id = KSZ8864_CHIP_ID,
1668 .dev_name = "KSZ8864",
1669 .num_vlans = 4096,
1670 .num_alus = 0,
1671 .num_statics = 32,
1672 .cpu_ports = 0x10, /* can be configured as cpu port */
1673 .port_cnt = 5, /* total cpu and user ports */
1674 .num_tx_queues = 4,
1675 .num_ipms = 4,
1676 .ops = &ksz88xx_dev_ops,
1677 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1678 .mib_names = ksz88xx_mib_names,
1679 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1680 .reg_mib_cnt = MIB_COUNTER_NUM,
1681 .regs = ksz8895_regs,
1682 .masks = ksz8895_masks,
1683 .shifts = ksz8895_shifts,
1684 .supports_mii = {false, false, false, false, true},
1685 .supports_rmii = {false, false, false, false, true},
1686 .internal_phy = {false, true, true, true, false},
1687 },
1688
1689 [KSZ8895] = {
1690 .chip_id = KSZ8895_CHIP_ID,
1691 .dev_name = "KSZ8895",
1692 .num_vlans = 4096,
1693 .num_alus = 0,
1694 .num_statics = 32,
1695 .cpu_ports = 0x10, /* can be configured as cpu port */
1696 .port_cnt = 5, /* total cpu and user ports */
1697 .num_tx_queues = 4,
1698 .num_ipms = 4,
1699 .ops = &ksz88xx_dev_ops,
1700 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1701 .mib_names = ksz88xx_mib_names,
1702 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1703 .reg_mib_cnt = MIB_COUNTER_NUM,
1704 .regs = ksz8895_regs,
1705 .masks = ksz8895_masks,
1706 .shifts = ksz8895_shifts,
1707 .supports_mii = {false, false, false, false, true},
1708 .supports_rmii = {false, false, false, false, true},
1709 .internal_phy = {true, true, true, true, false},
1710 },
1711
1712 [KSZ9477] = {
1713 .chip_id = KSZ9477_CHIP_ID,
1714 .dev_name = "KSZ9477",
1715 .num_vlans = 4096,
1716 .num_alus = 4096,
1717 .num_statics = 16,
1718 .cpu_ports = 0x7F, /* can be configured as cpu port */
1719 .port_cnt = 7, /* total physical port count */
1720 .port_nirqs = 4,
1721 .num_tx_queues = 4,
1722 .num_ipms = 8,
1723 .tc_cbs_supported = true,
1724 .ops = &ksz9477_dev_ops,
1725 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1726 .phy_errata_9477 = true,
1727 .mib_names = ksz9477_mib_names,
1728 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1729 .reg_mib_cnt = MIB_COUNTER_NUM,
1730 .regs = ksz9477_regs,
1731 .masks = ksz9477_masks,
1732 .shifts = ksz9477_shifts,
1733 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1734 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1735 .supports_mii = {false, false, false, false,
1736 false, true, false},
1737 .supports_rmii = {false, false, false, false,
1738 false, true, false},
1739 .supports_rgmii = {false, false, false, false,
1740 false, true, false},
1741 .internal_phy = {true, true, true, true,
1742 true, false, false},
1743 .gbit_capable = {true, true, true, true, true, true, true},
1744 .ptp_capable = true,
1745 .sgmii_port = 7,
1746 .wr_table = &ksz9477_register_set,
1747 .rd_table = &ksz9477_register_set,
1748 },
1749
1750 [KSZ9896] = {
1751 .chip_id = KSZ9896_CHIP_ID,
1752 .dev_name = "KSZ9896",
1753 .num_vlans = 4096,
1754 .num_alus = 4096,
1755 .num_statics = 16,
1756 .cpu_ports = 0x3F, /* can be configured as cpu port */
1757 .port_cnt = 6, /* total physical port count */
1758 .port_nirqs = 2,
1759 .num_tx_queues = 4,
1760 .num_ipms = 8,
1761 .ops = &ksz9477_dev_ops,
1762 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1763 .phy_errata_9477 = true,
1764 .mib_names = ksz9477_mib_names,
1765 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1766 .reg_mib_cnt = MIB_COUNTER_NUM,
1767 .regs = ksz9477_regs,
1768 .masks = ksz9477_masks,
1769 .shifts = ksz9477_shifts,
1770 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1771 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1772 .supports_mii = {false, false, false, false,
1773 false, true},
1774 .supports_rmii = {false, false, false, false,
1775 false, true},
1776 .supports_rgmii = {false, false, false, false,
1777 false, true},
1778 .internal_phy = {true, true, true, true,
1779 true, false},
1780 .gbit_capable = {true, true, true, true, true, true},
1781 .wr_table = &ksz9896_register_set,
1782 .rd_table = &ksz9896_register_set,
1783 },
1784
1785 [KSZ9897] = {
1786 .chip_id = KSZ9897_CHIP_ID,
1787 .dev_name = "KSZ9897",
1788 .num_vlans = 4096,
1789 .num_alus = 4096,
1790 .num_statics = 16,
1791 .cpu_ports = 0x7F, /* can be configured as cpu port */
1792 .port_cnt = 7, /* total physical port count */
1793 .port_nirqs = 2,
1794 .num_tx_queues = 4,
1795 .num_ipms = 8,
1796 .ops = &ksz9477_dev_ops,
1797 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1798 .phy_errata_9477 = true,
1799 .mib_names = ksz9477_mib_names,
1800 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1801 .reg_mib_cnt = MIB_COUNTER_NUM,
1802 .regs = ksz9477_regs,
1803 .masks = ksz9477_masks,
1804 .shifts = ksz9477_shifts,
1805 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1806 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1807 .supports_mii = {false, false, false, false,
1808 false, true, true},
1809 .supports_rmii = {false, false, false, false,
1810 false, true, true},
1811 .supports_rgmii = {false, false, false, false,
1812 false, true, true},
1813 .internal_phy = {true, true, true, true,
1814 true, false, false},
1815 .gbit_capable = {true, true, true, true, true, true, true},
1816 },
1817
1818 [KSZ9893] = {
1819 .chip_id = KSZ9893_CHIP_ID,
1820 .dev_name = "KSZ9893",
1821 .num_vlans = 4096,
1822 .num_alus = 4096,
1823 .num_statics = 16,
1824 .cpu_ports = 0x07, /* can be configured as cpu port */
1825 .port_cnt = 3, /* total port count */
1826 .port_nirqs = 2,
1827 .num_tx_queues = 4,
1828 .num_ipms = 8,
1829 .ops = &ksz9477_dev_ops,
1830 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1831 .mib_names = ksz9477_mib_names,
1832 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1833 .reg_mib_cnt = MIB_COUNTER_NUM,
1834 .regs = ksz9477_regs,
1835 .masks = ksz9477_masks,
1836 .shifts = ksz9477_shifts,
1837 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1838 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1839 .supports_mii = {false, false, true},
1840 .supports_rmii = {false, false, true},
1841 .supports_rgmii = {false, false, true},
1842 .internal_phy = {true, true, false},
1843 .gbit_capable = {true, true, true},
1844 },
1845
1846 [KSZ9563] = {
1847 .chip_id = KSZ9563_CHIP_ID,
1848 .dev_name = "KSZ9563",
1849 .num_vlans = 4096,
1850 .num_alus = 4096,
1851 .num_statics = 16,
1852 .cpu_ports = 0x07, /* can be configured as cpu port */
1853 .port_cnt = 3, /* total port count */
1854 .port_nirqs = 3,
1855 .num_tx_queues = 4,
1856 .num_ipms = 8,
1857 .tc_cbs_supported = true,
1858 .ops = &ksz9477_dev_ops,
1859 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1860 .mib_names = ksz9477_mib_names,
1861 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1862 .reg_mib_cnt = MIB_COUNTER_NUM,
1863 .regs = ksz9477_regs,
1864 .masks = ksz9477_masks,
1865 .shifts = ksz9477_shifts,
1866 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1867 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1868 .supports_mii = {false, false, true},
1869 .supports_rmii = {false, false, true},
1870 .supports_rgmii = {false, false, true},
1871 .internal_phy = {true, true, false},
1872 .gbit_capable = {true, true, true},
1873 .ptp_capable = true,
1874 },
1875
1876 [KSZ8567] = {
1877 .chip_id = KSZ8567_CHIP_ID,
1878 .dev_name = "KSZ8567",
1879 .num_vlans = 4096,
1880 .num_alus = 4096,
1881 .num_statics = 16,
1882 .cpu_ports = 0x7F, /* can be configured as cpu port */
1883 .port_cnt = 7, /* total port count */
1884 .port_nirqs = 3,
1885 .num_tx_queues = 4,
1886 .num_ipms = 8,
1887 .tc_cbs_supported = true,
1888 .ops = &ksz9477_dev_ops,
1889 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1890 .phy_errata_9477 = true,
1891 .mib_names = ksz9477_mib_names,
1892 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1893 .reg_mib_cnt = MIB_COUNTER_NUM,
1894 .regs = ksz9477_regs,
1895 .masks = ksz9477_masks,
1896 .shifts = ksz9477_shifts,
1897 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1898 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1899 .supports_mii = {false, false, false, false,
1900 false, true, true},
1901 .supports_rmii = {false, false, false, false,
1902 false, true, true},
1903 .supports_rgmii = {false, false, false, false,
1904 false, true, true},
1905 .internal_phy = {true, true, true, true,
1906 true, false, false},
1907 .gbit_capable = {false, false, false, false, false,
1908 true, true},
1909 .ptp_capable = true,
1910 },
1911
1912 [KSZ9567] = {
1913 .chip_id = KSZ9567_CHIP_ID,
1914 .dev_name = "KSZ9567",
1915 .num_vlans = 4096,
1916 .num_alus = 4096,
1917 .num_statics = 16,
1918 .cpu_ports = 0x7F, /* can be configured as cpu port */
1919 .port_cnt = 7, /* total physical port count */
1920 .port_nirqs = 3,
1921 .num_tx_queues = 4,
1922 .num_ipms = 8,
1923 .tc_cbs_supported = true,
1924 .ops = &ksz9477_dev_ops,
1925 .mib_names = ksz9477_mib_names,
1926 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1927 .reg_mib_cnt = MIB_COUNTER_NUM,
1928 .regs = ksz9477_regs,
1929 .masks = ksz9477_masks,
1930 .shifts = ksz9477_shifts,
1931 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1932 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1933 .supports_mii = {false, false, false, false,
1934 false, true, true},
1935 .supports_rmii = {false, false, false, false,
1936 false, true, true},
1937 .supports_rgmii = {false, false, false, false,
1938 false, true, true},
1939 .internal_phy = {true, true, true, true,
1940 true, false, false},
1941 .gbit_capable = {true, true, true, true, true, true, true},
1942 .ptp_capable = true,
1943 },
1944
1945 [LAN9370] = {
1946 .chip_id = LAN9370_CHIP_ID,
1947 .dev_name = "LAN9370",
1948 .num_vlans = 4096,
1949 .num_alus = 1024,
1950 .num_statics = 256,
1951 .cpu_ports = 0x10, /* can be configured as cpu port */
1952 .port_cnt = 5, /* total physical port count */
1953 .port_nirqs = 6,
1954 .num_tx_queues = 8,
1955 .num_ipms = 8,
1956 .tc_cbs_supported = true,
1957 .phy_side_mdio_supported = true,
1958 .ops = &lan937x_dev_ops,
1959 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1960 .mib_names = ksz9477_mib_names,
1961 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1962 .reg_mib_cnt = MIB_COUNTER_NUM,
1963 .regs = ksz9477_regs,
1964 .masks = lan937x_masks,
1965 .shifts = lan937x_shifts,
1966 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1967 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1968 .supports_mii = {false, false, false, false, true},
1969 .supports_rmii = {false, false, false, false, true},
1970 .supports_rgmii = {false, false, false, false, true},
1971 .internal_phy = {true, true, true, true, false},
1972 .ptp_capable = true,
1973 },
1974
1975 [LAN9371] = {
1976 .chip_id = LAN9371_CHIP_ID,
1977 .dev_name = "LAN9371",
1978 .num_vlans = 4096,
1979 .num_alus = 1024,
1980 .num_statics = 256,
1981 .cpu_ports = 0x30, /* can be configured as cpu port */
1982 .port_cnt = 6, /* total physical port count */
1983 .port_nirqs = 6,
1984 .num_tx_queues = 8,
1985 .num_ipms = 8,
1986 .tc_cbs_supported = true,
1987 .phy_side_mdio_supported = true,
1988 .ops = &lan937x_dev_ops,
1989 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1990 .mib_names = ksz9477_mib_names,
1991 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1992 .reg_mib_cnt = MIB_COUNTER_NUM,
1993 .regs = ksz9477_regs,
1994 .masks = lan937x_masks,
1995 .shifts = lan937x_shifts,
1996 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1997 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1998 .supports_mii = {false, false, false, false, true, true},
1999 .supports_rmii = {false, false, false, false, true, true},
2000 .supports_rgmii = {false, false, false, false, true, true},
2001 .internal_phy = {true, true, true, true, false, false},
2002 .ptp_capable = true,
2003 },
2004
2005 [LAN9372] = {
2006 .chip_id = LAN9372_CHIP_ID,
2007 .dev_name = "LAN9372",
2008 .num_vlans = 4096,
2009 .num_alus = 1024,
2010 .num_statics = 256,
2011 .cpu_ports = 0x30, /* can be configured as cpu port */
2012 .port_cnt = 8, /* total physical port count */
2013 .port_nirqs = 6,
2014 .num_tx_queues = 8,
2015 .num_ipms = 8,
2016 .tc_cbs_supported = true,
2017 .phy_side_mdio_supported = true,
2018 .ops = &lan937x_dev_ops,
2019 .phylink_mac_ops = &lan937x_phylink_mac_ops,
2020 .mib_names = ksz9477_mib_names,
2021 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
2022 .reg_mib_cnt = MIB_COUNTER_NUM,
2023 .regs = ksz9477_regs,
2024 .masks = lan937x_masks,
2025 .shifts = lan937x_shifts,
2026 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
2027 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
2028 .supports_mii = {false, false, false, false,
2029 true, true, false, false},
2030 .supports_rmii = {false, false, false, false,
2031 true, true, false, false},
2032 .supports_rgmii = {false, false, false, false,
2033 true, true, false, false},
2034 .internal_phy = {true, true, true, true,
2035 false, false, true, true},
2036 .ptp_capable = true,
2037 },
2038
2039 [LAN9373] = {
2040 .chip_id = LAN9373_CHIP_ID,
2041 .dev_name = "LAN9373",
2042 .num_vlans = 4096,
2043 .num_alus = 1024,
2044 .num_statics = 256,
2045 .cpu_ports = 0x38, /* can be configured as cpu port */
2046 .port_cnt = 5, /* total physical port count */
2047 .port_nirqs = 6,
2048 .num_tx_queues = 8,
2049 .num_ipms = 8,
2050 .tc_cbs_supported = true,
2051 .phy_side_mdio_supported = true,
2052 .ops = &lan937x_dev_ops,
2053 .phylink_mac_ops = &lan937x_phylink_mac_ops,
2054 .mib_names = ksz9477_mib_names,
2055 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
2056 .reg_mib_cnt = MIB_COUNTER_NUM,
2057 .regs = ksz9477_regs,
2058 .masks = lan937x_masks,
2059 .shifts = lan937x_shifts,
2060 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
2061 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
2062 .supports_mii = {false, false, false, false,
2063 true, true, false, false},
2064 .supports_rmii = {false, false, false, false,
2065 true, true, false, false},
2066 .supports_rgmii = {false, false, false, false,
2067 true, true, false, false},
2068 .internal_phy = {true, true, true, false,
2069 false, false, true, true},
2070 .ptp_capable = true,
2071 },
2072
2073 [LAN9374] = {
2074 .chip_id = LAN9374_CHIP_ID,
2075 .dev_name = "LAN9374",
2076 .num_vlans = 4096,
2077 .num_alus = 1024,
2078 .num_statics = 256,
2079 .cpu_ports = 0x30, /* can be configured as cpu port */
2080 .port_cnt = 8, /* total physical port count */
2081 .port_nirqs = 6,
2082 .num_tx_queues = 8,
2083 .num_ipms = 8,
2084 .tc_cbs_supported = true,
2085 .phy_side_mdio_supported = true,
2086 .ops = &lan937x_dev_ops,
2087 .phylink_mac_ops = &lan937x_phylink_mac_ops,
2088 .mib_names = ksz9477_mib_names,
2089 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
2090 .reg_mib_cnt = MIB_COUNTER_NUM,
2091 .regs = ksz9477_regs,
2092 .masks = lan937x_masks,
2093 .shifts = lan937x_shifts,
2094 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
2095 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
2096 .supports_mii = {false, false, false, false,
2097 true, true, false, false},
2098 .supports_rmii = {false, false, false, false,
2099 true, true, false, false},
2100 .supports_rgmii = {false, false, false, false,
2101 true, true, false, false},
2102 .internal_phy = {true, true, true, true,
2103 false, false, true, true},
2104 .ptp_capable = true,
2105 },
2106
2107 [LAN9646] = {
2108 .chip_id = LAN9646_CHIP_ID,
2109 .dev_name = "LAN9646",
2110 .num_vlans = 4096,
2111 .num_alus = 4096,
2112 .num_statics = 16,
2113 .cpu_ports = 0x7F, /* can be configured as cpu port */
2114 .port_cnt = 7, /* total physical port count */
2115 .port_nirqs = 4,
2116 .num_tx_queues = 4,
2117 .num_ipms = 8,
2118 .ops = &ksz9477_dev_ops,
2119 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
2120 .phy_errata_9477 = true,
2121 .mib_names = ksz9477_mib_names,
2122 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
2123 .reg_mib_cnt = MIB_COUNTER_NUM,
2124 .regs = ksz9477_regs,
2125 .masks = ksz9477_masks,
2126 .shifts = ksz9477_shifts,
2127 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
2128 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
2129 .supports_mii = {false, false, false, false,
2130 false, true, true},
2131 .supports_rmii = {false, false, false, false,
2132 false, true, true},
2133 .supports_rgmii = {false, false, false, false,
2134 false, true, true},
2135 .internal_phy = {true, true, true, true,
2136 true, false, false},
2137 .gbit_capable = {true, true, true, true, true, true, true},
2138 .sgmii_port = 7,
2139 .wr_table = &ksz9477_register_set,
2140 .rd_table = &ksz9477_register_set,
2141 },
2142 };
2143 EXPORT_SYMBOL_GPL(ksz_switch_chips);
2144
ksz_lookup_info(unsigned int prod_num)2145 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
2146 {
2147 int i;
2148
2149 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
2150 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
2151
2152 if (chip->chip_id == prod_num)
2153 return chip;
2154 }
2155
2156 return NULL;
2157 }
2158
ksz_check_device_id(struct ksz_device * dev)2159 static int ksz_check_device_id(struct ksz_device *dev)
2160 {
2161 const struct ksz_chip_data *expected_chip_data;
2162 u32 expected_chip_id;
2163
2164 if (dev->pdata) {
2165 expected_chip_id = dev->pdata->chip_id;
2166 expected_chip_data = ksz_lookup_info(expected_chip_id);
2167 if (WARN_ON(!expected_chip_data))
2168 return -ENODEV;
2169 } else {
2170 expected_chip_data = of_device_get_match_data(dev->dev);
2171 expected_chip_id = expected_chip_data->chip_id;
2172 }
2173
2174 if (expected_chip_id != dev->chip_id) {
2175 dev_err(dev->dev,
2176 "Device tree specifies chip %s but found %s, please fix it!\n",
2177 expected_chip_data->dev_name, dev->info->dev_name);
2178 return -ENODEV;
2179 }
2180
2181 return 0;
2182 }
2183
ksz_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)2184 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
2185 struct phylink_config *config)
2186 {
2187 struct ksz_device *dev = ds->priv;
2188
2189 if (dev->info->supports_mii[port])
2190 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
2191
2192 if (dev->info->supports_rmii[port])
2193 __set_bit(PHY_INTERFACE_MODE_RMII,
2194 config->supported_interfaces);
2195
2196 if (dev->info->supports_rgmii[port])
2197 phy_interface_set_rgmii(config->supported_interfaces);
2198
2199 if (dev->info->internal_phy[port]) {
2200 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
2201 config->supported_interfaces);
2202 /* Compatibility for phylib's default interface type when the
2203 * phy-mode property is absent
2204 */
2205 __set_bit(PHY_INTERFACE_MODE_GMII,
2206 config->supported_interfaces);
2207 }
2208
2209 if (dev->dev_ops->get_caps)
2210 dev->dev_ops->get_caps(dev, port, config);
2211
2212 if (ds->ops->support_eee && ds->ops->support_eee(ds, port)) {
2213 memcpy(config->lpi_interfaces, config->supported_interfaces,
2214 sizeof(config->lpi_interfaces));
2215
2216 config->lpi_capabilities = MAC_100FD;
2217 if (dev->info->gbit_capable[port])
2218 config->lpi_capabilities |= MAC_1000FD;
2219
2220 /* EEE is fully operational */
2221 config->eee_enabled_default = true;
2222 }
2223 }
2224
ksz_r_mib_stats64(struct ksz_device * dev,int port)2225 void ksz_r_mib_stats64(struct ksz_device *dev, int port)
2226 {
2227 struct ethtool_pause_stats *pstats;
2228 struct rtnl_link_stats64 *stats;
2229 struct ksz_stats_raw *raw;
2230 struct ksz_port_mib *mib;
2231 int ret;
2232
2233 mib = &dev->ports[port].mib;
2234 stats = &mib->stats64;
2235 pstats = &mib->pause_stats;
2236 raw = (struct ksz_stats_raw *)mib->counters;
2237
2238 spin_lock(&mib->stats64_lock);
2239
2240 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
2241 raw->rx_pause;
2242 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
2243 raw->tx_pause;
2244
2245 /* HW counters are counting bytes + FCS which is not acceptable
2246 * for rtnl_link_stats64 interface
2247 */
2248 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
2249 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
2250
2251 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
2252 raw->rx_oversize;
2253
2254 stats->rx_crc_errors = raw->rx_crc_err;
2255 stats->rx_frame_errors = raw->rx_align_err;
2256 stats->rx_dropped = raw->rx_discards;
2257 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2258 stats->rx_frame_errors + stats->rx_dropped;
2259
2260 stats->tx_window_errors = raw->tx_late_col;
2261 stats->tx_fifo_errors = raw->tx_discards;
2262 stats->tx_aborted_errors = raw->tx_exc_col;
2263 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
2264 stats->tx_aborted_errors;
2265
2266 stats->multicast = raw->rx_mcast;
2267 stats->collisions = raw->tx_total_col;
2268
2269 pstats->tx_pause_frames = raw->tx_pause;
2270 pstats->rx_pause_frames = raw->rx_pause;
2271
2272 spin_unlock(&mib->stats64_lock);
2273
2274 if (dev->info->phy_errata_9477 && !ksz_is_sgmii_port(dev, port)) {
2275 ret = ksz9477_errata_monitor(dev, port, raw->tx_late_col);
2276 if (ret)
2277 dev_err(dev->dev, "Failed to monitor transmission halt\n");
2278 }
2279 }
2280
ksz88xx_r_mib_stats64(struct ksz_device * dev,int port)2281 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port)
2282 {
2283 struct ethtool_pause_stats *pstats;
2284 struct rtnl_link_stats64 *stats;
2285 struct ksz88xx_stats_raw *raw;
2286 struct ksz_port_mib *mib;
2287
2288 mib = &dev->ports[port].mib;
2289 stats = &mib->stats64;
2290 pstats = &mib->pause_stats;
2291 raw = (struct ksz88xx_stats_raw *)mib->counters;
2292
2293 spin_lock(&mib->stats64_lock);
2294
2295 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
2296 raw->rx_pause;
2297 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
2298 raw->tx_pause;
2299
2300 /* HW counters are counting bytes + FCS which is not acceptable
2301 * for rtnl_link_stats64 interface
2302 */
2303 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN;
2304 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN;
2305
2306 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
2307 raw->rx_oversize;
2308
2309 stats->rx_crc_errors = raw->rx_crc_err;
2310 stats->rx_frame_errors = raw->rx_align_err;
2311 stats->rx_dropped = raw->rx_discards;
2312 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2313 stats->rx_frame_errors + stats->rx_dropped;
2314
2315 stats->tx_window_errors = raw->tx_late_col;
2316 stats->tx_fifo_errors = raw->tx_discards;
2317 stats->tx_aborted_errors = raw->tx_exc_col;
2318 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
2319 stats->tx_aborted_errors;
2320
2321 stats->multicast = raw->rx_mcast;
2322 stats->collisions = raw->tx_total_col;
2323
2324 pstats->tx_pause_frames = raw->tx_pause;
2325 pstats->rx_pause_frames = raw->rx_pause;
2326
2327 spin_unlock(&mib->stats64_lock);
2328 }
2329
ksz_get_stats64(struct dsa_switch * ds,int port,struct rtnl_link_stats64 * s)2330 static void ksz_get_stats64(struct dsa_switch *ds, int port,
2331 struct rtnl_link_stats64 *s)
2332 {
2333 struct ksz_device *dev = ds->priv;
2334 struct ksz_port_mib *mib;
2335
2336 mib = &dev->ports[port].mib;
2337
2338 spin_lock(&mib->stats64_lock);
2339 memcpy(s, &mib->stats64, sizeof(*s));
2340 spin_unlock(&mib->stats64_lock);
2341 }
2342
ksz_get_pause_stats(struct dsa_switch * ds,int port,struct ethtool_pause_stats * pause_stats)2343 static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
2344 struct ethtool_pause_stats *pause_stats)
2345 {
2346 struct ksz_device *dev = ds->priv;
2347 struct ksz_port_mib *mib;
2348
2349 mib = &dev->ports[port].mib;
2350
2351 spin_lock(&mib->stats64_lock);
2352 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
2353 spin_unlock(&mib->stats64_lock);
2354 }
2355
ksz_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * buf)2356 static void ksz_get_strings(struct dsa_switch *ds, int port,
2357 u32 stringset, uint8_t *buf)
2358 {
2359 struct ksz_device *dev = ds->priv;
2360 int i;
2361
2362 if (stringset != ETH_SS_STATS)
2363 return;
2364
2365 for (i = 0; i < dev->info->mib_cnt; i++)
2366 ethtool_puts(&buf, dev->info->mib_names[i].string);
2367 }
2368
2369 /**
2370 * ksz_update_port_member - Adjust port forwarding rules based on STP state and
2371 * isolation settings.
2372 * @dev: A pointer to the struct ksz_device representing the device.
2373 * @port: The port number to adjust.
2374 *
2375 * This function dynamically adjusts the port membership configuration for a
2376 * specified port and other device ports, based on Spanning Tree Protocol (STP)
2377 * states and port isolation settings. Each port, including the CPU port, has a
2378 * membership register, represented as a bitfield, where each bit corresponds
2379 * to a port number. A set bit indicates permission to forward frames to that
2380 * port. This function iterates over all ports, updating the membership register
2381 * to reflect current forwarding permissions:
2382 *
2383 * 1. Forwards frames only to ports that are part of the same bridge group and
2384 * in the BR_STATE_FORWARDING state.
2385 * 2. Takes into account the isolation status of ports; ports in the
2386 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward
2387 * frames to each other, even if they are in the same bridge group.
2388 * 3. Ensures that the CPU port is included in the membership based on its
2389 * upstream port configuration, allowing for management and control traffic
2390 * to flow as required.
2391 */
ksz_update_port_member(struct ksz_device * dev,int port)2392 static void ksz_update_port_member(struct ksz_device *dev, int port)
2393 {
2394 struct ksz_port *p = &dev->ports[port];
2395 struct dsa_switch *ds = dev->ds;
2396 u8 port_member = 0, cpu_port;
2397 const struct dsa_port *dp;
2398 int i, j;
2399
2400 if (!dsa_is_user_port(ds, port))
2401 return;
2402
2403 dp = dsa_to_port(ds, port);
2404 cpu_port = BIT(dsa_upstream_port(ds, port));
2405
2406 for (i = 0; i < ds->num_ports; i++) {
2407 const struct dsa_port *other_dp = dsa_to_port(ds, i);
2408 struct ksz_port *other_p = &dev->ports[i];
2409 u8 val = 0;
2410
2411 if (!dsa_is_user_port(ds, i))
2412 continue;
2413 if (port == i)
2414 continue;
2415 if (!dsa_port_bridge_same(dp, other_dp))
2416 continue;
2417 if (other_p->stp_state != BR_STATE_FORWARDING)
2418 continue;
2419
2420 /* At this point we know that "port" and "other" port [i] are in
2421 * the same bridge group and that "other" port [i] is in
2422 * forwarding stp state. If "port" is also in forwarding stp
2423 * state, we can allow forwarding from port [port] to port [i].
2424 * Except if both ports are isolated.
2425 */
2426 if (p->stp_state == BR_STATE_FORWARDING &&
2427 !(p->isolated && other_p->isolated)) {
2428 val |= BIT(port);
2429 port_member |= BIT(i);
2430 }
2431
2432 /* Retain port [i]'s relationship to other ports than [port] */
2433 for (j = 0; j < ds->num_ports; j++) {
2434 const struct dsa_port *third_dp;
2435 struct ksz_port *third_p;
2436
2437 if (j == i)
2438 continue;
2439 if (j == port)
2440 continue;
2441 if (!dsa_is_user_port(ds, j))
2442 continue;
2443 third_p = &dev->ports[j];
2444 if (third_p->stp_state != BR_STATE_FORWARDING)
2445 continue;
2446
2447 third_dp = dsa_to_port(ds, j);
2448
2449 /* Now we updating relation of the "other" port [i] to
2450 * the "third" port [j]. We already know that "other"
2451 * port [i] is in forwarding stp state and that "third"
2452 * port [j] is in forwarding stp state too.
2453 * We need to check if "other" port [i] and "third" port
2454 * [j] are in the same bridge group and not isolated
2455 * before allowing forwarding from port [i] to port [j].
2456 */
2457 if (dsa_port_bridge_same(other_dp, third_dp) &&
2458 !(other_p->isolated && third_p->isolated))
2459 val |= BIT(j);
2460 }
2461
2462 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
2463 }
2464
2465 /* HSR ports are setup once so need to use the assigned membership
2466 * when the port is enabled.
2467 */
2468 if (!port_member && p->stp_state == BR_STATE_FORWARDING &&
2469 (dev->hsr_ports & BIT(port)))
2470 port_member = dev->hsr_ports;
2471 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
2472 }
2473
ksz_sw_mdio_read(struct mii_bus * bus,int addr,int regnum)2474 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
2475 {
2476 struct ksz_device *dev = bus->priv;
2477 u16 val;
2478 int ret;
2479
2480 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val);
2481 if (ret < 0)
2482 return ret;
2483
2484 return val;
2485 }
2486
ksz_sw_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)2487 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
2488 u16 val)
2489 {
2490 struct ksz_device *dev = bus->priv;
2491
2492 return dev->dev_ops->w_phy(dev, addr, regnum, val);
2493 }
2494
2495 /**
2496 * ksz_parent_mdio_read - Read data from a PHY register on the parent MDIO bus.
2497 * @bus: MDIO bus structure.
2498 * @addr: PHY address on the parent MDIO bus.
2499 * @regnum: Register number to read.
2500 *
2501 * This function provides a direct read operation on the parent MDIO bus for
2502 * accessing PHY registers. By bypassing SPI or I2C, it uses the parent MDIO bus
2503 * to retrieve data from the PHY registers at the specified address and register
2504 * number.
2505 *
2506 * Return: Value of the PHY register, or a negative error code on failure.
2507 */
ksz_parent_mdio_read(struct mii_bus * bus,int addr,int regnum)2508 static int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum)
2509 {
2510 struct ksz_device *dev = bus->priv;
2511
2512 return mdiobus_read_nested(dev->parent_mdio_bus, addr, regnum);
2513 }
2514
2515 /**
2516 * ksz_parent_mdio_write - Write data to a PHY register on the parent MDIO bus.
2517 * @bus: MDIO bus structure.
2518 * @addr: PHY address on the parent MDIO bus.
2519 * @regnum: Register number to write to.
2520 * @val: Value to write to the PHY register.
2521 *
2522 * This function provides a direct write operation on the parent MDIO bus for
2523 * accessing PHY registers. Bypassing SPI or I2C, it uses the parent MDIO bus
2524 * to modify the PHY register values at the specified address.
2525 *
2526 * Return: 0 on success, or a negative error code on failure.
2527 */
ksz_parent_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)2528 static int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum,
2529 u16 val)
2530 {
2531 struct ksz_device *dev = bus->priv;
2532
2533 return mdiobus_write_nested(dev->parent_mdio_bus, addr, regnum, val);
2534 }
2535
2536 /**
2537 * ksz_phy_addr_to_port - Map a PHY address to the corresponding switch port.
2538 * @dev: Pointer to device structure.
2539 * @addr: PHY address to map to a port.
2540 *
2541 * This function finds the corresponding switch port for a given PHY address by
2542 * iterating over all user ports on the device. It checks if a port's PHY
2543 * address in `phy_addr_map` matches the specified address and if the port
2544 * contains an internal PHY. If a match is found, the index of the port is
2545 * returned.
2546 *
2547 * Return: Port index on success, or -EINVAL if no matching port is found.
2548 */
ksz_phy_addr_to_port(struct ksz_device * dev,int addr)2549 static int ksz_phy_addr_to_port(struct ksz_device *dev, int addr)
2550 {
2551 struct dsa_switch *ds = dev->ds;
2552 struct dsa_port *dp;
2553
2554 dsa_switch_for_each_user_port(dp, ds) {
2555 if (dev->info->internal_phy[dp->index] &&
2556 dev->phy_addr_map[dp->index] == addr)
2557 return dp->index;
2558 }
2559
2560 return -EINVAL;
2561 }
2562
2563 /**
2564 * ksz_irq_phy_setup - Configure IRQs for PHYs in the KSZ device.
2565 * @dev: Pointer to the KSZ device structure.
2566 *
2567 * Sets up IRQs for each active PHY connected to the KSZ switch by mapping the
2568 * appropriate IRQs for each PHY and assigning them to the `user_mii_bus` in
2569 * the DSA switch structure. Each IRQ is mapped based on the port's IRQ domain.
2570 *
2571 * Return: 0 on success, or a negative error code on failure.
2572 */
ksz_irq_phy_setup(struct ksz_device * dev)2573 static int ksz_irq_phy_setup(struct ksz_device *dev)
2574 {
2575 struct dsa_switch *ds = dev->ds;
2576 int phy, port;
2577 int irq;
2578 int ret;
2579
2580 for (phy = 0; phy < PHY_MAX_ADDR; phy++) {
2581 if (BIT(phy) & ds->phys_mii_mask) {
2582 port = ksz_phy_addr_to_port(dev, phy);
2583 if (port < 0) {
2584 ret = port;
2585 goto out;
2586 }
2587
2588 irq = irq_find_mapping(dev->ports[port].pirq.domain,
2589 PORT_SRC_PHY_INT);
2590 if (irq < 0) {
2591 ret = irq;
2592 goto out;
2593 }
2594 ds->user_mii_bus->irq[phy] = irq;
2595 }
2596 }
2597 return 0;
2598 out:
2599 while (phy--)
2600 if (BIT(phy) & ds->phys_mii_mask)
2601 irq_dispose_mapping(ds->user_mii_bus->irq[phy]);
2602
2603 return ret;
2604 }
2605
2606 /**
2607 * ksz_irq_phy_free - Release IRQ mappings for PHYs in the KSZ device.
2608 * @dev: Pointer to the KSZ device structure.
2609 *
2610 * Releases any IRQ mappings previously assigned to active PHYs in the KSZ
2611 * switch by disposing of each mapped IRQ in the `user_mii_bus` structure.
2612 */
ksz_irq_phy_free(struct ksz_device * dev)2613 static void ksz_irq_phy_free(struct ksz_device *dev)
2614 {
2615 struct dsa_switch *ds = dev->ds;
2616 int phy;
2617
2618 for (phy = 0; phy < PHY_MAX_ADDR; phy++)
2619 if (BIT(phy) & ds->phys_mii_mask)
2620 irq_dispose_mapping(ds->user_mii_bus->irq[phy]);
2621 }
2622
2623 /**
2624 * ksz_parse_dt_phy_config - Parse and validate PHY configuration from DT
2625 * @dev: pointer to the KSZ device structure
2626 * @bus: pointer to the MII bus structure
2627 * @mdio_np: pointer to the MDIO node in the device tree
2628 *
2629 * This function parses and validates PHY configurations for each user port
2630 * defined in the device tree for a KSZ switch device. It verifies that the
2631 * `phy-handle` properties are correctly set and that the internal PHYs match
2632 * expected addresses and parent nodes. Sets up the PHY mask in the MII bus if
2633 * all validations pass. Logs error messages for any mismatches or missing data.
2634 *
2635 * Return: 0 on success, or a negative error code on failure.
2636 */
ksz_parse_dt_phy_config(struct ksz_device * dev,struct mii_bus * bus,struct device_node * mdio_np)2637 static int ksz_parse_dt_phy_config(struct ksz_device *dev, struct mii_bus *bus,
2638 struct device_node *mdio_np)
2639 {
2640 struct device_node *phy_node, *phy_parent_node;
2641 bool phys_are_valid = true;
2642 struct dsa_port *dp;
2643 u32 phy_addr;
2644 int ret;
2645
2646 dsa_switch_for_each_user_port(dp, dev->ds) {
2647 if (!dev->info->internal_phy[dp->index])
2648 continue;
2649
2650 phy_node = of_parse_phandle(dp->dn, "phy-handle", 0);
2651 if (!phy_node) {
2652 dev_err(dev->dev, "failed to parse phy-handle for port %d.\n",
2653 dp->index);
2654 phys_are_valid = false;
2655 continue;
2656 }
2657
2658 phy_parent_node = of_get_parent(phy_node);
2659 if (!phy_parent_node) {
2660 dev_err(dev->dev, "failed to get PHY-parent node for port %d\n",
2661 dp->index);
2662 phys_are_valid = false;
2663 } else if (phy_parent_node != mdio_np) {
2664 dev_err(dev->dev, "PHY-parent node mismatch for port %d, expected %pOF, got %pOF\n",
2665 dp->index, mdio_np, phy_parent_node);
2666 phys_are_valid = false;
2667 } else {
2668 ret = of_property_read_u32(phy_node, "reg", &phy_addr);
2669 if (ret < 0) {
2670 dev_err(dev->dev, "failed to read PHY address for port %d. Error %d\n",
2671 dp->index, ret);
2672 phys_are_valid = false;
2673 } else if (phy_addr != dev->phy_addr_map[dp->index]) {
2674 dev_err(dev->dev, "PHY address mismatch for port %d, expected 0x%x, got 0x%x\n",
2675 dp->index, dev->phy_addr_map[dp->index],
2676 phy_addr);
2677 phys_are_valid = false;
2678 } else {
2679 bus->phy_mask |= BIT(phy_addr);
2680 }
2681 }
2682
2683 of_node_put(phy_node);
2684 of_node_put(phy_parent_node);
2685 }
2686
2687 if (!phys_are_valid)
2688 return -EINVAL;
2689
2690 return 0;
2691 }
2692
2693 /**
2694 * ksz_mdio_register - Register and configure the MDIO bus for the KSZ device.
2695 * @dev: Pointer to the KSZ device structure.
2696 *
2697 * This function sets up and registers an MDIO bus for the KSZ switch device,
2698 * allowing access to its internal PHYs. If the device supports side MDIO,
2699 * the function will configure the external MDIO controller specified by the
2700 * "mdio-parent-bus" device tree property to directly manage internal PHYs.
2701 * Otherwise, SPI or I2C access is set up for PHY access.
2702 *
2703 * Return: 0 on success, or a negative error code on failure.
2704 */
ksz_mdio_register(struct ksz_device * dev)2705 static int ksz_mdio_register(struct ksz_device *dev)
2706 {
2707 struct device_node *parent_bus_node;
2708 struct mii_bus *parent_bus = NULL;
2709 struct dsa_switch *ds = dev->ds;
2710 struct device_node *mdio_np;
2711 struct mii_bus *bus;
2712 int ret, i;
2713
2714 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio");
2715 if (!mdio_np)
2716 return 0;
2717
2718 parent_bus_node = of_parse_phandle(mdio_np, "mdio-parent-bus", 0);
2719 if (parent_bus_node && !dev->info->phy_side_mdio_supported) {
2720 dev_err(dev->dev, "Side MDIO bus is not supported for this HW, ignoring 'mdio-parent-bus' property.\n");
2721 ret = -EINVAL;
2722
2723 goto put_mdio_node;
2724 } else if (parent_bus_node) {
2725 parent_bus = of_mdio_find_bus(parent_bus_node);
2726 if (!parent_bus) {
2727 ret = -EPROBE_DEFER;
2728
2729 goto put_mdio_node;
2730 }
2731
2732 dev->parent_mdio_bus = parent_bus;
2733 }
2734
2735 bus = devm_mdiobus_alloc(ds->dev);
2736 if (!bus) {
2737 ret = -ENOMEM;
2738 goto put_mdio_node;
2739 }
2740
2741 if (dev->dev_ops->mdio_bus_preinit) {
2742 ret = dev->dev_ops->mdio_bus_preinit(dev, !!parent_bus);
2743 if (ret)
2744 goto put_mdio_node;
2745 }
2746
2747 if (dev->dev_ops->create_phy_addr_map) {
2748 ret = dev->dev_ops->create_phy_addr_map(dev, !!parent_bus);
2749 if (ret)
2750 goto put_mdio_node;
2751 } else {
2752 for (i = 0; i < dev->info->port_cnt; i++)
2753 dev->phy_addr_map[i] = i;
2754 }
2755
2756 bus->priv = dev;
2757 if (parent_bus) {
2758 bus->read = ksz_parent_mdio_read;
2759 bus->write = ksz_parent_mdio_write;
2760 bus->name = "KSZ side MDIO";
2761 snprintf(bus->id, MII_BUS_ID_SIZE, "ksz-side-mdio-%d",
2762 ds->index);
2763 } else {
2764 bus->read = ksz_sw_mdio_read;
2765 bus->write = ksz_sw_mdio_write;
2766 bus->name = "ksz user smi";
2767 if (ds->dst->index != 0) {
2768 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d-%d", ds->dst->index, ds->index);
2769 } else {
2770 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index);
2771 }
2772 }
2773
2774 ret = ksz_parse_dt_phy_config(dev, bus, mdio_np);
2775 if (ret)
2776 goto put_mdio_node;
2777
2778 ds->phys_mii_mask = bus->phy_mask;
2779 bus->parent = ds->dev;
2780
2781 ds->user_mii_bus = bus;
2782
2783 if (dev->irq > 0) {
2784 ret = ksz_irq_phy_setup(dev);
2785 if (ret)
2786 goto put_mdio_node;
2787 }
2788
2789 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np);
2790 if (ret) {
2791 dev_err(ds->dev, "unable to register MDIO bus %s\n",
2792 bus->id);
2793 if (dev->irq > 0)
2794 ksz_irq_phy_free(dev);
2795 }
2796
2797 put_mdio_node:
2798 of_node_put(mdio_np);
2799 of_node_put(parent_bus_node);
2800
2801 return ret;
2802 }
2803
ksz_irq_mask(struct irq_data * d)2804 static void ksz_irq_mask(struct irq_data *d)
2805 {
2806 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2807
2808 kirq->masked |= BIT(d->hwirq);
2809 }
2810
ksz_irq_unmask(struct irq_data * d)2811 static void ksz_irq_unmask(struct irq_data *d)
2812 {
2813 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2814
2815 kirq->masked &= ~BIT(d->hwirq);
2816 }
2817
ksz_irq_bus_lock(struct irq_data * d)2818 static void ksz_irq_bus_lock(struct irq_data *d)
2819 {
2820 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2821
2822 mutex_lock(&kirq->dev->lock_irq);
2823 }
2824
ksz_irq_bus_sync_unlock(struct irq_data * d)2825 static void ksz_irq_bus_sync_unlock(struct irq_data *d)
2826 {
2827 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2828 struct ksz_device *dev = kirq->dev;
2829 int ret;
2830
2831 ret = ksz_write8(dev, kirq->reg_mask, kirq->masked);
2832 if (ret)
2833 dev_err(dev->dev, "failed to change IRQ mask\n");
2834
2835 mutex_unlock(&dev->lock_irq);
2836 }
2837
2838 static const struct irq_chip ksz_irq_chip = {
2839 .name = "ksz-irq",
2840 .irq_mask = ksz_irq_mask,
2841 .irq_unmask = ksz_irq_unmask,
2842 .irq_bus_lock = ksz_irq_bus_lock,
2843 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock,
2844 };
2845
ksz_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)2846 static int ksz_irq_domain_map(struct irq_domain *d,
2847 unsigned int irq, irq_hw_number_t hwirq)
2848 {
2849 irq_set_chip_data(irq, d->host_data);
2850 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq);
2851 irq_set_noprobe(irq);
2852
2853 return 0;
2854 }
2855
2856 static const struct irq_domain_ops ksz_irq_domain_ops = {
2857 .map = ksz_irq_domain_map,
2858 .xlate = irq_domain_xlate_twocell,
2859 };
2860
ksz_irq_free(struct ksz_irq * kirq)2861 static void ksz_irq_free(struct ksz_irq *kirq)
2862 {
2863 int irq, virq;
2864
2865 free_irq(kirq->irq_num, kirq);
2866
2867 for (irq = 0; irq < kirq->nirqs; irq++) {
2868 virq = irq_find_mapping(kirq->domain, irq);
2869 irq_dispose_mapping(virq);
2870 }
2871
2872 irq_domain_remove(kirq->domain);
2873 }
2874
ksz_irq_thread_fn(int irq,void * dev_id)2875 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id)
2876 {
2877 struct ksz_irq *kirq = dev_id;
2878 unsigned int nhandled = 0;
2879 struct ksz_device *dev;
2880 unsigned int sub_irq;
2881 u8 data;
2882 int ret;
2883 u8 n;
2884
2885 dev = kirq->dev;
2886
2887 /* Read interrupt status register */
2888 ret = ksz_read8(dev, kirq->reg_status, &data);
2889 if (ret)
2890 goto out;
2891
2892 for (n = 0; n < kirq->nirqs; ++n) {
2893 if (data & BIT(n)) {
2894 sub_irq = irq_find_mapping(kirq->domain, n);
2895 handle_nested_irq(sub_irq);
2896 ++nhandled;
2897 }
2898 }
2899 out:
2900 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
2901 }
2902
ksz_irq_common_setup(struct ksz_device * dev,struct ksz_irq * kirq)2903 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq)
2904 {
2905 int ret, n;
2906
2907 kirq->dev = dev;
2908 kirq->masked = ~0;
2909
2910 kirq->domain = irq_domain_create_simple(dev_fwnode(dev->dev), kirq->nirqs, 0,
2911 &ksz_irq_domain_ops, kirq);
2912 if (!kirq->domain)
2913 return -ENOMEM;
2914
2915 for (n = 0; n < kirq->nirqs; n++)
2916 irq_create_mapping(kirq->domain, n);
2917
2918 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn,
2919 IRQF_ONESHOT, kirq->name, kirq);
2920 if (ret)
2921 goto out;
2922
2923 return 0;
2924
2925 out:
2926 ksz_irq_free(kirq);
2927
2928 return ret;
2929 }
2930
ksz_girq_setup(struct ksz_device * dev)2931 static int ksz_girq_setup(struct ksz_device *dev)
2932 {
2933 struct ksz_irq *girq = &dev->girq;
2934
2935 girq->nirqs = dev->info->port_cnt;
2936 girq->reg_mask = REG_SW_PORT_INT_MASK__1;
2937 girq->reg_status = REG_SW_PORT_INT_STATUS__1;
2938 snprintf(girq->name, sizeof(girq->name), "global_port_irq");
2939
2940 girq->irq_num = dev->irq;
2941
2942 return ksz_irq_common_setup(dev, girq);
2943 }
2944
ksz_pirq_setup(struct ksz_device * dev,u8 p)2945 static int ksz_pirq_setup(struct ksz_device *dev, u8 p)
2946 {
2947 struct ksz_irq *pirq = &dev->ports[p].pirq;
2948
2949 pirq->nirqs = dev->info->port_nirqs;
2950 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
2951 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
2952 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p);
2953
2954 pirq->irq_num = irq_find_mapping(dev->girq.domain, p);
2955 if (pirq->irq_num < 0)
2956 return pirq->irq_num;
2957
2958 return ksz_irq_common_setup(dev, pirq);
2959 }
2960
2961 static int ksz_parse_drive_strength(struct ksz_device *dev);
2962
ksz_setup(struct dsa_switch * ds)2963 static int ksz_setup(struct dsa_switch *ds)
2964 {
2965 struct ksz_device *dev = ds->priv;
2966 u16 storm_mask, storm_rate;
2967 struct dsa_port *dp;
2968 struct ksz_port *p;
2969 const u16 *regs;
2970 int ret;
2971
2972 regs = dev->info->regs;
2973
2974 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
2975 dev->info->num_vlans, GFP_KERNEL);
2976 if (!dev->vlan_cache)
2977 return -ENOMEM;
2978
2979 ret = dev->dev_ops->reset(dev);
2980 if (ret) {
2981 dev_err(ds->dev, "failed to reset switch\n");
2982 return ret;
2983 }
2984
2985 ret = ksz_parse_drive_strength(dev);
2986 if (ret)
2987 return ret;
2988
2989 if (ksz_has_sgmii_port(dev) && dev->dev_ops->pcs_create) {
2990 ret = dev->dev_ops->pcs_create(dev);
2991 if (ret)
2992 return ret;
2993 }
2994
2995 /* set broadcast storm protection 10% rate */
2996 storm_mask = BROADCAST_STORM_RATE;
2997 storm_rate = (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100;
2998 if (ksz_is_ksz8463(dev)) {
2999 storm_mask = swab16(storm_mask);
3000 storm_rate = swab16(storm_rate);
3001 }
3002 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL],
3003 storm_mask, storm_rate);
3004
3005 dev->dev_ops->config_cpu_port(ds);
3006
3007 dev->dev_ops->enable_stp_addr(dev);
3008
3009 ds->num_tx_queues = dev->info->num_tx_queues;
3010
3011 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL],
3012 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
3013
3014 ksz_init_mib_timer(dev);
3015
3016 ds->configure_vlan_while_not_filtering = false;
3017 ds->dscp_prio_mapping_is_global = true;
3018
3019 if (dev->dev_ops->setup) {
3020 ret = dev->dev_ops->setup(ds);
3021 if (ret)
3022 return ret;
3023 }
3024
3025 /* Start with learning disabled on standalone user ports, and enabled
3026 * on the CPU port. In lack of other finer mechanisms, learning on the
3027 * CPU port will avoid flooding bridge local addresses on the network
3028 * in some cases.
3029 */
3030 p = &dev->ports[dev->cpu_port];
3031 p->learning = true;
3032
3033 if (dev->irq > 0) {
3034 ret = ksz_girq_setup(dev);
3035 if (ret)
3036 return ret;
3037
3038 dsa_switch_for_each_user_port(dp, dev->ds) {
3039 ret = ksz_pirq_setup(dev, dp->index);
3040 if (ret)
3041 goto out_girq;
3042
3043 if (dev->info->ptp_capable) {
3044 ret = ksz_ptp_irq_setup(ds, dp->index);
3045 if (ret)
3046 goto out_pirq;
3047 }
3048 }
3049 }
3050
3051 if (dev->info->ptp_capable) {
3052 ret = ksz_ptp_clock_register(ds);
3053 if (ret) {
3054 dev_err(dev->dev, "Failed to register PTP clock: %d\n",
3055 ret);
3056 goto out_ptpirq;
3057 }
3058 }
3059
3060 ret = ksz_mdio_register(dev);
3061 if (ret < 0) {
3062 dev_err(dev->dev, "failed to register the mdio");
3063 goto out_ptp_clock_unregister;
3064 }
3065
3066 ret = ksz_dcb_init(dev);
3067 if (ret)
3068 goto out_ptp_clock_unregister;
3069
3070 /* start switch */
3071 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL],
3072 SW_START, SW_START);
3073
3074 return 0;
3075
3076 out_ptp_clock_unregister:
3077 if (dev->info->ptp_capable)
3078 ksz_ptp_clock_unregister(ds);
3079 out_ptpirq:
3080 if (dev->irq > 0 && dev->info->ptp_capable)
3081 dsa_switch_for_each_user_port(dp, dev->ds)
3082 ksz_ptp_irq_free(ds, dp->index);
3083 out_pirq:
3084 if (dev->irq > 0)
3085 dsa_switch_for_each_user_port(dp, dev->ds)
3086 ksz_irq_free(&dev->ports[dp->index].pirq);
3087 out_girq:
3088 if (dev->irq > 0)
3089 ksz_irq_free(&dev->girq);
3090
3091 return ret;
3092 }
3093
ksz_teardown(struct dsa_switch * ds)3094 static void ksz_teardown(struct dsa_switch *ds)
3095 {
3096 struct ksz_device *dev = ds->priv;
3097 struct dsa_port *dp;
3098
3099 if (dev->info->ptp_capable)
3100 ksz_ptp_clock_unregister(ds);
3101
3102 if (dev->irq > 0) {
3103 dsa_switch_for_each_user_port(dp, dev->ds) {
3104 if (dev->info->ptp_capable)
3105 ksz_ptp_irq_free(ds, dp->index);
3106
3107 ksz_irq_free(&dev->ports[dp->index].pirq);
3108 }
3109
3110 ksz_irq_free(&dev->girq);
3111 }
3112
3113 if (dev->dev_ops->teardown)
3114 dev->dev_ops->teardown(ds);
3115 }
3116
port_r_cnt(struct ksz_device * dev,int port)3117 static void port_r_cnt(struct ksz_device *dev, int port)
3118 {
3119 struct ksz_port_mib *mib = &dev->ports[port].mib;
3120 u64 *dropped;
3121
3122 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
3123 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
3124 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
3125 &mib->counters[mib->cnt_ptr]);
3126 ++mib->cnt_ptr;
3127 }
3128
3129 /* last one in storage */
3130 dropped = &mib->counters[dev->info->mib_cnt];
3131
3132 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
3133 while (mib->cnt_ptr < dev->info->mib_cnt) {
3134 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
3135 dropped, &mib->counters[mib->cnt_ptr]);
3136 ++mib->cnt_ptr;
3137 }
3138 mib->cnt_ptr = 0;
3139 }
3140
ksz_mib_read_work(struct work_struct * work)3141 static void ksz_mib_read_work(struct work_struct *work)
3142 {
3143 struct ksz_device *dev = container_of(work, struct ksz_device,
3144 mib_read.work);
3145 struct ksz_port_mib *mib;
3146 struct ksz_port *p;
3147 int i;
3148
3149 for (i = 0; i < dev->info->port_cnt; i++) {
3150 if (dsa_is_unused_port(dev->ds, i))
3151 continue;
3152
3153 p = &dev->ports[i];
3154 mib = &p->mib;
3155 mutex_lock(&mib->cnt_mutex);
3156
3157 /* Only read MIB counters when the port is told to do.
3158 * If not, read only dropped counters when link is not up.
3159 */
3160 if (!p->read) {
3161 const struct dsa_port *dp = dsa_to_port(dev->ds, i);
3162
3163 if (!netif_carrier_ok(dp->user))
3164 mib->cnt_ptr = dev->info->reg_mib_cnt;
3165 }
3166 port_r_cnt(dev, i);
3167 p->read = false;
3168
3169 if (dev->dev_ops->r_mib_stat64)
3170 dev->dev_ops->r_mib_stat64(dev, i);
3171
3172 mutex_unlock(&mib->cnt_mutex);
3173 }
3174
3175 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
3176 }
3177
ksz_init_mib_timer(struct ksz_device * dev)3178 void ksz_init_mib_timer(struct ksz_device *dev)
3179 {
3180 int i;
3181
3182 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
3183
3184 for (i = 0; i < dev->info->port_cnt; i++) {
3185 struct ksz_port_mib *mib = &dev->ports[i].mib;
3186
3187 dev->dev_ops->port_init_cnt(dev, i);
3188
3189 mib->cnt_ptr = 0;
3190 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
3191 }
3192 }
3193
ksz_phy_read16(struct dsa_switch * ds,int addr,int reg)3194 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
3195 {
3196 struct ksz_device *dev = ds->priv;
3197 u16 val = 0xffff;
3198 int ret;
3199
3200 ret = dev->dev_ops->r_phy(dev, addr, reg, &val);
3201 if (ret)
3202 return ret;
3203
3204 return val;
3205 }
3206
ksz_phy_write16(struct dsa_switch * ds,int addr,int reg,u16 val)3207 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
3208 {
3209 struct ksz_device *dev = ds->priv;
3210 int ret;
3211
3212 ret = dev->dev_ops->w_phy(dev, addr, reg, val);
3213 if (ret)
3214 return ret;
3215
3216 return 0;
3217 }
3218
ksz_get_phy_flags(struct dsa_switch * ds,int port)3219 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
3220 {
3221 struct ksz_device *dev = ds->priv;
3222
3223 switch (dev->chip_id) {
3224 case KSZ88X3_CHIP_ID:
3225 /* Silicon Errata Sheet (DS80000830A):
3226 * Port 1 does not work with LinkMD Cable-Testing.
3227 * Port 1 does not respond to received PAUSE control frames.
3228 */
3229 if (!port)
3230 return MICREL_KSZ8_P1_ERRATA;
3231 break;
3232 }
3233
3234 return 0;
3235 }
3236
ksz_phylink_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)3237 static void ksz_phylink_mac_link_down(struct phylink_config *config,
3238 unsigned int mode,
3239 phy_interface_t interface)
3240 {
3241 struct dsa_port *dp = dsa_phylink_to_port(config);
3242 struct ksz_device *dev = dp->ds->priv;
3243
3244 /* Read all MIB counters when the link is going down. */
3245 dev->ports[dp->index].read = true;
3246 /* timer started */
3247 if (dev->mib_read_interval)
3248 schedule_delayed_work(&dev->mib_read, 0);
3249 }
3250
ksz_sset_count(struct dsa_switch * ds,int port,int sset)3251 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
3252 {
3253 struct ksz_device *dev = ds->priv;
3254
3255 if (sset != ETH_SS_STATS)
3256 return 0;
3257
3258 return dev->info->mib_cnt;
3259 }
3260
ksz_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * buf)3261 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
3262 uint64_t *buf)
3263 {
3264 const struct dsa_port *dp = dsa_to_port(ds, port);
3265 struct ksz_device *dev = ds->priv;
3266 struct ksz_port_mib *mib;
3267
3268 mib = &dev->ports[port].mib;
3269 mutex_lock(&mib->cnt_mutex);
3270
3271 /* Only read dropped counters if no link. */
3272 if (!netif_carrier_ok(dp->user))
3273 mib->cnt_ptr = dev->info->reg_mib_cnt;
3274 port_r_cnt(dev, port);
3275 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
3276 mutex_unlock(&mib->cnt_mutex);
3277 }
3278
ksz_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)3279 static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
3280 struct dsa_bridge bridge,
3281 bool *tx_fwd_offload,
3282 struct netlink_ext_ack *extack)
3283 {
3284 /* port_stp_state_set() will be called after to put the port in
3285 * appropriate state so there is no need to do anything.
3286 */
3287
3288 return 0;
3289 }
3290
ksz_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)3291 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
3292 struct dsa_bridge bridge)
3293 {
3294 /* port_stp_state_set() will be called after to put the port in
3295 * forwarding state so there is no need to do anything.
3296 */
3297 }
3298
ksz_port_fast_age(struct dsa_switch * ds,int port)3299 static void ksz_port_fast_age(struct dsa_switch *ds, int port)
3300 {
3301 struct ksz_device *dev = ds->priv;
3302
3303 dev->dev_ops->flush_dyn_mac_table(dev, port);
3304 }
3305
ksz_set_ageing_time(struct dsa_switch * ds,unsigned int msecs)3306 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
3307 {
3308 struct ksz_device *dev = ds->priv;
3309
3310 if (!dev->dev_ops->set_ageing_time)
3311 return -EOPNOTSUPP;
3312
3313 return dev->dev_ops->set_ageing_time(dev, msecs);
3314 }
3315
ksz_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)3316 static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
3317 const unsigned char *addr, u16 vid,
3318 struct dsa_db db)
3319 {
3320 struct ksz_device *dev = ds->priv;
3321
3322 if (!dev->dev_ops->fdb_add)
3323 return -EOPNOTSUPP;
3324
3325 return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
3326 }
3327
ksz_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)3328 static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
3329 const unsigned char *addr,
3330 u16 vid, struct dsa_db db)
3331 {
3332 struct ksz_device *dev = ds->priv;
3333
3334 if (!dev->dev_ops->fdb_del)
3335 return -EOPNOTSUPP;
3336
3337 return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
3338 }
3339
ksz_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)3340 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
3341 dsa_fdb_dump_cb_t *cb, void *data)
3342 {
3343 struct ksz_device *dev = ds->priv;
3344
3345 if (!dev->dev_ops->fdb_dump)
3346 return -EOPNOTSUPP;
3347
3348 return dev->dev_ops->fdb_dump(dev, port, cb, data);
3349 }
3350
ksz_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)3351 static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
3352 const struct switchdev_obj_port_mdb *mdb,
3353 struct dsa_db db)
3354 {
3355 struct ksz_device *dev = ds->priv;
3356
3357 if (!dev->dev_ops->mdb_add)
3358 return -EOPNOTSUPP;
3359
3360 return dev->dev_ops->mdb_add(dev, port, mdb, db);
3361 }
3362
ksz_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)3363 static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
3364 const struct switchdev_obj_port_mdb *mdb,
3365 struct dsa_db db)
3366 {
3367 struct ksz_device *dev = ds->priv;
3368
3369 if (!dev->dev_ops->mdb_del)
3370 return -EOPNOTSUPP;
3371
3372 return dev->dev_ops->mdb_del(dev, port, mdb, db);
3373 }
3374
ksz9477_set_default_prio_queue_mapping(struct ksz_device * dev,int port)3375 static int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev,
3376 int port)
3377 {
3378 u32 queue_map = 0;
3379 int ipm;
3380
3381 for (ipm = 0; ipm < dev->info->num_ipms; ipm++) {
3382 int queue;
3383
3384 /* Traffic Type (TT) is corresponding to the Internal Priority
3385 * Map (IPM) in the switch. Traffic Class (TC) is
3386 * corresponding to the queue in the switch.
3387 */
3388 queue = ieee8021q_tt_to_tc(ipm, dev->info->num_tx_queues);
3389 if (queue < 0)
3390 return queue;
3391
3392 queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S);
3393 }
3394
3395 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
3396 }
3397
ksz_port_setup(struct dsa_switch * ds,int port)3398 static int ksz_port_setup(struct dsa_switch *ds, int port)
3399 {
3400 struct ksz_device *dev = ds->priv;
3401 int ret;
3402
3403 if (!dsa_is_user_port(ds, port))
3404 return 0;
3405
3406 /* setup user port */
3407 dev->dev_ops->port_setup(dev, port, false);
3408
3409 if (!is_ksz8(dev)) {
3410 ret = ksz9477_set_default_prio_queue_mapping(dev, port);
3411 if (ret)
3412 return ret;
3413 }
3414
3415 /* port_stp_state_set() will be called after to enable the port so
3416 * there is no need to do anything.
3417 */
3418
3419 return ksz_dcb_init_port(dev, port);
3420 }
3421
ksz_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)3422 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
3423 {
3424 struct ksz_device *dev = ds->priv;
3425 struct ksz_port *p;
3426 const u16 *regs;
3427 u8 data;
3428
3429 regs = dev->info->regs;
3430
3431 ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
3432 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
3433
3434 p = &dev->ports[port];
3435
3436 switch (state) {
3437 case BR_STATE_DISABLED:
3438 data |= PORT_LEARN_DISABLE;
3439 break;
3440 case BR_STATE_LISTENING:
3441 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
3442 break;
3443 case BR_STATE_LEARNING:
3444 data |= PORT_RX_ENABLE;
3445 if (!p->learning)
3446 data |= PORT_LEARN_DISABLE;
3447 break;
3448 case BR_STATE_FORWARDING:
3449 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
3450 if (!p->learning)
3451 data |= PORT_LEARN_DISABLE;
3452 break;
3453 case BR_STATE_BLOCKING:
3454 data |= PORT_LEARN_DISABLE;
3455 break;
3456 default:
3457 dev_err(ds->dev, "invalid STP state: %d\n", state);
3458 return;
3459 }
3460
3461 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
3462
3463 p->stp_state = state;
3464
3465 ksz_update_port_member(dev, port);
3466 }
3467
ksz_port_teardown(struct dsa_switch * ds,int port)3468 static void ksz_port_teardown(struct dsa_switch *ds, int port)
3469 {
3470 struct ksz_device *dev = ds->priv;
3471
3472 switch (dev->chip_id) {
3473 case KSZ8563_CHIP_ID:
3474 case KSZ8567_CHIP_ID:
3475 case KSZ9477_CHIP_ID:
3476 case KSZ9563_CHIP_ID:
3477 case KSZ9567_CHIP_ID:
3478 case KSZ9893_CHIP_ID:
3479 case KSZ9896_CHIP_ID:
3480 case KSZ9897_CHIP_ID:
3481 case LAN9646_CHIP_ID:
3482 if (dsa_is_user_port(ds, port))
3483 ksz9477_port_acl_free(dev, port);
3484 }
3485 }
3486
ksz_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)3487 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
3488 struct switchdev_brport_flags flags,
3489 struct netlink_ext_ack *extack)
3490 {
3491 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED))
3492 return -EINVAL;
3493
3494 return 0;
3495 }
3496
ksz_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)3497 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
3498 struct switchdev_brport_flags flags,
3499 struct netlink_ext_ack *extack)
3500 {
3501 struct ksz_device *dev = ds->priv;
3502 struct ksz_port *p = &dev->ports[port];
3503
3504 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) {
3505 if (flags.mask & BR_LEARNING)
3506 p->learning = !!(flags.val & BR_LEARNING);
3507
3508 if (flags.mask & BR_ISOLATED)
3509 p->isolated = !!(flags.val & BR_ISOLATED);
3510
3511 /* Make the change take effect immediately */
3512 ksz_port_stp_state_set(ds, port, p->stp_state);
3513 }
3514
3515 return 0;
3516 }
3517
ksz_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)3518 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
3519 int port,
3520 enum dsa_tag_protocol mp)
3521 {
3522 struct ksz_device *dev = ds->priv;
3523 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
3524
3525 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev))
3526 proto = DSA_TAG_PROTO_KSZ8795;
3527
3528 if (dev->chip_id == KSZ88X3_CHIP_ID ||
3529 dev->chip_id == KSZ8463_CHIP_ID ||
3530 dev->chip_id == KSZ8563_CHIP_ID ||
3531 dev->chip_id == KSZ9893_CHIP_ID ||
3532 dev->chip_id == KSZ9563_CHIP_ID)
3533 proto = DSA_TAG_PROTO_KSZ9893;
3534
3535 if (dev->chip_id == KSZ8567_CHIP_ID ||
3536 dev->chip_id == KSZ9477_CHIP_ID ||
3537 dev->chip_id == KSZ9896_CHIP_ID ||
3538 dev->chip_id == KSZ9897_CHIP_ID ||
3539 dev->chip_id == KSZ9567_CHIP_ID ||
3540 dev->chip_id == LAN9646_CHIP_ID)
3541 proto = DSA_TAG_PROTO_KSZ9477;
3542
3543 if (is_lan937x(dev))
3544 proto = DSA_TAG_PROTO_LAN937X;
3545
3546 return proto;
3547 }
3548
ksz_connect_tag_protocol(struct dsa_switch * ds,enum dsa_tag_protocol proto)3549 static int ksz_connect_tag_protocol(struct dsa_switch *ds,
3550 enum dsa_tag_protocol proto)
3551 {
3552 struct ksz_tagger_data *tagger_data;
3553
3554 switch (proto) {
3555 case DSA_TAG_PROTO_KSZ8795:
3556 return 0;
3557 case DSA_TAG_PROTO_KSZ9893:
3558 case DSA_TAG_PROTO_KSZ9477:
3559 case DSA_TAG_PROTO_LAN937X:
3560 tagger_data = ksz_tagger_data(ds);
3561 tagger_data->xmit_work_fn = ksz_port_deferred_xmit;
3562 return 0;
3563 default:
3564 return -EPROTONOSUPPORT;
3565 }
3566 }
3567
ksz_port_vlan_filtering(struct dsa_switch * ds,int port,bool flag,struct netlink_ext_ack * extack)3568 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
3569 bool flag, struct netlink_ext_ack *extack)
3570 {
3571 struct ksz_device *dev = ds->priv;
3572
3573 if (!dev->dev_ops->vlan_filtering)
3574 return -EOPNOTSUPP;
3575
3576 return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
3577 }
3578
ksz_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)3579 static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
3580 const struct switchdev_obj_port_vlan *vlan,
3581 struct netlink_ext_ack *extack)
3582 {
3583 struct ksz_device *dev = ds->priv;
3584
3585 if (!dev->dev_ops->vlan_add)
3586 return -EOPNOTSUPP;
3587
3588 return dev->dev_ops->vlan_add(dev, port, vlan, extack);
3589 }
3590
ksz_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)3591 static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
3592 const struct switchdev_obj_port_vlan *vlan)
3593 {
3594 struct ksz_device *dev = ds->priv;
3595
3596 if (!dev->dev_ops->vlan_del)
3597 return -EOPNOTSUPP;
3598
3599 return dev->dev_ops->vlan_del(dev, port, vlan);
3600 }
3601
ksz_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)3602 static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
3603 struct dsa_mall_mirror_tc_entry *mirror,
3604 bool ingress, struct netlink_ext_ack *extack)
3605 {
3606 struct ksz_device *dev = ds->priv;
3607
3608 if (!dev->dev_ops->mirror_add)
3609 return -EOPNOTSUPP;
3610
3611 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
3612 }
3613
ksz_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)3614 static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
3615 struct dsa_mall_mirror_tc_entry *mirror)
3616 {
3617 struct ksz_device *dev = ds->priv;
3618
3619 if (dev->dev_ops->mirror_del)
3620 dev->dev_ops->mirror_del(dev, port, mirror);
3621 }
3622
ksz_change_mtu(struct dsa_switch * ds,int port,int mtu)3623 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
3624 {
3625 struct ksz_device *dev = ds->priv;
3626
3627 if (!dev->dev_ops->change_mtu)
3628 return -EOPNOTSUPP;
3629
3630 return dev->dev_ops->change_mtu(dev, port, mtu);
3631 }
3632
ksz_max_mtu(struct dsa_switch * ds,int port)3633 static int ksz_max_mtu(struct dsa_switch *ds, int port)
3634 {
3635 struct ksz_device *dev = ds->priv;
3636
3637 switch (dev->chip_id) {
3638 case KSZ8795_CHIP_ID:
3639 case KSZ8794_CHIP_ID:
3640 case KSZ8765_CHIP_ID:
3641 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3642 case KSZ8463_CHIP_ID:
3643 case KSZ88X3_CHIP_ID:
3644 case KSZ8864_CHIP_ID:
3645 case KSZ8895_CHIP_ID:
3646 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3647 case KSZ8563_CHIP_ID:
3648 case KSZ8567_CHIP_ID:
3649 case KSZ9477_CHIP_ID:
3650 case KSZ9563_CHIP_ID:
3651 case KSZ9567_CHIP_ID:
3652 case KSZ9893_CHIP_ID:
3653 case KSZ9896_CHIP_ID:
3654 case KSZ9897_CHIP_ID:
3655 case LAN9370_CHIP_ID:
3656 case LAN9371_CHIP_ID:
3657 case LAN9372_CHIP_ID:
3658 case LAN9373_CHIP_ID:
3659 case LAN9374_CHIP_ID:
3660 case LAN9646_CHIP_ID:
3661 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3662 }
3663
3664 return -EOPNOTSUPP;
3665 }
3666
3667 /**
3668 * ksz_support_eee - Determine Energy Efficient Ethernet (EEE) support for a
3669 * port
3670 * @ds: Pointer to the DSA switch structure
3671 * @port: Port number to check
3672 *
3673 * This function also documents devices where EEE was initially advertised but
3674 * later withdrawn due to reliability issues, as described in official errata
3675 * documents. These devices are explicitly listed to record known limitations,
3676 * even if there is no technical necessity for runtime checks.
3677 *
3678 * Returns: true if the internal PHY on the given port supports fully
3679 * operational EEE, false otherwise.
3680 */
ksz_support_eee(struct dsa_switch * ds,int port)3681 static bool ksz_support_eee(struct dsa_switch *ds, int port)
3682 {
3683 struct ksz_device *dev = ds->priv;
3684
3685 if (!dev->info->internal_phy[port])
3686 return false;
3687
3688 switch (dev->chip_id) {
3689 case KSZ8563_CHIP_ID:
3690 case KSZ9563_CHIP_ID:
3691 case KSZ9893_CHIP_ID:
3692 return true;
3693 case KSZ8567_CHIP_ID:
3694 /* KSZ8567R Errata DS80000752C Module 4 */
3695 case KSZ8765_CHIP_ID:
3696 case KSZ8794_CHIP_ID:
3697 case KSZ8795_CHIP_ID:
3698 /* KSZ879x/KSZ877x/KSZ876x Errata DS80000687C Module 2 */
3699 case KSZ9477_CHIP_ID:
3700 /* KSZ9477S Errata DS80000754A Module 4 */
3701 case KSZ9567_CHIP_ID:
3702 /* KSZ9567S Errata DS80000756A Module 4 */
3703 case KSZ9896_CHIP_ID:
3704 /* KSZ9896C Errata DS80000757A Module 3 */
3705 case KSZ9897_CHIP_ID:
3706 case LAN9646_CHIP_ID:
3707 /* KSZ9897R Errata DS80000758C Module 4 */
3708 /* Energy Efficient Ethernet (EEE) feature select must be
3709 * manually disabled
3710 * The EEE feature is enabled by default, but it is not fully
3711 * operational. It must be manually disabled through register
3712 * controls. If not disabled, the PHY ports can auto-negotiate
3713 * to enable EEE, and this feature can cause link drops when
3714 * linked to another device supporting EEE.
3715 *
3716 * The same item appears in the errata for all switches above.
3717 */
3718 break;
3719 }
3720
3721 return false;
3722 }
3723
ksz_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_keee * e)3724 static int ksz_set_mac_eee(struct dsa_switch *ds, int port,
3725 struct ethtool_keee *e)
3726 {
3727 struct ksz_device *dev = ds->priv;
3728
3729 if (!e->tx_lpi_enabled) {
3730 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n");
3731 return -EINVAL;
3732 }
3733
3734 if (e->tx_lpi_timer) {
3735 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n");
3736 return -EINVAL;
3737 }
3738
3739 return 0;
3740 }
3741
ksz_set_xmii(struct ksz_device * dev,int port,phy_interface_t interface)3742 static void ksz_set_xmii(struct ksz_device *dev, int port,
3743 phy_interface_t interface)
3744 {
3745 const u8 *bitval = dev->info->xmii_ctrl1;
3746 struct ksz_port *p = &dev->ports[port];
3747 const u16 *regs = dev->info->regs;
3748 u8 data8;
3749
3750 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3751
3752 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
3753 P_RGMII_ID_EG_ENABLE);
3754
3755 switch (interface) {
3756 case PHY_INTERFACE_MODE_MII:
3757 data8 |= bitval[P_MII_SEL];
3758 break;
3759 case PHY_INTERFACE_MODE_RMII:
3760 data8 |= bitval[P_RMII_SEL];
3761 break;
3762 case PHY_INTERFACE_MODE_GMII:
3763 data8 |= bitval[P_GMII_SEL];
3764 break;
3765 case PHY_INTERFACE_MODE_RGMII:
3766 case PHY_INTERFACE_MODE_RGMII_ID:
3767 case PHY_INTERFACE_MODE_RGMII_TXID:
3768 case PHY_INTERFACE_MODE_RGMII_RXID:
3769 data8 |= bitval[P_RGMII_SEL];
3770 /* On KSZ9893, disable RGMII in-band status support */
3771 if (dev->chip_id == KSZ9893_CHIP_ID ||
3772 dev->chip_id == KSZ8563_CHIP_ID ||
3773 dev->chip_id == KSZ9563_CHIP_ID ||
3774 is_lan937x(dev))
3775 data8 &= ~P_MII_MAC_MODE;
3776 break;
3777 default:
3778 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
3779 phy_modes(interface), port);
3780 return;
3781 }
3782
3783 if (p->rgmii_tx_val)
3784 data8 |= P_RGMII_ID_EG_ENABLE;
3785
3786 if (p->rgmii_rx_val)
3787 data8 |= P_RGMII_ID_IG_ENABLE;
3788
3789 /* Write the updated value */
3790 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
3791 }
3792
ksz_get_xmii(struct ksz_device * dev,int port,bool gbit)3793 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
3794 {
3795 const u8 *bitval = dev->info->xmii_ctrl1;
3796 const u16 *regs = dev->info->regs;
3797 phy_interface_t interface;
3798 u8 data8;
3799 u8 val;
3800
3801 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3802
3803 val = FIELD_GET(P_MII_SEL_M, data8);
3804
3805 if (val == bitval[P_MII_SEL]) {
3806 if (gbit)
3807 interface = PHY_INTERFACE_MODE_GMII;
3808 else
3809 interface = PHY_INTERFACE_MODE_MII;
3810 } else if (val == bitval[P_RMII_SEL]) {
3811 interface = PHY_INTERFACE_MODE_RMII;
3812 } else {
3813 interface = PHY_INTERFACE_MODE_RGMII;
3814 if (data8 & P_RGMII_ID_EG_ENABLE)
3815 interface = PHY_INTERFACE_MODE_RGMII_TXID;
3816 if (data8 & P_RGMII_ID_IG_ENABLE) {
3817 interface = PHY_INTERFACE_MODE_RGMII_RXID;
3818 if (data8 & P_RGMII_ID_EG_ENABLE)
3819 interface = PHY_INTERFACE_MODE_RGMII_ID;
3820 }
3821 }
3822
3823 return interface;
3824 }
3825
ksz88x3_phylink_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)3826 static void ksz88x3_phylink_mac_config(struct phylink_config *config,
3827 unsigned int mode,
3828 const struct phylink_link_state *state)
3829 {
3830 struct dsa_port *dp = dsa_phylink_to_port(config);
3831 struct ksz_device *dev = dp->ds->priv;
3832
3833 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN);
3834 }
3835
ksz_phylink_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)3836 static void ksz_phylink_mac_config(struct phylink_config *config,
3837 unsigned int mode,
3838 const struct phylink_link_state *state)
3839 {
3840 struct dsa_port *dp = dsa_phylink_to_port(config);
3841 struct ksz_device *dev = dp->ds->priv;
3842 int port = dp->index;
3843
3844 /* Internal PHYs */
3845 if (dev->info->internal_phy[port])
3846 return;
3847
3848 /* No need to configure XMII control register when using SGMII. */
3849 if (ksz_is_sgmii_port(dev, port))
3850 return;
3851
3852 if (phylink_autoneg_inband(mode)) {
3853 dev_err(dev->dev, "In-band AN not supported!\n");
3854 return;
3855 }
3856
3857 ksz_set_xmii(dev, port, state->interface);
3858
3859 if (dev->dev_ops->setup_rgmii_delay)
3860 dev->dev_ops->setup_rgmii_delay(dev, port);
3861 }
3862
ksz_get_gbit(struct ksz_device * dev,int port)3863 bool ksz_get_gbit(struct ksz_device *dev, int port)
3864 {
3865 const u8 *bitval = dev->info->xmii_ctrl1;
3866 const u16 *regs = dev->info->regs;
3867 bool gbit = false;
3868 u8 data8;
3869 bool val;
3870
3871 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3872
3873 val = FIELD_GET(P_GMII_1GBIT_M, data8);
3874
3875 if (val == bitval[P_GMII_1GBIT])
3876 gbit = true;
3877
3878 return gbit;
3879 }
3880
ksz_set_gbit(struct ksz_device * dev,int port,bool gbit)3881 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
3882 {
3883 const u8 *bitval = dev->info->xmii_ctrl1;
3884 const u16 *regs = dev->info->regs;
3885 u8 data8;
3886
3887 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3888
3889 data8 &= ~P_GMII_1GBIT_M;
3890
3891 if (gbit)
3892 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
3893 else
3894 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
3895
3896 /* Write the updated value */
3897 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
3898 }
3899
ksz_set_100_10mbit(struct ksz_device * dev,int port,int speed)3900 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
3901 {
3902 const u8 *bitval = dev->info->xmii_ctrl0;
3903 const u16 *regs = dev->info->regs;
3904 u8 data8;
3905
3906 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
3907
3908 data8 &= ~P_MII_100MBIT_M;
3909
3910 if (speed == SPEED_100)
3911 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
3912 else
3913 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
3914
3915 /* Write the updated value */
3916 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
3917 }
3918
ksz_port_set_xmii_speed(struct ksz_device * dev,int port,int speed)3919 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
3920 {
3921 if (speed == SPEED_1000)
3922 ksz_set_gbit(dev, port, true);
3923 else
3924 ksz_set_gbit(dev, port, false);
3925
3926 if (speed == SPEED_100 || speed == SPEED_10)
3927 ksz_set_100_10mbit(dev, port, speed);
3928 }
3929
ksz_duplex_flowctrl(struct ksz_device * dev,int port,int duplex,bool tx_pause,bool rx_pause)3930 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
3931 bool tx_pause, bool rx_pause)
3932 {
3933 const u8 *bitval = dev->info->xmii_ctrl0;
3934 const u32 *masks = dev->info->masks;
3935 const u16 *regs = dev->info->regs;
3936 u8 mask;
3937 u8 val;
3938
3939 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
3940 masks[P_MII_RX_FLOW_CTRL];
3941
3942 if (duplex == DUPLEX_FULL)
3943 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
3944 else
3945 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
3946
3947 if (tx_pause)
3948 val |= masks[P_MII_TX_FLOW_CTRL];
3949
3950 if (rx_pause)
3951 val |= masks[P_MII_RX_FLOW_CTRL];
3952
3953 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val);
3954 }
3955
ksz9477_phylink_mac_link_up(struct phylink_config * config,struct phy_device * phydev,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)3956 static void ksz9477_phylink_mac_link_up(struct phylink_config *config,
3957 struct phy_device *phydev,
3958 unsigned int mode,
3959 phy_interface_t interface,
3960 int speed, int duplex, bool tx_pause,
3961 bool rx_pause)
3962 {
3963 struct dsa_port *dp = dsa_phylink_to_port(config);
3964 struct ksz_device *dev = dp->ds->priv;
3965 int port = dp->index;
3966 struct ksz_port *p;
3967
3968 p = &dev->ports[port];
3969
3970 /* Internal PHYs */
3971 if (dev->info->internal_phy[port])
3972 return;
3973
3974 p->phydev.speed = speed;
3975
3976 ksz_port_set_xmii_speed(dev, port, speed);
3977
3978 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
3979 }
3980
ksz_switch_detect(struct ksz_device * dev)3981 static int ksz_switch_detect(struct ksz_device *dev)
3982 {
3983 u8 id1, id2, id4;
3984 u16 id16;
3985 u32 id32;
3986 int ret;
3987
3988 /* read chip id */
3989 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
3990 if (ret)
3991 return ret;
3992
3993 id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
3994 id2 = FIELD_GET(SW_CHIP_ID_M, id16);
3995
3996 switch (id1) {
3997 case KSZ84_FAMILY_ID:
3998 dev->chip_id = KSZ8463_CHIP_ID;
3999 break;
4000 case KSZ87_FAMILY_ID:
4001 if (id2 == KSZ87_CHIP_ID_95) {
4002 u8 val;
4003
4004 dev->chip_id = KSZ8795_CHIP_ID;
4005
4006 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val);
4007 if (val & KSZ8_PORT_FIBER_MODE)
4008 dev->chip_id = KSZ8765_CHIP_ID;
4009 } else if (id2 == KSZ87_CHIP_ID_94) {
4010 dev->chip_id = KSZ8794_CHIP_ID;
4011 } else {
4012 return -ENODEV;
4013 }
4014 break;
4015 case KSZ88_FAMILY_ID:
4016 if (id2 == KSZ88_CHIP_ID_63)
4017 dev->chip_id = KSZ88X3_CHIP_ID;
4018 else
4019 return -ENODEV;
4020 break;
4021 case KSZ8895_FAMILY_ID:
4022 if (id2 == KSZ8895_CHIP_ID_95 ||
4023 id2 == KSZ8895_CHIP_ID_95R)
4024 dev->chip_id = KSZ8895_CHIP_ID;
4025 else
4026 return -ENODEV;
4027 ret = ksz_read8(dev, REG_KSZ8864_CHIP_ID, &id4);
4028 if (ret)
4029 return ret;
4030 if (id4 & SW_KSZ8864)
4031 dev->chip_id = KSZ8864_CHIP_ID;
4032 break;
4033 default:
4034 ret = ksz_read32(dev, REG_CHIP_ID0, &id32);
4035 if (ret)
4036 return ret;
4037
4038 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
4039 id32 &= ~0xFF;
4040
4041 switch (id32) {
4042 case KSZ9477_CHIP_ID:
4043 case KSZ9896_CHIP_ID:
4044 case KSZ9897_CHIP_ID:
4045 case KSZ9567_CHIP_ID:
4046 case KSZ8567_CHIP_ID:
4047 case LAN9370_CHIP_ID:
4048 case LAN9371_CHIP_ID:
4049 case LAN9372_CHIP_ID:
4050 case LAN9373_CHIP_ID:
4051 case LAN9374_CHIP_ID:
4052
4053 /* LAN9646 does not have its own chip id. */
4054 if (dev->chip_id != LAN9646_CHIP_ID)
4055 dev->chip_id = id32;
4056 break;
4057 case KSZ9893_CHIP_ID:
4058 ret = ksz_read8(dev, REG_CHIP_ID4,
4059 &id4);
4060 if (ret)
4061 return ret;
4062
4063 if (id4 == SKU_ID_KSZ8563)
4064 dev->chip_id = KSZ8563_CHIP_ID;
4065 else if (id4 == SKU_ID_KSZ9563)
4066 dev->chip_id = KSZ9563_CHIP_ID;
4067 else
4068 dev->chip_id = KSZ9893_CHIP_ID;
4069
4070 break;
4071 default:
4072 dev_err(dev->dev,
4073 "unsupported switch detected %x)\n", id32);
4074 return -ENODEV;
4075 }
4076 }
4077 return 0;
4078 }
4079
ksz_cls_flower_add(struct dsa_switch * ds,int port,struct flow_cls_offload * cls,bool ingress)4080 static int ksz_cls_flower_add(struct dsa_switch *ds, int port,
4081 struct flow_cls_offload *cls, bool ingress)
4082 {
4083 struct ksz_device *dev = ds->priv;
4084
4085 switch (dev->chip_id) {
4086 case KSZ8563_CHIP_ID:
4087 case KSZ8567_CHIP_ID:
4088 case KSZ9477_CHIP_ID:
4089 case KSZ9563_CHIP_ID:
4090 case KSZ9567_CHIP_ID:
4091 case KSZ9893_CHIP_ID:
4092 case KSZ9896_CHIP_ID:
4093 case KSZ9897_CHIP_ID:
4094 case LAN9646_CHIP_ID:
4095 return ksz9477_cls_flower_add(ds, port, cls, ingress);
4096 }
4097
4098 return -EOPNOTSUPP;
4099 }
4100
ksz_cls_flower_del(struct dsa_switch * ds,int port,struct flow_cls_offload * cls,bool ingress)4101 static int ksz_cls_flower_del(struct dsa_switch *ds, int port,
4102 struct flow_cls_offload *cls, bool ingress)
4103 {
4104 struct ksz_device *dev = ds->priv;
4105
4106 switch (dev->chip_id) {
4107 case KSZ8563_CHIP_ID:
4108 case KSZ8567_CHIP_ID:
4109 case KSZ9477_CHIP_ID:
4110 case KSZ9563_CHIP_ID:
4111 case KSZ9567_CHIP_ID:
4112 case KSZ9893_CHIP_ID:
4113 case KSZ9896_CHIP_ID:
4114 case KSZ9897_CHIP_ID:
4115 case LAN9646_CHIP_ID:
4116 return ksz9477_cls_flower_del(ds, port, cls, ingress);
4117 }
4118
4119 return -EOPNOTSUPP;
4120 }
4121
4122 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth
4123 * is converted to Hex-decimal using the successive multiplication method. On
4124 * every step, integer part is taken and decimal part is carry forwarded.
4125 */
cinc_cal(s32 idle_slope,s32 send_slope,u32 * bw)4126 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw)
4127 {
4128 u32 cinc = 0;
4129 u32 txrate;
4130 u32 rate;
4131 u8 temp;
4132 u8 i;
4133
4134 txrate = idle_slope - send_slope;
4135
4136 if (!txrate)
4137 return -EINVAL;
4138
4139 rate = idle_slope;
4140
4141 /* 24 bit register */
4142 for (i = 0; i < 6; i++) {
4143 rate = rate * 16;
4144
4145 temp = rate / txrate;
4146
4147 rate %= txrate;
4148
4149 cinc = ((cinc << 4) | temp);
4150 }
4151
4152 *bw = cinc;
4153
4154 return 0;
4155 }
4156
ksz_setup_tc_mode(struct ksz_device * dev,int port,u8 scheduler,u8 shaper)4157 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler,
4158 u8 shaper)
4159 {
4160 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0,
4161 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) |
4162 FIELD_PREP(MTI_SHAPING_M, shaper));
4163 }
4164
ksz_setup_tc_cbs(struct dsa_switch * ds,int port,struct tc_cbs_qopt_offload * qopt)4165 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port,
4166 struct tc_cbs_qopt_offload *qopt)
4167 {
4168 struct ksz_device *dev = ds->priv;
4169 int ret;
4170 u32 bw;
4171
4172 if (!dev->info->tc_cbs_supported)
4173 return -EOPNOTSUPP;
4174
4175 if (qopt->queue > dev->info->num_tx_queues)
4176 return -EINVAL;
4177
4178 /* Queue Selection */
4179 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue);
4180 if (ret)
4181 return ret;
4182
4183 if (!qopt->enable)
4184 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
4185 MTI_SHAPING_OFF);
4186
4187 /* High Credit */
4188 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK,
4189 qopt->hicredit);
4190 if (ret)
4191 return ret;
4192
4193 /* Low Credit */
4194 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK,
4195 qopt->locredit);
4196 if (ret)
4197 return ret;
4198
4199 /* Credit Increment Register */
4200 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw);
4201 if (ret)
4202 return ret;
4203
4204 if (dev->dev_ops->tc_cbs_set_cinc) {
4205 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw);
4206 if (ret)
4207 return ret;
4208 }
4209
4210 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
4211 MTI_SHAPING_SRP);
4212 }
4213
ksz_disable_egress_rate_limit(struct ksz_device * dev,int port)4214 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port)
4215 {
4216 int queue, ret;
4217
4218 /* Configuration will not take effect until the last Port Queue X
4219 * Egress Limit Control Register is written.
4220 */
4221 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
4222 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue,
4223 KSZ9477_OUT_RATE_NO_LIMIT);
4224 if (ret)
4225 return ret;
4226 }
4227
4228 return 0;
4229 }
4230
ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params * p,int band)4231 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p,
4232 int band)
4233 {
4234 /* Compared to queues, bands prioritize packets differently. In strict
4235 * priority mode, the lowest priority is assigned to Queue 0 while the
4236 * highest priority is given to Band 0.
4237 */
4238 return p->bands - 1 - band;
4239 }
4240
ksz8463_tc_ctrl(int port,int queue)4241 static u8 ksz8463_tc_ctrl(int port, int queue)
4242 {
4243 u8 reg;
4244
4245 reg = 0xC8 + port * 4;
4246 reg += ((3 - queue) / 2) * 2;
4247 reg++;
4248 reg -= (queue & 1);
4249 return reg;
4250 }
4251
4252 /**
4253 * ksz88x3_tc_ets_add - Configure ETS (Enhanced Transmission Selection)
4254 * for a port on KSZ88x3 switch
4255 * @dev: Pointer to the KSZ switch device structure
4256 * @port: Port number to configure
4257 * @p: Pointer to offload replace parameters describing ETS bands and mapping
4258 *
4259 * The KSZ88x3 supports two scheduling modes: Strict Priority and
4260 * Weighted Fair Queuing (WFQ). Both modes have fixed behavior:
4261 * - No configurable queue-to-priority mapping
4262 * - No weight adjustment in WFQ mode
4263 *
4264 * This function configures the switch to use strict priority mode by
4265 * clearing the WFQ enable bit for all queues associated with ETS bands.
4266 * If strict priority is not explicitly requested, the switch will default
4267 * to WFQ mode.
4268 *
4269 * Return: 0 on success, or a negative error code on failure
4270 */
ksz88x3_tc_ets_add(struct ksz_device * dev,int port,struct tc_ets_qopt_offload_replace_params * p)4271 static int ksz88x3_tc_ets_add(struct ksz_device *dev, int port,
4272 struct tc_ets_qopt_offload_replace_params *p)
4273 {
4274 int ret, band;
4275
4276 /* Only strict priority mode is supported for now.
4277 * WFQ is implicitly enabled when strict mode is disabled.
4278 */
4279 for (band = 0; band < p->bands; band++) {
4280 int queue = ksz_ets_band_to_queue(p, band);
4281 u8 reg;
4282
4283 /* Calculate TXQ Split Control register address for this
4284 * port/queue
4285 */
4286 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue);
4287 if (ksz_is_ksz8463(dev))
4288 reg = ksz8463_tc_ctrl(port, queue);
4289
4290 /* Clear WFQ enable bit to select strict priority scheduling */
4291 ret = ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE, 0);
4292 if (ret)
4293 return ret;
4294 }
4295
4296 return 0;
4297 }
4298
4299 /**
4300 * ksz88x3_tc_ets_del - Reset ETS (Enhanced Transmission Selection) config
4301 * for a port on KSZ88x3 switch
4302 * @dev: Pointer to the KSZ switch device structure
4303 * @port: Port number to reset
4304 *
4305 * The KSZ88x3 supports only fixed scheduling modes: Strict Priority or
4306 * Weighted Fair Queuing (WFQ), with no reconfiguration of weights or
4307 * queue mapping. This function resets the port’s scheduling mode to
4308 * the default, which is WFQ, by enabling the WFQ bit for all queues.
4309 *
4310 * Return: 0 on success, or a negative error code on failure
4311 */
ksz88x3_tc_ets_del(struct ksz_device * dev,int port)4312 static int ksz88x3_tc_ets_del(struct ksz_device *dev, int port)
4313 {
4314 int ret, queue;
4315
4316 /* Iterate over all transmit queues for this port */
4317 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
4318 u8 reg;
4319
4320 /* Calculate TXQ Split Control register address for this
4321 * port/queue
4322 */
4323 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue);
4324 if (ksz_is_ksz8463(dev))
4325 reg = ksz8463_tc_ctrl(port, queue);
4326
4327 /* Set WFQ enable bit to revert back to default scheduling
4328 * mode
4329 */
4330 ret = ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE,
4331 KSZ8873_TXQ_WFQ_ENABLE);
4332 if (ret)
4333 return ret;
4334 }
4335
4336 return 0;
4337 }
4338
ksz_queue_set_strict(struct ksz_device * dev,int port,int queue)4339 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue)
4340 {
4341 int ret;
4342
4343 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
4344 if (ret)
4345 return ret;
4346
4347 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
4348 MTI_SHAPING_OFF);
4349 }
4350
ksz_queue_set_wrr(struct ksz_device * dev,int port,int queue,int weight)4351 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue,
4352 int weight)
4353 {
4354 int ret;
4355
4356 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
4357 if (ret)
4358 return ret;
4359
4360 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
4361 MTI_SHAPING_OFF);
4362 if (ret)
4363 return ret;
4364
4365 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight);
4366 }
4367
ksz_tc_ets_add(struct ksz_device * dev,int port,struct tc_ets_qopt_offload_replace_params * p)4368 static int ksz_tc_ets_add(struct ksz_device *dev, int port,
4369 struct tc_ets_qopt_offload_replace_params *p)
4370 {
4371 int ret, band, tc_prio;
4372 u32 queue_map = 0;
4373
4374 /* In order to ensure proper prioritization, it is necessary to set the
4375 * rate limit for the related queue to zero. Otherwise strict priority
4376 * or WRR mode will not work. This is a hardware limitation.
4377 */
4378 ret = ksz_disable_egress_rate_limit(dev, port);
4379 if (ret)
4380 return ret;
4381
4382 /* Configure queue scheduling mode for all bands. Currently only strict
4383 * prio mode is supported.
4384 */
4385 for (band = 0; band < p->bands; band++) {
4386 int queue = ksz_ets_band_to_queue(p, band);
4387
4388 ret = ksz_queue_set_strict(dev, port, queue);
4389 if (ret)
4390 return ret;
4391 }
4392
4393 /* Configure the mapping between traffic classes and queues. Note:
4394 * priomap variable support 16 traffic classes, but the chip can handle
4395 * only 8 classes.
4396 */
4397 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) {
4398 int queue;
4399
4400 if (tc_prio >= dev->info->num_ipms)
4401 break;
4402
4403 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]);
4404 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
4405 }
4406
4407 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
4408 }
4409
ksz_tc_ets_del(struct ksz_device * dev,int port)4410 static int ksz_tc_ets_del(struct ksz_device *dev, int port)
4411 {
4412 int ret, queue;
4413
4414 /* To restore the default chip configuration, set all queues to use the
4415 * WRR scheduler with a weight of 1.
4416 */
4417 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
4418 ret = ksz_queue_set_wrr(dev, port, queue,
4419 KSZ9477_DEFAULT_WRR_WEIGHT);
4420
4421 if (ret)
4422 return ret;
4423 }
4424
4425 /* Revert the queue mapping for TC-priority to its default setting on
4426 * the chip.
4427 */
4428 return ksz9477_set_default_prio_queue_mapping(dev, port);
4429 }
4430
ksz_tc_ets_validate(struct ksz_device * dev,int port,struct tc_ets_qopt_offload_replace_params * p)4431 static int ksz_tc_ets_validate(struct ksz_device *dev, int port,
4432 struct tc_ets_qopt_offload_replace_params *p)
4433 {
4434 int band;
4435
4436 /* Since it is not feasible to share one port among multiple qdisc,
4437 * the user must configure all available queues appropriately.
4438 */
4439 if (p->bands != dev->info->num_tx_queues) {
4440 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n",
4441 dev->info->num_tx_queues);
4442 return -EOPNOTSUPP;
4443 }
4444
4445 for (band = 0; band < p->bands; ++band) {
4446 /* The KSZ switches utilize a weighted round robin configuration
4447 * where a certain number of packets can be transmitted from a
4448 * queue before the next queue is serviced. For more information
4449 * on this, refer to section 5.2.8.4 of the KSZ8565R
4450 * documentation on the Port Transmit Queue Control 1 Register.
4451 * However, the current ETS Qdisc implementation (as of February
4452 * 2023) assigns a weight to each queue based on the number of
4453 * bytes or extrapolated bandwidth in percentages. Since this
4454 * differs from the KSZ switches' method and we don't want to
4455 * fake support by converting bytes to packets, it is better to
4456 * return an error instead.
4457 */
4458 if (p->quanta[band]) {
4459 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n");
4460 return -EOPNOTSUPP;
4461 }
4462 }
4463
4464 return 0;
4465 }
4466
ksz_tc_setup_qdisc_ets(struct dsa_switch * ds,int port,struct tc_ets_qopt_offload * qopt)4467 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port,
4468 struct tc_ets_qopt_offload *qopt)
4469 {
4470 struct ksz_device *dev = ds->priv;
4471 int ret;
4472
4473 if (is_ksz8(dev) && !(ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)))
4474 return -EOPNOTSUPP;
4475
4476 if (qopt->parent != TC_H_ROOT) {
4477 dev_err(dev->dev, "Parent should be \"root\"\n");
4478 return -EOPNOTSUPP;
4479 }
4480
4481 switch (qopt->command) {
4482 case TC_ETS_REPLACE:
4483 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params);
4484 if (ret)
4485 return ret;
4486
4487 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev))
4488 return ksz88x3_tc_ets_add(dev, port,
4489 &qopt->replace_params);
4490 else
4491 return ksz_tc_ets_add(dev, port, &qopt->replace_params);
4492 case TC_ETS_DESTROY:
4493 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev))
4494 return ksz88x3_tc_ets_del(dev, port);
4495 else
4496 return ksz_tc_ets_del(dev, port);
4497 case TC_ETS_STATS:
4498 case TC_ETS_GRAFT:
4499 return -EOPNOTSUPP;
4500 }
4501
4502 return -EOPNOTSUPP;
4503 }
4504
ksz_setup_tc(struct dsa_switch * ds,int port,enum tc_setup_type type,void * type_data)4505 static int ksz_setup_tc(struct dsa_switch *ds, int port,
4506 enum tc_setup_type type, void *type_data)
4507 {
4508 switch (type) {
4509 case TC_SETUP_QDISC_CBS:
4510 return ksz_setup_tc_cbs(ds, port, type_data);
4511 case TC_SETUP_QDISC_ETS:
4512 return ksz_tc_setup_qdisc_ets(ds, port, type_data);
4513 default:
4514 return -EOPNOTSUPP;
4515 }
4516 }
4517
4518 /**
4519 * ksz_handle_wake_reason - Handle wake reason on a specified port.
4520 * @dev: The device structure.
4521 * @port: The port number.
4522 *
4523 * This function reads the PME (Power Management Event) status register of a
4524 * specified port to determine the wake reason. If there is no wake event, it
4525 * returns early. Otherwise, it logs the wake reason which could be due to a
4526 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register
4527 * is then cleared to acknowledge the handling of the wake event.
4528 *
4529 * Return: 0 on success, or an error code on failure.
4530 */
ksz_handle_wake_reason(struct ksz_device * dev,int port)4531 int ksz_handle_wake_reason(struct ksz_device *dev, int port)
4532 {
4533 const struct ksz_dev_ops *ops = dev->dev_ops;
4534 const u16 *regs = dev->info->regs;
4535 u8 pme_status;
4536 int ret;
4537
4538 ret = ops->pme_pread8(dev, port, regs[REG_PORT_PME_STATUS],
4539 &pme_status);
4540 if (ret)
4541 return ret;
4542
4543 if (!pme_status)
4544 return 0;
4545
4546 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port,
4547 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "",
4548 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "",
4549 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : "");
4550
4551 return ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_STATUS],
4552 pme_status);
4553 }
4554
4555 /**
4556 * ksz_get_wol - Get Wake-on-LAN settings for a specified port.
4557 * @ds: The dsa_switch structure.
4558 * @port: The port number.
4559 * @wol: Pointer to ethtool Wake-on-LAN settings structure.
4560 *
4561 * This function checks the device PME wakeup_source flag and chip_id.
4562 * If enabled and supported, it sets the supported and active WoL
4563 * flags.
4564 */
ksz_get_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)4565 static void ksz_get_wol(struct dsa_switch *ds, int port,
4566 struct ethtool_wolinfo *wol)
4567 {
4568 struct ksz_device *dev = ds->priv;
4569 const u16 *regs = dev->info->regs;
4570 u8 pme_ctrl;
4571 int ret;
4572
4573 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev))
4574 return;
4575
4576 if (!dev->wakeup_source)
4577 return;
4578
4579 wol->supported = WAKE_PHY;
4580
4581 /* Check if the current MAC address on this port can be set
4582 * as global for WAKE_MAGIC support. The result may vary
4583 * dynamically based on other ports configurations.
4584 */
4585 if (ksz_is_port_mac_global_usable(dev->ds, port))
4586 wol->supported |= WAKE_MAGIC;
4587
4588 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL],
4589 &pme_ctrl);
4590 if (ret)
4591 return;
4592
4593 if (pme_ctrl & PME_WOL_MAGICPKT)
4594 wol->wolopts |= WAKE_MAGIC;
4595 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY))
4596 wol->wolopts |= WAKE_PHY;
4597 }
4598
4599 /**
4600 * ksz_set_wol - Set Wake-on-LAN settings for a specified port.
4601 * @ds: The dsa_switch structure.
4602 * @port: The port number.
4603 * @wol: Pointer to ethtool Wake-on-LAN settings structure.
4604 *
4605 * This function configures Wake-on-LAN (WoL) settings for a specified
4606 * port. It validates the provided WoL options, checks if PME is
4607 * enabled and supported, clears any previous wake reasons, and sets
4608 * the Magic Packet flag in the port's PME control register if
4609 * specified.
4610 *
4611 * Return: 0 on success, or other error codes on failure.
4612 */
ksz_set_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)4613 static int ksz_set_wol(struct dsa_switch *ds, int port,
4614 struct ethtool_wolinfo *wol)
4615 {
4616 u8 pme_ctrl = 0, pme_ctrl_old = 0;
4617 struct ksz_device *dev = ds->priv;
4618 const u16 *regs = dev->info->regs;
4619 bool magic_switched_off;
4620 bool magic_switched_on;
4621 int ret;
4622
4623 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
4624 return -EINVAL;
4625
4626 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev))
4627 return -EOPNOTSUPP;
4628
4629 if (!dev->wakeup_source)
4630 return -EOPNOTSUPP;
4631
4632 ret = ksz_handle_wake_reason(dev, port);
4633 if (ret)
4634 return ret;
4635
4636 if (wol->wolopts & WAKE_MAGIC)
4637 pme_ctrl |= PME_WOL_MAGICPKT;
4638 if (wol->wolopts & WAKE_PHY)
4639 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY;
4640
4641 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL],
4642 &pme_ctrl_old);
4643 if (ret)
4644 return ret;
4645
4646 if (pme_ctrl_old == pme_ctrl)
4647 return 0;
4648
4649 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) &&
4650 !(pme_ctrl & PME_WOL_MAGICPKT);
4651 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) &&
4652 (pme_ctrl & PME_WOL_MAGICPKT);
4653
4654 /* To keep reference count of MAC address, we should do this
4655 * operation only on change of WOL settings.
4656 */
4657 if (magic_switched_on) {
4658 ret = ksz_switch_macaddr_get(dev->ds, port, NULL);
4659 if (ret)
4660 return ret;
4661 } else if (magic_switched_off) {
4662 ksz_switch_macaddr_put(dev->ds);
4663 }
4664
4665 ret = dev->dev_ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL],
4666 pme_ctrl);
4667 if (ret) {
4668 if (magic_switched_on)
4669 ksz_switch_macaddr_put(dev->ds);
4670 return ret;
4671 }
4672
4673 return 0;
4674 }
4675
4676 /**
4677 * ksz_wol_pre_shutdown - Prepares the switch device for shutdown while
4678 * considering Wake-on-LAN (WoL) settings.
4679 * @dev: The switch device structure.
4680 * @wol_enabled: Pointer to a boolean which will be set to true if WoL is
4681 * enabled on any port.
4682 *
4683 * This function prepares the switch device for a safe shutdown while taking
4684 * into account the Wake-on-LAN (WoL) settings on the user ports. It updates
4685 * the wol_enabled flag accordingly to reflect whether WoL is active on any
4686 * port.
4687 */
ksz_wol_pre_shutdown(struct ksz_device * dev,bool * wol_enabled)4688 static void ksz_wol_pre_shutdown(struct ksz_device *dev, bool *wol_enabled)
4689 {
4690 const struct ksz_dev_ops *ops = dev->dev_ops;
4691 const u16 *regs = dev->info->regs;
4692 u8 pme_pin_en = PME_ENABLE;
4693 struct dsa_port *dp;
4694 int ret;
4695
4696 *wol_enabled = false;
4697
4698 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev))
4699 return;
4700
4701 if (!dev->wakeup_source)
4702 return;
4703
4704 dsa_switch_for_each_user_port(dp, dev->ds) {
4705 u8 pme_ctrl = 0;
4706
4707 ret = ops->pme_pread8(dev, dp->index,
4708 regs[REG_PORT_PME_CTRL], &pme_ctrl);
4709 if (!ret && pme_ctrl)
4710 *wol_enabled = true;
4711
4712 /* make sure there are no pending wake events which would
4713 * prevent the device from going to sleep/shutdown.
4714 */
4715 ksz_handle_wake_reason(dev, dp->index);
4716 }
4717
4718 /* Now we are save to enable PME pin. */
4719 if (*wol_enabled) {
4720 if (dev->pme_active_high)
4721 pme_pin_en |= PME_POLARITY;
4722 ops->pme_write8(dev, regs[REG_SW_PME_CTRL], pme_pin_en);
4723 if (ksz_is_ksz87xx(dev))
4724 ksz_write8(dev, KSZ87XX_REG_INT_EN, KSZ87XX_INT_PME_MASK);
4725 }
4726 }
4727
ksz_port_set_mac_address(struct dsa_switch * ds,int port,const unsigned char * addr)4728 static int ksz_port_set_mac_address(struct dsa_switch *ds, int port,
4729 const unsigned char *addr)
4730 {
4731 struct dsa_port *dp = dsa_to_port(ds, port);
4732 struct ethtool_wolinfo wol;
4733
4734 if (dp->hsr_dev) {
4735 dev_err(ds->dev,
4736 "Cannot change MAC address on port %d with active HSR offload\n",
4737 port);
4738 return -EBUSY;
4739 }
4740
4741 /* Need to initialize variable as the code to fill in settings may
4742 * not be executed.
4743 */
4744 wol.wolopts = 0;
4745
4746 ksz_get_wol(ds, dp->index, &wol);
4747 if (wol.wolopts & WAKE_MAGIC) {
4748 dev_err(ds->dev,
4749 "Cannot change MAC address on port %d with active Wake on Magic Packet\n",
4750 port);
4751 return -EBUSY;
4752 }
4753
4754 return 0;
4755 }
4756
4757 /**
4758 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port
4759 * can be used as a global address.
4760 * @ds: Pointer to the DSA switch structure.
4761 * @port: The port number on which the MAC address is to be checked.
4762 *
4763 * This function examines the MAC address set on the specified port and
4764 * determines if it can be used as a global address for the switch.
4765 *
4766 * Return: true if the port's MAC address can be used as a global address, false
4767 * otherwise.
4768 */
ksz_is_port_mac_global_usable(struct dsa_switch * ds,int port)4769 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port)
4770 {
4771 struct net_device *user = dsa_to_port(ds, port)->user;
4772 const unsigned char *addr = user->dev_addr;
4773 struct ksz_switch_macaddr *switch_macaddr;
4774 struct ksz_device *dev = ds->priv;
4775
4776 ASSERT_RTNL();
4777
4778 switch_macaddr = dev->switch_macaddr;
4779 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr))
4780 return false;
4781
4782 return true;
4783 }
4784
4785 /**
4786 * ksz_switch_macaddr_get - Program the switch's MAC address register.
4787 * @ds: DSA switch instance.
4788 * @port: Port number.
4789 * @extack: Netlink extended acknowledgment.
4790 *
4791 * This function programs the switch's MAC address register with the MAC address
4792 * of the requesting user port. This single address is used by the switch for
4793 * multiple features like HSR self-address filtering and WoL. Other user ports
4794 * can share ownership of this address as long as their MAC address is the same.
4795 * The MAC addresses of user ports must not change while they have ownership of
4796 * the switch MAC address.
4797 *
4798 * Return: 0 on success, or other error codes on failure.
4799 */
ksz_switch_macaddr_get(struct dsa_switch * ds,int port,struct netlink_ext_ack * extack)4800 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port,
4801 struct netlink_ext_ack *extack)
4802 {
4803 struct net_device *user = dsa_to_port(ds, port)->user;
4804 const unsigned char *addr = user->dev_addr;
4805 struct ksz_switch_macaddr *switch_macaddr;
4806 struct ksz_device *dev = ds->priv;
4807 const u16 *regs = dev->info->regs;
4808 int i, ret;
4809
4810 /* Make sure concurrent MAC address changes are blocked */
4811 ASSERT_RTNL();
4812
4813 switch_macaddr = dev->switch_macaddr;
4814 if (switch_macaddr) {
4815 if (!ether_addr_equal(switch_macaddr->addr, addr)) {
4816 NL_SET_ERR_MSG_FMT_MOD(extack,
4817 "Switch already configured for MAC address %pM",
4818 switch_macaddr->addr);
4819 return -EBUSY;
4820 }
4821
4822 refcount_inc(&switch_macaddr->refcount);
4823 return 0;
4824 }
4825
4826 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL);
4827 if (!switch_macaddr)
4828 return -ENOMEM;
4829
4830 ether_addr_copy(switch_macaddr->addr, addr);
4831 refcount_set(&switch_macaddr->refcount, 1);
4832 dev->switch_macaddr = switch_macaddr;
4833
4834 /* Program the switch MAC address to hardware */
4835 for (i = 0; i < ETH_ALEN; i++) {
4836 if (ksz_is_ksz8463(dev)) {
4837 u16 addr16 = ((u16)addr[i] << 8) | addr[i + 1];
4838
4839 ret = ksz_write16(dev, regs[REG_SW_MAC_ADDR] + i,
4840 addr16);
4841 i++;
4842 } else {
4843 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i,
4844 addr[i]);
4845 }
4846 if (ret)
4847 goto macaddr_drop;
4848 }
4849
4850 return 0;
4851
4852 macaddr_drop:
4853 dev->switch_macaddr = NULL;
4854 refcount_set(&switch_macaddr->refcount, 0);
4855 kfree(switch_macaddr);
4856
4857 return ret;
4858 }
4859
ksz_switch_macaddr_put(struct dsa_switch * ds)4860 void ksz_switch_macaddr_put(struct dsa_switch *ds)
4861 {
4862 struct ksz_switch_macaddr *switch_macaddr;
4863 struct ksz_device *dev = ds->priv;
4864 const u16 *regs = dev->info->regs;
4865 int i;
4866
4867 /* Make sure concurrent MAC address changes are blocked */
4868 ASSERT_RTNL();
4869
4870 switch_macaddr = dev->switch_macaddr;
4871 if (!refcount_dec_and_test(&switch_macaddr->refcount))
4872 return;
4873
4874 for (i = 0; i < ETH_ALEN; i++)
4875 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0);
4876
4877 dev->switch_macaddr = NULL;
4878 kfree(switch_macaddr);
4879 }
4880
ksz_hsr_join(struct dsa_switch * ds,int port,struct net_device * hsr,struct netlink_ext_ack * extack)4881 static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr,
4882 struct netlink_ext_ack *extack)
4883 {
4884 struct ksz_device *dev = ds->priv;
4885 enum hsr_version ver;
4886 int ret;
4887
4888 ret = hsr_get_version(hsr, &ver);
4889 if (ret)
4890 return ret;
4891
4892 if (dev->chip_id != KSZ9477_CHIP_ID) {
4893 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload");
4894 return -EOPNOTSUPP;
4895 }
4896
4897 /* KSZ9477 can support HW offloading of only 1 HSR device */
4898 if (dev->hsr_dev && hsr != dev->hsr_dev) {
4899 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR");
4900 return -EOPNOTSUPP;
4901 }
4902
4903 /* KSZ9477 only supports HSR v0 and v1 */
4904 if (!(ver == HSR_V0 || ver == HSR_V1)) {
4905 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported");
4906 return -EOPNOTSUPP;
4907 }
4908
4909 /* KSZ9477 can only perform HSR offloading for up to two ports */
4910 if (hweight8(dev->hsr_ports) >= 2) {
4911 NL_SET_ERR_MSG_MOD(extack,
4912 "Cannot offload more than two ports - using software HSR");
4913 return -EOPNOTSUPP;
4914 }
4915
4916 /* Self MAC address filtering, to avoid frames traversing
4917 * the HSR ring more than once.
4918 */
4919 ret = ksz_switch_macaddr_get(ds, port, extack);
4920 if (ret)
4921 return ret;
4922
4923 ksz9477_hsr_join(ds, port, hsr);
4924 dev->hsr_dev = hsr;
4925 dev->hsr_ports |= BIT(port);
4926
4927 return 0;
4928 }
4929
ksz_hsr_leave(struct dsa_switch * ds,int port,struct net_device * hsr)4930 static int ksz_hsr_leave(struct dsa_switch *ds, int port,
4931 struct net_device *hsr)
4932 {
4933 struct ksz_device *dev = ds->priv;
4934
4935 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID);
4936
4937 ksz9477_hsr_leave(ds, port, hsr);
4938 dev->hsr_ports &= ~BIT(port);
4939 if (!dev->hsr_ports)
4940 dev->hsr_dev = NULL;
4941
4942 ksz_switch_macaddr_put(ds);
4943
4944 return 0;
4945 }
4946
ksz_suspend(struct dsa_switch * ds)4947 static int ksz_suspend(struct dsa_switch *ds)
4948 {
4949 struct ksz_device *dev = ds->priv;
4950
4951 cancel_delayed_work_sync(&dev->mib_read);
4952 return 0;
4953 }
4954
ksz_resume(struct dsa_switch * ds)4955 static int ksz_resume(struct dsa_switch *ds)
4956 {
4957 struct ksz_device *dev = ds->priv;
4958
4959 if (dev->mib_read_interval)
4960 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
4961 return 0;
4962 }
4963
4964 static const struct dsa_switch_ops ksz_switch_ops = {
4965 .get_tag_protocol = ksz_get_tag_protocol,
4966 .connect_tag_protocol = ksz_connect_tag_protocol,
4967 .get_phy_flags = ksz_get_phy_flags,
4968 .setup = ksz_setup,
4969 .teardown = ksz_teardown,
4970 .phy_read = ksz_phy_read16,
4971 .phy_write = ksz_phy_write16,
4972 .phylink_get_caps = ksz_phylink_get_caps,
4973 .port_setup = ksz_port_setup,
4974 .set_ageing_time = ksz_set_ageing_time,
4975 .get_strings = ksz_get_strings,
4976 .get_ethtool_stats = ksz_get_ethtool_stats,
4977 .get_sset_count = ksz_sset_count,
4978 .port_bridge_join = ksz_port_bridge_join,
4979 .port_bridge_leave = ksz_port_bridge_leave,
4980 .port_hsr_join = ksz_hsr_join,
4981 .port_hsr_leave = ksz_hsr_leave,
4982 .port_set_mac_address = ksz_port_set_mac_address,
4983 .port_stp_state_set = ksz_port_stp_state_set,
4984 .port_teardown = ksz_port_teardown,
4985 .port_pre_bridge_flags = ksz_port_pre_bridge_flags,
4986 .port_bridge_flags = ksz_port_bridge_flags,
4987 .port_fast_age = ksz_port_fast_age,
4988 .port_vlan_filtering = ksz_port_vlan_filtering,
4989 .port_vlan_add = ksz_port_vlan_add,
4990 .port_vlan_del = ksz_port_vlan_del,
4991 .port_fdb_dump = ksz_port_fdb_dump,
4992 .port_fdb_add = ksz_port_fdb_add,
4993 .port_fdb_del = ksz_port_fdb_del,
4994 .port_mdb_add = ksz_port_mdb_add,
4995 .port_mdb_del = ksz_port_mdb_del,
4996 .port_mirror_add = ksz_port_mirror_add,
4997 .port_mirror_del = ksz_port_mirror_del,
4998 .get_stats64 = ksz_get_stats64,
4999 .get_pause_stats = ksz_get_pause_stats,
5000 .port_change_mtu = ksz_change_mtu,
5001 .port_max_mtu = ksz_max_mtu,
5002 .get_wol = ksz_get_wol,
5003 .set_wol = ksz_set_wol,
5004 .suspend = ksz_suspend,
5005 .resume = ksz_resume,
5006 .get_ts_info = ksz_get_ts_info,
5007 .port_hwtstamp_get = ksz_hwtstamp_get,
5008 .port_hwtstamp_set = ksz_hwtstamp_set,
5009 .port_txtstamp = ksz_port_txtstamp,
5010 .port_rxtstamp = ksz_port_rxtstamp,
5011 .cls_flower_add = ksz_cls_flower_add,
5012 .cls_flower_del = ksz_cls_flower_del,
5013 .port_setup_tc = ksz_setup_tc,
5014 .support_eee = ksz_support_eee,
5015 .set_mac_eee = ksz_set_mac_eee,
5016 .port_get_default_prio = ksz_port_get_default_prio,
5017 .port_set_default_prio = ksz_port_set_default_prio,
5018 .port_get_dscp_prio = ksz_port_get_dscp_prio,
5019 .port_add_dscp_prio = ksz_port_add_dscp_prio,
5020 .port_del_dscp_prio = ksz_port_del_dscp_prio,
5021 .port_get_apptrust = ksz_port_get_apptrust,
5022 .port_set_apptrust = ksz_port_set_apptrust,
5023 };
5024
ksz_switch_alloc(struct device * base,void * priv)5025 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
5026 {
5027 struct dsa_switch *ds;
5028 struct ksz_device *swdev;
5029
5030 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
5031 if (!ds)
5032 return NULL;
5033
5034 ds->dev = base;
5035 ds->num_ports = DSA_MAX_PORTS;
5036 ds->ops = &ksz_switch_ops;
5037
5038 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
5039 if (!swdev)
5040 return NULL;
5041
5042 ds->priv = swdev;
5043 swdev->dev = base;
5044
5045 swdev->ds = ds;
5046 swdev->priv = priv;
5047
5048 return swdev;
5049 }
5050 EXPORT_SYMBOL(ksz_switch_alloc);
5051
5052 /**
5053 * ksz_switch_shutdown - Shutdown routine for the switch device.
5054 * @dev: The switch device structure.
5055 *
5056 * This function is responsible for initiating a shutdown sequence for the
5057 * switch device. It invokes the reset operation defined in the device
5058 * operations, if available, to reset the switch. Subsequently, it calls the
5059 * DSA framework's shutdown function to ensure a proper shutdown of the DSA
5060 * switch.
5061 */
ksz_switch_shutdown(struct ksz_device * dev)5062 void ksz_switch_shutdown(struct ksz_device *dev)
5063 {
5064 bool wol_enabled = false;
5065
5066 ksz_wol_pre_shutdown(dev, &wol_enabled);
5067
5068 if (dev->dev_ops->reset && !wol_enabled)
5069 dev->dev_ops->reset(dev);
5070
5071 dsa_switch_shutdown(dev->ds);
5072 }
5073 EXPORT_SYMBOL(ksz_switch_shutdown);
5074
ksz_parse_rgmii_delay(struct ksz_device * dev,int port_num,struct device_node * port_dn)5075 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
5076 struct device_node *port_dn)
5077 {
5078 phy_interface_t phy_mode = dev->ports[port_num].interface;
5079 int rx_delay = -1, tx_delay = -1;
5080
5081 if (!phy_interface_mode_is_rgmii(phy_mode))
5082 return;
5083
5084 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
5085 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
5086
5087 if (rx_delay == -1 && tx_delay == -1) {
5088 dev_warn(dev->dev,
5089 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
5090 "please update device tree to specify \"rx-internal-delay-ps\" and "
5091 "\"tx-internal-delay-ps\"",
5092 port_num);
5093
5094 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
5095 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
5096 rx_delay = 2000;
5097
5098 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
5099 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
5100 tx_delay = 2000;
5101 }
5102
5103 if (rx_delay < 0)
5104 rx_delay = 0;
5105 if (tx_delay < 0)
5106 tx_delay = 0;
5107
5108 dev->ports[port_num].rgmii_rx_val = rx_delay;
5109 dev->ports[port_num].rgmii_tx_val = tx_delay;
5110 }
5111
5112 /**
5113 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding
5114 * register value.
5115 * @array: The array of drive strength values to search.
5116 * @array_size: The size of the array.
5117 * @microamp: The drive strength value in microamp to be converted.
5118 *
5119 * This function searches the array of drive strength values for the given
5120 * microamp value and returns the corresponding register value for that drive.
5121 *
5122 * Returns: If found, the corresponding register value for that drive strength
5123 * is returned. Otherwise, -EINVAL is returned indicating an invalid value.
5124 */
ksz_drive_strength_to_reg(const struct ksz_drive_strength * array,size_t array_size,int microamp)5125 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array,
5126 size_t array_size, int microamp)
5127 {
5128 int i;
5129
5130 for (i = 0; i < array_size; i++) {
5131 if (array[i].microamp == microamp)
5132 return array[i].reg_val;
5133 }
5134
5135 return -EINVAL;
5136 }
5137
5138 /**
5139 * ksz_drive_strength_error() - Report invalid drive strength value
5140 * @dev: ksz device
5141 * @array: The array of drive strength values to search.
5142 * @array_size: The size of the array.
5143 * @microamp: Invalid drive strength value in microamp
5144 *
5145 * This function logs an error message when an unsupported drive strength value
5146 * is detected. It lists out all the supported drive strength values for
5147 * reference in the error message.
5148 */
ksz_drive_strength_error(struct ksz_device * dev,const struct ksz_drive_strength * array,size_t array_size,int microamp)5149 static void ksz_drive_strength_error(struct ksz_device *dev,
5150 const struct ksz_drive_strength *array,
5151 size_t array_size, int microamp)
5152 {
5153 char supported_values[100];
5154 size_t remaining_size;
5155 int added_len;
5156 char *ptr;
5157 int i;
5158
5159 remaining_size = sizeof(supported_values);
5160 ptr = supported_values;
5161
5162 for (i = 0; i < array_size; i++) {
5163 added_len = snprintf(ptr, remaining_size,
5164 i == 0 ? "%d" : ", %d", array[i].microamp);
5165
5166 if (added_len >= remaining_size)
5167 break;
5168
5169 ptr += added_len;
5170 remaining_size -= added_len;
5171 }
5172
5173 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n",
5174 microamp, supported_values);
5175 }
5176
5177 /**
5178 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477
5179 * chip variants.
5180 * @dev: ksz device
5181 * @props: Array of drive strength properties to be applied
5182 * @num_props: Number of properties in the array
5183 *
5184 * This function configures the drive strength for various KSZ9477 chip variants
5185 * based on the provided properties. It handles chip-specific nuances and
5186 * ensures only valid drive strengths are written to the respective chip.
5187 *
5188 * Return: 0 on successful configuration, a negative error code on failure.
5189 */
ksz9477_drive_strength_write(struct ksz_device * dev,struct ksz_driver_strength_prop * props,int num_props)5190 static int ksz9477_drive_strength_write(struct ksz_device *dev,
5191 struct ksz_driver_strength_prop *props,
5192 int num_props)
5193 {
5194 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths);
5195 int i, ret, reg;
5196 u8 mask = 0;
5197 u8 val = 0;
5198
5199 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1)
5200 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
5201 props[KSZ_DRIVER_STRENGTH_IO].name);
5202
5203 if (dev->chip_id == KSZ8795_CHIP_ID ||
5204 dev->chip_id == KSZ8794_CHIP_ID ||
5205 dev->chip_id == KSZ8765_CHIP_ID)
5206 reg = KSZ8795_REG_SW_CTRL_20;
5207 else
5208 reg = KSZ9477_REG_SW_IO_STRENGTH;
5209
5210 for (i = 0; i < num_props; i++) {
5211 if (props[i].value == -1)
5212 continue;
5213
5214 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths,
5215 array_size, props[i].value);
5216 if (ret < 0) {
5217 ksz_drive_strength_error(dev, ksz9477_drive_strengths,
5218 array_size, props[i].value);
5219 return ret;
5220 }
5221
5222 mask |= SW_DRIVE_STRENGTH_M << props[i].offset;
5223 val |= ret << props[i].offset;
5224 }
5225
5226 return ksz_rmw8(dev, reg, mask, val);
5227 }
5228
5229 /**
5230 * ksz88x3_drive_strength_write() - Set the drive strength configuration for
5231 * KSZ8863 compatible chip variants.
5232 * @dev: ksz device
5233 * @props: Array of drive strength properties to be set
5234 * @num_props: Number of properties in the array
5235 *
5236 * This function applies the specified drive strength settings to KSZ88X3 chip
5237 * variants (KSZ8873, KSZ8863).
5238 * It ensures the configurations align with what the chip variant supports and
5239 * warns or errors out on unsupported settings.
5240 *
5241 * Return: 0 on success, error code otherwise
5242 */
ksz88x3_drive_strength_write(struct ksz_device * dev,struct ksz_driver_strength_prop * props,int num_props)5243 static int ksz88x3_drive_strength_write(struct ksz_device *dev,
5244 struct ksz_driver_strength_prop *props,
5245 int num_props)
5246 {
5247 size_t array_size = ARRAY_SIZE(ksz88x3_drive_strengths);
5248 int microamp;
5249 int i, ret;
5250
5251 for (i = 0; i < num_props; i++) {
5252 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO)
5253 continue;
5254
5255 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
5256 props[i].name);
5257 }
5258
5259 microamp = props[KSZ_DRIVER_STRENGTH_IO].value;
5260 ret = ksz_drive_strength_to_reg(ksz88x3_drive_strengths, array_size,
5261 microamp);
5262 if (ret < 0) {
5263 ksz_drive_strength_error(dev, ksz88x3_drive_strengths,
5264 array_size, microamp);
5265 return ret;
5266 }
5267
5268 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12,
5269 KSZ8873_DRIVE_STRENGTH_16MA, ret);
5270 }
5271
5272 /**
5273 * ksz_parse_drive_strength() - Extract and apply drive strength configurations
5274 * from device tree properties.
5275 * @dev: ksz device
5276 *
5277 * This function reads the specified drive strength properties from the
5278 * device tree, validates against the supported chip variants, and sets
5279 * them accordingly. An error should be critical here, as the drive strength
5280 * settings are crucial for EMI compliance.
5281 *
5282 * Return: 0 on success, error code otherwise
5283 */
ksz_parse_drive_strength(struct ksz_device * dev)5284 static int ksz_parse_drive_strength(struct ksz_device *dev)
5285 {
5286 struct ksz_driver_strength_prop of_props[] = {
5287 [KSZ_DRIVER_STRENGTH_HI] = {
5288 .name = "microchip,hi-drive-strength-microamp",
5289 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S,
5290 .value = -1,
5291 },
5292 [KSZ_DRIVER_STRENGTH_LO] = {
5293 .name = "microchip,lo-drive-strength-microamp",
5294 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S,
5295 .value = -1,
5296 },
5297 [KSZ_DRIVER_STRENGTH_IO] = {
5298 .name = "microchip,io-drive-strength-microamp",
5299 .offset = 0, /* don't care */
5300 .value = -1,
5301 },
5302 };
5303 struct device_node *np = dev->dev->of_node;
5304 bool have_any_prop = false;
5305 int i, ret;
5306
5307 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
5308 ret = of_property_read_u32(np, of_props[i].name,
5309 &of_props[i].value);
5310 if (ret && ret != -EINVAL)
5311 dev_warn(dev->dev, "Failed to read %s\n",
5312 of_props[i].name);
5313 if (ret)
5314 continue;
5315
5316 have_any_prop = true;
5317 }
5318
5319 if (!have_any_prop)
5320 return 0;
5321
5322 switch (dev->chip_id) {
5323 case KSZ88X3_CHIP_ID:
5324 return ksz88x3_drive_strength_write(dev, of_props,
5325 ARRAY_SIZE(of_props));
5326 case KSZ8795_CHIP_ID:
5327 case KSZ8794_CHIP_ID:
5328 case KSZ8765_CHIP_ID:
5329 case KSZ8563_CHIP_ID:
5330 case KSZ8567_CHIP_ID:
5331 case KSZ9477_CHIP_ID:
5332 case KSZ9563_CHIP_ID:
5333 case KSZ9567_CHIP_ID:
5334 case KSZ9893_CHIP_ID:
5335 case KSZ9896_CHIP_ID:
5336 case KSZ9897_CHIP_ID:
5337 case LAN9646_CHIP_ID:
5338 return ksz9477_drive_strength_write(dev, of_props,
5339 ARRAY_SIZE(of_props));
5340 default:
5341 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
5342 if (of_props[i].value == -1)
5343 continue;
5344
5345 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
5346 of_props[i].name);
5347 }
5348 }
5349
5350 return 0;
5351 }
5352
ksz8463_configure_straps_spi(struct ksz_device * dev)5353 static int ksz8463_configure_straps_spi(struct ksz_device *dev)
5354 {
5355 struct pinctrl *pinctrl;
5356 struct gpio_desc *rxd0;
5357 struct gpio_desc *rxd1;
5358
5359 rxd0 = devm_gpiod_get_index_optional(dev->dev, "straps-rxd", 0, GPIOD_OUT_LOW);
5360 if (IS_ERR(rxd0))
5361 return PTR_ERR(rxd0);
5362
5363 rxd1 = devm_gpiod_get_index_optional(dev->dev, "straps-rxd", 1, GPIOD_OUT_HIGH);
5364 if (IS_ERR(rxd1))
5365 return PTR_ERR(rxd1);
5366
5367 if (!rxd0 && !rxd1)
5368 return 0;
5369
5370 if ((rxd0 && !rxd1) || (rxd1 && !rxd0))
5371 return -EINVAL;
5372
5373 pinctrl = devm_pinctrl_get_select(dev->dev, "reset");
5374 if (IS_ERR(pinctrl))
5375 return PTR_ERR(pinctrl);
5376
5377 return 0;
5378 }
5379
ksz8463_release_straps_spi(struct ksz_device * dev)5380 static int ksz8463_release_straps_spi(struct ksz_device *dev)
5381 {
5382 return pinctrl_select_default_state(dev->dev);
5383 }
5384
ksz_switch_register(struct ksz_device * dev)5385 int ksz_switch_register(struct ksz_device *dev)
5386 {
5387 const struct ksz_chip_data *info;
5388 struct device_node *ports;
5389 phy_interface_t interface;
5390 unsigned int port_num;
5391 int ret;
5392 int i;
5393
5394 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset",
5395 GPIOD_OUT_LOW);
5396 if (IS_ERR(dev->reset_gpio))
5397 return PTR_ERR(dev->reset_gpio);
5398
5399 if (dev->reset_gpio) {
5400 if (of_device_is_compatible(dev->dev->of_node, "microchip,ksz8463")) {
5401 ret = ksz8463_configure_straps_spi(dev);
5402 if (ret)
5403 return ret;
5404 }
5405
5406 gpiod_set_value_cansleep(dev->reset_gpio, 1);
5407 usleep_range(10000, 12000);
5408 gpiod_set_value_cansleep(dev->reset_gpio, 0);
5409 msleep(100);
5410
5411 if (of_device_is_compatible(dev->dev->of_node, "microchip,ksz8463")) {
5412 ret = ksz8463_release_straps_spi(dev);
5413 if (ret)
5414 return ret;
5415 }
5416 }
5417
5418 mutex_init(&dev->dev_mutex);
5419 mutex_init(&dev->regmap_mutex);
5420 mutex_init(&dev->alu_mutex);
5421 mutex_init(&dev->vlan_mutex);
5422
5423 ret = ksz_switch_detect(dev);
5424 if (ret)
5425 return ret;
5426
5427 info = ksz_lookup_info(dev->chip_id);
5428 if (!info)
5429 return -ENODEV;
5430
5431 /* Update the compatible info with the probed one */
5432 dev->info = info;
5433
5434 dev_info(dev->dev, "found switch: %s, rev %i\n",
5435 dev->info->dev_name, dev->chip_rev);
5436
5437 ret = ksz_check_device_id(dev);
5438 if (ret)
5439 return ret;
5440
5441 dev->dev_ops = dev->info->ops;
5442
5443 ret = dev->dev_ops->init(dev);
5444 if (ret)
5445 return ret;
5446
5447 dev->ports = devm_kzalloc(dev->dev,
5448 dev->info->port_cnt * sizeof(struct ksz_port),
5449 GFP_KERNEL);
5450 if (!dev->ports)
5451 return -ENOMEM;
5452
5453 for (i = 0; i < dev->info->port_cnt; i++) {
5454 spin_lock_init(&dev->ports[i].mib.stats64_lock);
5455 mutex_init(&dev->ports[i].mib.cnt_mutex);
5456 dev->ports[i].mib.counters =
5457 devm_kzalloc(dev->dev,
5458 sizeof(u64) * (dev->info->mib_cnt + 1),
5459 GFP_KERNEL);
5460 if (!dev->ports[i].mib.counters)
5461 return -ENOMEM;
5462
5463 dev->ports[i].ksz_dev = dev;
5464 dev->ports[i].num = i;
5465 }
5466
5467 /* set the real number of ports */
5468 dev->ds->num_ports = dev->info->port_cnt;
5469
5470 /* set the phylink ops */
5471 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops;
5472
5473 /* Host port interface will be self detected, or specifically set in
5474 * device tree.
5475 */
5476 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
5477 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
5478 if (dev->dev->of_node) {
5479 ret = of_get_phy_mode(dev->dev->of_node, &interface);
5480 if (ret == 0)
5481 dev->compat_interface = interface;
5482 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports");
5483 if (!ports)
5484 ports = of_get_child_by_name(dev->dev->of_node, "ports");
5485 if (ports) {
5486 for_each_available_child_of_node_scoped(ports, port) {
5487 if (of_property_read_u32(port, "reg",
5488 &port_num))
5489 continue;
5490 if (!(dev->port_mask & BIT(port_num))) {
5491 of_node_put(ports);
5492 return -EINVAL;
5493 }
5494 of_get_phy_mode(port,
5495 &dev->ports[port_num].interface);
5496
5497 ksz_parse_rgmii_delay(dev, port_num, port);
5498 dev->ports[port_num].fiber =
5499 of_property_read_bool(port,
5500 "micrel,fiber-mode");
5501 }
5502 of_node_put(ports);
5503 }
5504 dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
5505 "microchip,synclko-125");
5506 dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
5507 "microchip,synclko-disable");
5508 if (dev->synclko_125 && dev->synclko_disable) {
5509 dev_err(dev->dev, "inconsistent synclko settings\n");
5510 return -EINVAL;
5511 }
5512
5513 dev->wakeup_source = of_property_read_bool(dev->dev->of_node,
5514 "wakeup-source");
5515 dev->pme_active_high = of_property_read_bool(dev->dev->of_node,
5516 "microchip,pme-active-high");
5517 }
5518
5519 ret = dsa_register_switch(dev->ds);
5520 if (ret) {
5521 dev->dev_ops->exit(dev);
5522 return ret;
5523 }
5524
5525 /* Read MIB counters every 30 seconds to avoid overflow. */
5526 dev->mib_read_interval = msecs_to_jiffies(5000);
5527
5528 /* Start the MIB timer. */
5529 schedule_delayed_work(&dev->mib_read, 0);
5530
5531 return ret;
5532 }
5533 EXPORT_SYMBOL(ksz_switch_register);
5534
ksz_switch_remove(struct ksz_device * dev)5535 void ksz_switch_remove(struct ksz_device *dev)
5536 {
5537 /* timer started */
5538 if (dev->mib_read_interval) {
5539 dev->mib_read_interval = 0;
5540 cancel_delayed_work_sync(&dev->mib_read);
5541 }
5542
5543 dev->dev_ops->exit(dev);
5544 dsa_unregister_switch(dev->ds);
5545
5546 if (dev->reset_gpio)
5547 gpiod_set_value_cansleep(dev->reset_gpio, 1);
5548
5549 }
5550 EXPORT_SYMBOL(ksz_switch_remove);
5551
5552 #ifdef CONFIG_PM_SLEEP
ksz_switch_suspend(struct device * dev)5553 int ksz_switch_suspend(struct device *dev)
5554 {
5555 struct ksz_device *priv = dev_get_drvdata(dev);
5556
5557 return dsa_switch_suspend(priv->ds);
5558 }
5559 EXPORT_SYMBOL(ksz_switch_suspend);
5560
ksz_switch_resume(struct device * dev)5561 int ksz_switch_resume(struct device *dev)
5562 {
5563 struct ksz_device *priv = dev_get_drvdata(dev);
5564
5565 return dsa_switch_resume(priv->ds);
5566 }
5567 EXPORT_SYMBOL(ksz_switch_resume);
5568 #endif
5569
5570 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
5571 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
5572 MODULE_LICENSE("GPL");
5573