1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Microchip switch driver common header
3 *
4 * Copyright (C) 2017-2025 Microchip Technology Inc.
5 */
6
7 #ifndef __KSZ_COMMON_H
8 #define __KSZ_COMMON_H
9
10 #include <linux/etherdevice.h>
11 #include <linux/kernel.h>
12 #include <linux/mutex.h>
13 #include <linux/pcs/pcs-xpcs.h>
14 #include <linux/phy.h>
15 #include <linux/regmap.h>
16 #include <net/dsa.h>
17 #include <linux/irq.h>
18 #include <linux/platform_data/microchip-ksz.h>
19
20 #include "ksz_ptp.h"
21
22 #define KSZ_MAX_NUM_PORTS 8
23 /* all KSZ switches count ports from 1 */
24 #define KSZ_PORT_1 0
25 #define KSZ_PORT_2 1
26 #define KSZ_PORT_4 3
27
28 struct ksz_device;
29 struct ksz_port;
30 struct phylink_mac_ops;
31
32 enum ksz_regmap_width {
33 KSZ_REGMAP_8,
34 KSZ_REGMAP_16,
35 KSZ_REGMAP_32,
36 __KSZ_NUM_REGMAPS,
37 };
38
39 struct vlan_table {
40 u32 table[3];
41 };
42
43 struct ksz_port_mib {
44 struct mutex cnt_mutex; /* structure access */
45 u8 cnt_ptr;
46 u64 *counters;
47 struct rtnl_link_stats64 stats64;
48 struct ethtool_pause_stats pause_stats;
49 struct spinlock stats64_lock;
50 };
51
52 struct ksz_mib_names {
53 int index;
54 char string[ETH_GSTRING_LEN];
55 };
56
57 struct ksz_chip_data {
58 u32 chip_id;
59 const char *dev_name;
60 int num_vlans;
61 int num_alus;
62 int num_statics;
63 int cpu_ports;
64 int port_cnt;
65 u8 port_nirqs;
66 u8 num_tx_queues;
67 u8 num_ipms; /* number of Internal Priority Maps */
68 bool tc_cbs_supported;
69
70 /**
71 * @phy_side_mdio_supported: Indicates if the chip supports an additional
72 * side MDIO channel for accessing integrated PHYs.
73 */
74 bool phy_side_mdio_supported;
75 const struct ksz_dev_ops *ops;
76 const struct phylink_mac_ops *phylink_mac_ops;
77 bool phy_errata_9477;
78 bool ksz87xx_eee_link_erratum;
79 const struct ksz_mib_names *mib_names;
80 int mib_cnt;
81 u8 reg_mib_cnt;
82 const u16 *regs;
83 const u32 *masks;
84 const u8 *shifts;
85 const u8 *xmii_ctrl0;
86 const u8 *xmii_ctrl1;
87 int stp_ctrl_reg;
88 int broadcast_ctrl_reg;
89 int multicast_ctrl_reg;
90 int start_ctrl_reg;
91 bool supports_mii[KSZ_MAX_NUM_PORTS];
92 bool supports_rmii[KSZ_MAX_NUM_PORTS];
93 bool supports_rgmii[KSZ_MAX_NUM_PORTS];
94 bool internal_phy[KSZ_MAX_NUM_PORTS];
95 bool gbit_capable[KSZ_MAX_NUM_PORTS];
96 bool ptp_capable;
97 u8 sgmii_port;
98 const struct regmap_access_table *wr_table;
99 const struct regmap_access_table *rd_table;
100 };
101
102 struct ksz_irq {
103 u16 masked;
104 u16 reg_mask;
105 u16 reg_status;
106 struct irq_domain *domain;
107 int nirqs;
108 int irq_num;
109 char name[16];
110 struct ksz_device *dev;
111 };
112
113 struct ksz_ptp_irq {
114 struct ksz_port *port;
115 u16 ts_reg;
116 bool ts_en;
117 char name[16];
118 int num;
119 };
120
121 struct ksz_switch_macaddr {
122 unsigned char addr[ETH_ALEN];
123 refcount_t refcount;
124 };
125
126 struct ksz_port {
127 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */
128 bool learning;
129 bool isolated;
130 int stp_state;
131 struct phy_device phydev;
132
133 u32 fiber:1; /* port is fiber */
134 u32 force:1;
135 u32 read:1; /* read MIB counters in background */
136 u32 freeze:1; /* MIB counter freeze is enabled */
137 u32 sgmii_adv_write:1;
138
139 struct ksz_port_mib mib;
140 phy_interface_t interface;
141 u32 rgmii_tx_val;
142 u32 rgmii_rx_val;
143 struct ksz_device *ksz_dev;
144 void *acl_priv;
145 struct ksz_irq pirq;
146 u8 num;
147 struct phylink_pcs *pcs;
148 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP)
149 struct kernel_hwtstamp_config tstamp_config;
150 bool hwts_tx_en;
151 bool hwts_rx_en;
152 struct ksz_irq ptpirq;
153 struct ksz_ptp_irq ptpmsg_irq[3];
154 ktime_t tstamp_msg;
155 struct completion tstamp_msg_comp;
156 #endif
157 bool manual_flow;
158 };
159
160 struct ksz_device {
161 struct dsa_switch *ds;
162 struct ksz_platform_data *pdata;
163 const struct ksz_chip_data *info;
164
165 struct mutex dev_mutex; /* device access */
166 struct mutex regmap_mutex; /* regmap access */
167 struct mutex alu_mutex; /* ALU access */
168 struct mutex vlan_mutex; /* vlan access */
169 const struct ksz_dev_ops *dev_ops;
170
171 struct device *dev;
172 struct regmap *regmap[__KSZ_NUM_REGMAPS];
173
174 void *priv;
175 int irq;
176
177 struct gpio_desc *reset_gpio; /* Optional reset GPIO */
178
179 /* chip specific data */
180 u32 chip_id;
181 u8 chip_rev;
182 int cpu_port; /* port connected to CPU */
183 int phy_port_cnt;
184 phy_interface_t compat_interface;
185 bool synclko_125;
186 bool synclko_disable;
187 bool wakeup_source;
188 bool pme_active_high;
189
190 struct vlan_table *vlan_cache;
191
192 struct ksz_port *ports;
193 struct delayed_work mib_read;
194 unsigned long mib_read_interval;
195 u16 mirror_rx;
196 u16 mirror_tx;
197 u16 port_mask;
198 struct mutex lock_irq; /* IRQ Access */
199 struct ksz_irq girq;
200 struct ksz_ptp_data ptp_data;
201
202 struct ksz_switch_macaddr *switch_macaddr;
203 struct net_device *hsr_dev; /* HSR */
204 u8 hsr_ports;
205
206 /**
207 * @phy_addr_map: Array mapping switch ports to their corresponding PHY
208 * addresses.
209 */
210 u8 phy_addr_map[KSZ_MAX_NUM_PORTS];
211
212 /**
213 * @parent_mdio_bus: Pointer to the external MDIO bus controller.
214 *
215 * This points to an external MDIO bus controller that is used to access
216 * the PHYs integrated within the switch. Unlike an integrated MDIO
217 * bus, this external controller provides a direct path for managing
218 * the switch’s internal PHYs, bypassing the main SPI interface.
219 */
220 struct mii_bus *parent_mdio_bus;
221 };
222
223 /* List of supported models */
224 enum ksz_model {
225 KSZ8463,
226 KSZ8563,
227 KSZ8567,
228 KSZ8795,
229 KSZ8794,
230 KSZ8765,
231 KSZ88X3,
232 KSZ8864,
233 KSZ8895,
234 KSZ9477,
235 KSZ9896,
236 KSZ9897,
237 KSZ9893,
238 KSZ9563,
239 KSZ9567,
240 LAN9370,
241 LAN9371,
242 LAN9372,
243 LAN9373,
244 LAN9374,
245 LAN9646,
246 };
247
248 enum ksz_regs {
249 REG_SW_MAC_ADDR,
250 REG_IND_CTRL_0,
251 REG_IND_DATA_8,
252 REG_IND_DATA_CHECK,
253 REG_IND_DATA_HI,
254 REG_IND_DATA_LO,
255 REG_IND_MIB_CHECK,
256 REG_IND_BYTE,
257 P_FORCE_CTRL,
258 P_LINK_STATUS,
259 P_LOCAL_CTRL,
260 P_NEG_RESTART_CTRL,
261 P_REMOTE_STATUS,
262 P_SPEED_STATUS,
263 S_TAIL_TAG_CTRL,
264 P_STP_CTRL,
265 S_START_CTRL,
266 S_BROADCAST_CTRL,
267 S_MULTICAST_CTRL,
268 P_XMII_CTRL_0,
269 P_XMII_CTRL_1,
270 REG_SW_PME_CTRL,
271 REG_PORT_PME_STATUS,
272 REG_PORT_PME_CTRL,
273 };
274
275 enum ksz_masks {
276 PORT_802_1P_REMAPPING,
277 SW_TAIL_TAG_ENABLE,
278 MIB_COUNTER_OVERFLOW,
279 MIB_COUNTER_VALID,
280 VLAN_TABLE_FID,
281 VLAN_TABLE_MEMBERSHIP,
282 VLAN_TABLE_VALID,
283 STATIC_MAC_TABLE_VALID,
284 STATIC_MAC_TABLE_USE_FID,
285 STATIC_MAC_TABLE_FID,
286 STATIC_MAC_TABLE_OVERRIDE,
287 STATIC_MAC_TABLE_FWD_PORTS,
288 DYNAMIC_MAC_TABLE_ENTRIES_H,
289 DYNAMIC_MAC_TABLE_MAC_EMPTY,
290 DYNAMIC_MAC_TABLE_NOT_READY,
291 DYNAMIC_MAC_TABLE_ENTRIES,
292 DYNAMIC_MAC_TABLE_FID,
293 DYNAMIC_MAC_TABLE_SRC_PORT,
294 DYNAMIC_MAC_TABLE_TIMESTAMP,
295 ALU_STAT_WRITE,
296 ALU_STAT_READ,
297 P_MII_TX_FLOW_CTRL,
298 P_MII_RX_FLOW_CTRL,
299 };
300
301 enum ksz_shifts {
302 VLAN_TABLE_MEMBERSHIP_S,
303 VLAN_TABLE,
304 STATIC_MAC_FWD_PORTS,
305 STATIC_MAC_FID,
306 DYNAMIC_MAC_ENTRIES_H,
307 DYNAMIC_MAC_ENTRIES,
308 DYNAMIC_MAC_FID,
309 DYNAMIC_MAC_TIMESTAMP,
310 DYNAMIC_MAC_SRC_PORT,
311 ALU_STAT_INDEX,
312 };
313
314 enum ksz_xmii_ctrl0 {
315 P_MII_100MBIT,
316 P_MII_10MBIT,
317 P_MII_FULL_DUPLEX,
318 P_MII_HALF_DUPLEX,
319 };
320
321 enum ksz_xmii_ctrl1 {
322 P_RGMII_SEL,
323 P_RMII_SEL,
324 P_GMII_SEL,
325 P_MII_SEL,
326 P_GMII_1GBIT,
327 P_GMII_NOT_1GBIT,
328 };
329
330 struct alu_struct {
331 /* entry 1 */
332 u8 is_static:1;
333 u8 is_src_filter:1;
334 u8 is_dst_filter:1;
335 u8 prio_age:3;
336 u32 _reserv_0_1:23;
337 u8 mstp:3;
338 /* entry 2 */
339 u8 is_override:1;
340 u8 is_use_fid:1;
341 u32 _reserv_1_1:23;
342 u8 port_forward:7;
343 /* entry 3 & 4*/
344 u32 _reserv_2_1:9;
345 u8 fid:7;
346 u8 mac[ETH_ALEN];
347 };
348
349 struct ksz_dev_ops {
350 int (*setup)(struct dsa_switch *ds);
351 void (*teardown)(struct dsa_switch *ds);
352 u32 (*get_port_addr)(int port, int offset);
353 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member);
354 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port);
355 void (*port_cleanup)(struct ksz_device *dev, int port);
356 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port);
357 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs);
358
359 /**
360 * @mdio_bus_preinit: Function pointer to pre-initialize the MDIO bus
361 * for accessing PHYs.
362 * @dev: Pointer to device structure.
363 * @side_mdio: Boolean indicating if the PHYs are accessed over a side
364 * MDIO bus.
365 *
366 * This function pointer is used to configure the MDIO bus for PHY
367 * access before initiating regular PHY operations. It enables either
368 * SPI/I2C or side MDIO access modes by unlocking necessary registers
369 * and setting up access permissions for the selected mode.
370 *
371 * Return:
372 * - 0 on success.
373 * - Negative error code on failure.
374 */
375 int (*mdio_bus_preinit)(struct ksz_device *dev, bool side_mdio);
376
377 /**
378 * @create_phy_addr_map: Function pointer to create a port-to-PHY
379 * address map.
380 * @dev: Pointer to device structure.
381 * @side_mdio: Boolean indicating if the PHYs are accessed over a side
382 * MDIO bus.
383 *
384 * This function pointer is responsible for mapping switch ports to PHY
385 * addresses according to the configured access mode (SPI or side MDIO)
386 * and the device’s strap configuration. The mapping setup may vary
387 * depending on the chip variant and configuration. Ensures the correct
388 * address mapping for PHY communication.
389 *
390 * Return:
391 * - 0 on success.
392 * - Negative error code on failure (e.g., invalid configuration).
393 */
394 int (*create_phy_addr_map)(struct ksz_device *dev, bool side_mdio);
395 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val);
396 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val);
397 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr,
398 u64 *cnt);
399 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr,
400 u64 *dropped, u64 *cnt);
401 void (*r_mib_stat64)(struct ksz_device *dev, int port);
402 int (*vlan_filtering)(struct ksz_device *dev, int port,
403 bool flag, struct netlink_ext_ack *extack);
404 int (*vlan_add)(struct ksz_device *dev, int port,
405 const struct switchdev_obj_port_vlan *vlan,
406 struct netlink_ext_ack *extack);
407 int (*vlan_del)(struct ksz_device *dev, int port,
408 const struct switchdev_obj_port_vlan *vlan);
409 int (*mirror_add)(struct ksz_device *dev, int port,
410 struct dsa_mall_mirror_tc_entry *mirror,
411 bool ingress, struct netlink_ext_ack *extack);
412 void (*mirror_del)(struct ksz_device *dev, int port,
413 struct dsa_mall_mirror_tc_entry *mirror);
414 int (*fdb_add)(struct ksz_device *dev, int port,
415 const unsigned char *addr, u16 vid, struct dsa_db db);
416 int (*fdb_del)(struct ksz_device *dev, int port,
417 const unsigned char *addr, u16 vid, struct dsa_db db);
418 int (*fdb_dump)(struct ksz_device *dev, int port,
419 dsa_fdb_dump_cb_t *cb, void *data);
420 int (*mdb_add)(struct ksz_device *dev, int port,
421 const struct switchdev_obj_port_mdb *mdb,
422 struct dsa_db db);
423 int (*mdb_del)(struct ksz_device *dev, int port,
424 const struct switchdev_obj_port_mdb *mdb,
425 struct dsa_db db);
426 void (*get_caps)(struct ksz_device *dev, int port,
427 struct phylink_config *config);
428 int (*change_mtu)(struct ksz_device *dev, int port, int mtu);
429 int (*pme_write8)(struct ksz_device *dev, u32 reg, u8 value);
430 int (*pme_pread8)(struct ksz_device *dev, int port, int offset,
431 u8 *data);
432 int (*pme_pwrite8)(struct ksz_device *dev, int port, int offset,
433 u8 data);
434 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze);
435 void (*port_init_cnt)(struct ksz_device *dev, int port);
436 void (*phylink_mac_link_up)(struct ksz_device *dev, int port,
437 unsigned int mode,
438 phy_interface_t interface,
439 struct phy_device *phydev, int speed,
440 int duplex, bool tx_pause, bool rx_pause);
441 void (*setup_rgmii_delay)(struct ksz_device *dev, int port);
442 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val);
443 void (*config_cpu_port)(struct dsa_switch *ds);
444 int (*enable_stp_addr)(struct ksz_device *dev);
445 int (*reset)(struct ksz_device *dev);
446 int (*init)(struct ksz_device *dev);
447 void (*exit)(struct ksz_device *dev);
448
449 int (*pcs_create)(struct ksz_device *dev);
450 };
451
452 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv);
453 int ksz_switch_register(struct ksz_device *dev);
454 void ksz_switch_remove(struct ksz_device *dev);
455 int ksz_switch_suspend(struct device *dev);
456 int ksz_switch_resume(struct device *dev);
457
458 void ksz_init_mib_timer(struct ksz_device *dev);
459 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port);
460 void ksz_r_mib_stats64(struct ksz_device *dev, int port);
461 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port);
462 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
463 bool ksz_get_gbit(struct ksz_device *dev, int port);
464 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit);
465 extern const struct ksz_chip_data ksz_switch_chips[];
466 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port,
467 struct netlink_ext_ack *extack);
468 void ksz_switch_macaddr_put(struct dsa_switch *ds);
469 void ksz_switch_shutdown(struct ksz_device *dev);
470 int ksz_handle_wake_reason(struct ksz_device *dev, int port);
471
472 /* Common register access functions */
ksz_regmap_8(struct ksz_device * dev)473 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev)
474 {
475 return dev->regmap[KSZ_REGMAP_8];
476 }
477
ksz_regmap_16(struct ksz_device * dev)478 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev)
479 {
480 return dev->regmap[KSZ_REGMAP_16];
481 }
482
ksz_regmap_32(struct ksz_device * dev)483 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev)
484 {
485 return dev->regmap[KSZ_REGMAP_32];
486 }
487
ksz_is_ksz8463(struct ksz_device * dev)488 static inline bool ksz_is_ksz8463(struct ksz_device *dev)
489 {
490 return dev->chip_id == KSZ8463_CHIP_ID;
491 }
492
ksz_read8(struct ksz_device * dev,u32 reg,u8 * val)493 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val)
494 {
495 unsigned int value;
496 int ret = regmap_read(ksz_regmap_8(dev), reg, &value);
497
498 if (ret)
499 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg,
500 ERR_PTR(ret));
501
502 *val = value;
503 return ret;
504 }
505
ksz_read16(struct ksz_device * dev,u32 reg,u16 * val)506 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val)
507 {
508 unsigned int value;
509 int ret = regmap_read(ksz_regmap_16(dev), reg, &value);
510
511 if (ret)
512 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg,
513 ERR_PTR(ret));
514
515 *val = value;
516 return ret;
517 }
518
ksz_read32(struct ksz_device * dev,u32 reg,u32 * val)519 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val)
520 {
521 unsigned int value;
522 int ret = regmap_read(ksz_regmap_32(dev), reg, &value);
523
524 if (ret)
525 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg,
526 ERR_PTR(ret));
527
528 *val = value;
529 return ret;
530 }
531
ksz_read64(struct ksz_device * dev,u32 reg,u64 * val)532 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val)
533 {
534 u32 value[2];
535 int ret;
536
537 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2);
538 if (ret)
539 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg,
540 ERR_PTR(ret));
541 else
542 *val = (u64)value[0] << 32 | value[1];
543
544 return ret;
545 }
546
ksz_write8(struct ksz_device * dev,u32 reg,u8 value)547 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value)
548 {
549 int ret;
550
551 ret = regmap_write(ksz_regmap_8(dev), reg, value);
552 if (ret)
553 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg,
554 ERR_PTR(ret));
555
556 return ret;
557 }
558
ksz_write16(struct ksz_device * dev,u32 reg,u16 value)559 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value)
560 {
561 int ret;
562
563 ret = regmap_write(ksz_regmap_16(dev), reg, value);
564 if (ret)
565 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg,
566 ERR_PTR(ret));
567
568 return ret;
569 }
570
ksz_write32(struct ksz_device * dev,u32 reg,u32 value)571 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value)
572 {
573 int ret;
574
575 ret = regmap_write(ksz_regmap_32(dev), reg, value);
576 if (ret)
577 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg,
578 ERR_PTR(ret));
579
580 return ret;
581 }
582
ksz_rmw16(struct ksz_device * dev,u32 reg,u16 mask,u16 value)583 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask,
584 u16 value)
585 {
586 int ret;
587
588 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value);
589 if (ret)
590 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg,
591 ERR_PTR(ret));
592
593 return ret;
594 }
595
ksz_rmw32(struct ksz_device * dev,u32 reg,u32 mask,u32 value)596 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask,
597 u32 value)
598 {
599 int ret;
600
601 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value);
602 if (ret)
603 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg,
604 ERR_PTR(ret));
605
606 return ret;
607 }
608
ksz_write64(struct ksz_device * dev,u32 reg,u64 value)609 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value)
610 {
611 u32 val[2];
612
613 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */
614 value = swab64(value);
615 val[0] = swab32(value & 0xffffffffULL);
616 val[1] = swab32(value >> 32ULL);
617
618 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2);
619 }
620
ksz_rmw8(struct ksz_device * dev,int offset,u8 mask,u8 val)621 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val)
622 {
623 int ret;
624
625 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val);
626 if (ret)
627 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset,
628 ERR_PTR(ret));
629
630 return ret;
631 }
632
ksz_pread8(struct ksz_device * dev,int port,int offset,u8 * data)633 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset,
634 u8 *data)
635 {
636 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data);
637 }
638
ksz_pread16(struct ksz_device * dev,int port,int offset,u16 * data)639 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset,
640 u16 *data)
641 {
642 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data);
643 }
644
ksz_pread32(struct ksz_device * dev,int port,int offset,u32 * data)645 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset,
646 u32 *data)
647 {
648 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data);
649 }
650
ksz_pwrite8(struct ksz_device * dev,int port,int offset,u8 data)651 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset,
652 u8 data)
653 {
654 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data);
655 }
656
ksz_pwrite16(struct ksz_device * dev,int port,int offset,u16 data)657 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset,
658 u16 data)
659 {
660 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset),
661 data);
662 }
663
ksz_pwrite32(struct ksz_device * dev,int port,int offset,u32 data)664 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset,
665 u32 data)
666 {
667 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset),
668 data);
669 }
670
ksz_prmw8(struct ksz_device * dev,int port,int offset,u8 mask,u8 val)671 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset,
672 u8 mask, u8 val)
673 {
674 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset),
675 mask, val);
676 }
677
ksz_prmw32(struct ksz_device * dev,int port,int offset,u32 mask,u32 val)678 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset,
679 u32 mask, u32 val)
680 {
681 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset),
682 mask, val);
683 }
684
ksz_regmap_lock(void * __mtx)685 static inline void ksz_regmap_lock(void *__mtx)
686 {
687 struct mutex *mtx = __mtx;
688 mutex_lock(mtx);
689 }
690
ksz_regmap_unlock(void * __mtx)691 static inline void ksz_regmap_unlock(void *__mtx)
692 {
693 struct mutex *mtx = __mtx;
694 mutex_unlock(mtx);
695 }
696
ksz_is_ksz87xx(struct ksz_device * dev)697 static inline bool ksz_is_ksz87xx(struct ksz_device *dev)
698 {
699 return dev->chip_id == KSZ8795_CHIP_ID ||
700 dev->chip_id == KSZ8794_CHIP_ID ||
701 dev->chip_id == KSZ8765_CHIP_ID;
702 }
703
ksz_is_ksz88x3(struct ksz_device * dev)704 static inline bool ksz_is_ksz88x3(struct ksz_device *dev)
705 {
706 return dev->chip_id == KSZ88X3_CHIP_ID;
707 }
708
ksz_is_8895_family(struct ksz_device * dev)709 static inline bool ksz_is_8895_family(struct ksz_device *dev)
710 {
711 return dev->chip_id == KSZ8895_CHIP_ID ||
712 dev->chip_id == KSZ8864_CHIP_ID;
713 }
714
is_ksz8(struct ksz_device * dev)715 static inline bool is_ksz8(struct ksz_device *dev)
716 {
717 return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev) ||
718 ksz_is_8895_family(dev) || ksz_is_ksz8463(dev);
719 }
720
is_ksz88xx(struct ksz_device * dev)721 static inline bool is_ksz88xx(struct ksz_device *dev)
722 {
723 return ksz_is_ksz88x3(dev) || ksz_is_8895_family(dev) ||
724 ksz_is_ksz8463(dev);
725 }
726
is_ksz9477(struct ksz_device * dev)727 static inline bool is_ksz9477(struct ksz_device *dev)
728 {
729 return dev->chip_id == KSZ9477_CHIP_ID;
730 }
731
is_lan937x(struct ksz_device * dev)732 static inline int is_lan937x(struct ksz_device *dev)
733 {
734 return dev->chip_id == LAN9370_CHIP_ID ||
735 dev->chip_id == LAN9371_CHIP_ID ||
736 dev->chip_id == LAN9372_CHIP_ID ||
737 dev->chip_id == LAN9373_CHIP_ID ||
738 dev->chip_id == LAN9374_CHIP_ID;
739 }
740
is_lan937x_tx_phy(struct ksz_device * dev,int port)741 static inline bool is_lan937x_tx_phy(struct ksz_device *dev, int port)
742 {
743 return (dev->chip_id == LAN9371_CHIP_ID ||
744 dev->chip_id == LAN9372_CHIP_ID) && port == KSZ_PORT_4;
745 }
746
ksz_get_sgmii_port(struct ksz_device * dev)747 static inline int ksz_get_sgmii_port(struct ksz_device *dev)
748 {
749 return dev->info->sgmii_port - 1;
750 }
751
ksz_has_sgmii_port(struct ksz_device * dev)752 static inline bool ksz_has_sgmii_port(struct ksz_device *dev)
753 {
754 return dev->info->sgmii_port > 0;
755 }
756
ksz_is_sgmii_port(struct ksz_device * dev,int port)757 static inline bool ksz_is_sgmii_port(struct ksz_device *dev, int port)
758 {
759 return dev->info->sgmii_port == port + 1;
760 }
761
762 /* STP State Defines */
763 #define PORT_TX_ENABLE BIT(2)
764 #define PORT_RX_ENABLE BIT(1)
765 #define PORT_LEARN_DISABLE BIT(0)
766
767 /* Switch ID Defines */
768 #define REG_CHIP_ID0 0x00
769
770 #define SW_FAMILY_ID_M GENMASK(15, 8)
771 #define KSZ84_FAMILY_ID 0x84
772 #define KSZ87_FAMILY_ID 0x87
773 #define KSZ88_FAMILY_ID 0x88
774 #define KSZ8895_FAMILY_ID 0x95
775
776 #define KSZ8_PORT_STATUS_0 0x08
777 #define KSZ8_PORT_FIBER_MODE BIT(7)
778
779 #define SW_CHIP_ID_M GENMASK(7, 4)
780 #define KSZ87_CHIP_ID_94 0x6
781 #define KSZ87_CHIP_ID_95 0x9
782 #define KSZ88_CHIP_ID_63 0x3
783 #define KSZ8895_CHIP_ID_95 0x4
784 #define KSZ8895_CHIP_ID_95R 0x6
785
786 /* KSZ8895 specific register */
787 #define REG_KSZ8864_CHIP_ID 0xFE
788 #define SW_KSZ8864 BIT(7)
789
790 #define SW_REV_ID_M GENMASK(7, 4)
791
792 /* KSZ9893, KSZ9563, KSZ8563 specific register */
793 #define REG_CHIP_ID4 0x0f
794 #define SKU_ID_KSZ8563 0x3c
795 #define SKU_ID_KSZ9563 0x1c
796
797 /* Driver set switch broadcast storm protection at 10% rate. */
798 #define BROADCAST_STORM_PROT_RATE 10
799
800 /* 148,800 frames * 67 ms / 100 */
801 #define BROADCAST_STORM_VALUE 9969
802
803 #define BROADCAST_STORM_RATE_HI 0x07
804 #define BROADCAST_STORM_RATE_LO 0xFF
805 #define BROADCAST_STORM_RATE 0x07FF
806
807 #define MULTICAST_STORM_DISABLE BIT(6)
808
809 #define SW_START 0x01
810
811 /* xMII configuration */
812 #define P_MII_DUPLEX_M BIT(6)
813 #define P_MII_100MBIT_M BIT(4)
814
815 #define P_GMII_1GBIT_M BIT(6)
816 #define P_RGMII_ID_IG_ENABLE BIT(4)
817 #define P_RGMII_ID_EG_ENABLE BIT(3)
818 #define P_MII_MAC_MODE BIT(2)
819 #define P_MII_SEL_M 0x3
820
821 /* KSZ9477, KSZ87xx Wake-on-LAN (WoL) masks */
822 #define PME_WOL_MAGICPKT BIT(2)
823 #define PME_WOL_LINKUP BIT(1)
824 #define PME_WOL_ENERGY BIT(0)
825
826 #define PME_ENABLE BIT(1)
827 #define PME_POLARITY BIT(0)
828
829 #define KSZ87XX_REG_INT_EN 0x7D
830 #define KSZ87XX_INT_PME_MASK BIT(4)
831
832 /* Interrupt */
833 #define REG_SW_PORT_INT_STATUS__1 0x001B
834 #define REG_SW_PORT_INT_MASK__1 0x001F
835
836 #define REG_PORT_INT_STATUS 0x001B
837 #define REG_PORT_INT_MASK 0x001F
838
839 #define PORT_SRC_PHY_INT 1
840 #define PORT_SRC_PTP_INT 2
841
842 #define KSZ8795_HUGE_PACKET_SIZE 2000
843 #define KSZ8863_HUGE_PACKET_SIZE 1916
844 #define KSZ8863_NORMAL_PACKET_SIZE 1536
845 #define KSZ8_LEGAL_PACKET_SIZE 1518
846 #define KSZ9477_MAX_FRAME_SIZE 9000
847
848 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e
849 /* Drive Strength of I/O Pad
850 * 0: 8mA, 1: 16mA
851 */
852 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6)
853
854 #define KSZ8795_REG_SW_CTRL_20 0xa3
855 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d
856 #define SW_DRIVE_STRENGTH_M 0x7
857 #define SW_DRIVE_STRENGTH_2MA 0
858 #define SW_DRIVE_STRENGTH_4MA 1
859 #define SW_DRIVE_STRENGTH_8MA 2
860 #define SW_DRIVE_STRENGTH_12MA 3
861 #define SW_DRIVE_STRENGTH_16MA 4
862 #define SW_DRIVE_STRENGTH_20MA 5
863 #define SW_DRIVE_STRENGTH_24MA 6
864 #define SW_DRIVE_STRENGTH_28MA 7
865 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4
866 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0
867
868 /* TXQ Split Control Register for per-port, per-queue configuration.
869 * Register 0xAF is TXQ Split for Q3 on Port 1.
870 * Register offset formula: 0xAF + (port * 4) + (3 - queue)
871 * where: port = 0..2, queue = 0..3
872 */
873 #define KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue) \
874 (0xAF + ((port) * 4) + (3 - (queue)))
875
876 /* Bit 7 selects between:
877 * 0 = Strict priority mode (highest-priority queue first)
878 * 1 = Weighted Fair Queuing (WFQ) mode:
879 * Queue weights: Q3:Q2:Q1:Q0 = 8:4:2:1
880 * If any queues are empty, weight is redistributed.
881 *
882 * Note: This is referred to as "Weighted Fair Queuing" (WFQ) in KSZ8863/8873
883 * documentation, and as "Weighted Round Robin" (WRR) in KSZ9477 family docs.
884 */
885 #define KSZ8873_TXQ_WFQ_ENABLE BIT(7)
886
887 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420
888 #define KSZ9477_OUT_RATE_NO_LIMIT 0
889
890 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808
891
892 #define KSZ9477_PORT_TC_MAP_S 4
893
894 /* CBS related registers */
895 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900
896
897 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914
898
899 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6)
900 #define MTI_SCHEDULE_STRICT_PRIO 0
901 #define MTI_SCHEDULE_WRR 2
902 #define MTI_SHAPING_M GENMASK(5, 4)
903 #define MTI_SHAPING_OFF 0
904 #define MTI_SHAPING_SRP 1
905 #define MTI_SHAPING_TIME_AWARE 2
906
907 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915
908 #define KSZ9477_DEFAULT_WRR_WEIGHT 1
909
910 #define REG_PORT_MTI_HI_WATER_MARK 0x0916
911 #define REG_PORT_MTI_LO_WATER_MARK 0x0918
912
913 /* Regmap tables generation */
914 #define KSZ_SPI_OP_RD 3
915 #define KSZ_SPI_OP_WR 2
916
917 #define swabnot_used(x) 0
918
919 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \
920 swab##swp((opcode) << ((regbits) + (regpad)))
921
922 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \
923 { \
924 .name = #width, \
925 .val_bits = (width), \
926 .reg_stride = 1, \
927 .reg_bits = (regbits) + (regalign), \
928 .pad_bits = (regpad), \
929 .max_register = BIT(regbits) - 1, \
930 .cache_type = REGCACHE_NONE, \
931 .read_flag_mask = \
932 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \
933 regbits, regpad), \
934 .write_flag_mask = \
935 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \
936 regbits, regpad), \
937 .lock = ksz_regmap_lock, \
938 .unlock = ksz_regmap_unlock, \
939 .reg_format_endian = REGMAP_ENDIAN_BIG, \
940 .val_format_endian = REGMAP_ENDIAN_BIG \
941 }
942
943 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \
944 static const struct regmap_config ksz##_regmap_config[] = { \
945 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \
946 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \
947 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \
948 }
949
950 #define KSZ8463_REGMAP_ENTRY(width, regbits, regpad, regalign) \
951 { \
952 .name = #width, \
953 .val_bits = (width), \
954 .reg_stride = (width / 8), \
955 .reg_bits = (regbits) + (regalign), \
956 .pad_bits = (regpad), \
957 .read = ksz8463_spi_read, \
958 .write = ksz8463_spi_write, \
959 .max_register = BIT(regbits) - 1, \
960 .cache_type = REGCACHE_NONE, \
961 .zero_flag_mask = 1, \
962 .use_single_read = 1, \
963 .use_single_write = 1, \
964 .lock = ksz_regmap_lock, \
965 .unlock = ksz_regmap_unlock, \
966 }
967
968 #define KSZ8463_REGMAP_TABLE(ksz, regbits, regpad, regalign) \
969 static const struct regmap_config ksz##_regmap_config[] = { \
970 [KSZ_REGMAP_8] = KSZ8463_REGMAP_ENTRY(8, (regbits), (regpad), (regalign)), \
971 [KSZ_REGMAP_16] = KSZ8463_REGMAP_ENTRY(16, (regbits), (regpad), (regalign)), \
972 [KSZ_REGMAP_32] = KSZ8463_REGMAP_ENTRY(32, (regbits), (regpad), (regalign)), \
973 }
974
975 #endif
976