1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Microchip switch driver main logic
4 *
5 * Copyright (C) 2017-2024 Microchip Technology Inc.
6 */
7
8 #include <linux/delay.h>
9 #include <linux/dsa/ksz_common.h>
10 #include <linux/export.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/platform_data/microchip-ksz.h>
15 #include <linux/phy.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_bridge.h>
18 #include <linux/if_vlan.h>
19 #include <linux/if_hsr.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/of.h>
23 #include <linux/of_mdio.h>
24 #include <linux/of_net.h>
25 #include <linux/micrel_phy.h>
26 #include <net/dsa.h>
27 #include <net/ieee8021q.h>
28 #include <net/pkt_cls.h>
29 #include <net/switchdev.h>
30
31 #include "ksz_common.h"
32 #include "ksz_dcb.h"
33 #include "ksz_ptp.h"
34 #include "ksz8.h"
35 #include "ksz9477.h"
36 #include "lan937x.h"
37
38 #define MIB_COUNTER_NUM 0x20
39
40 struct ksz_stats_raw {
41 u64 rx_hi;
42 u64 rx_undersize;
43 u64 rx_fragments;
44 u64 rx_oversize;
45 u64 rx_jabbers;
46 u64 rx_symbol_err;
47 u64 rx_crc_err;
48 u64 rx_align_err;
49 u64 rx_mac_ctrl;
50 u64 rx_pause;
51 u64 rx_bcast;
52 u64 rx_mcast;
53 u64 rx_ucast;
54 u64 rx_64_or_less;
55 u64 rx_65_127;
56 u64 rx_128_255;
57 u64 rx_256_511;
58 u64 rx_512_1023;
59 u64 rx_1024_1522;
60 u64 rx_1523_2000;
61 u64 rx_2001;
62 u64 tx_hi;
63 u64 tx_late_col;
64 u64 tx_pause;
65 u64 tx_bcast;
66 u64 tx_mcast;
67 u64 tx_ucast;
68 u64 tx_deferred;
69 u64 tx_total_col;
70 u64 tx_exc_col;
71 u64 tx_single_col;
72 u64 tx_mult_col;
73 u64 rx_total;
74 u64 tx_total;
75 u64 rx_discards;
76 u64 tx_discards;
77 };
78
79 struct ksz88xx_stats_raw {
80 u64 rx;
81 u64 rx_hi;
82 u64 rx_undersize;
83 u64 rx_fragments;
84 u64 rx_oversize;
85 u64 rx_jabbers;
86 u64 rx_symbol_err;
87 u64 rx_crc_err;
88 u64 rx_align_err;
89 u64 rx_mac_ctrl;
90 u64 rx_pause;
91 u64 rx_bcast;
92 u64 rx_mcast;
93 u64 rx_ucast;
94 u64 rx_64_or_less;
95 u64 rx_65_127;
96 u64 rx_128_255;
97 u64 rx_256_511;
98 u64 rx_512_1023;
99 u64 rx_1024_1522;
100 u64 tx;
101 u64 tx_hi;
102 u64 tx_late_col;
103 u64 tx_pause;
104 u64 tx_bcast;
105 u64 tx_mcast;
106 u64 tx_ucast;
107 u64 tx_deferred;
108 u64 tx_total_col;
109 u64 tx_exc_col;
110 u64 tx_single_col;
111 u64 tx_mult_col;
112 u64 rx_discards;
113 u64 tx_discards;
114 };
115
116 static const struct ksz_mib_names ksz88xx_mib_names[] = {
117 { 0x00, "rx" },
118 { 0x01, "rx_hi" },
119 { 0x02, "rx_undersize" },
120 { 0x03, "rx_fragments" },
121 { 0x04, "rx_oversize" },
122 { 0x05, "rx_jabbers" },
123 { 0x06, "rx_symbol_err" },
124 { 0x07, "rx_crc_err" },
125 { 0x08, "rx_align_err" },
126 { 0x09, "rx_mac_ctrl" },
127 { 0x0a, "rx_pause" },
128 { 0x0b, "rx_bcast" },
129 { 0x0c, "rx_mcast" },
130 { 0x0d, "rx_ucast" },
131 { 0x0e, "rx_64_or_less" },
132 { 0x0f, "rx_65_127" },
133 { 0x10, "rx_128_255" },
134 { 0x11, "rx_256_511" },
135 { 0x12, "rx_512_1023" },
136 { 0x13, "rx_1024_1522" },
137 { 0x14, "tx" },
138 { 0x15, "tx_hi" },
139 { 0x16, "tx_late_col" },
140 { 0x17, "tx_pause" },
141 { 0x18, "tx_bcast" },
142 { 0x19, "tx_mcast" },
143 { 0x1a, "tx_ucast" },
144 { 0x1b, "tx_deferred" },
145 { 0x1c, "tx_total_col" },
146 { 0x1d, "tx_exc_col" },
147 { 0x1e, "tx_single_col" },
148 { 0x1f, "tx_mult_col" },
149 { 0x100, "rx_discards" },
150 { 0x101, "tx_discards" },
151 };
152
153 static const struct ksz_mib_names ksz9477_mib_names[] = {
154 { 0x00, "rx_hi" },
155 { 0x01, "rx_undersize" },
156 { 0x02, "rx_fragments" },
157 { 0x03, "rx_oversize" },
158 { 0x04, "rx_jabbers" },
159 { 0x05, "rx_symbol_err" },
160 { 0x06, "rx_crc_err" },
161 { 0x07, "rx_align_err" },
162 { 0x08, "rx_mac_ctrl" },
163 { 0x09, "rx_pause" },
164 { 0x0A, "rx_bcast" },
165 { 0x0B, "rx_mcast" },
166 { 0x0C, "rx_ucast" },
167 { 0x0D, "rx_64_or_less" },
168 { 0x0E, "rx_65_127" },
169 { 0x0F, "rx_128_255" },
170 { 0x10, "rx_256_511" },
171 { 0x11, "rx_512_1023" },
172 { 0x12, "rx_1024_1522" },
173 { 0x13, "rx_1523_2000" },
174 { 0x14, "rx_2001" },
175 { 0x15, "tx_hi" },
176 { 0x16, "tx_late_col" },
177 { 0x17, "tx_pause" },
178 { 0x18, "tx_bcast" },
179 { 0x19, "tx_mcast" },
180 { 0x1A, "tx_ucast" },
181 { 0x1B, "tx_deferred" },
182 { 0x1C, "tx_total_col" },
183 { 0x1D, "tx_exc_col" },
184 { 0x1E, "tx_single_col" },
185 { 0x1F, "tx_mult_col" },
186 { 0x80, "rx_total" },
187 { 0x81, "tx_total" },
188 { 0x82, "rx_discards" },
189 { 0x83, "tx_discards" },
190 };
191
192 struct ksz_driver_strength_prop {
193 const char *name;
194 int offset;
195 int value;
196 };
197
198 enum ksz_driver_strength_type {
199 KSZ_DRIVER_STRENGTH_HI,
200 KSZ_DRIVER_STRENGTH_LO,
201 KSZ_DRIVER_STRENGTH_IO,
202 };
203
204 /**
205 * struct ksz_drive_strength - drive strength mapping
206 * @reg_val: register value
207 * @microamp: microamp value
208 */
209 struct ksz_drive_strength {
210 u32 reg_val;
211 u32 microamp;
212 };
213
214 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants
215 *
216 * This values are not documented in KSZ9477 variants but confirmed by
217 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893
218 * and KSZ8563 are using same register (drive strength) settings like KSZ8795.
219 *
220 * Documentation in KSZ8795CLX provides more information with some
221 * recommendations:
222 * - for high speed signals
223 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using
224 * 2.5V or 3.3V VDDIO.
225 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with
226 * using 1.8V VDDIO.
227 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V
228 * or 3.3V VDDIO.
229 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO.
230 * 5. In same interface, the heavy loading should use higher one of the
231 * drive current strength.
232 * - for low speed signals
233 * 1. 3.3V VDDIO, use either 4 mA or 8 mA.
234 * 2. 2.5V VDDIO, use either 8 mA or 12 mA.
235 * 3. 1.8V VDDIO, use either 12 mA or 16 mA.
236 * 4. If it is heavy loading, can use higher drive current strength.
237 */
238 static const struct ksz_drive_strength ksz9477_drive_strengths[] = {
239 { SW_DRIVE_STRENGTH_2MA, 2000 },
240 { SW_DRIVE_STRENGTH_4MA, 4000 },
241 { SW_DRIVE_STRENGTH_8MA, 8000 },
242 { SW_DRIVE_STRENGTH_12MA, 12000 },
243 { SW_DRIVE_STRENGTH_16MA, 16000 },
244 { SW_DRIVE_STRENGTH_20MA, 20000 },
245 { SW_DRIVE_STRENGTH_24MA, 24000 },
246 { SW_DRIVE_STRENGTH_28MA, 28000 },
247 };
248
249 /* ksz88x3_drive_strengths - Drive strength mapping for KSZ8863, KSZ8873, ..
250 * variants.
251 * This values are documented in KSZ8873 and KSZ8863 datasheets.
252 */
253 static const struct ksz_drive_strength ksz88x3_drive_strengths[] = {
254 { 0, 8000 },
255 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 },
256 };
257
258 static void ksz88x3_phylink_mac_config(struct phylink_config *config,
259 unsigned int mode,
260 const struct phylink_link_state *state);
261 static void ksz_phylink_mac_config(struct phylink_config *config,
262 unsigned int mode,
263 const struct phylink_link_state *state);
264 static void ksz_phylink_mac_link_down(struct phylink_config *config,
265 unsigned int mode,
266 phy_interface_t interface);
267
268 static const struct phylink_mac_ops ksz88x3_phylink_mac_ops = {
269 .mac_config = ksz88x3_phylink_mac_config,
270 .mac_link_down = ksz_phylink_mac_link_down,
271 .mac_link_up = ksz8_phylink_mac_link_up,
272 };
273
274 static const struct phylink_mac_ops ksz8_phylink_mac_ops = {
275 .mac_config = ksz_phylink_mac_config,
276 .mac_link_down = ksz_phylink_mac_link_down,
277 .mac_link_up = ksz8_phylink_mac_link_up,
278 };
279
280 static const struct ksz_dev_ops ksz88xx_dev_ops = {
281 .setup = ksz8_setup,
282 .get_port_addr = ksz8_get_port_addr,
283 .cfg_port_member = ksz8_cfg_port_member,
284 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
285 .port_setup = ksz8_port_setup,
286 .r_phy = ksz8_r_phy,
287 .w_phy = ksz8_w_phy,
288 .r_mib_cnt = ksz8_r_mib_cnt,
289 .r_mib_pkt = ksz8_r_mib_pkt,
290 .r_mib_stat64 = ksz88xx_r_mib_stats64,
291 .freeze_mib = ksz8_freeze_mib,
292 .port_init_cnt = ksz8_port_init_cnt,
293 .fdb_dump = ksz8_fdb_dump,
294 .fdb_add = ksz8_fdb_add,
295 .fdb_del = ksz8_fdb_del,
296 .mdb_add = ksz8_mdb_add,
297 .mdb_del = ksz8_mdb_del,
298 .vlan_filtering = ksz8_port_vlan_filtering,
299 .vlan_add = ksz8_port_vlan_add,
300 .vlan_del = ksz8_port_vlan_del,
301 .mirror_add = ksz8_port_mirror_add,
302 .mirror_del = ksz8_port_mirror_del,
303 .get_caps = ksz8_get_caps,
304 .config_cpu_port = ksz8_config_cpu_port,
305 .enable_stp_addr = ksz8_enable_stp_addr,
306 .reset = ksz8_reset_switch,
307 .init = ksz8_switch_init,
308 .exit = ksz8_switch_exit,
309 .change_mtu = ksz8_change_mtu,
310 .pme_write8 = ksz8_pme_write8,
311 .pme_pread8 = ksz8_pme_pread8,
312 .pme_pwrite8 = ksz8_pme_pwrite8,
313 };
314
315 static const struct ksz_dev_ops ksz87xx_dev_ops = {
316 .setup = ksz8_setup,
317 .get_port_addr = ksz8_get_port_addr,
318 .cfg_port_member = ksz8_cfg_port_member,
319 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
320 .port_setup = ksz8_port_setup,
321 .r_phy = ksz8_r_phy,
322 .w_phy = ksz8_w_phy,
323 .r_mib_cnt = ksz8_r_mib_cnt,
324 .r_mib_pkt = ksz8_r_mib_pkt,
325 .r_mib_stat64 = ksz_r_mib_stats64,
326 .freeze_mib = ksz8_freeze_mib,
327 .port_init_cnt = ksz8_port_init_cnt,
328 .fdb_dump = ksz8_fdb_dump,
329 .fdb_add = ksz8_fdb_add,
330 .fdb_del = ksz8_fdb_del,
331 .mdb_add = ksz8_mdb_add,
332 .mdb_del = ksz8_mdb_del,
333 .vlan_filtering = ksz8_port_vlan_filtering,
334 .vlan_add = ksz8_port_vlan_add,
335 .vlan_del = ksz8_port_vlan_del,
336 .mirror_add = ksz8_port_mirror_add,
337 .mirror_del = ksz8_port_mirror_del,
338 .get_caps = ksz8_get_caps,
339 .config_cpu_port = ksz8_config_cpu_port,
340 .enable_stp_addr = ksz8_enable_stp_addr,
341 .reset = ksz8_reset_switch,
342 .init = ksz8_switch_init,
343 .exit = ksz8_switch_exit,
344 .change_mtu = ksz8_change_mtu,
345 .pme_write8 = ksz8_pme_write8,
346 .pme_pread8 = ksz8_pme_pread8,
347 .pme_pwrite8 = ksz8_pme_pwrite8,
348 };
349
350 static void ksz9477_phylink_mac_link_up(struct phylink_config *config,
351 struct phy_device *phydev,
352 unsigned int mode,
353 phy_interface_t interface,
354 int speed, int duplex, bool tx_pause,
355 bool rx_pause);
356
357 static const struct phylink_mac_ops ksz9477_phylink_mac_ops = {
358 .mac_config = ksz_phylink_mac_config,
359 .mac_link_down = ksz_phylink_mac_link_down,
360 .mac_link_up = ksz9477_phylink_mac_link_up,
361 };
362
363 static const struct ksz_dev_ops ksz9477_dev_ops = {
364 .setup = ksz9477_setup,
365 .get_port_addr = ksz9477_get_port_addr,
366 .cfg_port_member = ksz9477_cfg_port_member,
367 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
368 .port_setup = ksz9477_port_setup,
369 .set_ageing_time = ksz9477_set_ageing_time,
370 .r_phy = ksz9477_r_phy,
371 .w_phy = ksz9477_w_phy,
372 .r_mib_cnt = ksz9477_r_mib_cnt,
373 .r_mib_pkt = ksz9477_r_mib_pkt,
374 .r_mib_stat64 = ksz_r_mib_stats64,
375 .freeze_mib = ksz9477_freeze_mib,
376 .port_init_cnt = ksz9477_port_init_cnt,
377 .vlan_filtering = ksz9477_port_vlan_filtering,
378 .vlan_add = ksz9477_port_vlan_add,
379 .vlan_del = ksz9477_port_vlan_del,
380 .mirror_add = ksz9477_port_mirror_add,
381 .mirror_del = ksz9477_port_mirror_del,
382 .get_caps = ksz9477_get_caps,
383 .fdb_dump = ksz9477_fdb_dump,
384 .fdb_add = ksz9477_fdb_add,
385 .fdb_del = ksz9477_fdb_del,
386 .mdb_add = ksz9477_mdb_add,
387 .mdb_del = ksz9477_mdb_del,
388 .change_mtu = ksz9477_change_mtu,
389 .pme_write8 = ksz_write8,
390 .pme_pread8 = ksz_pread8,
391 .pme_pwrite8 = ksz_pwrite8,
392 .config_cpu_port = ksz9477_config_cpu_port,
393 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc,
394 .enable_stp_addr = ksz9477_enable_stp_addr,
395 .reset = ksz9477_reset_switch,
396 .init = ksz9477_switch_init,
397 .exit = ksz9477_switch_exit,
398 };
399
400 static const struct phylink_mac_ops lan937x_phylink_mac_ops = {
401 .mac_config = ksz_phylink_mac_config,
402 .mac_link_down = ksz_phylink_mac_link_down,
403 .mac_link_up = ksz9477_phylink_mac_link_up,
404 };
405
406 static const struct ksz_dev_ops lan937x_dev_ops = {
407 .setup = lan937x_setup,
408 .teardown = lan937x_teardown,
409 .get_port_addr = ksz9477_get_port_addr,
410 .cfg_port_member = ksz9477_cfg_port_member,
411 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
412 .port_setup = lan937x_port_setup,
413 .set_ageing_time = lan937x_set_ageing_time,
414 .mdio_bus_preinit = lan937x_mdio_bus_preinit,
415 .create_phy_addr_map = lan937x_create_phy_addr_map,
416 .r_phy = lan937x_r_phy,
417 .w_phy = lan937x_w_phy,
418 .r_mib_cnt = ksz9477_r_mib_cnt,
419 .r_mib_pkt = ksz9477_r_mib_pkt,
420 .r_mib_stat64 = ksz_r_mib_stats64,
421 .freeze_mib = ksz9477_freeze_mib,
422 .port_init_cnt = ksz9477_port_init_cnt,
423 .vlan_filtering = ksz9477_port_vlan_filtering,
424 .vlan_add = ksz9477_port_vlan_add,
425 .vlan_del = ksz9477_port_vlan_del,
426 .mirror_add = ksz9477_port_mirror_add,
427 .mirror_del = ksz9477_port_mirror_del,
428 .get_caps = lan937x_phylink_get_caps,
429 .setup_rgmii_delay = lan937x_setup_rgmii_delay,
430 .fdb_dump = ksz9477_fdb_dump,
431 .fdb_add = ksz9477_fdb_add,
432 .fdb_del = ksz9477_fdb_del,
433 .mdb_add = ksz9477_mdb_add,
434 .mdb_del = ksz9477_mdb_del,
435 .change_mtu = lan937x_change_mtu,
436 .config_cpu_port = lan937x_config_cpu_port,
437 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc,
438 .enable_stp_addr = ksz9477_enable_stp_addr,
439 .reset = lan937x_reset_switch,
440 .init = lan937x_switch_init,
441 .exit = lan937x_switch_exit,
442 };
443
444 static const u16 ksz8795_regs[] = {
445 [REG_SW_MAC_ADDR] = 0x68,
446 [REG_IND_CTRL_0] = 0x6E,
447 [REG_IND_DATA_8] = 0x70,
448 [REG_IND_DATA_CHECK] = 0x72,
449 [REG_IND_DATA_HI] = 0x71,
450 [REG_IND_DATA_LO] = 0x75,
451 [REG_IND_MIB_CHECK] = 0x74,
452 [REG_IND_BYTE] = 0xA0,
453 [P_FORCE_CTRL] = 0x0C,
454 [P_LINK_STATUS] = 0x0E,
455 [P_LOCAL_CTRL] = 0x07,
456 [P_NEG_RESTART_CTRL] = 0x0D,
457 [P_REMOTE_STATUS] = 0x08,
458 [P_SPEED_STATUS] = 0x09,
459 [S_TAIL_TAG_CTRL] = 0x0C,
460 [P_STP_CTRL] = 0x02,
461 [S_START_CTRL] = 0x01,
462 [S_BROADCAST_CTRL] = 0x06,
463 [S_MULTICAST_CTRL] = 0x04,
464 [P_XMII_CTRL_0] = 0x06,
465 [P_XMII_CTRL_1] = 0x06,
466 [REG_SW_PME_CTRL] = 0x8003,
467 [REG_PORT_PME_STATUS] = 0x8003,
468 [REG_PORT_PME_CTRL] = 0x8007,
469 };
470
471 static const u32 ksz8795_masks[] = {
472 [PORT_802_1P_REMAPPING] = BIT(7),
473 [SW_TAIL_TAG_ENABLE] = BIT(1),
474 [MIB_COUNTER_OVERFLOW] = BIT(6),
475 [MIB_COUNTER_VALID] = BIT(5),
476 [VLAN_TABLE_FID] = GENMASK(6, 0),
477 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
478 [VLAN_TABLE_VALID] = BIT(12),
479 [STATIC_MAC_TABLE_VALID] = BIT(21),
480 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
481 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
482 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
483 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
484 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
485 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
486 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
487 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
488 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
489 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
490 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
491 [P_MII_TX_FLOW_CTRL] = BIT(5),
492 [P_MII_RX_FLOW_CTRL] = BIT(5),
493 };
494
495 static const u8 ksz8795_xmii_ctrl0[] = {
496 [P_MII_100MBIT] = 0,
497 [P_MII_10MBIT] = 1,
498 [P_MII_FULL_DUPLEX] = 0,
499 [P_MII_HALF_DUPLEX] = 1,
500 };
501
502 static const u8 ksz8795_xmii_ctrl1[] = {
503 [P_RGMII_SEL] = 3,
504 [P_GMII_SEL] = 2,
505 [P_RMII_SEL] = 1,
506 [P_MII_SEL] = 0,
507 [P_GMII_1GBIT] = 1,
508 [P_GMII_NOT_1GBIT] = 0,
509 };
510
511 static const u8 ksz8795_shifts[] = {
512 [VLAN_TABLE_MEMBERSHIP_S] = 7,
513 [VLAN_TABLE] = 16,
514 [STATIC_MAC_FWD_PORTS] = 16,
515 [STATIC_MAC_FID] = 24,
516 [DYNAMIC_MAC_ENTRIES_H] = 3,
517 [DYNAMIC_MAC_ENTRIES] = 29,
518 [DYNAMIC_MAC_FID] = 16,
519 [DYNAMIC_MAC_TIMESTAMP] = 27,
520 [DYNAMIC_MAC_SRC_PORT] = 24,
521 };
522
523 static const u16 ksz8863_regs[] = {
524 [REG_SW_MAC_ADDR] = 0x70,
525 [REG_IND_CTRL_0] = 0x79,
526 [REG_IND_DATA_8] = 0x7B,
527 [REG_IND_DATA_CHECK] = 0x7B,
528 [REG_IND_DATA_HI] = 0x7C,
529 [REG_IND_DATA_LO] = 0x80,
530 [REG_IND_MIB_CHECK] = 0x80,
531 [P_FORCE_CTRL] = 0x0C,
532 [P_LINK_STATUS] = 0x0E,
533 [P_LOCAL_CTRL] = 0x0C,
534 [P_NEG_RESTART_CTRL] = 0x0D,
535 [P_REMOTE_STATUS] = 0x0E,
536 [P_SPEED_STATUS] = 0x0F,
537 [S_TAIL_TAG_CTRL] = 0x03,
538 [P_STP_CTRL] = 0x02,
539 [S_START_CTRL] = 0x01,
540 [S_BROADCAST_CTRL] = 0x06,
541 [S_MULTICAST_CTRL] = 0x04,
542 };
543
544 static const u32 ksz8863_masks[] = {
545 [PORT_802_1P_REMAPPING] = BIT(3),
546 [SW_TAIL_TAG_ENABLE] = BIT(6),
547 [MIB_COUNTER_OVERFLOW] = BIT(7),
548 [MIB_COUNTER_VALID] = BIT(6),
549 [VLAN_TABLE_FID] = GENMASK(15, 12),
550 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
551 [VLAN_TABLE_VALID] = BIT(19),
552 [STATIC_MAC_TABLE_VALID] = BIT(19),
553 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
554 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22),
555 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
556 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
557 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),
558 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2),
559 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
560 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),
561 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
562 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
563 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
564 };
565
566 static u8 ksz8863_shifts[] = {
567 [VLAN_TABLE_MEMBERSHIP_S] = 16,
568 [STATIC_MAC_FWD_PORTS] = 16,
569 [STATIC_MAC_FID] = 22,
570 [DYNAMIC_MAC_ENTRIES_H] = 8,
571 [DYNAMIC_MAC_ENTRIES] = 24,
572 [DYNAMIC_MAC_FID] = 16,
573 [DYNAMIC_MAC_TIMESTAMP] = 22,
574 [DYNAMIC_MAC_SRC_PORT] = 20,
575 };
576
577 static const u16 ksz8895_regs[] = {
578 [REG_SW_MAC_ADDR] = 0x68,
579 [REG_IND_CTRL_0] = 0x6E,
580 [REG_IND_DATA_8] = 0x70,
581 [REG_IND_DATA_CHECK] = 0x72,
582 [REG_IND_DATA_HI] = 0x71,
583 [REG_IND_DATA_LO] = 0x75,
584 [REG_IND_MIB_CHECK] = 0x75,
585 [P_FORCE_CTRL] = 0x0C,
586 [P_LINK_STATUS] = 0x0E,
587 [P_LOCAL_CTRL] = 0x0C,
588 [P_NEG_RESTART_CTRL] = 0x0D,
589 [P_REMOTE_STATUS] = 0x0E,
590 [P_SPEED_STATUS] = 0x09,
591 [S_TAIL_TAG_CTRL] = 0x0C,
592 [P_STP_CTRL] = 0x02,
593 [S_START_CTRL] = 0x01,
594 [S_BROADCAST_CTRL] = 0x06,
595 [S_MULTICAST_CTRL] = 0x04,
596 };
597
598 static const u32 ksz8895_masks[] = {
599 [PORT_802_1P_REMAPPING] = BIT(7),
600 [SW_TAIL_TAG_ENABLE] = BIT(1),
601 [MIB_COUNTER_OVERFLOW] = BIT(7),
602 [MIB_COUNTER_VALID] = BIT(6),
603 [VLAN_TABLE_FID] = GENMASK(6, 0),
604 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
605 [VLAN_TABLE_VALID] = BIT(12),
606 [STATIC_MAC_TABLE_VALID] = BIT(21),
607 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
608 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
609 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
610 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
611 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
612 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
613 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
614 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
615 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
616 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
617 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
618 };
619
620 static const u8 ksz8895_shifts[] = {
621 [VLAN_TABLE_MEMBERSHIP_S] = 7,
622 [VLAN_TABLE] = 13,
623 [STATIC_MAC_FWD_PORTS] = 16,
624 [STATIC_MAC_FID] = 24,
625 [DYNAMIC_MAC_ENTRIES_H] = 3,
626 [DYNAMIC_MAC_ENTRIES] = 29,
627 [DYNAMIC_MAC_FID] = 16,
628 [DYNAMIC_MAC_TIMESTAMP] = 27,
629 [DYNAMIC_MAC_SRC_PORT] = 24,
630 };
631
632 static const u16 ksz9477_regs[] = {
633 [REG_SW_MAC_ADDR] = 0x0302,
634 [P_STP_CTRL] = 0x0B04,
635 [S_START_CTRL] = 0x0300,
636 [S_BROADCAST_CTRL] = 0x0332,
637 [S_MULTICAST_CTRL] = 0x0331,
638 [P_XMII_CTRL_0] = 0x0300,
639 [P_XMII_CTRL_1] = 0x0301,
640 [REG_SW_PME_CTRL] = 0x0006,
641 [REG_PORT_PME_STATUS] = 0x0013,
642 [REG_PORT_PME_CTRL] = 0x0017,
643 };
644
645 static const u32 ksz9477_masks[] = {
646 [ALU_STAT_WRITE] = 0,
647 [ALU_STAT_READ] = 1,
648 [P_MII_TX_FLOW_CTRL] = BIT(5),
649 [P_MII_RX_FLOW_CTRL] = BIT(3),
650 };
651
652 static const u8 ksz9477_shifts[] = {
653 [ALU_STAT_INDEX] = 16,
654 };
655
656 static const u8 ksz9477_xmii_ctrl0[] = {
657 [P_MII_100MBIT] = 1,
658 [P_MII_10MBIT] = 0,
659 [P_MII_FULL_DUPLEX] = 1,
660 [P_MII_HALF_DUPLEX] = 0,
661 };
662
663 static const u8 ksz9477_xmii_ctrl1[] = {
664 [P_RGMII_SEL] = 0,
665 [P_RMII_SEL] = 1,
666 [P_GMII_SEL] = 2,
667 [P_MII_SEL] = 3,
668 [P_GMII_1GBIT] = 0,
669 [P_GMII_NOT_1GBIT] = 1,
670 };
671
672 static const u32 lan937x_masks[] = {
673 [ALU_STAT_WRITE] = 1,
674 [ALU_STAT_READ] = 2,
675 [P_MII_TX_FLOW_CTRL] = BIT(5),
676 [P_MII_RX_FLOW_CTRL] = BIT(3),
677 };
678
679 static const u8 lan937x_shifts[] = {
680 [ALU_STAT_INDEX] = 8,
681 };
682
683 static const struct regmap_range ksz8563_valid_regs[] = {
684 regmap_reg_range(0x0000, 0x0003),
685 regmap_reg_range(0x0006, 0x0006),
686 regmap_reg_range(0x000f, 0x001f),
687 regmap_reg_range(0x0100, 0x0100),
688 regmap_reg_range(0x0104, 0x0107),
689 regmap_reg_range(0x010d, 0x010d),
690 regmap_reg_range(0x0110, 0x0113),
691 regmap_reg_range(0x0120, 0x012b),
692 regmap_reg_range(0x0201, 0x0201),
693 regmap_reg_range(0x0210, 0x0213),
694 regmap_reg_range(0x0300, 0x0300),
695 regmap_reg_range(0x0302, 0x031b),
696 regmap_reg_range(0x0320, 0x032b),
697 regmap_reg_range(0x0330, 0x0336),
698 regmap_reg_range(0x0338, 0x033e),
699 regmap_reg_range(0x0340, 0x035f),
700 regmap_reg_range(0x0370, 0x0370),
701 regmap_reg_range(0x0378, 0x0378),
702 regmap_reg_range(0x037c, 0x037d),
703 regmap_reg_range(0x0390, 0x0393),
704 regmap_reg_range(0x0400, 0x040e),
705 regmap_reg_range(0x0410, 0x042f),
706 regmap_reg_range(0x0500, 0x0519),
707 regmap_reg_range(0x0520, 0x054b),
708 regmap_reg_range(0x0550, 0x05b3),
709
710 /* port 1 */
711 regmap_reg_range(0x1000, 0x1001),
712 regmap_reg_range(0x1004, 0x100b),
713 regmap_reg_range(0x1013, 0x1013),
714 regmap_reg_range(0x1017, 0x1017),
715 regmap_reg_range(0x101b, 0x101b),
716 regmap_reg_range(0x101f, 0x1021),
717 regmap_reg_range(0x1030, 0x1030),
718 regmap_reg_range(0x1100, 0x1111),
719 regmap_reg_range(0x111a, 0x111d),
720 regmap_reg_range(0x1122, 0x1127),
721 regmap_reg_range(0x112a, 0x112b),
722 regmap_reg_range(0x1136, 0x1139),
723 regmap_reg_range(0x113e, 0x113f),
724 regmap_reg_range(0x1400, 0x1401),
725 regmap_reg_range(0x1403, 0x1403),
726 regmap_reg_range(0x1410, 0x1417),
727 regmap_reg_range(0x1420, 0x1423),
728 regmap_reg_range(0x1500, 0x1507),
729 regmap_reg_range(0x1600, 0x1612),
730 regmap_reg_range(0x1800, 0x180f),
731 regmap_reg_range(0x1900, 0x1907),
732 regmap_reg_range(0x1914, 0x191b),
733 regmap_reg_range(0x1a00, 0x1a03),
734 regmap_reg_range(0x1a04, 0x1a08),
735 regmap_reg_range(0x1b00, 0x1b01),
736 regmap_reg_range(0x1b04, 0x1b04),
737 regmap_reg_range(0x1c00, 0x1c05),
738 regmap_reg_range(0x1c08, 0x1c1b),
739
740 /* port 2 */
741 regmap_reg_range(0x2000, 0x2001),
742 regmap_reg_range(0x2004, 0x200b),
743 regmap_reg_range(0x2013, 0x2013),
744 regmap_reg_range(0x2017, 0x2017),
745 regmap_reg_range(0x201b, 0x201b),
746 regmap_reg_range(0x201f, 0x2021),
747 regmap_reg_range(0x2030, 0x2030),
748 regmap_reg_range(0x2100, 0x2111),
749 regmap_reg_range(0x211a, 0x211d),
750 regmap_reg_range(0x2122, 0x2127),
751 regmap_reg_range(0x212a, 0x212b),
752 regmap_reg_range(0x2136, 0x2139),
753 regmap_reg_range(0x213e, 0x213f),
754 regmap_reg_range(0x2400, 0x2401),
755 regmap_reg_range(0x2403, 0x2403),
756 regmap_reg_range(0x2410, 0x2417),
757 regmap_reg_range(0x2420, 0x2423),
758 regmap_reg_range(0x2500, 0x2507),
759 regmap_reg_range(0x2600, 0x2612),
760 regmap_reg_range(0x2800, 0x280f),
761 regmap_reg_range(0x2900, 0x2907),
762 regmap_reg_range(0x2914, 0x291b),
763 regmap_reg_range(0x2a00, 0x2a03),
764 regmap_reg_range(0x2a04, 0x2a08),
765 regmap_reg_range(0x2b00, 0x2b01),
766 regmap_reg_range(0x2b04, 0x2b04),
767 regmap_reg_range(0x2c00, 0x2c05),
768 regmap_reg_range(0x2c08, 0x2c1b),
769
770 /* port 3 */
771 regmap_reg_range(0x3000, 0x3001),
772 regmap_reg_range(0x3004, 0x300b),
773 regmap_reg_range(0x3013, 0x3013),
774 regmap_reg_range(0x3017, 0x3017),
775 regmap_reg_range(0x301b, 0x301b),
776 regmap_reg_range(0x301f, 0x3021),
777 regmap_reg_range(0x3030, 0x3030),
778 regmap_reg_range(0x3300, 0x3301),
779 regmap_reg_range(0x3303, 0x3303),
780 regmap_reg_range(0x3400, 0x3401),
781 regmap_reg_range(0x3403, 0x3403),
782 regmap_reg_range(0x3410, 0x3417),
783 regmap_reg_range(0x3420, 0x3423),
784 regmap_reg_range(0x3500, 0x3507),
785 regmap_reg_range(0x3600, 0x3612),
786 regmap_reg_range(0x3800, 0x380f),
787 regmap_reg_range(0x3900, 0x3907),
788 regmap_reg_range(0x3914, 0x391b),
789 regmap_reg_range(0x3a00, 0x3a03),
790 regmap_reg_range(0x3a04, 0x3a08),
791 regmap_reg_range(0x3b00, 0x3b01),
792 regmap_reg_range(0x3b04, 0x3b04),
793 regmap_reg_range(0x3c00, 0x3c05),
794 regmap_reg_range(0x3c08, 0x3c1b),
795 };
796
797 static const struct regmap_access_table ksz8563_register_set = {
798 .yes_ranges = ksz8563_valid_regs,
799 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
800 };
801
802 static const struct regmap_range ksz9477_valid_regs[] = {
803 regmap_reg_range(0x0000, 0x0003),
804 regmap_reg_range(0x0006, 0x0006),
805 regmap_reg_range(0x0010, 0x001f),
806 regmap_reg_range(0x0100, 0x0100),
807 regmap_reg_range(0x0103, 0x0107),
808 regmap_reg_range(0x010d, 0x010d),
809 regmap_reg_range(0x0110, 0x0113),
810 regmap_reg_range(0x0120, 0x012b),
811 regmap_reg_range(0x0201, 0x0201),
812 regmap_reg_range(0x0210, 0x0213),
813 regmap_reg_range(0x0300, 0x0300),
814 regmap_reg_range(0x0302, 0x031b),
815 regmap_reg_range(0x0320, 0x032b),
816 regmap_reg_range(0x0330, 0x0336),
817 regmap_reg_range(0x0338, 0x033b),
818 regmap_reg_range(0x033e, 0x033e),
819 regmap_reg_range(0x0340, 0x035f),
820 regmap_reg_range(0x0370, 0x0370),
821 regmap_reg_range(0x0378, 0x0378),
822 regmap_reg_range(0x037c, 0x037d),
823 regmap_reg_range(0x0390, 0x0393),
824 regmap_reg_range(0x0400, 0x040e),
825 regmap_reg_range(0x0410, 0x042f),
826 regmap_reg_range(0x0444, 0x044b),
827 regmap_reg_range(0x0450, 0x046f),
828 regmap_reg_range(0x0500, 0x0519),
829 regmap_reg_range(0x0520, 0x054b),
830 regmap_reg_range(0x0550, 0x05b3),
831 regmap_reg_range(0x0604, 0x060b),
832 regmap_reg_range(0x0610, 0x0612),
833 regmap_reg_range(0x0614, 0x062c),
834 regmap_reg_range(0x0640, 0x0645),
835 regmap_reg_range(0x0648, 0x064d),
836
837 /* port 1 */
838 regmap_reg_range(0x1000, 0x1001),
839 regmap_reg_range(0x1013, 0x1013),
840 regmap_reg_range(0x1017, 0x1017),
841 regmap_reg_range(0x101b, 0x101b),
842 regmap_reg_range(0x101f, 0x1020),
843 regmap_reg_range(0x1030, 0x1030),
844 regmap_reg_range(0x1100, 0x1115),
845 regmap_reg_range(0x111a, 0x111f),
846 regmap_reg_range(0x1120, 0x112b),
847 regmap_reg_range(0x1134, 0x113b),
848 regmap_reg_range(0x113c, 0x113f),
849 regmap_reg_range(0x1400, 0x1401),
850 regmap_reg_range(0x1403, 0x1403),
851 regmap_reg_range(0x1410, 0x1417),
852 regmap_reg_range(0x1420, 0x1423),
853 regmap_reg_range(0x1500, 0x1507),
854 regmap_reg_range(0x1600, 0x1613),
855 regmap_reg_range(0x1800, 0x180f),
856 regmap_reg_range(0x1820, 0x1827),
857 regmap_reg_range(0x1830, 0x1837),
858 regmap_reg_range(0x1840, 0x184b),
859 regmap_reg_range(0x1900, 0x1907),
860 regmap_reg_range(0x1914, 0x191b),
861 regmap_reg_range(0x1920, 0x1920),
862 regmap_reg_range(0x1923, 0x1927),
863 regmap_reg_range(0x1a00, 0x1a03),
864 regmap_reg_range(0x1a04, 0x1a07),
865 regmap_reg_range(0x1b00, 0x1b01),
866 regmap_reg_range(0x1b04, 0x1b04),
867 regmap_reg_range(0x1c00, 0x1c05),
868 regmap_reg_range(0x1c08, 0x1c1b),
869
870 /* port 2 */
871 regmap_reg_range(0x2000, 0x2001),
872 regmap_reg_range(0x2013, 0x2013),
873 regmap_reg_range(0x2017, 0x2017),
874 regmap_reg_range(0x201b, 0x201b),
875 regmap_reg_range(0x201f, 0x2020),
876 regmap_reg_range(0x2030, 0x2030),
877 regmap_reg_range(0x2100, 0x2115),
878 regmap_reg_range(0x211a, 0x211f),
879 regmap_reg_range(0x2120, 0x212b),
880 regmap_reg_range(0x2134, 0x213b),
881 regmap_reg_range(0x213c, 0x213f),
882 regmap_reg_range(0x2400, 0x2401),
883 regmap_reg_range(0x2403, 0x2403),
884 regmap_reg_range(0x2410, 0x2417),
885 regmap_reg_range(0x2420, 0x2423),
886 regmap_reg_range(0x2500, 0x2507),
887 regmap_reg_range(0x2600, 0x2613),
888 regmap_reg_range(0x2800, 0x280f),
889 regmap_reg_range(0x2820, 0x2827),
890 regmap_reg_range(0x2830, 0x2837),
891 regmap_reg_range(0x2840, 0x284b),
892 regmap_reg_range(0x2900, 0x2907),
893 regmap_reg_range(0x2914, 0x291b),
894 regmap_reg_range(0x2920, 0x2920),
895 regmap_reg_range(0x2923, 0x2927),
896 regmap_reg_range(0x2a00, 0x2a03),
897 regmap_reg_range(0x2a04, 0x2a07),
898 regmap_reg_range(0x2b00, 0x2b01),
899 regmap_reg_range(0x2b04, 0x2b04),
900 regmap_reg_range(0x2c00, 0x2c05),
901 regmap_reg_range(0x2c08, 0x2c1b),
902
903 /* port 3 */
904 regmap_reg_range(0x3000, 0x3001),
905 regmap_reg_range(0x3013, 0x3013),
906 regmap_reg_range(0x3017, 0x3017),
907 regmap_reg_range(0x301b, 0x301b),
908 regmap_reg_range(0x301f, 0x3020),
909 regmap_reg_range(0x3030, 0x3030),
910 regmap_reg_range(0x3100, 0x3115),
911 regmap_reg_range(0x311a, 0x311f),
912 regmap_reg_range(0x3120, 0x312b),
913 regmap_reg_range(0x3134, 0x313b),
914 regmap_reg_range(0x313c, 0x313f),
915 regmap_reg_range(0x3400, 0x3401),
916 regmap_reg_range(0x3403, 0x3403),
917 regmap_reg_range(0x3410, 0x3417),
918 regmap_reg_range(0x3420, 0x3423),
919 regmap_reg_range(0x3500, 0x3507),
920 regmap_reg_range(0x3600, 0x3613),
921 regmap_reg_range(0x3800, 0x380f),
922 regmap_reg_range(0x3820, 0x3827),
923 regmap_reg_range(0x3830, 0x3837),
924 regmap_reg_range(0x3840, 0x384b),
925 regmap_reg_range(0x3900, 0x3907),
926 regmap_reg_range(0x3914, 0x391b),
927 regmap_reg_range(0x3920, 0x3920),
928 regmap_reg_range(0x3923, 0x3927),
929 regmap_reg_range(0x3a00, 0x3a03),
930 regmap_reg_range(0x3a04, 0x3a07),
931 regmap_reg_range(0x3b00, 0x3b01),
932 regmap_reg_range(0x3b04, 0x3b04),
933 regmap_reg_range(0x3c00, 0x3c05),
934 regmap_reg_range(0x3c08, 0x3c1b),
935
936 /* port 4 */
937 regmap_reg_range(0x4000, 0x4001),
938 regmap_reg_range(0x4013, 0x4013),
939 regmap_reg_range(0x4017, 0x4017),
940 regmap_reg_range(0x401b, 0x401b),
941 regmap_reg_range(0x401f, 0x4020),
942 regmap_reg_range(0x4030, 0x4030),
943 regmap_reg_range(0x4100, 0x4115),
944 regmap_reg_range(0x411a, 0x411f),
945 regmap_reg_range(0x4120, 0x412b),
946 regmap_reg_range(0x4134, 0x413b),
947 regmap_reg_range(0x413c, 0x413f),
948 regmap_reg_range(0x4400, 0x4401),
949 regmap_reg_range(0x4403, 0x4403),
950 regmap_reg_range(0x4410, 0x4417),
951 regmap_reg_range(0x4420, 0x4423),
952 regmap_reg_range(0x4500, 0x4507),
953 regmap_reg_range(0x4600, 0x4613),
954 regmap_reg_range(0x4800, 0x480f),
955 regmap_reg_range(0x4820, 0x4827),
956 regmap_reg_range(0x4830, 0x4837),
957 regmap_reg_range(0x4840, 0x484b),
958 regmap_reg_range(0x4900, 0x4907),
959 regmap_reg_range(0x4914, 0x491b),
960 regmap_reg_range(0x4920, 0x4920),
961 regmap_reg_range(0x4923, 0x4927),
962 regmap_reg_range(0x4a00, 0x4a03),
963 regmap_reg_range(0x4a04, 0x4a07),
964 regmap_reg_range(0x4b00, 0x4b01),
965 regmap_reg_range(0x4b04, 0x4b04),
966 regmap_reg_range(0x4c00, 0x4c05),
967 regmap_reg_range(0x4c08, 0x4c1b),
968
969 /* port 5 */
970 regmap_reg_range(0x5000, 0x5001),
971 regmap_reg_range(0x5013, 0x5013),
972 regmap_reg_range(0x5017, 0x5017),
973 regmap_reg_range(0x501b, 0x501b),
974 regmap_reg_range(0x501f, 0x5020),
975 regmap_reg_range(0x5030, 0x5030),
976 regmap_reg_range(0x5100, 0x5115),
977 regmap_reg_range(0x511a, 0x511f),
978 regmap_reg_range(0x5120, 0x512b),
979 regmap_reg_range(0x5134, 0x513b),
980 regmap_reg_range(0x513c, 0x513f),
981 regmap_reg_range(0x5400, 0x5401),
982 regmap_reg_range(0x5403, 0x5403),
983 regmap_reg_range(0x5410, 0x5417),
984 regmap_reg_range(0x5420, 0x5423),
985 regmap_reg_range(0x5500, 0x5507),
986 regmap_reg_range(0x5600, 0x5613),
987 regmap_reg_range(0x5800, 0x580f),
988 regmap_reg_range(0x5820, 0x5827),
989 regmap_reg_range(0x5830, 0x5837),
990 regmap_reg_range(0x5840, 0x584b),
991 regmap_reg_range(0x5900, 0x5907),
992 regmap_reg_range(0x5914, 0x591b),
993 regmap_reg_range(0x5920, 0x5920),
994 regmap_reg_range(0x5923, 0x5927),
995 regmap_reg_range(0x5a00, 0x5a03),
996 regmap_reg_range(0x5a04, 0x5a07),
997 regmap_reg_range(0x5b00, 0x5b01),
998 regmap_reg_range(0x5b04, 0x5b04),
999 regmap_reg_range(0x5c00, 0x5c05),
1000 regmap_reg_range(0x5c08, 0x5c1b),
1001
1002 /* port 6 */
1003 regmap_reg_range(0x6000, 0x6001),
1004 regmap_reg_range(0x6013, 0x6013),
1005 regmap_reg_range(0x6017, 0x6017),
1006 regmap_reg_range(0x601b, 0x601b),
1007 regmap_reg_range(0x601f, 0x6020),
1008 regmap_reg_range(0x6030, 0x6030),
1009 regmap_reg_range(0x6300, 0x6301),
1010 regmap_reg_range(0x6400, 0x6401),
1011 regmap_reg_range(0x6403, 0x6403),
1012 regmap_reg_range(0x6410, 0x6417),
1013 regmap_reg_range(0x6420, 0x6423),
1014 regmap_reg_range(0x6500, 0x6507),
1015 regmap_reg_range(0x6600, 0x6613),
1016 regmap_reg_range(0x6800, 0x680f),
1017 regmap_reg_range(0x6820, 0x6827),
1018 regmap_reg_range(0x6830, 0x6837),
1019 regmap_reg_range(0x6840, 0x684b),
1020 regmap_reg_range(0x6900, 0x6907),
1021 regmap_reg_range(0x6914, 0x691b),
1022 regmap_reg_range(0x6920, 0x6920),
1023 regmap_reg_range(0x6923, 0x6927),
1024 regmap_reg_range(0x6a00, 0x6a03),
1025 regmap_reg_range(0x6a04, 0x6a07),
1026 regmap_reg_range(0x6b00, 0x6b01),
1027 regmap_reg_range(0x6b04, 0x6b04),
1028 regmap_reg_range(0x6c00, 0x6c05),
1029 regmap_reg_range(0x6c08, 0x6c1b),
1030
1031 /* port 7 */
1032 regmap_reg_range(0x7000, 0x7001),
1033 regmap_reg_range(0x7013, 0x7013),
1034 regmap_reg_range(0x7017, 0x7017),
1035 regmap_reg_range(0x701b, 0x701b),
1036 regmap_reg_range(0x701f, 0x7020),
1037 regmap_reg_range(0x7030, 0x7030),
1038 regmap_reg_range(0x7200, 0x7203),
1039 regmap_reg_range(0x7206, 0x7207),
1040 regmap_reg_range(0x7300, 0x7301),
1041 regmap_reg_range(0x7400, 0x7401),
1042 regmap_reg_range(0x7403, 0x7403),
1043 regmap_reg_range(0x7410, 0x7417),
1044 regmap_reg_range(0x7420, 0x7423),
1045 regmap_reg_range(0x7500, 0x7507),
1046 regmap_reg_range(0x7600, 0x7613),
1047 regmap_reg_range(0x7800, 0x780f),
1048 regmap_reg_range(0x7820, 0x7827),
1049 regmap_reg_range(0x7830, 0x7837),
1050 regmap_reg_range(0x7840, 0x784b),
1051 regmap_reg_range(0x7900, 0x7907),
1052 regmap_reg_range(0x7914, 0x791b),
1053 regmap_reg_range(0x7920, 0x7920),
1054 regmap_reg_range(0x7923, 0x7927),
1055 regmap_reg_range(0x7a00, 0x7a03),
1056 regmap_reg_range(0x7a04, 0x7a07),
1057 regmap_reg_range(0x7b00, 0x7b01),
1058 regmap_reg_range(0x7b04, 0x7b04),
1059 regmap_reg_range(0x7c00, 0x7c05),
1060 regmap_reg_range(0x7c08, 0x7c1b),
1061 };
1062
1063 static const struct regmap_access_table ksz9477_register_set = {
1064 .yes_ranges = ksz9477_valid_regs,
1065 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
1066 };
1067
1068 static const struct regmap_range ksz9896_valid_regs[] = {
1069 regmap_reg_range(0x0000, 0x0003),
1070 regmap_reg_range(0x0006, 0x0006),
1071 regmap_reg_range(0x0010, 0x001f),
1072 regmap_reg_range(0x0100, 0x0100),
1073 regmap_reg_range(0x0103, 0x0107),
1074 regmap_reg_range(0x010d, 0x010d),
1075 regmap_reg_range(0x0110, 0x0113),
1076 regmap_reg_range(0x0120, 0x0127),
1077 regmap_reg_range(0x0201, 0x0201),
1078 regmap_reg_range(0x0210, 0x0213),
1079 regmap_reg_range(0x0300, 0x0300),
1080 regmap_reg_range(0x0302, 0x030b),
1081 regmap_reg_range(0x0310, 0x031b),
1082 regmap_reg_range(0x0320, 0x032b),
1083 regmap_reg_range(0x0330, 0x0336),
1084 regmap_reg_range(0x0338, 0x033b),
1085 regmap_reg_range(0x033e, 0x033e),
1086 regmap_reg_range(0x0340, 0x035f),
1087 regmap_reg_range(0x0370, 0x0370),
1088 regmap_reg_range(0x0378, 0x0378),
1089 regmap_reg_range(0x037c, 0x037d),
1090 regmap_reg_range(0x0390, 0x0393),
1091 regmap_reg_range(0x0400, 0x040e),
1092 regmap_reg_range(0x0410, 0x042f),
1093
1094 /* port 1 */
1095 regmap_reg_range(0x1000, 0x1001),
1096 regmap_reg_range(0x1013, 0x1013),
1097 regmap_reg_range(0x1017, 0x1017),
1098 regmap_reg_range(0x101b, 0x101b),
1099 regmap_reg_range(0x101f, 0x1020),
1100 regmap_reg_range(0x1030, 0x1030),
1101 regmap_reg_range(0x1100, 0x1115),
1102 regmap_reg_range(0x111a, 0x111f),
1103 regmap_reg_range(0x1120, 0x112b),
1104 regmap_reg_range(0x1134, 0x113b),
1105 regmap_reg_range(0x113c, 0x113f),
1106 regmap_reg_range(0x1400, 0x1401),
1107 regmap_reg_range(0x1403, 0x1403),
1108 regmap_reg_range(0x1410, 0x1417),
1109 regmap_reg_range(0x1420, 0x1423),
1110 regmap_reg_range(0x1500, 0x1507),
1111 regmap_reg_range(0x1600, 0x1612),
1112 regmap_reg_range(0x1800, 0x180f),
1113 regmap_reg_range(0x1820, 0x1827),
1114 regmap_reg_range(0x1830, 0x1837),
1115 regmap_reg_range(0x1840, 0x184b),
1116 regmap_reg_range(0x1900, 0x1907),
1117 regmap_reg_range(0x1914, 0x1915),
1118 regmap_reg_range(0x1a00, 0x1a03),
1119 regmap_reg_range(0x1a04, 0x1a07),
1120 regmap_reg_range(0x1b00, 0x1b01),
1121 regmap_reg_range(0x1b04, 0x1b04),
1122
1123 /* port 2 */
1124 regmap_reg_range(0x2000, 0x2001),
1125 regmap_reg_range(0x2013, 0x2013),
1126 regmap_reg_range(0x2017, 0x2017),
1127 regmap_reg_range(0x201b, 0x201b),
1128 regmap_reg_range(0x201f, 0x2020),
1129 regmap_reg_range(0x2030, 0x2030),
1130 regmap_reg_range(0x2100, 0x2115),
1131 regmap_reg_range(0x211a, 0x211f),
1132 regmap_reg_range(0x2120, 0x212b),
1133 regmap_reg_range(0x2134, 0x213b),
1134 regmap_reg_range(0x213c, 0x213f),
1135 regmap_reg_range(0x2400, 0x2401),
1136 regmap_reg_range(0x2403, 0x2403),
1137 regmap_reg_range(0x2410, 0x2417),
1138 regmap_reg_range(0x2420, 0x2423),
1139 regmap_reg_range(0x2500, 0x2507),
1140 regmap_reg_range(0x2600, 0x2612),
1141 regmap_reg_range(0x2800, 0x280f),
1142 regmap_reg_range(0x2820, 0x2827),
1143 regmap_reg_range(0x2830, 0x2837),
1144 regmap_reg_range(0x2840, 0x284b),
1145 regmap_reg_range(0x2900, 0x2907),
1146 regmap_reg_range(0x2914, 0x2915),
1147 regmap_reg_range(0x2a00, 0x2a03),
1148 regmap_reg_range(0x2a04, 0x2a07),
1149 regmap_reg_range(0x2b00, 0x2b01),
1150 regmap_reg_range(0x2b04, 0x2b04),
1151
1152 /* port 3 */
1153 regmap_reg_range(0x3000, 0x3001),
1154 regmap_reg_range(0x3013, 0x3013),
1155 regmap_reg_range(0x3017, 0x3017),
1156 regmap_reg_range(0x301b, 0x301b),
1157 regmap_reg_range(0x301f, 0x3020),
1158 regmap_reg_range(0x3030, 0x3030),
1159 regmap_reg_range(0x3100, 0x3115),
1160 regmap_reg_range(0x311a, 0x311f),
1161 regmap_reg_range(0x3120, 0x312b),
1162 regmap_reg_range(0x3134, 0x313b),
1163 regmap_reg_range(0x313c, 0x313f),
1164 regmap_reg_range(0x3400, 0x3401),
1165 regmap_reg_range(0x3403, 0x3403),
1166 regmap_reg_range(0x3410, 0x3417),
1167 regmap_reg_range(0x3420, 0x3423),
1168 regmap_reg_range(0x3500, 0x3507),
1169 regmap_reg_range(0x3600, 0x3612),
1170 regmap_reg_range(0x3800, 0x380f),
1171 regmap_reg_range(0x3820, 0x3827),
1172 regmap_reg_range(0x3830, 0x3837),
1173 regmap_reg_range(0x3840, 0x384b),
1174 regmap_reg_range(0x3900, 0x3907),
1175 regmap_reg_range(0x3914, 0x3915),
1176 regmap_reg_range(0x3a00, 0x3a03),
1177 regmap_reg_range(0x3a04, 0x3a07),
1178 regmap_reg_range(0x3b00, 0x3b01),
1179 regmap_reg_range(0x3b04, 0x3b04),
1180
1181 /* port 4 */
1182 regmap_reg_range(0x4000, 0x4001),
1183 regmap_reg_range(0x4013, 0x4013),
1184 regmap_reg_range(0x4017, 0x4017),
1185 regmap_reg_range(0x401b, 0x401b),
1186 regmap_reg_range(0x401f, 0x4020),
1187 regmap_reg_range(0x4030, 0x4030),
1188 regmap_reg_range(0x4100, 0x4115),
1189 regmap_reg_range(0x411a, 0x411f),
1190 regmap_reg_range(0x4120, 0x412b),
1191 regmap_reg_range(0x4134, 0x413b),
1192 regmap_reg_range(0x413c, 0x413f),
1193 regmap_reg_range(0x4400, 0x4401),
1194 regmap_reg_range(0x4403, 0x4403),
1195 regmap_reg_range(0x4410, 0x4417),
1196 regmap_reg_range(0x4420, 0x4423),
1197 regmap_reg_range(0x4500, 0x4507),
1198 regmap_reg_range(0x4600, 0x4612),
1199 regmap_reg_range(0x4800, 0x480f),
1200 regmap_reg_range(0x4820, 0x4827),
1201 regmap_reg_range(0x4830, 0x4837),
1202 regmap_reg_range(0x4840, 0x484b),
1203 regmap_reg_range(0x4900, 0x4907),
1204 regmap_reg_range(0x4914, 0x4915),
1205 regmap_reg_range(0x4a00, 0x4a03),
1206 regmap_reg_range(0x4a04, 0x4a07),
1207 regmap_reg_range(0x4b00, 0x4b01),
1208 regmap_reg_range(0x4b04, 0x4b04),
1209
1210 /* port 5 */
1211 regmap_reg_range(0x5000, 0x5001),
1212 regmap_reg_range(0x5013, 0x5013),
1213 regmap_reg_range(0x5017, 0x5017),
1214 regmap_reg_range(0x501b, 0x501b),
1215 regmap_reg_range(0x501f, 0x5020),
1216 regmap_reg_range(0x5030, 0x5030),
1217 regmap_reg_range(0x5100, 0x5115),
1218 regmap_reg_range(0x511a, 0x511f),
1219 regmap_reg_range(0x5120, 0x512b),
1220 regmap_reg_range(0x5134, 0x513b),
1221 regmap_reg_range(0x513c, 0x513f),
1222 regmap_reg_range(0x5400, 0x5401),
1223 regmap_reg_range(0x5403, 0x5403),
1224 regmap_reg_range(0x5410, 0x5417),
1225 regmap_reg_range(0x5420, 0x5423),
1226 regmap_reg_range(0x5500, 0x5507),
1227 regmap_reg_range(0x5600, 0x5612),
1228 regmap_reg_range(0x5800, 0x580f),
1229 regmap_reg_range(0x5820, 0x5827),
1230 regmap_reg_range(0x5830, 0x5837),
1231 regmap_reg_range(0x5840, 0x584b),
1232 regmap_reg_range(0x5900, 0x5907),
1233 regmap_reg_range(0x5914, 0x5915),
1234 regmap_reg_range(0x5a00, 0x5a03),
1235 regmap_reg_range(0x5a04, 0x5a07),
1236 regmap_reg_range(0x5b00, 0x5b01),
1237 regmap_reg_range(0x5b04, 0x5b04),
1238
1239 /* port 6 */
1240 regmap_reg_range(0x6000, 0x6001),
1241 regmap_reg_range(0x6013, 0x6013),
1242 regmap_reg_range(0x6017, 0x6017),
1243 regmap_reg_range(0x601b, 0x601b),
1244 regmap_reg_range(0x601f, 0x6020),
1245 regmap_reg_range(0x6030, 0x6030),
1246 regmap_reg_range(0x6100, 0x6115),
1247 regmap_reg_range(0x611a, 0x611f),
1248 regmap_reg_range(0x6120, 0x612b),
1249 regmap_reg_range(0x6134, 0x613b),
1250 regmap_reg_range(0x613c, 0x613f),
1251 regmap_reg_range(0x6300, 0x6301),
1252 regmap_reg_range(0x6400, 0x6401),
1253 regmap_reg_range(0x6403, 0x6403),
1254 regmap_reg_range(0x6410, 0x6417),
1255 regmap_reg_range(0x6420, 0x6423),
1256 regmap_reg_range(0x6500, 0x6507),
1257 regmap_reg_range(0x6600, 0x6612),
1258 regmap_reg_range(0x6800, 0x680f),
1259 regmap_reg_range(0x6820, 0x6827),
1260 regmap_reg_range(0x6830, 0x6837),
1261 regmap_reg_range(0x6840, 0x684b),
1262 regmap_reg_range(0x6900, 0x6907),
1263 regmap_reg_range(0x6914, 0x6915),
1264 regmap_reg_range(0x6a00, 0x6a03),
1265 regmap_reg_range(0x6a04, 0x6a07),
1266 regmap_reg_range(0x6b00, 0x6b01),
1267 regmap_reg_range(0x6b04, 0x6b04),
1268 };
1269
1270 static const struct regmap_access_table ksz9896_register_set = {
1271 .yes_ranges = ksz9896_valid_regs,
1272 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1273 };
1274
1275 static const struct regmap_range ksz8873_valid_regs[] = {
1276 regmap_reg_range(0x00, 0x01),
1277 /* global control register */
1278 regmap_reg_range(0x02, 0x0f),
1279
1280 /* port registers */
1281 regmap_reg_range(0x10, 0x1d),
1282 regmap_reg_range(0x1e, 0x1f),
1283 regmap_reg_range(0x20, 0x2d),
1284 regmap_reg_range(0x2e, 0x2f),
1285 regmap_reg_range(0x30, 0x39),
1286 regmap_reg_range(0x3f, 0x3f),
1287
1288 /* advanced control registers */
1289 regmap_reg_range(0x60, 0x6f),
1290 regmap_reg_range(0x70, 0x75),
1291 regmap_reg_range(0x76, 0x78),
1292 regmap_reg_range(0x79, 0x7a),
1293 regmap_reg_range(0x7b, 0x83),
1294 regmap_reg_range(0x8e, 0x99),
1295 regmap_reg_range(0x9a, 0xa5),
1296 regmap_reg_range(0xa6, 0xa6),
1297 regmap_reg_range(0xa7, 0xaa),
1298 regmap_reg_range(0xab, 0xae),
1299 regmap_reg_range(0xaf, 0xba),
1300 regmap_reg_range(0xbb, 0xbc),
1301 regmap_reg_range(0xbd, 0xbd),
1302 regmap_reg_range(0xc0, 0xc0),
1303 regmap_reg_range(0xc2, 0xc2),
1304 regmap_reg_range(0xc3, 0xc3),
1305 regmap_reg_range(0xc4, 0xc4),
1306 regmap_reg_range(0xc6, 0xc6),
1307 };
1308
1309 static const struct regmap_access_table ksz8873_register_set = {
1310 .yes_ranges = ksz8873_valid_regs,
1311 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs),
1312 };
1313
1314 const struct ksz_chip_data ksz_switch_chips[] = {
1315 [KSZ8563] = {
1316 .chip_id = KSZ8563_CHIP_ID,
1317 .dev_name = "KSZ8563",
1318 .num_vlans = 4096,
1319 .num_alus = 4096,
1320 .num_statics = 16,
1321 .cpu_ports = 0x07, /* can be configured as cpu port */
1322 .port_cnt = 3, /* total port count */
1323 .port_nirqs = 3,
1324 .num_tx_queues = 4,
1325 .num_ipms = 8,
1326 .tc_cbs_supported = true,
1327 .ops = &ksz9477_dev_ops,
1328 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1329 .mib_names = ksz9477_mib_names,
1330 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1331 .reg_mib_cnt = MIB_COUNTER_NUM,
1332 .regs = ksz9477_regs,
1333 .masks = ksz9477_masks,
1334 .shifts = ksz9477_shifts,
1335 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1336 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1337 .supports_mii = {false, false, true},
1338 .supports_rmii = {false, false, true},
1339 .supports_rgmii = {false, false, true},
1340 .internal_phy = {true, true, false},
1341 .gbit_capable = {false, false, true},
1342 .ptp_capable = true,
1343 .wr_table = &ksz8563_register_set,
1344 .rd_table = &ksz8563_register_set,
1345 },
1346
1347 [KSZ8795] = {
1348 .chip_id = KSZ8795_CHIP_ID,
1349 .dev_name = "KSZ8795",
1350 .num_vlans = 4096,
1351 .num_alus = 0,
1352 .num_statics = 32,
1353 .cpu_ports = 0x10, /* can be configured as cpu port */
1354 .port_cnt = 5, /* total cpu and user ports */
1355 .num_tx_queues = 4,
1356 .num_ipms = 4,
1357 .ops = &ksz87xx_dev_ops,
1358 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1359 .ksz87xx_eee_link_erratum = true,
1360 .mib_names = ksz9477_mib_names,
1361 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1362 .reg_mib_cnt = MIB_COUNTER_NUM,
1363 .regs = ksz8795_regs,
1364 .masks = ksz8795_masks,
1365 .shifts = ksz8795_shifts,
1366 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1367 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1368 .supports_mii = {false, false, false, false, true},
1369 .supports_rmii = {false, false, false, false, true},
1370 .supports_rgmii = {false, false, false, false, true},
1371 .internal_phy = {true, true, true, true, false},
1372 },
1373
1374 [KSZ8794] = {
1375 /* WARNING
1376 * =======
1377 * KSZ8794 is similar to KSZ8795, except the port map
1378 * contains a gap between external and CPU ports, the
1379 * port map is NOT continuous. The per-port register
1380 * map is shifted accordingly too, i.e. registers at
1381 * offset 0x40 are NOT used on KSZ8794 and they ARE
1382 * used on KSZ8795 for external port 3.
1383 * external cpu
1384 * KSZ8794 0,1,2 4
1385 * KSZ8795 0,1,2,3 4
1386 * KSZ8765 0,1,2,3 4
1387 * port_cnt is configured as 5, even though it is 4
1388 */
1389 .chip_id = KSZ8794_CHIP_ID,
1390 .dev_name = "KSZ8794",
1391 .num_vlans = 4096,
1392 .num_alus = 0,
1393 .num_statics = 32,
1394 .cpu_ports = 0x10, /* can be configured as cpu port */
1395 .port_cnt = 5, /* total cpu and user ports */
1396 .num_tx_queues = 4,
1397 .num_ipms = 4,
1398 .ops = &ksz87xx_dev_ops,
1399 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1400 .ksz87xx_eee_link_erratum = true,
1401 .mib_names = ksz9477_mib_names,
1402 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1403 .reg_mib_cnt = MIB_COUNTER_NUM,
1404 .regs = ksz8795_regs,
1405 .masks = ksz8795_masks,
1406 .shifts = ksz8795_shifts,
1407 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1408 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1409 .supports_mii = {false, false, false, false, true},
1410 .supports_rmii = {false, false, false, false, true},
1411 .supports_rgmii = {false, false, false, false, true},
1412 .internal_phy = {true, true, true, false, false},
1413 },
1414
1415 [KSZ8765] = {
1416 .chip_id = KSZ8765_CHIP_ID,
1417 .dev_name = "KSZ8765",
1418 .num_vlans = 4096,
1419 .num_alus = 0,
1420 .num_statics = 32,
1421 .cpu_ports = 0x10, /* can be configured as cpu port */
1422 .port_cnt = 5, /* total cpu and user ports */
1423 .num_tx_queues = 4,
1424 .num_ipms = 4,
1425 .ops = &ksz87xx_dev_ops,
1426 .phylink_mac_ops = &ksz8_phylink_mac_ops,
1427 .ksz87xx_eee_link_erratum = true,
1428 .mib_names = ksz9477_mib_names,
1429 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1430 .reg_mib_cnt = MIB_COUNTER_NUM,
1431 .regs = ksz8795_regs,
1432 .masks = ksz8795_masks,
1433 .shifts = ksz8795_shifts,
1434 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1435 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1436 .supports_mii = {false, false, false, false, true},
1437 .supports_rmii = {false, false, false, false, true},
1438 .supports_rgmii = {false, false, false, false, true},
1439 .internal_phy = {true, true, true, true, false},
1440 },
1441
1442 [KSZ88X3] = {
1443 .chip_id = KSZ88X3_CHIP_ID,
1444 .dev_name = "KSZ8863/KSZ8873",
1445 .num_vlans = 16,
1446 .num_alus = 0,
1447 .num_statics = 8,
1448 .cpu_ports = 0x4, /* can be configured as cpu port */
1449 .port_cnt = 3,
1450 .num_tx_queues = 4,
1451 .num_ipms = 4,
1452 .ops = &ksz88xx_dev_ops,
1453 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1454 .mib_names = ksz88xx_mib_names,
1455 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1456 .reg_mib_cnt = MIB_COUNTER_NUM,
1457 .regs = ksz8863_regs,
1458 .masks = ksz8863_masks,
1459 .shifts = ksz8863_shifts,
1460 .supports_mii = {false, false, true},
1461 .supports_rmii = {false, false, true},
1462 .internal_phy = {true, true, false},
1463 .wr_table = &ksz8873_register_set,
1464 .rd_table = &ksz8873_register_set,
1465 },
1466
1467 [KSZ8864] = {
1468 /* WARNING
1469 * =======
1470 * KSZ8864 is similar to KSZ8895, except the first port
1471 * does not exist.
1472 * external cpu
1473 * KSZ8864 1,2,3 4
1474 * KSZ8895 0,1,2,3 4
1475 * port_cnt is configured as 5, even though it is 4
1476 */
1477 .chip_id = KSZ8864_CHIP_ID,
1478 .dev_name = "KSZ8864",
1479 .num_vlans = 4096,
1480 .num_alus = 0,
1481 .num_statics = 32,
1482 .cpu_ports = 0x10, /* can be configured as cpu port */
1483 .port_cnt = 5, /* total cpu and user ports */
1484 .num_tx_queues = 4,
1485 .num_ipms = 4,
1486 .ops = &ksz88xx_dev_ops,
1487 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1488 .mib_names = ksz88xx_mib_names,
1489 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1490 .reg_mib_cnt = MIB_COUNTER_NUM,
1491 .regs = ksz8895_regs,
1492 .masks = ksz8895_masks,
1493 .shifts = ksz8895_shifts,
1494 .supports_mii = {false, false, false, false, true},
1495 .supports_rmii = {false, false, false, false, true},
1496 .internal_phy = {false, true, true, true, false},
1497 },
1498
1499 [KSZ8895] = {
1500 .chip_id = KSZ8895_CHIP_ID,
1501 .dev_name = "KSZ8895",
1502 .num_vlans = 4096,
1503 .num_alus = 0,
1504 .num_statics = 32,
1505 .cpu_ports = 0x10, /* can be configured as cpu port */
1506 .port_cnt = 5, /* total cpu and user ports */
1507 .num_tx_queues = 4,
1508 .num_ipms = 4,
1509 .ops = &ksz88xx_dev_ops,
1510 .phylink_mac_ops = &ksz88x3_phylink_mac_ops,
1511 .mib_names = ksz88xx_mib_names,
1512 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1513 .reg_mib_cnt = MIB_COUNTER_NUM,
1514 .regs = ksz8895_regs,
1515 .masks = ksz8895_masks,
1516 .shifts = ksz8895_shifts,
1517 .supports_mii = {false, false, false, false, true},
1518 .supports_rmii = {false, false, false, false, true},
1519 .internal_phy = {true, true, true, true, false},
1520 },
1521
1522 [KSZ9477] = {
1523 .chip_id = KSZ9477_CHIP_ID,
1524 .dev_name = "KSZ9477",
1525 .num_vlans = 4096,
1526 .num_alus = 4096,
1527 .num_statics = 16,
1528 .cpu_ports = 0x7F, /* can be configured as cpu port */
1529 .port_cnt = 7, /* total physical port count */
1530 .port_nirqs = 4,
1531 .num_tx_queues = 4,
1532 .num_ipms = 8,
1533 .tc_cbs_supported = true,
1534 .ops = &ksz9477_dev_ops,
1535 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1536 .phy_errata_9477 = true,
1537 .mib_names = ksz9477_mib_names,
1538 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1539 .reg_mib_cnt = MIB_COUNTER_NUM,
1540 .regs = ksz9477_regs,
1541 .masks = ksz9477_masks,
1542 .shifts = ksz9477_shifts,
1543 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1544 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1545 .supports_mii = {false, false, false, false,
1546 false, true, false},
1547 .supports_rmii = {false, false, false, false,
1548 false, true, false},
1549 .supports_rgmii = {false, false, false, false,
1550 false, true, false},
1551 .internal_phy = {true, true, true, true,
1552 true, false, false},
1553 .gbit_capable = {true, true, true, true, true, true, true},
1554 .ptp_capable = true,
1555 .wr_table = &ksz9477_register_set,
1556 .rd_table = &ksz9477_register_set,
1557 },
1558
1559 [KSZ9896] = {
1560 .chip_id = KSZ9896_CHIP_ID,
1561 .dev_name = "KSZ9896",
1562 .num_vlans = 4096,
1563 .num_alus = 4096,
1564 .num_statics = 16,
1565 .cpu_ports = 0x3F, /* can be configured as cpu port */
1566 .port_cnt = 6, /* total physical port count */
1567 .port_nirqs = 2,
1568 .num_tx_queues = 4,
1569 .num_ipms = 8,
1570 .ops = &ksz9477_dev_ops,
1571 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1572 .phy_errata_9477 = true,
1573 .mib_names = ksz9477_mib_names,
1574 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1575 .reg_mib_cnt = MIB_COUNTER_NUM,
1576 .regs = ksz9477_regs,
1577 .masks = ksz9477_masks,
1578 .shifts = ksz9477_shifts,
1579 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1580 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1581 .supports_mii = {false, false, false, false,
1582 false, true},
1583 .supports_rmii = {false, false, false, false,
1584 false, true},
1585 .supports_rgmii = {false, false, false, false,
1586 false, true},
1587 .internal_phy = {true, true, true, true,
1588 true, false},
1589 .gbit_capable = {true, true, true, true, true, true},
1590 .wr_table = &ksz9896_register_set,
1591 .rd_table = &ksz9896_register_set,
1592 },
1593
1594 [KSZ9897] = {
1595 .chip_id = KSZ9897_CHIP_ID,
1596 .dev_name = "KSZ9897",
1597 .num_vlans = 4096,
1598 .num_alus = 4096,
1599 .num_statics = 16,
1600 .cpu_ports = 0x7F, /* can be configured as cpu port */
1601 .port_cnt = 7, /* total physical port count */
1602 .port_nirqs = 2,
1603 .num_tx_queues = 4,
1604 .num_ipms = 8,
1605 .ops = &ksz9477_dev_ops,
1606 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1607 .phy_errata_9477 = true,
1608 .mib_names = ksz9477_mib_names,
1609 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1610 .reg_mib_cnt = MIB_COUNTER_NUM,
1611 .regs = ksz9477_regs,
1612 .masks = ksz9477_masks,
1613 .shifts = ksz9477_shifts,
1614 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1615 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1616 .supports_mii = {false, false, false, false,
1617 false, true, true},
1618 .supports_rmii = {false, false, false, false,
1619 false, true, true},
1620 .supports_rgmii = {false, false, false, false,
1621 false, true, true},
1622 .internal_phy = {true, true, true, true,
1623 true, false, false},
1624 .gbit_capable = {true, true, true, true, true, true, true},
1625 },
1626
1627 [KSZ9893] = {
1628 .chip_id = KSZ9893_CHIP_ID,
1629 .dev_name = "KSZ9893",
1630 .num_vlans = 4096,
1631 .num_alus = 4096,
1632 .num_statics = 16,
1633 .cpu_ports = 0x07, /* can be configured as cpu port */
1634 .port_cnt = 3, /* total port count */
1635 .port_nirqs = 2,
1636 .num_tx_queues = 4,
1637 .num_ipms = 8,
1638 .ops = &ksz9477_dev_ops,
1639 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1640 .mib_names = ksz9477_mib_names,
1641 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1642 .reg_mib_cnt = MIB_COUNTER_NUM,
1643 .regs = ksz9477_regs,
1644 .masks = ksz9477_masks,
1645 .shifts = ksz9477_shifts,
1646 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1647 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1648 .supports_mii = {false, false, true},
1649 .supports_rmii = {false, false, true},
1650 .supports_rgmii = {false, false, true},
1651 .internal_phy = {true, true, false},
1652 .gbit_capable = {true, true, true},
1653 },
1654
1655 [KSZ9563] = {
1656 .chip_id = KSZ9563_CHIP_ID,
1657 .dev_name = "KSZ9563",
1658 .num_vlans = 4096,
1659 .num_alus = 4096,
1660 .num_statics = 16,
1661 .cpu_ports = 0x07, /* can be configured as cpu port */
1662 .port_cnt = 3, /* total port count */
1663 .port_nirqs = 3,
1664 .num_tx_queues = 4,
1665 .num_ipms = 8,
1666 .tc_cbs_supported = true,
1667 .ops = &ksz9477_dev_ops,
1668 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1669 .mib_names = ksz9477_mib_names,
1670 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1671 .reg_mib_cnt = MIB_COUNTER_NUM,
1672 .regs = ksz9477_regs,
1673 .masks = ksz9477_masks,
1674 .shifts = ksz9477_shifts,
1675 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1676 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1677 .supports_mii = {false, false, true},
1678 .supports_rmii = {false, false, true},
1679 .supports_rgmii = {false, false, true},
1680 .internal_phy = {true, true, false},
1681 .gbit_capable = {true, true, true},
1682 .ptp_capable = true,
1683 },
1684
1685 [KSZ8567] = {
1686 .chip_id = KSZ8567_CHIP_ID,
1687 .dev_name = "KSZ8567",
1688 .num_vlans = 4096,
1689 .num_alus = 4096,
1690 .num_statics = 16,
1691 .cpu_ports = 0x7F, /* can be configured as cpu port */
1692 .port_cnt = 7, /* total port count */
1693 .port_nirqs = 3,
1694 .num_tx_queues = 4,
1695 .num_ipms = 8,
1696 .tc_cbs_supported = true,
1697 .ops = &ksz9477_dev_ops,
1698 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1699 .phy_errata_9477 = true,
1700 .mib_names = ksz9477_mib_names,
1701 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1702 .reg_mib_cnt = MIB_COUNTER_NUM,
1703 .regs = ksz9477_regs,
1704 .masks = ksz9477_masks,
1705 .shifts = ksz9477_shifts,
1706 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1707 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1708 .supports_mii = {false, false, false, false,
1709 false, true, true},
1710 .supports_rmii = {false, false, false, false,
1711 false, true, true},
1712 .supports_rgmii = {false, false, false, false,
1713 false, true, true},
1714 .internal_phy = {true, true, true, true,
1715 true, false, false},
1716 .gbit_capable = {false, false, false, false, false,
1717 true, true},
1718 .ptp_capable = true,
1719 },
1720
1721 [KSZ9567] = {
1722 .chip_id = KSZ9567_CHIP_ID,
1723 .dev_name = "KSZ9567",
1724 .num_vlans = 4096,
1725 .num_alus = 4096,
1726 .num_statics = 16,
1727 .cpu_ports = 0x7F, /* can be configured as cpu port */
1728 .port_cnt = 7, /* total physical port count */
1729 .port_nirqs = 3,
1730 .num_tx_queues = 4,
1731 .num_ipms = 8,
1732 .tc_cbs_supported = true,
1733 .ops = &ksz9477_dev_ops,
1734 .mib_names = ksz9477_mib_names,
1735 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1736 .reg_mib_cnt = MIB_COUNTER_NUM,
1737 .regs = ksz9477_regs,
1738 .masks = ksz9477_masks,
1739 .shifts = ksz9477_shifts,
1740 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1741 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1742 .supports_mii = {false, false, false, false,
1743 false, true, true},
1744 .supports_rmii = {false, false, false, false,
1745 false, true, true},
1746 .supports_rgmii = {false, false, false, false,
1747 false, true, true},
1748 .internal_phy = {true, true, true, true,
1749 true, false, false},
1750 .gbit_capable = {true, true, true, true, true, true, true},
1751 .ptp_capable = true,
1752 },
1753
1754 [LAN9370] = {
1755 .chip_id = LAN9370_CHIP_ID,
1756 .dev_name = "LAN9370",
1757 .num_vlans = 4096,
1758 .num_alus = 1024,
1759 .num_statics = 256,
1760 .cpu_ports = 0x10, /* can be configured as cpu port */
1761 .port_cnt = 5, /* total physical port count */
1762 .port_nirqs = 6,
1763 .num_tx_queues = 8,
1764 .num_ipms = 8,
1765 .tc_cbs_supported = true,
1766 .phy_side_mdio_supported = true,
1767 .ops = &lan937x_dev_ops,
1768 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1769 .mib_names = ksz9477_mib_names,
1770 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1771 .reg_mib_cnt = MIB_COUNTER_NUM,
1772 .regs = ksz9477_regs,
1773 .masks = lan937x_masks,
1774 .shifts = lan937x_shifts,
1775 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1776 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1777 .supports_mii = {false, false, false, false, true},
1778 .supports_rmii = {false, false, false, false, true},
1779 .supports_rgmii = {false, false, false, false, true},
1780 .internal_phy = {true, true, true, true, false},
1781 .ptp_capable = true,
1782 },
1783
1784 [LAN9371] = {
1785 .chip_id = LAN9371_CHIP_ID,
1786 .dev_name = "LAN9371",
1787 .num_vlans = 4096,
1788 .num_alus = 1024,
1789 .num_statics = 256,
1790 .cpu_ports = 0x30, /* can be configured as cpu port */
1791 .port_cnt = 6, /* total physical port count */
1792 .port_nirqs = 6,
1793 .num_tx_queues = 8,
1794 .num_ipms = 8,
1795 .tc_cbs_supported = true,
1796 .phy_side_mdio_supported = true,
1797 .ops = &lan937x_dev_ops,
1798 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1799 .mib_names = ksz9477_mib_names,
1800 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1801 .reg_mib_cnt = MIB_COUNTER_NUM,
1802 .regs = ksz9477_regs,
1803 .masks = lan937x_masks,
1804 .shifts = lan937x_shifts,
1805 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1806 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1807 .supports_mii = {false, false, false, false, true, true},
1808 .supports_rmii = {false, false, false, false, true, true},
1809 .supports_rgmii = {false, false, false, false, true, true},
1810 .internal_phy = {true, true, true, true, false, false},
1811 .ptp_capable = true,
1812 },
1813
1814 [LAN9372] = {
1815 .chip_id = LAN9372_CHIP_ID,
1816 .dev_name = "LAN9372",
1817 .num_vlans = 4096,
1818 .num_alus = 1024,
1819 .num_statics = 256,
1820 .cpu_ports = 0x30, /* can be configured as cpu port */
1821 .port_cnt = 8, /* total physical port count */
1822 .port_nirqs = 6,
1823 .num_tx_queues = 8,
1824 .num_ipms = 8,
1825 .tc_cbs_supported = true,
1826 .phy_side_mdio_supported = true,
1827 .ops = &lan937x_dev_ops,
1828 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1829 .mib_names = ksz9477_mib_names,
1830 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1831 .reg_mib_cnt = MIB_COUNTER_NUM,
1832 .regs = ksz9477_regs,
1833 .masks = lan937x_masks,
1834 .shifts = lan937x_shifts,
1835 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1836 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1837 .supports_mii = {false, false, false, false,
1838 true, true, false, false},
1839 .supports_rmii = {false, false, false, false,
1840 true, true, false, false},
1841 .supports_rgmii = {false, false, false, false,
1842 true, true, false, false},
1843 .internal_phy = {true, true, true, true,
1844 false, false, true, true},
1845 .ptp_capable = true,
1846 },
1847
1848 [LAN9373] = {
1849 .chip_id = LAN9373_CHIP_ID,
1850 .dev_name = "LAN9373",
1851 .num_vlans = 4096,
1852 .num_alus = 1024,
1853 .num_statics = 256,
1854 .cpu_ports = 0x38, /* can be configured as cpu port */
1855 .port_cnt = 5, /* total physical port count */
1856 .port_nirqs = 6,
1857 .num_tx_queues = 8,
1858 .num_ipms = 8,
1859 .tc_cbs_supported = true,
1860 .phy_side_mdio_supported = true,
1861 .ops = &lan937x_dev_ops,
1862 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1863 .mib_names = ksz9477_mib_names,
1864 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1865 .reg_mib_cnt = MIB_COUNTER_NUM,
1866 .regs = ksz9477_regs,
1867 .masks = lan937x_masks,
1868 .shifts = lan937x_shifts,
1869 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1870 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1871 .supports_mii = {false, false, false, false,
1872 true, true, false, false},
1873 .supports_rmii = {false, false, false, false,
1874 true, true, false, false},
1875 .supports_rgmii = {false, false, false, false,
1876 true, true, false, false},
1877 .internal_phy = {true, true, true, false,
1878 false, false, true, true},
1879 .ptp_capable = true,
1880 },
1881
1882 [LAN9374] = {
1883 .chip_id = LAN9374_CHIP_ID,
1884 .dev_name = "LAN9374",
1885 .num_vlans = 4096,
1886 .num_alus = 1024,
1887 .num_statics = 256,
1888 .cpu_ports = 0x30, /* can be configured as cpu port */
1889 .port_cnt = 8, /* total physical port count */
1890 .port_nirqs = 6,
1891 .num_tx_queues = 8,
1892 .num_ipms = 8,
1893 .tc_cbs_supported = true,
1894 .phy_side_mdio_supported = true,
1895 .ops = &lan937x_dev_ops,
1896 .phylink_mac_ops = &lan937x_phylink_mac_ops,
1897 .mib_names = ksz9477_mib_names,
1898 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1899 .reg_mib_cnt = MIB_COUNTER_NUM,
1900 .regs = ksz9477_regs,
1901 .masks = lan937x_masks,
1902 .shifts = lan937x_shifts,
1903 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1904 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1905 .supports_mii = {false, false, false, false,
1906 true, true, false, false},
1907 .supports_rmii = {false, false, false, false,
1908 true, true, false, false},
1909 .supports_rgmii = {false, false, false, false,
1910 true, true, false, false},
1911 .internal_phy = {true, true, true, true,
1912 false, false, true, true},
1913 .ptp_capable = true,
1914 },
1915
1916 [LAN9646] = {
1917 .chip_id = LAN9646_CHIP_ID,
1918 .dev_name = "LAN9646",
1919 .num_vlans = 4096,
1920 .num_alus = 4096,
1921 .num_statics = 16,
1922 .cpu_ports = 0x7F, /* can be configured as cpu port */
1923 .port_cnt = 7, /* total physical port count */
1924 .port_nirqs = 4,
1925 .num_tx_queues = 4,
1926 .num_ipms = 8,
1927 .ops = &ksz9477_dev_ops,
1928 .phylink_mac_ops = &ksz9477_phylink_mac_ops,
1929 .phy_errata_9477 = true,
1930 .mib_names = ksz9477_mib_names,
1931 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1932 .reg_mib_cnt = MIB_COUNTER_NUM,
1933 .regs = ksz9477_regs,
1934 .masks = ksz9477_masks,
1935 .shifts = ksz9477_shifts,
1936 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1937 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1938 .supports_mii = {false, false, false, false,
1939 false, true, true},
1940 .supports_rmii = {false, false, false, false,
1941 false, true, true},
1942 .supports_rgmii = {false, false, false, false,
1943 false, true, true},
1944 .internal_phy = {true, true, true, true,
1945 true, false, false},
1946 .gbit_capable = {true, true, true, true, true, true, true},
1947 .wr_table = &ksz9477_register_set,
1948 .rd_table = &ksz9477_register_set,
1949 },
1950 };
1951 EXPORT_SYMBOL_GPL(ksz_switch_chips);
1952
ksz_lookup_info(unsigned int prod_num)1953 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
1954 {
1955 int i;
1956
1957 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
1958 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
1959
1960 if (chip->chip_id == prod_num)
1961 return chip;
1962 }
1963
1964 return NULL;
1965 }
1966
ksz_check_device_id(struct ksz_device * dev)1967 static int ksz_check_device_id(struct ksz_device *dev)
1968 {
1969 const struct ksz_chip_data *expected_chip_data;
1970 u32 expected_chip_id;
1971
1972 if (dev->pdata) {
1973 expected_chip_id = dev->pdata->chip_id;
1974 expected_chip_data = ksz_lookup_info(expected_chip_id);
1975 if (WARN_ON(!expected_chip_data))
1976 return -ENODEV;
1977 } else {
1978 expected_chip_data = of_device_get_match_data(dev->dev);
1979 expected_chip_id = expected_chip_data->chip_id;
1980 }
1981
1982 if (expected_chip_id != dev->chip_id) {
1983 dev_err(dev->dev,
1984 "Device tree specifies chip %s but found %s, please fix it!\n",
1985 expected_chip_data->dev_name, dev->info->dev_name);
1986 return -ENODEV;
1987 }
1988
1989 return 0;
1990 }
1991
ksz_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1992 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
1993 struct phylink_config *config)
1994 {
1995 struct ksz_device *dev = ds->priv;
1996
1997 if (dev->info->supports_mii[port])
1998 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1999
2000 if (dev->info->supports_rmii[port])
2001 __set_bit(PHY_INTERFACE_MODE_RMII,
2002 config->supported_interfaces);
2003
2004 if (dev->info->supports_rgmii[port])
2005 phy_interface_set_rgmii(config->supported_interfaces);
2006
2007 if (dev->info->internal_phy[port]) {
2008 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
2009 config->supported_interfaces);
2010 /* Compatibility for phylib's default interface type when the
2011 * phy-mode property is absent
2012 */
2013 __set_bit(PHY_INTERFACE_MODE_GMII,
2014 config->supported_interfaces);
2015 }
2016
2017 if (dev->dev_ops->get_caps)
2018 dev->dev_ops->get_caps(dev, port, config);
2019 }
2020
ksz_r_mib_stats64(struct ksz_device * dev,int port)2021 void ksz_r_mib_stats64(struct ksz_device *dev, int port)
2022 {
2023 struct ethtool_pause_stats *pstats;
2024 struct rtnl_link_stats64 *stats;
2025 struct ksz_stats_raw *raw;
2026 struct ksz_port_mib *mib;
2027 int ret;
2028
2029 mib = &dev->ports[port].mib;
2030 stats = &mib->stats64;
2031 pstats = &mib->pause_stats;
2032 raw = (struct ksz_stats_raw *)mib->counters;
2033
2034 spin_lock(&mib->stats64_lock);
2035
2036 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
2037 raw->rx_pause;
2038 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
2039 raw->tx_pause;
2040
2041 /* HW counters are counting bytes + FCS which is not acceptable
2042 * for rtnl_link_stats64 interface
2043 */
2044 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
2045 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
2046
2047 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
2048 raw->rx_oversize;
2049
2050 stats->rx_crc_errors = raw->rx_crc_err;
2051 stats->rx_frame_errors = raw->rx_align_err;
2052 stats->rx_dropped = raw->rx_discards;
2053 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2054 stats->rx_frame_errors + stats->rx_dropped;
2055
2056 stats->tx_window_errors = raw->tx_late_col;
2057 stats->tx_fifo_errors = raw->tx_discards;
2058 stats->tx_aborted_errors = raw->tx_exc_col;
2059 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
2060 stats->tx_aborted_errors;
2061
2062 stats->multicast = raw->rx_mcast;
2063 stats->collisions = raw->tx_total_col;
2064
2065 pstats->tx_pause_frames = raw->tx_pause;
2066 pstats->rx_pause_frames = raw->rx_pause;
2067
2068 spin_unlock(&mib->stats64_lock);
2069
2070 if (dev->info->phy_errata_9477) {
2071 ret = ksz9477_errata_monitor(dev, port, raw->tx_late_col);
2072 if (ret)
2073 dev_err(dev->dev, "Failed to monitor transmission halt\n");
2074 }
2075 }
2076
ksz88xx_r_mib_stats64(struct ksz_device * dev,int port)2077 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port)
2078 {
2079 struct ethtool_pause_stats *pstats;
2080 struct rtnl_link_stats64 *stats;
2081 struct ksz88xx_stats_raw *raw;
2082 struct ksz_port_mib *mib;
2083
2084 mib = &dev->ports[port].mib;
2085 stats = &mib->stats64;
2086 pstats = &mib->pause_stats;
2087 raw = (struct ksz88xx_stats_raw *)mib->counters;
2088
2089 spin_lock(&mib->stats64_lock);
2090
2091 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
2092 raw->rx_pause;
2093 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
2094 raw->tx_pause;
2095
2096 /* HW counters are counting bytes + FCS which is not acceptable
2097 * for rtnl_link_stats64 interface
2098 */
2099 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN;
2100 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN;
2101
2102 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
2103 raw->rx_oversize;
2104
2105 stats->rx_crc_errors = raw->rx_crc_err;
2106 stats->rx_frame_errors = raw->rx_align_err;
2107 stats->rx_dropped = raw->rx_discards;
2108 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2109 stats->rx_frame_errors + stats->rx_dropped;
2110
2111 stats->tx_window_errors = raw->tx_late_col;
2112 stats->tx_fifo_errors = raw->tx_discards;
2113 stats->tx_aborted_errors = raw->tx_exc_col;
2114 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
2115 stats->tx_aborted_errors;
2116
2117 stats->multicast = raw->rx_mcast;
2118 stats->collisions = raw->tx_total_col;
2119
2120 pstats->tx_pause_frames = raw->tx_pause;
2121 pstats->rx_pause_frames = raw->rx_pause;
2122
2123 spin_unlock(&mib->stats64_lock);
2124 }
2125
ksz_get_stats64(struct dsa_switch * ds,int port,struct rtnl_link_stats64 * s)2126 static void ksz_get_stats64(struct dsa_switch *ds, int port,
2127 struct rtnl_link_stats64 *s)
2128 {
2129 struct ksz_device *dev = ds->priv;
2130 struct ksz_port_mib *mib;
2131
2132 mib = &dev->ports[port].mib;
2133
2134 spin_lock(&mib->stats64_lock);
2135 memcpy(s, &mib->stats64, sizeof(*s));
2136 spin_unlock(&mib->stats64_lock);
2137 }
2138
ksz_get_pause_stats(struct dsa_switch * ds,int port,struct ethtool_pause_stats * pause_stats)2139 static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
2140 struct ethtool_pause_stats *pause_stats)
2141 {
2142 struct ksz_device *dev = ds->priv;
2143 struct ksz_port_mib *mib;
2144
2145 mib = &dev->ports[port].mib;
2146
2147 spin_lock(&mib->stats64_lock);
2148 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
2149 spin_unlock(&mib->stats64_lock);
2150 }
2151
ksz_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * buf)2152 static void ksz_get_strings(struct dsa_switch *ds, int port,
2153 u32 stringset, uint8_t *buf)
2154 {
2155 struct ksz_device *dev = ds->priv;
2156 int i;
2157
2158 if (stringset != ETH_SS_STATS)
2159 return;
2160
2161 for (i = 0; i < dev->info->mib_cnt; i++)
2162 ethtool_puts(&buf, dev->info->mib_names[i].string);
2163 }
2164
2165 /**
2166 * ksz_update_port_member - Adjust port forwarding rules based on STP state and
2167 * isolation settings.
2168 * @dev: A pointer to the struct ksz_device representing the device.
2169 * @port: The port number to adjust.
2170 *
2171 * This function dynamically adjusts the port membership configuration for a
2172 * specified port and other device ports, based on Spanning Tree Protocol (STP)
2173 * states and port isolation settings. Each port, including the CPU port, has a
2174 * membership register, represented as a bitfield, where each bit corresponds
2175 * to a port number. A set bit indicates permission to forward frames to that
2176 * port. This function iterates over all ports, updating the membership register
2177 * to reflect current forwarding permissions:
2178 *
2179 * 1. Forwards frames only to ports that are part of the same bridge group and
2180 * in the BR_STATE_FORWARDING state.
2181 * 2. Takes into account the isolation status of ports; ports in the
2182 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward
2183 * frames to each other, even if they are in the same bridge group.
2184 * 3. Ensures that the CPU port is included in the membership based on its
2185 * upstream port configuration, allowing for management and control traffic
2186 * to flow as required.
2187 */
ksz_update_port_member(struct ksz_device * dev,int port)2188 static void ksz_update_port_member(struct ksz_device *dev, int port)
2189 {
2190 struct ksz_port *p = &dev->ports[port];
2191 struct dsa_switch *ds = dev->ds;
2192 u8 port_member = 0, cpu_port;
2193 const struct dsa_port *dp;
2194 int i, j;
2195
2196 if (!dsa_is_user_port(ds, port))
2197 return;
2198
2199 dp = dsa_to_port(ds, port);
2200 cpu_port = BIT(dsa_upstream_port(ds, port));
2201
2202 for (i = 0; i < ds->num_ports; i++) {
2203 const struct dsa_port *other_dp = dsa_to_port(ds, i);
2204 struct ksz_port *other_p = &dev->ports[i];
2205 u8 val = 0;
2206
2207 if (!dsa_is_user_port(ds, i))
2208 continue;
2209 if (port == i)
2210 continue;
2211 if (!dsa_port_bridge_same(dp, other_dp))
2212 continue;
2213 if (other_p->stp_state != BR_STATE_FORWARDING)
2214 continue;
2215
2216 /* At this point we know that "port" and "other" port [i] are in
2217 * the same bridge group and that "other" port [i] is in
2218 * forwarding stp state. If "port" is also in forwarding stp
2219 * state, we can allow forwarding from port [port] to port [i].
2220 * Except if both ports are isolated.
2221 */
2222 if (p->stp_state == BR_STATE_FORWARDING &&
2223 !(p->isolated && other_p->isolated)) {
2224 val |= BIT(port);
2225 port_member |= BIT(i);
2226 }
2227
2228 /* Retain port [i]'s relationship to other ports than [port] */
2229 for (j = 0; j < ds->num_ports; j++) {
2230 const struct dsa_port *third_dp;
2231 struct ksz_port *third_p;
2232
2233 if (j == i)
2234 continue;
2235 if (j == port)
2236 continue;
2237 if (!dsa_is_user_port(ds, j))
2238 continue;
2239 third_p = &dev->ports[j];
2240 if (third_p->stp_state != BR_STATE_FORWARDING)
2241 continue;
2242
2243 third_dp = dsa_to_port(ds, j);
2244
2245 /* Now we updating relation of the "other" port [i] to
2246 * the "third" port [j]. We already know that "other"
2247 * port [i] is in forwarding stp state and that "third"
2248 * port [j] is in forwarding stp state too.
2249 * We need to check if "other" port [i] and "third" port
2250 * [j] are in the same bridge group and not isolated
2251 * before allowing forwarding from port [i] to port [j].
2252 */
2253 if (dsa_port_bridge_same(other_dp, third_dp) &&
2254 !(other_p->isolated && third_p->isolated))
2255 val |= BIT(j);
2256 }
2257
2258 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
2259 }
2260
2261 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
2262 }
2263
ksz_sw_mdio_read(struct mii_bus * bus,int addr,int regnum)2264 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
2265 {
2266 struct ksz_device *dev = bus->priv;
2267 u16 val;
2268 int ret;
2269
2270 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val);
2271 if (ret < 0)
2272 return ret;
2273
2274 return val;
2275 }
2276
ksz_sw_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)2277 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
2278 u16 val)
2279 {
2280 struct ksz_device *dev = bus->priv;
2281
2282 return dev->dev_ops->w_phy(dev, addr, regnum, val);
2283 }
2284
2285 /**
2286 * ksz_parent_mdio_read - Read data from a PHY register on the parent MDIO bus.
2287 * @bus: MDIO bus structure.
2288 * @addr: PHY address on the parent MDIO bus.
2289 * @regnum: Register number to read.
2290 *
2291 * This function provides a direct read operation on the parent MDIO bus for
2292 * accessing PHY registers. By bypassing SPI or I2C, it uses the parent MDIO bus
2293 * to retrieve data from the PHY registers at the specified address and register
2294 * number.
2295 *
2296 * Return: Value of the PHY register, or a negative error code on failure.
2297 */
ksz_parent_mdio_read(struct mii_bus * bus,int addr,int regnum)2298 static int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum)
2299 {
2300 struct ksz_device *dev = bus->priv;
2301
2302 return mdiobus_read_nested(dev->parent_mdio_bus, addr, regnum);
2303 }
2304
2305 /**
2306 * ksz_parent_mdio_write - Write data to a PHY register on the parent MDIO bus.
2307 * @bus: MDIO bus structure.
2308 * @addr: PHY address on the parent MDIO bus.
2309 * @regnum: Register number to write to.
2310 * @val: Value to write to the PHY register.
2311 *
2312 * This function provides a direct write operation on the parent MDIO bus for
2313 * accessing PHY registers. Bypassing SPI or I2C, it uses the parent MDIO bus
2314 * to modify the PHY register values at the specified address.
2315 *
2316 * Return: 0 on success, or a negative error code on failure.
2317 */
ksz_parent_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)2318 static int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum,
2319 u16 val)
2320 {
2321 struct ksz_device *dev = bus->priv;
2322
2323 return mdiobus_write_nested(dev->parent_mdio_bus, addr, regnum, val);
2324 }
2325
2326 /**
2327 * ksz_phy_addr_to_port - Map a PHY address to the corresponding switch port.
2328 * @dev: Pointer to device structure.
2329 * @addr: PHY address to map to a port.
2330 *
2331 * This function finds the corresponding switch port for a given PHY address by
2332 * iterating over all user ports on the device. It checks if a port's PHY
2333 * address in `phy_addr_map` matches the specified address and if the port
2334 * contains an internal PHY. If a match is found, the index of the port is
2335 * returned.
2336 *
2337 * Return: Port index on success, or -EINVAL if no matching port is found.
2338 */
ksz_phy_addr_to_port(struct ksz_device * dev,int addr)2339 static int ksz_phy_addr_to_port(struct ksz_device *dev, int addr)
2340 {
2341 struct dsa_switch *ds = dev->ds;
2342 struct dsa_port *dp;
2343
2344 dsa_switch_for_each_user_port(dp, ds) {
2345 if (dev->info->internal_phy[dp->index] &&
2346 dev->phy_addr_map[dp->index] == addr)
2347 return dp->index;
2348 }
2349
2350 return -EINVAL;
2351 }
2352
2353 /**
2354 * ksz_irq_phy_setup - Configure IRQs for PHYs in the KSZ device.
2355 * @dev: Pointer to the KSZ device structure.
2356 *
2357 * Sets up IRQs for each active PHY connected to the KSZ switch by mapping the
2358 * appropriate IRQs for each PHY and assigning them to the `user_mii_bus` in
2359 * the DSA switch structure. Each IRQ is mapped based on the port's IRQ domain.
2360 *
2361 * Return: 0 on success, or a negative error code on failure.
2362 */
ksz_irq_phy_setup(struct ksz_device * dev)2363 static int ksz_irq_phy_setup(struct ksz_device *dev)
2364 {
2365 struct dsa_switch *ds = dev->ds;
2366 int phy, port;
2367 int irq;
2368 int ret;
2369
2370 for (phy = 0; phy < PHY_MAX_ADDR; phy++) {
2371 if (BIT(phy) & ds->phys_mii_mask) {
2372 port = ksz_phy_addr_to_port(dev, phy);
2373 if (port < 0) {
2374 ret = port;
2375 goto out;
2376 }
2377
2378 irq = irq_find_mapping(dev->ports[port].pirq.domain,
2379 PORT_SRC_PHY_INT);
2380 if (irq < 0) {
2381 ret = irq;
2382 goto out;
2383 }
2384 ds->user_mii_bus->irq[phy] = irq;
2385 }
2386 }
2387 return 0;
2388 out:
2389 while (phy--)
2390 if (BIT(phy) & ds->phys_mii_mask)
2391 irq_dispose_mapping(ds->user_mii_bus->irq[phy]);
2392
2393 return ret;
2394 }
2395
2396 /**
2397 * ksz_irq_phy_free - Release IRQ mappings for PHYs in the KSZ device.
2398 * @dev: Pointer to the KSZ device structure.
2399 *
2400 * Releases any IRQ mappings previously assigned to active PHYs in the KSZ
2401 * switch by disposing of each mapped IRQ in the `user_mii_bus` structure.
2402 */
ksz_irq_phy_free(struct ksz_device * dev)2403 static void ksz_irq_phy_free(struct ksz_device *dev)
2404 {
2405 struct dsa_switch *ds = dev->ds;
2406 int phy;
2407
2408 for (phy = 0; phy < PHY_MAX_ADDR; phy++)
2409 if (BIT(phy) & ds->phys_mii_mask)
2410 irq_dispose_mapping(ds->user_mii_bus->irq[phy]);
2411 }
2412
2413 /**
2414 * ksz_parse_dt_phy_config - Parse and validate PHY configuration from DT
2415 * @dev: pointer to the KSZ device structure
2416 * @bus: pointer to the MII bus structure
2417 * @mdio_np: pointer to the MDIO node in the device tree
2418 *
2419 * This function parses and validates PHY configurations for each user port
2420 * defined in the device tree for a KSZ switch device. It verifies that the
2421 * `phy-handle` properties are correctly set and that the internal PHYs match
2422 * expected addresses and parent nodes. Sets up the PHY mask in the MII bus if
2423 * all validations pass. Logs error messages for any mismatches or missing data.
2424 *
2425 * Return: 0 on success, or a negative error code on failure.
2426 */
ksz_parse_dt_phy_config(struct ksz_device * dev,struct mii_bus * bus,struct device_node * mdio_np)2427 static int ksz_parse_dt_phy_config(struct ksz_device *dev, struct mii_bus *bus,
2428 struct device_node *mdio_np)
2429 {
2430 struct device_node *phy_node, *phy_parent_node;
2431 bool phys_are_valid = true;
2432 struct dsa_port *dp;
2433 u32 phy_addr;
2434 int ret;
2435
2436 dsa_switch_for_each_user_port(dp, dev->ds) {
2437 if (!dev->info->internal_phy[dp->index])
2438 continue;
2439
2440 phy_node = of_parse_phandle(dp->dn, "phy-handle", 0);
2441 if (!phy_node) {
2442 dev_err(dev->dev, "failed to parse phy-handle for port %d.\n",
2443 dp->index);
2444 phys_are_valid = false;
2445 continue;
2446 }
2447
2448 phy_parent_node = of_get_parent(phy_node);
2449 if (!phy_parent_node) {
2450 dev_err(dev->dev, "failed to get PHY-parent node for port %d\n",
2451 dp->index);
2452 phys_are_valid = false;
2453 } else if (phy_parent_node != mdio_np) {
2454 dev_err(dev->dev, "PHY-parent node mismatch for port %d, expected %pOF, got %pOF\n",
2455 dp->index, mdio_np, phy_parent_node);
2456 phys_are_valid = false;
2457 } else {
2458 ret = of_property_read_u32(phy_node, "reg", &phy_addr);
2459 if (ret < 0) {
2460 dev_err(dev->dev, "failed to read PHY address for port %d. Error %d\n",
2461 dp->index, ret);
2462 phys_are_valid = false;
2463 } else if (phy_addr != dev->phy_addr_map[dp->index]) {
2464 dev_err(dev->dev, "PHY address mismatch for port %d, expected 0x%x, got 0x%x\n",
2465 dp->index, dev->phy_addr_map[dp->index],
2466 phy_addr);
2467 phys_are_valid = false;
2468 } else {
2469 bus->phy_mask |= BIT(phy_addr);
2470 }
2471 }
2472
2473 of_node_put(phy_node);
2474 of_node_put(phy_parent_node);
2475 }
2476
2477 if (!phys_are_valid)
2478 return -EINVAL;
2479
2480 return 0;
2481 }
2482
2483 /**
2484 * ksz_mdio_register - Register and configure the MDIO bus for the KSZ device.
2485 * @dev: Pointer to the KSZ device structure.
2486 *
2487 * This function sets up and registers an MDIO bus for the KSZ switch device,
2488 * allowing access to its internal PHYs. If the device supports side MDIO,
2489 * the function will configure the external MDIO controller specified by the
2490 * "mdio-parent-bus" device tree property to directly manage internal PHYs.
2491 * Otherwise, SPI or I2C access is set up for PHY access.
2492 *
2493 * Return: 0 on success, or a negative error code on failure.
2494 */
ksz_mdio_register(struct ksz_device * dev)2495 static int ksz_mdio_register(struct ksz_device *dev)
2496 {
2497 struct device_node *parent_bus_node;
2498 struct mii_bus *parent_bus = NULL;
2499 struct dsa_switch *ds = dev->ds;
2500 struct device_node *mdio_np;
2501 struct mii_bus *bus;
2502 int ret, i;
2503
2504 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio");
2505 if (!mdio_np)
2506 return 0;
2507
2508 parent_bus_node = of_parse_phandle(mdio_np, "mdio-parent-bus", 0);
2509 if (parent_bus_node && !dev->info->phy_side_mdio_supported) {
2510 dev_err(dev->dev, "Side MDIO bus is not supported for this HW, ignoring 'mdio-parent-bus' property.\n");
2511 ret = -EINVAL;
2512
2513 goto put_mdio_node;
2514 } else if (parent_bus_node) {
2515 parent_bus = of_mdio_find_bus(parent_bus_node);
2516 if (!parent_bus) {
2517 ret = -EPROBE_DEFER;
2518
2519 goto put_mdio_node;
2520 }
2521
2522 dev->parent_mdio_bus = parent_bus;
2523 }
2524
2525 bus = devm_mdiobus_alloc(ds->dev);
2526 if (!bus) {
2527 ret = -ENOMEM;
2528 goto put_mdio_node;
2529 }
2530
2531 if (dev->dev_ops->mdio_bus_preinit) {
2532 ret = dev->dev_ops->mdio_bus_preinit(dev, !!parent_bus);
2533 if (ret)
2534 goto put_mdio_node;
2535 }
2536
2537 if (dev->dev_ops->create_phy_addr_map) {
2538 ret = dev->dev_ops->create_phy_addr_map(dev, !!parent_bus);
2539 if (ret)
2540 goto put_mdio_node;
2541 } else {
2542 for (i = 0; i < dev->info->port_cnt; i++)
2543 dev->phy_addr_map[i] = i;
2544 }
2545
2546 bus->priv = dev;
2547 if (parent_bus) {
2548 bus->read = ksz_parent_mdio_read;
2549 bus->write = ksz_parent_mdio_write;
2550 bus->name = "KSZ side MDIO";
2551 snprintf(bus->id, MII_BUS_ID_SIZE, "ksz-side-mdio-%d",
2552 ds->index);
2553 } else {
2554 bus->read = ksz_sw_mdio_read;
2555 bus->write = ksz_sw_mdio_write;
2556 bus->name = "ksz user smi";
2557 if (ds->dst->index != 0) {
2558 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d-%d", ds->dst->index, ds->index);
2559 } else {
2560 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index);
2561 }
2562 }
2563
2564 ret = ksz_parse_dt_phy_config(dev, bus, mdio_np);
2565 if (ret)
2566 goto put_mdio_node;
2567
2568 ds->phys_mii_mask = bus->phy_mask;
2569 bus->parent = ds->dev;
2570
2571 ds->user_mii_bus = bus;
2572
2573 if (dev->irq > 0) {
2574 ret = ksz_irq_phy_setup(dev);
2575 if (ret)
2576 goto put_mdio_node;
2577 }
2578
2579 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np);
2580 if (ret) {
2581 dev_err(ds->dev, "unable to register MDIO bus %s\n",
2582 bus->id);
2583 if (dev->irq > 0)
2584 ksz_irq_phy_free(dev);
2585 }
2586
2587 put_mdio_node:
2588 of_node_put(mdio_np);
2589 of_node_put(parent_bus_node);
2590
2591 return ret;
2592 }
2593
ksz_irq_mask(struct irq_data * d)2594 static void ksz_irq_mask(struct irq_data *d)
2595 {
2596 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2597
2598 kirq->masked |= BIT(d->hwirq);
2599 }
2600
ksz_irq_unmask(struct irq_data * d)2601 static void ksz_irq_unmask(struct irq_data *d)
2602 {
2603 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2604
2605 kirq->masked &= ~BIT(d->hwirq);
2606 }
2607
ksz_irq_bus_lock(struct irq_data * d)2608 static void ksz_irq_bus_lock(struct irq_data *d)
2609 {
2610 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2611
2612 mutex_lock(&kirq->dev->lock_irq);
2613 }
2614
ksz_irq_bus_sync_unlock(struct irq_data * d)2615 static void ksz_irq_bus_sync_unlock(struct irq_data *d)
2616 {
2617 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
2618 struct ksz_device *dev = kirq->dev;
2619 int ret;
2620
2621 ret = ksz_write8(dev, kirq->reg_mask, kirq->masked);
2622 if (ret)
2623 dev_err(dev->dev, "failed to change IRQ mask\n");
2624
2625 mutex_unlock(&dev->lock_irq);
2626 }
2627
2628 static const struct irq_chip ksz_irq_chip = {
2629 .name = "ksz-irq",
2630 .irq_mask = ksz_irq_mask,
2631 .irq_unmask = ksz_irq_unmask,
2632 .irq_bus_lock = ksz_irq_bus_lock,
2633 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock,
2634 };
2635
ksz_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)2636 static int ksz_irq_domain_map(struct irq_domain *d,
2637 unsigned int irq, irq_hw_number_t hwirq)
2638 {
2639 irq_set_chip_data(irq, d->host_data);
2640 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq);
2641 irq_set_noprobe(irq);
2642
2643 return 0;
2644 }
2645
2646 static const struct irq_domain_ops ksz_irq_domain_ops = {
2647 .map = ksz_irq_domain_map,
2648 .xlate = irq_domain_xlate_twocell,
2649 };
2650
ksz_irq_free(struct ksz_irq * kirq)2651 static void ksz_irq_free(struct ksz_irq *kirq)
2652 {
2653 int irq, virq;
2654
2655 free_irq(kirq->irq_num, kirq);
2656
2657 for (irq = 0; irq < kirq->nirqs; irq++) {
2658 virq = irq_find_mapping(kirq->domain, irq);
2659 irq_dispose_mapping(virq);
2660 }
2661
2662 irq_domain_remove(kirq->domain);
2663 }
2664
ksz_irq_thread_fn(int irq,void * dev_id)2665 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id)
2666 {
2667 struct ksz_irq *kirq = dev_id;
2668 unsigned int nhandled = 0;
2669 struct ksz_device *dev;
2670 unsigned int sub_irq;
2671 u8 data;
2672 int ret;
2673 u8 n;
2674
2675 dev = kirq->dev;
2676
2677 /* Read interrupt status register */
2678 ret = ksz_read8(dev, kirq->reg_status, &data);
2679 if (ret)
2680 goto out;
2681
2682 for (n = 0; n < kirq->nirqs; ++n) {
2683 if (data & BIT(n)) {
2684 sub_irq = irq_find_mapping(kirq->domain, n);
2685 handle_nested_irq(sub_irq);
2686 ++nhandled;
2687 }
2688 }
2689 out:
2690 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
2691 }
2692
ksz_irq_common_setup(struct ksz_device * dev,struct ksz_irq * kirq)2693 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq)
2694 {
2695 int ret, n;
2696
2697 kirq->dev = dev;
2698 kirq->masked = ~0;
2699
2700 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0,
2701 &ksz_irq_domain_ops, kirq);
2702 if (!kirq->domain)
2703 return -ENOMEM;
2704
2705 for (n = 0; n < kirq->nirqs; n++)
2706 irq_create_mapping(kirq->domain, n);
2707
2708 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn,
2709 IRQF_ONESHOT, kirq->name, kirq);
2710 if (ret)
2711 goto out;
2712
2713 return 0;
2714
2715 out:
2716 ksz_irq_free(kirq);
2717
2718 return ret;
2719 }
2720
ksz_girq_setup(struct ksz_device * dev)2721 static int ksz_girq_setup(struct ksz_device *dev)
2722 {
2723 struct ksz_irq *girq = &dev->girq;
2724
2725 girq->nirqs = dev->info->port_cnt;
2726 girq->reg_mask = REG_SW_PORT_INT_MASK__1;
2727 girq->reg_status = REG_SW_PORT_INT_STATUS__1;
2728 snprintf(girq->name, sizeof(girq->name), "global_port_irq");
2729
2730 girq->irq_num = dev->irq;
2731
2732 return ksz_irq_common_setup(dev, girq);
2733 }
2734
ksz_pirq_setup(struct ksz_device * dev,u8 p)2735 static int ksz_pirq_setup(struct ksz_device *dev, u8 p)
2736 {
2737 struct ksz_irq *pirq = &dev->ports[p].pirq;
2738
2739 pirq->nirqs = dev->info->port_nirqs;
2740 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
2741 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
2742 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p);
2743
2744 pirq->irq_num = irq_find_mapping(dev->girq.domain, p);
2745 if (pirq->irq_num < 0)
2746 return pirq->irq_num;
2747
2748 return ksz_irq_common_setup(dev, pirq);
2749 }
2750
2751 static int ksz_parse_drive_strength(struct ksz_device *dev);
2752
ksz_setup(struct dsa_switch * ds)2753 static int ksz_setup(struct dsa_switch *ds)
2754 {
2755 struct ksz_device *dev = ds->priv;
2756 struct dsa_port *dp;
2757 struct ksz_port *p;
2758 const u16 *regs;
2759 int ret;
2760
2761 regs = dev->info->regs;
2762
2763 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
2764 dev->info->num_vlans, GFP_KERNEL);
2765 if (!dev->vlan_cache)
2766 return -ENOMEM;
2767
2768 ret = dev->dev_ops->reset(dev);
2769 if (ret) {
2770 dev_err(ds->dev, "failed to reset switch\n");
2771 return ret;
2772 }
2773
2774 ret = ksz_parse_drive_strength(dev);
2775 if (ret)
2776 return ret;
2777
2778 /* set broadcast storm protection 10% rate */
2779 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL],
2780 BROADCAST_STORM_RATE,
2781 (BROADCAST_STORM_VALUE *
2782 BROADCAST_STORM_PROT_RATE) / 100);
2783
2784 dev->dev_ops->config_cpu_port(ds);
2785
2786 dev->dev_ops->enable_stp_addr(dev);
2787
2788 ds->num_tx_queues = dev->info->num_tx_queues;
2789
2790 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL],
2791 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
2792
2793 ksz_init_mib_timer(dev);
2794
2795 ds->configure_vlan_while_not_filtering = false;
2796 ds->dscp_prio_mapping_is_global = true;
2797
2798 if (dev->dev_ops->setup) {
2799 ret = dev->dev_ops->setup(ds);
2800 if (ret)
2801 return ret;
2802 }
2803
2804 /* Start with learning disabled on standalone user ports, and enabled
2805 * on the CPU port. In lack of other finer mechanisms, learning on the
2806 * CPU port will avoid flooding bridge local addresses on the network
2807 * in some cases.
2808 */
2809 p = &dev->ports[dev->cpu_port];
2810 p->learning = true;
2811
2812 if (dev->irq > 0) {
2813 ret = ksz_girq_setup(dev);
2814 if (ret)
2815 return ret;
2816
2817 dsa_switch_for_each_user_port(dp, dev->ds) {
2818 ret = ksz_pirq_setup(dev, dp->index);
2819 if (ret)
2820 goto out_girq;
2821
2822 if (dev->info->ptp_capable) {
2823 ret = ksz_ptp_irq_setup(ds, dp->index);
2824 if (ret)
2825 goto out_pirq;
2826 }
2827 }
2828 }
2829
2830 if (dev->info->ptp_capable) {
2831 ret = ksz_ptp_clock_register(ds);
2832 if (ret) {
2833 dev_err(dev->dev, "Failed to register PTP clock: %d\n",
2834 ret);
2835 goto out_ptpirq;
2836 }
2837 }
2838
2839 ret = ksz_mdio_register(dev);
2840 if (ret < 0) {
2841 dev_err(dev->dev, "failed to register the mdio");
2842 goto out_ptp_clock_unregister;
2843 }
2844
2845 ret = ksz_dcb_init(dev);
2846 if (ret)
2847 goto out_ptp_clock_unregister;
2848
2849 /* start switch */
2850 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL],
2851 SW_START, SW_START);
2852
2853 return 0;
2854
2855 out_ptp_clock_unregister:
2856 if (dev->info->ptp_capable)
2857 ksz_ptp_clock_unregister(ds);
2858 out_ptpirq:
2859 if (dev->irq > 0 && dev->info->ptp_capable)
2860 dsa_switch_for_each_user_port(dp, dev->ds)
2861 ksz_ptp_irq_free(ds, dp->index);
2862 out_pirq:
2863 if (dev->irq > 0)
2864 dsa_switch_for_each_user_port(dp, dev->ds)
2865 ksz_irq_free(&dev->ports[dp->index].pirq);
2866 out_girq:
2867 if (dev->irq > 0)
2868 ksz_irq_free(&dev->girq);
2869
2870 return ret;
2871 }
2872
ksz_teardown(struct dsa_switch * ds)2873 static void ksz_teardown(struct dsa_switch *ds)
2874 {
2875 struct ksz_device *dev = ds->priv;
2876 struct dsa_port *dp;
2877
2878 if (dev->info->ptp_capable)
2879 ksz_ptp_clock_unregister(ds);
2880
2881 if (dev->irq > 0) {
2882 dsa_switch_for_each_user_port(dp, dev->ds) {
2883 if (dev->info->ptp_capable)
2884 ksz_ptp_irq_free(ds, dp->index);
2885
2886 ksz_irq_free(&dev->ports[dp->index].pirq);
2887 }
2888
2889 ksz_irq_free(&dev->girq);
2890 }
2891
2892 if (dev->dev_ops->teardown)
2893 dev->dev_ops->teardown(ds);
2894 }
2895
port_r_cnt(struct ksz_device * dev,int port)2896 static void port_r_cnt(struct ksz_device *dev, int port)
2897 {
2898 struct ksz_port_mib *mib = &dev->ports[port].mib;
2899 u64 *dropped;
2900
2901 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
2902 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
2903 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
2904 &mib->counters[mib->cnt_ptr]);
2905 ++mib->cnt_ptr;
2906 }
2907
2908 /* last one in storage */
2909 dropped = &mib->counters[dev->info->mib_cnt];
2910
2911 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
2912 while (mib->cnt_ptr < dev->info->mib_cnt) {
2913 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
2914 dropped, &mib->counters[mib->cnt_ptr]);
2915 ++mib->cnt_ptr;
2916 }
2917 mib->cnt_ptr = 0;
2918 }
2919
ksz_mib_read_work(struct work_struct * work)2920 static void ksz_mib_read_work(struct work_struct *work)
2921 {
2922 struct ksz_device *dev = container_of(work, struct ksz_device,
2923 mib_read.work);
2924 struct ksz_port_mib *mib;
2925 struct ksz_port *p;
2926 int i;
2927
2928 for (i = 0; i < dev->info->port_cnt; i++) {
2929 if (dsa_is_unused_port(dev->ds, i))
2930 continue;
2931
2932 p = &dev->ports[i];
2933 mib = &p->mib;
2934 mutex_lock(&mib->cnt_mutex);
2935
2936 /* Only read MIB counters when the port is told to do.
2937 * If not, read only dropped counters when link is not up.
2938 */
2939 if (!p->read) {
2940 const struct dsa_port *dp = dsa_to_port(dev->ds, i);
2941
2942 if (!netif_carrier_ok(dp->user))
2943 mib->cnt_ptr = dev->info->reg_mib_cnt;
2944 }
2945 port_r_cnt(dev, i);
2946 p->read = false;
2947
2948 if (dev->dev_ops->r_mib_stat64)
2949 dev->dev_ops->r_mib_stat64(dev, i);
2950
2951 mutex_unlock(&mib->cnt_mutex);
2952 }
2953
2954 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
2955 }
2956
ksz_init_mib_timer(struct ksz_device * dev)2957 void ksz_init_mib_timer(struct ksz_device *dev)
2958 {
2959 int i;
2960
2961 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
2962
2963 for (i = 0; i < dev->info->port_cnt; i++) {
2964 struct ksz_port_mib *mib = &dev->ports[i].mib;
2965
2966 dev->dev_ops->port_init_cnt(dev, i);
2967
2968 mib->cnt_ptr = 0;
2969 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
2970 }
2971 }
2972
ksz_phy_read16(struct dsa_switch * ds,int addr,int reg)2973 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
2974 {
2975 struct ksz_device *dev = ds->priv;
2976 u16 val = 0xffff;
2977 int ret;
2978
2979 ret = dev->dev_ops->r_phy(dev, addr, reg, &val);
2980 if (ret)
2981 return ret;
2982
2983 return val;
2984 }
2985
ksz_phy_write16(struct dsa_switch * ds,int addr,int reg,u16 val)2986 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
2987 {
2988 struct ksz_device *dev = ds->priv;
2989 int ret;
2990
2991 ret = dev->dev_ops->w_phy(dev, addr, reg, val);
2992 if (ret)
2993 return ret;
2994
2995 return 0;
2996 }
2997
ksz_get_phy_flags(struct dsa_switch * ds,int port)2998 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
2999 {
3000 struct ksz_device *dev = ds->priv;
3001
3002 switch (dev->chip_id) {
3003 case KSZ88X3_CHIP_ID:
3004 /* Silicon Errata Sheet (DS80000830A):
3005 * Port 1 does not work with LinkMD Cable-Testing.
3006 * Port 1 does not respond to received PAUSE control frames.
3007 */
3008 if (!port)
3009 return MICREL_KSZ8_P1_ERRATA;
3010 break;
3011 case KSZ8567_CHIP_ID:
3012 /* KSZ8567R Errata DS80000752C Module 4 */
3013 case KSZ8765_CHIP_ID:
3014 case KSZ8794_CHIP_ID:
3015 case KSZ8795_CHIP_ID:
3016 /* KSZ879x/KSZ877x/KSZ876x Errata DS80000687C Module 2 */
3017 case KSZ9477_CHIP_ID:
3018 /* KSZ9477S Errata DS80000754A Module 4 */
3019 case KSZ9567_CHIP_ID:
3020 /* KSZ9567S Errata DS80000756A Module 4 */
3021 case KSZ9896_CHIP_ID:
3022 /* KSZ9896C Errata DS80000757A Module 3 */
3023 case KSZ9897_CHIP_ID:
3024 case LAN9646_CHIP_ID:
3025 /* KSZ9897R Errata DS80000758C Module 4 */
3026 /* Energy Efficient Ethernet (EEE) feature select must be manually disabled
3027 * The EEE feature is enabled by default, but it is not fully
3028 * operational. It must be manually disabled through register
3029 * controls. If not disabled, the PHY ports can auto-negotiate
3030 * to enable EEE, and this feature can cause link drops when
3031 * linked to another device supporting EEE.
3032 *
3033 * The same item appears in the errata for all switches above.
3034 */
3035 return MICREL_NO_EEE;
3036 }
3037
3038 return 0;
3039 }
3040
ksz_phylink_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)3041 static void ksz_phylink_mac_link_down(struct phylink_config *config,
3042 unsigned int mode,
3043 phy_interface_t interface)
3044 {
3045 struct dsa_port *dp = dsa_phylink_to_port(config);
3046 struct ksz_device *dev = dp->ds->priv;
3047
3048 /* Read all MIB counters when the link is going down. */
3049 dev->ports[dp->index].read = true;
3050 /* timer started */
3051 if (dev->mib_read_interval)
3052 schedule_delayed_work(&dev->mib_read, 0);
3053 }
3054
ksz_sset_count(struct dsa_switch * ds,int port,int sset)3055 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
3056 {
3057 struct ksz_device *dev = ds->priv;
3058
3059 if (sset != ETH_SS_STATS)
3060 return 0;
3061
3062 return dev->info->mib_cnt;
3063 }
3064
ksz_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * buf)3065 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
3066 uint64_t *buf)
3067 {
3068 const struct dsa_port *dp = dsa_to_port(ds, port);
3069 struct ksz_device *dev = ds->priv;
3070 struct ksz_port_mib *mib;
3071
3072 mib = &dev->ports[port].mib;
3073 mutex_lock(&mib->cnt_mutex);
3074
3075 /* Only read dropped counters if no link. */
3076 if (!netif_carrier_ok(dp->user))
3077 mib->cnt_ptr = dev->info->reg_mib_cnt;
3078 port_r_cnt(dev, port);
3079 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
3080 mutex_unlock(&mib->cnt_mutex);
3081 }
3082
ksz_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)3083 static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
3084 struct dsa_bridge bridge,
3085 bool *tx_fwd_offload,
3086 struct netlink_ext_ack *extack)
3087 {
3088 /* port_stp_state_set() will be called after to put the port in
3089 * appropriate state so there is no need to do anything.
3090 */
3091
3092 return 0;
3093 }
3094
ksz_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)3095 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
3096 struct dsa_bridge bridge)
3097 {
3098 /* port_stp_state_set() will be called after to put the port in
3099 * forwarding state so there is no need to do anything.
3100 */
3101 }
3102
ksz_port_fast_age(struct dsa_switch * ds,int port)3103 static void ksz_port_fast_age(struct dsa_switch *ds, int port)
3104 {
3105 struct ksz_device *dev = ds->priv;
3106
3107 dev->dev_ops->flush_dyn_mac_table(dev, port);
3108 }
3109
ksz_set_ageing_time(struct dsa_switch * ds,unsigned int msecs)3110 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
3111 {
3112 struct ksz_device *dev = ds->priv;
3113
3114 if (!dev->dev_ops->set_ageing_time)
3115 return -EOPNOTSUPP;
3116
3117 return dev->dev_ops->set_ageing_time(dev, msecs);
3118 }
3119
ksz_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)3120 static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
3121 const unsigned char *addr, u16 vid,
3122 struct dsa_db db)
3123 {
3124 struct ksz_device *dev = ds->priv;
3125
3126 if (!dev->dev_ops->fdb_add)
3127 return -EOPNOTSUPP;
3128
3129 return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
3130 }
3131
ksz_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)3132 static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
3133 const unsigned char *addr,
3134 u16 vid, struct dsa_db db)
3135 {
3136 struct ksz_device *dev = ds->priv;
3137
3138 if (!dev->dev_ops->fdb_del)
3139 return -EOPNOTSUPP;
3140
3141 return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
3142 }
3143
ksz_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)3144 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
3145 dsa_fdb_dump_cb_t *cb, void *data)
3146 {
3147 struct ksz_device *dev = ds->priv;
3148
3149 if (!dev->dev_ops->fdb_dump)
3150 return -EOPNOTSUPP;
3151
3152 return dev->dev_ops->fdb_dump(dev, port, cb, data);
3153 }
3154
ksz_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)3155 static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
3156 const struct switchdev_obj_port_mdb *mdb,
3157 struct dsa_db db)
3158 {
3159 struct ksz_device *dev = ds->priv;
3160
3161 if (!dev->dev_ops->mdb_add)
3162 return -EOPNOTSUPP;
3163
3164 return dev->dev_ops->mdb_add(dev, port, mdb, db);
3165 }
3166
ksz_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)3167 static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
3168 const struct switchdev_obj_port_mdb *mdb,
3169 struct dsa_db db)
3170 {
3171 struct ksz_device *dev = ds->priv;
3172
3173 if (!dev->dev_ops->mdb_del)
3174 return -EOPNOTSUPP;
3175
3176 return dev->dev_ops->mdb_del(dev, port, mdb, db);
3177 }
3178
ksz9477_set_default_prio_queue_mapping(struct ksz_device * dev,int port)3179 static int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev,
3180 int port)
3181 {
3182 u32 queue_map = 0;
3183 int ipm;
3184
3185 for (ipm = 0; ipm < dev->info->num_ipms; ipm++) {
3186 int queue;
3187
3188 /* Traffic Type (TT) is corresponding to the Internal Priority
3189 * Map (IPM) in the switch. Traffic Class (TC) is
3190 * corresponding to the queue in the switch.
3191 */
3192 queue = ieee8021q_tt_to_tc(ipm, dev->info->num_tx_queues);
3193 if (queue < 0)
3194 return queue;
3195
3196 queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S);
3197 }
3198
3199 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
3200 }
3201
ksz_port_setup(struct dsa_switch * ds,int port)3202 static int ksz_port_setup(struct dsa_switch *ds, int port)
3203 {
3204 struct ksz_device *dev = ds->priv;
3205 int ret;
3206
3207 if (!dsa_is_user_port(ds, port))
3208 return 0;
3209
3210 /* setup user port */
3211 dev->dev_ops->port_setup(dev, port, false);
3212
3213 if (!is_ksz8(dev)) {
3214 ret = ksz9477_set_default_prio_queue_mapping(dev, port);
3215 if (ret)
3216 return ret;
3217 }
3218
3219 /* port_stp_state_set() will be called after to enable the port so
3220 * there is no need to do anything.
3221 */
3222
3223 return ksz_dcb_init_port(dev, port);
3224 }
3225
ksz_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)3226 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
3227 {
3228 struct ksz_device *dev = ds->priv;
3229 struct ksz_port *p;
3230 const u16 *regs;
3231 u8 data;
3232
3233 regs = dev->info->regs;
3234
3235 ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
3236 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
3237
3238 p = &dev->ports[port];
3239
3240 switch (state) {
3241 case BR_STATE_DISABLED:
3242 data |= PORT_LEARN_DISABLE;
3243 break;
3244 case BR_STATE_LISTENING:
3245 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
3246 break;
3247 case BR_STATE_LEARNING:
3248 data |= PORT_RX_ENABLE;
3249 if (!p->learning)
3250 data |= PORT_LEARN_DISABLE;
3251 break;
3252 case BR_STATE_FORWARDING:
3253 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
3254 if (!p->learning)
3255 data |= PORT_LEARN_DISABLE;
3256 break;
3257 case BR_STATE_BLOCKING:
3258 data |= PORT_LEARN_DISABLE;
3259 break;
3260 default:
3261 dev_err(ds->dev, "invalid STP state: %d\n", state);
3262 return;
3263 }
3264
3265 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
3266
3267 p->stp_state = state;
3268
3269 ksz_update_port_member(dev, port);
3270 }
3271
ksz_port_teardown(struct dsa_switch * ds,int port)3272 static void ksz_port_teardown(struct dsa_switch *ds, int port)
3273 {
3274 struct ksz_device *dev = ds->priv;
3275
3276 switch (dev->chip_id) {
3277 case KSZ8563_CHIP_ID:
3278 case KSZ8567_CHIP_ID:
3279 case KSZ9477_CHIP_ID:
3280 case KSZ9563_CHIP_ID:
3281 case KSZ9567_CHIP_ID:
3282 case KSZ9893_CHIP_ID:
3283 case KSZ9896_CHIP_ID:
3284 case KSZ9897_CHIP_ID:
3285 case LAN9646_CHIP_ID:
3286 if (dsa_is_user_port(ds, port))
3287 ksz9477_port_acl_free(dev, port);
3288 }
3289 }
3290
ksz_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)3291 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
3292 struct switchdev_brport_flags flags,
3293 struct netlink_ext_ack *extack)
3294 {
3295 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED))
3296 return -EINVAL;
3297
3298 return 0;
3299 }
3300
ksz_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)3301 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
3302 struct switchdev_brport_flags flags,
3303 struct netlink_ext_ack *extack)
3304 {
3305 struct ksz_device *dev = ds->priv;
3306 struct ksz_port *p = &dev->ports[port];
3307
3308 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) {
3309 if (flags.mask & BR_LEARNING)
3310 p->learning = !!(flags.val & BR_LEARNING);
3311
3312 if (flags.mask & BR_ISOLATED)
3313 p->isolated = !!(flags.val & BR_ISOLATED);
3314
3315 /* Make the change take effect immediately */
3316 ksz_port_stp_state_set(ds, port, p->stp_state);
3317 }
3318
3319 return 0;
3320 }
3321
ksz_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)3322 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
3323 int port,
3324 enum dsa_tag_protocol mp)
3325 {
3326 struct ksz_device *dev = ds->priv;
3327 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
3328
3329 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev))
3330 proto = DSA_TAG_PROTO_KSZ8795;
3331
3332 if (dev->chip_id == KSZ88X3_CHIP_ID ||
3333 dev->chip_id == KSZ8563_CHIP_ID ||
3334 dev->chip_id == KSZ9893_CHIP_ID ||
3335 dev->chip_id == KSZ9563_CHIP_ID)
3336 proto = DSA_TAG_PROTO_KSZ9893;
3337
3338 if (dev->chip_id == KSZ8567_CHIP_ID ||
3339 dev->chip_id == KSZ9477_CHIP_ID ||
3340 dev->chip_id == KSZ9896_CHIP_ID ||
3341 dev->chip_id == KSZ9897_CHIP_ID ||
3342 dev->chip_id == KSZ9567_CHIP_ID ||
3343 dev->chip_id == LAN9646_CHIP_ID)
3344 proto = DSA_TAG_PROTO_KSZ9477;
3345
3346 if (is_lan937x(dev))
3347 proto = DSA_TAG_PROTO_LAN937X;
3348
3349 return proto;
3350 }
3351
ksz_connect_tag_protocol(struct dsa_switch * ds,enum dsa_tag_protocol proto)3352 static int ksz_connect_tag_protocol(struct dsa_switch *ds,
3353 enum dsa_tag_protocol proto)
3354 {
3355 struct ksz_tagger_data *tagger_data;
3356
3357 switch (proto) {
3358 case DSA_TAG_PROTO_KSZ8795:
3359 return 0;
3360 case DSA_TAG_PROTO_KSZ9893:
3361 case DSA_TAG_PROTO_KSZ9477:
3362 case DSA_TAG_PROTO_LAN937X:
3363 tagger_data = ksz_tagger_data(ds);
3364 tagger_data->xmit_work_fn = ksz_port_deferred_xmit;
3365 return 0;
3366 default:
3367 return -EPROTONOSUPPORT;
3368 }
3369 }
3370
ksz_port_vlan_filtering(struct dsa_switch * ds,int port,bool flag,struct netlink_ext_ack * extack)3371 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
3372 bool flag, struct netlink_ext_ack *extack)
3373 {
3374 struct ksz_device *dev = ds->priv;
3375
3376 if (!dev->dev_ops->vlan_filtering)
3377 return -EOPNOTSUPP;
3378
3379 return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
3380 }
3381
ksz_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)3382 static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
3383 const struct switchdev_obj_port_vlan *vlan,
3384 struct netlink_ext_ack *extack)
3385 {
3386 struct ksz_device *dev = ds->priv;
3387
3388 if (!dev->dev_ops->vlan_add)
3389 return -EOPNOTSUPP;
3390
3391 return dev->dev_ops->vlan_add(dev, port, vlan, extack);
3392 }
3393
ksz_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)3394 static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
3395 const struct switchdev_obj_port_vlan *vlan)
3396 {
3397 struct ksz_device *dev = ds->priv;
3398
3399 if (!dev->dev_ops->vlan_del)
3400 return -EOPNOTSUPP;
3401
3402 return dev->dev_ops->vlan_del(dev, port, vlan);
3403 }
3404
ksz_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)3405 static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
3406 struct dsa_mall_mirror_tc_entry *mirror,
3407 bool ingress, struct netlink_ext_ack *extack)
3408 {
3409 struct ksz_device *dev = ds->priv;
3410
3411 if (!dev->dev_ops->mirror_add)
3412 return -EOPNOTSUPP;
3413
3414 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
3415 }
3416
ksz_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)3417 static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
3418 struct dsa_mall_mirror_tc_entry *mirror)
3419 {
3420 struct ksz_device *dev = ds->priv;
3421
3422 if (dev->dev_ops->mirror_del)
3423 dev->dev_ops->mirror_del(dev, port, mirror);
3424 }
3425
ksz_change_mtu(struct dsa_switch * ds,int port,int mtu)3426 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
3427 {
3428 struct ksz_device *dev = ds->priv;
3429
3430 if (!dev->dev_ops->change_mtu)
3431 return -EOPNOTSUPP;
3432
3433 return dev->dev_ops->change_mtu(dev, port, mtu);
3434 }
3435
ksz_max_mtu(struct dsa_switch * ds,int port)3436 static int ksz_max_mtu(struct dsa_switch *ds, int port)
3437 {
3438 struct ksz_device *dev = ds->priv;
3439
3440 switch (dev->chip_id) {
3441 case KSZ8795_CHIP_ID:
3442 case KSZ8794_CHIP_ID:
3443 case KSZ8765_CHIP_ID:
3444 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3445 case KSZ88X3_CHIP_ID:
3446 case KSZ8864_CHIP_ID:
3447 case KSZ8895_CHIP_ID:
3448 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3449 case KSZ8563_CHIP_ID:
3450 case KSZ8567_CHIP_ID:
3451 case KSZ9477_CHIP_ID:
3452 case KSZ9563_CHIP_ID:
3453 case KSZ9567_CHIP_ID:
3454 case KSZ9893_CHIP_ID:
3455 case KSZ9896_CHIP_ID:
3456 case KSZ9897_CHIP_ID:
3457 case LAN9370_CHIP_ID:
3458 case LAN9371_CHIP_ID:
3459 case LAN9372_CHIP_ID:
3460 case LAN9373_CHIP_ID:
3461 case LAN9374_CHIP_ID:
3462 case LAN9646_CHIP_ID:
3463 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
3464 }
3465
3466 return -EOPNOTSUPP;
3467 }
3468
ksz_support_eee(struct dsa_switch * ds,int port)3469 static bool ksz_support_eee(struct dsa_switch *ds, int port)
3470 {
3471 struct ksz_device *dev = ds->priv;
3472
3473 if (!dev->info->internal_phy[port])
3474 return false;
3475
3476 switch (dev->chip_id) {
3477 case KSZ8563_CHIP_ID:
3478 case KSZ8567_CHIP_ID:
3479 case KSZ9477_CHIP_ID:
3480 case KSZ9563_CHIP_ID:
3481 case KSZ9567_CHIP_ID:
3482 case KSZ9893_CHIP_ID:
3483 case KSZ9896_CHIP_ID:
3484 case KSZ9897_CHIP_ID:
3485 case LAN9646_CHIP_ID:
3486 return true;
3487 }
3488
3489 return false;
3490 }
3491
ksz_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_keee * e)3492 static int ksz_set_mac_eee(struct dsa_switch *ds, int port,
3493 struct ethtool_keee *e)
3494 {
3495 struct ksz_device *dev = ds->priv;
3496
3497 if (!e->tx_lpi_enabled) {
3498 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n");
3499 return -EINVAL;
3500 }
3501
3502 if (e->tx_lpi_timer) {
3503 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n");
3504 return -EINVAL;
3505 }
3506
3507 return 0;
3508 }
3509
ksz_set_xmii(struct ksz_device * dev,int port,phy_interface_t interface)3510 static void ksz_set_xmii(struct ksz_device *dev, int port,
3511 phy_interface_t interface)
3512 {
3513 const u8 *bitval = dev->info->xmii_ctrl1;
3514 struct ksz_port *p = &dev->ports[port];
3515 const u16 *regs = dev->info->regs;
3516 u8 data8;
3517
3518 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3519
3520 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
3521 P_RGMII_ID_EG_ENABLE);
3522
3523 switch (interface) {
3524 case PHY_INTERFACE_MODE_MII:
3525 data8 |= bitval[P_MII_SEL];
3526 break;
3527 case PHY_INTERFACE_MODE_RMII:
3528 data8 |= bitval[P_RMII_SEL];
3529 break;
3530 case PHY_INTERFACE_MODE_GMII:
3531 data8 |= bitval[P_GMII_SEL];
3532 break;
3533 case PHY_INTERFACE_MODE_RGMII:
3534 case PHY_INTERFACE_MODE_RGMII_ID:
3535 case PHY_INTERFACE_MODE_RGMII_TXID:
3536 case PHY_INTERFACE_MODE_RGMII_RXID:
3537 data8 |= bitval[P_RGMII_SEL];
3538 /* On KSZ9893, disable RGMII in-band status support */
3539 if (dev->chip_id == KSZ9893_CHIP_ID ||
3540 dev->chip_id == KSZ8563_CHIP_ID ||
3541 dev->chip_id == KSZ9563_CHIP_ID ||
3542 is_lan937x(dev))
3543 data8 &= ~P_MII_MAC_MODE;
3544 break;
3545 default:
3546 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
3547 phy_modes(interface), port);
3548 return;
3549 }
3550
3551 if (p->rgmii_tx_val)
3552 data8 |= P_RGMII_ID_EG_ENABLE;
3553
3554 if (p->rgmii_rx_val)
3555 data8 |= P_RGMII_ID_IG_ENABLE;
3556
3557 /* Write the updated value */
3558 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
3559 }
3560
ksz_get_xmii(struct ksz_device * dev,int port,bool gbit)3561 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
3562 {
3563 const u8 *bitval = dev->info->xmii_ctrl1;
3564 const u16 *regs = dev->info->regs;
3565 phy_interface_t interface;
3566 u8 data8;
3567 u8 val;
3568
3569 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3570
3571 val = FIELD_GET(P_MII_SEL_M, data8);
3572
3573 if (val == bitval[P_MII_SEL]) {
3574 if (gbit)
3575 interface = PHY_INTERFACE_MODE_GMII;
3576 else
3577 interface = PHY_INTERFACE_MODE_MII;
3578 } else if (val == bitval[P_RMII_SEL]) {
3579 interface = PHY_INTERFACE_MODE_RMII;
3580 } else {
3581 interface = PHY_INTERFACE_MODE_RGMII;
3582 if (data8 & P_RGMII_ID_EG_ENABLE)
3583 interface = PHY_INTERFACE_MODE_RGMII_TXID;
3584 if (data8 & P_RGMII_ID_IG_ENABLE) {
3585 interface = PHY_INTERFACE_MODE_RGMII_RXID;
3586 if (data8 & P_RGMII_ID_EG_ENABLE)
3587 interface = PHY_INTERFACE_MODE_RGMII_ID;
3588 }
3589 }
3590
3591 return interface;
3592 }
3593
ksz88x3_phylink_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)3594 static void ksz88x3_phylink_mac_config(struct phylink_config *config,
3595 unsigned int mode,
3596 const struct phylink_link_state *state)
3597 {
3598 struct dsa_port *dp = dsa_phylink_to_port(config);
3599 struct ksz_device *dev = dp->ds->priv;
3600
3601 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN);
3602 }
3603
ksz_phylink_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)3604 static void ksz_phylink_mac_config(struct phylink_config *config,
3605 unsigned int mode,
3606 const struct phylink_link_state *state)
3607 {
3608 struct dsa_port *dp = dsa_phylink_to_port(config);
3609 struct ksz_device *dev = dp->ds->priv;
3610 int port = dp->index;
3611
3612 /* Internal PHYs */
3613 if (dev->info->internal_phy[port])
3614 return;
3615
3616 if (phylink_autoneg_inband(mode)) {
3617 dev_err(dev->dev, "In-band AN not supported!\n");
3618 return;
3619 }
3620
3621 ksz_set_xmii(dev, port, state->interface);
3622
3623 if (dev->dev_ops->setup_rgmii_delay)
3624 dev->dev_ops->setup_rgmii_delay(dev, port);
3625 }
3626
ksz_get_gbit(struct ksz_device * dev,int port)3627 bool ksz_get_gbit(struct ksz_device *dev, int port)
3628 {
3629 const u8 *bitval = dev->info->xmii_ctrl1;
3630 const u16 *regs = dev->info->regs;
3631 bool gbit = false;
3632 u8 data8;
3633 bool val;
3634
3635 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3636
3637 val = FIELD_GET(P_GMII_1GBIT_M, data8);
3638
3639 if (val == bitval[P_GMII_1GBIT])
3640 gbit = true;
3641
3642 return gbit;
3643 }
3644
ksz_set_gbit(struct ksz_device * dev,int port,bool gbit)3645 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
3646 {
3647 const u8 *bitval = dev->info->xmii_ctrl1;
3648 const u16 *regs = dev->info->regs;
3649 u8 data8;
3650
3651 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
3652
3653 data8 &= ~P_GMII_1GBIT_M;
3654
3655 if (gbit)
3656 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
3657 else
3658 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
3659
3660 /* Write the updated value */
3661 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
3662 }
3663
ksz_set_100_10mbit(struct ksz_device * dev,int port,int speed)3664 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
3665 {
3666 const u8 *bitval = dev->info->xmii_ctrl0;
3667 const u16 *regs = dev->info->regs;
3668 u8 data8;
3669
3670 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
3671
3672 data8 &= ~P_MII_100MBIT_M;
3673
3674 if (speed == SPEED_100)
3675 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
3676 else
3677 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
3678
3679 /* Write the updated value */
3680 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
3681 }
3682
ksz_port_set_xmii_speed(struct ksz_device * dev,int port,int speed)3683 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
3684 {
3685 if (speed == SPEED_1000)
3686 ksz_set_gbit(dev, port, true);
3687 else
3688 ksz_set_gbit(dev, port, false);
3689
3690 if (speed == SPEED_100 || speed == SPEED_10)
3691 ksz_set_100_10mbit(dev, port, speed);
3692 }
3693
ksz_duplex_flowctrl(struct ksz_device * dev,int port,int duplex,bool tx_pause,bool rx_pause)3694 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
3695 bool tx_pause, bool rx_pause)
3696 {
3697 const u8 *bitval = dev->info->xmii_ctrl0;
3698 const u32 *masks = dev->info->masks;
3699 const u16 *regs = dev->info->regs;
3700 u8 mask;
3701 u8 val;
3702
3703 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
3704 masks[P_MII_RX_FLOW_CTRL];
3705
3706 if (duplex == DUPLEX_FULL)
3707 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
3708 else
3709 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
3710
3711 if (tx_pause)
3712 val |= masks[P_MII_TX_FLOW_CTRL];
3713
3714 if (rx_pause)
3715 val |= masks[P_MII_RX_FLOW_CTRL];
3716
3717 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val);
3718 }
3719
ksz9477_phylink_mac_link_up(struct phylink_config * config,struct phy_device * phydev,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)3720 static void ksz9477_phylink_mac_link_up(struct phylink_config *config,
3721 struct phy_device *phydev,
3722 unsigned int mode,
3723 phy_interface_t interface,
3724 int speed, int duplex, bool tx_pause,
3725 bool rx_pause)
3726 {
3727 struct dsa_port *dp = dsa_phylink_to_port(config);
3728 struct ksz_device *dev = dp->ds->priv;
3729 int port = dp->index;
3730 struct ksz_port *p;
3731
3732 p = &dev->ports[port];
3733
3734 /* Internal PHYs */
3735 if (dev->info->internal_phy[port])
3736 return;
3737
3738 p->phydev.speed = speed;
3739
3740 ksz_port_set_xmii_speed(dev, port, speed);
3741
3742 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
3743 }
3744
ksz_switch_detect(struct ksz_device * dev)3745 static int ksz_switch_detect(struct ksz_device *dev)
3746 {
3747 u8 id1, id2, id4;
3748 u16 id16;
3749 u32 id32;
3750 int ret;
3751
3752 /* read chip id */
3753 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
3754 if (ret)
3755 return ret;
3756
3757 id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
3758 id2 = FIELD_GET(SW_CHIP_ID_M, id16);
3759
3760 switch (id1) {
3761 case KSZ87_FAMILY_ID:
3762 if (id2 == KSZ87_CHIP_ID_95) {
3763 u8 val;
3764
3765 dev->chip_id = KSZ8795_CHIP_ID;
3766
3767 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val);
3768 if (val & KSZ8_PORT_FIBER_MODE)
3769 dev->chip_id = KSZ8765_CHIP_ID;
3770 } else if (id2 == KSZ87_CHIP_ID_94) {
3771 dev->chip_id = KSZ8794_CHIP_ID;
3772 } else {
3773 return -ENODEV;
3774 }
3775 break;
3776 case KSZ88_FAMILY_ID:
3777 if (id2 == KSZ88_CHIP_ID_63)
3778 dev->chip_id = KSZ88X3_CHIP_ID;
3779 else
3780 return -ENODEV;
3781 break;
3782 case KSZ8895_FAMILY_ID:
3783 if (id2 == KSZ8895_CHIP_ID_95 ||
3784 id2 == KSZ8895_CHIP_ID_95R)
3785 dev->chip_id = KSZ8895_CHIP_ID;
3786 else
3787 return -ENODEV;
3788 ret = ksz_read8(dev, REG_KSZ8864_CHIP_ID, &id4);
3789 if (ret)
3790 return ret;
3791 if (id4 & SW_KSZ8864)
3792 dev->chip_id = KSZ8864_CHIP_ID;
3793 break;
3794 default:
3795 ret = ksz_read32(dev, REG_CHIP_ID0, &id32);
3796 if (ret)
3797 return ret;
3798
3799 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
3800 id32 &= ~0xFF;
3801
3802 switch (id32) {
3803 case KSZ9477_CHIP_ID:
3804 case KSZ9896_CHIP_ID:
3805 case KSZ9897_CHIP_ID:
3806 case KSZ9567_CHIP_ID:
3807 case KSZ8567_CHIP_ID:
3808 case LAN9370_CHIP_ID:
3809 case LAN9371_CHIP_ID:
3810 case LAN9372_CHIP_ID:
3811 case LAN9373_CHIP_ID:
3812 case LAN9374_CHIP_ID:
3813
3814 /* LAN9646 does not have its own chip id. */
3815 if (dev->chip_id != LAN9646_CHIP_ID)
3816 dev->chip_id = id32;
3817 break;
3818 case KSZ9893_CHIP_ID:
3819 ret = ksz_read8(dev, REG_CHIP_ID4,
3820 &id4);
3821 if (ret)
3822 return ret;
3823
3824 if (id4 == SKU_ID_KSZ8563)
3825 dev->chip_id = KSZ8563_CHIP_ID;
3826 else if (id4 == SKU_ID_KSZ9563)
3827 dev->chip_id = KSZ9563_CHIP_ID;
3828 else
3829 dev->chip_id = KSZ9893_CHIP_ID;
3830
3831 break;
3832 default:
3833 dev_err(dev->dev,
3834 "unsupported switch detected %x)\n", id32);
3835 return -ENODEV;
3836 }
3837 }
3838 return 0;
3839 }
3840
ksz_cls_flower_add(struct dsa_switch * ds,int port,struct flow_cls_offload * cls,bool ingress)3841 static int ksz_cls_flower_add(struct dsa_switch *ds, int port,
3842 struct flow_cls_offload *cls, bool ingress)
3843 {
3844 struct ksz_device *dev = ds->priv;
3845
3846 switch (dev->chip_id) {
3847 case KSZ8563_CHIP_ID:
3848 case KSZ8567_CHIP_ID:
3849 case KSZ9477_CHIP_ID:
3850 case KSZ9563_CHIP_ID:
3851 case KSZ9567_CHIP_ID:
3852 case KSZ9893_CHIP_ID:
3853 case KSZ9896_CHIP_ID:
3854 case KSZ9897_CHIP_ID:
3855 case LAN9646_CHIP_ID:
3856 return ksz9477_cls_flower_add(ds, port, cls, ingress);
3857 }
3858
3859 return -EOPNOTSUPP;
3860 }
3861
ksz_cls_flower_del(struct dsa_switch * ds,int port,struct flow_cls_offload * cls,bool ingress)3862 static int ksz_cls_flower_del(struct dsa_switch *ds, int port,
3863 struct flow_cls_offload *cls, bool ingress)
3864 {
3865 struct ksz_device *dev = ds->priv;
3866
3867 switch (dev->chip_id) {
3868 case KSZ8563_CHIP_ID:
3869 case KSZ8567_CHIP_ID:
3870 case KSZ9477_CHIP_ID:
3871 case KSZ9563_CHIP_ID:
3872 case KSZ9567_CHIP_ID:
3873 case KSZ9893_CHIP_ID:
3874 case KSZ9896_CHIP_ID:
3875 case KSZ9897_CHIP_ID:
3876 case LAN9646_CHIP_ID:
3877 return ksz9477_cls_flower_del(ds, port, cls, ingress);
3878 }
3879
3880 return -EOPNOTSUPP;
3881 }
3882
3883 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth
3884 * is converted to Hex-decimal using the successive multiplication method. On
3885 * every step, integer part is taken and decimal part is carry forwarded.
3886 */
cinc_cal(s32 idle_slope,s32 send_slope,u32 * bw)3887 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw)
3888 {
3889 u32 cinc = 0;
3890 u32 txrate;
3891 u32 rate;
3892 u8 temp;
3893 u8 i;
3894
3895 txrate = idle_slope - send_slope;
3896
3897 if (!txrate)
3898 return -EINVAL;
3899
3900 rate = idle_slope;
3901
3902 /* 24 bit register */
3903 for (i = 0; i < 6; i++) {
3904 rate = rate * 16;
3905
3906 temp = rate / txrate;
3907
3908 rate %= txrate;
3909
3910 cinc = ((cinc << 4) | temp);
3911 }
3912
3913 *bw = cinc;
3914
3915 return 0;
3916 }
3917
ksz_setup_tc_mode(struct ksz_device * dev,int port,u8 scheduler,u8 shaper)3918 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler,
3919 u8 shaper)
3920 {
3921 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0,
3922 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) |
3923 FIELD_PREP(MTI_SHAPING_M, shaper));
3924 }
3925
ksz_setup_tc_cbs(struct dsa_switch * ds,int port,struct tc_cbs_qopt_offload * qopt)3926 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port,
3927 struct tc_cbs_qopt_offload *qopt)
3928 {
3929 struct ksz_device *dev = ds->priv;
3930 int ret;
3931 u32 bw;
3932
3933 if (!dev->info->tc_cbs_supported)
3934 return -EOPNOTSUPP;
3935
3936 if (qopt->queue > dev->info->num_tx_queues)
3937 return -EINVAL;
3938
3939 /* Queue Selection */
3940 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue);
3941 if (ret)
3942 return ret;
3943
3944 if (!qopt->enable)
3945 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
3946 MTI_SHAPING_OFF);
3947
3948 /* High Credit */
3949 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK,
3950 qopt->hicredit);
3951 if (ret)
3952 return ret;
3953
3954 /* Low Credit */
3955 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK,
3956 qopt->locredit);
3957 if (ret)
3958 return ret;
3959
3960 /* Credit Increment Register */
3961 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw);
3962 if (ret)
3963 return ret;
3964
3965 if (dev->dev_ops->tc_cbs_set_cinc) {
3966 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw);
3967 if (ret)
3968 return ret;
3969 }
3970
3971 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
3972 MTI_SHAPING_SRP);
3973 }
3974
ksz_disable_egress_rate_limit(struct ksz_device * dev,int port)3975 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port)
3976 {
3977 int queue, ret;
3978
3979 /* Configuration will not take effect until the last Port Queue X
3980 * Egress Limit Control Register is written.
3981 */
3982 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
3983 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue,
3984 KSZ9477_OUT_RATE_NO_LIMIT);
3985 if (ret)
3986 return ret;
3987 }
3988
3989 return 0;
3990 }
3991
ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params * p,int band)3992 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p,
3993 int band)
3994 {
3995 /* Compared to queues, bands prioritize packets differently. In strict
3996 * priority mode, the lowest priority is assigned to Queue 0 while the
3997 * highest priority is given to Band 0.
3998 */
3999 return p->bands - 1 - band;
4000 }
4001
ksz_queue_set_strict(struct ksz_device * dev,int port,int queue)4002 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue)
4003 {
4004 int ret;
4005
4006 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
4007 if (ret)
4008 return ret;
4009
4010 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO,
4011 MTI_SHAPING_OFF);
4012 }
4013
ksz_queue_set_wrr(struct ksz_device * dev,int port,int queue,int weight)4014 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue,
4015 int weight)
4016 {
4017 int ret;
4018
4019 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue);
4020 if (ret)
4021 return ret;
4022
4023 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR,
4024 MTI_SHAPING_OFF);
4025 if (ret)
4026 return ret;
4027
4028 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight);
4029 }
4030
ksz_tc_ets_add(struct ksz_device * dev,int port,struct tc_ets_qopt_offload_replace_params * p)4031 static int ksz_tc_ets_add(struct ksz_device *dev, int port,
4032 struct tc_ets_qopt_offload_replace_params *p)
4033 {
4034 int ret, band, tc_prio;
4035 u32 queue_map = 0;
4036
4037 /* In order to ensure proper prioritization, it is necessary to set the
4038 * rate limit for the related queue to zero. Otherwise strict priority
4039 * or WRR mode will not work. This is a hardware limitation.
4040 */
4041 ret = ksz_disable_egress_rate_limit(dev, port);
4042 if (ret)
4043 return ret;
4044
4045 /* Configure queue scheduling mode for all bands. Currently only strict
4046 * prio mode is supported.
4047 */
4048 for (band = 0; band < p->bands; band++) {
4049 int queue = ksz_ets_band_to_queue(p, band);
4050
4051 ret = ksz_queue_set_strict(dev, port, queue);
4052 if (ret)
4053 return ret;
4054 }
4055
4056 /* Configure the mapping between traffic classes and queues. Note:
4057 * priomap variable support 16 traffic classes, but the chip can handle
4058 * only 8 classes.
4059 */
4060 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) {
4061 int queue;
4062
4063 if (tc_prio >= dev->info->num_ipms)
4064 break;
4065
4066 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]);
4067 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S);
4068 }
4069
4070 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map);
4071 }
4072
ksz_tc_ets_del(struct ksz_device * dev,int port)4073 static int ksz_tc_ets_del(struct ksz_device *dev, int port)
4074 {
4075 int ret, queue;
4076
4077 /* To restore the default chip configuration, set all queues to use the
4078 * WRR scheduler with a weight of 1.
4079 */
4080 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
4081 ret = ksz_queue_set_wrr(dev, port, queue,
4082 KSZ9477_DEFAULT_WRR_WEIGHT);
4083 if (ret)
4084 return ret;
4085 }
4086
4087 /* Revert the queue mapping for TC-priority to its default setting on
4088 * the chip.
4089 */
4090 return ksz9477_set_default_prio_queue_mapping(dev, port);
4091 }
4092
ksz_tc_ets_validate(struct ksz_device * dev,int port,struct tc_ets_qopt_offload_replace_params * p)4093 static int ksz_tc_ets_validate(struct ksz_device *dev, int port,
4094 struct tc_ets_qopt_offload_replace_params *p)
4095 {
4096 int band;
4097
4098 /* Since it is not feasible to share one port among multiple qdisc,
4099 * the user must configure all available queues appropriately.
4100 */
4101 if (p->bands != dev->info->num_tx_queues) {
4102 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n",
4103 dev->info->num_tx_queues);
4104 return -EOPNOTSUPP;
4105 }
4106
4107 for (band = 0; band < p->bands; ++band) {
4108 /* The KSZ switches utilize a weighted round robin configuration
4109 * where a certain number of packets can be transmitted from a
4110 * queue before the next queue is serviced. For more information
4111 * on this, refer to section 5.2.8.4 of the KSZ8565R
4112 * documentation on the Port Transmit Queue Control 1 Register.
4113 * However, the current ETS Qdisc implementation (as of February
4114 * 2023) assigns a weight to each queue based on the number of
4115 * bytes or extrapolated bandwidth in percentages. Since this
4116 * differs from the KSZ switches' method and we don't want to
4117 * fake support by converting bytes to packets, it is better to
4118 * return an error instead.
4119 */
4120 if (p->quanta[band]) {
4121 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n");
4122 return -EOPNOTSUPP;
4123 }
4124 }
4125
4126 return 0;
4127 }
4128
ksz_tc_setup_qdisc_ets(struct dsa_switch * ds,int port,struct tc_ets_qopt_offload * qopt)4129 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port,
4130 struct tc_ets_qopt_offload *qopt)
4131 {
4132 struct ksz_device *dev = ds->priv;
4133 int ret;
4134
4135 if (is_ksz8(dev))
4136 return -EOPNOTSUPP;
4137
4138 if (qopt->parent != TC_H_ROOT) {
4139 dev_err(dev->dev, "Parent should be \"root\"\n");
4140 return -EOPNOTSUPP;
4141 }
4142
4143 switch (qopt->command) {
4144 case TC_ETS_REPLACE:
4145 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params);
4146 if (ret)
4147 return ret;
4148
4149 return ksz_tc_ets_add(dev, port, &qopt->replace_params);
4150 case TC_ETS_DESTROY:
4151 return ksz_tc_ets_del(dev, port);
4152 case TC_ETS_STATS:
4153 case TC_ETS_GRAFT:
4154 return -EOPNOTSUPP;
4155 }
4156
4157 return -EOPNOTSUPP;
4158 }
4159
ksz_setup_tc(struct dsa_switch * ds,int port,enum tc_setup_type type,void * type_data)4160 static int ksz_setup_tc(struct dsa_switch *ds, int port,
4161 enum tc_setup_type type, void *type_data)
4162 {
4163 switch (type) {
4164 case TC_SETUP_QDISC_CBS:
4165 return ksz_setup_tc_cbs(ds, port, type_data);
4166 case TC_SETUP_QDISC_ETS:
4167 return ksz_tc_setup_qdisc_ets(ds, port, type_data);
4168 default:
4169 return -EOPNOTSUPP;
4170 }
4171 }
4172
4173 /**
4174 * ksz_handle_wake_reason - Handle wake reason on a specified port.
4175 * @dev: The device structure.
4176 * @port: The port number.
4177 *
4178 * This function reads the PME (Power Management Event) status register of a
4179 * specified port to determine the wake reason. If there is no wake event, it
4180 * returns early. Otherwise, it logs the wake reason which could be due to a
4181 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register
4182 * is then cleared to acknowledge the handling of the wake event.
4183 *
4184 * Return: 0 on success, or an error code on failure.
4185 */
ksz_handle_wake_reason(struct ksz_device * dev,int port)4186 int ksz_handle_wake_reason(struct ksz_device *dev, int port)
4187 {
4188 const struct ksz_dev_ops *ops = dev->dev_ops;
4189 const u16 *regs = dev->info->regs;
4190 u8 pme_status;
4191 int ret;
4192
4193 ret = ops->pme_pread8(dev, port, regs[REG_PORT_PME_STATUS],
4194 &pme_status);
4195 if (ret)
4196 return ret;
4197
4198 if (!pme_status)
4199 return 0;
4200
4201 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port,
4202 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "",
4203 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "",
4204 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : "");
4205
4206 return ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_STATUS],
4207 pme_status);
4208 }
4209
4210 /**
4211 * ksz_get_wol - Get Wake-on-LAN settings for a specified port.
4212 * @ds: The dsa_switch structure.
4213 * @port: The port number.
4214 * @wol: Pointer to ethtool Wake-on-LAN settings structure.
4215 *
4216 * This function checks the device PME wakeup_source flag and chip_id.
4217 * If enabled and supported, it sets the supported and active WoL
4218 * flags.
4219 */
ksz_get_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)4220 static void ksz_get_wol(struct dsa_switch *ds, int port,
4221 struct ethtool_wolinfo *wol)
4222 {
4223 struct ksz_device *dev = ds->priv;
4224 const u16 *regs = dev->info->regs;
4225 u8 pme_ctrl;
4226 int ret;
4227
4228 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev))
4229 return;
4230
4231 if (!dev->wakeup_source)
4232 return;
4233
4234 wol->supported = WAKE_PHY;
4235
4236 /* Check if the current MAC address on this port can be set
4237 * as global for WAKE_MAGIC support. The result may vary
4238 * dynamically based on other ports configurations.
4239 */
4240 if (ksz_is_port_mac_global_usable(dev->ds, port))
4241 wol->supported |= WAKE_MAGIC;
4242
4243 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL],
4244 &pme_ctrl);
4245 if (ret)
4246 return;
4247
4248 if (pme_ctrl & PME_WOL_MAGICPKT)
4249 wol->wolopts |= WAKE_MAGIC;
4250 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY))
4251 wol->wolopts |= WAKE_PHY;
4252 }
4253
4254 /**
4255 * ksz_set_wol - Set Wake-on-LAN settings for a specified port.
4256 * @ds: The dsa_switch structure.
4257 * @port: The port number.
4258 * @wol: Pointer to ethtool Wake-on-LAN settings structure.
4259 *
4260 * This function configures Wake-on-LAN (WoL) settings for a specified
4261 * port. It validates the provided WoL options, checks if PME is
4262 * enabled and supported, clears any previous wake reasons, and sets
4263 * the Magic Packet flag in the port's PME control register if
4264 * specified.
4265 *
4266 * Return: 0 on success, or other error codes on failure.
4267 */
ksz_set_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)4268 static int ksz_set_wol(struct dsa_switch *ds, int port,
4269 struct ethtool_wolinfo *wol)
4270 {
4271 u8 pme_ctrl = 0, pme_ctrl_old = 0;
4272 struct ksz_device *dev = ds->priv;
4273 const u16 *regs = dev->info->regs;
4274 bool magic_switched_off;
4275 bool magic_switched_on;
4276 int ret;
4277
4278 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
4279 return -EINVAL;
4280
4281 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev))
4282 return -EOPNOTSUPP;
4283
4284 if (!dev->wakeup_source)
4285 return -EOPNOTSUPP;
4286
4287 ret = ksz_handle_wake_reason(dev, port);
4288 if (ret)
4289 return ret;
4290
4291 if (wol->wolopts & WAKE_MAGIC)
4292 pme_ctrl |= PME_WOL_MAGICPKT;
4293 if (wol->wolopts & WAKE_PHY)
4294 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY;
4295
4296 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL],
4297 &pme_ctrl_old);
4298 if (ret)
4299 return ret;
4300
4301 if (pme_ctrl_old == pme_ctrl)
4302 return 0;
4303
4304 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) &&
4305 !(pme_ctrl & PME_WOL_MAGICPKT);
4306 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) &&
4307 (pme_ctrl & PME_WOL_MAGICPKT);
4308
4309 /* To keep reference count of MAC address, we should do this
4310 * operation only on change of WOL settings.
4311 */
4312 if (magic_switched_on) {
4313 ret = ksz_switch_macaddr_get(dev->ds, port, NULL);
4314 if (ret)
4315 return ret;
4316 } else if (magic_switched_off) {
4317 ksz_switch_macaddr_put(dev->ds);
4318 }
4319
4320 ret = dev->dev_ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL],
4321 pme_ctrl);
4322 if (ret) {
4323 if (magic_switched_on)
4324 ksz_switch_macaddr_put(dev->ds);
4325 return ret;
4326 }
4327
4328 return 0;
4329 }
4330
4331 /**
4332 * ksz_wol_pre_shutdown - Prepares the switch device for shutdown while
4333 * considering Wake-on-LAN (WoL) settings.
4334 * @dev: The switch device structure.
4335 * @wol_enabled: Pointer to a boolean which will be set to true if WoL is
4336 * enabled on any port.
4337 *
4338 * This function prepares the switch device for a safe shutdown while taking
4339 * into account the Wake-on-LAN (WoL) settings on the user ports. It updates
4340 * the wol_enabled flag accordingly to reflect whether WoL is active on any
4341 * port.
4342 */
ksz_wol_pre_shutdown(struct ksz_device * dev,bool * wol_enabled)4343 static void ksz_wol_pre_shutdown(struct ksz_device *dev, bool *wol_enabled)
4344 {
4345 const struct ksz_dev_ops *ops = dev->dev_ops;
4346 const u16 *regs = dev->info->regs;
4347 u8 pme_pin_en = PME_ENABLE;
4348 struct dsa_port *dp;
4349 int ret;
4350
4351 *wol_enabled = false;
4352
4353 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev))
4354 return;
4355
4356 if (!dev->wakeup_source)
4357 return;
4358
4359 dsa_switch_for_each_user_port(dp, dev->ds) {
4360 u8 pme_ctrl = 0;
4361
4362 ret = ops->pme_pread8(dev, dp->index,
4363 regs[REG_PORT_PME_CTRL], &pme_ctrl);
4364 if (!ret && pme_ctrl)
4365 *wol_enabled = true;
4366
4367 /* make sure there are no pending wake events which would
4368 * prevent the device from going to sleep/shutdown.
4369 */
4370 ksz_handle_wake_reason(dev, dp->index);
4371 }
4372
4373 /* Now we are save to enable PME pin. */
4374 if (*wol_enabled) {
4375 if (dev->pme_active_high)
4376 pme_pin_en |= PME_POLARITY;
4377 ops->pme_write8(dev, regs[REG_SW_PME_CTRL], pme_pin_en);
4378 if (ksz_is_ksz87xx(dev))
4379 ksz_write8(dev, KSZ87XX_REG_INT_EN, KSZ87XX_INT_PME_MASK);
4380 }
4381 }
4382
ksz_port_set_mac_address(struct dsa_switch * ds,int port,const unsigned char * addr)4383 static int ksz_port_set_mac_address(struct dsa_switch *ds, int port,
4384 const unsigned char *addr)
4385 {
4386 struct dsa_port *dp = dsa_to_port(ds, port);
4387 struct ethtool_wolinfo wol;
4388
4389 if (dp->hsr_dev) {
4390 dev_err(ds->dev,
4391 "Cannot change MAC address on port %d with active HSR offload\n",
4392 port);
4393 return -EBUSY;
4394 }
4395
4396 /* Need to initialize variable as the code to fill in settings may
4397 * not be executed.
4398 */
4399 wol.wolopts = 0;
4400
4401 ksz_get_wol(ds, dp->index, &wol);
4402 if (wol.wolopts & WAKE_MAGIC) {
4403 dev_err(ds->dev,
4404 "Cannot change MAC address on port %d with active Wake on Magic Packet\n",
4405 port);
4406 return -EBUSY;
4407 }
4408
4409 return 0;
4410 }
4411
4412 /**
4413 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port
4414 * can be used as a global address.
4415 * @ds: Pointer to the DSA switch structure.
4416 * @port: The port number on which the MAC address is to be checked.
4417 *
4418 * This function examines the MAC address set on the specified port and
4419 * determines if it can be used as a global address for the switch.
4420 *
4421 * Return: true if the port's MAC address can be used as a global address, false
4422 * otherwise.
4423 */
ksz_is_port_mac_global_usable(struct dsa_switch * ds,int port)4424 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port)
4425 {
4426 struct net_device *user = dsa_to_port(ds, port)->user;
4427 const unsigned char *addr = user->dev_addr;
4428 struct ksz_switch_macaddr *switch_macaddr;
4429 struct ksz_device *dev = ds->priv;
4430
4431 ASSERT_RTNL();
4432
4433 switch_macaddr = dev->switch_macaddr;
4434 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr))
4435 return false;
4436
4437 return true;
4438 }
4439
4440 /**
4441 * ksz_switch_macaddr_get - Program the switch's MAC address register.
4442 * @ds: DSA switch instance.
4443 * @port: Port number.
4444 * @extack: Netlink extended acknowledgment.
4445 *
4446 * This function programs the switch's MAC address register with the MAC address
4447 * of the requesting user port. This single address is used by the switch for
4448 * multiple features like HSR self-address filtering and WoL. Other user ports
4449 * can share ownership of this address as long as their MAC address is the same.
4450 * The MAC addresses of user ports must not change while they have ownership of
4451 * the switch MAC address.
4452 *
4453 * Return: 0 on success, or other error codes on failure.
4454 */
ksz_switch_macaddr_get(struct dsa_switch * ds,int port,struct netlink_ext_ack * extack)4455 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port,
4456 struct netlink_ext_ack *extack)
4457 {
4458 struct net_device *user = dsa_to_port(ds, port)->user;
4459 const unsigned char *addr = user->dev_addr;
4460 struct ksz_switch_macaddr *switch_macaddr;
4461 struct ksz_device *dev = ds->priv;
4462 const u16 *regs = dev->info->regs;
4463 int i, ret;
4464
4465 /* Make sure concurrent MAC address changes are blocked */
4466 ASSERT_RTNL();
4467
4468 switch_macaddr = dev->switch_macaddr;
4469 if (switch_macaddr) {
4470 if (!ether_addr_equal(switch_macaddr->addr, addr)) {
4471 NL_SET_ERR_MSG_FMT_MOD(extack,
4472 "Switch already configured for MAC address %pM",
4473 switch_macaddr->addr);
4474 return -EBUSY;
4475 }
4476
4477 refcount_inc(&switch_macaddr->refcount);
4478 return 0;
4479 }
4480
4481 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL);
4482 if (!switch_macaddr)
4483 return -ENOMEM;
4484
4485 ether_addr_copy(switch_macaddr->addr, addr);
4486 refcount_set(&switch_macaddr->refcount, 1);
4487 dev->switch_macaddr = switch_macaddr;
4488
4489 /* Program the switch MAC address to hardware */
4490 for (i = 0; i < ETH_ALEN; i++) {
4491 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, addr[i]);
4492 if (ret)
4493 goto macaddr_drop;
4494 }
4495
4496 return 0;
4497
4498 macaddr_drop:
4499 dev->switch_macaddr = NULL;
4500 refcount_set(&switch_macaddr->refcount, 0);
4501 kfree(switch_macaddr);
4502
4503 return ret;
4504 }
4505
ksz_switch_macaddr_put(struct dsa_switch * ds)4506 void ksz_switch_macaddr_put(struct dsa_switch *ds)
4507 {
4508 struct ksz_switch_macaddr *switch_macaddr;
4509 struct ksz_device *dev = ds->priv;
4510 const u16 *regs = dev->info->regs;
4511 int i;
4512
4513 /* Make sure concurrent MAC address changes are blocked */
4514 ASSERT_RTNL();
4515
4516 switch_macaddr = dev->switch_macaddr;
4517 if (!refcount_dec_and_test(&switch_macaddr->refcount))
4518 return;
4519
4520 for (i = 0; i < ETH_ALEN; i++)
4521 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0);
4522
4523 dev->switch_macaddr = NULL;
4524 kfree(switch_macaddr);
4525 }
4526
ksz_hsr_join(struct dsa_switch * ds,int port,struct net_device * hsr,struct netlink_ext_ack * extack)4527 static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr,
4528 struct netlink_ext_ack *extack)
4529 {
4530 struct ksz_device *dev = ds->priv;
4531 enum hsr_version ver;
4532 int ret;
4533
4534 ret = hsr_get_version(hsr, &ver);
4535 if (ret)
4536 return ret;
4537
4538 if (dev->chip_id != KSZ9477_CHIP_ID) {
4539 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload");
4540 return -EOPNOTSUPP;
4541 }
4542
4543 /* KSZ9477 can support HW offloading of only 1 HSR device */
4544 if (dev->hsr_dev && hsr != dev->hsr_dev) {
4545 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR");
4546 return -EOPNOTSUPP;
4547 }
4548
4549 /* KSZ9477 only supports HSR v0 and v1 */
4550 if (!(ver == HSR_V0 || ver == HSR_V1)) {
4551 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported");
4552 return -EOPNOTSUPP;
4553 }
4554
4555 /* KSZ9477 can only perform HSR offloading for up to two ports */
4556 if (hweight8(dev->hsr_ports) >= 2) {
4557 NL_SET_ERR_MSG_MOD(extack,
4558 "Cannot offload more than two ports - using software HSR");
4559 return -EOPNOTSUPP;
4560 }
4561
4562 /* Self MAC address filtering, to avoid frames traversing
4563 * the HSR ring more than once.
4564 */
4565 ret = ksz_switch_macaddr_get(ds, port, extack);
4566 if (ret)
4567 return ret;
4568
4569 ksz9477_hsr_join(ds, port, hsr);
4570 dev->hsr_dev = hsr;
4571 dev->hsr_ports |= BIT(port);
4572
4573 return 0;
4574 }
4575
ksz_hsr_leave(struct dsa_switch * ds,int port,struct net_device * hsr)4576 static int ksz_hsr_leave(struct dsa_switch *ds, int port,
4577 struct net_device *hsr)
4578 {
4579 struct ksz_device *dev = ds->priv;
4580
4581 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID);
4582
4583 ksz9477_hsr_leave(ds, port, hsr);
4584 dev->hsr_ports &= ~BIT(port);
4585 if (!dev->hsr_ports)
4586 dev->hsr_dev = NULL;
4587
4588 ksz_switch_macaddr_put(ds);
4589
4590 return 0;
4591 }
4592
ksz_suspend(struct dsa_switch * ds)4593 static int ksz_suspend(struct dsa_switch *ds)
4594 {
4595 struct ksz_device *dev = ds->priv;
4596
4597 cancel_delayed_work_sync(&dev->mib_read);
4598 return 0;
4599 }
4600
ksz_resume(struct dsa_switch * ds)4601 static int ksz_resume(struct dsa_switch *ds)
4602 {
4603 struct ksz_device *dev = ds->priv;
4604
4605 if (dev->mib_read_interval)
4606 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
4607 return 0;
4608 }
4609
4610 static const struct dsa_switch_ops ksz_switch_ops = {
4611 .get_tag_protocol = ksz_get_tag_protocol,
4612 .connect_tag_protocol = ksz_connect_tag_protocol,
4613 .get_phy_flags = ksz_get_phy_flags,
4614 .setup = ksz_setup,
4615 .teardown = ksz_teardown,
4616 .phy_read = ksz_phy_read16,
4617 .phy_write = ksz_phy_write16,
4618 .phylink_get_caps = ksz_phylink_get_caps,
4619 .port_setup = ksz_port_setup,
4620 .set_ageing_time = ksz_set_ageing_time,
4621 .get_strings = ksz_get_strings,
4622 .get_ethtool_stats = ksz_get_ethtool_stats,
4623 .get_sset_count = ksz_sset_count,
4624 .port_bridge_join = ksz_port_bridge_join,
4625 .port_bridge_leave = ksz_port_bridge_leave,
4626 .port_hsr_join = ksz_hsr_join,
4627 .port_hsr_leave = ksz_hsr_leave,
4628 .port_set_mac_address = ksz_port_set_mac_address,
4629 .port_stp_state_set = ksz_port_stp_state_set,
4630 .port_teardown = ksz_port_teardown,
4631 .port_pre_bridge_flags = ksz_port_pre_bridge_flags,
4632 .port_bridge_flags = ksz_port_bridge_flags,
4633 .port_fast_age = ksz_port_fast_age,
4634 .port_vlan_filtering = ksz_port_vlan_filtering,
4635 .port_vlan_add = ksz_port_vlan_add,
4636 .port_vlan_del = ksz_port_vlan_del,
4637 .port_fdb_dump = ksz_port_fdb_dump,
4638 .port_fdb_add = ksz_port_fdb_add,
4639 .port_fdb_del = ksz_port_fdb_del,
4640 .port_mdb_add = ksz_port_mdb_add,
4641 .port_mdb_del = ksz_port_mdb_del,
4642 .port_mirror_add = ksz_port_mirror_add,
4643 .port_mirror_del = ksz_port_mirror_del,
4644 .get_stats64 = ksz_get_stats64,
4645 .get_pause_stats = ksz_get_pause_stats,
4646 .port_change_mtu = ksz_change_mtu,
4647 .port_max_mtu = ksz_max_mtu,
4648 .get_wol = ksz_get_wol,
4649 .set_wol = ksz_set_wol,
4650 .suspend = ksz_suspend,
4651 .resume = ksz_resume,
4652 .get_ts_info = ksz_get_ts_info,
4653 .port_hwtstamp_get = ksz_hwtstamp_get,
4654 .port_hwtstamp_set = ksz_hwtstamp_set,
4655 .port_txtstamp = ksz_port_txtstamp,
4656 .port_rxtstamp = ksz_port_rxtstamp,
4657 .cls_flower_add = ksz_cls_flower_add,
4658 .cls_flower_del = ksz_cls_flower_del,
4659 .port_setup_tc = ksz_setup_tc,
4660 .support_eee = ksz_support_eee,
4661 .set_mac_eee = ksz_set_mac_eee,
4662 .port_get_default_prio = ksz_port_get_default_prio,
4663 .port_set_default_prio = ksz_port_set_default_prio,
4664 .port_get_dscp_prio = ksz_port_get_dscp_prio,
4665 .port_add_dscp_prio = ksz_port_add_dscp_prio,
4666 .port_del_dscp_prio = ksz_port_del_dscp_prio,
4667 .port_get_apptrust = ksz_port_get_apptrust,
4668 .port_set_apptrust = ksz_port_set_apptrust,
4669 };
4670
ksz_switch_alloc(struct device * base,void * priv)4671 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
4672 {
4673 struct dsa_switch *ds;
4674 struct ksz_device *swdev;
4675
4676 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
4677 if (!ds)
4678 return NULL;
4679
4680 ds->dev = base;
4681 ds->num_ports = DSA_MAX_PORTS;
4682 ds->ops = &ksz_switch_ops;
4683
4684 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
4685 if (!swdev)
4686 return NULL;
4687
4688 ds->priv = swdev;
4689 swdev->dev = base;
4690
4691 swdev->ds = ds;
4692 swdev->priv = priv;
4693
4694 return swdev;
4695 }
4696 EXPORT_SYMBOL(ksz_switch_alloc);
4697
4698 /**
4699 * ksz_switch_shutdown - Shutdown routine for the switch device.
4700 * @dev: The switch device structure.
4701 *
4702 * This function is responsible for initiating a shutdown sequence for the
4703 * switch device. It invokes the reset operation defined in the device
4704 * operations, if available, to reset the switch. Subsequently, it calls the
4705 * DSA framework's shutdown function to ensure a proper shutdown of the DSA
4706 * switch.
4707 */
ksz_switch_shutdown(struct ksz_device * dev)4708 void ksz_switch_shutdown(struct ksz_device *dev)
4709 {
4710 bool wol_enabled = false;
4711
4712 ksz_wol_pre_shutdown(dev, &wol_enabled);
4713
4714 if (dev->dev_ops->reset && !wol_enabled)
4715 dev->dev_ops->reset(dev);
4716
4717 dsa_switch_shutdown(dev->ds);
4718 }
4719 EXPORT_SYMBOL(ksz_switch_shutdown);
4720
ksz_parse_rgmii_delay(struct ksz_device * dev,int port_num,struct device_node * port_dn)4721 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
4722 struct device_node *port_dn)
4723 {
4724 phy_interface_t phy_mode = dev->ports[port_num].interface;
4725 int rx_delay = -1, tx_delay = -1;
4726
4727 if (!phy_interface_mode_is_rgmii(phy_mode))
4728 return;
4729
4730 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
4731 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
4732
4733 if (rx_delay == -1 && tx_delay == -1) {
4734 dev_warn(dev->dev,
4735 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
4736 "please update device tree to specify \"rx-internal-delay-ps\" and "
4737 "\"tx-internal-delay-ps\"",
4738 port_num);
4739
4740 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
4741 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
4742 rx_delay = 2000;
4743
4744 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
4745 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
4746 tx_delay = 2000;
4747 }
4748
4749 if (rx_delay < 0)
4750 rx_delay = 0;
4751 if (tx_delay < 0)
4752 tx_delay = 0;
4753
4754 dev->ports[port_num].rgmii_rx_val = rx_delay;
4755 dev->ports[port_num].rgmii_tx_val = tx_delay;
4756 }
4757
4758 /**
4759 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding
4760 * register value.
4761 * @array: The array of drive strength values to search.
4762 * @array_size: The size of the array.
4763 * @microamp: The drive strength value in microamp to be converted.
4764 *
4765 * This function searches the array of drive strength values for the given
4766 * microamp value and returns the corresponding register value for that drive.
4767 *
4768 * Returns: If found, the corresponding register value for that drive strength
4769 * is returned. Otherwise, -EINVAL is returned indicating an invalid value.
4770 */
ksz_drive_strength_to_reg(const struct ksz_drive_strength * array,size_t array_size,int microamp)4771 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array,
4772 size_t array_size, int microamp)
4773 {
4774 int i;
4775
4776 for (i = 0; i < array_size; i++) {
4777 if (array[i].microamp == microamp)
4778 return array[i].reg_val;
4779 }
4780
4781 return -EINVAL;
4782 }
4783
4784 /**
4785 * ksz_drive_strength_error() - Report invalid drive strength value
4786 * @dev: ksz device
4787 * @array: The array of drive strength values to search.
4788 * @array_size: The size of the array.
4789 * @microamp: Invalid drive strength value in microamp
4790 *
4791 * This function logs an error message when an unsupported drive strength value
4792 * is detected. It lists out all the supported drive strength values for
4793 * reference in the error message.
4794 */
ksz_drive_strength_error(struct ksz_device * dev,const struct ksz_drive_strength * array,size_t array_size,int microamp)4795 static void ksz_drive_strength_error(struct ksz_device *dev,
4796 const struct ksz_drive_strength *array,
4797 size_t array_size, int microamp)
4798 {
4799 char supported_values[100];
4800 size_t remaining_size;
4801 int added_len;
4802 char *ptr;
4803 int i;
4804
4805 remaining_size = sizeof(supported_values);
4806 ptr = supported_values;
4807
4808 for (i = 0; i < array_size; i++) {
4809 added_len = snprintf(ptr, remaining_size,
4810 i == 0 ? "%d" : ", %d", array[i].microamp);
4811
4812 if (added_len >= remaining_size)
4813 break;
4814
4815 ptr += added_len;
4816 remaining_size -= added_len;
4817 }
4818
4819 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n",
4820 microamp, supported_values);
4821 }
4822
4823 /**
4824 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477
4825 * chip variants.
4826 * @dev: ksz device
4827 * @props: Array of drive strength properties to be applied
4828 * @num_props: Number of properties in the array
4829 *
4830 * This function configures the drive strength for various KSZ9477 chip variants
4831 * based on the provided properties. It handles chip-specific nuances and
4832 * ensures only valid drive strengths are written to the respective chip.
4833 *
4834 * Return: 0 on successful configuration, a negative error code on failure.
4835 */
ksz9477_drive_strength_write(struct ksz_device * dev,struct ksz_driver_strength_prop * props,int num_props)4836 static int ksz9477_drive_strength_write(struct ksz_device *dev,
4837 struct ksz_driver_strength_prop *props,
4838 int num_props)
4839 {
4840 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths);
4841 int i, ret, reg;
4842 u8 mask = 0;
4843 u8 val = 0;
4844
4845 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1)
4846 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
4847 props[KSZ_DRIVER_STRENGTH_IO].name);
4848
4849 if (dev->chip_id == KSZ8795_CHIP_ID ||
4850 dev->chip_id == KSZ8794_CHIP_ID ||
4851 dev->chip_id == KSZ8765_CHIP_ID)
4852 reg = KSZ8795_REG_SW_CTRL_20;
4853 else
4854 reg = KSZ9477_REG_SW_IO_STRENGTH;
4855
4856 for (i = 0; i < num_props; i++) {
4857 if (props[i].value == -1)
4858 continue;
4859
4860 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths,
4861 array_size, props[i].value);
4862 if (ret < 0) {
4863 ksz_drive_strength_error(dev, ksz9477_drive_strengths,
4864 array_size, props[i].value);
4865 return ret;
4866 }
4867
4868 mask |= SW_DRIVE_STRENGTH_M << props[i].offset;
4869 val |= ret << props[i].offset;
4870 }
4871
4872 return ksz_rmw8(dev, reg, mask, val);
4873 }
4874
4875 /**
4876 * ksz88x3_drive_strength_write() - Set the drive strength configuration for
4877 * KSZ8863 compatible chip variants.
4878 * @dev: ksz device
4879 * @props: Array of drive strength properties to be set
4880 * @num_props: Number of properties in the array
4881 *
4882 * This function applies the specified drive strength settings to KSZ88X3 chip
4883 * variants (KSZ8873, KSZ8863).
4884 * It ensures the configurations align with what the chip variant supports and
4885 * warns or errors out on unsupported settings.
4886 *
4887 * Return: 0 on success, error code otherwise
4888 */
ksz88x3_drive_strength_write(struct ksz_device * dev,struct ksz_driver_strength_prop * props,int num_props)4889 static int ksz88x3_drive_strength_write(struct ksz_device *dev,
4890 struct ksz_driver_strength_prop *props,
4891 int num_props)
4892 {
4893 size_t array_size = ARRAY_SIZE(ksz88x3_drive_strengths);
4894 int microamp;
4895 int i, ret;
4896
4897 for (i = 0; i < num_props; i++) {
4898 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO)
4899 continue;
4900
4901 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
4902 props[i].name);
4903 }
4904
4905 microamp = props[KSZ_DRIVER_STRENGTH_IO].value;
4906 ret = ksz_drive_strength_to_reg(ksz88x3_drive_strengths, array_size,
4907 microamp);
4908 if (ret < 0) {
4909 ksz_drive_strength_error(dev, ksz88x3_drive_strengths,
4910 array_size, microamp);
4911 return ret;
4912 }
4913
4914 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12,
4915 KSZ8873_DRIVE_STRENGTH_16MA, ret);
4916 }
4917
4918 /**
4919 * ksz_parse_drive_strength() - Extract and apply drive strength configurations
4920 * from device tree properties.
4921 * @dev: ksz device
4922 *
4923 * This function reads the specified drive strength properties from the
4924 * device tree, validates against the supported chip variants, and sets
4925 * them accordingly. An error should be critical here, as the drive strength
4926 * settings are crucial for EMI compliance.
4927 *
4928 * Return: 0 on success, error code otherwise
4929 */
ksz_parse_drive_strength(struct ksz_device * dev)4930 static int ksz_parse_drive_strength(struct ksz_device *dev)
4931 {
4932 struct ksz_driver_strength_prop of_props[] = {
4933 [KSZ_DRIVER_STRENGTH_HI] = {
4934 .name = "microchip,hi-drive-strength-microamp",
4935 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S,
4936 .value = -1,
4937 },
4938 [KSZ_DRIVER_STRENGTH_LO] = {
4939 .name = "microchip,lo-drive-strength-microamp",
4940 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S,
4941 .value = -1,
4942 },
4943 [KSZ_DRIVER_STRENGTH_IO] = {
4944 .name = "microchip,io-drive-strength-microamp",
4945 .offset = 0, /* don't care */
4946 .value = -1,
4947 },
4948 };
4949 struct device_node *np = dev->dev->of_node;
4950 bool have_any_prop = false;
4951 int i, ret;
4952
4953 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
4954 ret = of_property_read_u32(np, of_props[i].name,
4955 &of_props[i].value);
4956 if (ret && ret != -EINVAL)
4957 dev_warn(dev->dev, "Failed to read %s\n",
4958 of_props[i].name);
4959 if (ret)
4960 continue;
4961
4962 have_any_prop = true;
4963 }
4964
4965 if (!have_any_prop)
4966 return 0;
4967
4968 switch (dev->chip_id) {
4969 case KSZ88X3_CHIP_ID:
4970 return ksz88x3_drive_strength_write(dev, of_props,
4971 ARRAY_SIZE(of_props));
4972 case KSZ8795_CHIP_ID:
4973 case KSZ8794_CHIP_ID:
4974 case KSZ8765_CHIP_ID:
4975 case KSZ8563_CHIP_ID:
4976 case KSZ8567_CHIP_ID:
4977 case KSZ9477_CHIP_ID:
4978 case KSZ9563_CHIP_ID:
4979 case KSZ9567_CHIP_ID:
4980 case KSZ9893_CHIP_ID:
4981 case KSZ9896_CHIP_ID:
4982 case KSZ9897_CHIP_ID:
4983 case LAN9646_CHIP_ID:
4984 return ksz9477_drive_strength_write(dev, of_props,
4985 ARRAY_SIZE(of_props));
4986 default:
4987 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
4988 if (of_props[i].value == -1)
4989 continue;
4990
4991 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
4992 of_props[i].name);
4993 }
4994 }
4995
4996 return 0;
4997 }
4998
ksz_switch_register(struct ksz_device * dev)4999 int ksz_switch_register(struct ksz_device *dev)
5000 {
5001 const struct ksz_chip_data *info;
5002 struct device_node *ports;
5003 phy_interface_t interface;
5004 unsigned int port_num;
5005 int ret;
5006 int i;
5007
5008 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset",
5009 GPIOD_OUT_LOW);
5010 if (IS_ERR(dev->reset_gpio))
5011 return PTR_ERR(dev->reset_gpio);
5012
5013 if (dev->reset_gpio) {
5014 gpiod_set_value_cansleep(dev->reset_gpio, 1);
5015 usleep_range(10000, 12000);
5016 gpiod_set_value_cansleep(dev->reset_gpio, 0);
5017 msleep(100);
5018 }
5019
5020 mutex_init(&dev->dev_mutex);
5021 mutex_init(&dev->regmap_mutex);
5022 mutex_init(&dev->alu_mutex);
5023 mutex_init(&dev->vlan_mutex);
5024
5025 ret = ksz_switch_detect(dev);
5026 if (ret)
5027 return ret;
5028
5029 info = ksz_lookup_info(dev->chip_id);
5030 if (!info)
5031 return -ENODEV;
5032
5033 /* Update the compatible info with the probed one */
5034 dev->info = info;
5035
5036 dev_info(dev->dev, "found switch: %s, rev %i\n",
5037 dev->info->dev_name, dev->chip_rev);
5038
5039 ret = ksz_check_device_id(dev);
5040 if (ret)
5041 return ret;
5042
5043 dev->dev_ops = dev->info->ops;
5044
5045 ret = dev->dev_ops->init(dev);
5046 if (ret)
5047 return ret;
5048
5049 dev->ports = devm_kzalloc(dev->dev,
5050 dev->info->port_cnt * sizeof(struct ksz_port),
5051 GFP_KERNEL);
5052 if (!dev->ports)
5053 return -ENOMEM;
5054
5055 for (i = 0; i < dev->info->port_cnt; i++) {
5056 spin_lock_init(&dev->ports[i].mib.stats64_lock);
5057 mutex_init(&dev->ports[i].mib.cnt_mutex);
5058 dev->ports[i].mib.counters =
5059 devm_kzalloc(dev->dev,
5060 sizeof(u64) * (dev->info->mib_cnt + 1),
5061 GFP_KERNEL);
5062 if (!dev->ports[i].mib.counters)
5063 return -ENOMEM;
5064
5065 dev->ports[i].ksz_dev = dev;
5066 dev->ports[i].num = i;
5067 }
5068
5069 /* set the real number of ports */
5070 dev->ds->num_ports = dev->info->port_cnt;
5071
5072 /* set the phylink ops */
5073 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops;
5074
5075 /* Host port interface will be self detected, or specifically set in
5076 * device tree.
5077 */
5078 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
5079 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
5080 if (dev->dev->of_node) {
5081 ret = of_get_phy_mode(dev->dev->of_node, &interface);
5082 if (ret == 0)
5083 dev->compat_interface = interface;
5084 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports");
5085 if (!ports)
5086 ports = of_get_child_by_name(dev->dev->of_node, "ports");
5087 if (ports) {
5088 for_each_available_child_of_node_scoped(ports, port) {
5089 if (of_property_read_u32(port, "reg",
5090 &port_num))
5091 continue;
5092 if (!(dev->port_mask & BIT(port_num))) {
5093 of_node_put(ports);
5094 return -EINVAL;
5095 }
5096 of_get_phy_mode(port,
5097 &dev->ports[port_num].interface);
5098
5099 ksz_parse_rgmii_delay(dev, port_num, port);
5100 }
5101 of_node_put(ports);
5102 }
5103 dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
5104 "microchip,synclko-125");
5105 dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
5106 "microchip,synclko-disable");
5107 if (dev->synclko_125 && dev->synclko_disable) {
5108 dev_err(dev->dev, "inconsistent synclko settings\n");
5109 return -EINVAL;
5110 }
5111
5112 dev->wakeup_source = of_property_read_bool(dev->dev->of_node,
5113 "wakeup-source");
5114 dev->pme_active_high = of_property_read_bool(dev->dev->of_node,
5115 "microchip,pme-active-high");
5116 }
5117
5118 ret = dsa_register_switch(dev->ds);
5119 if (ret) {
5120 dev->dev_ops->exit(dev);
5121 return ret;
5122 }
5123
5124 /* Read MIB counters every 30 seconds to avoid overflow. */
5125 dev->mib_read_interval = msecs_to_jiffies(5000);
5126
5127 /* Start the MIB timer. */
5128 schedule_delayed_work(&dev->mib_read, 0);
5129
5130 return ret;
5131 }
5132 EXPORT_SYMBOL(ksz_switch_register);
5133
ksz_switch_remove(struct ksz_device * dev)5134 void ksz_switch_remove(struct ksz_device *dev)
5135 {
5136 /* timer started */
5137 if (dev->mib_read_interval) {
5138 dev->mib_read_interval = 0;
5139 cancel_delayed_work_sync(&dev->mib_read);
5140 }
5141
5142 dev->dev_ops->exit(dev);
5143 dsa_unregister_switch(dev->ds);
5144
5145 if (dev->reset_gpio)
5146 gpiod_set_value_cansleep(dev->reset_gpio, 1);
5147
5148 }
5149 EXPORT_SYMBOL(ksz_switch_remove);
5150
5151 #ifdef CONFIG_PM_SLEEP
ksz_switch_suspend(struct device * dev)5152 int ksz_switch_suspend(struct device *dev)
5153 {
5154 struct ksz_device *priv = dev_get_drvdata(dev);
5155
5156 return dsa_switch_suspend(priv->ds);
5157 }
5158 EXPORT_SYMBOL(ksz_switch_suspend);
5159
ksz_switch_resume(struct device * dev)5160 int ksz_switch_resume(struct device *dev)
5161 {
5162 struct ksz_device *priv = dev_get_drvdata(dev);
5163
5164 return dsa_switch_resume(priv->ds);
5165 }
5166 EXPORT_SYMBOL(ksz_switch_resume);
5167 #endif
5168
5169 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
5170 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
5171 MODULE_LICENSE("GPL");
5172