1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip switch driver main logic 4 * 5 * Copyright (C) 2017-2025 Microchip Technology Inc. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/dsa/ksz_common.h> 10 #include <linux/export.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/platform_data/microchip-ksz.h> 15 #include <linux/phy.h> 16 #include <linux/etherdevice.h> 17 #include <linux/if_bridge.h> 18 #include <linux/if_vlan.h> 19 #include <linux/if_hsr.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/of.h> 23 #include <linux/of_mdio.h> 24 #include <linux/of_net.h> 25 #include <linux/micrel_phy.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <net/dsa.h> 28 #include <net/ieee8021q.h> 29 #include <net/pkt_cls.h> 30 #include <net/switchdev.h> 31 32 #include "ksz_common.h" 33 #include "ksz_dcb.h" 34 #include "ksz_ptp.h" 35 #include "ksz8.h" 36 #include "ksz9477.h" 37 #include "lan937x.h" 38 39 #define MIB_COUNTER_NUM 0x20 40 41 struct ksz_stats_raw { 42 u64 rx_hi; 43 u64 rx_undersize; 44 u64 rx_fragments; 45 u64 rx_oversize; 46 u64 rx_jabbers; 47 u64 rx_symbol_err; 48 u64 rx_crc_err; 49 u64 rx_align_err; 50 u64 rx_mac_ctrl; 51 u64 rx_pause; 52 u64 rx_bcast; 53 u64 rx_mcast; 54 u64 rx_ucast; 55 u64 rx_64_or_less; 56 u64 rx_65_127; 57 u64 rx_128_255; 58 u64 rx_256_511; 59 u64 rx_512_1023; 60 u64 rx_1024_1522; 61 u64 rx_1523_2000; 62 u64 rx_2001; 63 u64 tx_hi; 64 u64 tx_late_col; 65 u64 tx_pause; 66 u64 tx_bcast; 67 u64 tx_mcast; 68 u64 tx_ucast; 69 u64 tx_deferred; 70 u64 tx_total_col; 71 u64 tx_exc_col; 72 u64 tx_single_col; 73 u64 tx_mult_col; 74 u64 rx_total; 75 u64 tx_total; 76 u64 rx_discards; 77 u64 tx_discards; 78 }; 79 80 struct ksz88xx_stats_raw { 81 u64 rx; 82 u64 rx_hi; 83 u64 rx_undersize; 84 u64 rx_fragments; 85 u64 rx_oversize; 86 u64 rx_jabbers; 87 u64 rx_symbol_err; 88 u64 rx_crc_err; 89 u64 rx_align_err; 90 u64 rx_mac_ctrl; 91 u64 rx_pause; 92 u64 rx_bcast; 93 u64 rx_mcast; 94 u64 rx_ucast; 95 u64 rx_64_or_less; 96 u64 rx_65_127; 97 u64 rx_128_255; 98 u64 rx_256_511; 99 u64 rx_512_1023; 100 u64 rx_1024_1522; 101 u64 tx; 102 u64 tx_hi; 103 u64 tx_late_col; 104 u64 tx_pause; 105 u64 tx_bcast; 106 u64 tx_mcast; 107 u64 tx_ucast; 108 u64 tx_deferred; 109 u64 tx_total_col; 110 u64 tx_exc_col; 111 u64 tx_single_col; 112 u64 tx_mult_col; 113 u64 rx_discards; 114 u64 tx_discards; 115 }; 116 117 static const struct ksz_mib_names ksz88xx_mib_names[] = { 118 { 0x00, "rx" }, 119 { 0x01, "rx_hi" }, 120 { 0x02, "rx_undersize" }, 121 { 0x03, "rx_fragments" }, 122 { 0x04, "rx_oversize" }, 123 { 0x05, "rx_jabbers" }, 124 { 0x06, "rx_symbol_err" }, 125 { 0x07, "rx_crc_err" }, 126 { 0x08, "rx_align_err" }, 127 { 0x09, "rx_mac_ctrl" }, 128 { 0x0a, "rx_pause" }, 129 { 0x0b, "rx_bcast" }, 130 { 0x0c, "rx_mcast" }, 131 { 0x0d, "rx_ucast" }, 132 { 0x0e, "rx_64_or_less" }, 133 { 0x0f, "rx_65_127" }, 134 { 0x10, "rx_128_255" }, 135 { 0x11, "rx_256_511" }, 136 { 0x12, "rx_512_1023" }, 137 { 0x13, "rx_1024_1522" }, 138 { 0x14, "tx" }, 139 { 0x15, "tx_hi" }, 140 { 0x16, "tx_late_col" }, 141 { 0x17, "tx_pause" }, 142 { 0x18, "tx_bcast" }, 143 { 0x19, "tx_mcast" }, 144 { 0x1a, "tx_ucast" }, 145 { 0x1b, "tx_deferred" }, 146 { 0x1c, "tx_total_col" }, 147 { 0x1d, "tx_exc_col" }, 148 { 0x1e, "tx_single_col" }, 149 { 0x1f, "tx_mult_col" }, 150 { 0x100, "rx_discards" }, 151 { 0x101, "tx_discards" }, 152 }; 153 154 static const struct ksz_mib_names ksz9477_mib_names[] = { 155 { 0x00, "rx_hi" }, 156 { 0x01, "rx_undersize" }, 157 { 0x02, "rx_fragments" }, 158 { 0x03, "rx_oversize" }, 159 { 0x04, "rx_jabbers" }, 160 { 0x05, "rx_symbol_err" }, 161 { 0x06, "rx_crc_err" }, 162 { 0x07, "rx_align_err" }, 163 { 0x08, "rx_mac_ctrl" }, 164 { 0x09, "rx_pause" }, 165 { 0x0A, "rx_bcast" }, 166 { 0x0B, "rx_mcast" }, 167 { 0x0C, "rx_ucast" }, 168 { 0x0D, "rx_64_or_less" }, 169 { 0x0E, "rx_65_127" }, 170 { 0x0F, "rx_128_255" }, 171 { 0x10, "rx_256_511" }, 172 { 0x11, "rx_512_1023" }, 173 { 0x12, "rx_1024_1522" }, 174 { 0x13, "rx_1523_2000" }, 175 { 0x14, "rx_2001" }, 176 { 0x15, "tx_hi" }, 177 { 0x16, "tx_late_col" }, 178 { 0x17, "tx_pause" }, 179 { 0x18, "tx_bcast" }, 180 { 0x19, "tx_mcast" }, 181 { 0x1A, "tx_ucast" }, 182 { 0x1B, "tx_deferred" }, 183 { 0x1C, "tx_total_col" }, 184 { 0x1D, "tx_exc_col" }, 185 { 0x1E, "tx_single_col" }, 186 { 0x1F, "tx_mult_col" }, 187 { 0x80, "rx_total" }, 188 { 0x81, "tx_total" }, 189 { 0x82, "rx_discards" }, 190 { 0x83, "tx_discards" }, 191 }; 192 193 struct ksz_driver_strength_prop { 194 const char *name; 195 int offset; 196 int value; 197 }; 198 199 enum ksz_driver_strength_type { 200 KSZ_DRIVER_STRENGTH_HI, 201 KSZ_DRIVER_STRENGTH_LO, 202 KSZ_DRIVER_STRENGTH_IO, 203 }; 204 205 /** 206 * struct ksz_drive_strength - drive strength mapping 207 * @reg_val: register value 208 * @microamp: microamp value 209 */ 210 struct ksz_drive_strength { 211 u32 reg_val; 212 u32 microamp; 213 }; 214 215 /* ksz9477_drive_strengths - Drive strength mapping for KSZ9477 variants 216 * 217 * This values are not documented in KSZ9477 variants but confirmed by 218 * Microchip that KSZ9477, KSZ9567, KSZ8567, KSZ9897, KSZ9896, KSZ9563, KSZ9893 219 * and KSZ8563 are using same register (drive strength) settings like KSZ8795. 220 * 221 * Documentation in KSZ8795CLX provides more information with some 222 * recommendations: 223 * - for high speed signals 224 * 1. 4 mA or 8 mA is often used for MII, RMII, and SPI interface with using 225 * 2.5V or 3.3V VDDIO. 226 * 2. 12 mA or 16 mA is often used for MII, RMII, and SPI interface with 227 * using 1.8V VDDIO. 228 * 3. 20 mA or 24 mA is often used for GMII/RGMII interface with using 2.5V 229 * or 3.3V VDDIO. 230 * 4. 28 mA is often used for GMII/RGMII interface with using 1.8V VDDIO. 231 * 5. In same interface, the heavy loading should use higher one of the 232 * drive current strength. 233 * - for low speed signals 234 * 1. 3.3V VDDIO, use either 4 mA or 8 mA. 235 * 2. 2.5V VDDIO, use either 8 mA or 12 mA. 236 * 3. 1.8V VDDIO, use either 12 mA or 16 mA. 237 * 4. If it is heavy loading, can use higher drive current strength. 238 */ 239 static const struct ksz_drive_strength ksz9477_drive_strengths[] = { 240 { SW_DRIVE_STRENGTH_2MA, 2000 }, 241 { SW_DRIVE_STRENGTH_4MA, 4000 }, 242 { SW_DRIVE_STRENGTH_8MA, 8000 }, 243 { SW_DRIVE_STRENGTH_12MA, 12000 }, 244 { SW_DRIVE_STRENGTH_16MA, 16000 }, 245 { SW_DRIVE_STRENGTH_20MA, 20000 }, 246 { SW_DRIVE_STRENGTH_24MA, 24000 }, 247 { SW_DRIVE_STRENGTH_28MA, 28000 }, 248 }; 249 250 /* ksz88x3_drive_strengths - Drive strength mapping for KSZ8863, KSZ8873, .. 251 * variants. 252 * This values are documented in KSZ8873 and KSZ8863 datasheets. 253 */ 254 static const struct ksz_drive_strength ksz88x3_drive_strengths[] = { 255 { 0, 8000 }, 256 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 }, 257 }; 258 259 static void ksz88x3_phylink_mac_config(struct phylink_config *config, 260 unsigned int mode, 261 const struct phylink_link_state *state); 262 static void ksz_phylink_mac_config(struct phylink_config *config, 263 unsigned int mode, 264 const struct phylink_link_state *state); 265 static void ksz_phylink_mac_link_down(struct phylink_config *config, 266 unsigned int mode, 267 phy_interface_t interface); 268 269 /** 270 * ksz_phylink_mac_disable_tx_lpi() - Callback to signal LPI support (Dummy) 271 * @config: phylink config structure 272 * 273 * This function is a dummy handler. See ksz_phylink_mac_enable_tx_lpi() for 274 * a detailed explanation of EEE/LPI handling in KSZ switches. 275 */ 276 static void ksz_phylink_mac_disable_tx_lpi(struct phylink_config *config) 277 { 278 } 279 280 /** 281 * ksz_phylink_mac_enable_tx_lpi() - Callback to signal LPI support (Dummy) 282 * @config: phylink config structure 283 * @timer: timer value before entering LPI (unused) 284 * @tx_clock_stop: whether to stop the TX clock in LPI mode (unused) 285 * 286 * This function signals to phylink that the driver architecture supports 287 * LPI management, enabling phylink to control EEE advertisement during 288 * negotiation according to IEEE Std 802.3 (Clause 78). 289 * 290 * Hardware Management of EEE/LPI State: 291 * For KSZ switch ports with integrated PHYs (e.g., KSZ9893R ports 1-2), 292 * observation and testing suggest that the actual EEE / Low Power Idle (LPI) 293 * state transitions are managed autonomously by the hardware based on 294 * the auto-negotiation results. (Note: While the datasheet describes EEE 295 * operation based on negotiation, it doesn't explicitly detail the internal 296 * MAC/PHY interaction, so autonomous hardware management of the MAC state 297 * for LPI is inferred from observed behavior). 298 * This hardware control, consistent with the switch's ability to operate 299 * autonomously via strapping, means MAC-level software intervention is not 300 * required or exposed for managing the LPI state once EEE is negotiated. 301 * (Ref: KSZ9893R Data Sheet DS00002420D, primarily Section 4.7.5 explaining 302 * EEE, also Sections 4.1.7 on Auto-Negotiation and 3.2.1 on Configuration 303 * Straps). 304 * 305 * Additionally, ports configured as MAC interfaces (e.g., KSZ9893R port 3) 306 * lack documented MAC-level LPI control. 307 * 308 * Therefore, this callback performs no action and serves primarily to inform 309 * phylink of LPI awareness and to document the inferred hardware behavior. 310 * 311 * Returns: 0 (Always success) 312 */ 313 static int ksz_phylink_mac_enable_tx_lpi(struct phylink_config *config, 314 u32 timer, bool tx_clock_stop) 315 { 316 return 0; 317 } 318 319 static const struct phylink_mac_ops ksz88x3_phylink_mac_ops = { 320 .mac_config = ksz88x3_phylink_mac_config, 321 .mac_link_down = ksz_phylink_mac_link_down, 322 .mac_link_up = ksz8_phylink_mac_link_up, 323 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 324 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 325 }; 326 327 static const struct phylink_mac_ops ksz8_phylink_mac_ops = { 328 .mac_config = ksz_phylink_mac_config, 329 .mac_link_down = ksz_phylink_mac_link_down, 330 .mac_link_up = ksz8_phylink_mac_link_up, 331 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 332 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 333 }; 334 335 static const struct ksz_dev_ops ksz8463_dev_ops = { 336 .setup = ksz8_setup, 337 .get_port_addr = ksz8463_get_port_addr, 338 .cfg_port_member = ksz8_cfg_port_member, 339 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 340 .port_setup = ksz8_port_setup, 341 .r_phy = ksz8463_r_phy, 342 .w_phy = ksz8463_w_phy, 343 .r_mib_cnt = ksz8_r_mib_cnt, 344 .r_mib_pkt = ksz8_r_mib_pkt, 345 .r_mib_stat64 = ksz88xx_r_mib_stats64, 346 .freeze_mib = ksz8_freeze_mib, 347 .port_init_cnt = ksz8_port_init_cnt, 348 .fdb_dump = ksz8_fdb_dump, 349 .fdb_add = ksz8_fdb_add, 350 .fdb_del = ksz8_fdb_del, 351 .mdb_add = ksz8_mdb_add, 352 .mdb_del = ksz8_mdb_del, 353 .vlan_filtering = ksz8_port_vlan_filtering, 354 .vlan_add = ksz8_port_vlan_add, 355 .vlan_del = ksz8_port_vlan_del, 356 .mirror_add = ksz8_port_mirror_add, 357 .mirror_del = ksz8_port_mirror_del, 358 .get_caps = ksz8_get_caps, 359 .config_cpu_port = ksz8_config_cpu_port, 360 .enable_stp_addr = ksz8_enable_stp_addr, 361 .reset = ksz8_reset_switch, 362 .init = ksz8_switch_init, 363 .exit = ksz8_switch_exit, 364 .change_mtu = ksz8_change_mtu, 365 }; 366 367 static const struct ksz_dev_ops ksz88xx_dev_ops = { 368 .setup = ksz8_setup, 369 .get_port_addr = ksz8_get_port_addr, 370 .cfg_port_member = ksz8_cfg_port_member, 371 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 372 .port_setup = ksz8_port_setup, 373 .r_phy = ksz8_r_phy, 374 .w_phy = ksz8_w_phy, 375 .r_mib_cnt = ksz8_r_mib_cnt, 376 .r_mib_pkt = ksz8_r_mib_pkt, 377 .r_mib_stat64 = ksz88xx_r_mib_stats64, 378 .freeze_mib = ksz8_freeze_mib, 379 .port_init_cnt = ksz8_port_init_cnt, 380 .fdb_dump = ksz8_fdb_dump, 381 .fdb_add = ksz8_fdb_add, 382 .fdb_del = ksz8_fdb_del, 383 .mdb_add = ksz8_mdb_add, 384 .mdb_del = ksz8_mdb_del, 385 .vlan_filtering = ksz8_port_vlan_filtering, 386 .vlan_add = ksz8_port_vlan_add, 387 .vlan_del = ksz8_port_vlan_del, 388 .mirror_add = ksz8_port_mirror_add, 389 .mirror_del = ksz8_port_mirror_del, 390 .get_caps = ksz8_get_caps, 391 .config_cpu_port = ksz8_config_cpu_port, 392 .enable_stp_addr = ksz8_enable_stp_addr, 393 .reset = ksz8_reset_switch, 394 .init = ksz8_switch_init, 395 .exit = ksz8_switch_exit, 396 .change_mtu = ksz8_change_mtu, 397 .pme_write8 = ksz8_pme_write8, 398 .pme_pread8 = ksz8_pme_pread8, 399 .pme_pwrite8 = ksz8_pme_pwrite8, 400 }; 401 402 static const struct ksz_dev_ops ksz87xx_dev_ops = { 403 .setup = ksz8_setup, 404 .get_port_addr = ksz8_get_port_addr, 405 .cfg_port_member = ksz8_cfg_port_member, 406 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 407 .port_setup = ksz8_port_setup, 408 .r_phy = ksz8_r_phy, 409 .w_phy = ksz8_w_phy, 410 .r_mib_cnt = ksz8_r_mib_cnt, 411 .r_mib_pkt = ksz8_r_mib_pkt, 412 .r_mib_stat64 = ksz_r_mib_stats64, 413 .freeze_mib = ksz8_freeze_mib, 414 .port_init_cnt = ksz8_port_init_cnt, 415 .fdb_dump = ksz8_fdb_dump, 416 .fdb_add = ksz8_fdb_add, 417 .fdb_del = ksz8_fdb_del, 418 .mdb_add = ksz8_mdb_add, 419 .mdb_del = ksz8_mdb_del, 420 .vlan_filtering = ksz8_port_vlan_filtering, 421 .vlan_add = ksz8_port_vlan_add, 422 .vlan_del = ksz8_port_vlan_del, 423 .mirror_add = ksz8_port_mirror_add, 424 .mirror_del = ksz8_port_mirror_del, 425 .get_caps = ksz8_get_caps, 426 .config_cpu_port = ksz8_config_cpu_port, 427 .enable_stp_addr = ksz8_enable_stp_addr, 428 .reset = ksz8_reset_switch, 429 .init = ksz8_switch_init, 430 .exit = ksz8_switch_exit, 431 .change_mtu = ksz8_change_mtu, 432 .pme_write8 = ksz8_pme_write8, 433 .pme_pread8 = ksz8_pme_pread8, 434 .pme_pwrite8 = ksz8_pme_pwrite8, 435 }; 436 437 static void ksz9477_phylink_mac_link_up(struct phylink_config *config, 438 struct phy_device *phydev, 439 unsigned int mode, 440 phy_interface_t interface, 441 int speed, int duplex, bool tx_pause, 442 bool rx_pause); 443 444 static struct phylink_pcs * 445 ksz_phylink_mac_select_pcs(struct phylink_config *config, 446 phy_interface_t interface) 447 { 448 struct dsa_port *dp = dsa_phylink_to_port(config); 449 struct ksz_device *dev = dp->ds->priv; 450 struct ksz_port *p = &dev->ports[dp->index]; 451 452 if (ksz_is_sgmii_port(dev, dp->index) && 453 (interface == PHY_INTERFACE_MODE_SGMII || 454 interface == PHY_INTERFACE_MODE_1000BASEX)) 455 return p->pcs; 456 457 return NULL; 458 } 459 460 static const struct phylink_mac_ops ksz9477_phylink_mac_ops = { 461 .mac_config = ksz_phylink_mac_config, 462 .mac_link_down = ksz_phylink_mac_link_down, 463 .mac_link_up = ksz9477_phylink_mac_link_up, 464 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 465 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 466 .mac_select_pcs = ksz_phylink_mac_select_pcs, 467 }; 468 469 static const struct ksz_dev_ops ksz9477_dev_ops = { 470 .setup = ksz9477_setup, 471 .get_port_addr = ksz9477_get_port_addr, 472 .cfg_port_member = ksz9477_cfg_port_member, 473 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 474 .port_setup = ksz9477_port_setup, 475 .set_ageing_time = ksz9477_set_ageing_time, 476 .r_phy = ksz9477_r_phy, 477 .w_phy = ksz9477_w_phy, 478 .r_mib_cnt = ksz9477_r_mib_cnt, 479 .r_mib_pkt = ksz9477_r_mib_pkt, 480 .r_mib_stat64 = ksz_r_mib_stats64, 481 .freeze_mib = ksz9477_freeze_mib, 482 .port_init_cnt = ksz9477_port_init_cnt, 483 .vlan_filtering = ksz9477_port_vlan_filtering, 484 .vlan_add = ksz9477_port_vlan_add, 485 .vlan_del = ksz9477_port_vlan_del, 486 .mirror_add = ksz9477_port_mirror_add, 487 .mirror_del = ksz9477_port_mirror_del, 488 .get_caps = ksz9477_get_caps, 489 .fdb_dump = ksz9477_fdb_dump, 490 .fdb_add = ksz9477_fdb_add, 491 .fdb_del = ksz9477_fdb_del, 492 .mdb_add = ksz9477_mdb_add, 493 .mdb_del = ksz9477_mdb_del, 494 .change_mtu = ksz9477_change_mtu, 495 .pme_write8 = ksz_write8, 496 .pme_pread8 = ksz_pread8, 497 .pme_pwrite8 = ksz_pwrite8, 498 .config_cpu_port = ksz9477_config_cpu_port, 499 .tc_cbs_set_cinc = ksz9477_tc_cbs_set_cinc, 500 .enable_stp_addr = ksz9477_enable_stp_addr, 501 .reset = ksz9477_reset_switch, 502 .init = ksz9477_switch_init, 503 .exit = ksz9477_switch_exit, 504 .pcs_create = ksz9477_pcs_create, 505 }; 506 507 static const struct phylink_mac_ops lan937x_phylink_mac_ops = { 508 .mac_config = ksz_phylink_mac_config, 509 .mac_link_down = ksz_phylink_mac_link_down, 510 .mac_link_up = ksz9477_phylink_mac_link_up, 511 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 512 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 513 }; 514 515 static const struct ksz_dev_ops lan937x_dev_ops = { 516 .setup = lan937x_setup, 517 .teardown = lan937x_teardown, 518 .get_port_addr = ksz9477_get_port_addr, 519 .cfg_port_member = ksz9477_cfg_port_member, 520 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table, 521 .port_setup = lan937x_port_setup, 522 .set_ageing_time = lan937x_set_ageing_time, 523 .mdio_bus_preinit = lan937x_mdio_bus_preinit, 524 .create_phy_addr_map = lan937x_create_phy_addr_map, 525 .r_phy = lan937x_r_phy, 526 .w_phy = lan937x_w_phy, 527 .r_mib_cnt = ksz9477_r_mib_cnt, 528 .r_mib_pkt = ksz9477_r_mib_pkt, 529 .r_mib_stat64 = ksz_r_mib_stats64, 530 .freeze_mib = ksz9477_freeze_mib, 531 .port_init_cnt = ksz9477_port_init_cnt, 532 .vlan_filtering = ksz9477_port_vlan_filtering, 533 .vlan_add = ksz9477_port_vlan_add, 534 .vlan_del = ksz9477_port_vlan_del, 535 .mirror_add = ksz9477_port_mirror_add, 536 .mirror_del = ksz9477_port_mirror_del, 537 .get_caps = lan937x_phylink_get_caps, 538 .setup_rgmii_delay = lan937x_setup_rgmii_delay, 539 .fdb_dump = ksz9477_fdb_dump, 540 .fdb_add = ksz9477_fdb_add, 541 .fdb_del = ksz9477_fdb_del, 542 .mdb_add = ksz9477_mdb_add, 543 .mdb_del = ksz9477_mdb_del, 544 .change_mtu = lan937x_change_mtu, 545 .config_cpu_port = lan937x_config_cpu_port, 546 .tc_cbs_set_cinc = lan937x_tc_cbs_set_cinc, 547 .enable_stp_addr = ksz9477_enable_stp_addr, 548 .reset = lan937x_reset_switch, 549 .init = lan937x_switch_init, 550 .exit = lan937x_switch_exit, 551 }; 552 553 static const u16 ksz8463_regs[] = { 554 [REG_SW_MAC_ADDR] = 0x10, 555 [REG_IND_CTRL_0] = 0x30, 556 [REG_IND_DATA_8] = 0x26, 557 [REG_IND_DATA_CHECK] = 0x26, 558 [REG_IND_DATA_HI] = 0x28, 559 [REG_IND_DATA_LO] = 0x2C, 560 [REG_IND_MIB_CHECK] = 0x2F, 561 [P_FORCE_CTRL] = 0x0C, 562 [P_LINK_STATUS] = 0x0E, 563 [P_LOCAL_CTRL] = 0x0C, 564 [P_NEG_RESTART_CTRL] = 0x0D, 565 [P_REMOTE_STATUS] = 0x0E, 566 [P_SPEED_STATUS] = 0x0F, 567 [S_TAIL_TAG_CTRL] = 0xAD, 568 [P_STP_CTRL] = 0x6F, 569 [S_START_CTRL] = 0x01, 570 [S_BROADCAST_CTRL] = 0x06, 571 [S_MULTICAST_CTRL] = 0x04, 572 [PTP_CLK_CTRL] = 0x0600, 573 [PTP_RTC_NANOSEC] = 0x0604, 574 [PTP_RTC_SEC] = 0x0608, 575 [PTP_RTC_SUB_NANOSEC] = 0x060C, 576 [PTP_SUBNANOSEC_RATE] = 0x0610, 577 [PTP_MSG_CONF1] = 0x0620, 578 }; 579 580 static const u32 ksz8463_masks[] = { 581 [PORT_802_1P_REMAPPING] = BIT(3), 582 [SW_TAIL_TAG_ENABLE] = BIT(0), 583 [MIB_COUNTER_OVERFLOW] = BIT(7), 584 [MIB_COUNTER_VALID] = BIT(6), 585 [VLAN_TABLE_FID] = GENMASK(15, 12), 586 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 587 [VLAN_TABLE_VALID] = BIT(19), 588 [STATIC_MAC_TABLE_VALID] = BIT(19), 589 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 590 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 591 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 592 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 593 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 594 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 595 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 596 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 597 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 598 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 599 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 600 }; 601 602 static u8 ksz8463_shifts[] = { 603 [VLAN_TABLE_MEMBERSHIP_S] = 16, 604 [STATIC_MAC_FWD_PORTS] = 16, 605 [STATIC_MAC_FID] = 22, 606 [DYNAMIC_MAC_ENTRIES_H] = 8, 607 [DYNAMIC_MAC_ENTRIES] = 24, 608 [DYNAMIC_MAC_FID] = 16, 609 [DYNAMIC_MAC_TIMESTAMP] = 22, 610 [DYNAMIC_MAC_SRC_PORT] = 20, 611 }; 612 613 static const u16 ksz8795_regs[] = { 614 [REG_SW_MAC_ADDR] = 0x68, 615 [REG_IND_CTRL_0] = 0x6E, 616 [REG_IND_DATA_8] = 0x70, 617 [REG_IND_DATA_CHECK] = 0x72, 618 [REG_IND_DATA_HI] = 0x71, 619 [REG_IND_DATA_LO] = 0x75, 620 [REG_IND_MIB_CHECK] = 0x74, 621 [REG_IND_BYTE] = 0xA0, 622 [P_FORCE_CTRL] = 0x0C, 623 [P_LINK_STATUS] = 0x0E, 624 [P_LOCAL_CTRL] = 0x07, 625 [P_NEG_RESTART_CTRL] = 0x0D, 626 [P_REMOTE_STATUS] = 0x08, 627 [P_SPEED_STATUS] = 0x09, 628 [S_TAIL_TAG_CTRL] = 0x0C, 629 [P_STP_CTRL] = 0x02, 630 [S_START_CTRL] = 0x01, 631 [S_BROADCAST_CTRL] = 0x06, 632 [S_MULTICAST_CTRL] = 0x04, 633 [P_XMII_CTRL_0] = 0x06, 634 [P_XMII_CTRL_1] = 0x06, 635 [REG_SW_PME_CTRL] = 0x8003, 636 [REG_PORT_PME_STATUS] = 0x8003, 637 [REG_PORT_PME_CTRL] = 0x8007, 638 }; 639 640 static const u32 ksz8795_masks[] = { 641 [PORT_802_1P_REMAPPING] = BIT(7), 642 [SW_TAIL_TAG_ENABLE] = BIT(1), 643 [MIB_COUNTER_OVERFLOW] = BIT(6), 644 [MIB_COUNTER_VALID] = BIT(5), 645 [VLAN_TABLE_FID] = GENMASK(6, 0), 646 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 647 [VLAN_TABLE_VALID] = BIT(12), 648 [STATIC_MAC_TABLE_VALID] = BIT(21), 649 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 650 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 651 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 652 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 653 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 654 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 655 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 656 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 657 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 658 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 659 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 660 [P_MII_TX_FLOW_CTRL] = BIT(5), 661 [P_MII_RX_FLOW_CTRL] = BIT(5), 662 }; 663 664 static const u8 ksz8795_xmii_ctrl0[] = { 665 [P_MII_100MBIT] = 0, 666 [P_MII_10MBIT] = 1, 667 [P_MII_FULL_DUPLEX] = 0, 668 [P_MII_HALF_DUPLEX] = 1, 669 }; 670 671 static const u8 ksz8795_xmii_ctrl1[] = { 672 [P_RGMII_SEL] = 3, 673 [P_GMII_SEL] = 2, 674 [P_RMII_SEL] = 1, 675 [P_MII_SEL] = 0, 676 [P_GMII_1GBIT] = 1, 677 [P_GMII_NOT_1GBIT] = 0, 678 }; 679 680 static const u8 ksz8795_shifts[] = { 681 [VLAN_TABLE_MEMBERSHIP_S] = 7, 682 [VLAN_TABLE] = 16, 683 [STATIC_MAC_FWD_PORTS] = 16, 684 [STATIC_MAC_FID] = 24, 685 [DYNAMIC_MAC_ENTRIES_H] = 3, 686 [DYNAMIC_MAC_ENTRIES] = 29, 687 [DYNAMIC_MAC_FID] = 16, 688 [DYNAMIC_MAC_TIMESTAMP] = 27, 689 [DYNAMIC_MAC_SRC_PORT] = 24, 690 }; 691 692 static const u16 ksz8863_regs[] = { 693 [REG_SW_MAC_ADDR] = 0x70, 694 [REG_IND_CTRL_0] = 0x79, 695 [REG_IND_DATA_8] = 0x7B, 696 [REG_IND_DATA_CHECK] = 0x7B, 697 [REG_IND_DATA_HI] = 0x7C, 698 [REG_IND_DATA_LO] = 0x80, 699 [REG_IND_MIB_CHECK] = 0x80, 700 [P_FORCE_CTRL] = 0x0C, 701 [P_LINK_STATUS] = 0x0E, 702 [P_LOCAL_CTRL] = 0x0C, 703 [P_NEG_RESTART_CTRL] = 0x0D, 704 [P_REMOTE_STATUS] = 0x0E, 705 [P_SPEED_STATUS] = 0x0F, 706 [S_TAIL_TAG_CTRL] = 0x03, 707 [P_STP_CTRL] = 0x02, 708 [S_START_CTRL] = 0x01, 709 [S_BROADCAST_CTRL] = 0x06, 710 [S_MULTICAST_CTRL] = 0x04, 711 }; 712 713 static const u32 ksz8863_masks[] = { 714 [PORT_802_1P_REMAPPING] = BIT(3), 715 [SW_TAIL_TAG_ENABLE] = BIT(6), 716 [MIB_COUNTER_OVERFLOW] = BIT(7), 717 [MIB_COUNTER_VALID] = BIT(6), 718 [VLAN_TABLE_FID] = GENMASK(15, 12), 719 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 720 [VLAN_TABLE_VALID] = BIT(19), 721 [STATIC_MAC_TABLE_VALID] = BIT(19), 722 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 723 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22), 724 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 725 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 726 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0), 727 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2), 728 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 729 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24), 730 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 731 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 732 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 733 }; 734 735 static u8 ksz8863_shifts[] = { 736 [VLAN_TABLE_MEMBERSHIP_S] = 16, 737 [STATIC_MAC_FWD_PORTS] = 16, 738 [STATIC_MAC_FID] = 22, 739 [DYNAMIC_MAC_ENTRIES_H] = 8, 740 [DYNAMIC_MAC_ENTRIES] = 24, 741 [DYNAMIC_MAC_FID] = 16, 742 [DYNAMIC_MAC_TIMESTAMP] = 22, 743 [DYNAMIC_MAC_SRC_PORT] = 20, 744 }; 745 746 static const u16 ksz8895_regs[] = { 747 [REG_SW_MAC_ADDR] = 0x68, 748 [REG_IND_CTRL_0] = 0x6E, 749 [REG_IND_DATA_8] = 0x70, 750 [REG_IND_DATA_CHECK] = 0x72, 751 [REG_IND_DATA_HI] = 0x71, 752 [REG_IND_DATA_LO] = 0x75, 753 [REG_IND_MIB_CHECK] = 0x75, 754 [P_FORCE_CTRL] = 0x0C, 755 [P_LINK_STATUS] = 0x0E, 756 [P_LOCAL_CTRL] = 0x0C, 757 [P_NEG_RESTART_CTRL] = 0x0D, 758 [P_REMOTE_STATUS] = 0x0E, 759 [P_SPEED_STATUS] = 0x09, 760 [S_TAIL_TAG_CTRL] = 0x0C, 761 [P_STP_CTRL] = 0x02, 762 [S_START_CTRL] = 0x01, 763 [S_BROADCAST_CTRL] = 0x06, 764 [S_MULTICAST_CTRL] = 0x04, 765 }; 766 767 static const u32 ksz8895_masks[] = { 768 [PORT_802_1P_REMAPPING] = BIT(7), 769 [SW_TAIL_TAG_ENABLE] = BIT(1), 770 [MIB_COUNTER_OVERFLOW] = BIT(7), 771 [MIB_COUNTER_VALID] = BIT(6), 772 [VLAN_TABLE_FID] = GENMASK(6, 0), 773 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 774 [VLAN_TABLE_VALID] = BIT(12), 775 [STATIC_MAC_TABLE_VALID] = BIT(21), 776 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 777 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 778 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22), 779 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16), 780 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 781 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 782 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 783 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 784 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16), 785 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 786 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 787 }; 788 789 static const u8 ksz8895_shifts[] = { 790 [VLAN_TABLE_MEMBERSHIP_S] = 7, 791 [VLAN_TABLE] = 13, 792 [STATIC_MAC_FWD_PORTS] = 16, 793 [STATIC_MAC_FID] = 24, 794 [DYNAMIC_MAC_ENTRIES_H] = 3, 795 [DYNAMIC_MAC_ENTRIES] = 29, 796 [DYNAMIC_MAC_FID] = 16, 797 [DYNAMIC_MAC_TIMESTAMP] = 27, 798 [DYNAMIC_MAC_SRC_PORT] = 24, 799 }; 800 801 static const u16 ksz9477_regs[] = { 802 [REG_SW_MAC_ADDR] = 0x0302, 803 [P_STP_CTRL] = 0x0B04, 804 [S_START_CTRL] = 0x0300, 805 [S_BROADCAST_CTRL] = 0x0332, 806 [S_MULTICAST_CTRL] = 0x0331, 807 [P_XMII_CTRL_0] = 0x0300, 808 [P_XMII_CTRL_1] = 0x0301, 809 [REG_SW_PME_CTRL] = 0x0006, 810 [REG_PORT_PME_STATUS] = 0x0013, 811 [REG_PORT_PME_CTRL] = 0x0017, 812 [PTP_CLK_CTRL] = 0x0500, 813 [PTP_RTC_SUB_NANOSEC] = 0x0502, 814 [PTP_RTC_NANOSEC] = 0x0504, 815 [PTP_RTC_SEC] = 0x0508, 816 [PTP_SUBNANOSEC_RATE] = 0x050C, 817 [PTP_MSG_CONF1] = 0x0514, 818 }; 819 820 static const u32 ksz9477_masks[] = { 821 [ALU_STAT_WRITE] = 0, 822 [ALU_STAT_READ] = 1, 823 [ALU_STAT_DIRECT] = 0, 824 [ALU_RESV_MCAST_ADDR] = BIT(1), 825 [P_MII_TX_FLOW_CTRL] = BIT(5), 826 [P_MII_RX_FLOW_CTRL] = BIT(3), 827 }; 828 829 static const u8 ksz9477_shifts[] = { 830 [ALU_STAT_INDEX] = 16, 831 }; 832 833 static const u8 ksz9477_xmii_ctrl0[] = { 834 [P_MII_100MBIT] = 1, 835 [P_MII_10MBIT] = 0, 836 [P_MII_FULL_DUPLEX] = 1, 837 [P_MII_HALF_DUPLEX] = 0, 838 }; 839 840 static const u8 ksz9477_xmii_ctrl1[] = { 841 [P_RGMII_SEL] = 0, 842 [P_RMII_SEL] = 1, 843 [P_GMII_SEL] = 2, 844 [P_MII_SEL] = 3, 845 [P_GMII_1GBIT] = 0, 846 [P_GMII_NOT_1GBIT] = 1, 847 }; 848 849 static const u32 lan937x_masks[] = { 850 [ALU_STAT_WRITE] = 1, 851 [ALU_STAT_READ] = 2, 852 [ALU_STAT_DIRECT] = BIT(3), 853 [ALU_RESV_MCAST_ADDR] = BIT(2), 854 [P_MII_TX_FLOW_CTRL] = BIT(5), 855 [P_MII_RX_FLOW_CTRL] = BIT(3), 856 }; 857 858 static const u8 lan937x_shifts[] = { 859 [ALU_STAT_INDEX] = 8, 860 }; 861 862 static const struct regmap_range ksz8563_valid_regs[] = { 863 regmap_reg_range(0x0000, 0x0003), 864 regmap_reg_range(0x0006, 0x0006), 865 regmap_reg_range(0x000f, 0x001f), 866 regmap_reg_range(0x0100, 0x0100), 867 regmap_reg_range(0x0104, 0x0107), 868 regmap_reg_range(0x010d, 0x010d), 869 regmap_reg_range(0x0110, 0x0113), 870 regmap_reg_range(0x0120, 0x012b), 871 regmap_reg_range(0x0201, 0x0201), 872 regmap_reg_range(0x0210, 0x0213), 873 regmap_reg_range(0x0300, 0x0300), 874 regmap_reg_range(0x0302, 0x031b), 875 regmap_reg_range(0x0320, 0x032b), 876 regmap_reg_range(0x0330, 0x0336), 877 regmap_reg_range(0x0338, 0x033e), 878 regmap_reg_range(0x0340, 0x035f), 879 regmap_reg_range(0x0370, 0x0370), 880 regmap_reg_range(0x0378, 0x0378), 881 regmap_reg_range(0x037c, 0x037d), 882 regmap_reg_range(0x0390, 0x0393), 883 regmap_reg_range(0x0400, 0x040e), 884 regmap_reg_range(0x0410, 0x042f), 885 regmap_reg_range(0x0500, 0x0519), 886 regmap_reg_range(0x0520, 0x054b), 887 regmap_reg_range(0x0550, 0x05b3), 888 889 /* port 1 */ 890 regmap_reg_range(0x1000, 0x1001), 891 regmap_reg_range(0x1004, 0x100b), 892 regmap_reg_range(0x1013, 0x1013), 893 regmap_reg_range(0x1017, 0x1017), 894 regmap_reg_range(0x101b, 0x101b), 895 regmap_reg_range(0x101f, 0x1021), 896 regmap_reg_range(0x1030, 0x1030), 897 regmap_reg_range(0x1100, 0x1111), 898 regmap_reg_range(0x111a, 0x111d), 899 regmap_reg_range(0x1122, 0x1127), 900 regmap_reg_range(0x112a, 0x112b), 901 regmap_reg_range(0x1136, 0x1139), 902 regmap_reg_range(0x113e, 0x113f), 903 regmap_reg_range(0x1400, 0x1401), 904 regmap_reg_range(0x1403, 0x1403), 905 regmap_reg_range(0x1410, 0x1417), 906 regmap_reg_range(0x1420, 0x1423), 907 regmap_reg_range(0x1500, 0x1507), 908 regmap_reg_range(0x1600, 0x1612), 909 regmap_reg_range(0x1800, 0x180f), 910 regmap_reg_range(0x1900, 0x1907), 911 regmap_reg_range(0x1914, 0x191b), 912 regmap_reg_range(0x1a00, 0x1a03), 913 regmap_reg_range(0x1a04, 0x1a08), 914 regmap_reg_range(0x1b00, 0x1b01), 915 regmap_reg_range(0x1b04, 0x1b04), 916 regmap_reg_range(0x1c00, 0x1c05), 917 regmap_reg_range(0x1c08, 0x1c1b), 918 919 /* port 2 */ 920 regmap_reg_range(0x2000, 0x2001), 921 regmap_reg_range(0x2004, 0x200b), 922 regmap_reg_range(0x2013, 0x2013), 923 regmap_reg_range(0x2017, 0x2017), 924 regmap_reg_range(0x201b, 0x201b), 925 regmap_reg_range(0x201f, 0x2021), 926 regmap_reg_range(0x2030, 0x2030), 927 regmap_reg_range(0x2100, 0x2111), 928 regmap_reg_range(0x211a, 0x211d), 929 regmap_reg_range(0x2122, 0x2127), 930 regmap_reg_range(0x212a, 0x212b), 931 regmap_reg_range(0x2136, 0x2139), 932 regmap_reg_range(0x213e, 0x213f), 933 regmap_reg_range(0x2400, 0x2401), 934 regmap_reg_range(0x2403, 0x2403), 935 regmap_reg_range(0x2410, 0x2417), 936 regmap_reg_range(0x2420, 0x2423), 937 regmap_reg_range(0x2500, 0x2507), 938 regmap_reg_range(0x2600, 0x2612), 939 regmap_reg_range(0x2800, 0x280f), 940 regmap_reg_range(0x2900, 0x2907), 941 regmap_reg_range(0x2914, 0x291b), 942 regmap_reg_range(0x2a00, 0x2a03), 943 regmap_reg_range(0x2a04, 0x2a08), 944 regmap_reg_range(0x2b00, 0x2b01), 945 regmap_reg_range(0x2b04, 0x2b04), 946 regmap_reg_range(0x2c00, 0x2c05), 947 regmap_reg_range(0x2c08, 0x2c1b), 948 949 /* port 3 */ 950 regmap_reg_range(0x3000, 0x3001), 951 regmap_reg_range(0x3004, 0x300b), 952 regmap_reg_range(0x3013, 0x3013), 953 regmap_reg_range(0x3017, 0x3017), 954 regmap_reg_range(0x301b, 0x301b), 955 regmap_reg_range(0x301f, 0x3021), 956 regmap_reg_range(0x3030, 0x3030), 957 regmap_reg_range(0x3300, 0x3301), 958 regmap_reg_range(0x3303, 0x3303), 959 regmap_reg_range(0x3400, 0x3401), 960 regmap_reg_range(0x3403, 0x3403), 961 regmap_reg_range(0x3410, 0x3417), 962 regmap_reg_range(0x3420, 0x3423), 963 regmap_reg_range(0x3500, 0x3507), 964 regmap_reg_range(0x3600, 0x3612), 965 regmap_reg_range(0x3800, 0x380f), 966 regmap_reg_range(0x3900, 0x3907), 967 regmap_reg_range(0x3914, 0x391b), 968 regmap_reg_range(0x3a00, 0x3a03), 969 regmap_reg_range(0x3a04, 0x3a08), 970 regmap_reg_range(0x3b00, 0x3b01), 971 regmap_reg_range(0x3b04, 0x3b04), 972 regmap_reg_range(0x3c00, 0x3c05), 973 regmap_reg_range(0x3c08, 0x3c1b), 974 }; 975 976 static const struct regmap_access_table ksz8563_register_set = { 977 .yes_ranges = ksz8563_valid_regs, 978 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs), 979 }; 980 981 static const struct regmap_range ksz9477_valid_regs[] = { 982 regmap_reg_range(0x0000, 0x0003), 983 regmap_reg_range(0x0006, 0x0006), 984 regmap_reg_range(0x0010, 0x001f), 985 regmap_reg_range(0x0100, 0x0100), 986 regmap_reg_range(0x0103, 0x0107), 987 regmap_reg_range(0x010d, 0x010d), 988 regmap_reg_range(0x0110, 0x0113), 989 regmap_reg_range(0x0120, 0x012b), 990 regmap_reg_range(0x0201, 0x0201), 991 regmap_reg_range(0x0210, 0x0213), 992 regmap_reg_range(0x0300, 0x0300), 993 regmap_reg_range(0x0302, 0x031b), 994 regmap_reg_range(0x0320, 0x032b), 995 regmap_reg_range(0x0330, 0x0336), 996 regmap_reg_range(0x0338, 0x033b), 997 regmap_reg_range(0x033e, 0x033e), 998 regmap_reg_range(0x0340, 0x035f), 999 regmap_reg_range(0x0370, 0x0370), 1000 regmap_reg_range(0x0378, 0x0378), 1001 regmap_reg_range(0x037c, 0x037d), 1002 regmap_reg_range(0x0390, 0x0393), 1003 regmap_reg_range(0x0400, 0x040e), 1004 regmap_reg_range(0x0410, 0x042f), 1005 regmap_reg_range(0x0444, 0x044b), 1006 regmap_reg_range(0x0450, 0x046f), 1007 regmap_reg_range(0x0500, 0x0519), 1008 regmap_reg_range(0x0520, 0x054b), 1009 regmap_reg_range(0x0550, 0x05b3), 1010 regmap_reg_range(0x0604, 0x060b), 1011 regmap_reg_range(0x0610, 0x0612), 1012 regmap_reg_range(0x0614, 0x062c), 1013 regmap_reg_range(0x0640, 0x0645), 1014 regmap_reg_range(0x0648, 0x064d), 1015 1016 /* port 1 */ 1017 regmap_reg_range(0x1000, 0x1001), 1018 regmap_reg_range(0x1013, 0x1013), 1019 regmap_reg_range(0x1017, 0x1017), 1020 regmap_reg_range(0x101b, 0x101b), 1021 regmap_reg_range(0x101f, 0x1020), 1022 regmap_reg_range(0x1030, 0x1030), 1023 regmap_reg_range(0x1100, 0x1115), 1024 regmap_reg_range(0x111a, 0x111f), 1025 regmap_reg_range(0x1120, 0x112b), 1026 regmap_reg_range(0x1134, 0x113b), 1027 regmap_reg_range(0x113c, 0x113f), 1028 regmap_reg_range(0x1400, 0x1401), 1029 regmap_reg_range(0x1403, 0x1403), 1030 regmap_reg_range(0x1410, 0x1417), 1031 regmap_reg_range(0x1420, 0x1423), 1032 regmap_reg_range(0x1500, 0x1507), 1033 regmap_reg_range(0x1600, 0x1613), 1034 regmap_reg_range(0x1800, 0x180f), 1035 regmap_reg_range(0x1820, 0x1827), 1036 regmap_reg_range(0x1830, 0x1837), 1037 regmap_reg_range(0x1840, 0x184b), 1038 regmap_reg_range(0x1900, 0x1907), 1039 regmap_reg_range(0x1914, 0x191b), 1040 regmap_reg_range(0x1920, 0x1920), 1041 regmap_reg_range(0x1923, 0x1927), 1042 regmap_reg_range(0x1a00, 0x1a03), 1043 regmap_reg_range(0x1a04, 0x1a07), 1044 regmap_reg_range(0x1b00, 0x1b01), 1045 regmap_reg_range(0x1b04, 0x1b04), 1046 regmap_reg_range(0x1c00, 0x1c05), 1047 regmap_reg_range(0x1c08, 0x1c1b), 1048 1049 /* port 2 */ 1050 regmap_reg_range(0x2000, 0x2001), 1051 regmap_reg_range(0x2013, 0x2013), 1052 regmap_reg_range(0x2017, 0x2017), 1053 regmap_reg_range(0x201b, 0x201b), 1054 regmap_reg_range(0x201f, 0x2020), 1055 regmap_reg_range(0x2030, 0x2030), 1056 regmap_reg_range(0x2100, 0x2115), 1057 regmap_reg_range(0x211a, 0x211f), 1058 regmap_reg_range(0x2120, 0x212b), 1059 regmap_reg_range(0x2134, 0x213b), 1060 regmap_reg_range(0x213c, 0x213f), 1061 regmap_reg_range(0x2400, 0x2401), 1062 regmap_reg_range(0x2403, 0x2403), 1063 regmap_reg_range(0x2410, 0x2417), 1064 regmap_reg_range(0x2420, 0x2423), 1065 regmap_reg_range(0x2500, 0x2507), 1066 regmap_reg_range(0x2600, 0x2613), 1067 regmap_reg_range(0x2800, 0x280f), 1068 regmap_reg_range(0x2820, 0x2827), 1069 regmap_reg_range(0x2830, 0x2837), 1070 regmap_reg_range(0x2840, 0x284b), 1071 regmap_reg_range(0x2900, 0x2907), 1072 regmap_reg_range(0x2914, 0x291b), 1073 regmap_reg_range(0x2920, 0x2920), 1074 regmap_reg_range(0x2923, 0x2927), 1075 regmap_reg_range(0x2a00, 0x2a03), 1076 regmap_reg_range(0x2a04, 0x2a07), 1077 regmap_reg_range(0x2b00, 0x2b01), 1078 regmap_reg_range(0x2b04, 0x2b04), 1079 regmap_reg_range(0x2c00, 0x2c05), 1080 regmap_reg_range(0x2c08, 0x2c1b), 1081 1082 /* port 3 */ 1083 regmap_reg_range(0x3000, 0x3001), 1084 regmap_reg_range(0x3013, 0x3013), 1085 regmap_reg_range(0x3017, 0x3017), 1086 regmap_reg_range(0x301b, 0x301b), 1087 regmap_reg_range(0x301f, 0x3020), 1088 regmap_reg_range(0x3030, 0x3030), 1089 regmap_reg_range(0x3100, 0x3115), 1090 regmap_reg_range(0x311a, 0x311f), 1091 regmap_reg_range(0x3120, 0x312b), 1092 regmap_reg_range(0x3134, 0x313b), 1093 regmap_reg_range(0x313c, 0x313f), 1094 regmap_reg_range(0x3400, 0x3401), 1095 regmap_reg_range(0x3403, 0x3403), 1096 regmap_reg_range(0x3410, 0x3417), 1097 regmap_reg_range(0x3420, 0x3423), 1098 regmap_reg_range(0x3500, 0x3507), 1099 regmap_reg_range(0x3600, 0x3613), 1100 regmap_reg_range(0x3800, 0x380f), 1101 regmap_reg_range(0x3820, 0x3827), 1102 regmap_reg_range(0x3830, 0x3837), 1103 regmap_reg_range(0x3840, 0x384b), 1104 regmap_reg_range(0x3900, 0x3907), 1105 regmap_reg_range(0x3914, 0x391b), 1106 regmap_reg_range(0x3920, 0x3920), 1107 regmap_reg_range(0x3923, 0x3927), 1108 regmap_reg_range(0x3a00, 0x3a03), 1109 regmap_reg_range(0x3a04, 0x3a07), 1110 regmap_reg_range(0x3b00, 0x3b01), 1111 regmap_reg_range(0x3b04, 0x3b04), 1112 regmap_reg_range(0x3c00, 0x3c05), 1113 regmap_reg_range(0x3c08, 0x3c1b), 1114 1115 /* port 4 */ 1116 regmap_reg_range(0x4000, 0x4001), 1117 regmap_reg_range(0x4013, 0x4013), 1118 regmap_reg_range(0x4017, 0x4017), 1119 regmap_reg_range(0x401b, 0x401b), 1120 regmap_reg_range(0x401f, 0x4020), 1121 regmap_reg_range(0x4030, 0x4030), 1122 regmap_reg_range(0x4100, 0x4115), 1123 regmap_reg_range(0x411a, 0x411f), 1124 regmap_reg_range(0x4120, 0x412b), 1125 regmap_reg_range(0x4134, 0x413b), 1126 regmap_reg_range(0x413c, 0x413f), 1127 regmap_reg_range(0x4400, 0x4401), 1128 regmap_reg_range(0x4403, 0x4403), 1129 regmap_reg_range(0x4410, 0x4417), 1130 regmap_reg_range(0x4420, 0x4423), 1131 regmap_reg_range(0x4500, 0x4507), 1132 regmap_reg_range(0x4600, 0x4613), 1133 regmap_reg_range(0x4800, 0x480f), 1134 regmap_reg_range(0x4820, 0x4827), 1135 regmap_reg_range(0x4830, 0x4837), 1136 regmap_reg_range(0x4840, 0x484b), 1137 regmap_reg_range(0x4900, 0x4907), 1138 regmap_reg_range(0x4914, 0x491b), 1139 regmap_reg_range(0x4920, 0x4920), 1140 regmap_reg_range(0x4923, 0x4927), 1141 regmap_reg_range(0x4a00, 0x4a03), 1142 regmap_reg_range(0x4a04, 0x4a07), 1143 regmap_reg_range(0x4b00, 0x4b01), 1144 regmap_reg_range(0x4b04, 0x4b04), 1145 regmap_reg_range(0x4c00, 0x4c05), 1146 regmap_reg_range(0x4c08, 0x4c1b), 1147 1148 /* port 5 */ 1149 regmap_reg_range(0x5000, 0x5001), 1150 regmap_reg_range(0x5013, 0x5013), 1151 regmap_reg_range(0x5017, 0x5017), 1152 regmap_reg_range(0x501b, 0x501b), 1153 regmap_reg_range(0x501f, 0x5020), 1154 regmap_reg_range(0x5030, 0x5030), 1155 regmap_reg_range(0x5100, 0x5115), 1156 regmap_reg_range(0x511a, 0x511f), 1157 regmap_reg_range(0x5120, 0x512b), 1158 regmap_reg_range(0x5134, 0x513b), 1159 regmap_reg_range(0x513c, 0x513f), 1160 regmap_reg_range(0x5400, 0x5401), 1161 regmap_reg_range(0x5403, 0x5403), 1162 regmap_reg_range(0x5410, 0x5417), 1163 regmap_reg_range(0x5420, 0x5423), 1164 regmap_reg_range(0x5500, 0x5507), 1165 regmap_reg_range(0x5600, 0x5613), 1166 regmap_reg_range(0x5800, 0x580f), 1167 regmap_reg_range(0x5820, 0x5827), 1168 regmap_reg_range(0x5830, 0x5837), 1169 regmap_reg_range(0x5840, 0x584b), 1170 regmap_reg_range(0x5900, 0x5907), 1171 regmap_reg_range(0x5914, 0x591b), 1172 regmap_reg_range(0x5920, 0x5920), 1173 regmap_reg_range(0x5923, 0x5927), 1174 regmap_reg_range(0x5a00, 0x5a03), 1175 regmap_reg_range(0x5a04, 0x5a07), 1176 regmap_reg_range(0x5b00, 0x5b01), 1177 regmap_reg_range(0x5b04, 0x5b04), 1178 regmap_reg_range(0x5c00, 0x5c05), 1179 regmap_reg_range(0x5c08, 0x5c1b), 1180 1181 /* port 6 */ 1182 regmap_reg_range(0x6000, 0x6001), 1183 regmap_reg_range(0x6013, 0x6013), 1184 regmap_reg_range(0x6017, 0x6017), 1185 regmap_reg_range(0x601b, 0x601b), 1186 regmap_reg_range(0x601f, 0x6020), 1187 regmap_reg_range(0x6030, 0x6030), 1188 regmap_reg_range(0x6300, 0x6301), 1189 regmap_reg_range(0x6400, 0x6401), 1190 regmap_reg_range(0x6403, 0x6403), 1191 regmap_reg_range(0x6410, 0x6417), 1192 regmap_reg_range(0x6420, 0x6423), 1193 regmap_reg_range(0x6500, 0x6507), 1194 regmap_reg_range(0x6600, 0x6613), 1195 regmap_reg_range(0x6800, 0x680f), 1196 regmap_reg_range(0x6820, 0x6827), 1197 regmap_reg_range(0x6830, 0x6837), 1198 regmap_reg_range(0x6840, 0x684b), 1199 regmap_reg_range(0x6900, 0x6907), 1200 regmap_reg_range(0x6914, 0x691b), 1201 regmap_reg_range(0x6920, 0x6920), 1202 regmap_reg_range(0x6923, 0x6927), 1203 regmap_reg_range(0x6a00, 0x6a03), 1204 regmap_reg_range(0x6a04, 0x6a07), 1205 regmap_reg_range(0x6b00, 0x6b01), 1206 regmap_reg_range(0x6b04, 0x6b04), 1207 regmap_reg_range(0x6c00, 0x6c05), 1208 regmap_reg_range(0x6c08, 0x6c1b), 1209 1210 /* port 7 */ 1211 regmap_reg_range(0x7000, 0x7001), 1212 regmap_reg_range(0x7013, 0x7013), 1213 regmap_reg_range(0x7017, 0x7017), 1214 regmap_reg_range(0x701b, 0x701b), 1215 regmap_reg_range(0x701f, 0x7020), 1216 regmap_reg_range(0x7030, 0x7030), 1217 regmap_reg_range(0x7200, 0x7207), 1218 regmap_reg_range(0x7300, 0x7301), 1219 regmap_reg_range(0x7400, 0x7401), 1220 regmap_reg_range(0x7403, 0x7403), 1221 regmap_reg_range(0x7410, 0x7417), 1222 regmap_reg_range(0x7420, 0x7423), 1223 regmap_reg_range(0x7500, 0x7507), 1224 regmap_reg_range(0x7600, 0x7613), 1225 regmap_reg_range(0x7800, 0x780f), 1226 regmap_reg_range(0x7820, 0x7827), 1227 regmap_reg_range(0x7830, 0x7837), 1228 regmap_reg_range(0x7840, 0x784b), 1229 regmap_reg_range(0x7900, 0x7907), 1230 regmap_reg_range(0x7914, 0x791b), 1231 regmap_reg_range(0x7920, 0x7920), 1232 regmap_reg_range(0x7923, 0x7927), 1233 regmap_reg_range(0x7a00, 0x7a03), 1234 regmap_reg_range(0x7a04, 0x7a07), 1235 regmap_reg_range(0x7b00, 0x7b01), 1236 regmap_reg_range(0x7b04, 0x7b04), 1237 regmap_reg_range(0x7c00, 0x7c05), 1238 regmap_reg_range(0x7c08, 0x7c1b), 1239 }; 1240 1241 static const struct regmap_access_table ksz9477_register_set = { 1242 .yes_ranges = ksz9477_valid_regs, 1243 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs), 1244 }; 1245 1246 static const struct regmap_range ksz9896_valid_regs[] = { 1247 regmap_reg_range(0x0000, 0x0003), 1248 regmap_reg_range(0x0006, 0x0006), 1249 regmap_reg_range(0x0010, 0x001f), 1250 regmap_reg_range(0x0100, 0x0100), 1251 regmap_reg_range(0x0103, 0x0107), 1252 regmap_reg_range(0x010d, 0x010d), 1253 regmap_reg_range(0x0110, 0x0113), 1254 regmap_reg_range(0x0120, 0x0127), 1255 regmap_reg_range(0x0201, 0x0201), 1256 regmap_reg_range(0x0210, 0x0213), 1257 regmap_reg_range(0x0300, 0x0300), 1258 regmap_reg_range(0x0302, 0x030b), 1259 regmap_reg_range(0x0310, 0x031b), 1260 regmap_reg_range(0x0320, 0x032b), 1261 regmap_reg_range(0x0330, 0x0336), 1262 regmap_reg_range(0x0338, 0x033b), 1263 regmap_reg_range(0x033e, 0x033e), 1264 regmap_reg_range(0x0340, 0x035f), 1265 regmap_reg_range(0x0370, 0x0370), 1266 regmap_reg_range(0x0378, 0x0378), 1267 regmap_reg_range(0x037c, 0x037d), 1268 regmap_reg_range(0x0390, 0x0393), 1269 regmap_reg_range(0x0400, 0x040e), 1270 regmap_reg_range(0x0410, 0x042f), 1271 1272 /* port 1 */ 1273 regmap_reg_range(0x1000, 0x1001), 1274 regmap_reg_range(0x1013, 0x1013), 1275 regmap_reg_range(0x1017, 0x1017), 1276 regmap_reg_range(0x101b, 0x101b), 1277 regmap_reg_range(0x101f, 0x1020), 1278 regmap_reg_range(0x1030, 0x1030), 1279 regmap_reg_range(0x1100, 0x1115), 1280 regmap_reg_range(0x111a, 0x111f), 1281 regmap_reg_range(0x1120, 0x112b), 1282 regmap_reg_range(0x1134, 0x113b), 1283 regmap_reg_range(0x113c, 0x113f), 1284 regmap_reg_range(0x1400, 0x1401), 1285 regmap_reg_range(0x1403, 0x1403), 1286 regmap_reg_range(0x1410, 0x1417), 1287 regmap_reg_range(0x1420, 0x1423), 1288 regmap_reg_range(0x1500, 0x1507), 1289 regmap_reg_range(0x1600, 0x1612), 1290 regmap_reg_range(0x1800, 0x180f), 1291 regmap_reg_range(0x1820, 0x1827), 1292 regmap_reg_range(0x1830, 0x1837), 1293 regmap_reg_range(0x1840, 0x184b), 1294 regmap_reg_range(0x1900, 0x1907), 1295 regmap_reg_range(0x1914, 0x1915), 1296 regmap_reg_range(0x1a00, 0x1a03), 1297 regmap_reg_range(0x1a04, 0x1a07), 1298 regmap_reg_range(0x1b00, 0x1b01), 1299 regmap_reg_range(0x1b04, 0x1b04), 1300 1301 /* port 2 */ 1302 regmap_reg_range(0x2000, 0x2001), 1303 regmap_reg_range(0x2013, 0x2013), 1304 regmap_reg_range(0x2017, 0x2017), 1305 regmap_reg_range(0x201b, 0x201b), 1306 regmap_reg_range(0x201f, 0x2020), 1307 regmap_reg_range(0x2030, 0x2030), 1308 regmap_reg_range(0x2100, 0x2115), 1309 regmap_reg_range(0x211a, 0x211f), 1310 regmap_reg_range(0x2120, 0x212b), 1311 regmap_reg_range(0x2134, 0x213b), 1312 regmap_reg_range(0x213c, 0x213f), 1313 regmap_reg_range(0x2400, 0x2401), 1314 regmap_reg_range(0x2403, 0x2403), 1315 regmap_reg_range(0x2410, 0x2417), 1316 regmap_reg_range(0x2420, 0x2423), 1317 regmap_reg_range(0x2500, 0x2507), 1318 regmap_reg_range(0x2600, 0x2612), 1319 regmap_reg_range(0x2800, 0x280f), 1320 regmap_reg_range(0x2820, 0x2827), 1321 regmap_reg_range(0x2830, 0x2837), 1322 regmap_reg_range(0x2840, 0x284b), 1323 regmap_reg_range(0x2900, 0x2907), 1324 regmap_reg_range(0x2914, 0x2915), 1325 regmap_reg_range(0x2a00, 0x2a03), 1326 regmap_reg_range(0x2a04, 0x2a07), 1327 regmap_reg_range(0x2b00, 0x2b01), 1328 regmap_reg_range(0x2b04, 0x2b04), 1329 1330 /* port 3 */ 1331 regmap_reg_range(0x3000, 0x3001), 1332 regmap_reg_range(0x3013, 0x3013), 1333 regmap_reg_range(0x3017, 0x3017), 1334 regmap_reg_range(0x301b, 0x301b), 1335 regmap_reg_range(0x301f, 0x3020), 1336 regmap_reg_range(0x3030, 0x3030), 1337 regmap_reg_range(0x3100, 0x3115), 1338 regmap_reg_range(0x311a, 0x311f), 1339 regmap_reg_range(0x3120, 0x312b), 1340 regmap_reg_range(0x3134, 0x313b), 1341 regmap_reg_range(0x313c, 0x313f), 1342 regmap_reg_range(0x3400, 0x3401), 1343 regmap_reg_range(0x3403, 0x3403), 1344 regmap_reg_range(0x3410, 0x3417), 1345 regmap_reg_range(0x3420, 0x3423), 1346 regmap_reg_range(0x3500, 0x3507), 1347 regmap_reg_range(0x3600, 0x3612), 1348 regmap_reg_range(0x3800, 0x380f), 1349 regmap_reg_range(0x3820, 0x3827), 1350 regmap_reg_range(0x3830, 0x3837), 1351 regmap_reg_range(0x3840, 0x384b), 1352 regmap_reg_range(0x3900, 0x3907), 1353 regmap_reg_range(0x3914, 0x3915), 1354 regmap_reg_range(0x3a00, 0x3a03), 1355 regmap_reg_range(0x3a04, 0x3a07), 1356 regmap_reg_range(0x3b00, 0x3b01), 1357 regmap_reg_range(0x3b04, 0x3b04), 1358 1359 /* port 4 */ 1360 regmap_reg_range(0x4000, 0x4001), 1361 regmap_reg_range(0x4013, 0x4013), 1362 regmap_reg_range(0x4017, 0x4017), 1363 regmap_reg_range(0x401b, 0x401b), 1364 regmap_reg_range(0x401f, 0x4020), 1365 regmap_reg_range(0x4030, 0x4030), 1366 regmap_reg_range(0x4100, 0x4115), 1367 regmap_reg_range(0x411a, 0x411f), 1368 regmap_reg_range(0x4120, 0x412b), 1369 regmap_reg_range(0x4134, 0x413b), 1370 regmap_reg_range(0x413c, 0x413f), 1371 regmap_reg_range(0x4400, 0x4401), 1372 regmap_reg_range(0x4403, 0x4403), 1373 regmap_reg_range(0x4410, 0x4417), 1374 regmap_reg_range(0x4420, 0x4423), 1375 regmap_reg_range(0x4500, 0x4507), 1376 regmap_reg_range(0x4600, 0x4612), 1377 regmap_reg_range(0x4800, 0x480f), 1378 regmap_reg_range(0x4820, 0x4827), 1379 regmap_reg_range(0x4830, 0x4837), 1380 regmap_reg_range(0x4840, 0x484b), 1381 regmap_reg_range(0x4900, 0x4907), 1382 regmap_reg_range(0x4914, 0x4915), 1383 regmap_reg_range(0x4a00, 0x4a03), 1384 regmap_reg_range(0x4a04, 0x4a07), 1385 regmap_reg_range(0x4b00, 0x4b01), 1386 regmap_reg_range(0x4b04, 0x4b04), 1387 1388 /* port 5 */ 1389 regmap_reg_range(0x5000, 0x5001), 1390 regmap_reg_range(0x5013, 0x5013), 1391 regmap_reg_range(0x5017, 0x5017), 1392 regmap_reg_range(0x501b, 0x501b), 1393 regmap_reg_range(0x501f, 0x5020), 1394 regmap_reg_range(0x5030, 0x5030), 1395 regmap_reg_range(0x5100, 0x5115), 1396 regmap_reg_range(0x511a, 0x511f), 1397 regmap_reg_range(0x5120, 0x512b), 1398 regmap_reg_range(0x5134, 0x513b), 1399 regmap_reg_range(0x513c, 0x513f), 1400 regmap_reg_range(0x5400, 0x5401), 1401 regmap_reg_range(0x5403, 0x5403), 1402 regmap_reg_range(0x5410, 0x5417), 1403 regmap_reg_range(0x5420, 0x5423), 1404 regmap_reg_range(0x5500, 0x5507), 1405 regmap_reg_range(0x5600, 0x5612), 1406 regmap_reg_range(0x5800, 0x580f), 1407 regmap_reg_range(0x5820, 0x5827), 1408 regmap_reg_range(0x5830, 0x5837), 1409 regmap_reg_range(0x5840, 0x584b), 1410 regmap_reg_range(0x5900, 0x5907), 1411 regmap_reg_range(0x5914, 0x5915), 1412 regmap_reg_range(0x5a00, 0x5a03), 1413 regmap_reg_range(0x5a04, 0x5a07), 1414 regmap_reg_range(0x5b00, 0x5b01), 1415 regmap_reg_range(0x5b04, 0x5b04), 1416 1417 /* port 6 */ 1418 regmap_reg_range(0x6000, 0x6001), 1419 regmap_reg_range(0x6013, 0x6013), 1420 regmap_reg_range(0x6017, 0x6017), 1421 regmap_reg_range(0x601b, 0x601b), 1422 regmap_reg_range(0x601f, 0x6020), 1423 regmap_reg_range(0x6030, 0x6030), 1424 regmap_reg_range(0x6100, 0x6115), 1425 regmap_reg_range(0x611a, 0x611f), 1426 regmap_reg_range(0x6120, 0x612b), 1427 regmap_reg_range(0x6134, 0x613b), 1428 regmap_reg_range(0x613c, 0x613f), 1429 regmap_reg_range(0x6300, 0x6301), 1430 regmap_reg_range(0x6400, 0x6401), 1431 regmap_reg_range(0x6403, 0x6403), 1432 regmap_reg_range(0x6410, 0x6417), 1433 regmap_reg_range(0x6420, 0x6423), 1434 regmap_reg_range(0x6500, 0x6507), 1435 regmap_reg_range(0x6600, 0x6612), 1436 regmap_reg_range(0x6800, 0x680f), 1437 regmap_reg_range(0x6820, 0x6827), 1438 regmap_reg_range(0x6830, 0x6837), 1439 regmap_reg_range(0x6840, 0x684b), 1440 regmap_reg_range(0x6900, 0x6907), 1441 regmap_reg_range(0x6914, 0x6915), 1442 regmap_reg_range(0x6a00, 0x6a03), 1443 regmap_reg_range(0x6a04, 0x6a07), 1444 regmap_reg_range(0x6b00, 0x6b01), 1445 regmap_reg_range(0x6b04, 0x6b04), 1446 }; 1447 1448 static const struct regmap_access_table ksz9896_register_set = { 1449 .yes_ranges = ksz9896_valid_regs, 1450 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs), 1451 }; 1452 1453 static const struct regmap_range ksz8873_valid_regs[] = { 1454 regmap_reg_range(0x00, 0x01), 1455 /* global control register */ 1456 regmap_reg_range(0x02, 0x0f), 1457 1458 /* port registers */ 1459 regmap_reg_range(0x10, 0x1d), 1460 regmap_reg_range(0x1e, 0x1f), 1461 regmap_reg_range(0x20, 0x2d), 1462 regmap_reg_range(0x2e, 0x2f), 1463 regmap_reg_range(0x30, 0x39), 1464 regmap_reg_range(0x3f, 0x3f), 1465 1466 /* advanced control registers */ 1467 regmap_reg_range(0x43, 0x43), 1468 regmap_reg_range(0x60, 0x6f), 1469 regmap_reg_range(0x70, 0x75), 1470 regmap_reg_range(0x76, 0x78), 1471 regmap_reg_range(0x79, 0x7a), 1472 regmap_reg_range(0x7b, 0x83), 1473 regmap_reg_range(0x8e, 0x99), 1474 regmap_reg_range(0x9a, 0xa5), 1475 regmap_reg_range(0xa6, 0xa6), 1476 regmap_reg_range(0xa7, 0xaa), 1477 regmap_reg_range(0xab, 0xae), 1478 regmap_reg_range(0xaf, 0xba), 1479 regmap_reg_range(0xbb, 0xbc), 1480 regmap_reg_range(0xbd, 0xbd), 1481 regmap_reg_range(0xc0, 0xc0), 1482 regmap_reg_range(0xc2, 0xc2), 1483 regmap_reg_range(0xc3, 0xc3), 1484 regmap_reg_range(0xc4, 0xc4), 1485 regmap_reg_range(0xc6, 0xc6), 1486 }; 1487 1488 static const struct regmap_access_table ksz8873_register_set = { 1489 .yes_ranges = ksz8873_valid_regs, 1490 .n_yes_ranges = ARRAY_SIZE(ksz8873_valid_regs), 1491 }; 1492 1493 const struct ksz_chip_data ksz_switch_chips[] = { 1494 [KSZ8463] = { 1495 .chip_id = KSZ8463_CHIP_ID, 1496 .dev_name = "KSZ8463", 1497 .num_vlans = 16, 1498 .num_alus = 0, 1499 .num_statics = 8, 1500 .cpu_ports = 0x4, /* can be configured as cpu port */ 1501 .port_cnt = 3, 1502 .num_tx_queues = 4, 1503 .num_ipms = 4, 1504 .ops = &ksz8463_dev_ops, 1505 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1506 .mib_names = ksz88xx_mib_names, 1507 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1508 .reg_mib_cnt = MIB_COUNTER_NUM, 1509 .regs = ksz8463_regs, 1510 .masks = ksz8463_masks, 1511 .shifts = ksz8463_shifts, 1512 .supports_mii = {false, false, true}, 1513 .supports_rmii = {false, false, true}, 1514 .internal_phy = {true, true, false}, 1515 }, 1516 1517 [KSZ8563] = { 1518 .chip_id = KSZ8563_CHIP_ID, 1519 .dev_name = "KSZ8563", 1520 .num_vlans = 4096, 1521 .num_alus = 4096, 1522 .num_statics = 16, 1523 .cpu_ports = 0x07, /* can be configured as cpu port */ 1524 .port_cnt = 3, /* total port count */ 1525 .port_nirqs = 3, 1526 .num_tx_queues = 4, 1527 .num_ipms = 8, 1528 .tc_cbs_supported = true, 1529 .ops = &ksz9477_dev_ops, 1530 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1531 .mib_names = ksz9477_mib_names, 1532 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1533 .reg_mib_cnt = MIB_COUNTER_NUM, 1534 .regs = ksz9477_regs, 1535 .masks = ksz9477_masks, 1536 .shifts = ksz9477_shifts, 1537 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1538 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1539 .supports_mii = {false, false, true}, 1540 .supports_rmii = {false, false, true}, 1541 .supports_rgmii = {false, false, true}, 1542 .internal_phy = {true, true, false}, 1543 .gbit_capable = {false, false, true}, 1544 .ptp_capable = true, 1545 .wr_table = &ksz8563_register_set, 1546 .rd_table = &ksz8563_register_set, 1547 }, 1548 1549 [KSZ8795] = { 1550 .chip_id = KSZ8795_CHIP_ID, 1551 .dev_name = "KSZ8795", 1552 .num_vlans = 4096, 1553 .num_alus = 0, 1554 .num_statics = 32, 1555 .cpu_ports = 0x10, /* can be configured as cpu port */ 1556 .port_cnt = 5, /* total cpu and user ports */ 1557 .num_tx_queues = 4, 1558 .num_ipms = 4, 1559 .ops = &ksz87xx_dev_ops, 1560 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1561 .ksz87xx_eee_link_erratum = true, 1562 .mib_names = ksz9477_mib_names, 1563 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1564 .reg_mib_cnt = MIB_COUNTER_NUM, 1565 .regs = ksz8795_regs, 1566 .masks = ksz8795_masks, 1567 .shifts = ksz8795_shifts, 1568 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1569 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1570 .supports_mii = {false, false, false, false, true}, 1571 .supports_rmii = {false, false, false, false, true}, 1572 .supports_rgmii = {false, false, false, false, true}, 1573 .internal_phy = {true, true, true, true, false}, 1574 }, 1575 1576 [KSZ8794] = { 1577 /* WARNING 1578 * ======= 1579 * KSZ8794 is similar to KSZ8795, except the port map 1580 * contains a gap between external and CPU ports, the 1581 * port map is NOT continuous. The per-port register 1582 * map is shifted accordingly too, i.e. registers at 1583 * offset 0x40 are NOT used on KSZ8794 and they ARE 1584 * used on KSZ8795 for external port 3. 1585 * external cpu 1586 * KSZ8794 0,1,2 4 1587 * KSZ8795 0,1,2,3 4 1588 * KSZ8765 0,1,2,3 4 1589 * port_cnt is configured as 5, even though it is 4 1590 */ 1591 .chip_id = KSZ8794_CHIP_ID, 1592 .dev_name = "KSZ8794", 1593 .num_vlans = 4096, 1594 .num_alus = 0, 1595 .num_statics = 32, 1596 .cpu_ports = 0x10, /* can be configured as cpu port */ 1597 .port_cnt = 5, /* total cpu and user ports */ 1598 .num_tx_queues = 4, 1599 .num_ipms = 4, 1600 .ops = &ksz87xx_dev_ops, 1601 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1602 .ksz87xx_eee_link_erratum = true, 1603 .mib_names = ksz9477_mib_names, 1604 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1605 .reg_mib_cnt = MIB_COUNTER_NUM, 1606 .regs = ksz8795_regs, 1607 .masks = ksz8795_masks, 1608 .shifts = ksz8795_shifts, 1609 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1610 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1611 .supports_mii = {false, false, false, false, true}, 1612 .supports_rmii = {false, false, false, false, true}, 1613 .supports_rgmii = {false, false, false, false, true}, 1614 .internal_phy = {true, true, true, false, false}, 1615 }, 1616 1617 [KSZ8765] = { 1618 .chip_id = KSZ8765_CHIP_ID, 1619 .dev_name = "KSZ8765", 1620 .num_vlans = 4096, 1621 .num_alus = 0, 1622 .num_statics = 32, 1623 .cpu_ports = 0x10, /* can be configured as cpu port */ 1624 .port_cnt = 5, /* total cpu and user ports */ 1625 .num_tx_queues = 4, 1626 .num_ipms = 4, 1627 .ops = &ksz87xx_dev_ops, 1628 .phylink_mac_ops = &ksz8_phylink_mac_ops, 1629 .ksz87xx_eee_link_erratum = true, 1630 .mib_names = ksz9477_mib_names, 1631 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1632 .reg_mib_cnt = MIB_COUNTER_NUM, 1633 .regs = ksz8795_regs, 1634 .masks = ksz8795_masks, 1635 .shifts = ksz8795_shifts, 1636 .xmii_ctrl0 = ksz8795_xmii_ctrl0, 1637 .xmii_ctrl1 = ksz8795_xmii_ctrl1, 1638 .supports_mii = {false, false, false, false, true}, 1639 .supports_rmii = {false, false, false, false, true}, 1640 .supports_rgmii = {false, false, false, false, true}, 1641 .internal_phy = {true, true, true, true, false}, 1642 }, 1643 1644 [KSZ88X3] = { 1645 .chip_id = KSZ88X3_CHIP_ID, 1646 .dev_name = "KSZ8863/KSZ8873", 1647 .num_vlans = 16, 1648 .num_alus = 0, 1649 .num_statics = 8, 1650 .cpu_ports = 0x4, /* can be configured as cpu port */ 1651 .port_cnt = 3, 1652 .num_tx_queues = 4, 1653 .num_ipms = 4, 1654 .ops = &ksz88xx_dev_ops, 1655 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1656 .mib_names = ksz88xx_mib_names, 1657 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1658 .reg_mib_cnt = MIB_COUNTER_NUM, 1659 .regs = ksz8863_regs, 1660 .masks = ksz8863_masks, 1661 .shifts = ksz8863_shifts, 1662 .supports_mii = {false, false, true}, 1663 .supports_rmii = {false, false, true}, 1664 .internal_phy = {true, true, false}, 1665 .wr_table = &ksz8873_register_set, 1666 .rd_table = &ksz8873_register_set, 1667 }, 1668 1669 [KSZ8864] = { 1670 /* WARNING 1671 * ======= 1672 * KSZ8864 is similar to KSZ8895, except the first port 1673 * does not exist. 1674 * external cpu 1675 * KSZ8864 1,2,3 4 1676 * KSZ8895 0,1,2,3 4 1677 * port_cnt is configured as 5, even though it is 4 1678 */ 1679 .chip_id = KSZ8864_CHIP_ID, 1680 .dev_name = "KSZ8864", 1681 .num_vlans = 4096, 1682 .num_alus = 0, 1683 .num_statics = 32, 1684 .cpu_ports = 0x10, /* can be configured as cpu port */ 1685 .port_cnt = 5, /* total cpu and user ports */ 1686 .num_tx_queues = 4, 1687 .num_ipms = 4, 1688 .ops = &ksz88xx_dev_ops, 1689 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1690 .mib_names = ksz88xx_mib_names, 1691 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1692 .reg_mib_cnt = MIB_COUNTER_NUM, 1693 .regs = ksz8895_regs, 1694 .masks = ksz8895_masks, 1695 .shifts = ksz8895_shifts, 1696 .supports_mii = {false, false, false, false, true}, 1697 .supports_rmii = {false, false, false, false, true}, 1698 .internal_phy = {false, true, true, true, false}, 1699 }, 1700 1701 [KSZ8895] = { 1702 .chip_id = KSZ8895_CHIP_ID, 1703 .dev_name = "KSZ8895", 1704 .num_vlans = 4096, 1705 .num_alus = 0, 1706 .num_statics = 32, 1707 .cpu_ports = 0x10, /* can be configured as cpu port */ 1708 .port_cnt = 5, /* total cpu and user ports */ 1709 .num_tx_queues = 4, 1710 .num_ipms = 4, 1711 .ops = &ksz88xx_dev_ops, 1712 .phylink_mac_ops = &ksz88x3_phylink_mac_ops, 1713 .mib_names = ksz88xx_mib_names, 1714 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names), 1715 .reg_mib_cnt = MIB_COUNTER_NUM, 1716 .regs = ksz8895_regs, 1717 .masks = ksz8895_masks, 1718 .shifts = ksz8895_shifts, 1719 .supports_mii = {false, false, false, false, true}, 1720 .supports_rmii = {false, false, false, false, true}, 1721 .internal_phy = {true, true, true, true, false}, 1722 }, 1723 1724 [KSZ9477] = { 1725 .chip_id = KSZ9477_CHIP_ID, 1726 .dev_name = "KSZ9477", 1727 .num_vlans = 4096, 1728 .num_alus = 4096, 1729 .num_statics = 16, 1730 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1731 .port_cnt = 7, /* total physical port count */ 1732 .port_nirqs = 4, 1733 .num_tx_queues = 4, 1734 .num_ipms = 8, 1735 .tc_cbs_supported = true, 1736 .ops = &ksz9477_dev_ops, 1737 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1738 .phy_errata_9477 = true, 1739 .mib_names = ksz9477_mib_names, 1740 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1741 .reg_mib_cnt = MIB_COUNTER_NUM, 1742 .regs = ksz9477_regs, 1743 .masks = ksz9477_masks, 1744 .shifts = ksz9477_shifts, 1745 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1746 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1747 .supports_mii = {false, false, false, false, 1748 false, true, false}, 1749 .supports_rmii = {false, false, false, false, 1750 false, true, false}, 1751 .supports_rgmii = {false, false, false, false, 1752 false, true, false}, 1753 .internal_phy = {true, true, true, true, 1754 true, false, false}, 1755 .gbit_capable = {true, true, true, true, true, true, true}, 1756 .ptp_capable = true, 1757 .sgmii_port = 7, 1758 .wr_table = &ksz9477_register_set, 1759 .rd_table = &ksz9477_register_set, 1760 }, 1761 1762 [KSZ9896] = { 1763 .chip_id = KSZ9896_CHIP_ID, 1764 .dev_name = "KSZ9896", 1765 .num_vlans = 4096, 1766 .num_alus = 4096, 1767 .num_statics = 16, 1768 .cpu_ports = 0x3F, /* can be configured as cpu port */ 1769 .port_cnt = 6, /* total physical port count */ 1770 .port_nirqs = 2, 1771 .num_tx_queues = 4, 1772 .num_ipms = 8, 1773 .ops = &ksz9477_dev_ops, 1774 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1775 .phy_errata_9477 = true, 1776 .mib_names = ksz9477_mib_names, 1777 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1778 .reg_mib_cnt = MIB_COUNTER_NUM, 1779 .regs = ksz9477_regs, 1780 .masks = ksz9477_masks, 1781 .shifts = ksz9477_shifts, 1782 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1783 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1784 .supports_mii = {false, false, false, false, 1785 false, true}, 1786 .supports_rmii = {false, false, false, false, 1787 false, true}, 1788 .supports_rgmii = {false, false, false, false, 1789 false, true}, 1790 .internal_phy = {true, true, true, true, 1791 true, false}, 1792 .gbit_capable = {true, true, true, true, true, true}, 1793 .wr_table = &ksz9896_register_set, 1794 .rd_table = &ksz9896_register_set, 1795 }, 1796 1797 [KSZ9897] = { 1798 .chip_id = KSZ9897_CHIP_ID, 1799 .dev_name = "KSZ9897", 1800 .num_vlans = 4096, 1801 .num_alus = 4096, 1802 .num_statics = 16, 1803 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1804 .port_cnt = 7, /* total physical port count */ 1805 .port_nirqs = 2, 1806 .num_tx_queues = 4, 1807 .num_ipms = 8, 1808 .ops = &ksz9477_dev_ops, 1809 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1810 .phy_errata_9477 = true, 1811 .mib_names = ksz9477_mib_names, 1812 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1813 .reg_mib_cnt = MIB_COUNTER_NUM, 1814 .regs = ksz9477_regs, 1815 .masks = ksz9477_masks, 1816 .shifts = ksz9477_shifts, 1817 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1818 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1819 .supports_mii = {false, false, false, false, 1820 false, true, true}, 1821 .supports_rmii = {false, false, false, false, 1822 false, true, true}, 1823 .supports_rgmii = {false, false, false, false, 1824 false, true, true}, 1825 .internal_phy = {true, true, true, true, 1826 true, false, false}, 1827 .gbit_capable = {true, true, true, true, true, true, true}, 1828 }, 1829 1830 [KSZ9893] = { 1831 .chip_id = KSZ9893_CHIP_ID, 1832 .dev_name = "KSZ9893", 1833 .num_vlans = 4096, 1834 .num_alus = 4096, 1835 .num_statics = 16, 1836 .cpu_ports = 0x07, /* can be configured as cpu port */ 1837 .port_cnt = 3, /* total port count */ 1838 .port_nirqs = 2, 1839 .num_tx_queues = 4, 1840 .num_ipms = 8, 1841 .ops = &ksz9477_dev_ops, 1842 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1843 .mib_names = ksz9477_mib_names, 1844 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1845 .reg_mib_cnt = MIB_COUNTER_NUM, 1846 .regs = ksz9477_regs, 1847 .masks = ksz9477_masks, 1848 .shifts = ksz9477_shifts, 1849 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1850 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1851 .supports_mii = {false, false, true}, 1852 .supports_rmii = {false, false, true}, 1853 .supports_rgmii = {false, false, true}, 1854 .internal_phy = {true, true, false}, 1855 .gbit_capable = {true, true, true}, 1856 }, 1857 1858 [KSZ9563] = { 1859 .chip_id = KSZ9563_CHIP_ID, 1860 .dev_name = "KSZ9563", 1861 .num_vlans = 4096, 1862 .num_alus = 4096, 1863 .num_statics = 16, 1864 .cpu_ports = 0x07, /* can be configured as cpu port */ 1865 .port_cnt = 3, /* total port count */ 1866 .port_nirqs = 3, 1867 .num_tx_queues = 4, 1868 .num_ipms = 8, 1869 .tc_cbs_supported = true, 1870 .ops = &ksz9477_dev_ops, 1871 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1872 .mib_names = ksz9477_mib_names, 1873 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1874 .reg_mib_cnt = MIB_COUNTER_NUM, 1875 .regs = ksz9477_regs, 1876 .masks = ksz9477_masks, 1877 .shifts = ksz9477_shifts, 1878 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1879 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */ 1880 .supports_mii = {false, false, true}, 1881 .supports_rmii = {false, false, true}, 1882 .supports_rgmii = {false, false, true}, 1883 .internal_phy = {true, true, false}, 1884 .gbit_capable = {true, true, true}, 1885 .ptp_capable = true, 1886 }, 1887 1888 [KSZ8567] = { 1889 .chip_id = KSZ8567_CHIP_ID, 1890 .dev_name = "KSZ8567", 1891 .num_vlans = 4096, 1892 .num_alus = 4096, 1893 .num_statics = 16, 1894 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1895 .port_cnt = 7, /* total port count */ 1896 .port_nirqs = 3, 1897 .num_tx_queues = 4, 1898 .num_ipms = 8, 1899 .tc_cbs_supported = true, 1900 .ops = &ksz9477_dev_ops, 1901 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 1902 .phy_errata_9477 = true, 1903 .mib_names = ksz9477_mib_names, 1904 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1905 .reg_mib_cnt = MIB_COUNTER_NUM, 1906 .regs = ksz9477_regs, 1907 .masks = ksz9477_masks, 1908 .shifts = ksz9477_shifts, 1909 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1910 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1911 .supports_mii = {false, false, false, false, 1912 false, true, true}, 1913 .supports_rmii = {false, false, false, false, 1914 false, true, true}, 1915 .supports_rgmii = {false, false, false, false, 1916 false, true, true}, 1917 .internal_phy = {true, true, true, true, 1918 true, false, false}, 1919 .gbit_capable = {false, false, false, false, false, 1920 true, true}, 1921 .ptp_capable = true, 1922 }, 1923 1924 [KSZ9567] = { 1925 .chip_id = KSZ9567_CHIP_ID, 1926 .dev_name = "KSZ9567", 1927 .num_vlans = 4096, 1928 .num_alus = 4096, 1929 .num_statics = 16, 1930 .cpu_ports = 0x7F, /* can be configured as cpu port */ 1931 .port_cnt = 7, /* total physical port count */ 1932 .port_nirqs = 3, 1933 .num_tx_queues = 4, 1934 .num_ipms = 8, 1935 .tc_cbs_supported = true, 1936 .ops = &ksz9477_dev_ops, 1937 .mib_names = ksz9477_mib_names, 1938 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1939 .reg_mib_cnt = MIB_COUNTER_NUM, 1940 .regs = ksz9477_regs, 1941 .masks = ksz9477_masks, 1942 .shifts = ksz9477_shifts, 1943 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1944 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1945 .supports_mii = {false, false, false, false, 1946 false, true, true}, 1947 .supports_rmii = {false, false, false, false, 1948 false, true, true}, 1949 .supports_rgmii = {false, false, false, false, 1950 false, true, true}, 1951 .internal_phy = {true, true, true, true, 1952 true, false, false}, 1953 .gbit_capable = {true, true, true, true, true, true, true}, 1954 .ptp_capable = true, 1955 }, 1956 1957 [LAN9370] = { 1958 .chip_id = LAN9370_CHIP_ID, 1959 .dev_name = "LAN9370", 1960 .num_vlans = 4096, 1961 .num_alus = 1024, 1962 .num_statics = 256, 1963 .cpu_ports = 0x10, /* can be configured as cpu port */ 1964 .port_cnt = 5, /* total physical port count */ 1965 .port_nirqs = 6, 1966 .num_tx_queues = 8, 1967 .num_ipms = 8, 1968 .tc_cbs_supported = true, 1969 .phy_side_mdio_supported = true, 1970 .ops = &lan937x_dev_ops, 1971 .phylink_mac_ops = &lan937x_phylink_mac_ops, 1972 .mib_names = ksz9477_mib_names, 1973 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 1974 .reg_mib_cnt = MIB_COUNTER_NUM, 1975 .regs = ksz9477_regs, 1976 .masks = lan937x_masks, 1977 .shifts = lan937x_shifts, 1978 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 1979 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 1980 .supports_mii = {false, false, false, false, true}, 1981 .supports_rmii = {false, false, false, false, true}, 1982 .supports_rgmii = {false, false, false, false, true}, 1983 .internal_phy = {true, true, true, true, false}, 1984 .ptp_capable = true, 1985 }, 1986 1987 [LAN9371] = { 1988 .chip_id = LAN9371_CHIP_ID, 1989 .dev_name = "LAN9371", 1990 .num_vlans = 4096, 1991 .num_alus = 1024, 1992 .num_statics = 256, 1993 .cpu_ports = 0x30, /* can be configured as cpu port */ 1994 .port_cnt = 6, /* total physical port count */ 1995 .port_nirqs = 6, 1996 .num_tx_queues = 8, 1997 .num_ipms = 8, 1998 .tc_cbs_supported = true, 1999 .phy_side_mdio_supported = true, 2000 .ops = &lan937x_dev_ops, 2001 .phylink_mac_ops = &lan937x_phylink_mac_ops, 2002 .mib_names = ksz9477_mib_names, 2003 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 2004 .reg_mib_cnt = MIB_COUNTER_NUM, 2005 .regs = ksz9477_regs, 2006 .masks = lan937x_masks, 2007 .shifts = lan937x_shifts, 2008 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 2009 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 2010 .supports_mii = {false, false, false, false, true, true}, 2011 .supports_rmii = {false, false, false, false, true, true}, 2012 .supports_rgmii = {false, false, false, false, true, true}, 2013 .internal_phy = {true, true, true, true, false, false}, 2014 .ptp_capable = true, 2015 }, 2016 2017 [LAN9372] = { 2018 .chip_id = LAN9372_CHIP_ID, 2019 .dev_name = "LAN9372", 2020 .num_vlans = 4096, 2021 .num_alus = 1024, 2022 .num_statics = 256, 2023 .cpu_ports = 0x30, /* can be configured as cpu port */ 2024 .port_cnt = 8, /* total physical port count */ 2025 .port_nirqs = 6, 2026 .num_tx_queues = 8, 2027 .num_ipms = 8, 2028 .tc_cbs_supported = true, 2029 .phy_side_mdio_supported = true, 2030 .ops = &lan937x_dev_ops, 2031 .phylink_mac_ops = &lan937x_phylink_mac_ops, 2032 .mib_names = ksz9477_mib_names, 2033 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 2034 .reg_mib_cnt = MIB_COUNTER_NUM, 2035 .regs = ksz9477_regs, 2036 .masks = lan937x_masks, 2037 .shifts = lan937x_shifts, 2038 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 2039 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 2040 .supports_mii = {false, false, false, false, 2041 true, true, false, false}, 2042 .supports_rmii = {false, false, false, false, 2043 true, true, false, false}, 2044 .supports_rgmii = {false, false, false, false, 2045 true, true, false, false}, 2046 .internal_phy = {true, true, true, true, 2047 false, false, true, true}, 2048 .ptp_capable = true, 2049 }, 2050 2051 [LAN9373] = { 2052 .chip_id = LAN9373_CHIP_ID, 2053 .dev_name = "LAN9373", 2054 .num_vlans = 4096, 2055 .num_alus = 1024, 2056 .num_statics = 256, 2057 .cpu_ports = 0x38, /* can be configured as cpu port */ 2058 .port_cnt = 5, /* total physical port count */ 2059 .port_nirqs = 6, 2060 .num_tx_queues = 8, 2061 .num_ipms = 8, 2062 .tc_cbs_supported = true, 2063 .phy_side_mdio_supported = true, 2064 .ops = &lan937x_dev_ops, 2065 .phylink_mac_ops = &lan937x_phylink_mac_ops, 2066 .mib_names = ksz9477_mib_names, 2067 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 2068 .reg_mib_cnt = MIB_COUNTER_NUM, 2069 .regs = ksz9477_regs, 2070 .masks = lan937x_masks, 2071 .shifts = lan937x_shifts, 2072 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 2073 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 2074 .supports_mii = {false, false, false, false, 2075 true, true, false, false}, 2076 .supports_rmii = {false, false, false, false, 2077 true, true, false, false}, 2078 .supports_rgmii = {false, false, false, false, 2079 true, true, false, false}, 2080 .internal_phy = {true, true, true, false, 2081 false, false, true, true}, 2082 .ptp_capable = true, 2083 }, 2084 2085 [LAN9374] = { 2086 .chip_id = LAN9374_CHIP_ID, 2087 .dev_name = "LAN9374", 2088 .num_vlans = 4096, 2089 .num_alus = 1024, 2090 .num_statics = 256, 2091 .cpu_ports = 0x30, /* can be configured as cpu port */ 2092 .port_cnt = 8, /* total physical port count */ 2093 .port_nirqs = 6, 2094 .num_tx_queues = 8, 2095 .num_ipms = 8, 2096 .tc_cbs_supported = true, 2097 .phy_side_mdio_supported = true, 2098 .ops = &lan937x_dev_ops, 2099 .phylink_mac_ops = &lan937x_phylink_mac_ops, 2100 .mib_names = ksz9477_mib_names, 2101 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 2102 .reg_mib_cnt = MIB_COUNTER_NUM, 2103 .regs = ksz9477_regs, 2104 .masks = lan937x_masks, 2105 .shifts = lan937x_shifts, 2106 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 2107 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 2108 .supports_mii = {false, false, false, false, 2109 true, true, false, false}, 2110 .supports_rmii = {false, false, false, false, 2111 true, true, false, false}, 2112 .supports_rgmii = {false, false, false, false, 2113 true, true, false, false}, 2114 .internal_phy = {true, true, true, true, 2115 false, false, true, true}, 2116 .ptp_capable = true, 2117 }, 2118 2119 [LAN9646] = { 2120 .chip_id = LAN9646_CHIP_ID, 2121 .dev_name = "LAN9646", 2122 .num_vlans = 4096, 2123 .num_alus = 4096, 2124 .num_statics = 16, 2125 .cpu_ports = 0x7F, /* can be configured as cpu port */ 2126 .port_cnt = 7, /* total physical port count */ 2127 .port_nirqs = 4, 2128 .num_tx_queues = 4, 2129 .num_ipms = 8, 2130 .ops = &ksz9477_dev_ops, 2131 .phylink_mac_ops = &ksz9477_phylink_mac_ops, 2132 .phy_errata_9477 = true, 2133 .mib_names = ksz9477_mib_names, 2134 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names), 2135 .reg_mib_cnt = MIB_COUNTER_NUM, 2136 .regs = ksz9477_regs, 2137 .masks = ksz9477_masks, 2138 .shifts = ksz9477_shifts, 2139 .xmii_ctrl0 = ksz9477_xmii_ctrl0, 2140 .xmii_ctrl1 = ksz9477_xmii_ctrl1, 2141 .supports_mii = {false, false, false, false, 2142 false, true, true}, 2143 .supports_rmii = {false, false, false, false, 2144 false, true, true}, 2145 .supports_rgmii = {false, false, false, false, 2146 false, true, true}, 2147 .internal_phy = {true, true, true, true, 2148 true, false, false}, 2149 .gbit_capable = {true, true, true, true, true, true, true}, 2150 .sgmii_port = 7, 2151 .wr_table = &ksz9477_register_set, 2152 .rd_table = &ksz9477_register_set, 2153 }, 2154 }; 2155 EXPORT_SYMBOL_GPL(ksz_switch_chips); 2156 2157 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num) 2158 { 2159 int i; 2160 2161 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) { 2162 const struct ksz_chip_data *chip = &ksz_switch_chips[i]; 2163 2164 if (chip->chip_id == prod_num) 2165 return chip; 2166 } 2167 2168 return NULL; 2169 } 2170 2171 static int ksz_check_device_id(struct ksz_device *dev) 2172 { 2173 const struct ksz_chip_data *expected_chip_data; 2174 u32 expected_chip_id; 2175 2176 if (dev->pdata) { 2177 expected_chip_id = dev->pdata->chip_id; 2178 expected_chip_data = ksz_lookup_info(expected_chip_id); 2179 if (WARN_ON(!expected_chip_data)) 2180 return -ENODEV; 2181 } else { 2182 expected_chip_data = of_device_get_match_data(dev->dev); 2183 expected_chip_id = expected_chip_data->chip_id; 2184 } 2185 2186 if (expected_chip_id != dev->chip_id) { 2187 dev_err(dev->dev, 2188 "Device tree specifies chip %s but found %s, please fix it!\n", 2189 expected_chip_data->dev_name, dev->info->dev_name); 2190 return -ENODEV; 2191 } 2192 2193 return 0; 2194 } 2195 2196 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port, 2197 struct phylink_config *config) 2198 { 2199 struct ksz_device *dev = ds->priv; 2200 2201 if (dev->info->supports_mii[port]) 2202 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 2203 2204 if (dev->info->supports_rmii[port]) 2205 __set_bit(PHY_INTERFACE_MODE_RMII, 2206 config->supported_interfaces); 2207 2208 if (dev->info->supports_rgmii[port]) 2209 phy_interface_set_rgmii(config->supported_interfaces); 2210 2211 if (dev->info->internal_phy[port]) { 2212 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2213 config->supported_interfaces); 2214 /* Compatibility for phylib's default interface type when the 2215 * phy-mode property is absent 2216 */ 2217 __set_bit(PHY_INTERFACE_MODE_GMII, 2218 config->supported_interfaces); 2219 } 2220 2221 if (dev->dev_ops->get_caps) 2222 dev->dev_ops->get_caps(dev, port, config); 2223 2224 if (ds->ops->support_eee && ds->ops->support_eee(ds, port)) { 2225 memcpy(config->lpi_interfaces, config->supported_interfaces, 2226 sizeof(config->lpi_interfaces)); 2227 2228 config->lpi_capabilities = MAC_100FD; 2229 if (dev->info->gbit_capable[port]) 2230 config->lpi_capabilities |= MAC_1000FD; 2231 2232 /* EEE is fully operational */ 2233 config->eee_enabled_default = true; 2234 } 2235 } 2236 2237 void ksz_r_mib_stats64(struct ksz_device *dev, int port) 2238 { 2239 struct ethtool_pause_stats *pstats; 2240 struct rtnl_link_stats64 *stats; 2241 struct ksz_stats_raw *raw; 2242 struct ksz_port_mib *mib; 2243 int ret; 2244 2245 mib = &dev->ports[port].mib; 2246 stats = &mib->stats64; 2247 pstats = &mib->pause_stats; 2248 raw = (struct ksz_stats_raw *)mib->counters; 2249 2250 spin_lock(&mib->stats64_lock); 2251 2252 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 2253 raw->rx_pause; 2254 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2255 raw->tx_pause; 2256 2257 /* HW counters are counting bytes + FCS which is not acceptable 2258 * for rtnl_link_stats64 interface 2259 */ 2260 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN; 2261 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN; 2262 2263 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2264 raw->rx_oversize; 2265 2266 stats->rx_crc_errors = raw->rx_crc_err; 2267 stats->rx_frame_errors = raw->rx_align_err; 2268 stats->rx_dropped = raw->rx_discards; 2269 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2270 stats->rx_frame_errors + stats->rx_dropped; 2271 2272 stats->tx_window_errors = raw->tx_late_col; 2273 stats->tx_fifo_errors = raw->tx_discards; 2274 stats->tx_aborted_errors = raw->tx_exc_col; 2275 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2276 stats->tx_aborted_errors; 2277 2278 stats->multicast = raw->rx_mcast; 2279 stats->collisions = raw->tx_total_col; 2280 2281 pstats->tx_pause_frames = raw->tx_pause; 2282 pstats->rx_pause_frames = raw->rx_pause; 2283 2284 spin_unlock(&mib->stats64_lock); 2285 2286 if (dev->info->phy_errata_9477 && !ksz_is_sgmii_port(dev, port)) { 2287 ret = ksz9477_errata_monitor(dev, port, raw->tx_late_col); 2288 if (ret) 2289 dev_err(dev->dev, "Failed to monitor transmission halt\n"); 2290 } 2291 } 2292 2293 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port) 2294 { 2295 struct ethtool_pause_stats *pstats; 2296 struct rtnl_link_stats64 *stats; 2297 struct ksz88xx_stats_raw *raw; 2298 struct ksz_port_mib *mib; 2299 2300 mib = &dev->ports[port].mib; 2301 stats = &mib->stats64; 2302 pstats = &mib->pause_stats; 2303 raw = (struct ksz88xx_stats_raw *)mib->counters; 2304 2305 spin_lock(&mib->stats64_lock); 2306 2307 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast + 2308 raw->rx_pause; 2309 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast + 2310 raw->tx_pause; 2311 2312 /* HW counters are counting bytes + FCS which is not acceptable 2313 * for rtnl_link_stats64 interface 2314 */ 2315 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN; 2316 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN; 2317 2318 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments + 2319 raw->rx_oversize; 2320 2321 stats->rx_crc_errors = raw->rx_crc_err; 2322 stats->rx_frame_errors = raw->rx_align_err; 2323 stats->rx_dropped = raw->rx_discards; 2324 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + 2325 stats->rx_frame_errors + stats->rx_dropped; 2326 2327 stats->tx_window_errors = raw->tx_late_col; 2328 stats->tx_fifo_errors = raw->tx_discards; 2329 stats->tx_aborted_errors = raw->tx_exc_col; 2330 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors + 2331 stats->tx_aborted_errors; 2332 2333 stats->multicast = raw->rx_mcast; 2334 stats->collisions = raw->tx_total_col; 2335 2336 pstats->tx_pause_frames = raw->tx_pause; 2337 pstats->rx_pause_frames = raw->rx_pause; 2338 2339 spin_unlock(&mib->stats64_lock); 2340 } 2341 2342 static void ksz_get_stats64(struct dsa_switch *ds, int port, 2343 struct rtnl_link_stats64 *s) 2344 { 2345 struct ksz_device *dev = ds->priv; 2346 struct ksz_port_mib *mib; 2347 2348 mib = &dev->ports[port].mib; 2349 2350 spin_lock(&mib->stats64_lock); 2351 memcpy(s, &mib->stats64, sizeof(*s)); 2352 spin_unlock(&mib->stats64_lock); 2353 } 2354 2355 static void ksz_get_pause_stats(struct dsa_switch *ds, int port, 2356 struct ethtool_pause_stats *pause_stats) 2357 { 2358 struct ksz_device *dev = ds->priv; 2359 struct ksz_port_mib *mib; 2360 2361 mib = &dev->ports[port].mib; 2362 2363 spin_lock(&mib->stats64_lock); 2364 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats)); 2365 spin_unlock(&mib->stats64_lock); 2366 } 2367 2368 static void ksz_get_strings(struct dsa_switch *ds, int port, 2369 u32 stringset, uint8_t *buf) 2370 { 2371 struct ksz_device *dev = ds->priv; 2372 int i; 2373 2374 if (stringset != ETH_SS_STATS) 2375 return; 2376 2377 for (i = 0; i < dev->info->mib_cnt; i++) 2378 ethtool_puts(&buf, dev->info->mib_names[i].string); 2379 } 2380 2381 /** 2382 * ksz_update_port_member - Adjust port forwarding rules based on STP state and 2383 * isolation settings. 2384 * @dev: A pointer to the struct ksz_device representing the device. 2385 * @port: The port number to adjust. 2386 * 2387 * This function dynamically adjusts the port membership configuration for a 2388 * specified port and other device ports, based on Spanning Tree Protocol (STP) 2389 * states and port isolation settings. Each port, including the CPU port, has a 2390 * membership register, represented as a bitfield, where each bit corresponds 2391 * to a port number. A set bit indicates permission to forward frames to that 2392 * port. This function iterates over all ports, updating the membership register 2393 * to reflect current forwarding permissions: 2394 * 2395 * 1. Forwards frames only to ports that are part of the same bridge group and 2396 * in the BR_STATE_FORWARDING state. 2397 * 2. Takes into account the isolation status of ports; ports in the 2398 * BR_STATE_FORWARDING state with BR_ISOLATED configuration will not forward 2399 * frames to each other, even if they are in the same bridge group. 2400 * 3. Ensures that the CPU port is included in the membership based on its 2401 * upstream port configuration, allowing for management and control traffic 2402 * to flow as required. 2403 */ 2404 static void ksz_update_port_member(struct ksz_device *dev, int port) 2405 { 2406 struct ksz_port *p = &dev->ports[port]; 2407 struct dsa_switch *ds = dev->ds; 2408 u8 port_member = 0, cpu_port; 2409 const struct dsa_port *dp; 2410 int i, j; 2411 2412 if (!dsa_is_user_port(ds, port)) 2413 return; 2414 2415 dp = dsa_to_port(ds, port); 2416 cpu_port = BIT(dsa_upstream_port(ds, port)); 2417 2418 for (i = 0; i < ds->num_ports; i++) { 2419 const struct dsa_port *other_dp = dsa_to_port(ds, i); 2420 struct ksz_port *other_p = &dev->ports[i]; 2421 u8 val = 0; 2422 2423 if (!dsa_is_user_port(ds, i)) 2424 continue; 2425 if (port == i) 2426 continue; 2427 if (!dsa_port_bridge_same(dp, other_dp)) 2428 continue; 2429 if (other_p->stp_state != BR_STATE_FORWARDING) 2430 continue; 2431 2432 /* At this point we know that "port" and "other" port [i] are in 2433 * the same bridge group and that "other" port [i] is in 2434 * forwarding stp state. If "port" is also in forwarding stp 2435 * state, we can allow forwarding from port [port] to port [i]. 2436 * Except if both ports are isolated. 2437 */ 2438 if (p->stp_state == BR_STATE_FORWARDING && 2439 !(p->isolated && other_p->isolated)) { 2440 val |= BIT(port); 2441 port_member |= BIT(i); 2442 } 2443 2444 /* Retain port [i]'s relationship to other ports than [port] */ 2445 for (j = 0; j < ds->num_ports; j++) { 2446 const struct dsa_port *third_dp; 2447 struct ksz_port *third_p; 2448 2449 if (j == i) 2450 continue; 2451 if (j == port) 2452 continue; 2453 if (!dsa_is_user_port(ds, j)) 2454 continue; 2455 third_p = &dev->ports[j]; 2456 if (third_p->stp_state != BR_STATE_FORWARDING) 2457 continue; 2458 2459 third_dp = dsa_to_port(ds, j); 2460 2461 /* Now we updating relation of the "other" port [i] to 2462 * the "third" port [j]. We already know that "other" 2463 * port [i] is in forwarding stp state and that "third" 2464 * port [j] is in forwarding stp state too. 2465 * We need to check if "other" port [i] and "third" port 2466 * [j] are in the same bridge group and not isolated 2467 * before allowing forwarding from port [i] to port [j]. 2468 */ 2469 if (dsa_port_bridge_same(other_dp, third_dp) && 2470 !(other_p->isolated && third_p->isolated)) 2471 val |= BIT(j); 2472 } 2473 2474 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port); 2475 } 2476 2477 /* HSR ports are setup once so need to use the assigned membership 2478 * when the port is enabled. 2479 */ 2480 if (!port_member && p->stp_state == BR_STATE_FORWARDING && 2481 (dev->hsr_ports & BIT(port))) 2482 port_member = dev->hsr_ports; 2483 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port); 2484 } 2485 2486 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) 2487 { 2488 struct ksz_device *dev = bus->priv; 2489 u16 val; 2490 int ret; 2491 2492 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val); 2493 if (ret < 0) 2494 return ret; 2495 2496 return val; 2497 } 2498 2499 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, 2500 u16 val) 2501 { 2502 struct ksz_device *dev = bus->priv; 2503 2504 return dev->dev_ops->w_phy(dev, addr, regnum, val); 2505 } 2506 2507 /** 2508 * ksz_parent_mdio_read - Read data from a PHY register on the parent MDIO bus. 2509 * @bus: MDIO bus structure. 2510 * @addr: PHY address on the parent MDIO bus. 2511 * @regnum: Register number to read. 2512 * 2513 * This function provides a direct read operation on the parent MDIO bus for 2514 * accessing PHY registers. By bypassing SPI or I2C, it uses the parent MDIO bus 2515 * to retrieve data from the PHY registers at the specified address and register 2516 * number. 2517 * 2518 * Return: Value of the PHY register, or a negative error code on failure. 2519 */ 2520 static int ksz_parent_mdio_read(struct mii_bus *bus, int addr, int regnum) 2521 { 2522 struct ksz_device *dev = bus->priv; 2523 2524 return mdiobus_read_nested(dev->parent_mdio_bus, addr, regnum); 2525 } 2526 2527 /** 2528 * ksz_parent_mdio_write - Write data to a PHY register on the parent MDIO bus. 2529 * @bus: MDIO bus structure. 2530 * @addr: PHY address on the parent MDIO bus. 2531 * @regnum: Register number to write to. 2532 * @val: Value to write to the PHY register. 2533 * 2534 * This function provides a direct write operation on the parent MDIO bus for 2535 * accessing PHY registers. Bypassing SPI or I2C, it uses the parent MDIO bus 2536 * to modify the PHY register values at the specified address. 2537 * 2538 * Return: 0 on success, or a negative error code on failure. 2539 */ 2540 static int ksz_parent_mdio_write(struct mii_bus *bus, int addr, int regnum, 2541 u16 val) 2542 { 2543 struct ksz_device *dev = bus->priv; 2544 2545 return mdiobus_write_nested(dev->parent_mdio_bus, addr, regnum, val); 2546 } 2547 2548 /** 2549 * ksz_phy_addr_to_port - Map a PHY address to the corresponding switch port. 2550 * @dev: Pointer to device structure. 2551 * @addr: PHY address to map to a port. 2552 * 2553 * This function finds the corresponding switch port for a given PHY address by 2554 * iterating over all user ports on the device. It checks if a port's PHY 2555 * address in `phy_addr_map` matches the specified address and if the port 2556 * contains an internal PHY. If a match is found, the index of the port is 2557 * returned. 2558 * 2559 * Return: Port index on success, or -EINVAL if no matching port is found. 2560 */ 2561 static int ksz_phy_addr_to_port(struct ksz_device *dev, int addr) 2562 { 2563 struct dsa_switch *ds = dev->ds; 2564 struct dsa_port *dp; 2565 2566 dsa_switch_for_each_user_port(dp, ds) { 2567 if (dev->info->internal_phy[dp->index] && 2568 dev->phy_addr_map[dp->index] == addr) 2569 return dp->index; 2570 } 2571 2572 return -EINVAL; 2573 } 2574 2575 /** 2576 * ksz_irq_phy_setup - Configure IRQs for PHYs in the KSZ device. 2577 * @dev: Pointer to the KSZ device structure. 2578 * 2579 * Sets up IRQs for each active PHY connected to the KSZ switch by mapping the 2580 * appropriate IRQs for each PHY and assigning them to the `user_mii_bus` in 2581 * the DSA switch structure. Each IRQ is mapped based on the port's IRQ domain. 2582 * 2583 * Return: 0 on success, or a negative error code on failure. 2584 */ 2585 static int ksz_irq_phy_setup(struct ksz_device *dev) 2586 { 2587 struct dsa_switch *ds = dev->ds; 2588 int phy, port; 2589 int irq; 2590 int ret; 2591 2592 for (phy = 0; phy < PHY_MAX_ADDR; phy++) { 2593 if (BIT(phy) & ds->phys_mii_mask) { 2594 port = ksz_phy_addr_to_port(dev, phy); 2595 if (port < 0) { 2596 ret = port; 2597 goto out; 2598 } 2599 2600 irq = irq_find_mapping(dev->ports[port].pirq.domain, 2601 PORT_SRC_PHY_INT); 2602 if (!irq) { 2603 ret = -EINVAL; 2604 goto out; 2605 } 2606 ds->user_mii_bus->irq[phy] = irq; 2607 } 2608 } 2609 return 0; 2610 out: 2611 while (phy--) 2612 if (BIT(phy) & ds->phys_mii_mask) 2613 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2614 2615 return ret; 2616 } 2617 2618 /** 2619 * ksz_irq_phy_free - Release IRQ mappings for PHYs in the KSZ device. 2620 * @dev: Pointer to the KSZ device structure. 2621 * 2622 * Releases any IRQ mappings previously assigned to active PHYs in the KSZ 2623 * switch by disposing of each mapped IRQ in the `user_mii_bus` structure. 2624 */ 2625 static void ksz_irq_phy_free(struct ksz_device *dev) 2626 { 2627 struct dsa_switch *ds = dev->ds; 2628 int phy; 2629 2630 for (phy = 0; phy < PHY_MAX_ADDR; phy++) 2631 if (BIT(phy) & ds->phys_mii_mask) 2632 irq_dispose_mapping(ds->user_mii_bus->irq[phy]); 2633 } 2634 2635 /** 2636 * ksz_parse_dt_phy_config - Parse and validate PHY configuration from DT 2637 * @dev: pointer to the KSZ device structure 2638 * @bus: pointer to the MII bus structure 2639 * @mdio_np: pointer to the MDIO node in the device tree 2640 * 2641 * This function parses and validates PHY configurations for each user port 2642 * defined in the device tree for a KSZ switch device. It verifies that the 2643 * `phy-handle` properties are correctly set and that the internal PHYs match 2644 * expected addresses and parent nodes. Sets up the PHY mask in the MII bus if 2645 * all validations pass. Logs error messages for any mismatches or missing data. 2646 * 2647 * Return: 0 on success, or a negative error code on failure. 2648 */ 2649 static int ksz_parse_dt_phy_config(struct ksz_device *dev, struct mii_bus *bus, 2650 struct device_node *mdio_np) 2651 { 2652 struct device_node *phy_node, *phy_parent_node; 2653 bool phys_are_valid = true; 2654 struct dsa_port *dp; 2655 u32 phy_addr; 2656 int ret; 2657 2658 dsa_switch_for_each_user_port(dp, dev->ds) { 2659 if (!dev->info->internal_phy[dp->index]) 2660 continue; 2661 2662 phy_node = of_parse_phandle(dp->dn, "phy-handle", 0); 2663 if (!phy_node) { 2664 dev_err(dev->dev, "failed to parse phy-handle for port %d.\n", 2665 dp->index); 2666 phys_are_valid = false; 2667 continue; 2668 } 2669 2670 phy_parent_node = of_get_parent(phy_node); 2671 if (!phy_parent_node) { 2672 dev_err(dev->dev, "failed to get PHY-parent node for port %d\n", 2673 dp->index); 2674 phys_are_valid = false; 2675 } else if (phy_parent_node != mdio_np) { 2676 dev_err(dev->dev, "PHY-parent node mismatch for port %d, expected %pOF, got %pOF\n", 2677 dp->index, mdio_np, phy_parent_node); 2678 phys_are_valid = false; 2679 } else { 2680 ret = of_property_read_u32(phy_node, "reg", &phy_addr); 2681 if (ret < 0) { 2682 dev_err(dev->dev, "failed to read PHY address for port %d. Error %d\n", 2683 dp->index, ret); 2684 phys_are_valid = false; 2685 } else if (phy_addr != dev->phy_addr_map[dp->index]) { 2686 dev_err(dev->dev, "PHY address mismatch for port %d, expected 0x%x, got 0x%x\n", 2687 dp->index, dev->phy_addr_map[dp->index], 2688 phy_addr); 2689 phys_are_valid = false; 2690 } else { 2691 bus->phy_mask |= BIT(phy_addr); 2692 } 2693 } 2694 2695 of_node_put(phy_node); 2696 of_node_put(phy_parent_node); 2697 } 2698 2699 if (!phys_are_valid) 2700 return -EINVAL; 2701 2702 return 0; 2703 } 2704 2705 /** 2706 * ksz_mdio_register - Register and configure the MDIO bus for the KSZ device. 2707 * @dev: Pointer to the KSZ device structure. 2708 * 2709 * This function sets up and registers an MDIO bus for the KSZ switch device, 2710 * allowing access to its internal PHYs. If the device supports side MDIO, 2711 * the function will configure the external MDIO controller specified by the 2712 * "mdio-parent-bus" device tree property to directly manage internal PHYs. 2713 * Otherwise, SPI or I2C access is set up for PHY access. 2714 * 2715 * Return: 0 on success, or a negative error code on failure. 2716 */ 2717 static int ksz_mdio_register(struct ksz_device *dev) 2718 { 2719 struct device_node *parent_bus_node; 2720 struct mii_bus *parent_bus = NULL; 2721 struct dsa_switch *ds = dev->ds; 2722 struct device_node *mdio_np; 2723 struct mii_bus *bus; 2724 int ret, i; 2725 2726 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio"); 2727 if (!mdio_np) 2728 return 0; 2729 2730 parent_bus_node = of_parse_phandle(mdio_np, "mdio-parent-bus", 0); 2731 if (parent_bus_node && !dev->info->phy_side_mdio_supported) { 2732 dev_err(dev->dev, "Side MDIO bus is not supported for this HW, ignoring 'mdio-parent-bus' property.\n"); 2733 ret = -EINVAL; 2734 2735 goto put_mdio_node; 2736 } else if (parent_bus_node) { 2737 parent_bus = of_mdio_find_bus(parent_bus_node); 2738 if (!parent_bus) { 2739 ret = -EPROBE_DEFER; 2740 2741 goto put_mdio_node; 2742 } 2743 2744 dev->parent_mdio_bus = parent_bus; 2745 } 2746 2747 bus = devm_mdiobus_alloc(ds->dev); 2748 if (!bus) { 2749 ret = -ENOMEM; 2750 goto put_mdio_node; 2751 } 2752 2753 if (dev->dev_ops->mdio_bus_preinit) { 2754 ret = dev->dev_ops->mdio_bus_preinit(dev, !!parent_bus); 2755 if (ret) 2756 goto put_mdio_node; 2757 } 2758 2759 if (dev->dev_ops->create_phy_addr_map) { 2760 ret = dev->dev_ops->create_phy_addr_map(dev, !!parent_bus); 2761 if (ret) 2762 goto put_mdio_node; 2763 } else { 2764 for (i = 0; i < dev->info->port_cnt; i++) 2765 dev->phy_addr_map[i] = i; 2766 } 2767 2768 bus->priv = dev; 2769 if (parent_bus) { 2770 bus->read = ksz_parent_mdio_read; 2771 bus->write = ksz_parent_mdio_write; 2772 bus->name = "KSZ side MDIO"; 2773 snprintf(bus->id, MII_BUS_ID_SIZE, "ksz-side-mdio-%d", 2774 ds->index); 2775 } else { 2776 bus->read = ksz_sw_mdio_read; 2777 bus->write = ksz_sw_mdio_write; 2778 bus->name = "ksz user smi"; 2779 if (ds->dst->index != 0) { 2780 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d-%d", ds->dst->index, ds->index); 2781 } else { 2782 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index); 2783 } 2784 } 2785 2786 ret = ksz_parse_dt_phy_config(dev, bus, mdio_np); 2787 if (ret) 2788 goto put_mdio_node; 2789 2790 ds->phys_mii_mask = bus->phy_mask; 2791 bus->parent = ds->dev; 2792 2793 ds->user_mii_bus = bus; 2794 2795 if (dev->irq > 0) { 2796 ret = ksz_irq_phy_setup(dev); 2797 if (ret) 2798 goto put_mdio_node; 2799 } 2800 2801 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np); 2802 if (ret) { 2803 dev_err(ds->dev, "unable to register MDIO bus %s\n", 2804 bus->id); 2805 if (dev->irq > 0) 2806 ksz_irq_phy_free(dev); 2807 } 2808 2809 put_mdio_node: 2810 of_node_put(mdio_np); 2811 of_node_put(parent_bus_node); 2812 2813 return ret; 2814 } 2815 2816 static void ksz_irq_mask(struct irq_data *d) 2817 { 2818 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2819 2820 kirq->masked |= BIT(d->hwirq); 2821 } 2822 2823 static void ksz_irq_unmask(struct irq_data *d) 2824 { 2825 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2826 2827 kirq->masked &= ~BIT(d->hwirq); 2828 } 2829 2830 static void ksz_irq_bus_lock(struct irq_data *d) 2831 { 2832 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2833 2834 mutex_lock(&kirq->dev->lock_irq); 2835 } 2836 2837 static void ksz_irq_bus_sync_unlock(struct irq_data *d) 2838 { 2839 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d); 2840 struct ksz_device *dev = kirq->dev; 2841 int ret; 2842 2843 ret = ksz_write8(dev, kirq->reg_mask, kirq->masked); 2844 if (ret) 2845 dev_err(dev->dev, "failed to change IRQ mask\n"); 2846 2847 mutex_unlock(&dev->lock_irq); 2848 } 2849 2850 static const struct irq_chip ksz_irq_chip = { 2851 .name = "ksz-irq", 2852 .irq_mask = ksz_irq_mask, 2853 .irq_unmask = ksz_irq_unmask, 2854 .irq_bus_lock = ksz_irq_bus_lock, 2855 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock, 2856 }; 2857 2858 static int ksz_irq_domain_map(struct irq_domain *d, 2859 unsigned int irq, irq_hw_number_t hwirq) 2860 { 2861 irq_set_chip_data(irq, d->host_data); 2862 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq); 2863 irq_set_noprobe(irq); 2864 2865 return 0; 2866 } 2867 2868 static const struct irq_domain_ops ksz_irq_domain_ops = { 2869 .map = ksz_irq_domain_map, 2870 .xlate = irq_domain_xlate_twocell, 2871 }; 2872 2873 static void ksz_irq_free(struct ksz_irq *kirq) 2874 { 2875 int irq, virq; 2876 2877 free_irq(kirq->irq_num, kirq); 2878 2879 for (irq = 0; irq < kirq->nirqs; irq++) { 2880 virq = irq_find_mapping(kirq->domain, irq); 2881 irq_dispose_mapping(virq); 2882 } 2883 2884 irq_domain_remove(kirq->domain); 2885 } 2886 2887 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id) 2888 { 2889 struct ksz_irq *kirq = dev_id; 2890 unsigned int nhandled = 0; 2891 struct ksz_device *dev; 2892 unsigned int sub_irq; 2893 u8 data; 2894 int ret; 2895 u8 n; 2896 2897 dev = kirq->dev; 2898 2899 /* Read interrupt status register */ 2900 ret = ksz_read8(dev, kirq->reg_status, &data); 2901 if (ret) 2902 goto out; 2903 2904 for (n = 0; n < kirq->nirqs; ++n) { 2905 if (data & BIT(n)) { 2906 sub_irq = irq_find_mapping(kirq->domain, n); 2907 handle_nested_irq(sub_irq); 2908 ++nhandled; 2909 } 2910 } 2911 out: 2912 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 2913 } 2914 2915 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq) 2916 { 2917 int ret, n; 2918 2919 kirq->dev = dev; 2920 2921 kirq->domain = irq_domain_create_simple(dev_fwnode(dev->dev), kirq->nirqs, 0, 2922 &ksz_irq_domain_ops, kirq); 2923 if (!kirq->domain) 2924 return -ENOMEM; 2925 2926 for (n = 0; n < kirq->nirqs; n++) 2927 irq_create_mapping(kirq->domain, n); 2928 2929 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn, 2930 IRQF_ONESHOT, kirq->name, kirq); 2931 if (ret) 2932 goto out; 2933 2934 return 0; 2935 2936 out: 2937 ksz_irq_free(kirq); 2938 2939 return ret; 2940 } 2941 2942 static int ksz_girq_setup(struct ksz_device *dev) 2943 { 2944 struct ksz_irq *girq = &dev->girq; 2945 2946 girq->nirqs = dev->info->port_cnt; 2947 girq->reg_mask = REG_SW_PORT_INT_MASK__1; 2948 girq->reg_status = REG_SW_PORT_INT_STATUS__1; 2949 girq->masked = ~0; 2950 snprintf(girq->name, sizeof(girq->name), "global_port_irq"); 2951 2952 girq->irq_num = dev->irq; 2953 2954 return ksz_irq_common_setup(dev, girq); 2955 } 2956 2957 static int ksz_pirq_setup(struct ksz_device *dev, u8 p) 2958 { 2959 struct ksz_irq *pirq = &dev->ports[p].pirq; 2960 2961 pirq->nirqs = dev->info->port_nirqs; 2962 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK); 2963 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS); 2964 pirq->masked = ~0; 2965 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p); 2966 2967 pirq->irq_num = irq_find_mapping(dev->girq.domain, p); 2968 if (!pirq->irq_num) 2969 return -EINVAL; 2970 2971 return ksz_irq_common_setup(dev, pirq); 2972 } 2973 2974 static int ksz_parse_drive_strength(struct ksz_device *dev); 2975 2976 static int ksz_setup(struct dsa_switch *ds) 2977 { 2978 struct ksz_device *dev = ds->priv; 2979 u16 storm_mask, storm_rate; 2980 struct dsa_port *dp; 2981 struct ksz_port *p; 2982 const u16 *regs; 2983 int ret; 2984 2985 regs = dev->info->regs; 2986 2987 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2988 dev->info->num_vlans, GFP_KERNEL); 2989 if (!dev->vlan_cache) 2990 return -ENOMEM; 2991 2992 ret = dev->dev_ops->reset(dev); 2993 if (ret) { 2994 dev_err(ds->dev, "failed to reset switch\n"); 2995 return ret; 2996 } 2997 2998 ret = ksz_parse_drive_strength(dev); 2999 if (ret) 3000 return ret; 3001 3002 if (ksz_has_sgmii_port(dev) && dev->dev_ops->pcs_create) { 3003 ret = dev->dev_ops->pcs_create(dev); 3004 if (ret) 3005 return ret; 3006 } 3007 3008 /* set broadcast storm protection 10% rate */ 3009 storm_mask = BROADCAST_STORM_RATE; 3010 storm_rate = (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100; 3011 if (ksz_is_ksz8463(dev)) { 3012 storm_mask = swab16(storm_mask); 3013 storm_rate = swab16(storm_rate); 3014 } 3015 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 3016 storm_mask, storm_rate); 3017 3018 dev->dev_ops->config_cpu_port(ds); 3019 3020 dev->dev_ops->enable_stp_addr(dev); 3021 3022 ds->num_tx_queues = dev->info->num_tx_queues; 3023 3024 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 3025 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 3026 3027 ksz_init_mib_timer(dev); 3028 3029 ds->configure_vlan_while_not_filtering = false; 3030 ds->dscp_prio_mapping_is_global = true; 3031 3032 if (dev->dev_ops->setup) { 3033 ret = dev->dev_ops->setup(ds); 3034 if (ret) 3035 return ret; 3036 } 3037 3038 /* Start with learning disabled on standalone user ports, and enabled 3039 * on the CPU port. In lack of other finer mechanisms, learning on the 3040 * CPU port will avoid flooding bridge local addresses on the network 3041 * in some cases. 3042 */ 3043 p = &dev->ports[dev->cpu_port]; 3044 p->learning = true; 3045 3046 if (dev->irq > 0) { 3047 ret = ksz_girq_setup(dev); 3048 if (ret) 3049 return ret; 3050 3051 dsa_switch_for_each_user_port(dp, dev->ds) { 3052 ret = ksz_pirq_setup(dev, dp->index); 3053 if (ret) 3054 goto port_release; 3055 3056 if (dev->info->ptp_capable) { 3057 ret = ksz_ptp_irq_setup(ds, dp->index); 3058 if (ret) 3059 goto pirq_release; 3060 } 3061 } 3062 } 3063 3064 if (dev->info->ptp_capable) { 3065 ret = ksz_ptp_clock_register(ds); 3066 if (ret) { 3067 dev_err(dev->dev, "Failed to register PTP clock: %d\n", 3068 ret); 3069 goto port_release; 3070 } 3071 } 3072 3073 ret = ksz_mdio_register(dev); 3074 if (ret < 0) { 3075 dev_err(dev->dev, "failed to register the mdio"); 3076 goto out_ptp_clock_unregister; 3077 } 3078 3079 ret = ksz_dcb_init(dev); 3080 if (ret) 3081 goto out_ptp_clock_unregister; 3082 3083 /* start switch */ 3084 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 3085 SW_START, SW_START); 3086 3087 return 0; 3088 3089 out_ptp_clock_unregister: 3090 if (dev->info->ptp_capable) 3091 ksz_ptp_clock_unregister(ds); 3092 port_release: 3093 if (dev->irq > 0) { 3094 dsa_switch_for_each_user_port_continue_reverse(dp, dev->ds) { 3095 if (dev->info->ptp_capable) 3096 ksz_ptp_irq_free(ds, dp->index); 3097 pirq_release: 3098 ksz_irq_free(&dev->ports[dp->index].pirq); 3099 } 3100 ksz_irq_free(&dev->girq); 3101 } 3102 3103 return ret; 3104 } 3105 3106 static void ksz_teardown(struct dsa_switch *ds) 3107 { 3108 struct ksz_device *dev = ds->priv; 3109 struct dsa_port *dp; 3110 3111 if (dev->info->ptp_capable) 3112 ksz_ptp_clock_unregister(ds); 3113 3114 if (dev->irq > 0) { 3115 dsa_switch_for_each_user_port(dp, dev->ds) { 3116 if (dev->info->ptp_capable) 3117 ksz_ptp_irq_free(ds, dp->index); 3118 3119 ksz_irq_free(&dev->ports[dp->index].pirq); 3120 } 3121 3122 ksz_irq_free(&dev->girq); 3123 } 3124 3125 if (dev->dev_ops->teardown) 3126 dev->dev_ops->teardown(ds); 3127 } 3128 3129 static void port_r_cnt(struct ksz_device *dev, int port) 3130 { 3131 struct ksz_port_mib *mib = &dev->ports[port].mib; 3132 u64 *dropped; 3133 3134 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 3135 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 3136 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 3137 &mib->counters[mib->cnt_ptr]); 3138 ++mib->cnt_ptr; 3139 } 3140 3141 /* last one in storage */ 3142 dropped = &mib->counters[dev->info->mib_cnt]; 3143 3144 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 3145 while (mib->cnt_ptr < dev->info->mib_cnt) { 3146 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 3147 dropped, &mib->counters[mib->cnt_ptr]); 3148 ++mib->cnt_ptr; 3149 } 3150 mib->cnt_ptr = 0; 3151 } 3152 3153 static void ksz_mib_read_work(struct work_struct *work) 3154 { 3155 struct ksz_device *dev = container_of(work, struct ksz_device, 3156 mib_read.work); 3157 struct ksz_port_mib *mib; 3158 struct ksz_port *p; 3159 int i; 3160 3161 for (i = 0; i < dev->info->port_cnt; i++) { 3162 if (dsa_is_unused_port(dev->ds, i)) 3163 continue; 3164 3165 p = &dev->ports[i]; 3166 mib = &p->mib; 3167 mutex_lock(&mib->cnt_mutex); 3168 3169 /* Only read MIB counters when the port is told to do. 3170 * If not, read only dropped counters when link is not up. 3171 */ 3172 if (!p->read) { 3173 const struct dsa_port *dp = dsa_to_port(dev->ds, i); 3174 3175 if (!netif_carrier_ok(dp->user)) 3176 mib->cnt_ptr = dev->info->reg_mib_cnt; 3177 } 3178 port_r_cnt(dev, i); 3179 p->read = false; 3180 3181 if (dev->dev_ops->r_mib_stat64) 3182 dev->dev_ops->r_mib_stat64(dev, i); 3183 3184 mutex_unlock(&mib->cnt_mutex); 3185 } 3186 3187 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 3188 } 3189 3190 void ksz_init_mib_timer(struct ksz_device *dev) 3191 { 3192 int i; 3193 3194 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work); 3195 3196 for (i = 0; i < dev->info->port_cnt; i++) { 3197 struct ksz_port_mib *mib = &dev->ports[i].mib; 3198 3199 dev->dev_ops->port_init_cnt(dev, i); 3200 3201 mib->cnt_ptr = 0; 3202 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64)); 3203 } 3204 } 3205 3206 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg) 3207 { 3208 struct ksz_device *dev = ds->priv; 3209 u16 val = 0xffff; 3210 int ret; 3211 3212 ret = dev->dev_ops->r_phy(dev, addr, reg, &val); 3213 if (ret) 3214 return ret; 3215 3216 return val; 3217 } 3218 3219 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 3220 { 3221 struct ksz_device *dev = ds->priv; 3222 int ret; 3223 3224 ret = dev->dev_ops->w_phy(dev, addr, reg, val); 3225 if (ret) 3226 return ret; 3227 3228 return 0; 3229 } 3230 3231 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port) 3232 { 3233 struct ksz_device *dev = ds->priv; 3234 3235 switch (dev->chip_id) { 3236 case KSZ88X3_CHIP_ID: 3237 /* Silicon Errata Sheet (DS80000830A): 3238 * Port 1 does not work with LinkMD Cable-Testing. 3239 * Port 1 does not respond to received PAUSE control frames. 3240 */ 3241 if (!port) 3242 return MICREL_KSZ8_P1_ERRATA; 3243 break; 3244 } 3245 3246 return 0; 3247 } 3248 3249 static void ksz_phylink_mac_link_down(struct phylink_config *config, 3250 unsigned int mode, 3251 phy_interface_t interface) 3252 { 3253 struct dsa_port *dp = dsa_phylink_to_port(config); 3254 struct ksz_device *dev = dp->ds->priv; 3255 3256 /* Read all MIB counters when the link is going down. */ 3257 dev->ports[dp->index].read = true; 3258 /* timer started */ 3259 if (dev->mib_read_interval) 3260 schedule_delayed_work(&dev->mib_read, 0); 3261 } 3262 3263 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset) 3264 { 3265 struct ksz_device *dev = ds->priv; 3266 3267 if (sset != ETH_SS_STATS) 3268 return 0; 3269 3270 return dev->info->mib_cnt; 3271 } 3272 3273 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port, 3274 uint64_t *buf) 3275 { 3276 const struct dsa_port *dp = dsa_to_port(ds, port); 3277 struct ksz_device *dev = ds->priv; 3278 struct ksz_port_mib *mib; 3279 3280 mib = &dev->ports[port].mib; 3281 mutex_lock(&mib->cnt_mutex); 3282 3283 /* Only read dropped counters if no link. */ 3284 if (!netif_carrier_ok(dp->user)) 3285 mib->cnt_ptr = dev->info->reg_mib_cnt; 3286 port_r_cnt(dev, port); 3287 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64)); 3288 mutex_unlock(&mib->cnt_mutex); 3289 } 3290 3291 static int ksz_port_bridge_join(struct dsa_switch *ds, int port, 3292 struct dsa_bridge bridge, 3293 bool *tx_fwd_offload, 3294 struct netlink_ext_ack *extack) 3295 { 3296 /* port_stp_state_set() will be called after to put the port in 3297 * appropriate state so there is no need to do anything. 3298 */ 3299 3300 return 0; 3301 } 3302 3303 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port, 3304 struct dsa_bridge bridge) 3305 { 3306 /* port_stp_state_set() will be called after to put the port in 3307 * forwarding state so there is no need to do anything. 3308 */ 3309 } 3310 3311 static void ksz_port_fast_age(struct dsa_switch *ds, int port) 3312 { 3313 struct ksz_device *dev = ds->priv; 3314 3315 dev->dev_ops->flush_dyn_mac_table(dev, port); 3316 } 3317 3318 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 3319 { 3320 struct ksz_device *dev = ds->priv; 3321 3322 if (!dev->dev_ops->set_ageing_time) 3323 return -EOPNOTSUPP; 3324 3325 return dev->dev_ops->set_ageing_time(dev, msecs); 3326 } 3327 3328 static int ksz_port_fdb_add(struct dsa_switch *ds, int port, 3329 const unsigned char *addr, u16 vid, 3330 struct dsa_db db) 3331 { 3332 struct ksz_device *dev = ds->priv; 3333 3334 if (!dev->dev_ops->fdb_add) 3335 return -EOPNOTSUPP; 3336 3337 return dev->dev_ops->fdb_add(dev, port, addr, vid, db); 3338 } 3339 3340 static int ksz_port_fdb_del(struct dsa_switch *ds, int port, 3341 const unsigned char *addr, 3342 u16 vid, struct dsa_db db) 3343 { 3344 struct ksz_device *dev = ds->priv; 3345 3346 if (!dev->dev_ops->fdb_del) 3347 return -EOPNOTSUPP; 3348 3349 return dev->dev_ops->fdb_del(dev, port, addr, vid, db); 3350 } 3351 3352 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port, 3353 dsa_fdb_dump_cb_t *cb, void *data) 3354 { 3355 struct ksz_device *dev = ds->priv; 3356 3357 if (!dev->dev_ops->fdb_dump) 3358 return -EOPNOTSUPP; 3359 3360 return dev->dev_ops->fdb_dump(dev, port, cb, data); 3361 } 3362 3363 static int ksz_port_mdb_add(struct dsa_switch *ds, int port, 3364 const struct switchdev_obj_port_mdb *mdb, 3365 struct dsa_db db) 3366 { 3367 struct ksz_device *dev = ds->priv; 3368 3369 if (!dev->dev_ops->mdb_add) 3370 return -EOPNOTSUPP; 3371 3372 return dev->dev_ops->mdb_add(dev, port, mdb, db); 3373 } 3374 3375 static int ksz_port_mdb_del(struct dsa_switch *ds, int port, 3376 const struct switchdev_obj_port_mdb *mdb, 3377 struct dsa_db db) 3378 { 3379 struct ksz_device *dev = ds->priv; 3380 3381 if (!dev->dev_ops->mdb_del) 3382 return -EOPNOTSUPP; 3383 3384 return dev->dev_ops->mdb_del(dev, port, mdb, db); 3385 } 3386 3387 static int ksz9477_set_default_prio_queue_mapping(struct ksz_device *dev, 3388 int port) 3389 { 3390 u32 queue_map = 0; 3391 int ipm; 3392 3393 for (ipm = 0; ipm < dev->info->num_ipms; ipm++) { 3394 int queue; 3395 3396 /* Traffic Type (TT) is corresponding to the Internal Priority 3397 * Map (IPM) in the switch. Traffic Class (TC) is 3398 * corresponding to the queue in the switch. 3399 */ 3400 queue = ieee8021q_tt_to_tc(ipm, dev->info->num_tx_queues); 3401 if (queue < 0) 3402 return queue; 3403 3404 queue_map |= queue << (ipm * KSZ9477_PORT_TC_MAP_S); 3405 } 3406 3407 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 3408 } 3409 3410 static int ksz_port_setup(struct dsa_switch *ds, int port) 3411 { 3412 struct ksz_device *dev = ds->priv; 3413 int ret; 3414 3415 if (!dsa_is_user_port(ds, port)) 3416 return 0; 3417 3418 /* setup user port */ 3419 dev->dev_ops->port_setup(dev, port, false); 3420 3421 if (!is_ksz8(dev)) { 3422 ret = ksz9477_set_default_prio_queue_mapping(dev, port); 3423 if (ret) 3424 return ret; 3425 } 3426 3427 /* port_stp_state_set() will be called after to enable the port so 3428 * there is no need to do anything. 3429 */ 3430 3431 return ksz_dcb_init_port(dev, port); 3432 } 3433 3434 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 3435 { 3436 struct ksz_device *dev = ds->priv; 3437 struct ksz_port *p; 3438 const u16 *regs; 3439 u8 data; 3440 3441 regs = dev->info->regs; 3442 3443 ksz_pread8(dev, port, regs[P_STP_CTRL], &data); 3444 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE); 3445 3446 p = &dev->ports[port]; 3447 3448 switch (state) { 3449 case BR_STATE_DISABLED: 3450 data |= PORT_LEARN_DISABLE; 3451 break; 3452 case BR_STATE_LISTENING: 3453 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE); 3454 break; 3455 case BR_STATE_LEARNING: 3456 data |= PORT_RX_ENABLE; 3457 if (!p->learning) 3458 data |= PORT_LEARN_DISABLE; 3459 break; 3460 case BR_STATE_FORWARDING: 3461 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE); 3462 if (!p->learning) 3463 data |= PORT_LEARN_DISABLE; 3464 break; 3465 case BR_STATE_BLOCKING: 3466 data |= PORT_LEARN_DISABLE; 3467 break; 3468 default: 3469 dev_err(ds->dev, "invalid STP state: %d\n", state); 3470 return; 3471 } 3472 3473 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data); 3474 3475 p->stp_state = state; 3476 3477 ksz_update_port_member(dev, port); 3478 } 3479 3480 static void ksz_port_teardown(struct dsa_switch *ds, int port) 3481 { 3482 struct ksz_device *dev = ds->priv; 3483 3484 switch (dev->chip_id) { 3485 case KSZ8563_CHIP_ID: 3486 case KSZ8567_CHIP_ID: 3487 case KSZ9477_CHIP_ID: 3488 case KSZ9563_CHIP_ID: 3489 case KSZ9567_CHIP_ID: 3490 case KSZ9893_CHIP_ID: 3491 case KSZ9896_CHIP_ID: 3492 case KSZ9897_CHIP_ID: 3493 case LAN9646_CHIP_ID: 3494 if (dsa_is_user_port(ds, port)) 3495 ksz9477_port_acl_free(dev, port); 3496 } 3497 } 3498 3499 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port, 3500 struct switchdev_brport_flags flags, 3501 struct netlink_ext_ack *extack) 3502 { 3503 if (flags.mask & ~(BR_LEARNING | BR_ISOLATED)) 3504 return -EINVAL; 3505 3506 return 0; 3507 } 3508 3509 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port, 3510 struct switchdev_brport_flags flags, 3511 struct netlink_ext_ack *extack) 3512 { 3513 struct ksz_device *dev = ds->priv; 3514 struct ksz_port *p = &dev->ports[port]; 3515 3516 if (flags.mask & (BR_LEARNING | BR_ISOLATED)) { 3517 if (flags.mask & BR_LEARNING) 3518 p->learning = !!(flags.val & BR_LEARNING); 3519 3520 if (flags.mask & BR_ISOLATED) 3521 p->isolated = !!(flags.val & BR_ISOLATED); 3522 3523 /* Make the change take effect immediately */ 3524 ksz_port_stp_state_set(ds, port, p->stp_state); 3525 } 3526 3527 return 0; 3528 } 3529 3530 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds, 3531 int port, 3532 enum dsa_tag_protocol mp) 3533 { 3534 struct ksz_device *dev = ds->priv; 3535 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE; 3536 3537 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev)) 3538 proto = DSA_TAG_PROTO_KSZ8795; 3539 3540 if (dev->chip_id == KSZ88X3_CHIP_ID || 3541 dev->chip_id == KSZ8463_CHIP_ID || 3542 dev->chip_id == KSZ8563_CHIP_ID || 3543 dev->chip_id == KSZ9893_CHIP_ID || 3544 dev->chip_id == KSZ9563_CHIP_ID) 3545 proto = DSA_TAG_PROTO_KSZ9893; 3546 3547 if (dev->chip_id == KSZ8567_CHIP_ID || 3548 dev->chip_id == KSZ9477_CHIP_ID || 3549 dev->chip_id == KSZ9896_CHIP_ID || 3550 dev->chip_id == KSZ9897_CHIP_ID || 3551 dev->chip_id == KSZ9567_CHIP_ID || 3552 dev->chip_id == LAN9646_CHIP_ID) 3553 proto = DSA_TAG_PROTO_KSZ9477; 3554 3555 if (is_lan937x(dev)) 3556 proto = DSA_TAG_PROTO_LAN937X; 3557 3558 return proto; 3559 } 3560 3561 static int ksz_connect_tag_protocol(struct dsa_switch *ds, 3562 enum dsa_tag_protocol proto) 3563 { 3564 struct ksz_tagger_data *tagger_data; 3565 3566 switch (proto) { 3567 case DSA_TAG_PROTO_KSZ8795: 3568 return 0; 3569 case DSA_TAG_PROTO_KSZ9893: 3570 case DSA_TAG_PROTO_KSZ9477: 3571 case DSA_TAG_PROTO_LAN937X: 3572 tagger_data = ksz_tagger_data(ds); 3573 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 3574 return 0; 3575 default: 3576 return -EPROTONOSUPPORT; 3577 } 3578 } 3579 3580 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port, 3581 bool flag, struct netlink_ext_ack *extack) 3582 { 3583 struct ksz_device *dev = ds->priv; 3584 3585 if (!dev->dev_ops->vlan_filtering) 3586 return -EOPNOTSUPP; 3587 3588 return dev->dev_ops->vlan_filtering(dev, port, flag, extack); 3589 } 3590 3591 static int ksz_port_vlan_add(struct dsa_switch *ds, int port, 3592 const struct switchdev_obj_port_vlan *vlan, 3593 struct netlink_ext_ack *extack) 3594 { 3595 struct ksz_device *dev = ds->priv; 3596 3597 if (!dev->dev_ops->vlan_add) 3598 return -EOPNOTSUPP; 3599 3600 return dev->dev_ops->vlan_add(dev, port, vlan, extack); 3601 } 3602 3603 static int ksz_port_vlan_del(struct dsa_switch *ds, int port, 3604 const struct switchdev_obj_port_vlan *vlan) 3605 { 3606 struct ksz_device *dev = ds->priv; 3607 3608 if (!dev->dev_ops->vlan_del) 3609 return -EOPNOTSUPP; 3610 3611 return dev->dev_ops->vlan_del(dev, port, vlan); 3612 } 3613 3614 static int ksz_port_mirror_add(struct dsa_switch *ds, int port, 3615 struct dsa_mall_mirror_tc_entry *mirror, 3616 bool ingress, struct netlink_ext_ack *extack) 3617 { 3618 struct ksz_device *dev = ds->priv; 3619 3620 if (!dev->dev_ops->mirror_add) 3621 return -EOPNOTSUPP; 3622 3623 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack); 3624 } 3625 3626 static void ksz_port_mirror_del(struct dsa_switch *ds, int port, 3627 struct dsa_mall_mirror_tc_entry *mirror) 3628 { 3629 struct ksz_device *dev = ds->priv; 3630 3631 if (dev->dev_ops->mirror_del) 3632 dev->dev_ops->mirror_del(dev, port, mirror); 3633 } 3634 3635 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu) 3636 { 3637 struct ksz_device *dev = ds->priv; 3638 3639 if (!dev->dev_ops->change_mtu) 3640 return -EOPNOTSUPP; 3641 3642 return dev->dev_ops->change_mtu(dev, port, mtu); 3643 } 3644 3645 static int ksz_max_mtu(struct dsa_switch *ds, int port) 3646 { 3647 struct ksz_device *dev = ds->priv; 3648 3649 switch (dev->chip_id) { 3650 case KSZ8795_CHIP_ID: 3651 case KSZ8794_CHIP_ID: 3652 case KSZ8765_CHIP_ID: 3653 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3654 case KSZ8463_CHIP_ID: 3655 case KSZ88X3_CHIP_ID: 3656 case KSZ8864_CHIP_ID: 3657 case KSZ8895_CHIP_ID: 3658 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3659 case KSZ8563_CHIP_ID: 3660 case KSZ8567_CHIP_ID: 3661 case KSZ9477_CHIP_ID: 3662 case KSZ9563_CHIP_ID: 3663 case KSZ9567_CHIP_ID: 3664 case KSZ9893_CHIP_ID: 3665 case KSZ9896_CHIP_ID: 3666 case KSZ9897_CHIP_ID: 3667 case LAN9370_CHIP_ID: 3668 case LAN9371_CHIP_ID: 3669 case LAN9372_CHIP_ID: 3670 case LAN9373_CHIP_ID: 3671 case LAN9374_CHIP_ID: 3672 case LAN9646_CHIP_ID: 3673 return KSZ9477_MAX_FRAME_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN; 3674 } 3675 3676 return -EOPNOTSUPP; 3677 } 3678 3679 /** 3680 * ksz_support_eee - Determine Energy Efficient Ethernet (EEE) support for a 3681 * port 3682 * @ds: Pointer to the DSA switch structure 3683 * @port: Port number to check 3684 * 3685 * This function also documents devices where EEE was initially advertised but 3686 * later withdrawn due to reliability issues, as described in official errata 3687 * documents. These devices are explicitly listed to record known limitations, 3688 * even if there is no technical necessity for runtime checks. 3689 * 3690 * Returns: true if the internal PHY on the given port supports fully 3691 * operational EEE, false otherwise. 3692 */ 3693 static bool ksz_support_eee(struct dsa_switch *ds, int port) 3694 { 3695 struct ksz_device *dev = ds->priv; 3696 3697 if (!dev->info->internal_phy[port]) 3698 return false; 3699 3700 switch (dev->chip_id) { 3701 case KSZ8563_CHIP_ID: 3702 case KSZ9563_CHIP_ID: 3703 case KSZ9893_CHIP_ID: 3704 return true; 3705 case KSZ8567_CHIP_ID: 3706 /* KSZ8567R Errata DS80000752C Module 4 */ 3707 case KSZ8765_CHIP_ID: 3708 case KSZ8794_CHIP_ID: 3709 case KSZ8795_CHIP_ID: 3710 /* KSZ879x/KSZ877x/KSZ876x Errata DS80000687C Module 2 */ 3711 case KSZ9477_CHIP_ID: 3712 /* KSZ9477S Errata DS80000754A Module 4 */ 3713 case KSZ9567_CHIP_ID: 3714 /* KSZ9567S Errata DS80000756A Module 4 */ 3715 case KSZ9896_CHIP_ID: 3716 /* KSZ9896C Errata DS80000757A Module 3 */ 3717 case KSZ9897_CHIP_ID: 3718 case LAN9646_CHIP_ID: 3719 /* KSZ9897R Errata DS80000758C Module 4 */ 3720 /* Energy Efficient Ethernet (EEE) feature select must be 3721 * manually disabled 3722 * The EEE feature is enabled by default, but it is not fully 3723 * operational. It must be manually disabled through register 3724 * controls. If not disabled, the PHY ports can auto-negotiate 3725 * to enable EEE, and this feature can cause link drops when 3726 * linked to another device supporting EEE. 3727 * 3728 * The same item appears in the errata for all switches above. 3729 */ 3730 break; 3731 } 3732 3733 return false; 3734 } 3735 3736 static int ksz_set_mac_eee(struct dsa_switch *ds, int port, 3737 struct ethtool_keee *e) 3738 { 3739 struct ksz_device *dev = ds->priv; 3740 3741 if (!e->tx_lpi_enabled) { 3742 dev_err(dev->dev, "Disabling EEE Tx LPI is not supported\n"); 3743 return -EINVAL; 3744 } 3745 3746 if (e->tx_lpi_timer) { 3747 dev_err(dev->dev, "Setting EEE Tx LPI timer is not supported\n"); 3748 return -EINVAL; 3749 } 3750 3751 return 0; 3752 } 3753 3754 static void ksz_set_xmii(struct ksz_device *dev, int port, 3755 phy_interface_t interface) 3756 { 3757 const u8 *bitval = dev->info->xmii_ctrl1; 3758 struct ksz_port *p = &dev->ports[port]; 3759 const u16 *regs = dev->info->regs; 3760 u8 data8; 3761 3762 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3763 3764 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE | 3765 P_RGMII_ID_EG_ENABLE); 3766 3767 switch (interface) { 3768 case PHY_INTERFACE_MODE_MII: 3769 data8 |= bitval[P_MII_SEL]; 3770 break; 3771 case PHY_INTERFACE_MODE_RMII: 3772 data8 |= bitval[P_RMII_SEL]; 3773 break; 3774 case PHY_INTERFACE_MODE_GMII: 3775 data8 |= bitval[P_GMII_SEL]; 3776 break; 3777 case PHY_INTERFACE_MODE_RGMII: 3778 case PHY_INTERFACE_MODE_RGMII_ID: 3779 case PHY_INTERFACE_MODE_RGMII_TXID: 3780 case PHY_INTERFACE_MODE_RGMII_RXID: 3781 data8 |= bitval[P_RGMII_SEL]; 3782 /* On KSZ9893, disable RGMII in-band status support */ 3783 if (dev->chip_id == KSZ9893_CHIP_ID || 3784 dev->chip_id == KSZ8563_CHIP_ID || 3785 dev->chip_id == KSZ9563_CHIP_ID || 3786 is_lan937x(dev)) 3787 data8 &= ~P_MII_MAC_MODE; 3788 break; 3789 default: 3790 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n", 3791 phy_modes(interface), port); 3792 return; 3793 } 3794 3795 if (p->rgmii_tx_val) 3796 data8 |= P_RGMII_ID_EG_ENABLE; 3797 3798 if (p->rgmii_rx_val) 3799 data8 |= P_RGMII_ID_IG_ENABLE; 3800 3801 /* Write the updated value */ 3802 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3803 } 3804 3805 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit) 3806 { 3807 const u8 *bitval = dev->info->xmii_ctrl1; 3808 const u16 *regs = dev->info->regs; 3809 phy_interface_t interface; 3810 u8 data8; 3811 u8 val; 3812 3813 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3814 3815 val = FIELD_GET(P_MII_SEL_M, data8); 3816 3817 if (val == bitval[P_MII_SEL]) { 3818 if (gbit) 3819 interface = PHY_INTERFACE_MODE_GMII; 3820 else 3821 interface = PHY_INTERFACE_MODE_MII; 3822 } else if (val == bitval[P_RMII_SEL]) { 3823 interface = PHY_INTERFACE_MODE_RMII; 3824 } else { 3825 interface = PHY_INTERFACE_MODE_RGMII; 3826 if (data8 & P_RGMII_ID_EG_ENABLE) 3827 interface = PHY_INTERFACE_MODE_RGMII_TXID; 3828 if (data8 & P_RGMII_ID_IG_ENABLE) { 3829 interface = PHY_INTERFACE_MODE_RGMII_RXID; 3830 if (data8 & P_RGMII_ID_EG_ENABLE) 3831 interface = PHY_INTERFACE_MODE_RGMII_ID; 3832 } 3833 } 3834 3835 return interface; 3836 } 3837 3838 static void ksz88x3_phylink_mac_config(struct phylink_config *config, 3839 unsigned int mode, 3840 const struct phylink_link_state *state) 3841 { 3842 struct dsa_port *dp = dsa_phylink_to_port(config); 3843 struct ksz_device *dev = dp->ds->priv; 3844 3845 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN); 3846 } 3847 3848 static void ksz_phylink_mac_config(struct phylink_config *config, 3849 unsigned int mode, 3850 const struct phylink_link_state *state) 3851 { 3852 struct dsa_port *dp = dsa_phylink_to_port(config); 3853 struct ksz_device *dev = dp->ds->priv; 3854 int port = dp->index; 3855 3856 /* Internal PHYs */ 3857 if (dev->info->internal_phy[port]) 3858 return; 3859 3860 /* No need to configure XMII control register when using SGMII. */ 3861 if (ksz_is_sgmii_port(dev, port)) 3862 return; 3863 3864 if (phylink_autoneg_inband(mode)) { 3865 dev_err(dev->dev, "In-band AN not supported!\n"); 3866 return; 3867 } 3868 3869 ksz_set_xmii(dev, port, state->interface); 3870 3871 if (dev->dev_ops->setup_rgmii_delay) 3872 dev->dev_ops->setup_rgmii_delay(dev, port); 3873 } 3874 3875 bool ksz_get_gbit(struct ksz_device *dev, int port) 3876 { 3877 const u8 *bitval = dev->info->xmii_ctrl1; 3878 const u16 *regs = dev->info->regs; 3879 bool gbit = false; 3880 u8 data8; 3881 bool val; 3882 3883 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3884 3885 val = FIELD_GET(P_GMII_1GBIT_M, data8); 3886 3887 if (val == bitval[P_GMII_1GBIT]) 3888 gbit = true; 3889 3890 return gbit; 3891 } 3892 3893 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit) 3894 { 3895 const u8 *bitval = dev->info->xmii_ctrl1; 3896 const u16 *regs = dev->info->regs; 3897 u8 data8; 3898 3899 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8); 3900 3901 data8 &= ~P_GMII_1GBIT_M; 3902 3903 if (gbit) 3904 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]); 3905 else 3906 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]); 3907 3908 /* Write the updated value */ 3909 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8); 3910 } 3911 3912 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed) 3913 { 3914 const u8 *bitval = dev->info->xmii_ctrl0; 3915 const u16 *regs = dev->info->regs; 3916 u8 data8; 3917 3918 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8); 3919 3920 data8 &= ~P_MII_100MBIT_M; 3921 3922 if (speed == SPEED_100) 3923 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]); 3924 else 3925 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]); 3926 3927 /* Write the updated value */ 3928 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8); 3929 } 3930 3931 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed) 3932 { 3933 if (speed == SPEED_1000) 3934 ksz_set_gbit(dev, port, true); 3935 else 3936 ksz_set_gbit(dev, port, false); 3937 3938 if (speed == SPEED_100 || speed == SPEED_10) 3939 ksz_set_100_10mbit(dev, port, speed); 3940 } 3941 3942 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex, 3943 bool tx_pause, bool rx_pause) 3944 { 3945 const u8 *bitval = dev->info->xmii_ctrl0; 3946 const u32 *masks = dev->info->masks; 3947 const u16 *regs = dev->info->regs; 3948 u8 mask; 3949 u8 val; 3950 3951 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] | 3952 masks[P_MII_RX_FLOW_CTRL]; 3953 3954 if (duplex == DUPLEX_FULL) 3955 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]); 3956 else 3957 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]); 3958 3959 if (tx_pause) 3960 val |= masks[P_MII_TX_FLOW_CTRL]; 3961 3962 if (rx_pause) 3963 val |= masks[P_MII_RX_FLOW_CTRL]; 3964 3965 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val); 3966 } 3967 3968 static void ksz9477_phylink_mac_link_up(struct phylink_config *config, 3969 struct phy_device *phydev, 3970 unsigned int mode, 3971 phy_interface_t interface, 3972 int speed, int duplex, bool tx_pause, 3973 bool rx_pause) 3974 { 3975 struct dsa_port *dp = dsa_phylink_to_port(config); 3976 struct ksz_device *dev = dp->ds->priv; 3977 int port = dp->index; 3978 struct ksz_port *p; 3979 3980 p = &dev->ports[port]; 3981 3982 /* Internal PHYs */ 3983 if (dev->info->internal_phy[port]) 3984 return; 3985 3986 p->phydev.speed = speed; 3987 3988 ksz_port_set_xmii_speed(dev, port, speed); 3989 3990 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause); 3991 } 3992 3993 static int ksz_switch_detect(struct ksz_device *dev) 3994 { 3995 u8 id1, id2, id4; 3996 u16 id16; 3997 u32 id32; 3998 int ret; 3999 4000 /* read chip id */ 4001 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 4002 if (ret) 4003 return ret; 4004 4005 id1 = FIELD_GET(SW_FAMILY_ID_M, id16); 4006 id2 = FIELD_GET(SW_CHIP_ID_M, id16); 4007 4008 switch (id1) { 4009 case KSZ84_FAMILY_ID: 4010 dev->chip_id = KSZ8463_CHIP_ID; 4011 break; 4012 case KSZ87_FAMILY_ID: 4013 if (id2 == KSZ87_CHIP_ID_95) { 4014 u8 val; 4015 4016 dev->chip_id = KSZ8795_CHIP_ID; 4017 4018 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val); 4019 if (val & KSZ8_PORT_FIBER_MODE) 4020 dev->chip_id = KSZ8765_CHIP_ID; 4021 } else if (id2 == KSZ87_CHIP_ID_94) { 4022 dev->chip_id = KSZ8794_CHIP_ID; 4023 } else { 4024 return -ENODEV; 4025 } 4026 break; 4027 case KSZ88_FAMILY_ID: 4028 if (id2 == KSZ88_CHIP_ID_63) 4029 dev->chip_id = KSZ88X3_CHIP_ID; 4030 else 4031 return -ENODEV; 4032 break; 4033 case KSZ8895_FAMILY_ID: 4034 if (id2 == KSZ8895_CHIP_ID_95 || 4035 id2 == KSZ8895_CHIP_ID_95R) 4036 dev->chip_id = KSZ8895_CHIP_ID; 4037 else 4038 return -ENODEV; 4039 ret = ksz_read8(dev, REG_KSZ8864_CHIP_ID, &id4); 4040 if (ret) 4041 return ret; 4042 if (id4 & SW_KSZ8864) 4043 dev->chip_id = KSZ8864_CHIP_ID; 4044 break; 4045 default: 4046 ret = ksz_read32(dev, REG_CHIP_ID0, &id32); 4047 if (ret) 4048 return ret; 4049 4050 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32); 4051 id32 &= ~0xFF; 4052 4053 switch (id32) { 4054 case KSZ9477_CHIP_ID: 4055 case KSZ9896_CHIP_ID: 4056 case KSZ9897_CHIP_ID: 4057 case KSZ9567_CHIP_ID: 4058 case KSZ8567_CHIP_ID: 4059 case LAN9370_CHIP_ID: 4060 case LAN9371_CHIP_ID: 4061 case LAN9372_CHIP_ID: 4062 case LAN9373_CHIP_ID: 4063 case LAN9374_CHIP_ID: 4064 4065 /* LAN9646 does not have its own chip id. */ 4066 if (dev->chip_id != LAN9646_CHIP_ID) 4067 dev->chip_id = id32; 4068 break; 4069 case KSZ9893_CHIP_ID: 4070 ret = ksz_read8(dev, REG_CHIP_ID4, 4071 &id4); 4072 if (ret) 4073 return ret; 4074 4075 if (id4 == SKU_ID_KSZ8563) 4076 dev->chip_id = KSZ8563_CHIP_ID; 4077 else if (id4 == SKU_ID_KSZ9563) 4078 dev->chip_id = KSZ9563_CHIP_ID; 4079 else 4080 dev->chip_id = KSZ9893_CHIP_ID; 4081 4082 break; 4083 default: 4084 dev_err(dev->dev, 4085 "unsupported switch detected %x)\n", id32); 4086 return -ENODEV; 4087 } 4088 } 4089 return 0; 4090 } 4091 4092 static int ksz_cls_flower_add(struct dsa_switch *ds, int port, 4093 struct flow_cls_offload *cls, bool ingress) 4094 { 4095 struct ksz_device *dev = ds->priv; 4096 4097 switch (dev->chip_id) { 4098 case KSZ8563_CHIP_ID: 4099 case KSZ8567_CHIP_ID: 4100 case KSZ9477_CHIP_ID: 4101 case KSZ9563_CHIP_ID: 4102 case KSZ9567_CHIP_ID: 4103 case KSZ9893_CHIP_ID: 4104 case KSZ9896_CHIP_ID: 4105 case KSZ9897_CHIP_ID: 4106 case LAN9646_CHIP_ID: 4107 return ksz9477_cls_flower_add(ds, port, cls, ingress); 4108 } 4109 4110 return -EOPNOTSUPP; 4111 } 4112 4113 static int ksz_cls_flower_del(struct dsa_switch *ds, int port, 4114 struct flow_cls_offload *cls, bool ingress) 4115 { 4116 struct ksz_device *dev = ds->priv; 4117 4118 switch (dev->chip_id) { 4119 case KSZ8563_CHIP_ID: 4120 case KSZ8567_CHIP_ID: 4121 case KSZ9477_CHIP_ID: 4122 case KSZ9563_CHIP_ID: 4123 case KSZ9567_CHIP_ID: 4124 case KSZ9893_CHIP_ID: 4125 case KSZ9896_CHIP_ID: 4126 case KSZ9897_CHIP_ID: 4127 case LAN9646_CHIP_ID: 4128 return ksz9477_cls_flower_del(ds, port, cls, ingress); 4129 } 4130 4131 return -EOPNOTSUPP; 4132 } 4133 4134 /* Bandwidth is calculated by idle slope/transmission speed. Then the Bandwidth 4135 * is converted to Hex-decimal using the successive multiplication method. On 4136 * every step, integer part is taken and decimal part is carry forwarded. 4137 */ 4138 static int cinc_cal(s32 idle_slope, s32 send_slope, u32 *bw) 4139 { 4140 u32 cinc = 0; 4141 u32 txrate; 4142 u32 rate; 4143 u8 temp; 4144 u8 i; 4145 4146 txrate = idle_slope - send_slope; 4147 4148 if (!txrate) 4149 return -EINVAL; 4150 4151 rate = idle_slope; 4152 4153 /* 24 bit register */ 4154 for (i = 0; i < 6; i++) { 4155 rate = rate * 16; 4156 4157 temp = rate / txrate; 4158 4159 rate %= txrate; 4160 4161 cinc = ((cinc << 4) | temp); 4162 } 4163 4164 *bw = cinc; 4165 4166 return 0; 4167 } 4168 4169 static int ksz_setup_tc_mode(struct ksz_device *dev, int port, u8 scheduler, 4170 u8 shaper) 4171 { 4172 return ksz_pwrite8(dev, port, REG_PORT_MTI_QUEUE_CTRL_0, 4173 FIELD_PREP(MTI_SCHEDULE_MODE_M, scheduler) | 4174 FIELD_PREP(MTI_SHAPING_M, shaper)); 4175 } 4176 4177 static int ksz_setup_tc_cbs(struct dsa_switch *ds, int port, 4178 struct tc_cbs_qopt_offload *qopt) 4179 { 4180 struct ksz_device *dev = ds->priv; 4181 int ret; 4182 u32 bw; 4183 4184 if (!dev->info->tc_cbs_supported) 4185 return -EOPNOTSUPP; 4186 4187 if (qopt->queue > dev->info->num_tx_queues) 4188 return -EINVAL; 4189 4190 /* Queue Selection */ 4191 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, qopt->queue); 4192 if (ret) 4193 return ret; 4194 4195 if (!qopt->enable) 4196 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 4197 MTI_SHAPING_OFF); 4198 4199 /* High Credit */ 4200 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_HI_WATER_MARK, 4201 qopt->hicredit); 4202 if (ret) 4203 return ret; 4204 4205 /* Low Credit */ 4206 ret = ksz_pwrite16(dev, port, REG_PORT_MTI_LO_WATER_MARK, 4207 qopt->locredit); 4208 if (ret) 4209 return ret; 4210 4211 /* Credit Increment Register */ 4212 ret = cinc_cal(qopt->idleslope, qopt->sendslope, &bw); 4213 if (ret) 4214 return ret; 4215 4216 if (dev->dev_ops->tc_cbs_set_cinc) { 4217 ret = dev->dev_ops->tc_cbs_set_cinc(dev, port, bw); 4218 if (ret) 4219 return ret; 4220 } 4221 4222 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 4223 MTI_SHAPING_SRP); 4224 } 4225 4226 static int ksz_disable_egress_rate_limit(struct ksz_device *dev, int port) 4227 { 4228 int queue, ret; 4229 4230 /* Configuration will not take effect until the last Port Queue X 4231 * Egress Limit Control Register is written. 4232 */ 4233 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 4234 ret = ksz_pwrite8(dev, port, KSZ9477_REG_PORT_OUT_RATE_0 + queue, 4235 KSZ9477_OUT_RATE_NO_LIMIT); 4236 if (ret) 4237 return ret; 4238 } 4239 4240 return 0; 4241 } 4242 4243 static int ksz_ets_band_to_queue(struct tc_ets_qopt_offload_replace_params *p, 4244 int band) 4245 { 4246 /* Compared to queues, bands prioritize packets differently. In strict 4247 * priority mode, the lowest priority is assigned to Queue 0 while the 4248 * highest priority is given to Band 0. 4249 */ 4250 return p->bands - 1 - band; 4251 } 4252 4253 static u8 ksz8463_tc_ctrl(int port, int queue) 4254 { 4255 u8 reg; 4256 4257 reg = 0xC8 + port * 4; 4258 reg += ((3 - queue) / 2) * 2; 4259 reg++; 4260 reg -= (queue & 1); 4261 return reg; 4262 } 4263 4264 /** 4265 * ksz88x3_tc_ets_add - Configure ETS (Enhanced Transmission Selection) 4266 * for a port on KSZ88x3 switch 4267 * @dev: Pointer to the KSZ switch device structure 4268 * @port: Port number to configure 4269 * @p: Pointer to offload replace parameters describing ETS bands and mapping 4270 * 4271 * The KSZ88x3 supports two scheduling modes: Strict Priority and 4272 * Weighted Fair Queuing (WFQ). Both modes have fixed behavior: 4273 * - No configurable queue-to-priority mapping 4274 * - No weight adjustment in WFQ mode 4275 * 4276 * This function configures the switch to use strict priority mode by 4277 * clearing the WFQ enable bit for all queues associated with ETS bands. 4278 * If strict priority is not explicitly requested, the switch will default 4279 * to WFQ mode. 4280 * 4281 * Return: 0 on success, or a negative error code on failure 4282 */ 4283 static int ksz88x3_tc_ets_add(struct ksz_device *dev, int port, 4284 struct tc_ets_qopt_offload_replace_params *p) 4285 { 4286 int ret, band; 4287 4288 /* Only strict priority mode is supported for now. 4289 * WFQ is implicitly enabled when strict mode is disabled. 4290 */ 4291 for (band = 0; band < p->bands; band++) { 4292 int queue = ksz_ets_band_to_queue(p, band); 4293 u8 reg; 4294 4295 /* Calculate TXQ Split Control register address for this 4296 * port/queue 4297 */ 4298 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue); 4299 if (ksz_is_ksz8463(dev)) 4300 reg = ksz8463_tc_ctrl(port, queue); 4301 4302 /* Clear WFQ enable bit to select strict priority scheduling */ 4303 ret = ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE, 0); 4304 if (ret) 4305 return ret; 4306 } 4307 4308 return 0; 4309 } 4310 4311 /** 4312 * ksz88x3_tc_ets_del - Reset ETS (Enhanced Transmission Selection) config 4313 * for a port on KSZ88x3 switch 4314 * @dev: Pointer to the KSZ switch device structure 4315 * @port: Port number to reset 4316 * 4317 * The KSZ88x3 supports only fixed scheduling modes: Strict Priority or 4318 * Weighted Fair Queuing (WFQ), with no reconfiguration of weights or 4319 * queue mapping. This function resets the port’s scheduling mode to 4320 * the default, which is WFQ, by enabling the WFQ bit for all queues. 4321 * 4322 * Return: 0 on success, or a negative error code on failure 4323 */ 4324 static int ksz88x3_tc_ets_del(struct ksz_device *dev, int port) 4325 { 4326 int ret, queue; 4327 4328 /* Iterate over all transmit queues for this port */ 4329 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 4330 u8 reg; 4331 4332 /* Calculate TXQ Split Control register address for this 4333 * port/queue 4334 */ 4335 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue); 4336 if (ksz_is_ksz8463(dev)) 4337 reg = ksz8463_tc_ctrl(port, queue); 4338 4339 /* Set WFQ enable bit to revert back to default scheduling 4340 * mode 4341 */ 4342 ret = ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE, 4343 KSZ8873_TXQ_WFQ_ENABLE); 4344 if (ret) 4345 return ret; 4346 } 4347 4348 return 0; 4349 } 4350 4351 static int ksz_queue_set_strict(struct ksz_device *dev, int port, int queue) 4352 { 4353 int ret; 4354 4355 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 4356 if (ret) 4357 return ret; 4358 4359 return ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_STRICT_PRIO, 4360 MTI_SHAPING_OFF); 4361 } 4362 4363 static int ksz_queue_set_wrr(struct ksz_device *dev, int port, int queue, 4364 int weight) 4365 { 4366 int ret; 4367 4368 ret = ksz_pwrite32(dev, port, REG_PORT_MTI_QUEUE_INDEX__4, queue); 4369 if (ret) 4370 return ret; 4371 4372 ret = ksz_setup_tc_mode(dev, port, MTI_SCHEDULE_WRR, 4373 MTI_SHAPING_OFF); 4374 if (ret) 4375 return ret; 4376 4377 return ksz_pwrite8(dev, port, KSZ9477_PORT_MTI_QUEUE_CTRL_1, weight); 4378 } 4379 4380 static int ksz_tc_ets_add(struct ksz_device *dev, int port, 4381 struct tc_ets_qopt_offload_replace_params *p) 4382 { 4383 int ret, band, tc_prio; 4384 u32 queue_map = 0; 4385 4386 /* In order to ensure proper prioritization, it is necessary to set the 4387 * rate limit for the related queue to zero. Otherwise strict priority 4388 * or WRR mode will not work. This is a hardware limitation. 4389 */ 4390 ret = ksz_disable_egress_rate_limit(dev, port); 4391 if (ret) 4392 return ret; 4393 4394 /* Configure queue scheduling mode for all bands. Currently only strict 4395 * prio mode is supported. 4396 */ 4397 for (band = 0; band < p->bands; band++) { 4398 int queue = ksz_ets_band_to_queue(p, band); 4399 4400 ret = ksz_queue_set_strict(dev, port, queue); 4401 if (ret) 4402 return ret; 4403 } 4404 4405 /* Configure the mapping between traffic classes and queues. Note: 4406 * priomap variable support 16 traffic classes, but the chip can handle 4407 * only 8 classes. 4408 */ 4409 for (tc_prio = 0; tc_prio < ARRAY_SIZE(p->priomap); tc_prio++) { 4410 int queue; 4411 4412 if (tc_prio >= dev->info->num_ipms) 4413 break; 4414 4415 queue = ksz_ets_band_to_queue(p, p->priomap[tc_prio]); 4416 queue_map |= queue << (tc_prio * KSZ9477_PORT_TC_MAP_S); 4417 } 4418 4419 return ksz_pwrite32(dev, port, KSZ9477_PORT_MRI_TC_MAP__4, queue_map); 4420 } 4421 4422 static int ksz_tc_ets_del(struct ksz_device *dev, int port) 4423 { 4424 int ret, queue; 4425 4426 /* To restore the default chip configuration, set all queues to use the 4427 * WRR scheduler with a weight of 1. 4428 */ 4429 for (queue = 0; queue < dev->info->num_tx_queues; queue++) { 4430 ret = ksz_queue_set_wrr(dev, port, queue, 4431 KSZ9477_DEFAULT_WRR_WEIGHT); 4432 4433 if (ret) 4434 return ret; 4435 } 4436 4437 /* Revert the queue mapping for TC-priority to its default setting on 4438 * the chip. 4439 */ 4440 return ksz9477_set_default_prio_queue_mapping(dev, port); 4441 } 4442 4443 static int ksz_tc_ets_validate(struct ksz_device *dev, int port, 4444 struct tc_ets_qopt_offload_replace_params *p) 4445 { 4446 int band; 4447 4448 /* Since it is not feasible to share one port among multiple qdisc, 4449 * the user must configure all available queues appropriately. 4450 */ 4451 if (p->bands != dev->info->num_tx_queues) { 4452 dev_err(dev->dev, "Not supported amount of bands. It should be %d\n", 4453 dev->info->num_tx_queues); 4454 return -EOPNOTSUPP; 4455 } 4456 4457 for (band = 0; band < p->bands; ++band) { 4458 /* The KSZ switches utilize a weighted round robin configuration 4459 * where a certain number of packets can be transmitted from a 4460 * queue before the next queue is serviced. For more information 4461 * on this, refer to section 5.2.8.4 of the KSZ8565R 4462 * documentation on the Port Transmit Queue Control 1 Register. 4463 * However, the current ETS Qdisc implementation (as of February 4464 * 2023) assigns a weight to each queue based on the number of 4465 * bytes or extrapolated bandwidth in percentages. Since this 4466 * differs from the KSZ switches' method and we don't want to 4467 * fake support by converting bytes to packets, it is better to 4468 * return an error instead. 4469 */ 4470 if (p->quanta[band]) { 4471 dev_err(dev->dev, "Quanta/weights configuration is not supported.\n"); 4472 return -EOPNOTSUPP; 4473 } 4474 } 4475 4476 return 0; 4477 } 4478 4479 static int ksz_tc_setup_qdisc_ets(struct dsa_switch *ds, int port, 4480 struct tc_ets_qopt_offload *qopt) 4481 { 4482 struct ksz_device *dev = ds->priv; 4483 int ret; 4484 4485 if (is_ksz8(dev) && !(ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev))) 4486 return -EOPNOTSUPP; 4487 4488 if (qopt->parent != TC_H_ROOT) { 4489 dev_err(dev->dev, "Parent should be \"root\"\n"); 4490 return -EOPNOTSUPP; 4491 } 4492 4493 switch (qopt->command) { 4494 case TC_ETS_REPLACE: 4495 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params); 4496 if (ret) 4497 return ret; 4498 4499 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 4500 return ksz88x3_tc_ets_add(dev, port, 4501 &qopt->replace_params); 4502 else 4503 return ksz_tc_ets_add(dev, port, &qopt->replace_params); 4504 case TC_ETS_DESTROY: 4505 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) 4506 return ksz88x3_tc_ets_del(dev, port); 4507 else 4508 return ksz_tc_ets_del(dev, port); 4509 case TC_ETS_STATS: 4510 case TC_ETS_GRAFT: 4511 return -EOPNOTSUPP; 4512 } 4513 4514 return -EOPNOTSUPP; 4515 } 4516 4517 static int ksz_setup_tc(struct dsa_switch *ds, int port, 4518 enum tc_setup_type type, void *type_data) 4519 { 4520 switch (type) { 4521 case TC_SETUP_QDISC_CBS: 4522 return ksz_setup_tc_cbs(ds, port, type_data); 4523 case TC_SETUP_QDISC_ETS: 4524 return ksz_tc_setup_qdisc_ets(ds, port, type_data); 4525 default: 4526 return -EOPNOTSUPP; 4527 } 4528 } 4529 4530 /** 4531 * ksz_handle_wake_reason - Handle wake reason on a specified port. 4532 * @dev: The device structure. 4533 * @port: The port number. 4534 * 4535 * This function reads the PME (Power Management Event) status register of a 4536 * specified port to determine the wake reason. If there is no wake event, it 4537 * returns early. Otherwise, it logs the wake reason which could be due to a 4538 * "Magic Packet", "Link Up", or "Energy Detect" event. The PME status register 4539 * is then cleared to acknowledge the handling of the wake event. 4540 * 4541 * Return: 0 on success, or an error code on failure. 4542 */ 4543 int ksz_handle_wake_reason(struct ksz_device *dev, int port) 4544 { 4545 const struct ksz_dev_ops *ops = dev->dev_ops; 4546 const u16 *regs = dev->info->regs; 4547 u8 pme_status; 4548 int ret; 4549 4550 ret = ops->pme_pread8(dev, port, regs[REG_PORT_PME_STATUS], 4551 &pme_status); 4552 if (ret) 4553 return ret; 4554 4555 if (!pme_status) 4556 return 0; 4557 4558 dev_dbg(dev->dev, "Wake event on port %d due to:%s%s%s\n", port, 4559 pme_status & PME_WOL_MAGICPKT ? " \"Magic Packet\"" : "", 4560 pme_status & PME_WOL_LINKUP ? " \"Link Up\"" : "", 4561 pme_status & PME_WOL_ENERGY ? " \"Energy detect\"" : ""); 4562 4563 return ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_STATUS], 4564 pme_status); 4565 } 4566 4567 /** 4568 * ksz_get_wol - Get Wake-on-LAN settings for a specified port. 4569 * @ds: The dsa_switch structure. 4570 * @port: The port number. 4571 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 4572 * 4573 * This function checks the device PME wakeup_source flag and chip_id. 4574 * If enabled and supported, it sets the supported and active WoL 4575 * flags. 4576 */ 4577 static void ksz_get_wol(struct dsa_switch *ds, int port, 4578 struct ethtool_wolinfo *wol) 4579 { 4580 struct ksz_device *dev = ds->priv; 4581 const u16 *regs = dev->info->regs; 4582 u8 pme_ctrl; 4583 int ret; 4584 4585 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4586 return; 4587 4588 if (!dev->wakeup_source) 4589 return; 4590 4591 wol->supported = WAKE_PHY; 4592 4593 /* Check if the current MAC address on this port can be set 4594 * as global for WAKE_MAGIC support. The result may vary 4595 * dynamically based on other ports configurations. 4596 */ 4597 if (ksz_is_port_mac_global_usable(dev->ds, port)) 4598 wol->supported |= WAKE_MAGIC; 4599 4600 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 4601 &pme_ctrl); 4602 if (ret) 4603 return; 4604 4605 if (pme_ctrl & PME_WOL_MAGICPKT) 4606 wol->wolopts |= WAKE_MAGIC; 4607 if (pme_ctrl & (PME_WOL_LINKUP | PME_WOL_ENERGY)) 4608 wol->wolopts |= WAKE_PHY; 4609 } 4610 4611 /** 4612 * ksz_set_wol - Set Wake-on-LAN settings for a specified port. 4613 * @ds: The dsa_switch structure. 4614 * @port: The port number. 4615 * @wol: Pointer to ethtool Wake-on-LAN settings structure. 4616 * 4617 * This function configures Wake-on-LAN (WoL) settings for a specified 4618 * port. It validates the provided WoL options, checks if PME is 4619 * enabled and supported, clears any previous wake reasons, and sets 4620 * the Magic Packet flag in the port's PME control register if 4621 * specified. 4622 * 4623 * Return: 0 on success, or other error codes on failure. 4624 */ 4625 static int ksz_set_wol(struct dsa_switch *ds, int port, 4626 struct ethtool_wolinfo *wol) 4627 { 4628 u8 pme_ctrl = 0, pme_ctrl_old = 0; 4629 struct ksz_device *dev = ds->priv; 4630 const u16 *regs = dev->info->regs; 4631 bool magic_switched_off; 4632 bool magic_switched_on; 4633 int ret; 4634 4635 if (wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC)) 4636 return -EINVAL; 4637 4638 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4639 return -EOPNOTSUPP; 4640 4641 if (!dev->wakeup_source) 4642 return -EOPNOTSUPP; 4643 4644 ret = ksz_handle_wake_reason(dev, port); 4645 if (ret) 4646 return ret; 4647 4648 if (wol->wolopts & WAKE_MAGIC) 4649 pme_ctrl |= PME_WOL_MAGICPKT; 4650 if (wol->wolopts & WAKE_PHY) 4651 pme_ctrl |= PME_WOL_LINKUP | PME_WOL_ENERGY; 4652 4653 ret = dev->dev_ops->pme_pread8(dev, port, regs[REG_PORT_PME_CTRL], 4654 &pme_ctrl_old); 4655 if (ret) 4656 return ret; 4657 4658 if (pme_ctrl_old == pme_ctrl) 4659 return 0; 4660 4661 magic_switched_off = (pme_ctrl_old & PME_WOL_MAGICPKT) && 4662 !(pme_ctrl & PME_WOL_MAGICPKT); 4663 magic_switched_on = !(pme_ctrl_old & PME_WOL_MAGICPKT) && 4664 (pme_ctrl & PME_WOL_MAGICPKT); 4665 4666 /* To keep reference count of MAC address, we should do this 4667 * operation only on change of WOL settings. 4668 */ 4669 if (magic_switched_on) { 4670 ret = ksz_switch_macaddr_get(dev->ds, port, NULL); 4671 if (ret) 4672 return ret; 4673 } else if (magic_switched_off) { 4674 ksz_switch_macaddr_put(dev->ds); 4675 } 4676 4677 ret = dev->dev_ops->pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 4678 pme_ctrl); 4679 if (ret) { 4680 if (magic_switched_on) 4681 ksz_switch_macaddr_put(dev->ds); 4682 return ret; 4683 } 4684 4685 return 0; 4686 } 4687 4688 /** 4689 * ksz_wol_pre_shutdown - Prepares the switch device for shutdown while 4690 * considering Wake-on-LAN (WoL) settings. 4691 * @dev: The switch device structure. 4692 * @wol_enabled: Pointer to a boolean which will be set to true if WoL is 4693 * enabled on any port. 4694 * 4695 * This function prepares the switch device for a safe shutdown while taking 4696 * into account the Wake-on-LAN (WoL) settings on the user ports. It updates 4697 * the wol_enabled flag accordingly to reflect whether WoL is active on any 4698 * port. 4699 */ 4700 static void ksz_wol_pre_shutdown(struct ksz_device *dev, bool *wol_enabled) 4701 { 4702 const struct ksz_dev_ops *ops = dev->dev_ops; 4703 const u16 *regs = dev->info->regs; 4704 u8 pme_pin_en = PME_ENABLE; 4705 struct dsa_port *dp; 4706 int ret; 4707 4708 *wol_enabled = false; 4709 4710 if (!is_ksz9477(dev) && !ksz_is_ksz87xx(dev)) 4711 return; 4712 4713 if (!dev->wakeup_source) 4714 return; 4715 4716 dsa_switch_for_each_user_port(dp, dev->ds) { 4717 u8 pme_ctrl = 0; 4718 4719 ret = ops->pme_pread8(dev, dp->index, 4720 regs[REG_PORT_PME_CTRL], &pme_ctrl); 4721 if (!ret && pme_ctrl) 4722 *wol_enabled = true; 4723 4724 /* make sure there are no pending wake events which would 4725 * prevent the device from going to sleep/shutdown. 4726 */ 4727 ksz_handle_wake_reason(dev, dp->index); 4728 } 4729 4730 /* Now we are save to enable PME pin. */ 4731 if (*wol_enabled) { 4732 if (dev->pme_active_high) 4733 pme_pin_en |= PME_POLARITY; 4734 ops->pme_write8(dev, regs[REG_SW_PME_CTRL], pme_pin_en); 4735 if (ksz_is_ksz87xx(dev)) 4736 ksz_write8(dev, KSZ87XX_REG_INT_EN, KSZ87XX_INT_PME_MASK); 4737 } 4738 } 4739 4740 static int ksz_port_set_mac_address(struct dsa_switch *ds, int port, 4741 const unsigned char *addr) 4742 { 4743 struct dsa_port *dp = dsa_to_port(ds, port); 4744 struct ethtool_wolinfo wol; 4745 4746 if (dp->hsr_dev) { 4747 dev_err(ds->dev, 4748 "Cannot change MAC address on port %d with active HSR offload\n", 4749 port); 4750 return -EBUSY; 4751 } 4752 4753 /* Need to initialize variable as the code to fill in settings may 4754 * not be executed. 4755 */ 4756 wol.wolopts = 0; 4757 4758 ksz_get_wol(ds, dp->index, &wol); 4759 if (wol.wolopts & WAKE_MAGIC) { 4760 dev_err(ds->dev, 4761 "Cannot change MAC address on port %d with active Wake on Magic Packet\n", 4762 port); 4763 return -EBUSY; 4764 } 4765 4766 return 0; 4767 } 4768 4769 /** 4770 * ksz_is_port_mac_global_usable - Check if the MAC address on a given port 4771 * can be used as a global address. 4772 * @ds: Pointer to the DSA switch structure. 4773 * @port: The port number on which the MAC address is to be checked. 4774 * 4775 * This function examines the MAC address set on the specified port and 4776 * determines if it can be used as a global address for the switch. 4777 * 4778 * Return: true if the port's MAC address can be used as a global address, false 4779 * otherwise. 4780 */ 4781 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port) 4782 { 4783 struct net_device *user = dsa_to_port(ds, port)->user; 4784 const unsigned char *addr = user->dev_addr; 4785 struct ksz_switch_macaddr *switch_macaddr; 4786 struct ksz_device *dev = ds->priv; 4787 4788 ASSERT_RTNL(); 4789 4790 switch_macaddr = dev->switch_macaddr; 4791 if (switch_macaddr && !ether_addr_equal(switch_macaddr->addr, addr)) 4792 return false; 4793 4794 return true; 4795 } 4796 4797 /** 4798 * ksz_switch_macaddr_get - Program the switch's MAC address register. 4799 * @ds: DSA switch instance. 4800 * @port: Port number. 4801 * @extack: Netlink extended acknowledgment. 4802 * 4803 * This function programs the switch's MAC address register with the MAC address 4804 * of the requesting user port. This single address is used by the switch for 4805 * multiple features like HSR self-address filtering and WoL. Other user ports 4806 * can share ownership of this address as long as their MAC address is the same. 4807 * The MAC addresses of user ports must not change while they have ownership of 4808 * the switch MAC address. 4809 * 4810 * Return: 0 on success, or other error codes on failure. 4811 */ 4812 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 4813 struct netlink_ext_ack *extack) 4814 { 4815 struct net_device *user = dsa_to_port(ds, port)->user; 4816 const unsigned char *addr = user->dev_addr; 4817 struct ksz_switch_macaddr *switch_macaddr; 4818 struct ksz_device *dev = ds->priv; 4819 const u16 *regs = dev->info->regs; 4820 int i, ret; 4821 4822 /* Make sure concurrent MAC address changes are blocked */ 4823 ASSERT_RTNL(); 4824 4825 switch_macaddr = dev->switch_macaddr; 4826 if (switch_macaddr) { 4827 if (!ether_addr_equal(switch_macaddr->addr, addr)) { 4828 NL_SET_ERR_MSG_FMT_MOD(extack, 4829 "Switch already configured for MAC address %pM", 4830 switch_macaddr->addr); 4831 return -EBUSY; 4832 } 4833 4834 refcount_inc(&switch_macaddr->refcount); 4835 return 0; 4836 } 4837 4838 switch_macaddr = kzalloc(sizeof(*switch_macaddr), GFP_KERNEL); 4839 if (!switch_macaddr) 4840 return -ENOMEM; 4841 4842 ether_addr_copy(switch_macaddr->addr, addr); 4843 refcount_set(&switch_macaddr->refcount, 1); 4844 dev->switch_macaddr = switch_macaddr; 4845 4846 /* Program the switch MAC address to hardware */ 4847 for (i = 0; i < ETH_ALEN; i++) { 4848 if (ksz_is_ksz8463(dev)) { 4849 u16 addr16 = ((u16)addr[i] << 8) | addr[i + 1]; 4850 4851 ret = ksz_write16(dev, regs[REG_SW_MAC_ADDR] + i, 4852 addr16); 4853 i++; 4854 } else { 4855 ret = ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 4856 addr[i]); 4857 } 4858 if (ret) 4859 goto macaddr_drop; 4860 } 4861 4862 return 0; 4863 4864 macaddr_drop: 4865 dev->switch_macaddr = NULL; 4866 refcount_set(&switch_macaddr->refcount, 0); 4867 kfree(switch_macaddr); 4868 4869 return ret; 4870 } 4871 4872 void ksz_switch_macaddr_put(struct dsa_switch *ds) 4873 { 4874 struct ksz_switch_macaddr *switch_macaddr; 4875 struct ksz_device *dev = ds->priv; 4876 const u16 *regs = dev->info->regs; 4877 int i; 4878 4879 /* Make sure concurrent MAC address changes are blocked */ 4880 ASSERT_RTNL(); 4881 4882 switch_macaddr = dev->switch_macaddr; 4883 if (!refcount_dec_and_test(&switch_macaddr->refcount)) 4884 return; 4885 4886 for (i = 0; i < ETH_ALEN; i++) 4887 ksz_write8(dev, regs[REG_SW_MAC_ADDR] + i, 0); 4888 4889 dev->switch_macaddr = NULL; 4890 kfree(switch_macaddr); 4891 } 4892 4893 static int ksz_hsr_join(struct dsa_switch *ds, int port, struct net_device *hsr, 4894 struct netlink_ext_ack *extack) 4895 { 4896 struct ksz_device *dev = ds->priv; 4897 enum hsr_version ver; 4898 int ret; 4899 4900 ret = hsr_get_version(hsr, &ver); 4901 if (ret) 4902 return ret; 4903 4904 if (dev->chip_id != KSZ9477_CHIP_ID) { 4905 NL_SET_ERR_MSG_MOD(extack, "Chip does not support HSR offload"); 4906 return -EOPNOTSUPP; 4907 } 4908 4909 /* KSZ9477 can support HW offloading of only 1 HSR device */ 4910 if (dev->hsr_dev && hsr != dev->hsr_dev) { 4911 NL_SET_ERR_MSG_MOD(extack, "Offload supported for a single HSR"); 4912 return -EOPNOTSUPP; 4913 } 4914 4915 /* KSZ9477 only supports HSR v0 and v1 */ 4916 if (!(ver == HSR_V0 || ver == HSR_V1)) { 4917 NL_SET_ERR_MSG_MOD(extack, "Only HSR v0 and v1 supported"); 4918 return -EOPNOTSUPP; 4919 } 4920 4921 /* KSZ9477 can only perform HSR offloading for up to two ports */ 4922 if (hweight8(dev->hsr_ports) >= 2) { 4923 NL_SET_ERR_MSG_MOD(extack, 4924 "Cannot offload more than two ports - using software HSR"); 4925 return -EOPNOTSUPP; 4926 } 4927 4928 /* Self MAC address filtering, to avoid frames traversing 4929 * the HSR ring more than once. 4930 */ 4931 ret = ksz_switch_macaddr_get(ds, port, extack); 4932 if (ret) 4933 return ret; 4934 4935 ksz9477_hsr_join(ds, port, hsr); 4936 dev->hsr_dev = hsr; 4937 dev->hsr_ports |= BIT(port); 4938 4939 return 0; 4940 } 4941 4942 static int ksz_hsr_leave(struct dsa_switch *ds, int port, 4943 struct net_device *hsr) 4944 { 4945 struct ksz_device *dev = ds->priv; 4946 4947 WARN_ON(dev->chip_id != KSZ9477_CHIP_ID); 4948 4949 ksz9477_hsr_leave(ds, port, hsr); 4950 dev->hsr_ports &= ~BIT(port); 4951 if (!dev->hsr_ports) 4952 dev->hsr_dev = NULL; 4953 4954 ksz_switch_macaddr_put(ds); 4955 4956 return 0; 4957 } 4958 4959 static int ksz_suspend(struct dsa_switch *ds) 4960 { 4961 struct ksz_device *dev = ds->priv; 4962 4963 cancel_delayed_work_sync(&dev->mib_read); 4964 return 0; 4965 } 4966 4967 static int ksz_resume(struct dsa_switch *ds) 4968 { 4969 struct ksz_device *dev = ds->priv; 4970 4971 if (dev->mib_read_interval) 4972 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval); 4973 return 0; 4974 } 4975 4976 static const struct dsa_switch_ops ksz_switch_ops = { 4977 .get_tag_protocol = ksz_get_tag_protocol, 4978 .connect_tag_protocol = ksz_connect_tag_protocol, 4979 .get_phy_flags = ksz_get_phy_flags, 4980 .setup = ksz_setup, 4981 .teardown = ksz_teardown, 4982 .phy_read = ksz_phy_read16, 4983 .phy_write = ksz_phy_write16, 4984 .phylink_get_caps = ksz_phylink_get_caps, 4985 .port_setup = ksz_port_setup, 4986 .set_ageing_time = ksz_set_ageing_time, 4987 .get_strings = ksz_get_strings, 4988 .get_ethtool_stats = ksz_get_ethtool_stats, 4989 .get_sset_count = ksz_sset_count, 4990 .port_bridge_join = ksz_port_bridge_join, 4991 .port_bridge_leave = ksz_port_bridge_leave, 4992 .port_hsr_join = ksz_hsr_join, 4993 .port_hsr_leave = ksz_hsr_leave, 4994 .port_set_mac_address = ksz_port_set_mac_address, 4995 .port_stp_state_set = ksz_port_stp_state_set, 4996 .port_teardown = ksz_port_teardown, 4997 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 4998 .port_bridge_flags = ksz_port_bridge_flags, 4999 .port_fast_age = ksz_port_fast_age, 5000 .port_vlan_filtering = ksz_port_vlan_filtering, 5001 .port_vlan_add = ksz_port_vlan_add, 5002 .port_vlan_del = ksz_port_vlan_del, 5003 .port_fdb_dump = ksz_port_fdb_dump, 5004 .port_fdb_add = ksz_port_fdb_add, 5005 .port_fdb_del = ksz_port_fdb_del, 5006 .port_mdb_add = ksz_port_mdb_add, 5007 .port_mdb_del = ksz_port_mdb_del, 5008 .port_mirror_add = ksz_port_mirror_add, 5009 .port_mirror_del = ksz_port_mirror_del, 5010 .get_stats64 = ksz_get_stats64, 5011 .get_pause_stats = ksz_get_pause_stats, 5012 .port_change_mtu = ksz_change_mtu, 5013 .port_max_mtu = ksz_max_mtu, 5014 .get_wol = ksz_get_wol, 5015 .set_wol = ksz_set_wol, 5016 .suspend = ksz_suspend, 5017 .resume = ksz_resume, 5018 .get_ts_info = ksz_get_ts_info, 5019 .port_hwtstamp_get = ksz_hwtstamp_get, 5020 .port_hwtstamp_set = ksz_hwtstamp_set, 5021 .port_txtstamp = ksz_port_txtstamp, 5022 .port_rxtstamp = ksz_port_rxtstamp, 5023 .cls_flower_add = ksz_cls_flower_add, 5024 .cls_flower_del = ksz_cls_flower_del, 5025 .port_setup_tc = ksz_setup_tc, 5026 .support_eee = ksz_support_eee, 5027 .set_mac_eee = ksz_set_mac_eee, 5028 .port_get_default_prio = ksz_port_get_default_prio, 5029 .port_set_default_prio = ksz_port_set_default_prio, 5030 .port_get_dscp_prio = ksz_port_get_dscp_prio, 5031 .port_add_dscp_prio = ksz_port_add_dscp_prio, 5032 .port_del_dscp_prio = ksz_port_del_dscp_prio, 5033 .port_get_apptrust = ksz_port_get_apptrust, 5034 .port_set_apptrust = ksz_port_set_apptrust, 5035 }; 5036 5037 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv) 5038 { 5039 struct dsa_switch *ds; 5040 struct ksz_device *swdev; 5041 5042 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL); 5043 if (!ds) 5044 return NULL; 5045 5046 ds->dev = base; 5047 ds->num_ports = DSA_MAX_PORTS; 5048 ds->ops = &ksz_switch_ops; 5049 5050 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL); 5051 if (!swdev) 5052 return NULL; 5053 5054 ds->priv = swdev; 5055 swdev->dev = base; 5056 5057 swdev->ds = ds; 5058 swdev->priv = priv; 5059 5060 return swdev; 5061 } 5062 EXPORT_SYMBOL(ksz_switch_alloc); 5063 5064 /** 5065 * ksz_switch_shutdown - Shutdown routine for the switch device. 5066 * @dev: The switch device structure. 5067 * 5068 * This function is responsible for initiating a shutdown sequence for the 5069 * switch device. It invokes the reset operation defined in the device 5070 * operations, if available, to reset the switch. Subsequently, it calls the 5071 * DSA framework's shutdown function to ensure a proper shutdown of the DSA 5072 * switch. 5073 */ 5074 void ksz_switch_shutdown(struct ksz_device *dev) 5075 { 5076 bool wol_enabled = false; 5077 5078 ksz_wol_pre_shutdown(dev, &wol_enabled); 5079 5080 if (dev->dev_ops->reset && !wol_enabled) 5081 dev->dev_ops->reset(dev); 5082 5083 dsa_switch_shutdown(dev->ds); 5084 } 5085 EXPORT_SYMBOL(ksz_switch_shutdown); 5086 5087 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num, 5088 struct device_node *port_dn) 5089 { 5090 phy_interface_t phy_mode = dev->ports[port_num].interface; 5091 int rx_delay = -1, tx_delay = -1; 5092 5093 if (!phy_interface_mode_is_rgmii(phy_mode)) 5094 return; 5095 5096 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay); 5097 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay); 5098 5099 if (rx_delay == -1 && tx_delay == -1) { 5100 dev_warn(dev->dev, 5101 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, " 5102 "please update device tree to specify \"rx-internal-delay-ps\" and " 5103 "\"tx-internal-delay-ps\"", 5104 port_num); 5105 5106 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID || 5107 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 5108 rx_delay = 2000; 5109 5110 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID || 5111 phy_mode == PHY_INTERFACE_MODE_RGMII_ID) 5112 tx_delay = 2000; 5113 } 5114 5115 if (rx_delay < 0) 5116 rx_delay = 0; 5117 if (tx_delay < 0) 5118 tx_delay = 0; 5119 5120 dev->ports[port_num].rgmii_rx_val = rx_delay; 5121 dev->ports[port_num].rgmii_tx_val = tx_delay; 5122 } 5123 5124 /** 5125 * ksz_drive_strength_to_reg() - Convert drive strength value to corresponding 5126 * register value. 5127 * @array: The array of drive strength values to search. 5128 * @array_size: The size of the array. 5129 * @microamp: The drive strength value in microamp to be converted. 5130 * 5131 * This function searches the array of drive strength values for the given 5132 * microamp value and returns the corresponding register value for that drive. 5133 * 5134 * Returns: If found, the corresponding register value for that drive strength 5135 * is returned. Otherwise, -EINVAL is returned indicating an invalid value. 5136 */ 5137 static int ksz_drive_strength_to_reg(const struct ksz_drive_strength *array, 5138 size_t array_size, int microamp) 5139 { 5140 int i; 5141 5142 for (i = 0; i < array_size; i++) { 5143 if (array[i].microamp == microamp) 5144 return array[i].reg_val; 5145 } 5146 5147 return -EINVAL; 5148 } 5149 5150 /** 5151 * ksz_drive_strength_error() - Report invalid drive strength value 5152 * @dev: ksz device 5153 * @array: The array of drive strength values to search. 5154 * @array_size: The size of the array. 5155 * @microamp: Invalid drive strength value in microamp 5156 * 5157 * This function logs an error message when an unsupported drive strength value 5158 * is detected. It lists out all the supported drive strength values for 5159 * reference in the error message. 5160 */ 5161 static void ksz_drive_strength_error(struct ksz_device *dev, 5162 const struct ksz_drive_strength *array, 5163 size_t array_size, int microamp) 5164 { 5165 char supported_values[100]; 5166 size_t remaining_size; 5167 int added_len; 5168 char *ptr; 5169 int i; 5170 5171 remaining_size = sizeof(supported_values); 5172 ptr = supported_values; 5173 5174 for (i = 0; i < array_size; i++) { 5175 added_len = snprintf(ptr, remaining_size, 5176 i == 0 ? "%d" : ", %d", array[i].microamp); 5177 5178 if (added_len >= remaining_size) 5179 break; 5180 5181 ptr += added_len; 5182 remaining_size -= added_len; 5183 } 5184 5185 dev_err(dev->dev, "Invalid drive strength %d, supported values are %s\n", 5186 microamp, supported_values); 5187 } 5188 5189 /** 5190 * ksz9477_drive_strength_write() - Set the drive strength for specific KSZ9477 5191 * chip variants. 5192 * @dev: ksz device 5193 * @props: Array of drive strength properties to be applied 5194 * @num_props: Number of properties in the array 5195 * 5196 * This function configures the drive strength for various KSZ9477 chip variants 5197 * based on the provided properties. It handles chip-specific nuances and 5198 * ensures only valid drive strengths are written to the respective chip. 5199 * 5200 * Return: 0 on successful configuration, a negative error code on failure. 5201 */ 5202 static int ksz9477_drive_strength_write(struct ksz_device *dev, 5203 struct ksz_driver_strength_prop *props, 5204 int num_props) 5205 { 5206 size_t array_size = ARRAY_SIZE(ksz9477_drive_strengths); 5207 int i, ret, reg; 5208 u8 mask = 0; 5209 u8 val = 0; 5210 5211 if (props[KSZ_DRIVER_STRENGTH_IO].value != -1) 5212 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 5213 props[KSZ_DRIVER_STRENGTH_IO].name); 5214 5215 if (dev->chip_id == KSZ8795_CHIP_ID || 5216 dev->chip_id == KSZ8794_CHIP_ID || 5217 dev->chip_id == KSZ8765_CHIP_ID) 5218 reg = KSZ8795_REG_SW_CTRL_20; 5219 else 5220 reg = KSZ9477_REG_SW_IO_STRENGTH; 5221 5222 for (i = 0; i < num_props; i++) { 5223 if (props[i].value == -1) 5224 continue; 5225 5226 ret = ksz_drive_strength_to_reg(ksz9477_drive_strengths, 5227 array_size, props[i].value); 5228 if (ret < 0) { 5229 ksz_drive_strength_error(dev, ksz9477_drive_strengths, 5230 array_size, props[i].value); 5231 return ret; 5232 } 5233 5234 mask |= SW_DRIVE_STRENGTH_M << props[i].offset; 5235 val |= ret << props[i].offset; 5236 } 5237 5238 return ksz_rmw8(dev, reg, mask, val); 5239 } 5240 5241 /** 5242 * ksz88x3_drive_strength_write() - Set the drive strength configuration for 5243 * KSZ8863 compatible chip variants. 5244 * @dev: ksz device 5245 * @props: Array of drive strength properties to be set 5246 * @num_props: Number of properties in the array 5247 * 5248 * This function applies the specified drive strength settings to KSZ88X3 chip 5249 * variants (KSZ8873, KSZ8863). 5250 * It ensures the configurations align with what the chip variant supports and 5251 * warns or errors out on unsupported settings. 5252 * 5253 * Return: 0 on success, error code otherwise 5254 */ 5255 static int ksz88x3_drive_strength_write(struct ksz_device *dev, 5256 struct ksz_driver_strength_prop *props, 5257 int num_props) 5258 { 5259 size_t array_size = ARRAY_SIZE(ksz88x3_drive_strengths); 5260 int microamp; 5261 int i, ret; 5262 5263 for (i = 0; i < num_props; i++) { 5264 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO) 5265 continue; 5266 5267 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 5268 props[i].name); 5269 } 5270 5271 microamp = props[KSZ_DRIVER_STRENGTH_IO].value; 5272 ret = ksz_drive_strength_to_reg(ksz88x3_drive_strengths, array_size, 5273 microamp); 5274 if (ret < 0) { 5275 ksz_drive_strength_error(dev, ksz88x3_drive_strengths, 5276 array_size, microamp); 5277 return ret; 5278 } 5279 5280 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12, 5281 KSZ8873_DRIVE_STRENGTH_16MA, ret); 5282 } 5283 5284 /** 5285 * ksz_parse_drive_strength() - Extract and apply drive strength configurations 5286 * from device tree properties. 5287 * @dev: ksz device 5288 * 5289 * This function reads the specified drive strength properties from the 5290 * device tree, validates against the supported chip variants, and sets 5291 * them accordingly. An error should be critical here, as the drive strength 5292 * settings are crucial for EMI compliance. 5293 * 5294 * Return: 0 on success, error code otherwise 5295 */ 5296 static int ksz_parse_drive_strength(struct ksz_device *dev) 5297 { 5298 struct ksz_driver_strength_prop of_props[] = { 5299 [KSZ_DRIVER_STRENGTH_HI] = { 5300 .name = "microchip,hi-drive-strength-microamp", 5301 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S, 5302 .value = -1, 5303 }, 5304 [KSZ_DRIVER_STRENGTH_LO] = { 5305 .name = "microchip,lo-drive-strength-microamp", 5306 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S, 5307 .value = -1, 5308 }, 5309 [KSZ_DRIVER_STRENGTH_IO] = { 5310 .name = "microchip,io-drive-strength-microamp", 5311 .offset = 0, /* don't care */ 5312 .value = -1, 5313 }, 5314 }; 5315 struct device_node *np = dev->dev->of_node; 5316 bool have_any_prop = false; 5317 int i, ret; 5318 5319 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 5320 ret = of_property_read_u32(np, of_props[i].name, 5321 &of_props[i].value); 5322 if (ret && ret != -EINVAL) 5323 dev_warn(dev->dev, "Failed to read %s\n", 5324 of_props[i].name); 5325 if (ret) 5326 continue; 5327 5328 have_any_prop = true; 5329 } 5330 5331 if (!have_any_prop) 5332 return 0; 5333 5334 switch (dev->chip_id) { 5335 case KSZ88X3_CHIP_ID: 5336 return ksz88x3_drive_strength_write(dev, of_props, 5337 ARRAY_SIZE(of_props)); 5338 case KSZ8795_CHIP_ID: 5339 case KSZ8794_CHIP_ID: 5340 case KSZ8765_CHIP_ID: 5341 case KSZ8563_CHIP_ID: 5342 case KSZ8567_CHIP_ID: 5343 case KSZ9477_CHIP_ID: 5344 case KSZ9563_CHIP_ID: 5345 case KSZ9567_CHIP_ID: 5346 case KSZ9893_CHIP_ID: 5347 case KSZ9896_CHIP_ID: 5348 case KSZ9897_CHIP_ID: 5349 case LAN9646_CHIP_ID: 5350 return ksz9477_drive_strength_write(dev, of_props, 5351 ARRAY_SIZE(of_props)); 5352 default: 5353 for (i = 0; i < ARRAY_SIZE(of_props); i++) { 5354 if (of_props[i].value == -1) 5355 continue; 5356 5357 dev_warn(dev->dev, "%s is not supported by this chip variant\n", 5358 of_props[i].name); 5359 } 5360 } 5361 5362 return 0; 5363 } 5364 5365 static int ksz8463_configure_straps_spi(struct ksz_device *dev) 5366 { 5367 struct pinctrl *pinctrl; 5368 struct gpio_desc *rxd0; 5369 struct gpio_desc *rxd1; 5370 5371 rxd0 = devm_gpiod_get_index_optional(dev->dev, "straps-rxd", 0, GPIOD_OUT_LOW); 5372 if (IS_ERR(rxd0)) 5373 return PTR_ERR(rxd0); 5374 5375 rxd1 = devm_gpiod_get_index_optional(dev->dev, "straps-rxd", 1, GPIOD_OUT_HIGH); 5376 if (IS_ERR(rxd1)) 5377 return PTR_ERR(rxd1); 5378 5379 if (!rxd0 && !rxd1) 5380 return 0; 5381 5382 if ((rxd0 && !rxd1) || (rxd1 && !rxd0)) 5383 return -EINVAL; 5384 5385 pinctrl = devm_pinctrl_get_select(dev->dev, "reset"); 5386 if (IS_ERR(pinctrl)) 5387 return PTR_ERR(pinctrl); 5388 5389 return 0; 5390 } 5391 5392 static int ksz8463_release_straps_spi(struct ksz_device *dev) 5393 { 5394 return pinctrl_select_default_state(dev->dev); 5395 } 5396 5397 int ksz_switch_register(struct ksz_device *dev) 5398 { 5399 const struct ksz_chip_data *info; 5400 struct device_node *ports; 5401 phy_interface_t interface; 5402 unsigned int port_num; 5403 int ret; 5404 int i; 5405 5406 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset", 5407 GPIOD_OUT_LOW); 5408 if (IS_ERR(dev->reset_gpio)) 5409 return PTR_ERR(dev->reset_gpio); 5410 5411 if (dev->reset_gpio) { 5412 if (of_device_is_compatible(dev->dev->of_node, "microchip,ksz8463")) { 5413 ret = ksz8463_configure_straps_spi(dev); 5414 if (ret) 5415 return ret; 5416 } 5417 5418 gpiod_set_value_cansleep(dev->reset_gpio, 1); 5419 usleep_range(10000, 12000); 5420 gpiod_set_value_cansleep(dev->reset_gpio, 0); 5421 msleep(100); 5422 5423 if (of_device_is_compatible(dev->dev->of_node, "microchip,ksz8463")) { 5424 ret = ksz8463_release_straps_spi(dev); 5425 if (ret) 5426 return ret; 5427 } 5428 } 5429 5430 mutex_init(&dev->dev_mutex); 5431 mutex_init(&dev->regmap_mutex); 5432 mutex_init(&dev->alu_mutex); 5433 mutex_init(&dev->vlan_mutex); 5434 5435 ret = ksz_switch_detect(dev); 5436 if (ret) 5437 return ret; 5438 5439 info = ksz_lookup_info(dev->chip_id); 5440 if (!info) 5441 return -ENODEV; 5442 5443 /* Update the compatible info with the probed one */ 5444 dev->info = info; 5445 5446 dev_info(dev->dev, "found switch: %s, rev %i\n", 5447 dev->info->dev_name, dev->chip_rev); 5448 5449 ret = ksz_check_device_id(dev); 5450 if (ret) 5451 return ret; 5452 5453 dev->dev_ops = dev->info->ops; 5454 5455 ret = dev->dev_ops->init(dev); 5456 if (ret) 5457 return ret; 5458 5459 dev->ports = devm_kzalloc(dev->dev, 5460 dev->info->port_cnt * sizeof(struct ksz_port), 5461 GFP_KERNEL); 5462 if (!dev->ports) 5463 return -ENOMEM; 5464 5465 for (i = 0; i < dev->info->port_cnt; i++) { 5466 spin_lock_init(&dev->ports[i].mib.stats64_lock); 5467 mutex_init(&dev->ports[i].mib.cnt_mutex); 5468 dev->ports[i].mib.counters = 5469 devm_kzalloc(dev->dev, 5470 sizeof(u64) * (dev->info->mib_cnt + 1), 5471 GFP_KERNEL); 5472 if (!dev->ports[i].mib.counters) 5473 return -ENOMEM; 5474 5475 dev->ports[i].ksz_dev = dev; 5476 dev->ports[i].num = i; 5477 } 5478 5479 /* set the real number of ports */ 5480 dev->ds->num_ports = dev->info->port_cnt; 5481 5482 /* set the phylink ops */ 5483 dev->ds->phylink_mac_ops = dev->info->phylink_mac_ops; 5484 5485 /* Host port interface will be self detected, or specifically set in 5486 * device tree. 5487 */ 5488 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num) 5489 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA; 5490 if (dev->dev->of_node) { 5491 ret = of_get_phy_mode(dev->dev->of_node, &interface); 5492 if (ret == 0) 5493 dev->compat_interface = interface; 5494 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports"); 5495 if (!ports) 5496 ports = of_get_child_by_name(dev->dev->of_node, "ports"); 5497 if (ports) { 5498 for_each_available_child_of_node_scoped(ports, port) { 5499 if (of_property_read_u32(port, "reg", 5500 &port_num)) 5501 continue; 5502 if (!(dev->port_mask & BIT(port_num))) { 5503 of_node_put(ports); 5504 return -EINVAL; 5505 } 5506 of_get_phy_mode(port, 5507 &dev->ports[port_num].interface); 5508 5509 ksz_parse_rgmii_delay(dev, port_num, port); 5510 dev->ports[port_num].fiber = 5511 of_property_read_bool(port, 5512 "micrel,fiber-mode"); 5513 } 5514 of_node_put(ports); 5515 } 5516 dev->synclko_125 = of_property_read_bool(dev->dev->of_node, 5517 "microchip,synclko-125"); 5518 dev->synclko_disable = of_property_read_bool(dev->dev->of_node, 5519 "microchip,synclko-disable"); 5520 if (dev->synclko_125 && dev->synclko_disable) { 5521 dev_err(dev->dev, "inconsistent synclko settings\n"); 5522 return -EINVAL; 5523 } 5524 5525 dev->wakeup_source = of_property_read_bool(dev->dev->of_node, 5526 "wakeup-source"); 5527 dev->pme_active_high = of_property_read_bool(dev->dev->of_node, 5528 "microchip,pme-active-high"); 5529 } 5530 5531 ret = dsa_register_switch(dev->ds); 5532 if (ret) { 5533 dev->dev_ops->exit(dev); 5534 return ret; 5535 } 5536 5537 /* Read MIB counters every 30 seconds to avoid overflow. */ 5538 dev->mib_read_interval = msecs_to_jiffies(5000); 5539 5540 /* Start the MIB timer. */ 5541 schedule_delayed_work(&dev->mib_read, 0); 5542 5543 return ret; 5544 } 5545 EXPORT_SYMBOL(ksz_switch_register); 5546 5547 void ksz_switch_remove(struct ksz_device *dev) 5548 { 5549 /* timer started */ 5550 if (dev->mib_read_interval) { 5551 dev->mib_read_interval = 0; 5552 cancel_delayed_work_sync(&dev->mib_read); 5553 } 5554 5555 dev->dev_ops->exit(dev); 5556 dsa_unregister_switch(dev->ds); 5557 5558 if (dev->reset_gpio) 5559 gpiod_set_value_cansleep(dev->reset_gpio, 1); 5560 5561 } 5562 EXPORT_SYMBOL(ksz_switch_remove); 5563 5564 #ifdef CONFIG_PM_SLEEP 5565 int ksz_switch_suspend(struct device *dev) 5566 { 5567 struct ksz_device *priv = dev_get_drvdata(dev); 5568 5569 return dsa_switch_suspend(priv->ds); 5570 } 5571 EXPORT_SYMBOL(ksz_switch_suspend); 5572 5573 int ksz_switch_resume(struct device *dev) 5574 { 5575 struct ksz_device *priv = dev_get_drvdata(dev); 5576 5577 return dsa_switch_resume(priv->ds); 5578 } 5579 EXPORT_SYMBOL(ksz_switch_resume); 5580 #endif 5581 5582 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>"); 5583 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver"); 5584 MODULE_LICENSE("GPL"); 5585