xref: /linux/drivers/net/dsa/microchip/ksz8.c (revision 9410645520e9b820069761f3450ef6661418e279)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Microchip KSZ8XXX series switch driver
4  *
5  * It supports the following switches:
6  * - KSZ8863, KSZ8873 aka KSZ88X3
7  * - KSZ8895, KSZ8864 aka KSZ8895 family
8  * - KSZ8794, KSZ8795, KSZ8765 aka KSZ87XX
9  * Note that it does NOT support:
10  * - KSZ8563, KSZ8567 - see KSZ9477 driver
11  *
12  * Copyright (C) 2017 Microchip Technology Inc.
13  *	Tristram Ha <Tristram.Ha@microchip.com>
14  */
15 
16 #include <linux/bitfield.h>
17 #include <linux/delay.h>
18 #include <linux/export.h>
19 #include <linux/gpio.h>
20 #include <linux/if_vlan.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/platform_data/microchip-ksz.h>
24 #include <linux/phy.h>
25 #include <linux/etherdevice.h>
26 #include <linux/if_bridge.h>
27 #include <linux/micrel_phy.h>
28 #include <net/dsa.h>
29 #include <net/switchdev.h>
30 #include <linux/phylink.h>
31 
32 #include "ksz_common.h"
33 #include "ksz8_reg.h"
34 #include "ksz8.h"
35 
ksz_cfg(struct ksz_device * dev,u32 addr,u8 bits,bool set)36 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
37 {
38 	regmap_update_bits(ksz_regmap_8(dev), addr, bits, set ? bits : 0);
39 }
40 
ksz_port_cfg(struct ksz_device * dev,int port,int offset,u8 bits,bool set)41 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
42 			 bool set)
43 {
44 	regmap_update_bits(ksz_regmap_8(dev), PORT_CTRL_ADDR(port, offset),
45 			   bits, set ? bits : 0);
46 }
47 
48 /**
49  * ksz8_ind_write8 - EEE/ACL/PME indirect register write
50  * @dev: The device structure.
51  * @table: Function & table select, register 110.
52  * @addr: Indirect access control, register 111.
53  * @data: The data to be written.
54  *
55  * This function performs an indirect register write for EEE, ACL or
56  * PME switch functionalities. Both 8-bit registers 110 and 111 are
57  * written at once with ksz_write16, using the serial multiple write
58  * functionality.
59  *
60  * Return: 0 on success, or an error code on failure.
61  */
ksz8_ind_write8(struct ksz_device * dev,u8 table,u16 addr,u8 data)62 static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data)
63 {
64 	const u16 *regs;
65 	u16 ctrl_addr;
66 	int ret = 0;
67 
68 	regs = dev->info->regs;
69 
70 	mutex_lock(&dev->alu_mutex);
71 
72 	ctrl_addr = IND_ACC_TABLE(table) | addr;
73 	ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
74 	if (!ret)
75 		ret = ksz_write8(dev, regs[REG_IND_BYTE], data);
76 
77 	mutex_unlock(&dev->alu_mutex);
78 
79 	return ret;
80 }
81 
82 /**
83  * ksz8_ind_read8 - EEE/ACL/PME indirect register read
84  * @dev: The device structure.
85  * @table: Function & table select, register 110.
86  * @addr: Indirect access control, register 111.
87  * @val: The value read.
88  *
89  * This function performs an indirect register read for EEE, ACL or
90  * PME switch functionalities. Both 8-bit registers 110 and 111 are
91  * written at once with ksz_write16, using the serial multiple write
92  * functionality.
93  *
94  * Return: 0 on success, or an error code on failure.
95  */
ksz8_ind_read8(struct ksz_device * dev,u8 table,u16 addr,u8 * val)96 static int ksz8_ind_read8(struct ksz_device *dev, u8 table, u16 addr, u8 *val)
97 {
98 	const u16 *regs;
99 	u16 ctrl_addr;
100 	int ret = 0;
101 
102 	regs = dev->info->regs;
103 
104 	mutex_lock(&dev->alu_mutex);
105 
106 	ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
107 	ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
108 	if (!ret)
109 		ret = ksz_read8(dev, regs[REG_IND_BYTE], val);
110 
111 	mutex_unlock(&dev->alu_mutex);
112 
113 	return ret;
114 }
115 
ksz8_pme_write8(struct ksz_device * dev,u32 reg,u8 value)116 int ksz8_pme_write8(struct ksz_device *dev, u32 reg, u8 value)
117 {
118 	return ksz8_ind_write8(dev, (u8)(reg >> 8), (u8)(reg), value);
119 }
120 
ksz8_pme_pread8(struct ksz_device * dev,int port,int offset,u8 * data)121 int ksz8_pme_pread8(struct ksz_device *dev, int port, int offset, u8 *data)
122 {
123 	u8 table = (u8)(offset >> 8 | (port + 1));
124 
125 	return ksz8_ind_read8(dev, table, (u8)(offset), data);
126 }
127 
ksz8_pme_pwrite8(struct ksz_device * dev,int port,int offset,u8 data)128 int ksz8_pme_pwrite8(struct ksz_device *dev, int port, int offset, u8 data)
129 {
130 	u8 table = (u8)(offset >> 8 | (port + 1));
131 
132 	return ksz8_ind_write8(dev, table, (u8)(offset), data);
133 }
134 
ksz8_reset_switch(struct ksz_device * dev)135 int ksz8_reset_switch(struct ksz_device *dev)
136 {
137 	if (ksz_is_ksz88x3(dev)) {
138 		/* reset switch */
139 		ksz_cfg(dev, KSZ8863_REG_SW_RESET,
140 			KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true);
141 		ksz_cfg(dev, KSZ8863_REG_SW_RESET,
142 			KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false);
143 	} else {
144 		/* reset switch */
145 		ksz_write8(dev, REG_POWER_MANAGEMENT_1,
146 			   SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S);
147 		ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0);
148 	}
149 
150 	return 0;
151 }
152 
ksz8863_change_mtu(struct ksz_device * dev,int frame_size)153 static int ksz8863_change_mtu(struct ksz_device *dev, int frame_size)
154 {
155 	u8 ctrl2 = 0;
156 
157 	if (frame_size <= KSZ8_LEGAL_PACKET_SIZE)
158 		ctrl2 |= KSZ8863_LEGAL_PACKET_ENABLE;
159 	else if (frame_size > KSZ8863_NORMAL_PACKET_SIZE)
160 		ctrl2 |= KSZ8863_HUGE_PACKET_ENABLE;
161 
162 	return ksz_rmw8(dev, REG_SW_CTRL_2, KSZ8863_LEGAL_PACKET_ENABLE |
163 			KSZ8863_HUGE_PACKET_ENABLE, ctrl2);
164 }
165 
ksz8795_change_mtu(struct ksz_device * dev,int frame_size)166 static int ksz8795_change_mtu(struct ksz_device *dev, int frame_size)
167 {
168 	u8 ctrl1 = 0, ctrl2 = 0;
169 	int ret;
170 
171 	if (frame_size > KSZ8_LEGAL_PACKET_SIZE)
172 		ctrl2 |= SW_LEGAL_PACKET_DISABLE;
173 	if (frame_size > KSZ8863_NORMAL_PACKET_SIZE)
174 		ctrl1 |= SW_HUGE_PACKET;
175 
176 	ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_HUGE_PACKET, ctrl1);
177 	if (ret)
178 		return ret;
179 
180 	return ksz_rmw8(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, ctrl2);
181 }
182 
ksz8_change_mtu(struct ksz_device * dev,int port,int mtu)183 int ksz8_change_mtu(struct ksz_device *dev, int port, int mtu)
184 {
185 	u16 frame_size;
186 
187 	if (!dsa_is_cpu_port(dev->ds, port))
188 		return 0;
189 
190 	frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
191 
192 	switch (dev->chip_id) {
193 	case KSZ8795_CHIP_ID:
194 	case KSZ8794_CHIP_ID:
195 	case KSZ8765_CHIP_ID:
196 		return ksz8795_change_mtu(dev, frame_size);
197 	case KSZ88X3_CHIP_ID:
198 	case KSZ8864_CHIP_ID:
199 	case KSZ8895_CHIP_ID:
200 		return ksz8863_change_mtu(dev, frame_size);
201 	}
202 
203 	return -EOPNOTSUPP;
204 }
205 
ksz8_port_queue_split(struct ksz_device * dev,int port,int queues)206 static int ksz8_port_queue_split(struct ksz_device *dev, int port, int queues)
207 {
208 	u8 mask_4q, mask_2q;
209 	u8 reg_4q, reg_2q;
210 	u8 data_4q = 0;
211 	u8 data_2q = 0;
212 	int ret;
213 
214 	if (ksz_is_ksz88x3(dev)) {
215 		mask_4q = KSZ8873_PORT_4QUEUE_SPLIT_EN;
216 		mask_2q = KSZ8873_PORT_2QUEUE_SPLIT_EN;
217 		reg_4q = REG_PORT_CTRL_0;
218 		reg_2q = REG_PORT_CTRL_2;
219 
220 		/* KSZ8795 family switches have Weighted Fair Queueing (WFQ)
221 		 * enabled by default. Enable it for KSZ8873 family switches
222 		 * too. Default value for KSZ8873 family is strict priority,
223 		 * which should be enabled by using TC_SETUP_QDISC_ETS, not
224 		 * by default.
225 		 */
226 		ret = ksz_rmw8(dev, REG_SW_CTRL_3, WEIGHTED_FAIR_QUEUE_ENABLE,
227 			       WEIGHTED_FAIR_QUEUE_ENABLE);
228 		if (ret)
229 			return ret;
230 	} else {
231 		mask_4q = KSZ8795_PORT_4QUEUE_SPLIT_EN;
232 		mask_2q = KSZ8795_PORT_2QUEUE_SPLIT_EN;
233 		reg_4q = REG_PORT_CTRL_13;
234 		reg_2q = REG_PORT_CTRL_0;
235 
236 		/* TODO: this is legacy from initial KSZ8795 driver, should be
237 		 * moved to appropriate place in the future.
238 		 */
239 		ret = ksz_rmw8(dev, REG_SW_CTRL_19,
240 			       SW_OUT_RATE_LIMIT_QUEUE_BASED,
241 			       SW_OUT_RATE_LIMIT_QUEUE_BASED);
242 		if (ret)
243 			return ret;
244 	}
245 
246 	if (queues == 4)
247 		data_4q = mask_4q;
248 	else if (queues == 2)
249 		data_2q = mask_2q;
250 
251 	ret = ksz_prmw8(dev, port, reg_4q, mask_4q, data_4q);
252 	if (ret)
253 		return ret;
254 
255 	return ksz_prmw8(dev, port, reg_2q, mask_2q, data_2q);
256 }
257 
ksz8_all_queues_split(struct ksz_device * dev,int queues)258 int ksz8_all_queues_split(struct ksz_device *dev, int queues)
259 {
260 	struct dsa_switch *ds = dev->ds;
261 	const struct dsa_port *dp;
262 
263 	dsa_switch_for_each_port(dp, ds) {
264 		int ret = ksz8_port_queue_split(dev, dp->index, queues);
265 
266 		if (ret)
267 			return ret;
268 	}
269 
270 	return 0;
271 }
272 
ksz8_r_mib_cnt(struct ksz_device * dev,int port,u16 addr,u64 * cnt)273 void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt)
274 {
275 	const u32 *masks;
276 	const u16 *regs;
277 	u16 ctrl_addr;
278 	u32 data;
279 	u8 check;
280 	int loop;
281 
282 	masks = dev->info->masks;
283 	regs = dev->info->regs;
284 
285 	ctrl_addr = addr + dev->info->reg_mib_cnt * port;
286 	ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
287 
288 	mutex_lock(&dev->alu_mutex);
289 	ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
290 
291 	/* It is almost guaranteed to always read the valid bit because of
292 	 * slow SPI speed.
293 	 */
294 	for (loop = 2; loop > 0; loop--) {
295 		ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
296 
297 		if (check & masks[MIB_COUNTER_VALID]) {
298 			ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
299 			if (check & masks[MIB_COUNTER_OVERFLOW])
300 				*cnt += MIB_COUNTER_VALUE + 1;
301 			*cnt += data & MIB_COUNTER_VALUE;
302 			break;
303 		}
304 	}
305 	mutex_unlock(&dev->alu_mutex);
306 }
307 
ksz8795_r_mib_pkt(struct ksz_device * dev,int port,u16 addr,u64 * dropped,u64 * cnt)308 static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
309 			      u64 *dropped, u64 *cnt)
310 {
311 	const u32 *masks;
312 	const u16 *regs;
313 	u16 ctrl_addr;
314 	u32 data;
315 	u8 check;
316 	int loop;
317 
318 	masks = dev->info->masks;
319 	regs = dev->info->regs;
320 
321 	addr -= dev->info->reg_mib_cnt;
322 	ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port;
323 	ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0;
324 	ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
325 
326 	mutex_lock(&dev->alu_mutex);
327 	ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
328 
329 	/* It is almost guaranteed to always read the valid bit because of
330 	 * slow SPI speed.
331 	 */
332 	for (loop = 2; loop > 0; loop--) {
333 		ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
334 
335 		if (check & masks[MIB_COUNTER_VALID]) {
336 			ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
337 			if (addr < 2) {
338 				u64 total;
339 
340 				total = check & MIB_TOTAL_BYTES_H;
341 				total <<= 32;
342 				*cnt += total;
343 				*cnt += data;
344 				if (check & masks[MIB_COUNTER_OVERFLOW]) {
345 					total = MIB_TOTAL_BYTES_H + 1;
346 					total <<= 32;
347 					*cnt += total;
348 				}
349 			} else {
350 				if (check & masks[MIB_COUNTER_OVERFLOW])
351 					*cnt += MIB_PACKET_DROPPED + 1;
352 				*cnt += data & MIB_PACKET_DROPPED;
353 			}
354 			break;
355 		}
356 	}
357 	mutex_unlock(&dev->alu_mutex);
358 }
359 
ksz8863_r_mib_pkt(struct ksz_device * dev,int port,u16 addr,u64 * dropped,u64 * cnt)360 static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
361 			      u64 *dropped, u64 *cnt)
362 {
363 	u32 *last = (u32 *)dropped;
364 	const u16 *regs;
365 	u16 ctrl_addr;
366 	u32 data;
367 	u32 cur;
368 
369 	regs = dev->info->regs;
370 
371 	addr -= dev->info->reg_mib_cnt;
372 	ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 :
373 			   KSZ8863_MIB_PACKET_DROPPED_RX_0;
374 	ctrl_addr += port;
375 	ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
376 
377 	mutex_lock(&dev->alu_mutex);
378 	ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
379 	ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
380 	mutex_unlock(&dev->alu_mutex);
381 
382 	data &= MIB_PACKET_DROPPED;
383 	cur = last[addr];
384 	if (data != cur) {
385 		last[addr] = data;
386 		if (data < cur)
387 			data += MIB_PACKET_DROPPED + 1;
388 		data -= cur;
389 		*cnt += data;
390 	}
391 }
392 
ksz8_r_mib_pkt(struct ksz_device * dev,int port,u16 addr,u64 * dropped,u64 * cnt)393 void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
394 		    u64 *dropped, u64 *cnt)
395 {
396 	if (is_ksz88xx(dev))
397 		ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt);
398 	else
399 		ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt);
400 }
401 
ksz8_freeze_mib(struct ksz_device * dev,int port,bool freeze)402 void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze)
403 {
404 	if (is_ksz88xx(dev))
405 		return;
406 
407 	/* enable the port for flush/freeze function */
408 	if (freeze)
409 		ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
410 	ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze);
411 
412 	/* disable the port after freeze is done */
413 	if (!freeze)
414 		ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
415 }
416 
ksz8_port_init_cnt(struct ksz_device * dev,int port)417 void ksz8_port_init_cnt(struct ksz_device *dev, int port)
418 {
419 	struct ksz_port_mib *mib = &dev->ports[port].mib;
420 	u64 *dropped;
421 
422 	/* For KSZ8795 family. */
423 	if (ksz_is_ksz87xx(dev)) {
424 		/* flush all enabled port MIB counters */
425 		ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
426 		ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true);
427 		ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
428 	}
429 
430 	mib->cnt_ptr = 0;
431 
432 	/* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
433 	while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
434 		dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
435 					&mib->counters[mib->cnt_ptr]);
436 		++mib->cnt_ptr;
437 	}
438 
439 	/* last one in storage */
440 	dropped = &mib->counters[dev->info->mib_cnt];
441 
442 	/* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
443 	while (mib->cnt_ptr < dev->info->mib_cnt) {
444 		dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
445 					dropped, &mib->counters[mib->cnt_ptr]);
446 		++mib->cnt_ptr;
447 	}
448 }
449 
ksz8_r_table(struct ksz_device * dev,int table,u16 addr,u64 * data)450 static int ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data)
451 {
452 	const u16 *regs;
453 	u16 ctrl_addr;
454 	int ret;
455 
456 	regs = dev->info->regs;
457 
458 	ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
459 
460 	mutex_lock(&dev->alu_mutex);
461 	ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
462 	if (ret)
463 		goto unlock_alu;
464 
465 	ret = ksz_read64(dev, regs[REG_IND_DATA_HI], data);
466 unlock_alu:
467 	mutex_unlock(&dev->alu_mutex);
468 
469 	return ret;
470 }
471 
ksz8_w_table(struct ksz_device * dev,int table,u16 addr,u64 data)472 static int ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data)
473 {
474 	const u16 *regs;
475 	u16 ctrl_addr;
476 	int ret;
477 
478 	regs = dev->info->regs;
479 
480 	ctrl_addr = IND_ACC_TABLE(table) | addr;
481 
482 	mutex_lock(&dev->alu_mutex);
483 	ret = ksz_write64(dev, regs[REG_IND_DATA_HI], data);
484 	if (ret)
485 		goto unlock_alu;
486 
487 	ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
488 unlock_alu:
489 	mutex_unlock(&dev->alu_mutex);
490 
491 	return ret;
492 }
493 
ksz8_valid_dyn_entry(struct ksz_device * dev,u8 * data)494 static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data)
495 {
496 	int timeout = 100;
497 	const u32 *masks;
498 	const u16 *regs;
499 	int ret;
500 
501 	masks = dev->info->masks;
502 	regs = dev->info->regs;
503 
504 	do {
505 		ret = ksz_read8(dev, regs[REG_IND_DATA_CHECK], data);
506 		if (ret)
507 			return ret;
508 
509 		timeout--;
510 	} while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout);
511 
512 	/* Entry is not ready for accessing. */
513 	if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY])
514 		return -ETIMEDOUT;
515 
516 	/* Entry is ready for accessing. */
517 	return ksz_read8(dev, regs[REG_IND_DATA_8], data);
518 }
519 
ksz8_r_dyn_mac_table(struct ksz_device * dev,u16 addr,u8 * mac_addr,u8 * fid,u8 * src_port,u16 * entries)520 static int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr, u8 *mac_addr,
521 				u8 *fid, u8 *src_port, u16 *entries)
522 {
523 	u32 data_hi, data_lo;
524 	const u8 *shifts;
525 	const u32 *masks;
526 	const u16 *regs;
527 	u16 ctrl_addr;
528 	u64 buf = 0;
529 	u8 data;
530 	int cnt;
531 	int ret;
532 
533 	shifts = dev->info->shifts;
534 	masks = dev->info->masks;
535 	regs = dev->info->regs;
536 
537 	ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr;
538 
539 	mutex_lock(&dev->alu_mutex);
540 	ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
541 	if (ret)
542 		goto unlock_alu;
543 
544 	ret = ksz8_valid_dyn_entry(dev, &data);
545 	if (ret)
546 		goto unlock_alu;
547 
548 	if (data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY]) {
549 		*entries = 0;
550 		goto unlock_alu;
551 	}
552 
553 	ret = ksz_read64(dev, regs[REG_IND_DATA_HI], &buf);
554 	if (ret)
555 		goto unlock_alu;
556 
557 	data_hi = (u32)(buf >> 32);
558 	data_lo = (u32)buf;
559 
560 	/* Check out how many valid entry in the table. */
561 	cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H];
562 	cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H];
563 	cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >>
564 		shifts[DYNAMIC_MAC_ENTRIES];
565 	*entries = cnt + 1;
566 
567 	*fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >>
568 		shifts[DYNAMIC_MAC_FID];
569 	*src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >>
570 		shifts[DYNAMIC_MAC_SRC_PORT];
571 
572 	mac_addr[5] = (u8)data_lo;
573 	mac_addr[4] = (u8)(data_lo >> 8);
574 	mac_addr[3] = (u8)(data_lo >> 16);
575 	mac_addr[2] = (u8)(data_lo >> 24);
576 
577 	mac_addr[1] = (u8)data_hi;
578 	mac_addr[0] = (u8)(data_hi >> 8);
579 
580 unlock_alu:
581 	mutex_unlock(&dev->alu_mutex);
582 
583 	return ret;
584 }
585 
ksz8_r_sta_mac_table(struct ksz_device * dev,u16 addr,struct alu_struct * alu,bool * valid)586 static int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr,
587 				struct alu_struct *alu, bool *valid)
588 {
589 	u32 data_hi, data_lo;
590 	const u8 *shifts;
591 	const u32 *masks;
592 	u64 data;
593 	int ret;
594 
595 	shifts = dev->info->shifts;
596 	masks = dev->info->masks;
597 
598 	ret = ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data);
599 	if (ret)
600 		return ret;
601 
602 	data_hi = data >> 32;
603 	data_lo = (u32)data;
604 
605 	if (!(data_hi & (masks[STATIC_MAC_TABLE_VALID] |
606 			 masks[STATIC_MAC_TABLE_OVERRIDE]))) {
607 		*valid = false;
608 		return 0;
609 	}
610 
611 	alu->mac[5] = (u8)data_lo;
612 	alu->mac[4] = (u8)(data_lo >> 8);
613 	alu->mac[3] = (u8)(data_lo >> 16);
614 	alu->mac[2] = (u8)(data_lo >> 24);
615 	alu->mac[1] = (u8)data_hi;
616 	alu->mac[0] = (u8)(data_hi >> 8);
617 	alu->port_forward =
618 		(data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >>
619 			shifts[STATIC_MAC_FWD_PORTS];
620 	alu->is_override = (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0;
621 
622 	/* KSZ8795/KSZ8895 family switches have STATIC_MAC_TABLE_USE_FID and
623 	 * STATIC_MAC_TABLE_FID definitions off by 1 when doing read on the
624 	 * static MAC table compared to doing write.
625 	 */
626 	if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev))
627 		data_hi >>= 1;
628 	alu->is_static = true;
629 	alu->is_use_fid = (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0;
630 	alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >>
631 		shifts[STATIC_MAC_FID];
632 
633 	*valid = true;
634 
635 	return 0;
636 }
637 
ksz8_w_sta_mac_table(struct ksz_device * dev,u16 addr,struct alu_struct * alu)638 static int ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr,
639 				struct alu_struct *alu)
640 {
641 	u32 data_hi, data_lo;
642 	const u8 *shifts;
643 	const u32 *masks;
644 	u64 data;
645 
646 	shifts = dev->info->shifts;
647 	masks = dev->info->masks;
648 
649 	data_lo = ((u32)alu->mac[2] << 24) |
650 		((u32)alu->mac[3] << 16) |
651 		((u32)alu->mac[4] << 8) | alu->mac[5];
652 	data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1];
653 	data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS];
654 
655 	if (alu->is_override)
656 		data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE];
657 	if (alu->is_use_fid) {
658 		data_hi |= masks[STATIC_MAC_TABLE_USE_FID];
659 		data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID];
660 	}
661 	if (alu->is_static)
662 		data_hi |= masks[STATIC_MAC_TABLE_VALID];
663 	else
664 		data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE];
665 
666 	data = (u64)data_hi << 32 | data_lo;
667 
668 	return ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data);
669 }
670 
ksz8_from_vlan(struct ksz_device * dev,u32 vlan,u8 * fid,u8 * member,u8 * valid)671 static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid,
672 			   u8 *member, u8 *valid)
673 {
674 	const u8 *shifts;
675 	const u32 *masks;
676 
677 	shifts = dev->info->shifts;
678 	masks = dev->info->masks;
679 
680 	*fid = vlan & masks[VLAN_TABLE_FID];
681 	*member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >>
682 			shifts[VLAN_TABLE_MEMBERSHIP_S];
683 	*valid = !!(vlan & masks[VLAN_TABLE_VALID]);
684 }
685 
ksz8_to_vlan(struct ksz_device * dev,u8 fid,u8 member,u8 valid,u16 * vlan)686 static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid,
687 			 u16 *vlan)
688 {
689 	const u8 *shifts;
690 	const u32 *masks;
691 
692 	shifts = dev->info->shifts;
693 	masks = dev->info->masks;
694 
695 	*vlan = fid;
696 	*vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S];
697 	if (valid)
698 		*vlan |= masks[VLAN_TABLE_VALID];
699 }
700 
ksz8_r_vlan_entries(struct ksz_device * dev,u16 addr)701 static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr)
702 {
703 	const u8 *shifts;
704 	u64 data;
705 	int i;
706 
707 	shifts = dev->info->shifts;
708 
709 	ksz8_r_table(dev, TABLE_VLAN, addr, &data);
710 	addr *= 4;
711 	for (i = 0; i < 4; i++) {
712 		dev->vlan_cache[addr + i].table[0] = (u16)data;
713 		data >>= shifts[VLAN_TABLE];
714 	}
715 }
716 
ksz8_r_vlan_table(struct ksz_device * dev,u16 vid,u16 * vlan)717 static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan)
718 {
719 	int index;
720 	u16 *data;
721 	u16 addr;
722 	u64 buf;
723 
724 	data = (u16 *)&buf;
725 	addr = vid / 4;
726 	index = vid & 3;
727 	ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
728 	*vlan = data[index];
729 }
730 
ksz8_w_vlan_table(struct ksz_device * dev,u16 vid,u16 vlan)731 static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan)
732 {
733 	int index;
734 	u16 *data;
735 	u16 addr;
736 	u64 buf;
737 
738 	data = (u16 *)&buf;
739 	addr = vid / 4;
740 	index = vid & 3;
741 	ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
742 	data[index] = vlan;
743 	dev->vlan_cache[vid].table[0] = vlan;
744 	ksz8_w_table(dev, TABLE_VLAN, addr, buf);
745 }
746 
747 /**
748  * ksz879x_get_loopback - KSZ879x specific function to get loopback
749  *                        configuration status for a specific port
750  * @dev: Pointer to the device structure
751  * @port: Port number to query
752  * @val: Pointer to store the result
753  *
754  * This function reads the SMI registers to determine whether loopback mode
755  * is enabled for a specific port.
756  *
757  * Return: 0 on success, error code on failure.
758  */
ksz879x_get_loopback(struct ksz_device * dev,u16 port,u16 * val)759 static int ksz879x_get_loopback(struct ksz_device *dev, u16 port,
760 				u16 *val)
761 {
762 	u8 stat3;
763 	int ret;
764 
765 	ret = ksz_pread8(dev, port, REG_PORT_STATUS_3, &stat3);
766 	if (ret)
767 		return ret;
768 
769 	if (stat3 & PORT_PHY_LOOPBACK)
770 		*val |= BMCR_LOOPBACK;
771 
772 	return 0;
773 }
774 
775 /**
776  * ksz879x_set_loopback - KSZ879x specific function  to set loopback mode for
777  *			  a specific port
778  * @dev: Pointer to the device structure.
779  * @port: Port number to modify.
780  * @val: Value indicating whether to enable or disable loopback mode.
781  *
782  * This function translates loopback bit of the BMCR register into the
783  * corresponding hardware register bit value and writes it to the SMI interface.
784  *
785  * Return: 0 on success, error code on failure.
786  */
ksz879x_set_loopback(struct ksz_device * dev,u16 port,u16 val)787 static int ksz879x_set_loopback(struct ksz_device *dev, u16 port, u16 val)
788 {
789 	u8 stat3 = 0;
790 
791 	if (val & BMCR_LOOPBACK)
792 		stat3 |= PORT_PHY_LOOPBACK;
793 
794 	return ksz_prmw8(dev, port, REG_PORT_STATUS_3, PORT_PHY_LOOPBACK,
795 			 stat3);
796 }
797 
798 /**
799  * ksz8_r_phy_ctrl - Translates and reads from the SMI interface to a MIIM PHY
800  *		     Control register (Reg. 31).
801  * @dev: The KSZ device instance.
802  * @port: The port number to be read.
803  * @val: The value read from the SMI interface.
804  *
805  * This function reads the SMI interface and translates the hardware register
806  * bit values into their corresponding control settings for a MIIM PHY Control
807  * register.
808  *
809  * Return: 0 on success, error code on failure.
810  */
ksz8_r_phy_ctrl(struct ksz_device * dev,int port,u16 * val)811 static int ksz8_r_phy_ctrl(struct ksz_device *dev, int port, u16 *val)
812 {
813 	const u16 *regs = dev->info->regs;
814 	u8 reg_val;
815 	int ret;
816 
817 	*val = 0;
818 
819 	ret = ksz_pread8(dev, port, regs[P_LINK_STATUS], &reg_val);
820 	if (ret < 0)
821 		return ret;
822 
823 	if (reg_val & PORT_MDIX_STATUS)
824 		*val |= KSZ886X_CTRL_MDIX_STAT;
825 
826 	ret = ksz_pread8(dev, port, REG_PORT_LINK_MD_CTRL, &reg_val);
827 	if (ret < 0)
828 		return ret;
829 
830 	if (reg_val & PORT_FORCE_LINK)
831 		*val |= KSZ886X_CTRL_FORCE_LINK;
832 
833 	if (reg_val & PORT_POWER_SAVING)
834 		*val |= KSZ886X_CTRL_PWRSAVE;
835 
836 	if (reg_val & PORT_PHY_REMOTE_LOOPBACK)
837 		*val |= KSZ886X_CTRL_REMOTE_LOOPBACK;
838 
839 	return 0;
840 }
841 
842 /**
843  * ksz8_r_phy_bmcr - Translates and reads from the SMI interface to a MIIM PHY
844  *		     Basic mode control register (Reg. 0).
845  * @dev: The KSZ device instance.
846  * @port: The port number to be read.
847  * @val: The value read from the SMI interface.
848  *
849  * This function reads the SMI interface and translates the hardware register
850  * bit values into their corresponding control settings for a MIIM PHY Basic
851  * mode control register.
852  *
853  * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873
854  * -------------------------------------------------------------------
855  * MIIM Bit                    | KSZ8794 Reg/Bit             | KSZ8873 Reg/Bit
856  * ----------------------------+-----------------------------+----------------
857  * Bit 15 - Soft Reset         | 0xF/4                       | Not supported
858  * Bit 14 - Loopback           | 0xD/0 (MAC), 0xF/7 (PHY)    ~ 0xD/0 (PHY)
859  * Bit 13 - Force 100          | 0xC/6                       = 0xC/6
860  * Bit 12 - AN Enable          | 0xC/7 (reverse logic)       ~ 0xC/7
861  * Bit 11 - Power Down         | 0xD/3                       = 0xD/3
862  * Bit 10 - PHY Isolate        | 0xF/5                       | Not supported
863  * Bit 9 - Restart AN          | 0xD/5                       = 0xD/5
864  * Bit 8 - Force Full-Duplex   | 0xC/5                       = 0xC/5
865  * Bit 7 - Collision Test/Res. | Not supported               | Not supported
866  * Bit 6 - Reserved            | Not supported               | Not supported
867  * Bit 5 - Hp_mdix             | 0x9/7                       ~ 0xF/7
868  * Bit 4 - Force MDI           | 0xD/1                       = 0xD/1
869  * Bit 3 - Disable MDIX        | 0xD/2                       = 0xD/2
870  * Bit 2 - Disable Far-End F.  | ????                        | 0xD/4
871  * Bit 1 - Disable Transmit    | 0xD/6                       = 0xD/6
872  * Bit 0 - Disable LED         | 0xD/7                       = 0xD/7
873  * -------------------------------------------------------------------
874  *
875  * Return: 0 on success, error code on failure.
876  */
ksz8_r_phy_bmcr(struct ksz_device * dev,u16 port,u16 * val)877 static int ksz8_r_phy_bmcr(struct ksz_device *dev, u16 port, u16 *val)
878 {
879 	const u16 *regs = dev->info->regs;
880 	u8 restart, speed, ctrl;
881 	int ret;
882 
883 	*val = 0;
884 
885 	ret = ksz_pread8(dev, port, regs[P_NEG_RESTART_CTRL], &restart);
886 	if (ret)
887 		return ret;
888 
889 	ret = ksz_pread8(dev, port, regs[P_SPEED_STATUS], &speed);
890 	if (ret)
891 		return ret;
892 
893 	ret = ksz_pread8(dev, port, regs[P_FORCE_CTRL], &ctrl);
894 	if (ret)
895 		return ret;
896 
897 	if (ctrl & PORT_FORCE_100_MBIT)
898 		*val |= BMCR_SPEED100;
899 
900 	if (ksz_is_ksz88x3(dev)) {
901 		if (restart & KSZ8873_PORT_PHY_LOOPBACK)
902 			*val |= BMCR_LOOPBACK;
903 
904 		if ((ctrl & PORT_AUTO_NEG_ENABLE))
905 			*val |= BMCR_ANENABLE;
906 	} else {
907 		ret = ksz879x_get_loopback(dev, port, val);
908 		if (ret)
909 			return ret;
910 
911 		if (!(ctrl & PORT_AUTO_NEG_DISABLE))
912 			*val |= BMCR_ANENABLE;
913 	}
914 
915 	if (restart & PORT_POWER_DOWN)
916 		*val |= BMCR_PDOWN;
917 
918 	if (restart & PORT_AUTO_NEG_RESTART)
919 		*val |= BMCR_ANRESTART;
920 
921 	if (ctrl & PORT_FORCE_FULL_DUPLEX)
922 		*val |= BMCR_FULLDPLX;
923 
924 	if (speed & PORT_HP_MDIX)
925 		*val |= KSZ886X_BMCR_HP_MDIX;
926 
927 	if (restart & PORT_FORCE_MDIX)
928 		*val |= KSZ886X_BMCR_FORCE_MDI;
929 
930 	if (restart & PORT_AUTO_MDIX_DISABLE)
931 		*val |= KSZ886X_BMCR_DISABLE_AUTO_MDIX;
932 
933 	if (restart & PORT_TX_DISABLE)
934 		*val |= KSZ886X_BMCR_DISABLE_TRANSMIT;
935 
936 	if (restart & PORT_LED_OFF)
937 		*val |= KSZ886X_BMCR_DISABLE_LED;
938 
939 	return 0;
940 }
941 
ksz8_r_phy(struct ksz_device * dev,u16 phy,u16 reg,u16 * val)942 int ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
943 {
944 	u8 ctrl, link, val1, val2;
945 	int processed = true;
946 	const u16 *regs;
947 	u16 data = 0;
948 	u16 p = phy;
949 	int ret;
950 
951 	regs = dev->info->regs;
952 
953 	switch (reg) {
954 	case MII_BMCR:
955 		ret = ksz8_r_phy_bmcr(dev, p, &data);
956 		if (ret)
957 			return ret;
958 		break;
959 	case MII_BMSR:
960 		ret = ksz_pread8(dev, p, regs[P_LINK_STATUS], &link);
961 		if (ret)
962 			return ret;
963 
964 		data = BMSR_100FULL |
965 		       BMSR_100HALF |
966 		       BMSR_10FULL |
967 		       BMSR_10HALF |
968 		       BMSR_ANEGCAPABLE;
969 		if (link & PORT_AUTO_NEG_COMPLETE)
970 			data |= BMSR_ANEGCOMPLETE;
971 		if (link & PORT_STAT_LINK_GOOD)
972 			data |= BMSR_LSTATUS;
973 		break;
974 	case MII_PHYSID1:
975 		data = KSZ8795_ID_HI;
976 		break;
977 	case MII_PHYSID2:
978 		if (ksz_is_ksz88x3(dev))
979 			data = KSZ8863_ID_LO;
980 		else
981 			data = KSZ8795_ID_LO;
982 		break;
983 	case MII_ADVERTISE:
984 		ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
985 		if (ret)
986 			return ret;
987 
988 		data = ADVERTISE_CSMA;
989 		if (ctrl & PORT_AUTO_NEG_SYM_PAUSE)
990 			data |= ADVERTISE_PAUSE_CAP;
991 		if (ctrl & PORT_AUTO_NEG_100BTX_FD)
992 			data |= ADVERTISE_100FULL;
993 		if (ctrl & PORT_AUTO_NEG_100BTX)
994 			data |= ADVERTISE_100HALF;
995 		if (ctrl & PORT_AUTO_NEG_10BT_FD)
996 			data |= ADVERTISE_10FULL;
997 		if (ctrl & PORT_AUTO_NEG_10BT)
998 			data |= ADVERTISE_10HALF;
999 		break;
1000 	case MII_LPA:
1001 		ret = ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link);
1002 		if (ret)
1003 			return ret;
1004 
1005 		data = LPA_SLCT;
1006 		if (link & PORT_REMOTE_SYM_PAUSE)
1007 			data |= LPA_PAUSE_CAP;
1008 		if (link & PORT_REMOTE_100BTX_FD)
1009 			data |= LPA_100FULL;
1010 		if (link & PORT_REMOTE_100BTX)
1011 			data |= LPA_100HALF;
1012 		if (link & PORT_REMOTE_10BT_FD)
1013 			data |= LPA_10FULL;
1014 		if (link & PORT_REMOTE_10BT)
1015 			data |= LPA_10HALF;
1016 		if (data & ~LPA_SLCT)
1017 			data |= LPA_LPACK;
1018 		break;
1019 	case PHY_REG_LINK_MD:
1020 		ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1);
1021 		if (ret)
1022 			return ret;
1023 
1024 		ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2);
1025 		if (ret)
1026 			return ret;
1027 
1028 		if (val1 & PORT_START_CABLE_DIAG)
1029 			data |= PHY_START_CABLE_DIAG;
1030 
1031 		if (val1 & PORT_CABLE_10M_SHORT)
1032 			data |= PHY_CABLE_10M_SHORT;
1033 
1034 		data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M,
1035 				FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1));
1036 
1037 		data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M,
1038 				(FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) |
1039 				FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2));
1040 		break;
1041 	case PHY_REG_PHY_CTRL:
1042 		ret = ksz8_r_phy_ctrl(dev, p, &data);
1043 		if (ret)
1044 			return ret;
1045 
1046 		break;
1047 	default:
1048 		processed = false;
1049 		break;
1050 	}
1051 	if (processed)
1052 		*val = data;
1053 
1054 	return 0;
1055 }
1056 
1057 /**
1058  * ksz8_w_phy_ctrl - Translates and writes to the SMI interface from a MIIM PHY
1059  *		     Control register (Reg. 31).
1060  * @dev: The KSZ device instance.
1061  * @port: The port number to be configured.
1062  * @val: The register value to be written.
1063  *
1064  * This function translates control settings from a MIIM PHY Control register
1065  * into their corresponding hardware register bit values for the SMI
1066  * interface.
1067  *
1068  * Return: 0 on success, error code on failure.
1069  */
ksz8_w_phy_ctrl(struct ksz_device * dev,int port,u16 val)1070 static int ksz8_w_phy_ctrl(struct ksz_device *dev, int port, u16 val)
1071 {
1072 	u8 reg_val = 0;
1073 	int ret;
1074 
1075 	if (val & KSZ886X_CTRL_FORCE_LINK)
1076 		reg_val |= PORT_FORCE_LINK;
1077 
1078 	if (val & KSZ886X_CTRL_PWRSAVE)
1079 		reg_val |= PORT_POWER_SAVING;
1080 
1081 	if (val & KSZ886X_CTRL_REMOTE_LOOPBACK)
1082 		reg_val |= PORT_PHY_REMOTE_LOOPBACK;
1083 
1084 	ret = ksz_prmw8(dev, port, REG_PORT_LINK_MD_CTRL, PORT_FORCE_LINK |
1085 			PORT_POWER_SAVING | PORT_PHY_REMOTE_LOOPBACK, reg_val);
1086 	return ret;
1087 }
1088 
1089 /**
1090  * ksz8_w_phy_bmcr - Translates and writes to the SMI interface from a MIIM PHY
1091  *		     Basic mode control register (Reg. 0).
1092  * @dev: The KSZ device instance.
1093  * @port: The port number to be configured.
1094  * @val: The register value to be written.
1095  *
1096  * This function translates control settings from a MIIM PHY Basic mode control
1097  * register into their corresponding hardware register bit values for the SMI
1098  * interface.
1099  *
1100  * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873
1101  * -------------------------------------------------------------------
1102  * MIIM Bit                    | KSZ8794 Reg/Bit             | KSZ8873 Reg/Bit
1103  * ----------------------------+-----------------------------+----------------
1104  * Bit 15 - Soft Reset         | 0xF/4                       | Not supported
1105  * Bit 14 - Loopback           | 0xD/0 (MAC), 0xF/7 (PHY)    ~ 0xD/0 (PHY)
1106  * Bit 13 - Force 100          | 0xC/6                       = 0xC/6
1107  * Bit 12 - AN Enable          | 0xC/7 (reverse logic)       ~ 0xC/7
1108  * Bit 11 - Power Down         | 0xD/3                       = 0xD/3
1109  * Bit 10 - PHY Isolate        | 0xF/5                       | Not supported
1110  * Bit 9 - Restart AN          | 0xD/5                       = 0xD/5
1111  * Bit 8 - Force Full-Duplex   | 0xC/5                       = 0xC/5
1112  * Bit 7 - Collision Test/Res. | Not supported               | Not supported
1113  * Bit 6 - Reserved            | Not supported               | Not supported
1114  * Bit 5 - Hp_mdix             | 0x9/7                       ~ 0xF/7
1115  * Bit 4 - Force MDI           | 0xD/1                       = 0xD/1
1116  * Bit 3 - Disable MDIX        | 0xD/2                       = 0xD/2
1117  * Bit 2 - Disable Far-End F.  | ????                        | 0xD/4
1118  * Bit 1 - Disable Transmit    | 0xD/6                       = 0xD/6
1119  * Bit 0 - Disable LED         | 0xD/7                       = 0xD/7
1120  * -------------------------------------------------------------------
1121  *
1122  * Return: 0 on success, error code on failure.
1123  */
ksz8_w_phy_bmcr(struct ksz_device * dev,u16 port,u16 val)1124 static int ksz8_w_phy_bmcr(struct ksz_device *dev, u16 port, u16 val)
1125 {
1126 	u8 restart, speed, ctrl, restart_mask;
1127 	const u16 *regs = dev->info->regs;
1128 	int ret;
1129 
1130 	/* Do not support PHY reset function. */
1131 	if (val & BMCR_RESET)
1132 		return 0;
1133 
1134 	speed = 0;
1135 	if (val & KSZ886X_BMCR_HP_MDIX)
1136 		speed |= PORT_HP_MDIX;
1137 
1138 	ret = ksz_prmw8(dev, port, regs[P_SPEED_STATUS], PORT_HP_MDIX, speed);
1139 	if (ret)
1140 		return ret;
1141 
1142 	ctrl = 0;
1143 	if (ksz_is_ksz88x3(dev)) {
1144 		if ((val & BMCR_ANENABLE))
1145 			ctrl |= PORT_AUTO_NEG_ENABLE;
1146 	} else {
1147 		if (!(val & BMCR_ANENABLE))
1148 			ctrl |= PORT_AUTO_NEG_DISABLE;
1149 
1150 		/* Fiber port does not support auto-negotiation. */
1151 		if (dev->ports[port].fiber)
1152 			ctrl |= PORT_AUTO_NEG_DISABLE;
1153 	}
1154 
1155 	if (val & BMCR_SPEED100)
1156 		ctrl |= PORT_FORCE_100_MBIT;
1157 
1158 	if (val & BMCR_FULLDPLX)
1159 		ctrl |= PORT_FORCE_FULL_DUPLEX;
1160 
1161 	ret = ksz_prmw8(dev, port, regs[P_FORCE_CTRL], PORT_FORCE_100_MBIT |
1162 		 /* PORT_AUTO_NEG_ENABLE and PORT_AUTO_NEG_DISABLE are the same
1163 		  * bits
1164 		  */
1165 		 PORT_FORCE_FULL_DUPLEX | PORT_AUTO_NEG_ENABLE, ctrl);
1166 	if (ret)
1167 		return ret;
1168 
1169 	restart = 0;
1170 	restart_mask = PORT_LED_OFF | PORT_TX_DISABLE | PORT_AUTO_NEG_RESTART |
1171 		PORT_POWER_DOWN | PORT_AUTO_MDIX_DISABLE | PORT_FORCE_MDIX;
1172 
1173 	if (val & KSZ886X_BMCR_DISABLE_LED)
1174 		restart |= PORT_LED_OFF;
1175 
1176 	if (val & KSZ886X_BMCR_DISABLE_TRANSMIT)
1177 		restart |= PORT_TX_DISABLE;
1178 
1179 	if (val & BMCR_ANRESTART)
1180 		restart |= PORT_AUTO_NEG_RESTART;
1181 
1182 	if (val & BMCR_PDOWN)
1183 		restart |= PORT_POWER_DOWN;
1184 
1185 	if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX)
1186 		restart |= PORT_AUTO_MDIX_DISABLE;
1187 
1188 	if (val & KSZ886X_BMCR_FORCE_MDI)
1189 		restart |= PORT_FORCE_MDIX;
1190 
1191 	if (ksz_is_ksz88x3(dev)) {
1192 		restart_mask |= KSZ8873_PORT_PHY_LOOPBACK;
1193 
1194 		if (val & BMCR_LOOPBACK)
1195 			restart |= KSZ8873_PORT_PHY_LOOPBACK;
1196 	} else {
1197 		ret = ksz879x_set_loopback(dev, port, val);
1198 		if (ret)
1199 			return ret;
1200 	}
1201 
1202 	return ksz_prmw8(dev, port, regs[P_NEG_RESTART_CTRL], restart_mask,
1203 			 restart);
1204 }
1205 
ksz8_w_phy(struct ksz_device * dev,u16 phy,u16 reg,u16 val)1206 int ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
1207 {
1208 	const u16 *regs;
1209 	u8 ctrl, data;
1210 	u16 p = phy;
1211 	int ret;
1212 
1213 	regs = dev->info->regs;
1214 
1215 	switch (reg) {
1216 	case MII_BMCR:
1217 		ret = ksz8_w_phy_bmcr(dev, p, val);
1218 		if (ret)
1219 			return ret;
1220 		break;
1221 	case MII_ADVERTISE:
1222 		ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
1223 		if (ret)
1224 			return ret;
1225 
1226 		data = ctrl;
1227 		data &= ~(PORT_AUTO_NEG_SYM_PAUSE |
1228 			  PORT_AUTO_NEG_100BTX_FD |
1229 			  PORT_AUTO_NEG_100BTX |
1230 			  PORT_AUTO_NEG_10BT_FD |
1231 			  PORT_AUTO_NEG_10BT);
1232 		if (val & ADVERTISE_PAUSE_CAP)
1233 			data |= PORT_AUTO_NEG_SYM_PAUSE;
1234 		if (val & ADVERTISE_100FULL)
1235 			data |= PORT_AUTO_NEG_100BTX_FD;
1236 		if (val & ADVERTISE_100HALF)
1237 			data |= PORT_AUTO_NEG_100BTX;
1238 		if (val & ADVERTISE_10FULL)
1239 			data |= PORT_AUTO_NEG_10BT_FD;
1240 		if (val & ADVERTISE_10HALF)
1241 			data |= PORT_AUTO_NEG_10BT;
1242 
1243 		if (data != ctrl) {
1244 			ret = ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data);
1245 			if (ret)
1246 				return ret;
1247 		}
1248 		break;
1249 	case PHY_REG_LINK_MD:
1250 		if (val & PHY_START_CABLE_DIAG)
1251 			ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true);
1252 		break;
1253 
1254 	case PHY_REG_PHY_CTRL:
1255 		ret = ksz8_w_phy_ctrl(dev, p, val);
1256 		if (ret)
1257 			return ret;
1258 		break;
1259 	default:
1260 		break;
1261 	}
1262 
1263 	return 0;
1264 }
1265 
ksz8_cfg_port_member(struct ksz_device * dev,int port,u8 member)1266 void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member)
1267 {
1268 	u8 data;
1269 
1270 	ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1271 	data &= ~PORT_VLAN_MEMBERSHIP;
1272 	data |= (member & dev->port_mask);
1273 	ksz_pwrite8(dev, port, P_MIRROR_CTRL, data);
1274 }
1275 
ksz8_flush_dyn_mac_table(struct ksz_device * dev,int port)1276 void ksz8_flush_dyn_mac_table(struct ksz_device *dev, int port)
1277 {
1278 	u8 learn[DSA_MAX_PORTS];
1279 	int first, index, cnt;
1280 	const u16 *regs;
1281 
1282 	regs = dev->info->regs;
1283 
1284 	if ((uint)port < dev->info->port_cnt) {
1285 		first = port;
1286 		cnt = port + 1;
1287 	} else {
1288 		/* Flush all ports. */
1289 		first = 0;
1290 		cnt = dev->info->port_cnt;
1291 	}
1292 	for (index = first; index < cnt; index++) {
1293 		ksz_pread8(dev, index, regs[P_STP_CTRL], &learn[index]);
1294 		if (!(learn[index] & PORT_LEARN_DISABLE))
1295 			ksz_pwrite8(dev, index, regs[P_STP_CTRL],
1296 				    learn[index] | PORT_LEARN_DISABLE);
1297 	}
1298 	ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
1299 	for (index = first; index < cnt; index++) {
1300 		if (!(learn[index] & PORT_LEARN_DISABLE))
1301 			ksz_pwrite8(dev, index, regs[P_STP_CTRL], learn[index]);
1302 	}
1303 }
1304 
ksz8_fdb_dump(struct ksz_device * dev,int port,dsa_fdb_dump_cb_t * cb,void * data)1305 int ksz8_fdb_dump(struct ksz_device *dev, int port,
1306 		  dsa_fdb_dump_cb_t *cb, void *data)
1307 {
1308 	u8 mac[ETH_ALEN];
1309 	u8 src_port, fid;
1310 	u16 entries = 0;
1311 	int ret, i;
1312 
1313 	for (i = 0; i < KSZ8_DYN_MAC_ENTRIES; i++) {
1314 		ret = ksz8_r_dyn_mac_table(dev, i, mac, &fid, &src_port,
1315 					   &entries);
1316 		if (ret)
1317 			return ret;
1318 
1319 		if (i >= entries)
1320 			return 0;
1321 
1322 		if (port == src_port) {
1323 			ret = cb(mac, fid, false, data);
1324 			if (ret)
1325 				return ret;
1326 		}
1327 	}
1328 
1329 	return 0;
1330 }
1331 
ksz8_add_sta_mac(struct ksz_device * dev,int port,const unsigned char * addr,u16 vid)1332 static int ksz8_add_sta_mac(struct ksz_device *dev, int port,
1333 			    const unsigned char *addr, u16 vid)
1334 {
1335 	struct alu_struct alu;
1336 	int index, ret;
1337 	int empty = 0;
1338 
1339 	alu.port_forward = 0;
1340 	for (index = 0; index < dev->info->num_statics; index++) {
1341 		bool valid;
1342 
1343 		ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid);
1344 		if (ret)
1345 			return ret;
1346 		if (!valid) {
1347 			/* Remember the first empty entry. */
1348 			if (!empty)
1349 				empty = index + 1;
1350 			continue;
1351 		}
1352 
1353 		if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid)
1354 			break;
1355 	}
1356 
1357 	/* no available entry */
1358 	if (index == dev->info->num_statics && !empty)
1359 		return -ENOSPC;
1360 
1361 	/* add entry */
1362 	if (index == dev->info->num_statics) {
1363 		index = empty - 1;
1364 		memset(&alu, 0, sizeof(alu));
1365 		memcpy(alu.mac, addr, ETH_ALEN);
1366 		alu.is_static = true;
1367 	}
1368 	alu.port_forward |= BIT(port);
1369 	if (vid) {
1370 		alu.is_use_fid = true;
1371 
1372 		/* Need a way to map VID to FID. */
1373 		alu.fid = vid;
1374 	}
1375 
1376 	return ksz8_w_sta_mac_table(dev, index, &alu);
1377 }
1378 
ksz8_del_sta_mac(struct ksz_device * dev,int port,const unsigned char * addr,u16 vid)1379 static int ksz8_del_sta_mac(struct ksz_device *dev, int port,
1380 			    const unsigned char *addr, u16 vid)
1381 {
1382 	struct alu_struct alu;
1383 	int index, ret;
1384 
1385 	for (index = 0; index < dev->info->num_statics; index++) {
1386 		bool valid;
1387 
1388 		ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid);
1389 		if (ret)
1390 			return ret;
1391 		if (!valid)
1392 			continue;
1393 
1394 		if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid)
1395 			break;
1396 	}
1397 
1398 	/* no available entry */
1399 	if (index == dev->info->num_statics)
1400 		return 0;
1401 
1402 	/* clear port */
1403 	alu.port_forward &= ~BIT(port);
1404 	if (!alu.port_forward)
1405 		alu.is_static = false;
1406 
1407 	return ksz8_w_sta_mac_table(dev, index, &alu);
1408 }
1409 
ksz8_mdb_add(struct ksz_device * dev,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1410 int ksz8_mdb_add(struct ksz_device *dev, int port,
1411 		 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db)
1412 {
1413 	return ksz8_add_sta_mac(dev, port, mdb->addr, mdb->vid);
1414 }
1415 
ksz8_mdb_del(struct ksz_device * dev,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1416 int ksz8_mdb_del(struct ksz_device *dev, int port,
1417 		 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db)
1418 {
1419 	return ksz8_del_sta_mac(dev, port, mdb->addr, mdb->vid);
1420 }
1421 
ksz8_fdb_add(struct ksz_device * dev,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1422 int ksz8_fdb_add(struct ksz_device *dev, int port, const unsigned char *addr,
1423 		 u16 vid, struct dsa_db db)
1424 {
1425 	return ksz8_add_sta_mac(dev, port, addr, vid);
1426 }
1427 
ksz8_fdb_del(struct ksz_device * dev,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1428 int ksz8_fdb_del(struct ksz_device *dev, int port, const unsigned char *addr,
1429 		 u16 vid, struct dsa_db db)
1430 {
1431 	return ksz8_del_sta_mac(dev, port, addr, vid);
1432 }
1433 
ksz8_port_vlan_filtering(struct ksz_device * dev,int port,bool flag,struct netlink_ext_ack * extack)1434 int ksz8_port_vlan_filtering(struct ksz_device *dev, int port, bool flag,
1435 			     struct netlink_ext_ack *extack)
1436 {
1437 	if (ksz_is_ksz88x3(dev))
1438 		return -ENOTSUPP;
1439 
1440 	/* Discard packets with VID not enabled on the switch */
1441 	ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag);
1442 
1443 	/* Discard packets with VID not enabled on the ingress port */
1444 	for (port = 0; port < dev->phy_port_cnt; ++port)
1445 		ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER,
1446 			     flag);
1447 
1448 	return 0;
1449 }
1450 
ksz8_port_enable_pvid(struct ksz_device * dev,int port,bool state)1451 static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state)
1452 {
1453 	if (ksz_is_ksz88x3(dev)) {
1454 		ksz_cfg(dev, REG_SW_INSERT_SRC_PVID,
1455 			0x03 << (4 - 2 * port), state);
1456 	} else {
1457 		ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00);
1458 	}
1459 }
1460 
ksz8_port_vlan_add(struct ksz_device * dev,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)1461 int ksz8_port_vlan_add(struct ksz_device *dev, int port,
1462 		       const struct switchdev_obj_port_vlan *vlan,
1463 		       struct netlink_ext_ack *extack)
1464 {
1465 	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1466 	struct ksz_port *p = &dev->ports[port];
1467 	u16 data, new_pvid = 0;
1468 	u8 fid, member, valid;
1469 
1470 	if (ksz_is_ksz88x3(dev))
1471 		return -ENOTSUPP;
1472 
1473 	/* If a VLAN is added with untagged flag different from the
1474 	 * port's Remove Tag flag, we need to change the latter.
1475 	 * Ignore VID 0, which is always untagged.
1476 	 * Ignore CPU port, which will always be tagged.
1477 	 */
1478 	if (untagged != p->remove_tag && vlan->vid != 0 &&
1479 	    port != dev->cpu_port) {
1480 		unsigned int vid;
1481 
1482 		/* Reject attempts to add a VLAN that requires the
1483 		 * Remove Tag flag to be changed, unless there are no
1484 		 * other VLANs currently configured.
1485 		 */
1486 		for (vid = 1; vid < dev->info->num_vlans; ++vid) {
1487 			/* Skip the VID we are going to add or reconfigure */
1488 			if (vid == vlan->vid)
1489 				continue;
1490 
1491 			ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0],
1492 				       &fid, &member, &valid);
1493 			if (valid && (member & BIT(port)))
1494 				return -EINVAL;
1495 		}
1496 
1497 		ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged);
1498 		p->remove_tag = untagged;
1499 	}
1500 
1501 	ksz8_r_vlan_table(dev, vlan->vid, &data);
1502 	ksz8_from_vlan(dev, data, &fid, &member, &valid);
1503 
1504 	/* First time to setup the VLAN entry. */
1505 	if (!valid) {
1506 		/* Need to find a way to map VID to FID. */
1507 		fid = 1;
1508 		valid = 1;
1509 	}
1510 	member |= BIT(port);
1511 
1512 	ksz8_to_vlan(dev, fid, member, valid, &data);
1513 	ksz8_w_vlan_table(dev, vlan->vid, data);
1514 
1515 	/* change PVID */
1516 	if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1517 		new_pvid = vlan->vid;
1518 
1519 	if (new_pvid) {
1520 		u16 vid;
1521 
1522 		ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid);
1523 		vid &= ~VLAN_VID_MASK;
1524 		vid |= new_pvid;
1525 		ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid);
1526 
1527 		ksz8_port_enable_pvid(dev, port, true);
1528 	}
1529 
1530 	return 0;
1531 }
1532 
ksz8_port_vlan_del(struct ksz_device * dev,int port,const struct switchdev_obj_port_vlan * vlan)1533 int ksz8_port_vlan_del(struct ksz_device *dev, int port,
1534 		       const struct switchdev_obj_port_vlan *vlan)
1535 {
1536 	u16 data, pvid;
1537 	u8 fid, member, valid;
1538 
1539 	if (ksz_is_ksz88x3(dev))
1540 		return -ENOTSUPP;
1541 
1542 	ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid);
1543 	pvid = pvid & 0xFFF;
1544 
1545 	ksz8_r_vlan_table(dev, vlan->vid, &data);
1546 	ksz8_from_vlan(dev, data, &fid, &member, &valid);
1547 
1548 	member &= ~BIT(port);
1549 
1550 	/* Invalidate the entry if no more member. */
1551 	if (!member) {
1552 		fid = 0;
1553 		valid = 0;
1554 	}
1555 
1556 	ksz8_to_vlan(dev, fid, member, valid, &data);
1557 	ksz8_w_vlan_table(dev, vlan->vid, data);
1558 
1559 	if (pvid == vlan->vid)
1560 		ksz8_port_enable_pvid(dev, port, false);
1561 
1562 	return 0;
1563 }
1564 
ksz8_port_mirror_add(struct ksz_device * dev,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)1565 int ksz8_port_mirror_add(struct ksz_device *dev, int port,
1566 			 struct dsa_mall_mirror_tc_entry *mirror,
1567 			 bool ingress, struct netlink_ext_ack *extack)
1568 {
1569 	if (ingress) {
1570 		ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
1571 		dev->mirror_rx |= BIT(port);
1572 	} else {
1573 		ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
1574 		dev->mirror_tx |= BIT(port);
1575 	}
1576 
1577 	ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
1578 
1579 	/* configure mirror port */
1580 	if (dev->mirror_rx || dev->mirror_tx)
1581 		ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1582 			     PORT_MIRROR_SNIFFER, true);
1583 
1584 	return 0;
1585 }
1586 
ksz8_port_mirror_del(struct ksz_device * dev,int port,struct dsa_mall_mirror_tc_entry * mirror)1587 void ksz8_port_mirror_del(struct ksz_device *dev, int port,
1588 			  struct dsa_mall_mirror_tc_entry *mirror)
1589 {
1590 	u8 data;
1591 
1592 	if (mirror->ingress) {
1593 		ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
1594 		dev->mirror_rx &= ~BIT(port);
1595 	} else {
1596 		ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
1597 		dev->mirror_tx &= ~BIT(port);
1598 	}
1599 
1600 	ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1601 
1602 	if (!dev->mirror_rx && !dev->mirror_tx)
1603 		ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1604 			     PORT_MIRROR_SNIFFER, false);
1605 }
1606 
ksz8795_cpu_interface_select(struct ksz_device * dev,int port)1607 static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
1608 {
1609 	struct ksz_port *p = &dev->ports[port];
1610 
1611 	if (!ksz_is_ksz87xx(dev))
1612 		return;
1613 
1614 	if (!p->interface && dev->compat_interface) {
1615 		dev_warn(dev->dev,
1616 			 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
1617 			 "Please update your device tree.\n",
1618 			 port);
1619 		p->interface = dev->compat_interface;
1620 	}
1621 }
1622 
ksz8_port_setup(struct ksz_device * dev,int port,bool cpu_port)1623 void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)
1624 {
1625 	const u16 *regs = dev->info->regs;
1626 	struct dsa_switch *ds = dev->ds;
1627 	const u32 *masks;
1628 	int queues;
1629 	u8 member;
1630 
1631 	masks = dev->info->masks;
1632 
1633 	/* enable broadcast storm limit */
1634 	ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
1635 
1636 	/* For KSZ88x3 enable only one queue by default, otherwise we won't
1637 	 * be able to get rid of PCP prios on Port 2.
1638 	 */
1639 	if (ksz_is_ksz88x3(dev))
1640 		queues = 1;
1641 	else
1642 		queues = dev->info->num_tx_queues;
1643 
1644 	ksz8_port_queue_split(dev, port, queues);
1645 
1646 	/* replace priority */
1647 	ksz_port_cfg(dev, port, P_802_1P_CTRL,
1648 		     masks[PORT_802_1P_REMAPPING], false);
1649 
1650 	if (cpu_port)
1651 		member = dsa_user_ports(ds);
1652 	else
1653 		member = BIT(dsa_upstream_port(ds, port));
1654 
1655 	ksz8_cfg_port_member(dev, port, member);
1656 
1657 	/* Disable all WoL options by default. Otherwise
1658 	 * ksz_switch_macaddr_get/put logic will not work properly.
1659 	 * CPU port 4 has no WoL functionality.
1660 	 */
1661 	if (ksz_is_ksz87xx(dev) && !cpu_port)
1662 		ksz8_pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 0);
1663 }
1664 
ksz88x3_config_rmii_clk(struct ksz_device * dev)1665 static void ksz88x3_config_rmii_clk(struct ksz_device *dev)
1666 {
1667 	struct dsa_port *cpu_dp = dsa_to_port(dev->ds, dev->cpu_port);
1668 	bool rmii_clk_internal;
1669 
1670 	if (!ksz_is_ksz88x3(dev))
1671 		return;
1672 
1673 	rmii_clk_internal = of_property_read_bool(cpu_dp->dn,
1674 						  "microchip,rmii-clk-internal");
1675 
1676 	ksz_cfg(dev, KSZ88X3_REG_FVID_AND_HOST_MODE,
1677 		KSZ88X3_PORT3_RMII_CLK_INTERNAL, rmii_clk_internal);
1678 }
1679 
ksz8_config_cpu_port(struct dsa_switch * ds)1680 void ksz8_config_cpu_port(struct dsa_switch *ds)
1681 {
1682 	struct ksz_device *dev = ds->priv;
1683 	struct ksz_port *p;
1684 	const u32 *masks;
1685 	const u16 *regs;
1686 	u8 remote;
1687 	int i;
1688 
1689 	masks = dev->info->masks;
1690 	regs = dev->info->regs;
1691 
1692 	ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true);
1693 
1694 	ksz8_port_setup(dev, dev->cpu_port, true);
1695 
1696 	ksz8795_cpu_interface_select(dev, dev->cpu_port);
1697 	ksz88x3_config_rmii_clk(dev);
1698 
1699 	for (i = 0; i < dev->phy_port_cnt; i++) {
1700 		ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1701 	}
1702 	for (i = 0; i < dev->phy_port_cnt; i++) {
1703 		p = &dev->ports[i];
1704 
1705 		/* For KSZ8795 family. */
1706 		if (ksz_is_ksz87xx(dev)) {
1707 			ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote);
1708 			if (remote & KSZ8_PORT_FIBER_MODE)
1709 				p->fiber = 1;
1710 		}
1711 		if (p->fiber)
1712 			ksz_port_cfg(dev, i, regs[P_STP_CTRL],
1713 				     PORT_FORCE_FLOW_CTRL, true);
1714 		else
1715 			ksz_port_cfg(dev, i, regs[P_STP_CTRL],
1716 				     PORT_FORCE_FLOW_CTRL, false);
1717 	}
1718 }
1719 
1720 /**
1721  * ksz8_phy_port_link_up - Configures ports with integrated PHYs
1722  * @dev: The KSZ device instance.
1723  * @port: The port number to configure.
1724  * @duplex: The desired duplex mode.
1725  * @tx_pause: If true, enables transmit pause.
1726  * @rx_pause: If true, enables receive pause.
1727  *
1728  * Description:
1729  * The function configures flow control settings for a given port based on the
1730  * desired settings and current duplex mode.
1731  *
1732  * According to the KSZ8873 datasheet, the PORT_FORCE_FLOW_CTRL bit in the
1733  * Port Control 2 register (0x1A for Port 1, 0x22 for Port 2, 0x32 for Port 3)
1734  * determines how flow control is handled on the port:
1735  *    "1 = will always enable full-duplex flow control on the port, regardless
1736  *         of AN result.
1737  *     0 = full-duplex flow control is enabled based on AN result."
1738  *
1739  * This means that the flow control behavior depends on the state of this bit:
1740  * - If PORT_FORCE_FLOW_CTRL is set to 1, the switch will ignore AN results and
1741  *   force flow control on the port.
1742  * - If PORT_FORCE_FLOW_CTRL is set to 0, the switch will enable or disable
1743  *   flow control based on the AN results.
1744  *
1745  * However, there is a potential limitation in this configuration. It is
1746  * currently not possible to force disable flow control on a port if we still
1747  * advertise pause support. While such a configuration is not currently
1748  * supported by Linux, and may not make practical sense, it's important to be
1749  * aware of this limitation when working with the KSZ8873 and similar devices.
1750  */
ksz8_phy_port_link_up(struct ksz_device * dev,int port,int duplex,bool tx_pause,bool rx_pause)1751 static void ksz8_phy_port_link_up(struct ksz_device *dev, int port, int duplex,
1752 				  bool tx_pause, bool rx_pause)
1753 {
1754 	const u16 *regs = dev->info->regs;
1755 	u8 sctrl = 0;
1756 
1757 	/* The KSZ8795 switch differs from the KSZ8873 by supporting
1758 	 * asymmetric pause control. However, since a single bit is used to
1759 	 * control both RX and TX pause, we can't enforce asymmetric pause
1760 	 * control - both TX and RX pause will be either enabled or disabled
1761 	 * together.
1762 	 *
1763 	 * If auto-negotiation is enabled, we usually allow the flow control to
1764 	 * be determined by the auto-negotiation process based on the
1765 	 * capabilities of both link partners. However, for KSZ8873, the
1766 	 * PORT_FORCE_FLOW_CTRL bit may be set by the hardware bootstrap,
1767 	 * ignoring the auto-negotiation result. Thus, even in auto-negotiation
1768 	 * mode, we need to ensure that the PORT_FORCE_FLOW_CTRL bit is
1769 	 * properly cleared.
1770 	 *
1771 	 * In the absence of pause auto-negotiation, we will enforce symmetric
1772 	 * pause control for both variants of switches - KSZ8873 and KSZ8795.
1773 	 *
1774 	 * Autoneg Pause Autoneg      rx,tx	PORT_FORCE_FLOW_CTRL
1775 	 * 1		1		x	0
1776 	 * 0		1		x	0 (flow control probably disabled)
1777 	 * x		0		1	1 (flow control force enabled)
1778 	 * 1		0		0	0 (flow control still depends on
1779 	 *					   aneg result due to hardware)
1780 	 * 0		0		0	0 (flow control probably disabled)
1781 	 */
1782 	if (dev->ports[port].manual_flow && tx_pause)
1783 		sctrl |= PORT_FORCE_FLOW_CTRL;
1784 
1785 	ksz_prmw8(dev, port, regs[P_STP_CTRL], PORT_FORCE_FLOW_CTRL, sctrl);
1786 }
1787 
1788 /**
1789  * ksz8_cpu_port_link_up - Configures the CPU port of the switch.
1790  * @dev: The KSZ device instance.
1791  * @speed: The desired link speed.
1792  * @duplex: The desired duplex mode.
1793  * @tx_pause: If true, enables transmit pause.
1794  * @rx_pause: If true, enables receive pause.
1795  *
1796  * Description:
1797  * The function configures flow control and speed settings for the CPU
1798  * port of the switch based on the desired settings, current duplex mode, and
1799  * speed.
1800  */
ksz8_cpu_port_link_up(struct ksz_device * dev,int speed,int duplex,bool tx_pause,bool rx_pause)1801 static void ksz8_cpu_port_link_up(struct ksz_device *dev, int speed, int duplex,
1802 				  bool tx_pause, bool rx_pause)
1803 {
1804 	const u16 *regs = dev->info->regs;
1805 	u8 ctrl = 0;
1806 
1807 	/* SW_FLOW_CTRL, SW_HALF_DUPLEX, and SW_10_MBIT bits are bootstrappable
1808 	 * at least on KSZ8873. They can have different values depending on your
1809 	 * board setup.
1810 	 */
1811 	if (tx_pause || rx_pause)
1812 		ctrl |= SW_FLOW_CTRL;
1813 
1814 	if (duplex == DUPLEX_HALF)
1815 		ctrl |= SW_HALF_DUPLEX;
1816 
1817 	/* This hardware only supports SPEED_10 and SPEED_100. For SPEED_10
1818 	 * we need to set the SW_10_MBIT bit. Otherwise, we can leave it 0.
1819 	 */
1820 	if (speed == SPEED_10)
1821 		ctrl |= SW_10_MBIT;
1822 
1823 	ksz_rmw8(dev, regs[S_BROADCAST_CTRL], SW_HALF_DUPLEX | SW_FLOW_CTRL |
1824 		 SW_10_MBIT, ctrl);
1825 }
1826 
ksz8_phylink_mac_link_up(struct phylink_config * config,struct phy_device * phydev,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)1827 void ksz8_phylink_mac_link_up(struct phylink_config *config,
1828 			      struct phy_device *phydev, unsigned int mode,
1829 			      phy_interface_t interface, int speed, int duplex,
1830 			      bool tx_pause, bool rx_pause)
1831 {
1832 	struct dsa_port *dp = dsa_phylink_to_port(config);
1833 	struct ksz_device *dev = dp->ds->priv;
1834 	int port = dp->index;
1835 
1836 	/* If the port is the CPU port, apply special handling. Only the CPU
1837 	 * port is configured via global registers.
1838 	 */
1839 	if (dev->cpu_port == port)
1840 		ksz8_cpu_port_link_up(dev, speed, duplex, tx_pause, rx_pause);
1841 	else if (dev->info->internal_phy[port])
1842 		ksz8_phy_port_link_up(dev, port, duplex, tx_pause, rx_pause);
1843 }
1844 
ksz8_handle_global_errata(struct dsa_switch * ds)1845 static int ksz8_handle_global_errata(struct dsa_switch *ds)
1846 {
1847 	struct ksz_device *dev = ds->priv;
1848 	int ret = 0;
1849 
1850 	/* KSZ87xx Errata DS80000687C.
1851 	 * Module 2: Link drops with some EEE link partners.
1852 	 *   An issue with the EEE next page exchange between the
1853 	 *   KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in
1854 	 *   the link dropping.
1855 	 */
1856 	if (dev->info->ksz87xx_eee_link_erratum)
1857 		ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0);
1858 
1859 	return ret;
1860 }
1861 
ksz8_enable_stp_addr(struct ksz_device * dev)1862 int ksz8_enable_stp_addr(struct ksz_device *dev)
1863 {
1864 	struct alu_struct alu;
1865 
1866 	/* Setup STP address for STP operation. */
1867 	memset(&alu, 0, sizeof(alu));
1868 	ether_addr_copy(alu.mac, eth_stp_addr);
1869 	alu.is_static = true;
1870 	alu.is_override = true;
1871 	alu.port_forward = dev->info->cpu_ports;
1872 
1873 	return ksz8_w_sta_mac_table(dev, 0, &alu);
1874 }
1875 
ksz8_setup(struct dsa_switch * ds)1876 int ksz8_setup(struct dsa_switch *ds)
1877 {
1878 	struct ksz_device *dev = ds->priv;
1879 	const u16 *regs = dev->info->regs;
1880 	int i, ret = 0;
1881 
1882 	ds->mtu_enforcement_ingress = true;
1883 
1884 	/* We rely on software untagging on the CPU port, so that we
1885 	 * can support both tagged and untagged VLANs
1886 	 */
1887 	ds->untag_bridge_pvid = true;
1888 
1889 	/* VLAN filtering is partly controlled by the global VLAN
1890 	 * Enable flag
1891 	 */
1892 	ds->vlan_filtering_is_global = true;
1893 
1894 	/* Enable automatic fast aging when link changed detected. */
1895 	ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true);
1896 
1897 	/* Enable aggressive back off algorithm in half duplex mode. */
1898 	regmap_update_bits(ksz_regmap_8(dev), REG_SW_CTRL_1,
1899 			   SW_AGGR_BACKOFF, SW_AGGR_BACKOFF);
1900 
1901 	/*
1902 	 * Make sure unicast VLAN boundary is set as default and
1903 	 * enable no excessive collision drop.
1904 	 */
1905 	regmap_update_bits(ksz_regmap_8(dev), REG_SW_CTRL_2,
1906 			   UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP,
1907 			   UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP);
1908 
1909 	ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false);
1910 
1911 	ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
1912 
1913 	if (!ksz_is_ksz88x3(dev))
1914 		ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true);
1915 
1916 	for (i = 0; i < (dev->info->num_vlans / 4); i++)
1917 		ksz8_r_vlan_entries(dev, i);
1918 
1919 	/* Make sure PME (WoL) is not enabled. If requested, it will
1920 	 * be enabled by ksz_wol_pre_shutdown(). Otherwise, some PMICs
1921 	 * do not like PME events changes before shutdown. PME only
1922 	 * available on KSZ87xx family.
1923 	 */
1924 	if (ksz_is_ksz87xx(dev)) {
1925 		ret = ksz8_pme_write8(dev, regs[REG_SW_PME_CTRL], 0);
1926 		if (!ret)
1927 			ret = ksz_rmw8(dev, REG_INT_ENABLE, INT_PME, 0);
1928 	}
1929 
1930 	if (!ret)
1931 		return ksz8_handle_global_errata(ds);
1932 	else
1933 		return ret;
1934 }
1935 
ksz8_get_caps(struct ksz_device * dev,int port,struct phylink_config * config)1936 void ksz8_get_caps(struct ksz_device *dev, int port,
1937 		   struct phylink_config *config)
1938 {
1939 	config->mac_capabilities = MAC_10 | MAC_100;
1940 
1941 	/* Silicon Errata Sheet (DS80000830A):
1942 	 * "Port 1 does not respond to received flow control PAUSE frames"
1943 	 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3
1944 	 * switches.
1945 	 */
1946 	if (!ksz_is_ksz88x3(dev) || port)
1947 		config->mac_capabilities |= MAC_SYM_PAUSE;
1948 
1949 	/* Asym pause is not supported on KSZ8863 and KSZ8873 */
1950 	if (!ksz_is_ksz88x3(dev))
1951 		config->mac_capabilities |= MAC_ASYM_PAUSE;
1952 }
1953 
ksz8_get_port_addr(int port,int offset)1954 u32 ksz8_get_port_addr(int port, int offset)
1955 {
1956 	return PORT_CTRL_ADDR(port, offset);
1957 }
1958 
ksz8_switch_init(struct ksz_device * dev)1959 int ksz8_switch_init(struct ksz_device *dev)
1960 {
1961 	dev->cpu_port = fls(dev->info->cpu_ports) - 1;
1962 	dev->phy_port_cnt = dev->info->port_cnt - 1;
1963 	dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports;
1964 
1965 	return 0;
1966 }
1967 
ksz8_switch_exit(struct ksz_device * dev)1968 void ksz8_switch_exit(struct ksz_device *dev)
1969 {
1970 	ksz8_reset_switch(dev);
1971 }
1972 
1973 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>");
1974 MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver");
1975 MODULE_LICENSE("GPL");
1976