1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ8XXX series switch driver 4 * 5 * It supports the following switches: 6 * - KSZ8463 7 * - KSZ8863, KSZ8873 aka KSZ88X3 8 * - KSZ8895, KSZ8864 aka KSZ8895 family 9 * - KSZ8794, KSZ8795, KSZ8765 aka KSZ87XX 10 * Note that it does NOT support: 11 * - KSZ8563, KSZ8567 - see KSZ9477 driver 12 * 13 * Copyright (C) 2017 Microchip Technology Inc. 14 * Tristram Ha <Tristram.Ha@microchip.com> 15 */ 16 17 #include <linux/bitfield.h> 18 #include <linux/delay.h> 19 #include <linux/dsa/ksz_common.h> 20 #include <linux/export.h> 21 #include <linux/gpio.h> 22 #include <linux/if_vlan.h> 23 #include <linux/kernel.h> 24 #include <linux/module.h> 25 #include <linux/platform_data/microchip-ksz.h> 26 #include <linux/phy.h> 27 #include <linux/etherdevice.h> 28 #include <linux/if_bridge.h> 29 #include <linux/micrel_phy.h> 30 #include <net/dsa.h> 31 #include <net/switchdev.h> 32 #include <linux/phylink.h> 33 34 #include "ksz_common.h" 35 #include "ksz_dcb.h" 36 #include "ksz8_reg.h" 37 #include "ksz8.h" 38 39 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 40 { 41 ksz_rmw8(dev, addr, bits, set ? bits : 0); 42 } 43 44 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 45 bool set) 46 { 47 ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), bits, 48 set ? bits : 0); 49 } 50 51 /** 52 * ksz8_ind_write8 - EEE/ACL/PME indirect register write 53 * @dev: The device structure. 54 * @table: Function & table select, register 110. 55 * @addr: Indirect access control, register 111. 56 * @data: The data to be written. 57 * 58 * This function performs an indirect register write for EEE, ACL or 59 * PME switch functionalities. Both 8-bit registers 110 and 111 are 60 * written at once with ksz_write16, using the serial multiple write 61 * functionality. 62 * 63 * Return: 0 on success, or an error code on failure. 64 */ 65 static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data) 66 { 67 const u16 *regs; 68 u16 ctrl_addr; 69 int ret = 0; 70 71 regs = dev->info->regs; 72 73 mutex_lock(&dev->alu_mutex); 74 75 ctrl_addr = IND_ACC_TABLE(table) | addr; 76 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 77 if (!ret) 78 ret = ksz_write8(dev, regs[REG_IND_BYTE], data); 79 80 mutex_unlock(&dev->alu_mutex); 81 82 return ret; 83 } 84 85 /** 86 * ksz8_ind_read8 - EEE/ACL/PME indirect register read 87 * @dev: The device structure. 88 * @table: Function & table select, register 110. 89 * @addr: Indirect access control, register 111. 90 * @val: The value read. 91 * 92 * This function performs an indirect register read for EEE, ACL or 93 * PME switch functionalities. Both 8-bit registers 110 and 111 are 94 * written at once with ksz_write16, using the serial multiple write 95 * functionality. 96 * 97 * Return: 0 on success, or an error code on failure. 98 */ 99 static int ksz8_ind_read8(struct ksz_device *dev, u8 table, u16 addr, u8 *val) 100 { 101 const u16 *regs; 102 u16 ctrl_addr; 103 int ret = 0; 104 105 regs = dev->info->regs; 106 107 mutex_lock(&dev->alu_mutex); 108 109 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr; 110 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 111 if (!ret) 112 ret = ksz_read8(dev, regs[REG_IND_BYTE], val); 113 114 mutex_unlock(&dev->alu_mutex); 115 116 return ret; 117 } 118 119 static int ksz8_pme_write8(struct ksz_device *dev, u32 reg, u8 value) 120 { 121 return ksz8_ind_write8(dev, (u8)(reg >> 8), (u8)(reg), value); 122 } 123 124 static int ksz8_pme_pread8(struct ksz_device *dev, int port, int offset, u8 *data) 125 { 126 u8 table = (u8)(offset >> 8 | (port + 1)); 127 128 return ksz8_ind_read8(dev, table, (u8)(offset), data); 129 } 130 131 static int ksz8_pme_pwrite8(struct ksz_device *dev, int port, int offset, u8 data) 132 { 133 u8 table = (u8)(offset >> 8 | (port + 1)); 134 135 return ksz8_ind_write8(dev, table, (u8)(offset), data); 136 } 137 138 static int ksz8_reset_switch(struct ksz_device *dev) 139 { 140 if (ksz_is_ksz88x3(dev)) { 141 /* reset switch */ 142 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 143 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true); 144 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 145 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false); 146 } else if (ksz_is_ksz8463(dev)) { 147 ksz_cfg(dev, KSZ8463_REG_SW_RESET, 148 KSZ8463_GLOBAL_SOFTWARE_RESET, true); 149 ksz_cfg(dev, KSZ8463_REG_SW_RESET, 150 KSZ8463_GLOBAL_SOFTWARE_RESET, false); 151 } else { 152 /* reset switch */ 153 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 154 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S); 155 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0); 156 } 157 158 return 0; 159 } 160 161 static int ksz8863_change_mtu(struct ksz_device *dev, int frame_size) 162 { 163 u8 ctrl2 = 0; 164 165 if (frame_size <= KSZ8_LEGAL_PACKET_SIZE) 166 ctrl2 |= KSZ8863_LEGAL_PACKET_ENABLE; 167 else if (frame_size > KSZ8863_NORMAL_PACKET_SIZE) 168 ctrl2 |= KSZ8863_HUGE_PACKET_ENABLE; 169 170 return ksz_rmw8(dev, REG_SW_CTRL_2, KSZ8863_LEGAL_PACKET_ENABLE | 171 KSZ8863_HUGE_PACKET_ENABLE, ctrl2); 172 } 173 174 static int ksz8795_change_mtu(struct ksz_device *dev, int frame_size) 175 { 176 u8 ctrl1 = 0, ctrl2 = 0; 177 int ret; 178 179 if (frame_size > KSZ8_LEGAL_PACKET_SIZE) 180 ctrl2 |= SW_LEGAL_PACKET_DISABLE; 181 if (frame_size > KSZ8863_NORMAL_PACKET_SIZE) 182 ctrl1 |= SW_HUGE_PACKET; 183 184 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_HUGE_PACKET, ctrl1); 185 if (ret) 186 return ret; 187 188 return ksz_rmw8(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, ctrl2); 189 } 190 191 static int ksz8_change_mtu(struct dsa_switch *ds, int port, int mtu) 192 { 193 struct ksz_device *dev = ds->priv; 194 u16 frame_size; 195 196 if (!dsa_is_cpu_port(dev->ds, port)) 197 return 0; 198 199 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 200 201 switch (dev->chip_id) { 202 case KSZ8795_CHIP_ID: 203 case KSZ8794_CHIP_ID: 204 case KSZ8765_CHIP_ID: 205 return ksz8795_change_mtu(dev, frame_size); 206 case KSZ8463_CHIP_ID: 207 case KSZ88X3_CHIP_ID: 208 case KSZ8864_CHIP_ID: 209 case KSZ8895_CHIP_ID: 210 return ksz8863_change_mtu(dev, frame_size); 211 } 212 213 return -EOPNOTSUPP; 214 } 215 216 static int ksz8_port_queue_split(struct ksz_device *dev, int port, int queues) 217 { 218 u8 mask_4q, mask_2q; 219 u8 reg_4q, reg_2q; 220 u8 data_4q = 0; 221 u8 data_2q = 0; 222 int ret; 223 224 if (ksz_is_ksz88x3(dev)) { 225 mask_4q = KSZ8873_PORT_4QUEUE_SPLIT_EN; 226 mask_2q = KSZ8873_PORT_2QUEUE_SPLIT_EN; 227 reg_4q = REG_PORT_CTRL_0; 228 reg_2q = REG_PORT_CTRL_2; 229 230 /* KSZ8795 family switches have Weighted Fair Queueing (WFQ) 231 * enabled by default. Enable it for KSZ8873 family switches 232 * too. Default value for KSZ8873 family is strict priority, 233 * which should be enabled by using TC_SETUP_QDISC_ETS, not 234 * by default. 235 */ 236 ret = ksz_rmw8(dev, REG_SW_CTRL_3, WEIGHTED_FAIR_QUEUE_ENABLE, 237 WEIGHTED_FAIR_QUEUE_ENABLE); 238 if (ret) 239 return ret; 240 } else if (ksz_is_ksz8463(dev)) { 241 mask_4q = KSZ8873_PORT_4QUEUE_SPLIT_EN; 242 mask_2q = KSZ8873_PORT_2QUEUE_SPLIT_EN; 243 reg_4q = P1CR1; 244 reg_2q = P1CR1 + 1; 245 } else { 246 mask_4q = KSZ8795_PORT_4QUEUE_SPLIT_EN; 247 mask_2q = KSZ8795_PORT_2QUEUE_SPLIT_EN; 248 reg_4q = REG_PORT_CTRL_13; 249 reg_2q = REG_PORT_CTRL_0; 250 251 /* TODO: this is legacy from initial KSZ8795 driver, should be 252 * moved to appropriate place in the future. 253 */ 254 ret = ksz_rmw8(dev, REG_SW_CTRL_19, 255 SW_OUT_RATE_LIMIT_QUEUE_BASED, 256 SW_OUT_RATE_LIMIT_QUEUE_BASED); 257 if (ret) 258 return ret; 259 } 260 261 if (queues == 4) 262 data_4q = mask_4q; 263 else if (queues == 2) 264 data_2q = mask_2q; 265 266 ret = ksz_prmw8(dev, port, reg_4q, mask_4q, data_4q); 267 if (ret) 268 return ret; 269 270 return ksz_prmw8(dev, port, reg_2q, mask_2q, data_2q); 271 } 272 273 static void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 274 { 275 const u32 *masks; 276 const u16 *regs; 277 u16 ctrl_addr; 278 u32 data; 279 u8 check; 280 int loop; 281 282 masks = dev->info->masks; 283 regs = dev->info->regs; 284 285 ctrl_addr = addr + dev->info->reg_mib_cnt * port; 286 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 287 288 mutex_lock(&dev->alu_mutex); 289 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 290 291 /* It is almost guaranteed to always read the valid bit because of 292 * slow SPI speed. 293 */ 294 for (loop = 2; loop > 0; loop--) { 295 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 296 297 if (check & masks[MIB_COUNTER_VALID]) { 298 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 299 if (check & masks[MIB_COUNTER_OVERFLOW]) 300 *cnt += MIB_COUNTER_VALUE + 1; 301 *cnt += data & MIB_COUNTER_VALUE; 302 break; 303 } 304 } 305 mutex_unlock(&dev->alu_mutex); 306 } 307 308 static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 309 u64 *dropped, u64 *cnt) 310 { 311 const u32 *masks; 312 const u16 *regs; 313 u16 ctrl_addr; 314 u32 data; 315 u8 check; 316 int loop; 317 318 masks = dev->info->masks; 319 regs = dev->info->regs; 320 321 addr -= dev->info->reg_mib_cnt; 322 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port; 323 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0; 324 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 325 326 mutex_lock(&dev->alu_mutex); 327 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 328 329 /* It is almost guaranteed to always read the valid bit because of 330 * slow SPI speed. 331 */ 332 for (loop = 2; loop > 0; loop--) { 333 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 334 335 if (check & masks[MIB_COUNTER_VALID]) { 336 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 337 if (addr < 2) { 338 u64 total; 339 340 total = check & MIB_TOTAL_BYTES_H; 341 total <<= 32; 342 *cnt += total; 343 *cnt += data; 344 if (check & masks[MIB_COUNTER_OVERFLOW]) { 345 total = MIB_TOTAL_BYTES_H + 1; 346 total <<= 32; 347 *cnt += total; 348 } 349 } else { 350 if (check & masks[MIB_COUNTER_OVERFLOW]) 351 *cnt += MIB_PACKET_DROPPED + 1; 352 *cnt += data & MIB_PACKET_DROPPED; 353 } 354 break; 355 } 356 } 357 mutex_unlock(&dev->alu_mutex); 358 } 359 360 static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 361 u64 *dropped, u64 *cnt) 362 { 363 u32 *last = (u32 *)dropped; 364 const u16 *regs; 365 u16 ctrl_addr; 366 u32 data; 367 u32 cur; 368 369 regs = dev->info->regs; 370 371 addr -= dev->info->reg_mib_cnt; 372 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 : 373 KSZ8863_MIB_PACKET_DROPPED_RX_0; 374 if (ksz_is_8895_family(dev) && 375 ctrl_addr == KSZ8863_MIB_PACKET_DROPPED_RX_0) 376 ctrl_addr = KSZ8895_MIB_PACKET_DROPPED_RX_0; 377 ctrl_addr += port; 378 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 379 380 mutex_lock(&dev->alu_mutex); 381 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 382 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 383 mutex_unlock(&dev->alu_mutex); 384 385 data &= MIB_PACKET_DROPPED; 386 cur = last[addr]; 387 if (data != cur) { 388 last[addr] = data; 389 if (data < cur) 390 data += MIB_PACKET_DROPPED + 1; 391 data -= cur; 392 *cnt += data; 393 } 394 } 395 396 static void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 397 u64 *dropped, u64 *cnt) 398 { 399 if (is_ksz88xx(dev)) 400 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt); 401 else 402 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt); 403 } 404 405 static void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze) 406 { 407 if (is_ksz88xx(dev)) 408 return; 409 410 /* enable the port for flush/freeze function */ 411 if (freeze) 412 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 413 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze); 414 415 /* disable the port after freeze is done */ 416 if (!freeze) 417 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 418 } 419 420 static void ksz8_port_init_cnt(struct ksz_device *dev, int port) 421 { 422 struct ksz_port_mib *mib = &dev->ports[port].mib; 423 u64 *dropped; 424 425 /* For KSZ8795 family. */ 426 if (ksz_is_ksz87xx(dev)) { 427 /* flush all enabled port MIB counters */ 428 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 429 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true); 430 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 431 } 432 433 mib->cnt_ptr = 0; 434 435 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 436 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 437 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 438 &mib->counters[mib->cnt_ptr]); 439 ++mib->cnt_ptr; 440 } 441 442 /* last one in storage */ 443 dropped = &mib->counters[dev->info->mib_cnt]; 444 445 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 446 while (mib->cnt_ptr < dev->info->mib_cnt) { 447 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 448 dropped, &mib->counters[mib->cnt_ptr]); 449 ++mib->cnt_ptr; 450 } 451 } 452 453 static int ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data) 454 { 455 const u16 *regs; 456 u16 ctrl_addr; 457 int ret; 458 459 regs = dev->info->regs; 460 461 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr; 462 463 mutex_lock(&dev->alu_mutex); 464 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 465 if (ret) 466 goto unlock_alu; 467 468 ret = ksz_read64(dev, regs[REG_IND_DATA_HI], data); 469 unlock_alu: 470 mutex_unlock(&dev->alu_mutex); 471 472 return ret; 473 } 474 475 static int ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data) 476 { 477 const u16 *regs; 478 u16 ctrl_addr; 479 int ret; 480 481 regs = dev->info->regs; 482 483 ctrl_addr = IND_ACC_TABLE(table) | addr; 484 485 mutex_lock(&dev->alu_mutex); 486 ret = ksz_write64(dev, regs[REG_IND_DATA_HI], data); 487 if (ret) 488 goto unlock_alu; 489 490 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 491 unlock_alu: 492 mutex_unlock(&dev->alu_mutex); 493 494 return ret; 495 } 496 497 static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data) 498 { 499 int timeout = 100; 500 const u32 *masks; 501 const u16 *regs; 502 int ret; 503 504 masks = dev->info->masks; 505 regs = dev->info->regs; 506 507 do { 508 ret = ksz_read8(dev, regs[REG_IND_DATA_CHECK], data); 509 if (ret) 510 return ret; 511 512 timeout--; 513 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout); 514 515 /* Entry is not ready for accessing. */ 516 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) 517 return -ETIMEDOUT; 518 519 /* Entry is ready for accessing. */ 520 return ksz_read8(dev, regs[REG_IND_DATA_8], data); 521 } 522 523 static int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr, u8 *mac_addr, 524 u8 *fid, u8 *src_port, u16 *entries) 525 { 526 u32 data_hi, data_lo; 527 const u8 *shifts; 528 const u32 *masks; 529 const u16 *regs; 530 u16 ctrl_addr; 531 u64 buf = 0; 532 u8 data; 533 int cnt; 534 int ret; 535 536 shifts = dev->info->shifts; 537 masks = dev->info->masks; 538 regs = dev->info->regs; 539 540 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr; 541 542 mutex_lock(&dev->alu_mutex); 543 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 544 if (ret) 545 goto unlock_alu; 546 547 ret = ksz8_valid_dyn_entry(dev, &data); 548 if (ret) 549 goto unlock_alu; 550 551 if (data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY]) { 552 *entries = 0; 553 goto unlock_alu; 554 } 555 556 ret = ksz_read64(dev, regs[REG_IND_DATA_HI], &buf); 557 if (ret) 558 goto unlock_alu; 559 560 data_hi = (u32)(buf >> 32); 561 data_lo = (u32)buf; 562 563 /* Check out how many valid entry in the table. */ 564 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H]; 565 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H]; 566 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >> 567 shifts[DYNAMIC_MAC_ENTRIES]; 568 *entries = cnt + 1; 569 570 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >> 571 shifts[DYNAMIC_MAC_FID]; 572 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >> 573 shifts[DYNAMIC_MAC_SRC_PORT]; 574 575 mac_addr[5] = (u8)data_lo; 576 mac_addr[4] = (u8)(data_lo >> 8); 577 mac_addr[3] = (u8)(data_lo >> 16); 578 mac_addr[2] = (u8)(data_lo >> 24); 579 580 mac_addr[1] = (u8)data_hi; 581 mac_addr[0] = (u8)(data_hi >> 8); 582 583 unlock_alu: 584 mutex_unlock(&dev->alu_mutex); 585 586 return ret; 587 } 588 589 static int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr, 590 struct alu_struct *alu, bool *valid) 591 { 592 u32 data_hi, data_lo; 593 const u8 *shifts; 594 const u32 *masks; 595 u64 data; 596 int ret; 597 598 shifts = dev->info->shifts; 599 masks = dev->info->masks; 600 601 ret = ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data); 602 if (ret) 603 return ret; 604 605 data_hi = data >> 32; 606 data_lo = (u32)data; 607 608 if (!(data_hi & (masks[STATIC_MAC_TABLE_VALID] | 609 masks[STATIC_MAC_TABLE_OVERRIDE]))) { 610 *valid = false; 611 return 0; 612 } 613 614 alu->mac[5] = (u8)data_lo; 615 alu->mac[4] = (u8)(data_lo >> 8); 616 alu->mac[3] = (u8)(data_lo >> 16); 617 alu->mac[2] = (u8)(data_lo >> 24); 618 alu->mac[1] = (u8)data_hi; 619 alu->mac[0] = (u8)(data_hi >> 8); 620 alu->port_forward = 621 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >> 622 shifts[STATIC_MAC_FWD_PORTS]; 623 alu->is_override = (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0; 624 625 /* KSZ8795/KSZ8895 family switches have STATIC_MAC_TABLE_USE_FID and 626 * STATIC_MAC_TABLE_FID definitions off by 1 when doing read on the 627 * static MAC table compared to doing write. 628 */ 629 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev)) 630 data_hi >>= 1; 631 alu->is_static = true; 632 alu->is_use_fid = (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0; 633 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >> 634 shifts[STATIC_MAC_FID]; 635 636 *valid = true; 637 638 return 0; 639 } 640 641 static int ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr, 642 struct alu_struct *alu) 643 { 644 u32 data_hi, data_lo; 645 const u8 *shifts; 646 const u32 *masks; 647 u64 data; 648 649 shifts = dev->info->shifts; 650 masks = dev->info->masks; 651 652 data_lo = ((u32)alu->mac[2] << 24) | 653 ((u32)alu->mac[3] << 16) | 654 ((u32)alu->mac[4] << 8) | alu->mac[5]; 655 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1]; 656 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS]; 657 658 if (alu->is_override) 659 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE]; 660 if (alu->is_use_fid) { 661 data_hi |= masks[STATIC_MAC_TABLE_USE_FID]; 662 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID]; 663 } 664 if (alu->is_static) 665 data_hi |= masks[STATIC_MAC_TABLE_VALID]; 666 else 667 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE]; 668 669 data = (u64)data_hi << 32 | data_lo; 670 671 return ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data); 672 } 673 674 static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid, 675 u8 *member, u8 *valid) 676 { 677 const u8 *shifts; 678 const u32 *masks; 679 680 shifts = dev->info->shifts; 681 masks = dev->info->masks; 682 683 *fid = vlan & masks[VLAN_TABLE_FID]; 684 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >> 685 shifts[VLAN_TABLE_MEMBERSHIP_S]; 686 *valid = !!(vlan & masks[VLAN_TABLE_VALID]); 687 } 688 689 static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid, 690 u16 *vlan) 691 { 692 const u8 *shifts; 693 const u32 *masks; 694 695 shifts = dev->info->shifts; 696 masks = dev->info->masks; 697 698 *vlan = fid; 699 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S]; 700 if (valid) 701 *vlan |= masks[VLAN_TABLE_VALID]; 702 } 703 704 static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr) 705 { 706 const u8 *shifts; 707 u64 data; 708 int i; 709 710 shifts = dev->info->shifts; 711 712 ksz8_r_table(dev, TABLE_VLAN, addr, &data); 713 addr *= 4; 714 for (i = 0; i < 4; i++) { 715 dev->vlan_cache[addr + i].table[0] = (u16)data; 716 data >>= shifts[VLAN_TABLE]; 717 } 718 } 719 720 static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan) 721 { 722 int index; 723 u16 *data; 724 u16 addr; 725 u64 buf; 726 727 data = (u16 *)&buf; 728 addr = vid / 4; 729 index = vid & 3; 730 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 731 *vlan = data[index]; 732 } 733 734 static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan) 735 { 736 int index; 737 u16 *data; 738 u16 addr; 739 u64 buf; 740 741 data = (u16 *)&buf; 742 addr = vid / 4; 743 index = vid & 3; 744 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 745 data[index] = vlan; 746 dev->vlan_cache[vid].table[0] = vlan; 747 ksz8_w_table(dev, TABLE_VLAN, addr, buf); 748 } 749 750 /** 751 * ksz879x_get_loopback - KSZ879x specific function to get loopback 752 * configuration status for a specific port 753 * @dev: Pointer to the device structure 754 * @port: Port number to query 755 * @val: Pointer to store the result 756 * 757 * This function reads the SMI registers to determine whether loopback mode 758 * is enabled for a specific port. 759 * 760 * Return: 0 on success, error code on failure. 761 */ 762 static int ksz879x_get_loopback(struct ksz_device *dev, u16 port, 763 u16 *val) 764 { 765 u8 stat3; 766 int ret; 767 768 ret = ksz_pread8(dev, port, REG_PORT_STATUS_3, &stat3); 769 if (ret) 770 return ret; 771 772 if (stat3 & PORT_PHY_LOOPBACK) 773 *val |= BMCR_LOOPBACK; 774 775 return 0; 776 } 777 778 /** 779 * ksz879x_set_loopback - KSZ879x specific function to set loopback mode for 780 * a specific port 781 * @dev: Pointer to the device structure. 782 * @port: Port number to modify. 783 * @val: Value indicating whether to enable or disable loopback mode. 784 * 785 * This function translates loopback bit of the BMCR register into the 786 * corresponding hardware register bit value and writes it to the SMI interface. 787 * 788 * Return: 0 on success, error code on failure. 789 */ 790 static int ksz879x_set_loopback(struct ksz_device *dev, u16 port, u16 val) 791 { 792 u8 stat3 = 0; 793 794 if (val & BMCR_LOOPBACK) 795 stat3 |= PORT_PHY_LOOPBACK; 796 797 return ksz_prmw8(dev, port, REG_PORT_STATUS_3, PORT_PHY_LOOPBACK, 798 stat3); 799 } 800 801 static int ksz87xx_apply_low_loss_preset(struct ksz_device *dev, bool enable) 802 { 803 /* Apply the Microchip erratum short-cable preset (LPF 62 MHz, EQ init 0) 804 * providing a conservative configuration for short or low-loss cables. 805 */ 806 u8 lpf_bw, eq_init; 807 int ret; 808 809 lpf_bw = KSZ87XX_PHY_LPF_62MHZ; 810 eq_init = KSZ87XX_DSP_EQ_INIT_LOW_LOSS; 811 812 if (!ksz_is_ksz87xx(dev)) 813 return -EOPNOTSUPP; 814 815 if (!enable) { 816 /* Restore default values (LPF 90 MHz, EQ init 15). */ 817 lpf_bw = KSZ87XX_PHY_LPF_90MHZ; 818 eq_init = KSZ87XX_DSP_EQ_INIT_FACTORY; 819 } 820 821 ret = ksz8_ind_write8(dev, TABLE_LINK_MD, KSZ87XX_REG_PHY_LPF, lpf_bw); 822 if (ret) 823 return ret; 824 825 dev->lpf_bw = lpf_bw; 826 ret = ksz8_ind_write8(dev, TABLE_LINK_MD, KSZ87XX_REG_DSP_EQ, eq_init); 827 if (ret) 828 return ret; 829 830 dev->eq_init = eq_init; 831 832 return ret; 833 } 834 835 /** 836 * ksz8_r_phy_ctrl - Translates and reads from the SMI interface to a MIIM PHY 837 * Control register (Reg. 31). 838 * @dev: The KSZ device instance. 839 * @port: The port number to be read. 840 * @val: The value read from the SMI interface. 841 * 842 * This function reads the SMI interface and translates the hardware register 843 * bit values into their corresponding control settings for a MIIM PHY Control 844 * register. 845 * 846 * Return: 0 on success, error code on failure. 847 */ 848 static int ksz8_r_phy_ctrl(struct ksz_device *dev, int port, u16 *val) 849 { 850 const u16 *regs = dev->info->regs; 851 u8 reg_val; 852 int ret; 853 854 *val = 0; 855 856 ret = ksz_pread8(dev, port, regs[P_LINK_STATUS], ®_val); 857 if (ret < 0) 858 return ret; 859 860 if (reg_val & PORT_MDIX_STATUS) 861 *val |= KSZ886X_CTRL_MDIX_STAT; 862 863 ret = ksz_pread8(dev, port, REG_PORT_LINK_MD_CTRL, ®_val); 864 if (ret < 0) 865 return ret; 866 867 if (reg_val & PORT_FORCE_LINK) 868 *val |= KSZ886X_CTRL_FORCE_LINK; 869 870 if (reg_val & PORT_POWER_SAVING) 871 *val |= KSZ886X_CTRL_PWRSAVE; 872 873 if (reg_val & PORT_PHY_REMOTE_LOOPBACK) 874 *val |= KSZ886X_CTRL_REMOTE_LOOPBACK; 875 876 return 0; 877 } 878 879 /** 880 * ksz8_r_phy_bmcr - Translates and reads from the SMI interface to a MIIM PHY 881 * Basic mode control register (Reg. 0). 882 * @dev: The KSZ device instance. 883 * @port: The port number to be read. 884 * @val: The value read from the SMI interface. 885 * 886 * This function reads the SMI interface and translates the hardware register 887 * bit values into their corresponding control settings for a MIIM PHY Basic 888 * mode control register. 889 * 890 * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873 891 * ------------------------------------------------------------------- 892 * MIIM Bit | KSZ8794 Reg/Bit | KSZ8873 Reg/Bit 893 * ----------------------------+-----------------------------+---------------- 894 * Bit 15 - Soft Reset | 0xF/4 | Not supported 895 * Bit 14 - Loopback | 0xD/0 (MAC), 0xF/7 (PHY) ~ 0xD/0 (PHY) 896 * Bit 13 - Force 100 | 0xC/6 = 0xC/6 897 * Bit 12 - AN Enable | 0xC/7 (reverse logic) ~ 0xC/7 898 * Bit 11 - Power Down | 0xD/3 = 0xD/3 899 * Bit 10 - PHY Isolate | 0xF/5 | Not supported 900 * Bit 9 - Restart AN | 0xD/5 = 0xD/5 901 * Bit 8 - Force Full-Duplex | 0xC/5 = 0xC/5 902 * Bit 7 - Collision Test/Res. | Not supported | Not supported 903 * Bit 6 - Reserved | Not supported | Not supported 904 * Bit 5 - Hp_mdix | 0x9/7 ~ 0xF/7 905 * Bit 4 - Force MDI | 0xD/1 = 0xD/1 906 * Bit 3 - Disable MDIX | 0xD/2 = 0xD/2 907 * Bit 2 - Disable Far-End F. | ???? | 0xD/4 908 * Bit 1 - Disable Transmit | 0xD/6 = 0xD/6 909 * Bit 0 - Disable LED | 0xD/7 = 0xD/7 910 * ------------------------------------------------------------------- 911 * 912 * Return: 0 on success, error code on failure. 913 */ 914 static int ksz8_r_phy_bmcr(struct ksz_device *dev, u16 port, u16 *val) 915 { 916 const u16 *regs = dev->info->regs; 917 u8 restart, speed, ctrl; 918 int ret; 919 920 *val = 0; 921 922 ret = ksz_pread8(dev, port, regs[P_NEG_RESTART_CTRL], &restart); 923 if (ret) 924 return ret; 925 926 ret = ksz_pread8(dev, port, regs[P_SPEED_STATUS], &speed); 927 if (ret) 928 return ret; 929 930 ret = ksz_pread8(dev, port, regs[P_FORCE_CTRL], &ctrl); 931 if (ret) 932 return ret; 933 934 if (ctrl & PORT_FORCE_100_MBIT) 935 *val |= BMCR_SPEED100; 936 937 if (ksz_is_ksz88x3(dev)) { 938 if (restart & KSZ8873_PORT_PHY_LOOPBACK) 939 *val |= BMCR_LOOPBACK; 940 941 if ((ctrl & PORT_AUTO_NEG_ENABLE)) 942 *val |= BMCR_ANENABLE; 943 } else { 944 ret = ksz879x_get_loopback(dev, port, val); 945 if (ret) 946 return ret; 947 948 if (!(ctrl & PORT_AUTO_NEG_DISABLE)) 949 *val |= BMCR_ANENABLE; 950 } 951 952 if (restart & PORT_POWER_DOWN) 953 *val |= BMCR_PDOWN; 954 955 if (restart & PORT_AUTO_NEG_RESTART) 956 *val |= BMCR_ANRESTART; 957 958 if (ctrl & PORT_FORCE_FULL_DUPLEX) 959 *val |= BMCR_FULLDPLX; 960 961 if (speed & PORT_HP_MDIX) 962 *val |= KSZ886X_BMCR_HP_MDIX; 963 964 if (restart & PORT_FORCE_MDIX) 965 *val |= KSZ886X_BMCR_FORCE_MDI; 966 967 if (restart & PORT_AUTO_MDIX_DISABLE) 968 *val |= KSZ886X_BMCR_DISABLE_AUTO_MDIX; 969 970 if (restart & PORT_TX_DISABLE) 971 *val |= KSZ886X_BMCR_DISABLE_TRANSMIT; 972 973 if (restart & PORT_LED_OFF) 974 *val |= KSZ886X_BMCR_DISABLE_LED; 975 976 return 0; 977 } 978 979 static int ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) 980 { 981 u8 ctrl, link, val1, val2; 982 int processed = true; 983 const u16 *regs; 984 u16 data = 0; 985 u16 p = phy; 986 int ret; 987 988 regs = dev->info->regs; 989 990 switch (reg) { 991 case MII_BMCR: 992 ret = ksz8_r_phy_bmcr(dev, p, &data); 993 if (ret) 994 return ret; 995 break; 996 case MII_BMSR: 997 ret = ksz_pread8(dev, p, regs[P_LINK_STATUS], &link); 998 if (ret) 999 return ret; 1000 1001 data = BMSR_100FULL | 1002 BMSR_100HALF | 1003 BMSR_10FULL | 1004 BMSR_10HALF | 1005 BMSR_ANEGCAPABLE; 1006 if (link & PORT_AUTO_NEG_COMPLETE) 1007 data |= BMSR_ANEGCOMPLETE; 1008 if (link & PORT_STAT_LINK_GOOD) 1009 data |= BMSR_LSTATUS; 1010 break; 1011 case MII_PHYSID1: 1012 data = KSZ8795_ID_HI; 1013 break; 1014 case MII_PHYSID2: 1015 if (ksz_is_ksz88x3(dev)) 1016 data = KSZ8863_ID_LO; 1017 else 1018 data = KSZ8795_ID_LO; 1019 break; 1020 case MII_ADVERTISE: 1021 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 1022 if (ret) 1023 return ret; 1024 1025 data = ADVERTISE_CSMA; 1026 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE) 1027 data |= ADVERTISE_PAUSE_CAP; 1028 if (ctrl & PORT_AUTO_NEG_100BTX_FD) 1029 data |= ADVERTISE_100FULL; 1030 if (ctrl & PORT_AUTO_NEG_100BTX) 1031 data |= ADVERTISE_100HALF; 1032 if (ctrl & PORT_AUTO_NEG_10BT_FD) 1033 data |= ADVERTISE_10FULL; 1034 if (ctrl & PORT_AUTO_NEG_10BT) 1035 data |= ADVERTISE_10HALF; 1036 break; 1037 case MII_LPA: 1038 ret = ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link); 1039 if (ret) 1040 return ret; 1041 1042 data = LPA_SLCT; 1043 if (link & PORT_REMOTE_SYM_PAUSE) 1044 data |= LPA_PAUSE_CAP; 1045 if (link & PORT_REMOTE_100BTX_FD) 1046 data |= LPA_100FULL; 1047 if (link & PORT_REMOTE_100BTX) 1048 data |= LPA_100HALF; 1049 if (link & PORT_REMOTE_10BT_FD) 1050 data |= LPA_10FULL; 1051 if (link & PORT_REMOTE_10BT) 1052 data |= LPA_10HALF; 1053 if (data & ~LPA_SLCT) 1054 data |= LPA_LPACK; 1055 break; 1056 case PHY_REG_LINK_MD: 1057 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1); 1058 if (ret) 1059 return ret; 1060 1061 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2); 1062 if (ret) 1063 return ret; 1064 1065 if (val1 & PORT_START_CABLE_DIAG) 1066 data |= PHY_START_CABLE_DIAG; 1067 1068 if (val1 & PORT_CABLE_10M_SHORT) 1069 data |= PHY_CABLE_10M_SHORT; 1070 1071 data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M, 1072 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1)); 1073 1074 data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M, 1075 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) | 1076 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2)); 1077 break; 1078 case PHY_REG_PHY_CTRL: 1079 ret = ksz8_r_phy_ctrl(dev, p, &data); 1080 if (ret) 1081 return ret; 1082 1083 break; 1084 case PHY_REG_KSZ87XX_SHORT_CABLE: 1085 if (!ksz_is_ksz87xx(dev)) 1086 return -EOPNOTSUPP; 1087 data = !!(dev->lpf_bw == KSZ87XX_PHY_LPF_62MHZ && 1088 dev->eq_init == KSZ87XX_DSP_EQ_INIT_LOW_LOSS); 1089 break; 1090 case PHY_REG_KSZ87XX_LPF_BW: 1091 if (!ksz_is_ksz87xx(dev)) 1092 return -EOPNOTSUPP; 1093 data = dev->lpf_bw; 1094 break; 1095 case PHY_REG_KSZ87XX_EQ_INIT: 1096 if (!ksz_is_ksz87xx(dev)) 1097 return -EOPNOTSUPP; 1098 data = dev->eq_init; 1099 break; 1100 default: 1101 processed = false; 1102 break; 1103 } 1104 if (processed) 1105 *val = data; 1106 1107 return 0; 1108 } 1109 1110 static int ksz8_phy_read16(struct dsa_switch *ds, int addr, int reg) 1111 { 1112 struct ksz_device *dev = ds->priv; 1113 u16 val = 0xffff; 1114 int ret; 1115 1116 ret = ksz8_r_phy(dev, addr, reg, &val); 1117 if (ret) 1118 return ret; 1119 1120 return val; 1121 } 1122 1123 /** 1124 * ksz8_w_phy_ctrl - Translates and writes to the SMI interface from a MIIM PHY 1125 * Control register (Reg. 31). 1126 * @dev: The KSZ device instance. 1127 * @port: The port number to be configured. 1128 * @val: The register value to be written. 1129 * 1130 * This function translates control settings from a MIIM PHY Control register 1131 * into their corresponding hardware register bit values for the SMI 1132 * interface. 1133 * 1134 * Return: 0 on success, error code on failure. 1135 */ 1136 static int ksz8_w_phy_ctrl(struct ksz_device *dev, int port, u16 val) 1137 { 1138 u8 reg_val = 0; 1139 int ret; 1140 1141 if (val & KSZ886X_CTRL_FORCE_LINK) 1142 reg_val |= PORT_FORCE_LINK; 1143 1144 if (val & KSZ886X_CTRL_PWRSAVE) 1145 reg_val |= PORT_POWER_SAVING; 1146 1147 if (val & KSZ886X_CTRL_REMOTE_LOOPBACK) 1148 reg_val |= PORT_PHY_REMOTE_LOOPBACK; 1149 1150 ret = ksz_prmw8(dev, port, REG_PORT_LINK_MD_CTRL, PORT_FORCE_LINK | 1151 PORT_POWER_SAVING | PORT_PHY_REMOTE_LOOPBACK, reg_val); 1152 return ret; 1153 } 1154 1155 /** 1156 * ksz8_w_phy_bmcr - Translates and writes to the SMI interface from a MIIM PHY 1157 * Basic mode control register (Reg. 0). 1158 * @dev: The KSZ device instance. 1159 * @port: The port number to be configured. 1160 * @val: The register value to be written. 1161 * 1162 * This function translates control settings from a MIIM PHY Basic mode control 1163 * register into their corresponding hardware register bit values for the SMI 1164 * interface. 1165 * 1166 * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873 1167 * ------------------------------------------------------------------- 1168 * MIIM Bit | KSZ8794 Reg/Bit | KSZ8873 Reg/Bit 1169 * ----------------------------+-----------------------------+---------------- 1170 * Bit 15 - Soft Reset | 0xF/4 | Not supported 1171 * Bit 14 - Loopback | 0xD/0 (MAC), 0xF/7 (PHY) ~ 0xD/0 (PHY) 1172 * Bit 13 - Force 100 | 0xC/6 = 0xC/6 1173 * Bit 12 - AN Enable | 0xC/7 (reverse logic) ~ 0xC/7 1174 * Bit 11 - Power Down | 0xD/3 = 0xD/3 1175 * Bit 10 - PHY Isolate | 0xF/5 | Not supported 1176 * Bit 9 - Restart AN | 0xD/5 = 0xD/5 1177 * Bit 8 - Force Full-Duplex | 0xC/5 = 0xC/5 1178 * Bit 7 - Collision Test/Res. | Not supported | Not supported 1179 * Bit 6 - Reserved | Not supported | Not supported 1180 * Bit 5 - Hp_mdix | 0x9/7 ~ 0xF/7 1181 * Bit 4 - Force MDI | 0xD/1 = 0xD/1 1182 * Bit 3 - Disable MDIX | 0xD/2 = 0xD/2 1183 * Bit 2 - Disable Far-End F. | ???? | 0xD/4 1184 * Bit 1 - Disable Transmit | 0xD/6 = 0xD/6 1185 * Bit 0 - Disable LED | 0xD/7 = 0xD/7 1186 * ------------------------------------------------------------------- 1187 * 1188 * Return: 0 on success, error code on failure. 1189 */ 1190 static int ksz8_w_phy_bmcr(struct ksz_device *dev, u16 port, u16 val) 1191 { 1192 u8 restart, speed, ctrl, restart_mask; 1193 const u16 *regs = dev->info->regs; 1194 int ret; 1195 1196 /* Do not support PHY reset function. */ 1197 if (val & BMCR_RESET) 1198 return 0; 1199 1200 speed = 0; 1201 if (val & KSZ886X_BMCR_HP_MDIX) 1202 speed |= PORT_HP_MDIX; 1203 1204 ret = ksz_prmw8(dev, port, regs[P_SPEED_STATUS], PORT_HP_MDIX, speed); 1205 if (ret) 1206 return ret; 1207 1208 ctrl = 0; 1209 if (ksz_is_ksz88x3(dev)) { 1210 if ((val & BMCR_ANENABLE)) 1211 ctrl |= PORT_AUTO_NEG_ENABLE; 1212 } else { 1213 if (!(val & BMCR_ANENABLE)) 1214 ctrl |= PORT_AUTO_NEG_DISABLE; 1215 1216 /* Fiber port does not support auto-negotiation. */ 1217 if (dev->ports[port].fiber) 1218 ctrl |= PORT_AUTO_NEG_DISABLE; 1219 } 1220 1221 if (val & BMCR_SPEED100) 1222 ctrl |= PORT_FORCE_100_MBIT; 1223 1224 if (val & BMCR_FULLDPLX) 1225 ctrl |= PORT_FORCE_FULL_DUPLEX; 1226 1227 ret = ksz_prmw8(dev, port, regs[P_FORCE_CTRL], PORT_FORCE_100_MBIT | 1228 /* PORT_AUTO_NEG_ENABLE and PORT_AUTO_NEG_DISABLE are the same 1229 * bits 1230 */ 1231 PORT_FORCE_FULL_DUPLEX | PORT_AUTO_NEG_ENABLE, ctrl); 1232 if (ret) 1233 return ret; 1234 1235 restart = 0; 1236 restart_mask = PORT_LED_OFF | PORT_TX_DISABLE | PORT_AUTO_NEG_RESTART | 1237 PORT_POWER_DOWN | PORT_AUTO_MDIX_DISABLE | PORT_FORCE_MDIX; 1238 1239 if (val & KSZ886X_BMCR_DISABLE_LED) 1240 restart |= PORT_LED_OFF; 1241 1242 if (val & KSZ886X_BMCR_DISABLE_TRANSMIT) 1243 restart |= PORT_TX_DISABLE; 1244 1245 if (val & BMCR_ANRESTART) 1246 restart |= PORT_AUTO_NEG_RESTART; 1247 1248 if (val & BMCR_PDOWN) 1249 restart |= PORT_POWER_DOWN; 1250 1251 if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX) 1252 restart |= PORT_AUTO_MDIX_DISABLE; 1253 1254 if (val & KSZ886X_BMCR_FORCE_MDI) 1255 restart |= PORT_FORCE_MDIX; 1256 1257 if (ksz_is_ksz88x3(dev)) { 1258 restart_mask |= KSZ8873_PORT_PHY_LOOPBACK; 1259 1260 if (val & BMCR_LOOPBACK) 1261 restart |= KSZ8873_PORT_PHY_LOOPBACK; 1262 } else { 1263 ret = ksz879x_set_loopback(dev, port, val); 1264 if (ret) 1265 return ret; 1266 } 1267 1268 return ksz_prmw8(dev, port, regs[P_NEG_RESTART_CTRL], restart_mask, 1269 restart); 1270 } 1271 1272 static int ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) 1273 { 1274 const u16 *regs; 1275 u8 ctrl, data; 1276 u16 p = phy; 1277 int ret; 1278 1279 regs = dev->info->regs; 1280 1281 switch (reg) { 1282 case MII_BMCR: 1283 ret = ksz8_w_phy_bmcr(dev, p, val); 1284 if (ret) 1285 return ret; 1286 break; 1287 case MII_ADVERTISE: 1288 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 1289 if (ret) 1290 return ret; 1291 1292 data = ctrl; 1293 data &= ~(PORT_AUTO_NEG_SYM_PAUSE | 1294 PORT_AUTO_NEG_100BTX_FD | 1295 PORT_AUTO_NEG_100BTX | 1296 PORT_AUTO_NEG_10BT_FD | 1297 PORT_AUTO_NEG_10BT); 1298 if (val & ADVERTISE_PAUSE_CAP) 1299 data |= PORT_AUTO_NEG_SYM_PAUSE; 1300 if (val & ADVERTISE_100FULL) 1301 data |= PORT_AUTO_NEG_100BTX_FD; 1302 if (val & ADVERTISE_100HALF) 1303 data |= PORT_AUTO_NEG_100BTX; 1304 if (val & ADVERTISE_10FULL) 1305 data |= PORT_AUTO_NEG_10BT_FD; 1306 if (val & ADVERTISE_10HALF) 1307 data |= PORT_AUTO_NEG_10BT; 1308 1309 if (data != ctrl) { 1310 ret = ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data); 1311 if (ret) 1312 return ret; 1313 } 1314 break; 1315 case PHY_REG_LINK_MD: 1316 if (val & PHY_START_CABLE_DIAG) 1317 ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true); 1318 break; 1319 1320 case PHY_REG_PHY_CTRL: 1321 ret = ksz8_w_phy_ctrl(dev, p, val); 1322 if (ret) 1323 return ret; 1324 break; 1325 case PHY_REG_KSZ87XX_SHORT_CABLE: 1326 if (!ksz_is_ksz87xx(dev)) 1327 return -EOPNOTSUPP; 1328 dev_info_once(dev->dev, 1329 "KSZ87xx low-loss tuning is global, applied switch-wide\n"); 1330 ret = ksz87xx_apply_low_loss_preset(dev, !!val); 1331 if (ret) 1332 return ret; 1333 break; 1334 case PHY_REG_KSZ87XX_LPF_BW: 1335 if (!ksz_is_ksz87xx(dev)) 1336 return -EOPNOTSUPP; 1337 dev_info_once(dev->dev, 1338 "KSZ87xx low-loss tuning is global, applied switch-wide\n"); 1339 /* Only accept LPF bandwidth bits [7:6] */ 1340 if (val & ~KSZ87XX_PHY_LPF_MASK) 1341 return -EINVAL; 1342 ret = ksz8_ind_write8(dev, TABLE_LINK_MD, KSZ87XX_REG_PHY_LPF, (u8)val); 1343 if (ret) 1344 return ret; 1345 dev->lpf_bw = val; 1346 break; 1347 case PHY_REG_KSZ87XX_EQ_INIT: 1348 if (!ksz_is_ksz87xx(dev)) 1349 return -EOPNOTSUPP; 1350 dev_info_once(dev->dev, 1351 "KSZ87xx low-loss tuning is global, applied switch-wide\n"); 1352 /* Only accept DSP EQ initial value bits [5:0] */ 1353 if (val & ~KSZ87XX_DSP_EQ_VALID_MASK) 1354 return -EINVAL; 1355 ret = ksz8_ind_write8(dev, TABLE_LINK_MD, KSZ87XX_REG_DSP_EQ, (u8)val); 1356 if (ret) 1357 return ret; 1358 dev->eq_init = val; 1359 break; 1360 default: 1361 break; 1362 } 1363 1364 return 0; 1365 } 1366 1367 static int ksz8_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 1368 { 1369 struct ksz_device *dev = ds->priv; 1370 int ret; 1371 1372 ret = ksz8_w_phy(dev, addr, reg, val); 1373 if (ret) 1374 return ret; 1375 1376 return 0; 1377 } 1378 1379 static void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member) 1380 { 1381 int offset = P_MIRROR_CTRL; 1382 u8 data; 1383 1384 if (ksz_is_ksz8463(dev)) 1385 offset = P1CR2; 1386 ksz_pread8(dev, port, offset, &data); 1387 data &= ~dev->port_mask; 1388 data |= (member & dev->port_mask); 1389 ksz_pwrite8(dev, port, offset, data); 1390 } 1391 1392 static void ksz8_flush_dyn_mac_table(struct dsa_switch *ds, int port) 1393 { 1394 struct ksz_device *dev = ds->priv; 1395 u8 learn[DSA_MAX_PORTS]; 1396 int first, index, cnt; 1397 const u16 *regs; 1398 int reg = S_FLUSH_TABLE_CTRL; 1399 int mask = SW_FLUSH_DYN_MAC_TABLE; 1400 1401 regs = dev->info->regs; 1402 1403 if ((uint)port < dev->info->port_cnt) { 1404 first = port; 1405 cnt = port + 1; 1406 } else { 1407 /* Flush all ports. */ 1408 first = 0; 1409 cnt = dev->info->port_cnt; 1410 } 1411 for (index = first; index < cnt; index++) { 1412 ksz_pread8(dev, index, regs[P_STP_CTRL], &learn[index]); 1413 if (!(learn[index] & PORT_LEARN_DISABLE)) 1414 ksz_pwrite8(dev, index, regs[P_STP_CTRL], 1415 learn[index] | PORT_LEARN_DISABLE); 1416 } 1417 if (ksz_is_ksz8463(dev)) { 1418 reg = KSZ8463_FLUSH_TABLE_CTRL; 1419 mask = KSZ8463_FLUSH_DYN_MAC_TABLE; 1420 } 1421 ksz_cfg(dev, reg, mask, true); 1422 for (index = first; index < cnt; index++) { 1423 if (!(learn[index] & PORT_LEARN_DISABLE)) 1424 ksz_pwrite8(dev, index, regs[P_STP_CTRL], learn[index]); 1425 } 1426 } 1427 1428 static int ksz8_fdb_dump(struct dsa_switch *ds, int port, 1429 dsa_fdb_dump_cb_t *cb, void *data) 1430 { 1431 struct ksz_device *dev = ds->priv; 1432 u8 mac[ETH_ALEN]; 1433 u8 src_port, fid; 1434 u16 entries = 0; 1435 int ret, i; 1436 1437 for (i = 0; i < KSZ8_DYN_MAC_ENTRIES; i++) { 1438 ret = ksz8_r_dyn_mac_table(dev, i, mac, &fid, &src_port, 1439 &entries); 1440 if (ret) 1441 return ret; 1442 1443 if (i >= entries) 1444 return 0; 1445 1446 if (port == src_port) { 1447 ret = cb(mac, fid, false, data); 1448 if (ret) 1449 return ret; 1450 } 1451 } 1452 1453 return 0; 1454 } 1455 1456 static int ksz8_add_sta_mac(struct ksz_device *dev, int port, 1457 const unsigned char *addr, u16 vid) 1458 { 1459 struct alu_struct alu; 1460 int index, ret; 1461 int empty = 0; 1462 1463 alu.port_forward = 0; 1464 for (index = 0; index < dev->info->num_statics; index++) { 1465 bool valid; 1466 1467 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid); 1468 if (ret) 1469 return ret; 1470 if (!valid) { 1471 /* Remember the first empty entry. */ 1472 if (!empty) 1473 empty = index + 1; 1474 continue; 1475 } 1476 1477 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid) 1478 break; 1479 } 1480 1481 /* no available entry */ 1482 if (index == dev->info->num_statics && !empty) 1483 return -ENOSPC; 1484 1485 /* add entry */ 1486 if (index == dev->info->num_statics) { 1487 index = empty - 1; 1488 memset(&alu, 0, sizeof(alu)); 1489 memcpy(alu.mac, addr, ETH_ALEN); 1490 alu.is_static = true; 1491 } 1492 alu.port_forward |= BIT(port); 1493 if (vid) { 1494 alu.is_use_fid = true; 1495 1496 /* Need a way to map VID to FID. */ 1497 alu.fid = vid; 1498 } 1499 1500 return ksz8_w_sta_mac_table(dev, index, &alu); 1501 } 1502 1503 static int ksz8_del_sta_mac(struct ksz_device *dev, int port, 1504 const unsigned char *addr, u16 vid) 1505 { 1506 struct alu_struct alu; 1507 int index, ret; 1508 1509 for (index = 0; index < dev->info->num_statics; index++) { 1510 bool valid; 1511 1512 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid); 1513 if (ret) 1514 return ret; 1515 if (!valid) 1516 continue; 1517 1518 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid) 1519 break; 1520 } 1521 1522 /* no available entry */ 1523 if (index == dev->info->num_statics) 1524 return 0; 1525 1526 /* clear port */ 1527 alu.port_forward &= ~BIT(port); 1528 if (!alu.port_forward) 1529 alu.is_static = false; 1530 1531 return ksz8_w_sta_mac_table(dev, index, &alu); 1532 } 1533 1534 static int ksz8_mdb_add(struct dsa_switch *ds, int port, 1535 const struct switchdev_obj_port_mdb *mdb, 1536 struct dsa_db db) 1537 { 1538 return ksz8_add_sta_mac(ds->priv, port, mdb->addr, mdb->vid); 1539 } 1540 1541 static int ksz8_mdb_del(struct dsa_switch *ds, int port, 1542 const struct switchdev_obj_port_mdb *mdb, 1543 struct dsa_db db) 1544 { 1545 return ksz8_del_sta_mac(ds->priv, port, mdb->addr, mdb->vid); 1546 } 1547 1548 static int ksz8_fdb_add(struct dsa_switch *ds, int port, 1549 const unsigned char *addr, u16 vid, struct dsa_db db) 1550 { 1551 return ksz8_add_sta_mac(ds->priv, port, addr, vid); 1552 } 1553 1554 static int ksz8_fdb_del(struct dsa_switch *ds, int port, 1555 const unsigned char *addr, u16 vid, struct dsa_db db) 1556 { 1557 return ksz8_del_sta_mac(ds->priv, port, addr, vid); 1558 } 1559 1560 static int ksz8_port_vlan_filtering(struct dsa_switch *ds, int port, bool flag, 1561 struct netlink_ext_ack *extack) 1562 { 1563 struct ksz_device *dev = ds->priv; 1564 1565 if (ksz_is_ksz88x3(dev)) 1566 return -ENOTSUPP; 1567 1568 /* Discard packets with VID not enabled on the switch */ 1569 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag); 1570 1571 /* Discard packets with VID not enabled on the ingress port */ 1572 for (port = 0; port < dev->phy_port_cnt; ++port) 1573 ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER, 1574 flag); 1575 1576 return 0; 1577 } 1578 1579 static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state) 1580 { 1581 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) { 1582 int reg = REG_SW_INSERT_SRC_PVID; 1583 1584 if (ksz_is_ksz8463(dev)) 1585 reg = KSZ8463_REG_SW_CTRL_9; 1586 ksz_cfg(dev, reg, 0x03 << (4 - 2 * port), state); 1587 } else { 1588 ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00); 1589 } 1590 } 1591 1592 static int ksz8_port_vlan_add(struct dsa_switch *ds, int port, 1593 const struct switchdev_obj_port_vlan *vlan, 1594 struct netlink_ext_ack *extack) 1595 { 1596 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1597 struct ksz_device *dev = ds->priv; 1598 struct ksz_port *p = &dev->ports[port]; 1599 u16 data, new_pvid = 0; 1600 u8 fid, member, valid; 1601 1602 if (ksz_is_ksz88x3(dev)) 1603 return -ENOTSUPP; 1604 1605 /* If a VLAN is added with untagged flag different from the 1606 * port's Remove Tag flag, we need to change the latter. 1607 * Ignore VID 0, which is always untagged. 1608 * Ignore CPU port, which will always be tagged. 1609 */ 1610 if (untagged != p->remove_tag && vlan->vid != 0 && 1611 port != dev->cpu_port) { 1612 unsigned int vid; 1613 1614 /* Reject attempts to add a VLAN that requires the 1615 * Remove Tag flag to be changed, unless there are no 1616 * other VLANs currently configured. 1617 */ 1618 for (vid = 1; vid < dev->info->num_vlans; ++vid) { 1619 /* Skip the VID we are going to add or reconfigure */ 1620 if (vid == vlan->vid) 1621 continue; 1622 1623 ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0], 1624 &fid, &member, &valid); 1625 if (valid && (member & BIT(port))) 1626 return -EINVAL; 1627 } 1628 1629 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged); 1630 p->remove_tag = untagged; 1631 } 1632 1633 ksz8_r_vlan_table(dev, vlan->vid, &data); 1634 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1635 1636 /* First time to setup the VLAN entry. */ 1637 if (!valid) { 1638 /* Need to find a way to map VID to FID. */ 1639 fid = 1; 1640 valid = 1; 1641 } 1642 member |= BIT(port); 1643 1644 ksz8_to_vlan(dev, fid, member, valid, &data); 1645 ksz8_w_vlan_table(dev, vlan->vid, data); 1646 1647 /* change PVID */ 1648 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 1649 new_pvid = vlan->vid; 1650 1651 if (new_pvid) { 1652 u16 vid; 1653 1654 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid); 1655 vid &= ~VLAN_VID_MASK; 1656 vid |= new_pvid; 1657 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid); 1658 1659 ksz8_port_enable_pvid(dev, port, true); 1660 } 1661 1662 return 0; 1663 } 1664 1665 static int ksz8_port_vlan_del(struct dsa_switch *ds, int port, 1666 const struct switchdev_obj_port_vlan *vlan) 1667 { 1668 struct ksz_device *dev = ds->priv; 1669 u8 fid, member, valid; 1670 u16 data, pvid; 1671 1672 if (ksz_is_ksz88x3(dev)) 1673 return -ENOTSUPP; 1674 1675 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid); 1676 pvid = pvid & 0xFFF; 1677 1678 ksz8_r_vlan_table(dev, vlan->vid, &data); 1679 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1680 1681 member &= ~BIT(port); 1682 1683 /* Invalidate the entry if no more member. */ 1684 if (!member) { 1685 fid = 0; 1686 valid = 0; 1687 } 1688 1689 ksz8_to_vlan(dev, fid, member, valid, &data); 1690 ksz8_w_vlan_table(dev, vlan->vid, data); 1691 1692 if (pvid == vlan->vid) 1693 ksz8_port_enable_pvid(dev, port, false); 1694 1695 return 0; 1696 } 1697 1698 static int ksz8_port_mirror_add(struct dsa_switch *ds, int port, 1699 struct dsa_mall_mirror_tc_entry *mirror, 1700 bool ingress, struct netlink_ext_ack *extack) 1701 { 1702 struct ksz_device *dev = ds->priv; 1703 int offset = P_MIRROR_CTRL; 1704 1705 if (ksz_is_ksz8463(dev)) 1706 offset = P1CR2; 1707 if (ingress) { 1708 ksz_port_cfg(dev, port, offset, PORT_MIRROR_RX, true); 1709 dev->mirror_rx |= BIT(port); 1710 } else { 1711 ksz_port_cfg(dev, port, offset, PORT_MIRROR_TX, true); 1712 dev->mirror_tx |= BIT(port); 1713 } 1714 1715 ksz_port_cfg(dev, port, offset, PORT_MIRROR_SNIFFER, false); 1716 1717 /* configure mirror port */ 1718 if (dev->mirror_rx || dev->mirror_tx) 1719 ksz_port_cfg(dev, mirror->to_local_port, offset, 1720 PORT_MIRROR_SNIFFER, true); 1721 1722 return 0; 1723 } 1724 1725 static void ksz8_port_mirror_del(struct dsa_switch *ds, int port, 1726 struct dsa_mall_mirror_tc_entry *mirror) 1727 { 1728 struct ksz_device *dev = ds->priv; 1729 int offset = P_MIRROR_CTRL; 1730 u8 data; 1731 1732 if (ksz_is_ksz8463(dev)) 1733 offset = P1CR2; 1734 if (mirror->ingress) { 1735 ksz_port_cfg(dev, port, offset, PORT_MIRROR_RX, false); 1736 dev->mirror_rx &= ~BIT(port); 1737 } else { 1738 ksz_port_cfg(dev, port, offset, PORT_MIRROR_TX, false); 1739 dev->mirror_tx &= ~BIT(port); 1740 } 1741 1742 ksz_pread8(dev, port, offset, &data); 1743 1744 if (!dev->mirror_rx && !dev->mirror_tx) 1745 ksz_port_cfg(dev, mirror->to_local_port, offset, 1746 PORT_MIRROR_SNIFFER, false); 1747 } 1748 1749 static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port) 1750 { 1751 struct ksz_port *p = &dev->ports[port]; 1752 1753 if (!ksz_is_ksz87xx(dev)) 1754 return; 1755 1756 if (!p->interface && dev->compat_interface) { 1757 dev_warn(dev->dev, 1758 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1759 "Please update your device tree.\n", 1760 port); 1761 p->interface = dev->compat_interface; 1762 } 1763 } 1764 1765 static void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1766 { 1767 const u16 *regs = dev->info->regs; 1768 struct dsa_switch *ds = dev->ds; 1769 const u32 *masks; 1770 int offset; 1771 u8 member; 1772 1773 masks = dev->info->masks; 1774 1775 /* enable broadcast storm limit */ 1776 offset = P_BCAST_STORM_CTRL; 1777 if (ksz_is_ksz8463(dev)) 1778 offset = P1CR1; 1779 ksz_port_cfg(dev, port, offset, PORT_BROADCAST_STORM, true); 1780 1781 ksz8_port_queue_split(dev, port, dev->info->num_tx_queues); 1782 1783 /* replace priority */ 1784 offset = P_802_1P_CTRL; 1785 if (ksz_is_ksz8463(dev)) 1786 offset = P1CR2; 1787 ksz_port_cfg(dev, port, offset, 1788 masks[PORT_802_1P_REMAPPING], false); 1789 1790 if (cpu_port) 1791 member = dsa_user_ports(ds); 1792 else 1793 member = BIT(dsa_upstream_port(ds, port)); 1794 1795 ksz8_cfg_port_member(dev, port, member); 1796 1797 /* Disable all WoL options by default. Otherwise 1798 * ksz_switch_macaddr_get/put logic will not work properly. 1799 * CPU port 4 has no WoL functionality. 1800 */ 1801 if (ksz_is_ksz87xx(dev) && !cpu_port) 1802 ksz8_pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 0); 1803 } 1804 1805 static int ksz8_dsa_port_setup(struct dsa_switch *ds, int port) 1806 { 1807 struct ksz_device *dev = ds->priv; 1808 1809 if (!dsa_is_user_port(ds, port)) 1810 return 0; 1811 1812 ksz8_port_setup(dev, port, false); 1813 return ksz_dcb_init_port(dev, port); 1814 } 1815 1816 static void ksz88x3_config_rmii_clk(struct ksz_device *dev) 1817 { 1818 struct dsa_port *cpu_dp = dsa_to_port(dev->ds, dev->cpu_port); 1819 bool rmii_clk_internal; 1820 1821 if (!ksz_is_ksz88x3(dev)) 1822 return; 1823 1824 rmii_clk_internal = of_property_read_bool(cpu_dp->dn, 1825 "microchip,rmii-clk-internal"); 1826 1827 ksz_cfg(dev, KSZ88X3_REG_FVID_AND_HOST_MODE, 1828 KSZ88X3_PORT3_RMII_CLK_INTERNAL, rmii_clk_internal); 1829 } 1830 1831 static void ksz8_config_cpu_port(struct dsa_switch *ds) 1832 { 1833 struct ksz_device *dev = ds->priv; 1834 struct ksz_port *p; 1835 const u32 *masks; 1836 const u16 *regs; 1837 u8 remote; 1838 u8 fiber_ports = 0; 1839 int i; 1840 1841 masks = dev->info->masks; 1842 regs = dev->info->regs; 1843 1844 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true); 1845 1846 ksz8_port_setup(dev, dev->cpu_port, true); 1847 1848 ksz8795_cpu_interface_select(dev, dev->cpu_port); 1849 ksz88x3_config_rmii_clk(dev); 1850 1851 for (i = 0; i < dev->phy_port_cnt; i++) { 1852 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1853 } 1854 for (i = 0; i < dev->phy_port_cnt; i++) { 1855 p = &dev->ports[i]; 1856 1857 /* For KSZ8795 family. */ 1858 if (ksz_is_ksz87xx(dev)) { 1859 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote); 1860 if (remote & KSZ8_PORT_FIBER_MODE) 1861 p->fiber = 1; 1862 } 1863 if (p->fiber) 1864 ksz_port_cfg(dev, i, regs[P_STP_CTRL], 1865 PORT_FORCE_FLOW_CTRL, true); 1866 else 1867 ksz_port_cfg(dev, i, regs[P_STP_CTRL], 1868 PORT_FORCE_FLOW_CTRL, false); 1869 if (p->fiber) 1870 fiber_ports |= (1 << i); 1871 } 1872 if (ksz_is_ksz8463(dev)) { 1873 /* Setup fiber ports. */ 1874 if (fiber_ports) { 1875 fiber_ports &= 3; 1876 regmap_update_bits(ksz_regmap_16(dev), 1877 KSZ8463_REG_CFG_CTRL, 1878 fiber_ports << PORT_COPPER_MODE_S, 1879 0); 1880 regmap_update_bits(ksz_regmap_16(dev), 1881 KSZ8463_REG_DSP_CTRL_6, 1882 COPPER_RECEIVE_ADJUSTMENT, 0); 1883 } 1884 1885 /* Turn off PTP function as the switch's proprietary way of 1886 * handling timestamp is not supported in current Linux PTP 1887 * stack implementation. 1888 */ 1889 regmap_update_bits(ksz_regmap_16(dev), 1890 KSZ8463_PTP_MSG_CONF1, 1891 PTP_ENABLE, 0); 1892 regmap_update_bits(ksz_regmap_16(dev), 1893 KSZ8463_PTP_CLK_CTRL, 1894 PTP_CLK_ENABLE, 0); 1895 } 1896 } 1897 1898 /** 1899 * ksz8_phy_port_link_up - Configures ports with integrated PHYs 1900 * @dev: The KSZ device instance. 1901 * @port: The port number to configure. 1902 * @duplex: The desired duplex mode. 1903 * @tx_pause: If true, enables transmit pause. 1904 * @rx_pause: If true, enables receive pause. 1905 * 1906 * Description: 1907 * The function configures flow control settings for a given port based on the 1908 * desired settings and current duplex mode. 1909 * 1910 * According to the KSZ8873 datasheet, the PORT_FORCE_FLOW_CTRL bit in the 1911 * Port Control 2 register (0x1A for Port 1, 0x22 for Port 2, 0x32 for Port 3) 1912 * determines how flow control is handled on the port: 1913 * "1 = will always enable full-duplex flow control on the port, regardless 1914 * of AN result. 1915 * 0 = full-duplex flow control is enabled based on AN result." 1916 * 1917 * This means that the flow control behavior depends on the state of this bit: 1918 * - If PORT_FORCE_FLOW_CTRL is set to 1, the switch will ignore AN results and 1919 * force flow control on the port. 1920 * - If PORT_FORCE_FLOW_CTRL is set to 0, the switch will enable or disable 1921 * flow control based on the AN results. 1922 * 1923 * However, there is a potential limitation in this configuration. It is 1924 * currently not possible to force disable flow control on a port if we still 1925 * advertise pause support. While such a configuration is not currently 1926 * supported by Linux, and may not make practical sense, it's important to be 1927 * aware of this limitation when working with the KSZ8873 and similar devices. 1928 */ 1929 static void ksz8_phy_port_link_up(struct ksz_device *dev, int port, int duplex, 1930 bool tx_pause, bool rx_pause) 1931 { 1932 const u16 *regs = dev->info->regs; 1933 u8 sctrl = 0; 1934 1935 /* The KSZ8795 switch differs from the KSZ8873 by supporting 1936 * asymmetric pause control. However, since a single bit is used to 1937 * control both RX and TX pause, we can't enforce asymmetric pause 1938 * control - both TX and RX pause will be either enabled or disabled 1939 * together. 1940 * 1941 * If auto-negotiation is enabled, we usually allow the flow control to 1942 * be determined by the auto-negotiation process based on the 1943 * capabilities of both link partners. However, for KSZ8873, the 1944 * PORT_FORCE_FLOW_CTRL bit may be set by the hardware bootstrap, 1945 * ignoring the auto-negotiation result. Thus, even in auto-negotiation 1946 * mode, we need to ensure that the PORT_FORCE_FLOW_CTRL bit is 1947 * properly cleared. 1948 * 1949 * In the absence of pause auto-negotiation, we will enforce symmetric 1950 * pause control for both variants of switches - KSZ8873 and KSZ8795. 1951 * 1952 * Autoneg Pause Autoneg rx,tx PORT_FORCE_FLOW_CTRL 1953 * 1 1 x 0 1954 * 0 1 x 0 (flow control probably disabled) 1955 * x 0 1 1 (flow control force enabled) 1956 * 1 0 0 0 (flow control still depends on 1957 * aneg result due to hardware) 1958 * 0 0 0 0 (flow control probably disabled) 1959 */ 1960 if (dev->ports[port].manual_flow && tx_pause) 1961 sctrl |= PORT_FORCE_FLOW_CTRL; 1962 1963 ksz_prmw8(dev, port, regs[P_STP_CTRL], PORT_FORCE_FLOW_CTRL, sctrl); 1964 } 1965 1966 /** 1967 * ksz8_cpu_port_link_up - Configures the CPU port of the switch. 1968 * @dev: The KSZ device instance. 1969 * @speed: The desired link speed. 1970 * @duplex: The desired duplex mode. 1971 * @tx_pause: If true, enables transmit pause. 1972 * @rx_pause: If true, enables receive pause. 1973 * 1974 * Description: 1975 * The function configures flow control and speed settings for the CPU 1976 * port of the switch based on the desired settings, current duplex mode, and 1977 * speed. 1978 */ 1979 static void ksz8_cpu_port_link_up(struct ksz_device *dev, int speed, int duplex, 1980 bool tx_pause, bool rx_pause) 1981 { 1982 const u16 *regs = dev->info->regs; 1983 u8 ctrl = 0; 1984 1985 /* SW_FLOW_CTRL, SW_HALF_DUPLEX, and SW_10_MBIT bits are bootstrappable 1986 * at least on KSZ8873. They can have different values depending on your 1987 * board setup. 1988 */ 1989 if (tx_pause || rx_pause) 1990 ctrl |= SW_FLOW_CTRL; 1991 1992 if (duplex == DUPLEX_HALF) 1993 ctrl |= SW_HALF_DUPLEX; 1994 1995 /* This hardware only supports SPEED_10 and SPEED_100. For SPEED_10 1996 * we need to set the SW_10_MBIT bit. Otherwise, we can leave it 0. 1997 */ 1998 if (speed == SPEED_10) 1999 ctrl |= SW_10_MBIT; 2000 2001 ksz_rmw8(dev, regs[S_BROADCAST_CTRL], SW_HALF_DUPLEX | SW_FLOW_CTRL | 2002 SW_10_MBIT, ctrl); 2003 } 2004 2005 static void ksz8_phylink_mac_link_up(struct phylink_config *config, 2006 struct phy_device *phydev, 2007 unsigned int mode, 2008 phy_interface_t interface, 2009 int speed, int duplex, 2010 bool tx_pause, bool rx_pause) 2011 { 2012 struct dsa_port *dp = dsa_phylink_to_port(config); 2013 struct ksz_device *dev = dp->ds->priv; 2014 int port = dp->index; 2015 2016 /* If the port is the CPU port, apply special handling. Only the CPU 2017 * port is configured via global registers. 2018 */ 2019 if (dev->cpu_port == port) 2020 ksz8_cpu_port_link_up(dev, speed, duplex, tx_pause, rx_pause); 2021 else if (dev->info->internal_phy[port]) 2022 ksz8_phy_port_link_up(dev, port, duplex, tx_pause, rx_pause); 2023 } 2024 2025 static int ksz8_handle_global_errata(struct dsa_switch *ds) 2026 { 2027 struct ksz_device *dev = ds->priv; 2028 int ret = 0; 2029 2030 /* KSZ87xx Errata DS80000687C. 2031 * Module 2: Link drops with some EEE link partners. 2032 * An issue with the EEE next page exchange between the 2033 * KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in 2034 * the link dropping. 2035 */ 2036 if (dev->info->ksz87xx_eee_link_erratum) 2037 ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0); 2038 2039 return ret; 2040 } 2041 2042 static int ksz8_enable_stp_addr(struct ksz_device *dev) 2043 { 2044 struct alu_struct alu; 2045 2046 /* Setup STP address for STP operation. */ 2047 memset(&alu, 0, sizeof(alu)); 2048 ether_addr_copy(alu.mac, eth_stp_addr); 2049 alu.is_static = true; 2050 alu.is_override = true; 2051 alu.port_forward = dev->info->cpu_ports; 2052 2053 return ksz8_w_sta_mac_table(dev, 0, &alu); 2054 } 2055 2056 static int ksz8_setup(struct dsa_switch *ds) 2057 { 2058 struct ksz_device *dev = ds->priv; 2059 u16 storm_mask, storm_rate; 2060 struct dsa_port *dp; 2061 struct ksz_port *p; 2062 const u16 *regs; 2063 int i, ret; 2064 2065 regs = dev->info->regs; 2066 2067 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 2068 dev->info->num_vlans, GFP_KERNEL); 2069 if (!dev->vlan_cache) 2070 return -ENOMEM; 2071 2072 ret = ksz8_reset_switch(dev); 2073 if (ret) { 2074 dev_err(ds->dev, "failed to reset switch\n"); 2075 return ret; 2076 } 2077 2078 ret = ksz_parse_drive_strength(dev); 2079 if (ret) 2080 return ret; 2081 2082 /* set broadcast storm protection 10% rate */ 2083 storm_mask = BROADCAST_STORM_RATE; 2084 storm_rate = (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100; 2085 if (ksz_is_ksz8463(dev)) { 2086 storm_mask = swab16(storm_mask); 2087 storm_rate = swab16(storm_rate); 2088 } 2089 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL], 2090 storm_mask, storm_rate); 2091 2092 ksz8_config_cpu_port(ds); 2093 2094 ksz8_enable_stp_addr(dev); 2095 2096 ds->num_tx_queues = dev->info->num_tx_queues; 2097 2098 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL], 2099 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE); 2100 2101 ksz_init_mib_timer(dev); 2102 2103 ds->configure_vlan_while_not_filtering = false; 2104 ds->dscp_prio_mapping_is_global = true; 2105 ds->mtu_enforcement_ingress = true; 2106 2107 /* We rely on software untagging on the CPU port, so that we 2108 * can support both tagged and untagged VLANs 2109 */ 2110 ds->untag_bridge_pvid = true; 2111 2112 /* VLAN filtering is partly controlled by the global VLAN 2113 * Enable flag 2114 */ 2115 ds->vlan_filtering_is_global = true; 2116 2117 /* Enable automatic fast aging when link changed detected. */ 2118 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true); 2119 2120 /* Enable aggressive back off algorithm in half duplex mode. */ 2121 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_AGGR_BACKOFF, SW_AGGR_BACKOFF); 2122 if (ret) 2123 return ret; 2124 2125 /* 2126 * Make sure unicast VLAN boundary is set as default and 2127 * enable no excessive collision drop. 2128 */ 2129 ret = ksz_rmw8(dev, REG_SW_CTRL_2, 2130 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP, 2131 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP); 2132 if (ret) 2133 return ret; 2134 2135 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false); 2136 2137 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 2138 2139 if (!ksz_is_ksz88x3(dev) && !ksz_is_ksz8463(dev)) 2140 ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true); 2141 2142 for (i = 0; i < (dev->info->num_vlans / 4); i++) 2143 ksz8_r_vlan_entries(dev, i); 2144 2145 /* Make sure PME (WoL) is not enabled. If requested, it will 2146 * be enabled by ksz_wol_pre_shutdown(). Otherwise, some PMICs 2147 * do not like PME events changes before shutdown. PME only 2148 * available on KSZ87xx family. 2149 */ 2150 if (ksz_is_ksz87xx(dev)) { 2151 ret = ksz8_pme_write8(dev, regs[REG_SW_PME_CTRL], 0); 2152 if (!ret) 2153 ret = ksz_rmw8(dev, REG_INT_ENABLE, INT_PME, 0); 2154 if (ret) 2155 return ret; 2156 } 2157 2158 /* Initialize KSZ87xx short-cable preset control */ 2159 dev->eq_init = KSZ87XX_DSP_EQ_INIT_FACTORY; 2160 dev->lpf_bw = KSZ87XX_PHY_LPF_90MHZ; 2161 2162 ret = ksz8_handle_global_errata(ds); 2163 if (ret) 2164 return ret; 2165 2166 /* Start with learning disabled on standalone user ports, and enabled 2167 * on the CPU port. In lack of other finer mechanisms, learning on the 2168 * CPU port will avoid flooding bridge local addresses on the network 2169 * in some cases. 2170 */ 2171 p = &dev->ports[dev->cpu_port]; 2172 p->learning = true; 2173 2174 if (dev->irq > 0) { 2175 ret = ksz_girq_setup(dev); 2176 if (ret) 2177 return ret; 2178 2179 dsa_switch_for_each_user_port(dp, dev->ds) { 2180 ret = ksz_pirq_setup(dev, dp->index); 2181 if (ret) 2182 goto port_release; 2183 2184 if (dev->info->ptp_capable) { 2185 ret = ksz_ptp_irq_setup(ds, dp->index); 2186 if (ret) 2187 goto pirq_release; 2188 } 2189 } 2190 } 2191 2192 if (dev->info->ptp_capable) { 2193 ret = ksz_ptp_clock_register(ds); 2194 if (ret) { 2195 dev_err(dev->dev, "Failed to register PTP clock: %d\n", 2196 ret); 2197 goto port_release; 2198 } 2199 } 2200 2201 ret = ksz_mdio_register(dev); 2202 if (ret < 0) { 2203 dev_err(dev->dev, "failed to register the mdio"); 2204 goto out_ptp_clock_unregister; 2205 } 2206 2207 ret = ksz_dcb_init(dev); 2208 if (ret) 2209 goto out_ptp_clock_unregister; 2210 2211 /* start switch */ 2212 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL], 2213 SW_START, SW_START); 2214 2215 return 0; 2216 2217 out_ptp_clock_unregister: 2218 if (dev->info->ptp_capable) 2219 ksz_ptp_clock_unregister(ds); 2220 port_release: 2221 if (dev->irq > 0) { 2222 dsa_switch_for_each_user_port_continue_reverse(dp, dev->ds) { 2223 if (dev->info->ptp_capable) 2224 ksz_ptp_irq_free(ds, dp->index); 2225 pirq_release: 2226 ksz_irq_free(&dev->ports[dp->index].pirq); 2227 } 2228 ksz_irq_free(&dev->girq); 2229 } 2230 2231 return ret; 2232 } 2233 2234 static void ksz8_phylink_get_caps(struct dsa_switch *ds, int port, 2235 struct phylink_config *config) 2236 { 2237 struct ksz_device *dev = ds->priv; 2238 2239 config->mac_capabilities = MAC_10 | MAC_100; 2240 2241 /* Silicon Errata Sheet (DS80000830A): 2242 * "Port 1 does not respond to received flow control PAUSE frames" 2243 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3 2244 * switches. 2245 */ 2246 if (!ksz_is_ksz88x3(dev) || port) 2247 config->mac_capabilities |= MAC_SYM_PAUSE; 2248 2249 /* Asym pause is not supported on KSZ8863 and KSZ8873 */ 2250 if (!ksz_is_ksz88x3(dev)) 2251 config->mac_capabilities |= MAC_ASYM_PAUSE; 2252 2253 ksz_phylink_get_caps(ds, port, config); 2254 } 2255 2256 static u32 ksz8_get_port_addr(int port, int offset) 2257 { 2258 return PORT_CTRL_ADDR(port, offset); 2259 } 2260 2261 static u32 ksz8463_get_port_addr(int port, int offset) 2262 { 2263 return offset + 0x18 * port; 2264 } 2265 2266 static u16 ksz8463_get_phy_addr(u16 phy, u16 reg, u16 offset) 2267 { 2268 return offset + reg * 2 + phy * (P2MBCR - P1MBCR); 2269 } 2270 2271 static int ksz8463_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) 2272 { 2273 u16 sw_reg = 0; 2274 u16 data = 0; 2275 int ret; 2276 2277 if (phy > 1) 2278 return -ENOSPC; 2279 switch (reg) { 2280 case MII_PHYSID1: 2281 sw_reg = ksz8463_get_phy_addr(phy, 0, PHY1IHR); 2282 break; 2283 case MII_PHYSID2: 2284 sw_reg = ksz8463_get_phy_addr(phy, 0, PHY1ILR); 2285 break; 2286 case MII_BMCR: 2287 case MII_BMSR: 2288 case MII_ADVERTISE: 2289 case MII_LPA: 2290 sw_reg = ksz8463_get_phy_addr(phy, reg, P1MBCR); 2291 break; 2292 case MII_TPISTATUS: 2293 /* This register holds the PHY interrupt status for simulated 2294 * Micrel KSZ PHY. 2295 */ 2296 data = 0x0505; 2297 break; 2298 default: 2299 break; 2300 } 2301 if (sw_reg) { 2302 ret = ksz_read16(dev, sw_reg, &data); 2303 if (ret) 2304 return ret; 2305 } 2306 *val = data; 2307 2308 return 0; 2309 } 2310 2311 static int ksz8463_phy_read16(struct dsa_switch *ds, int addr, int reg) 2312 { 2313 struct ksz_device *dev = ds->priv; 2314 u16 val = 0xffff; 2315 int ret; 2316 2317 ret = ksz8463_r_phy(dev, addr, reg, &val); 2318 if (ret) 2319 return ret; 2320 2321 return val; 2322 } 2323 2324 static int ksz8463_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) 2325 { 2326 u16 sw_reg = 0; 2327 int ret; 2328 2329 if (phy > 1) 2330 return -ENOSPC; 2331 2332 /* No write to fiber port. */ 2333 if (dev->ports[phy].fiber) 2334 return 0; 2335 switch (reg) { 2336 case MII_BMCR: 2337 case MII_ADVERTISE: 2338 sw_reg = ksz8463_get_phy_addr(phy, reg, P1MBCR); 2339 break; 2340 default: 2341 break; 2342 } 2343 if (sw_reg) { 2344 ret = ksz_write16(dev, sw_reg, val); 2345 if (ret) 2346 return ret; 2347 } 2348 2349 return 0; 2350 } 2351 2352 static int ksz8463_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val) 2353 { 2354 struct ksz_device *dev = ds->priv; 2355 int ret; 2356 2357 ret = ksz8463_w_phy(dev, addr, reg, val); 2358 if (ret) 2359 return ret; 2360 2361 return 0; 2362 } 2363 2364 static u32 ksz88xx_get_phy_flags(struct dsa_switch *ds, int port) 2365 { 2366 struct ksz_device *dev = ds->priv; 2367 2368 switch (dev->chip_id) { 2369 case KSZ88X3_CHIP_ID: 2370 /* Silicon Errata Sheet (DS80000830A): 2371 * Port 1 does not work with LinkMD Cable-Testing. 2372 * Port 1 does not respond to received PAUSE control frames. 2373 */ 2374 if (!port) 2375 return MICREL_KSZ8_P1_ERRATA; 2376 break; 2377 } 2378 2379 return 0; 2380 } 2381 2382 static int ksz8_switch_init(struct ksz_device *dev) 2383 { 2384 dev->cpu_port = fls(dev->info->cpu_ports) - 1; 2385 dev->phy_port_cnt = dev->info->port_cnt - 1; 2386 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports; 2387 2388 return 0; 2389 } 2390 2391 static enum dsa_tag_protocol ksz8463_get_tag_protocol(struct dsa_switch *ds, 2392 int port, 2393 enum dsa_tag_protocol mp) 2394 { 2395 return DSA_TAG_PROTO_KSZ9893; 2396 } 2397 2398 static int ksz8463_connect_tag_protocol(struct dsa_switch *ds, 2399 enum dsa_tag_protocol proto) 2400 { 2401 struct ksz_tagger_data *tagger_data; 2402 2403 if (proto != DSA_TAG_PROTO_KSZ9893) 2404 return -EPROTONOSUPPORT; 2405 2406 tagger_data = ksz_tagger_data(ds); 2407 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 2408 2409 return 0; 2410 } 2411 2412 static enum dsa_tag_protocol ksz87xx_get_tag_protocol(struct dsa_switch *ds, 2413 int port, 2414 enum dsa_tag_protocol mp) 2415 { 2416 return DSA_TAG_PROTO_KSZ8795; 2417 } 2418 2419 static int ksz87xx_connect_tag_protocol(struct dsa_switch *ds, 2420 enum dsa_tag_protocol proto) 2421 { 2422 if (proto != DSA_TAG_PROTO_KSZ8795) 2423 return -EPROTONOSUPPORT; 2424 2425 return 0; 2426 } 2427 2428 static enum dsa_tag_protocol ksz88xx_get_tag_protocol(struct dsa_switch *ds, 2429 int port, 2430 enum dsa_tag_protocol mp) 2431 { 2432 struct ksz_device *dev = ds->priv; 2433 2434 if (ksz_is_8895_family(dev)) /* KSZ8864, KSZ8895 */ 2435 return DSA_TAG_PROTO_KSZ8795; 2436 2437 return DSA_TAG_PROTO_KSZ9893; 2438 } 2439 2440 static int ksz88xx_connect_tag_protocol(struct dsa_switch *ds, 2441 enum dsa_tag_protocol proto) 2442 { 2443 struct ksz_tagger_data *tagger_data; 2444 2445 if (ksz_is_8895_family(ds->priv)) { /* KSZ8864, KSZ8895 */ 2446 if (proto != DSA_TAG_PROTO_KSZ8795) 2447 return -EPROTONOSUPPORT; 2448 2449 return 0; 2450 } 2451 2452 if (proto != DSA_TAG_PROTO_KSZ9893) 2453 return -EPROTONOSUPPORT; 2454 2455 tagger_data = ksz_tagger_data(ds); 2456 tagger_data->xmit_work_fn = ksz_port_deferred_xmit; 2457 2458 return 0; 2459 } 2460 2461 static void ksz88x3_phylink_mac_config(struct phylink_config *config, 2462 unsigned int mode, 2463 const struct phylink_link_state *state) 2464 { 2465 struct dsa_port *dp = dsa_phylink_to_port(config); 2466 struct ksz_device *dev = dp->ds->priv; 2467 2468 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN); 2469 } 2470 2471 const struct phylink_mac_ops ksz88x3_phylink_mac_ops = { 2472 .mac_config = ksz88x3_phylink_mac_config, 2473 .mac_link_down = ksz_phylink_mac_link_down, 2474 .mac_link_up = ksz8_phylink_mac_link_up, 2475 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 2476 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 2477 }; 2478 2479 const struct phylink_mac_ops ksz8_phylink_mac_ops = { 2480 .mac_config = ksz_phylink_mac_config, 2481 .mac_link_down = ksz_phylink_mac_link_down, 2482 .mac_link_up = ksz8_phylink_mac_link_up, 2483 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi, 2484 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi, 2485 }; 2486 2487 const struct ksz_dev_ops ksz8463_dev_ops = { 2488 .get_port_addr = ksz8463_get_port_addr, 2489 .cfg_port_member = ksz8_cfg_port_member, 2490 .r_mib_cnt = ksz8_r_mib_cnt, 2491 .r_mib_pkt = ksz8_r_mib_pkt, 2492 .r_mib_stat64 = ksz88xx_r_mib_stats64, 2493 .freeze_mib = ksz8_freeze_mib, 2494 .port_init_cnt = ksz8_port_init_cnt, 2495 .init = ksz8_switch_init, 2496 }; 2497 2498 const struct ksz_dev_ops ksz87xx_dev_ops = { 2499 .get_port_addr = ksz8_get_port_addr, 2500 .cfg_port_member = ksz8_cfg_port_member, 2501 .r_mib_cnt = ksz8_r_mib_cnt, 2502 .r_mib_pkt = ksz8_r_mib_pkt, 2503 .r_mib_stat64 = ksz_r_mib_stats64, 2504 .freeze_mib = ksz8_freeze_mib, 2505 .port_init_cnt = ksz8_port_init_cnt, 2506 .init = ksz8_switch_init, 2507 .pme_write8 = ksz8_pme_write8, 2508 .pme_pread8 = ksz8_pme_pread8, 2509 .pme_pwrite8 = ksz8_pme_pwrite8, 2510 }; 2511 2512 const struct ksz_dev_ops ksz88xx_dev_ops = { 2513 .get_port_addr = ksz8_get_port_addr, 2514 .cfg_port_member = ksz8_cfg_port_member, 2515 .r_mib_cnt = ksz8_r_mib_cnt, 2516 .r_mib_pkt = ksz8_r_mib_pkt, 2517 .r_mib_stat64 = ksz88xx_r_mib_stats64, 2518 .freeze_mib = ksz8_freeze_mib, 2519 .port_init_cnt = ksz8_port_init_cnt, 2520 .init = ksz8_switch_init, 2521 .pme_write8 = ksz8_pme_write8, 2522 .pme_pread8 = ksz8_pme_pread8, 2523 .pme_pwrite8 = ksz8_pme_pwrite8, 2524 }; 2525 2526 const struct dsa_switch_ops ksz8463_switch_ops = { 2527 .get_tag_protocol = ksz8463_get_tag_protocol, 2528 .connect_tag_protocol = ksz8463_connect_tag_protocol, 2529 .setup = ksz8_setup, 2530 .teardown = ksz_teardown, 2531 .phy_read = ksz8463_phy_read16, 2532 .phy_write = ksz8463_phy_write16, 2533 .phylink_get_caps = ksz8_phylink_get_caps, 2534 .port_setup = ksz8_dsa_port_setup, 2535 .get_strings = ksz_get_strings, 2536 .get_ethtool_stats = ksz_get_ethtool_stats, 2537 .get_sset_count = ksz_sset_count, 2538 .port_bridge_join = ksz_port_bridge_join, 2539 .port_bridge_leave = ksz_port_bridge_leave, 2540 .port_set_mac_address = ksz_port_set_mac_address, 2541 .port_stp_state_set = ksz_port_stp_state_set, 2542 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 2543 .port_bridge_flags = ksz_port_bridge_flags, 2544 .port_fast_age = ksz8_flush_dyn_mac_table, 2545 .port_fdb_dump = ksz8_fdb_dump, 2546 .port_fdb_add = ksz8_fdb_add, 2547 .port_fdb_del = ksz8_fdb_del, 2548 .port_mdb_add = ksz8_mdb_add, 2549 .port_mdb_del = ksz8_mdb_del, 2550 .port_mirror_add = ksz8_port_mirror_add, 2551 .port_mirror_del = ksz8_port_mirror_del, 2552 .get_stats64 = ksz_get_stats64, 2553 .get_pause_stats = ksz_get_pause_stats, 2554 .port_change_mtu = ksz8_change_mtu, 2555 .port_max_mtu = ksz_max_mtu, 2556 .suspend = ksz_suspend, 2557 .resume = ksz_resume, 2558 .get_ts_info = ksz_get_ts_info, 2559 .port_hwtstamp_get = ksz_hwtstamp_get, 2560 .port_hwtstamp_set = ksz_hwtstamp_set, 2561 .port_txtstamp = ksz_port_txtstamp, 2562 .port_rxtstamp = ksz_port_rxtstamp, 2563 .port_setup_tc = ksz_setup_tc, 2564 .port_get_default_prio = ksz_port_get_default_prio, 2565 .port_set_default_prio = ksz_port_set_default_prio, 2566 .port_get_dscp_prio = ksz_port_get_dscp_prio, 2567 .port_add_dscp_prio = ksz_port_add_dscp_prio, 2568 .port_del_dscp_prio = ksz_port_del_dscp_prio, 2569 .port_get_apptrust = ksz_port_get_apptrust, 2570 .port_set_apptrust = ksz_port_set_apptrust, 2571 }; 2572 2573 const struct dsa_switch_ops ksz87xx_switch_ops = { 2574 .get_tag_protocol = ksz87xx_get_tag_protocol, 2575 .connect_tag_protocol = ksz87xx_connect_tag_protocol, 2576 .setup = ksz8_setup, 2577 .teardown = ksz_teardown, 2578 .phy_read = ksz8_phy_read16, 2579 .phy_write = ksz8_phy_write16, 2580 .phylink_get_caps = ksz8_phylink_get_caps, 2581 .port_setup = ksz8_dsa_port_setup, 2582 .get_strings = ksz_get_strings, 2583 .get_ethtool_stats = ksz_get_ethtool_stats, 2584 .get_sset_count = ksz_sset_count, 2585 .port_bridge_join = ksz_port_bridge_join, 2586 .port_bridge_leave = ksz_port_bridge_leave, 2587 .port_set_mac_address = ksz_port_set_mac_address, 2588 .port_stp_state_set = ksz_port_stp_state_set, 2589 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 2590 .port_bridge_flags = ksz_port_bridge_flags, 2591 .port_fast_age = ksz8_flush_dyn_mac_table, 2592 .port_vlan_filtering = ksz8_port_vlan_filtering, 2593 .port_vlan_add = ksz8_port_vlan_add, 2594 .port_vlan_del = ksz8_port_vlan_del, 2595 .port_fdb_dump = ksz8_fdb_dump, 2596 .port_fdb_add = ksz8_fdb_add, 2597 .port_fdb_del = ksz8_fdb_del, 2598 .port_mdb_add = ksz8_mdb_add, 2599 .port_mdb_del = ksz8_mdb_del, 2600 .port_mirror_add = ksz8_port_mirror_add, 2601 .port_mirror_del = ksz8_port_mirror_del, 2602 .get_stats64 = ksz_get_stats64, 2603 .get_pause_stats = ksz_get_pause_stats, 2604 .port_change_mtu = ksz8_change_mtu, 2605 .port_max_mtu = ksz_max_mtu, 2606 .suspend = ksz_suspend, 2607 .resume = ksz_resume, 2608 .get_ts_info = ksz_get_ts_info, 2609 .port_hwtstamp_get = ksz_hwtstamp_get, 2610 .port_hwtstamp_set = ksz_hwtstamp_set, 2611 .port_txtstamp = ksz_port_txtstamp, 2612 .port_rxtstamp = ksz_port_rxtstamp, 2613 .port_setup_tc = ksz_setup_tc, 2614 .port_get_default_prio = ksz_port_get_default_prio, 2615 .port_set_default_prio = ksz_port_set_default_prio, 2616 .port_get_dscp_prio = ksz_port_get_dscp_prio, 2617 .port_add_dscp_prio = ksz_port_add_dscp_prio, 2618 .port_del_dscp_prio = ksz_port_del_dscp_prio, 2619 .port_get_apptrust = ksz_port_get_apptrust, 2620 .port_set_apptrust = ksz_port_set_apptrust, 2621 }; 2622 2623 const struct dsa_switch_ops ksz88xx_switch_ops = { 2624 .get_tag_protocol = ksz88xx_get_tag_protocol, 2625 .connect_tag_protocol = ksz88xx_connect_tag_protocol, 2626 .get_phy_flags = ksz88xx_get_phy_flags, 2627 .setup = ksz8_setup, 2628 .teardown = ksz_teardown, 2629 .phy_read = ksz8_phy_read16, 2630 .phy_write = ksz8_phy_write16, 2631 .phylink_get_caps = ksz8_phylink_get_caps, 2632 .port_setup = ksz8_dsa_port_setup, 2633 .get_strings = ksz_get_strings, 2634 .get_ethtool_stats = ksz_get_ethtool_stats, 2635 .get_sset_count = ksz_sset_count, 2636 .port_bridge_join = ksz_port_bridge_join, 2637 .port_bridge_leave = ksz_port_bridge_leave, 2638 .port_set_mac_address = ksz_port_set_mac_address, 2639 .port_stp_state_set = ksz_port_stp_state_set, 2640 .port_pre_bridge_flags = ksz_port_pre_bridge_flags, 2641 .port_bridge_flags = ksz_port_bridge_flags, 2642 .port_fast_age = ksz8_flush_dyn_mac_table, 2643 .port_vlan_filtering = ksz8_port_vlan_filtering, 2644 .port_vlan_add = ksz8_port_vlan_add, 2645 .port_vlan_del = ksz8_port_vlan_del, 2646 .port_fdb_dump = ksz8_fdb_dump, 2647 .port_fdb_add = ksz8_fdb_add, 2648 .port_fdb_del = ksz8_fdb_del, 2649 .port_mdb_add = ksz8_mdb_add, 2650 .port_mdb_del = ksz8_mdb_del, 2651 .port_mirror_add = ksz8_port_mirror_add, 2652 .port_mirror_del = ksz8_port_mirror_del, 2653 .get_stats64 = ksz_get_stats64, 2654 .get_pause_stats = ksz_get_pause_stats, 2655 .port_change_mtu = ksz8_change_mtu, 2656 .port_max_mtu = ksz_max_mtu, 2657 .get_wol = ksz_get_wol, 2658 .set_wol = ksz_set_wol, 2659 .suspend = ksz_suspend, 2660 .resume = ksz_resume, 2661 .get_ts_info = ksz_get_ts_info, 2662 .port_hwtstamp_get = ksz_hwtstamp_get, 2663 .port_hwtstamp_set = ksz_hwtstamp_set, 2664 .port_txtstamp = ksz_port_txtstamp, 2665 .port_rxtstamp = ksz_port_rxtstamp, 2666 .port_setup_tc = ksz_setup_tc, 2667 .port_get_default_prio = ksz_port_get_default_prio, 2668 .port_set_default_prio = ksz_port_set_default_prio, 2669 .port_get_dscp_prio = ksz_port_get_dscp_prio, 2670 .port_add_dscp_prio = ksz_port_add_dscp_prio, 2671 .port_del_dscp_prio = ksz_port_del_dscp_prio, 2672 .port_get_apptrust = ksz_port_get_apptrust, 2673 .port_set_apptrust = ksz_port_set_apptrust, 2674 }; 2675 2676 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>"); 2677 MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver"); 2678 MODULE_LICENSE("GPL"); 2679