1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Microchip KSZ8XXX series switch driver
4 *
5 * It supports the following switches:
6 * - KSZ8463
7 * - KSZ8863, KSZ8873 aka KSZ88X3
8 * - KSZ8895, KSZ8864 aka KSZ8895 family
9 * - KSZ8794, KSZ8795, KSZ8765 aka KSZ87XX
10 * Note that it does NOT support:
11 * - KSZ8563, KSZ8567 - see KSZ9477 driver
12 *
13 * Copyright (C) 2017 Microchip Technology Inc.
14 * Tristram Ha <Tristram.Ha@microchip.com>
15 */
16
17 #include <linux/bitfield.h>
18 #include <linux/delay.h>
19 #include <linux/dsa/ksz_common.h>
20 #include <linux/export.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/if_vlan.h>
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/platform_data/microchip-ksz.h>
26 #include <linux/phy.h>
27 #include <linux/etherdevice.h>
28 #include <linux/if_bridge.h>
29 #include <linux/micrel_phy.h>
30 #include <net/dsa.h>
31 #include <net/switchdev.h>
32 #include <linux/phylink.h>
33
34 #include "ksz_common.h"
35 #include "ksz_dcb.h"
36 #include "ksz8_reg.h"
37 #include "ksz8.h"
38
39 /*
40 * We use only the high-byte (so odd addresses) of the 16-bits registers to fit
41 * in the common IRQ framework
42 */
43 #define KSZ8463_REG_ISR 0x191
44 #define KSZ8463_REG_IER 0x193
45
46 /* ksz88x3_drive_strengths - Drive strength mapping for KSZ8863, KSZ8873, ..
47 * variants.
48 * This values are documented in KSZ8873 and KSZ8863 datasheets.
49 */
50 static const struct ksz_drive_strength ksz88x3_drive_strengths[] = {
51 { 0, 8000 },
52 { KSZ8873_DRIVE_STRENGTH_16MA, 16000 },
53 };
54
55 struct ksz88xx_stats_raw {
56 u64 rx;
57 u64 rx_hi;
58 u64 rx_undersize;
59 u64 rx_fragments;
60 u64 rx_oversize;
61 u64 rx_jabbers;
62 u64 rx_symbol_err;
63 u64 rx_crc_err;
64 u64 rx_align_err;
65 u64 rx_mac_ctrl;
66 u64 rx_pause;
67 u64 rx_bcast;
68 u64 rx_mcast;
69 u64 rx_ucast;
70 u64 rx_64_or_less;
71 u64 rx_65_127;
72 u64 rx_128_255;
73 u64 rx_256_511;
74 u64 rx_512_1023;
75 u64 rx_1024_1522;
76 u64 tx;
77 u64 tx_hi;
78 u64 tx_late_col;
79 u64 tx_pause;
80 u64 tx_bcast;
81 u64 tx_mcast;
82 u64 tx_ucast;
83 u64 tx_deferred;
84 u64 tx_total_col;
85 u64 tx_exc_col;
86 u64 tx_single_col;
87 u64 tx_mult_col;
88 u64 rx_discards;
89 u64 tx_discards;
90 };
91
ksz_cfg(struct ksz_device * dev,u32 addr,u8 bits,bool set)92 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
93 {
94 ksz_rmw8(dev, addr, bits, set ? bits : 0);
95 }
96
ksz_port_cfg(struct ksz_device * dev,int port,int offset,u8 bits,bool set)97 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
98 bool set)
99 {
100 ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), bits,
101 set ? bits : 0);
102 }
103
104 /**
105 * ksz8_ind_write8 - EEE/ACL/PME indirect register write
106 * @dev: The device structure.
107 * @table: Function & table select, register 110.
108 * @addr: Indirect access control, register 111.
109 * @data: The data to be written.
110 *
111 * This function performs an indirect register write for EEE, ACL or
112 * PME switch functionalities. Both 8-bit registers 110 and 111 are
113 * written at once with ksz_write16, using the serial multiple write
114 * functionality.
115 *
116 * Return: 0 on success, or an error code on failure.
117 */
ksz8_ind_write8(struct ksz_device * dev,u8 table,u16 addr,u8 data)118 static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data)
119 {
120 const u16 *regs;
121 u16 ctrl_addr;
122 int ret = 0;
123
124 regs = dev->info->regs;
125
126 mutex_lock(&dev->alu_mutex);
127
128 ctrl_addr = IND_ACC_TABLE(table) | addr;
129 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
130 if (!ret)
131 ret = ksz_write8(dev, regs[REG_IND_BYTE], data);
132
133 mutex_unlock(&dev->alu_mutex);
134
135 return ret;
136 }
137
138 /**
139 * ksz8_ind_read8 - EEE/ACL/PME indirect register read
140 * @dev: The device structure.
141 * @table: Function & table select, register 110.
142 * @addr: Indirect access control, register 111.
143 * @val: The value read.
144 *
145 * This function performs an indirect register read for EEE, ACL or
146 * PME switch functionalities. Both 8-bit registers 110 and 111 are
147 * written at once with ksz_write16, using the serial multiple write
148 * functionality.
149 *
150 * Return: 0 on success, or an error code on failure.
151 */
ksz8_ind_read8(struct ksz_device * dev,u8 table,u16 addr,u8 * val)152 static int ksz8_ind_read8(struct ksz_device *dev, u8 table, u16 addr, u8 *val)
153 {
154 const u16 *regs;
155 u16 ctrl_addr;
156 int ret = 0;
157
158 regs = dev->info->regs;
159
160 mutex_lock(&dev->alu_mutex);
161
162 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
163 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
164 if (!ret)
165 ret = ksz_read8(dev, regs[REG_IND_BYTE], val);
166
167 mutex_unlock(&dev->alu_mutex);
168
169 return ret;
170 }
171
ksz8_pme_write8(struct ksz_device * dev,u32 reg,u8 value)172 static int ksz8_pme_write8(struct ksz_device *dev, u32 reg, u8 value)
173 {
174 return ksz8_ind_write8(dev, (u8)(reg >> 8), (u8)(reg), value);
175 }
176
ksz8_pme_pread8(struct ksz_device * dev,int port,int offset,u8 * data)177 static int ksz8_pme_pread8(struct ksz_device *dev, int port, int offset, u8 *data)
178 {
179 u8 table = (u8)(offset >> 8 | (port + 1));
180
181 return ksz8_ind_read8(dev, table, (u8)(offset), data);
182 }
183
ksz8_pme_pwrite8(struct ksz_device * dev,int port,int offset,u8 data)184 static int ksz8_pme_pwrite8(struct ksz_device *dev, int port, int offset, u8 data)
185 {
186 u8 table = (u8)(offset >> 8 | (port + 1));
187
188 return ksz8_ind_write8(dev, table, (u8)(offset), data);
189 }
190
ksz8463_irq_mask(struct irq_data * d)191 static void ksz8463_irq_mask(struct irq_data *d)
192 {
193 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
194
195 kirq->masked &= ~BIT(d->hwirq);
196 }
197
ksz8463_irq_unmask(struct irq_data * d)198 static void ksz8463_irq_unmask(struct irq_data *d)
199 {
200 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
201
202 kirq->masked |= BIT(d->hwirq);
203 }
204
205 static const struct irq_chip ksz8463_irq_chip = {
206 .name = "ksz8463-irq",
207 .irq_mask = ksz8463_irq_mask,
208 .irq_unmask = ksz8463_irq_unmask,
209 .irq_bus_lock = ksz_irq_bus_lock,
210 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock,
211 };
212
ksz8463_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)213 static int ksz8463_irq_domain_map(struct irq_domain *d,
214 unsigned int irq, irq_hw_number_t hwirq)
215 {
216 irq_set_chip_data(irq, d->host_data);
217 irq_set_chip_and_handler(irq, &ksz8463_irq_chip, handle_level_irq);
218 irq_set_noprobe(irq);
219
220 return 0;
221 }
222
223 static const struct irq_domain_ops ksz8463_irq_domain_ops = {
224 .map = ksz8463_irq_domain_map,
225 .xlate = irq_domain_xlate_twocell,
226 };
227
ksz8463_girq_setup(struct ksz_device * dev)228 static int ksz8463_girq_setup(struct ksz_device *dev)
229 {
230 struct ksz_irq *girq = &dev->girq;
231
232 girq->nirqs = 8;
233 girq->reg_mask = KSZ8463_REG_IER;
234 girq->reg_status = KSZ8463_REG_ISR;
235 girq->masked = 0;
236 snprintf(girq->name, sizeof(girq->name), "ksz8463-girq");
237
238 girq->irq_num = dev->irq;
239
240 return ksz_irq_common_setup(dev, girq, &ksz8463_irq_domain_ops);
241 }
242
ksz8463_reset_switch(struct ksz_device * dev)243 static int ksz8463_reset_switch(struct ksz_device *dev)
244 {
245 ksz_cfg(dev, KSZ8463_REG_SW_RESET,
246 KSZ8463_GLOBAL_SOFTWARE_RESET | KSZ8463_PTP_SOFTWARE_RESET,
247 true);
248 ksz_cfg(dev, KSZ8463_REG_SW_RESET,
249 KSZ8463_GLOBAL_SOFTWARE_RESET | KSZ8463_PTP_SOFTWARE_RESET,
250 false);
251 return 0;
252 }
253
ksz8_reset_switch(struct ksz_device * dev)254 static int ksz8_reset_switch(struct ksz_device *dev)
255 {
256 if (ksz_is_ksz88x3(dev)) {
257 /* reset switch */
258 ksz_cfg(dev, KSZ8863_REG_SW_RESET,
259 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true);
260 ksz_cfg(dev, KSZ8863_REG_SW_RESET,
261 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false);
262 } else {
263 /* reset switch */
264 ksz_write8(dev, REG_POWER_MANAGEMENT_1,
265 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S);
266 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0);
267 }
268
269 return 0;
270 }
271
ksz88xx_change_mtu(struct dsa_switch * ds,int port,int mtu)272 static int ksz88xx_change_mtu(struct dsa_switch *ds, int port, int mtu)
273 {
274 struct ksz_device *dev = ds->priv;
275 int frame_size;
276 u8 ctrl2 = 0;
277
278 if (!dsa_is_cpu_port(dev->ds, port))
279 return 0;
280
281 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
282
283 if (frame_size <= KSZ8_LEGAL_PACKET_SIZE)
284 ctrl2 |= KSZ8863_LEGAL_PACKET_ENABLE;
285 else if (frame_size > KSZ8863_NORMAL_PACKET_SIZE)
286 ctrl2 |= KSZ8863_HUGE_PACKET_ENABLE;
287
288 return ksz_rmw8(dev, REG_SW_CTRL_2, KSZ8863_LEGAL_PACKET_ENABLE |
289 KSZ8863_HUGE_PACKET_ENABLE, ctrl2);
290 }
291
ksz87xx_change_mtu(struct dsa_switch * ds,int port,int mtu)292 static int ksz87xx_change_mtu(struct dsa_switch *ds, int port, int mtu)
293 {
294 struct ksz_device *dev = ds->priv;
295 u8 ctrl1 = 0, ctrl2 = 0;
296 u16 frame_size;
297 int ret;
298
299 if (!dsa_is_cpu_port(dev->ds, port))
300 return 0;
301
302 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
303
304 if (frame_size > KSZ8_LEGAL_PACKET_SIZE)
305 ctrl2 |= SW_LEGAL_PACKET_DISABLE;
306 if (frame_size > KSZ8863_NORMAL_PACKET_SIZE)
307 ctrl1 |= SW_HUGE_PACKET;
308
309 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_HUGE_PACKET, ctrl1);
310 if (ret)
311 return ret;
312
313 return ksz_rmw8(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, ctrl2);
314 }
315
ksz87xx_max_mtu(struct dsa_switch * ds,int port)316 static int ksz87xx_max_mtu(struct dsa_switch *ds, int port)
317 {
318 return KSZ8795_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
319 }
320
ksz88xx_max_mtu(struct dsa_switch * ds,int port)321 static int ksz88xx_max_mtu(struct dsa_switch *ds, int port)
322 {
323 return KSZ8863_HUGE_PACKET_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN;
324 }
325
ksz8_port_queue_split(struct ksz_device * dev,int port,int queues)326 static int ksz8_port_queue_split(struct ksz_device *dev, int port, int queues)
327 {
328 u8 mask_4q, mask_2q;
329 u8 reg_4q, reg_2q;
330 u8 data_4q = 0;
331 u8 data_2q = 0;
332 int ret;
333
334 if (ksz_is_ksz88x3(dev)) {
335 mask_4q = KSZ8873_PORT_4QUEUE_SPLIT_EN;
336 mask_2q = KSZ8873_PORT_2QUEUE_SPLIT_EN;
337 reg_4q = REG_PORT_CTRL_0;
338 reg_2q = REG_PORT_CTRL_2;
339
340 /* KSZ8795 family switches have Weighted Fair Queueing (WFQ)
341 * enabled by default. Enable it for KSZ8873 family switches
342 * too. Default value for KSZ8873 family is strict priority,
343 * which should be enabled by using TC_SETUP_QDISC_ETS, not
344 * by default.
345 */
346 ret = ksz_rmw8(dev, REG_SW_CTRL_3, WEIGHTED_FAIR_QUEUE_ENABLE,
347 WEIGHTED_FAIR_QUEUE_ENABLE);
348 if (ret)
349 return ret;
350 } else if (ksz_is_ksz8463(dev)) {
351 mask_4q = KSZ8873_PORT_4QUEUE_SPLIT_EN;
352 mask_2q = KSZ8873_PORT_2QUEUE_SPLIT_EN;
353 reg_4q = P1CR1;
354 reg_2q = P1CR1 + 1;
355 } else {
356 mask_4q = KSZ8795_PORT_4QUEUE_SPLIT_EN;
357 mask_2q = KSZ8795_PORT_2QUEUE_SPLIT_EN;
358 reg_4q = REG_PORT_CTRL_13;
359 reg_2q = REG_PORT_CTRL_0;
360
361 /* TODO: this is legacy from initial KSZ8795 driver, should be
362 * moved to appropriate place in the future.
363 */
364 ret = ksz_rmw8(dev, REG_SW_CTRL_19,
365 SW_OUT_RATE_LIMIT_QUEUE_BASED,
366 SW_OUT_RATE_LIMIT_QUEUE_BASED);
367 if (ret)
368 return ret;
369 }
370
371 if (queues == 4)
372 data_4q = mask_4q;
373 else if (queues == 2)
374 data_2q = mask_2q;
375
376 ret = ksz_prmw8(dev, port, reg_4q, mask_4q, data_4q);
377 if (ret)
378 return ret;
379
380 return ksz_prmw8(dev, port, reg_2q, mask_2q, data_2q);
381 }
382
ksz8_r_mib_cnt(struct ksz_device * dev,int port,u16 addr,u64 * cnt)383 static void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt)
384 {
385 const u32 *masks;
386 const u16 *regs;
387 u16 ctrl_addr;
388 u32 data;
389 u8 check;
390 int loop;
391
392 masks = dev->info->masks;
393 regs = dev->info->regs;
394
395 ctrl_addr = addr + dev->info->reg_mib_cnt * port;
396 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
397
398 mutex_lock(&dev->alu_mutex);
399 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
400
401 /* It is almost guaranteed to always read the valid bit because of
402 * slow SPI speed.
403 */
404 for (loop = 2; loop > 0; loop--) {
405 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
406
407 if (check & masks[MIB_COUNTER_VALID]) {
408 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
409 if (check & masks[MIB_COUNTER_OVERFLOW])
410 *cnt += MIB_COUNTER_VALUE + 1;
411 *cnt += data & MIB_COUNTER_VALUE;
412 break;
413 }
414 }
415 mutex_unlock(&dev->alu_mutex);
416 }
417
ksz8795_r_mib_pkt(struct ksz_device * dev,int port,u16 addr,u64 * dropped,u64 * cnt)418 static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
419 u64 *dropped, u64 *cnt)
420 {
421 const u32 *masks;
422 const u16 *regs;
423 u16 ctrl_addr;
424 u32 data;
425 u8 check;
426 int loop;
427
428 masks = dev->info->masks;
429 regs = dev->info->regs;
430
431 addr -= dev->info->reg_mib_cnt;
432 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port;
433 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0;
434 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
435
436 mutex_lock(&dev->alu_mutex);
437 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
438
439 /* It is almost guaranteed to always read the valid bit because of
440 * slow SPI speed.
441 */
442 for (loop = 2; loop > 0; loop--) {
443 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
444
445 if (check & masks[MIB_COUNTER_VALID]) {
446 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
447 if (addr < 2) {
448 u64 total;
449
450 total = check & MIB_TOTAL_BYTES_H;
451 total <<= 32;
452 *cnt += total;
453 *cnt += data;
454 if (check & masks[MIB_COUNTER_OVERFLOW]) {
455 total = MIB_TOTAL_BYTES_H + 1;
456 total <<= 32;
457 *cnt += total;
458 }
459 } else {
460 if (check & masks[MIB_COUNTER_OVERFLOW])
461 *cnt += MIB_PACKET_DROPPED + 1;
462 *cnt += data & MIB_PACKET_DROPPED;
463 }
464 break;
465 }
466 }
467 mutex_unlock(&dev->alu_mutex);
468 }
469
ksz8863_r_mib_pkt(struct ksz_device * dev,int port,u16 addr,u64 * dropped,u64 * cnt)470 static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
471 u64 *dropped, u64 *cnt)
472 {
473 u32 *last = (u32 *)dropped;
474 const u16 *regs;
475 u16 ctrl_addr;
476 u32 data;
477 u32 cur;
478
479 regs = dev->info->regs;
480
481 addr -= dev->info->reg_mib_cnt;
482 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 :
483 KSZ8863_MIB_PACKET_DROPPED_RX_0;
484 if (ksz_is_8895_family(dev) &&
485 ctrl_addr == KSZ8863_MIB_PACKET_DROPPED_RX_0)
486 ctrl_addr = KSZ8895_MIB_PACKET_DROPPED_RX_0;
487 ctrl_addr += port;
488 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
489
490 mutex_lock(&dev->alu_mutex);
491 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
492 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
493 mutex_unlock(&dev->alu_mutex);
494
495 data &= MIB_PACKET_DROPPED;
496 cur = last[addr];
497 if (data != cur) {
498 last[addr] = data;
499 if (data < cur)
500 data += MIB_PACKET_DROPPED + 1;
501 data -= cur;
502 *cnt += data;
503 }
504 }
505
ksz8_r_mib_pkt(struct ksz_device * dev,int port,u16 addr,u64 * dropped,u64 * cnt)506 static void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
507 u64 *dropped, u64 *cnt)
508 {
509 if (is_ksz88xx(dev))
510 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt);
511 else
512 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt);
513 }
514
ksz8_freeze_mib(struct ksz_device * dev,int port,bool freeze)515 static void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze)
516 {
517 if (is_ksz88xx(dev))
518 return;
519
520 /* enable the port for flush/freeze function */
521 if (freeze)
522 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
523 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze);
524
525 /* disable the port after freeze is done */
526 if (!freeze)
527 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
528 }
529
ksz8_port_init_cnt(struct ksz_device * dev,int port)530 static void ksz8_port_init_cnt(struct ksz_device *dev, int port)
531 {
532 struct ksz_port_mib *mib = &dev->ports[port].mib;
533 u64 *dropped;
534
535 /* For KSZ8795 family. */
536 if (ksz_is_ksz87xx(dev)) {
537 /* flush all enabled port MIB counters */
538 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
539 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true);
540 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
541 }
542
543 mib->cnt_ptr = 0;
544
545 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
546 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
547 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
548 &mib->counters[mib->cnt_ptr]);
549 ++mib->cnt_ptr;
550 }
551
552 /* last one in storage */
553 dropped = &mib->counters[dev->info->mib_cnt];
554
555 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
556 while (mib->cnt_ptr < dev->info->mib_cnt) {
557 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
558 dropped, &mib->counters[mib->cnt_ptr]);
559 ++mib->cnt_ptr;
560 }
561 }
562
ksz8_r_table(struct ksz_device * dev,int table,u16 addr,u64 * data)563 static int ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data)
564 {
565 const u16 *regs;
566 u16 ctrl_addr;
567 int ret;
568
569 regs = dev->info->regs;
570
571 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
572
573 mutex_lock(&dev->alu_mutex);
574 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
575 if (ret)
576 goto unlock_alu;
577
578 ret = ksz_read64(dev, regs[REG_IND_DATA_HI], data);
579 unlock_alu:
580 mutex_unlock(&dev->alu_mutex);
581
582 return ret;
583 }
584
ksz8_w_table(struct ksz_device * dev,int table,u16 addr,u64 data)585 static int ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data)
586 {
587 const u16 *regs;
588 u16 ctrl_addr;
589 int ret;
590
591 regs = dev->info->regs;
592
593 ctrl_addr = IND_ACC_TABLE(table) | addr;
594
595 mutex_lock(&dev->alu_mutex);
596 ret = ksz_write64(dev, regs[REG_IND_DATA_HI], data);
597 if (ret)
598 goto unlock_alu;
599
600 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
601 unlock_alu:
602 mutex_unlock(&dev->alu_mutex);
603
604 return ret;
605 }
606
ksz8_valid_dyn_entry(struct ksz_device * dev,u8 * data)607 static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data)
608 {
609 int timeout = 100;
610 const u32 *masks;
611 const u16 *regs;
612 int ret;
613
614 masks = dev->info->masks;
615 regs = dev->info->regs;
616
617 do {
618 ret = ksz_read8(dev, regs[REG_IND_DATA_CHECK], data);
619 if (ret)
620 return ret;
621
622 timeout--;
623 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout);
624
625 /* Entry is not ready for accessing. */
626 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY])
627 return -ETIMEDOUT;
628
629 /* Entry is ready for accessing. */
630 return ksz_read8(dev, regs[REG_IND_DATA_8], data);
631 }
632
ksz8_r_dyn_mac_table(struct ksz_device * dev,u16 addr,u8 * mac_addr,u8 * fid,u8 * src_port,u16 * entries)633 static int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr, u8 *mac_addr,
634 u8 *fid, u8 *src_port, u16 *entries)
635 {
636 u32 data_hi, data_lo;
637 const u8 *shifts;
638 const u32 *masks;
639 const u16 *regs;
640 u16 ctrl_addr;
641 u64 buf = 0;
642 u8 data;
643 int cnt;
644 int ret;
645
646 shifts = dev->info->shifts;
647 masks = dev->info->masks;
648 regs = dev->info->regs;
649
650 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr;
651
652 mutex_lock(&dev->alu_mutex);
653 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
654 if (ret)
655 goto unlock_alu;
656
657 ret = ksz8_valid_dyn_entry(dev, &data);
658 if (ret)
659 goto unlock_alu;
660
661 if (data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY]) {
662 *entries = 0;
663 goto unlock_alu;
664 }
665
666 ret = ksz_read64(dev, regs[REG_IND_DATA_HI], &buf);
667 if (ret)
668 goto unlock_alu;
669
670 data_hi = (u32)(buf >> 32);
671 data_lo = (u32)buf;
672
673 /* Check out how many valid entry in the table. */
674 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H];
675 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H];
676 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >>
677 shifts[DYNAMIC_MAC_ENTRIES];
678 *entries = cnt + 1;
679
680 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >>
681 shifts[DYNAMIC_MAC_FID];
682 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >>
683 shifts[DYNAMIC_MAC_SRC_PORT];
684
685 mac_addr[5] = (u8)data_lo;
686 mac_addr[4] = (u8)(data_lo >> 8);
687 mac_addr[3] = (u8)(data_lo >> 16);
688 mac_addr[2] = (u8)(data_lo >> 24);
689
690 mac_addr[1] = (u8)data_hi;
691 mac_addr[0] = (u8)(data_hi >> 8);
692
693 unlock_alu:
694 mutex_unlock(&dev->alu_mutex);
695
696 return ret;
697 }
698
ksz8_r_sta_mac_table(struct ksz_device * dev,u16 addr,struct alu_struct * alu,bool * valid)699 static int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr,
700 struct alu_struct *alu, bool *valid)
701 {
702 u32 data_hi, data_lo;
703 const u8 *shifts;
704 const u32 *masks;
705 u64 data;
706 int ret;
707
708 shifts = dev->info->shifts;
709 masks = dev->info->masks;
710
711 ret = ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data);
712 if (ret)
713 return ret;
714
715 data_hi = data >> 32;
716 data_lo = (u32)data;
717
718 if (!(data_hi & (masks[STATIC_MAC_TABLE_VALID] |
719 masks[STATIC_MAC_TABLE_OVERRIDE]))) {
720 *valid = false;
721 return 0;
722 }
723
724 alu->mac[5] = (u8)data_lo;
725 alu->mac[4] = (u8)(data_lo >> 8);
726 alu->mac[3] = (u8)(data_lo >> 16);
727 alu->mac[2] = (u8)(data_lo >> 24);
728 alu->mac[1] = (u8)data_hi;
729 alu->mac[0] = (u8)(data_hi >> 8);
730 alu->port_forward =
731 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >>
732 shifts[STATIC_MAC_FWD_PORTS];
733 alu->is_override = (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0;
734
735 /* KSZ8795/KSZ8895 family switches have STATIC_MAC_TABLE_USE_FID and
736 * STATIC_MAC_TABLE_FID definitions off by 1 when doing read on the
737 * static MAC table compared to doing write.
738 */
739 if (ksz_is_ksz87xx(dev) || ksz_is_8895_family(dev))
740 data_hi >>= 1;
741 alu->is_static = true;
742 alu->is_use_fid = (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0;
743 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >>
744 shifts[STATIC_MAC_FID];
745
746 *valid = true;
747
748 return 0;
749 }
750
ksz8_w_sta_mac_table(struct ksz_device * dev,u16 addr,struct alu_struct * alu)751 static int ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr,
752 struct alu_struct *alu)
753 {
754 u32 data_hi, data_lo;
755 const u8 *shifts;
756 const u32 *masks;
757 u64 data;
758
759 shifts = dev->info->shifts;
760 masks = dev->info->masks;
761
762 data_lo = ((u32)alu->mac[2] << 24) |
763 ((u32)alu->mac[3] << 16) |
764 ((u32)alu->mac[4] << 8) | alu->mac[5];
765 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1];
766 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS];
767
768 if (alu->is_override)
769 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE];
770 if (alu->is_use_fid) {
771 data_hi |= masks[STATIC_MAC_TABLE_USE_FID];
772 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID];
773 }
774 if (alu->is_static)
775 data_hi |= masks[STATIC_MAC_TABLE_VALID];
776 else
777 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE];
778
779 data = (u64)data_hi << 32 | data_lo;
780
781 return ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data);
782 }
783
ksz8_from_vlan(struct ksz_device * dev,u32 vlan,u8 * fid,u8 * member,u8 * valid)784 static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid,
785 u8 *member, u8 *valid)
786 {
787 const u8 *shifts;
788 const u32 *masks;
789
790 shifts = dev->info->shifts;
791 masks = dev->info->masks;
792
793 *fid = vlan & masks[VLAN_TABLE_FID];
794 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >>
795 shifts[VLAN_TABLE_MEMBERSHIP_S];
796 *valid = !!(vlan & masks[VLAN_TABLE_VALID]);
797 }
798
ksz8_to_vlan(struct ksz_device * dev,u8 fid,u8 member,u8 valid,u16 * vlan)799 static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid,
800 u16 *vlan)
801 {
802 const u8 *shifts;
803 const u32 *masks;
804
805 shifts = dev->info->shifts;
806 masks = dev->info->masks;
807
808 *vlan = fid;
809 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S];
810 if (valid)
811 *vlan |= masks[VLAN_TABLE_VALID];
812 }
813
ksz8_r_vlan_entries(struct ksz_device * dev,u16 addr)814 static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr)
815 {
816 const u8 *shifts;
817 u64 data;
818 int i;
819
820 shifts = dev->info->shifts;
821
822 ksz8_r_table(dev, TABLE_VLAN, addr, &data);
823 addr *= 4;
824 for (i = 0; i < 4; i++) {
825 dev->vlan_cache[addr + i].table[0] = (u16)data;
826 data >>= shifts[VLAN_TABLE];
827 }
828 }
829
ksz8_r_vlan_table(struct ksz_device * dev,u16 vid,u16 * vlan)830 static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan)
831 {
832 int index;
833 u16 *data;
834 u16 addr;
835 u64 buf;
836
837 data = (u16 *)&buf;
838 addr = vid / 4;
839 index = vid & 3;
840 ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
841 *vlan = data[index];
842 }
843
ksz8_w_vlan_table(struct ksz_device * dev,u16 vid,u16 vlan)844 static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan)
845 {
846 int index;
847 u16 *data;
848 u16 addr;
849 u64 buf;
850
851 data = (u16 *)&buf;
852 addr = vid / 4;
853 index = vid & 3;
854 ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
855 data[index] = vlan;
856 dev->vlan_cache[vid].table[0] = vlan;
857 ksz8_w_table(dev, TABLE_VLAN, addr, buf);
858 }
859
860 /**
861 * ksz879x_get_loopback - KSZ879x specific function to get loopback
862 * configuration status for a specific port
863 * @dev: Pointer to the device structure
864 * @port: Port number to query
865 * @val: Pointer to store the result
866 *
867 * This function reads the SMI registers to determine whether loopback mode
868 * is enabled for a specific port.
869 *
870 * Return: 0 on success, error code on failure.
871 */
ksz879x_get_loopback(struct ksz_device * dev,u16 port,u16 * val)872 static int ksz879x_get_loopback(struct ksz_device *dev, u16 port,
873 u16 *val)
874 {
875 u8 stat3;
876 int ret;
877
878 ret = ksz_pread8(dev, port, REG_PORT_STATUS_3, &stat3);
879 if (ret)
880 return ret;
881
882 if (stat3 & PORT_PHY_LOOPBACK)
883 *val |= BMCR_LOOPBACK;
884
885 return 0;
886 }
887
888 /**
889 * ksz879x_set_loopback - KSZ879x specific function to set loopback mode for
890 * a specific port
891 * @dev: Pointer to the device structure.
892 * @port: Port number to modify.
893 * @val: Value indicating whether to enable or disable loopback mode.
894 *
895 * This function translates loopback bit of the BMCR register into the
896 * corresponding hardware register bit value and writes it to the SMI interface.
897 *
898 * Return: 0 on success, error code on failure.
899 */
ksz879x_set_loopback(struct ksz_device * dev,u16 port,u16 val)900 static int ksz879x_set_loopback(struct ksz_device *dev, u16 port, u16 val)
901 {
902 u8 stat3 = 0;
903
904 if (val & BMCR_LOOPBACK)
905 stat3 |= PORT_PHY_LOOPBACK;
906
907 return ksz_prmw8(dev, port, REG_PORT_STATUS_3, PORT_PHY_LOOPBACK,
908 stat3);
909 }
910
ksz87xx_apply_low_loss_preset(struct ksz_device * dev,bool enable)911 static int ksz87xx_apply_low_loss_preset(struct ksz_device *dev, bool enable)
912 {
913 /* Apply the Microchip erratum short-cable preset (LPF 62 MHz, EQ init 0)
914 * providing a conservative configuration for short or low-loss cables.
915 */
916 u8 lpf_bw, eq_init;
917 int ret;
918
919 lpf_bw = KSZ87XX_PHY_LPF_62MHZ;
920 eq_init = KSZ87XX_DSP_EQ_INIT_LOW_LOSS;
921
922 if (!ksz_is_ksz87xx(dev))
923 return -EOPNOTSUPP;
924
925 if (!enable) {
926 /* Restore default values (LPF 90 MHz, EQ init 15). */
927 lpf_bw = KSZ87XX_PHY_LPF_90MHZ;
928 eq_init = KSZ87XX_DSP_EQ_INIT_FACTORY;
929 }
930
931 ret = ksz8_ind_write8(dev, TABLE_LINK_MD, KSZ87XX_REG_PHY_LPF, lpf_bw);
932 if (ret)
933 return ret;
934
935 dev->lpf_bw = lpf_bw;
936 ret = ksz8_ind_write8(dev, TABLE_LINK_MD, KSZ87XX_REG_DSP_EQ, eq_init);
937 if (ret)
938 return ret;
939
940 dev->eq_init = eq_init;
941
942 return ret;
943 }
944
945 /**
946 * ksz8_r_phy_ctrl - Translates and reads from the SMI interface to a MIIM PHY
947 * Control register (Reg. 31).
948 * @dev: The KSZ device instance.
949 * @port: The port number to be read.
950 * @val: The value read from the SMI interface.
951 *
952 * This function reads the SMI interface and translates the hardware register
953 * bit values into their corresponding control settings for a MIIM PHY Control
954 * register.
955 *
956 * Return: 0 on success, error code on failure.
957 */
ksz8_r_phy_ctrl(struct ksz_device * dev,int port,u16 * val)958 static int ksz8_r_phy_ctrl(struct ksz_device *dev, int port, u16 *val)
959 {
960 const u16 *regs = dev->info->regs;
961 u8 reg_val;
962 int ret;
963
964 *val = 0;
965
966 ret = ksz_pread8(dev, port, regs[P_LINK_STATUS], ®_val);
967 if (ret < 0)
968 return ret;
969
970 if (reg_val & PORT_MDIX_STATUS)
971 *val |= KSZ886X_CTRL_MDIX_STAT;
972
973 ret = ksz_pread8(dev, port, REG_PORT_LINK_MD_CTRL, ®_val);
974 if (ret < 0)
975 return ret;
976
977 if (reg_val & PORT_FORCE_LINK)
978 *val |= KSZ886X_CTRL_FORCE_LINK;
979
980 if (reg_val & PORT_POWER_SAVING)
981 *val |= KSZ886X_CTRL_PWRSAVE;
982
983 if (reg_val & PORT_PHY_REMOTE_LOOPBACK)
984 *val |= KSZ886X_CTRL_REMOTE_LOOPBACK;
985
986 return 0;
987 }
988
989 /**
990 * ksz8_r_phy_bmcr - Translates and reads from the SMI interface to a MIIM PHY
991 * Basic mode control register (Reg. 0).
992 * @dev: The KSZ device instance.
993 * @port: The port number to be read.
994 * @val: The value read from the SMI interface.
995 *
996 * This function reads the SMI interface and translates the hardware register
997 * bit values into their corresponding control settings for a MIIM PHY Basic
998 * mode control register.
999 *
1000 * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873
1001 * -------------------------------------------------------------------
1002 * MIIM Bit | KSZ8794 Reg/Bit | KSZ8873 Reg/Bit
1003 * ----------------------------+-----------------------------+----------------
1004 * Bit 15 - Soft Reset | 0xF/4 | Not supported
1005 * Bit 14 - Loopback | 0xD/0 (MAC), 0xF/7 (PHY) ~ 0xD/0 (PHY)
1006 * Bit 13 - Force 100 | 0xC/6 = 0xC/6
1007 * Bit 12 - AN Enable | 0xC/7 (reverse logic) ~ 0xC/7
1008 * Bit 11 - Power Down | 0xD/3 = 0xD/3
1009 * Bit 10 - PHY Isolate | 0xF/5 | Not supported
1010 * Bit 9 - Restart AN | 0xD/5 = 0xD/5
1011 * Bit 8 - Force Full-Duplex | 0xC/5 = 0xC/5
1012 * Bit 7 - Collision Test/Res. | Not supported | Not supported
1013 * Bit 6 - Reserved | Not supported | Not supported
1014 * Bit 5 - Hp_mdix | 0x9/7 ~ 0xF/7
1015 * Bit 4 - Force MDI | 0xD/1 = 0xD/1
1016 * Bit 3 - Disable MDIX | 0xD/2 = 0xD/2
1017 * Bit 2 - Disable Far-End F. | ???? | 0xD/4
1018 * Bit 1 - Disable Transmit | 0xD/6 = 0xD/6
1019 * Bit 0 - Disable LED | 0xD/7 = 0xD/7
1020 * -------------------------------------------------------------------
1021 *
1022 * Return: 0 on success, error code on failure.
1023 */
ksz8_r_phy_bmcr(struct ksz_device * dev,u16 port,u16 * val)1024 static int ksz8_r_phy_bmcr(struct ksz_device *dev, u16 port, u16 *val)
1025 {
1026 const u16 *regs = dev->info->regs;
1027 u8 restart, speed, ctrl;
1028 int ret;
1029
1030 *val = 0;
1031
1032 ret = ksz_pread8(dev, port, regs[P_NEG_RESTART_CTRL], &restart);
1033 if (ret)
1034 return ret;
1035
1036 ret = ksz_pread8(dev, port, regs[P_SPEED_STATUS], &speed);
1037 if (ret)
1038 return ret;
1039
1040 ret = ksz_pread8(dev, port, regs[P_FORCE_CTRL], &ctrl);
1041 if (ret)
1042 return ret;
1043
1044 if (ctrl & PORT_FORCE_100_MBIT)
1045 *val |= BMCR_SPEED100;
1046
1047 if (ksz_is_ksz88x3(dev)) {
1048 if (restart & KSZ8873_PORT_PHY_LOOPBACK)
1049 *val |= BMCR_LOOPBACK;
1050
1051 if ((ctrl & PORT_AUTO_NEG_ENABLE))
1052 *val |= BMCR_ANENABLE;
1053 } else {
1054 ret = ksz879x_get_loopback(dev, port, val);
1055 if (ret)
1056 return ret;
1057
1058 if (!(ctrl & PORT_AUTO_NEG_DISABLE))
1059 *val |= BMCR_ANENABLE;
1060 }
1061
1062 if (restart & PORT_POWER_DOWN)
1063 *val |= BMCR_PDOWN;
1064
1065 if (restart & PORT_AUTO_NEG_RESTART)
1066 *val |= BMCR_ANRESTART;
1067
1068 if (ctrl & PORT_FORCE_FULL_DUPLEX)
1069 *val |= BMCR_FULLDPLX;
1070
1071 if (speed & PORT_HP_MDIX)
1072 *val |= KSZ886X_BMCR_HP_MDIX;
1073
1074 if (restart & PORT_FORCE_MDIX)
1075 *val |= KSZ886X_BMCR_FORCE_MDI;
1076
1077 if (restart & PORT_AUTO_MDIX_DISABLE)
1078 *val |= KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1079
1080 if (restart & PORT_TX_DISABLE)
1081 *val |= KSZ886X_BMCR_DISABLE_TRANSMIT;
1082
1083 if (restart & PORT_LED_OFF)
1084 *val |= KSZ886X_BMCR_DISABLE_LED;
1085
1086 return 0;
1087 }
1088
ksz8_r_phy(struct ksz_device * dev,u16 phy,u16 reg,u16 * val)1089 static int ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
1090 {
1091 u8 ctrl, link, val1, val2;
1092 int processed = true;
1093 const u16 *regs;
1094 u16 data = 0;
1095 u16 p = phy;
1096 int ret;
1097
1098 regs = dev->info->regs;
1099
1100 switch (reg) {
1101 case MII_BMCR:
1102 ret = ksz8_r_phy_bmcr(dev, p, &data);
1103 if (ret)
1104 return ret;
1105 break;
1106 case MII_BMSR:
1107 ret = ksz_pread8(dev, p, regs[P_LINK_STATUS], &link);
1108 if (ret)
1109 return ret;
1110
1111 data = BMSR_100FULL |
1112 BMSR_100HALF |
1113 BMSR_10FULL |
1114 BMSR_10HALF |
1115 BMSR_ANEGCAPABLE;
1116 if (link & PORT_AUTO_NEG_COMPLETE)
1117 data |= BMSR_ANEGCOMPLETE;
1118 if (link & PORT_STAT_LINK_GOOD)
1119 data |= BMSR_LSTATUS;
1120 break;
1121 case MII_PHYSID1:
1122 data = KSZ8795_ID_HI;
1123 break;
1124 case MII_PHYSID2:
1125 if (ksz_is_ksz88x3(dev))
1126 data = KSZ8863_ID_LO;
1127 else
1128 data = KSZ8795_ID_LO;
1129 break;
1130 case MII_ADVERTISE:
1131 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
1132 if (ret)
1133 return ret;
1134
1135 data = ADVERTISE_CSMA;
1136 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE)
1137 data |= ADVERTISE_PAUSE_CAP;
1138 if (ctrl & PORT_AUTO_NEG_100BTX_FD)
1139 data |= ADVERTISE_100FULL;
1140 if (ctrl & PORT_AUTO_NEG_100BTX)
1141 data |= ADVERTISE_100HALF;
1142 if (ctrl & PORT_AUTO_NEG_10BT_FD)
1143 data |= ADVERTISE_10FULL;
1144 if (ctrl & PORT_AUTO_NEG_10BT)
1145 data |= ADVERTISE_10HALF;
1146 break;
1147 case MII_LPA:
1148 ret = ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link);
1149 if (ret)
1150 return ret;
1151
1152 data = LPA_SLCT;
1153 if (link & PORT_REMOTE_SYM_PAUSE)
1154 data |= LPA_PAUSE_CAP;
1155 if (link & PORT_REMOTE_100BTX_FD)
1156 data |= LPA_100FULL;
1157 if (link & PORT_REMOTE_100BTX)
1158 data |= LPA_100HALF;
1159 if (link & PORT_REMOTE_10BT_FD)
1160 data |= LPA_10FULL;
1161 if (link & PORT_REMOTE_10BT)
1162 data |= LPA_10HALF;
1163 if (data & ~LPA_SLCT)
1164 data |= LPA_LPACK;
1165 break;
1166 case PHY_REG_LINK_MD:
1167 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1);
1168 if (ret)
1169 return ret;
1170
1171 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2);
1172 if (ret)
1173 return ret;
1174
1175 if (val1 & PORT_START_CABLE_DIAG)
1176 data |= PHY_START_CABLE_DIAG;
1177
1178 if (val1 & PORT_CABLE_10M_SHORT)
1179 data |= PHY_CABLE_10M_SHORT;
1180
1181 data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M,
1182 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1));
1183
1184 data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M,
1185 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) |
1186 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2));
1187 break;
1188 case PHY_REG_PHY_CTRL:
1189 ret = ksz8_r_phy_ctrl(dev, p, &data);
1190 if (ret)
1191 return ret;
1192
1193 break;
1194 case PHY_REG_KSZ87XX_SHORT_CABLE:
1195 if (!ksz_is_ksz87xx(dev))
1196 return -EOPNOTSUPP;
1197 data = !!(dev->lpf_bw == KSZ87XX_PHY_LPF_62MHZ &&
1198 dev->eq_init == KSZ87XX_DSP_EQ_INIT_LOW_LOSS);
1199 break;
1200 case PHY_REG_KSZ87XX_LPF_BW:
1201 if (!ksz_is_ksz87xx(dev))
1202 return -EOPNOTSUPP;
1203 data = dev->lpf_bw;
1204 break;
1205 case PHY_REG_KSZ87XX_EQ_INIT:
1206 if (!ksz_is_ksz87xx(dev))
1207 return -EOPNOTSUPP;
1208 data = dev->eq_init;
1209 break;
1210 default:
1211 processed = false;
1212 break;
1213 }
1214 if (processed)
1215 *val = data;
1216
1217 return 0;
1218 }
1219
ksz8_phy_read16(struct dsa_switch * ds,int addr,int reg)1220 static int ksz8_phy_read16(struct dsa_switch *ds, int addr, int reg)
1221 {
1222 struct ksz_device *dev = ds->priv;
1223 u16 val = 0xffff;
1224 int ret;
1225
1226 ret = ksz8_r_phy(dev, addr, reg, &val);
1227 if (ret)
1228 return ret;
1229
1230 return val;
1231 }
1232
1233 /**
1234 * ksz8_w_phy_ctrl - Translates and writes to the SMI interface from a MIIM PHY
1235 * Control register (Reg. 31).
1236 * @dev: The KSZ device instance.
1237 * @port: The port number to be configured.
1238 * @val: The register value to be written.
1239 *
1240 * This function translates control settings from a MIIM PHY Control register
1241 * into their corresponding hardware register bit values for the SMI
1242 * interface.
1243 *
1244 * Return: 0 on success, error code on failure.
1245 */
ksz8_w_phy_ctrl(struct ksz_device * dev,int port,u16 val)1246 static int ksz8_w_phy_ctrl(struct ksz_device *dev, int port, u16 val)
1247 {
1248 u8 reg_val = 0;
1249 int ret;
1250
1251 if (val & KSZ886X_CTRL_FORCE_LINK)
1252 reg_val |= PORT_FORCE_LINK;
1253
1254 if (val & KSZ886X_CTRL_PWRSAVE)
1255 reg_val |= PORT_POWER_SAVING;
1256
1257 if (val & KSZ886X_CTRL_REMOTE_LOOPBACK)
1258 reg_val |= PORT_PHY_REMOTE_LOOPBACK;
1259
1260 ret = ksz_prmw8(dev, port, REG_PORT_LINK_MD_CTRL, PORT_FORCE_LINK |
1261 PORT_POWER_SAVING | PORT_PHY_REMOTE_LOOPBACK, reg_val);
1262 return ret;
1263 }
1264
1265 /**
1266 * ksz8_w_phy_bmcr - Translates and writes to the SMI interface from a MIIM PHY
1267 * Basic mode control register (Reg. 0).
1268 * @dev: The KSZ device instance.
1269 * @port: The port number to be configured.
1270 * @val: The register value to be written.
1271 *
1272 * This function translates control settings from a MIIM PHY Basic mode control
1273 * register into their corresponding hardware register bit values for the SMI
1274 * interface.
1275 *
1276 * MIIM Bit Mapping Comparison between KSZ8794 and KSZ8873
1277 * -------------------------------------------------------------------
1278 * MIIM Bit | KSZ8794 Reg/Bit | KSZ8873 Reg/Bit
1279 * ----------------------------+-----------------------------+----------------
1280 * Bit 15 - Soft Reset | 0xF/4 | Not supported
1281 * Bit 14 - Loopback | 0xD/0 (MAC), 0xF/7 (PHY) ~ 0xD/0 (PHY)
1282 * Bit 13 - Force 100 | 0xC/6 = 0xC/6
1283 * Bit 12 - AN Enable | 0xC/7 (reverse logic) ~ 0xC/7
1284 * Bit 11 - Power Down | 0xD/3 = 0xD/3
1285 * Bit 10 - PHY Isolate | 0xF/5 | Not supported
1286 * Bit 9 - Restart AN | 0xD/5 = 0xD/5
1287 * Bit 8 - Force Full-Duplex | 0xC/5 = 0xC/5
1288 * Bit 7 - Collision Test/Res. | Not supported | Not supported
1289 * Bit 6 - Reserved | Not supported | Not supported
1290 * Bit 5 - Hp_mdix | 0x9/7 ~ 0xF/7
1291 * Bit 4 - Force MDI | 0xD/1 = 0xD/1
1292 * Bit 3 - Disable MDIX | 0xD/2 = 0xD/2
1293 * Bit 2 - Disable Far-End F. | ???? | 0xD/4
1294 * Bit 1 - Disable Transmit | 0xD/6 = 0xD/6
1295 * Bit 0 - Disable LED | 0xD/7 = 0xD/7
1296 * -------------------------------------------------------------------
1297 *
1298 * Return: 0 on success, error code on failure.
1299 */
ksz8_w_phy_bmcr(struct ksz_device * dev,u16 port,u16 val)1300 static int ksz8_w_phy_bmcr(struct ksz_device *dev, u16 port, u16 val)
1301 {
1302 u8 restart, speed, ctrl, restart_mask;
1303 const u16 *regs = dev->info->regs;
1304 int ret;
1305
1306 /* Do not support PHY reset function. */
1307 if (val & BMCR_RESET)
1308 return 0;
1309
1310 speed = 0;
1311 if (val & KSZ886X_BMCR_HP_MDIX)
1312 speed |= PORT_HP_MDIX;
1313
1314 ret = ksz_prmw8(dev, port, regs[P_SPEED_STATUS], PORT_HP_MDIX, speed);
1315 if (ret)
1316 return ret;
1317
1318 ctrl = 0;
1319 if (ksz_is_ksz88x3(dev)) {
1320 if ((val & BMCR_ANENABLE))
1321 ctrl |= PORT_AUTO_NEG_ENABLE;
1322 } else {
1323 if (!(val & BMCR_ANENABLE))
1324 ctrl |= PORT_AUTO_NEG_DISABLE;
1325
1326 /* Fiber port does not support auto-negotiation. */
1327 if (dev->ports[port].fiber)
1328 ctrl |= PORT_AUTO_NEG_DISABLE;
1329 }
1330
1331 if (val & BMCR_SPEED100)
1332 ctrl |= PORT_FORCE_100_MBIT;
1333
1334 if (val & BMCR_FULLDPLX)
1335 ctrl |= PORT_FORCE_FULL_DUPLEX;
1336
1337 ret = ksz_prmw8(dev, port, regs[P_FORCE_CTRL], PORT_FORCE_100_MBIT |
1338 /* PORT_AUTO_NEG_ENABLE and PORT_AUTO_NEG_DISABLE are the same
1339 * bits
1340 */
1341 PORT_FORCE_FULL_DUPLEX | PORT_AUTO_NEG_ENABLE, ctrl);
1342 if (ret)
1343 return ret;
1344
1345 restart = 0;
1346 restart_mask = PORT_LED_OFF | PORT_TX_DISABLE | PORT_AUTO_NEG_RESTART |
1347 PORT_POWER_DOWN | PORT_AUTO_MDIX_DISABLE | PORT_FORCE_MDIX;
1348
1349 if (val & KSZ886X_BMCR_DISABLE_LED)
1350 restart |= PORT_LED_OFF;
1351
1352 if (val & KSZ886X_BMCR_DISABLE_TRANSMIT)
1353 restart |= PORT_TX_DISABLE;
1354
1355 if (val & BMCR_ANRESTART)
1356 restart |= PORT_AUTO_NEG_RESTART;
1357
1358 if (val & BMCR_PDOWN)
1359 restart |= PORT_POWER_DOWN;
1360
1361 if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX)
1362 restart |= PORT_AUTO_MDIX_DISABLE;
1363
1364 if (val & KSZ886X_BMCR_FORCE_MDI)
1365 restart |= PORT_FORCE_MDIX;
1366
1367 if (ksz_is_ksz88x3(dev)) {
1368 restart_mask |= KSZ8873_PORT_PHY_LOOPBACK;
1369
1370 if (val & BMCR_LOOPBACK)
1371 restart |= KSZ8873_PORT_PHY_LOOPBACK;
1372 } else {
1373 ret = ksz879x_set_loopback(dev, port, val);
1374 if (ret)
1375 return ret;
1376 }
1377
1378 return ksz_prmw8(dev, port, regs[P_NEG_RESTART_CTRL], restart_mask,
1379 restart);
1380 }
1381
ksz8_w_phy(struct ksz_device * dev,u16 phy,u16 reg,u16 val)1382 static int ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
1383 {
1384 const u16 *regs;
1385 u8 ctrl, data;
1386 u16 p = phy;
1387 int ret;
1388
1389 regs = dev->info->regs;
1390
1391 switch (reg) {
1392 case MII_BMCR:
1393 ret = ksz8_w_phy_bmcr(dev, p, val);
1394 if (ret)
1395 return ret;
1396 break;
1397 case MII_ADVERTISE:
1398 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
1399 if (ret)
1400 return ret;
1401
1402 data = ctrl;
1403 data &= ~(PORT_AUTO_NEG_SYM_PAUSE |
1404 PORT_AUTO_NEG_100BTX_FD |
1405 PORT_AUTO_NEG_100BTX |
1406 PORT_AUTO_NEG_10BT_FD |
1407 PORT_AUTO_NEG_10BT);
1408 if (val & ADVERTISE_PAUSE_CAP)
1409 data |= PORT_AUTO_NEG_SYM_PAUSE;
1410 if (val & ADVERTISE_100FULL)
1411 data |= PORT_AUTO_NEG_100BTX_FD;
1412 if (val & ADVERTISE_100HALF)
1413 data |= PORT_AUTO_NEG_100BTX;
1414 if (val & ADVERTISE_10FULL)
1415 data |= PORT_AUTO_NEG_10BT_FD;
1416 if (val & ADVERTISE_10HALF)
1417 data |= PORT_AUTO_NEG_10BT;
1418
1419 if (data != ctrl) {
1420 ret = ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data);
1421 if (ret)
1422 return ret;
1423 }
1424 break;
1425 case PHY_REG_LINK_MD:
1426 if (val & PHY_START_CABLE_DIAG)
1427 ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true);
1428 break;
1429
1430 case PHY_REG_PHY_CTRL:
1431 ret = ksz8_w_phy_ctrl(dev, p, val);
1432 if (ret)
1433 return ret;
1434 break;
1435 case PHY_REG_KSZ87XX_SHORT_CABLE:
1436 if (!ksz_is_ksz87xx(dev))
1437 return -EOPNOTSUPP;
1438 dev_info_once(dev->dev,
1439 "KSZ87xx low-loss tuning is global, applied switch-wide\n");
1440 ret = ksz87xx_apply_low_loss_preset(dev, !!val);
1441 if (ret)
1442 return ret;
1443 break;
1444 case PHY_REG_KSZ87XX_LPF_BW:
1445 if (!ksz_is_ksz87xx(dev))
1446 return -EOPNOTSUPP;
1447 dev_info_once(dev->dev,
1448 "KSZ87xx low-loss tuning is global, applied switch-wide\n");
1449 /* Only accept LPF bandwidth bits [7:6] */
1450 if (val & ~KSZ87XX_PHY_LPF_MASK)
1451 return -EINVAL;
1452 ret = ksz8_ind_write8(dev, TABLE_LINK_MD, KSZ87XX_REG_PHY_LPF, (u8)val);
1453 if (ret)
1454 return ret;
1455 dev->lpf_bw = val;
1456 break;
1457 case PHY_REG_KSZ87XX_EQ_INIT:
1458 if (!ksz_is_ksz87xx(dev))
1459 return -EOPNOTSUPP;
1460 dev_info_once(dev->dev,
1461 "KSZ87xx low-loss tuning is global, applied switch-wide\n");
1462 /* Only accept DSP EQ initial value bits [5:0] */
1463 if (val & ~KSZ87XX_DSP_EQ_VALID_MASK)
1464 return -EINVAL;
1465 ret = ksz8_ind_write8(dev, TABLE_LINK_MD, KSZ87XX_REG_DSP_EQ, (u8)val);
1466 if (ret)
1467 return ret;
1468 dev->eq_init = val;
1469 break;
1470 default:
1471 break;
1472 }
1473
1474 return 0;
1475 }
1476
ksz8_phy_write16(struct dsa_switch * ds,int addr,int reg,u16 val)1477 static int ksz8_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
1478 {
1479 struct ksz_device *dev = ds->priv;
1480 int ret;
1481
1482 ret = ksz8_w_phy(dev, addr, reg, val);
1483 if (ret)
1484 return ret;
1485
1486 return 0;
1487 }
1488
ksz8_cfg_port_member(struct ksz_device * dev,int port,u8 member)1489 static void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member)
1490 {
1491 int offset = P_MIRROR_CTRL;
1492 u8 data;
1493
1494 if (ksz_is_ksz8463(dev))
1495 offset = P1CR2;
1496 ksz_pread8(dev, port, offset, &data);
1497 data &= ~dev->port_mask;
1498 data |= (member & dev->port_mask);
1499 ksz_pwrite8(dev, port, offset, data);
1500 }
1501
ksz8_flush_dyn_mac_table(struct dsa_switch * ds,int port)1502 static void ksz8_flush_dyn_mac_table(struct dsa_switch *ds, int port)
1503 {
1504 struct ksz_device *dev = ds->priv;
1505 u8 learn[DSA_MAX_PORTS];
1506 int first, index, cnt;
1507 const u16 *regs;
1508 int reg = S_FLUSH_TABLE_CTRL;
1509 int mask = SW_FLUSH_DYN_MAC_TABLE;
1510
1511 regs = dev->info->regs;
1512
1513 if ((uint)port < dev->info->port_cnt) {
1514 first = port;
1515 cnt = port + 1;
1516 } else {
1517 /* Flush all ports. */
1518 first = 0;
1519 cnt = dev->info->port_cnt;
1520 }
1521 for (index = first; index < cnt; index++) {
1522 ksz_pread8(dev, index, regs[P_STP_CTRL], &learn[index]);
1523 if (!(learn[index] & PORT_LEARN_DISABLE))
1524 ksz_pwrite8(dev, index, regs[P_STP_CTRL],
1525 learn[index] | PORT_LEARN_DISABLE);
1526 }
1527 if (ksz_is_ksz8463(dev)) {
1528 reg = KSZ8463_FLUSH_TABLE_CTRL;
1529 mask = KSZ8463_FLUSH_DYN_MAC_TABLE;
1530 }
1531 ksz_cfg(dev, reg, mask, true);
1532 for (index = first; index < cnt; index++) {
1533 if (!(learn[index] & PORT_LEARN_DISABLE))
1534 ksz_pwrite8(dev, index, regs[P_STP_CTRL], learn[index]);
1535 }
1536 }
1537
ksz8_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)1538 static int ksz8_fdb_dump(struct dsa_switch *ds, int port,
1539 dsa_fdb_dump_cb_t *cb, void *data)
1540 {
1541 struct ksz_device *dev = ds->priv;
1542 u8 mac[ETH_ALEN];
1543 u8 src_port, fid;
1544 u16 entries = 0;
1545 int ret, i;
1546
1547 for (i = 0; i < KSZ8_DYN_MAC_ENTRIES; i++) {
1548 ret = ksz8_r_dyn_mac_table(dev, i, mac, &fid, &src_port,
1549 &entries);
1550 if (ret)
1551 return ret;
1552
1553 if (i >= entries)
1554 return 0;
1555
1556 if (port == src_port) {
1557 ret = cb(mac, fid, false, data);
1558 if (ret)
1559 return ret;
1560 }
1561 }
1562
1563 return 0;
1564 }
1565
ksz8_add_sta_mac(struct ksz_device * dev,int port,const unsigned char * addr,u16 vid)1566 static int ksz8_add_sta_mac(struct ksz_device *dev, int port,
1567 const unsigned char *addr, u16 vid)
1568 {
1569 struct alu_struct alu;
1570 int index, ret;
1571 int empty = 0;
1572
1573 alu.port_forward = 0;
1574 for (index = 0; index < dev->info->num_statics; index++) {
1575 bool valid;
1576
1577 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid);
1578 if (ret)
1579 return ret;
1580 if (!valid) {
1581 /* Remember the first empty entry. */
1582 if (!empty)
1583 empty = index + 1;
1584 continue;
1585 }
1586
1587 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid)
1588 break;
1589 }
1590
1591 /* no available entry */
1592 if (index == dev->info->num_statics && !empty)
1593 return -ENOSPC;
1594
1595 /* add entry */
1596 if (index == dev->info->num_statics) {
1597 index = empty - 1;
1598 memset(&alu, 0, sizeof(alu));
1599 memcpy(alu.mac, addr, ETH_ALEN);
1600 alu.is_static = true;
1601 }
1602 alu.port_forward |= BIT(port);
1603 if (vid) {
1604 alu.is_use_fid = true;
1605
1606 /* Need a way to map VID to FID. */
1607 alu.fid = vid;
1608 }
1609
1610 return ksz8_w_sta_mac_table(dev, index, &alu);
1611 }
1612
ksz8_del_sta_mac(struct ksz_device * dev,int port,const unsigned char * addr,u16 vid)1613 static int ksz8_del_sta_mac(struct ksz_device *dev, int port,
1614 const unsigned char *addr, u16 vid)
1615 {
1616 struct alu_struct alu;
1617 int index, ret;
1618
1619 for (index = 0; index < dev->info->num_statics; index++) {
1620 bool valid;
1621
1622 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid);
1623 if (ret)
1624 return ret;
1625 if (!valid)
1626 continue;
1627
1628 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid)
1629 break;
1630 }
1631
1632 /* no available entry */
1633 if (index == dev->info->num_statics)
1634 return 0;
1635
1636 /* clear port */
1637 alu.port_forward &= ~BIT(port);
1638 if (!alu.port_forward)
1639 alu.is_static = false;
1640
1641 return ksz8_w_sta_mac_table(dev, index, &alu);
1642 }
1643
ksz8_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1644 static int ksz8_mdb_add(struct dsa_switch *ds, int port,
1645 const struct switchdev_obj_port_mdb *mdb,
1646 struct dsa_db db)
1647 {
1648 return ksz8_add_sta_mac(ds->priv, port, mdb->addr, mdb->vid);
1649 }
1650
ksz8_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1651 static int ksz8_mdb_del(struct dsa_switch *ds, int port,
1652 const struct switchdev_obj_port_mdb *mdb,
1653 struct dsa_db db)
1654 {
1655 return ksz8_del_sta_mac(ds->priv, port, mdb->addr, mdb->vid);
1656 }
1657
ksz8_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1658 static int ksz8_fdb_add(struct dsa_switch *ds, int port,
1659 const unsigned char *addr, u16 vid, struct dsa_db db)
1660 {
1661 return ksz8_add_sta_mac(ds->priv, port, addr, vid);
1662 }
1663
ksz8_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1664 static int ksz8_fdb_del(struct dsa_switch *ds, int port,
1665 const unsigned char *addr, u16 vid, struct dsa_db db)
1666 {
1667 return ksz8_del_sta_mac(ds->priv, port, addr, vid);
1668 }
1669
ksz8_port_vlan_filtering(struct dsa_switch * ds,int port,bool flag,struct netlink_ext_ack * extack)1670 static int ksz8_port_vlan_filtering(struct dsa_switch *ds, int port, bool flag,
1671 struct netlink_ext_ack *extack)
1672 {
1673 struct ksz_device *dev = ds->priv;
1674
1675 if (ksz_is_ksz88x3(dev))
1676 return -ENOTSUPP;
1677
1678 /* Discard packets with VID not enabled on the switch */
1679 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag);
1680
1681 /* Discard packets with VID not enabled on the ingress port */
1682 for (port = 0; port < dev->phy_port_cnt; ++port)
1683 ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER,
1684 flag);
1685
1686 return 0;
1687 }
1688
ksz8_port_enable_pvid(struct ksz_device * dev,int port,bool state)1689 static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state)
1690 {
1691 if (ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)) {
1692 int reg = REG_SW_INSERT_SRC_PVID;
1693
1694 if (ksz_is_ksz8463(dev))
1695 reg = KSZ8463_REG_SW_CTRL_9;
1696 ksz_cfg(dev, reg, 0x03 << (4 - 2 * port), state);
1697 } else {
1698 ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00);
1699 }
1700 }
1701
ksz8_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)1702 static int ksz8_port_vlan_add(struct dsa_switch *ds, int port,
1703 const struct switchdev_obj_port_vlan *vlan,
1704 struct netlink_ext_ack *extack)
1705 {
1706 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1707 struct ksz_device *dev = ds->priv;
1708 struct ksz_port *p = &dev->ports[port];
1709 u16 data, new_pvid = 0;
1710 u8 fid, member, valid;
1711
1712 if (ksz_is_ksz88x3(dev))
1713 return -ENOTSUPP;
1714
1715 /* If a VLAN is added with untagged flag different from the
1716 * port's Remove Tag flag, we need to change the latter.
1717 * Ignore VID 0, which is always untagged.
1718 * Ignore CPU port, which will always be tagged.
1719 */
1720 if (untagged != p->remove_tag && vlan->vid != 0 &&
1721 port != dev->cpu_port) {
1722 unsigned int vid;
1723
1724 /* Reject attempts to add a VLAN that requires the
1725 * Remove Tag flag to be changed, unless there are no
1726 * other VLANs currently configured.
1727 */
1728 for (vid = 1; vid < dev->info->num_vlans; ++vid) {
1729 /* Skip the VID we are going to add or reconfigure */
1730 if (vid == vlan->vid)
1731 continue;
1732
1733 ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0],
1734 &fid, &member, &valid);
1735 if (valid && (member & BIT(port)))
1736 return -EINVAL;
1737 }
1738
1739 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged);
1740 p->remove_tag = untagged;
1741 }
1742
1743 ksz8_r_vlan_table(dev, vlan->vid, &data);
1744 ksz8_from_vlan(dev, data, &fid, &member, &valid);
1745
1746 /* First time to setup the VLAN entry. */
1747 if (!valid) {
1748 /* Need to find a way to map VID to FID. */
1749 fid = 1;
1750 valid = 1;
1751 }
1752 member |= BIT(port);
1753
1754 ksz8_to_vlan(dev, fid, member, valid, &data);
1755 ksz8_w_vlan_table(dev, vlan->vid, data);
1756
1757 /* change PVID */
1758 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1759 new_pvid = vlan->vid;
1760
1761 if (new_pvid) {
1762 u16 vid;
1763
1764 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid);
1765 vid &= ~VLAN_VID_MASK;
1766 vid |= new_pvid;
1767 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid);
1768
1769 ksz8_port_enable_pvid(dev, port, true);
1770 }
1771
1772 return 0;
1773 }
1774
ksz8_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)1775 static int ksz8_port_vlan_del(struct dsa_switch *ds, int port,
1776 const struct switchdev_obj_port_vlan *vlan)
1777 {
1778 struct ksz_device *dev = ds->priv;
1779 u8 fid, member, valid;
1780 u16 data, pvid;
1781
1782 if (ksz_is_ksz88x3(dev))
1783 return -ENOTSUPP;
1784
1785 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid);
1786 pvid = pvid & 0xFFF;
1787
1788 ksz8_r_vlan_table(dev, vlan->vid, &data);
1789 ksz8_from_vlan(dev, data, &fid, &member, &valid);
1790
1791 member &= ~BIT(port);
1792
1793 /* Invalidate the entry if no more member. */
1794 if (!member) {
1795 fid = 0;
1796 valid = 0;
1797 }
1798
1799 ksz8_to_vlan(dev, fid, member, valid, &data);
1800 ksz8_w_vlan_table(dev, vlan->vid, data);
1801
1802 if (pvid == vlan->vid)
1803 ksz8_port_enable_pvid(dev, port, false);
1804
1805 return 0;
1806 }
1807
ksz8_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)1808 static int ksz8_port_mirror_add(struct dsa_switch *ds, int port,
1809 struct dsa_mall_mirror_tc_entry *mirror,
1810 bool ingress, struct netlink_ext_ack *extack)
1811 {
1812 struct ksz_device *dev = ds->priv;
1813 int offset = P_MIRROR_CTRL;
1814
1815 if (ksz_is_ksz8463(dev))
1816 offset = P1CR2;
1817 if (ingress) {
1818 ksz_port_cfg(dev, port, offset, PORT_MIRROR_RX, true);
1819 dev->mirror_rx |= BIT(port);
1820 } else {
1821 ksz_port_cfg(dev, port, offset, PORT_MIRROR_TX, true);
1822 dev->mirror_tx |= BIT(port);
1823 }
1824
1825 ksz_port_cfg(dev, port, offset, PORT_MIRROR_SNIFFER, false);
1826
1827 /* configure mirror port */
1828 if (dev->mirror_rx || dev->mirror_tx)
1829 ksz_port_cfg(dev, mirror->to_local_port, offset,
1830 PORT_MIRROR_SNIFFER, true);
1831
1832 return 0;
1833 }
1834
ksz8_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)1835 static void ksz8_port_mirror_del(struct dsa_switch *ds, int port,
1836 struct dsa_mall_mirror_tc_entry *mirror)
1837 {
1838 struct ksz_device *dev = ds->priv;
1839 int offset = P_MIRROR_CTRL;
1840 u8 data;
1841
1842 if (ksz_is_ksz8463(dev))
1843 offset = P1CR2;
1844 if (mirror->ingress) {
1845 ksz_port_cfg(dev, port, offset, PORT_MIRROR_RX, false);
1846 dev->mirror_rx &= ~BIT(port);
1847 } else {
1848 ksz_port_cfg(dev, port, offset, PORT_MIRROR_TX, false);
1849 dev->mirror_tx &= ~BIT(port);
1850 }
1851
1852 ksz_pread8(dev, port, offset, &data);
1853
1854 if (!dev->mirror_rx && !dev->mirror_tx)
1855 ksz_port_cfg(dev, mirror->to_local_port, offset,
1856 PORT_MIRROR_SNIFFER, false);
1857 }
1858
ksz8463_tc_ctrl(int port,int queue)1859 static u8 ksz8463_tc_ctrl(int port, int queue)
1860 {
1861 u8 reg;
1862
1863 reg = 0xC8 + port * 4;
1864 reg += ((3 - queue) / 2) * 2;
1865 reg++;
1866 reg -= (queue & 1);
1867 return reg;
1868 }
1869
1870 /**
1871 * ksz88x3_tc_ets_add - Configure ETS (Enhanced Transmission Selection)
1872 * for a port on KSZ88x3 switch
1873 * @dev: Pointer to the KSZ switch device structure
1874 * @port: Port number to configure
1875 * @p: Pointer to offload replace parameters describing ETS bands and mapping
1876 *
1877 * The KSZ88x3 supports two scheduling modes: Strict Priority and
1878 * Weighted Fair Queuing (WFQ). Both modes have fixed behavior:
1879 * - No configurable queue-to-priority mapping
1880 * - No weight adjustment in WFQ mode
1881 *
1882 * This function configures the switch to use strict priority mode by
1883 * clearing the WFQ enable bit for all queues associated with ETS bands.
1884 * If strict priority is not explicitly requested, the switch will default
1885 * to WFQ mode.
1886 *
1887 * Return: 0 on success, or a negative error code on failure
1888 */
ksz88x3_tc_ets_add(struct ksz_device * dev,int port,struct tc_ets_qopt_offload_replace_params * p)1889 static int ksz88x3_tc_ets_add(struct ksz_device *dev, int port,
1890 struct tc_ets_qopt_offload_replace_params *p)
1891 {
1892 int ret, band;
1893
1894 /* Only strict priority mode is supported for now.
1895 * WFQ is implicitly enabled when strict mode is disabled.
1896 */
1897 for (band = 0; band < p->bands; band++) {
1898 int queue = ksz_ets_band_to_queue(p, band);
1899 u8 reg;
1900
1901 /* Calculate TXQ Split Control register address for this
1902 * port/queue
1903 */
1904 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue);
1905 if (ksz_is_ksz8463(dev))
1906 reg = ksz8463_tc_ctrl(port, queue);
1907
1908 /* Clear WFQ enable bit to select strict priority scheduling */
1909 ret = ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE, 0);
1910 if (ret)
1911 return ret;
1912 }
1913
1914 return 0;
1915 }
1916
1917 /**
1918 * ksz88x3_tc_ets_del - Reset ETS (Enhanced Transmission Selection) config
1919 * for a port on KSZ88x3 switch
1920 * @dev: Pointer to the KSZ switch device structure
1921 * @port: Port number to reset
1922 *
1923 * The KSZ88x3 supports only fixed scheduling modes: Strict Priority or
1924 * Weighted Fair Queuing (WFQ), with no reconfiguration of weights or
1925 * queue mapping. This function resets the port’s scheduling mode to
1926 * the default, which is WFQ, by enabling the WFQ bit for all queues.
1927 *
1928 * Return: 0 on success, or a negative error code on failure
1929 */
ksz88x3_tc_ets_del(struct ksz_device * dev,int port)1930 static int ksz88x3_tc_ets_del(struct ksz_device *dev, int port)
1931 {
1932 int ret, queue;
1933
1934 /* Iterate over all transmit queues for this port */
1935 for (queue = 0; queue < dev->info->num_tx_queues; queue++) {
1936 u8 reg;
1937
1938 /* Calculate TXQ Split Control register address for this
1939 * port/queue
1940 */
1941 reg = KSZ8873_TXQ_SPLIT_CTRL_REG(port, queue);
1942 if (ksz_is_ksz8463(dev))
1943 reg = ksz8463_tc_ctrl(port, queue);
1944
1945 /* Set WFQ enable bit to revert back to default scheduling
1946 * mode
1947 */
1948 ret = ksz_rmw8(dev, reg, KSZ8873_TXQ_WFQ_ENABLE,
1949 KSZ8873_TXQ_WFQ_ENABLE);
1950 if (ret)
1951 return ret;
1952 }
1953
1954 return 0;
1955 }
1956
ksz8_tc_setup_qdisc_ets(struct dsa_switch * ds,int port,struct tc_ets_qopt_offload * qopt)1957 static int ksz8_tc_setup_qdisc_ets(struct dsa_switch *ds, int port,
1958 struct tc_ets_qopt_offload *qopt)
1959 {
1960 struct ksz_device *dev = ds->priv;
1961 int ret;
1962
1963 if (!(ksz_is_ksz88x3(dev) || ksz_is_ksz8463(dev)))
1964 return -EOPNOTSUPP;
1965
1966 if (qopt->parent != TC_H_ROOT) {
1967 dev_err(dev->dev, "Parent should be \"root\"\n");
1968 return -EOPNOTSUPP;
1969 }
1970
1971 switch (qopt->command) {
1972 case TC_ETS_REPLACE:
1973 ret = ksz_tc_ets_validate(dev, port, &qopt->replace_params);
1974 if (ret)
1975 return ret;
1976
1977 return ksz88x3_tc_ets_add(dev, port, &qopt->replace_params);
1978 case TC_ETS_DESTROY:
1979 return ksz88x3_tc_ets_del(dev, port);
1980 case TC_ETS_STATS:
1981 case TC_ETS_GRAFT:
1982 return -EOPNOTSUPP;
1983 }
1984
1985 return -EOPNOTSUPP;
1986 }
1987
ksz87xx_setup_tc(struct dsa_switch * ds,int port,enum tc_setup_type type,void * type_data)1988 static int ksz87xx_setup_tc(struct dsa_switch *ds, int port,
1989 enum tc_setup_type type, void *type_data)
1990 {
1991 switch (type) {
1992 case TC_SETUP_QDISC_CBS:
1993 return ksz_setup_tc_cbs(ds, port, type_data);
1994 default:
1995 return -EOPNOTSUPP;
1996 }
1997 }
1998
ksz8_setup_tc(struct dsa_switch * ds,int port,enum tc_setup_type type,void * type_data)1999 static int ksz8_setup_tc(struct dsa_switch *ds, int port,
2000 enum tc_setup_type type, void *type_data)
2001 {
2002 switch (type) {
2003 case TC_SETUP_QDISC_CBS:
2004 return ksz_setup_tc_cbs(ds, port, type_data);
2005 case TC_SETUP_QDISC_ETS:
2006 return ksz8_tc_setup_qdisc_ets(ds, port, type_data);
2007 default:
2008 return -EOPNOTSUPP;
2009 }
2010 }
2011
ksz8795_cpu_interface_select(struct ksz_device * dev,int port)2012 static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
2013 {
2014 struct ksz_port *p = &dev->ports[port];
2015
2016 if (!ksz_is_ksz87xx(dev))
2017 return;
2018
2019 if (!p->interface && dev->compat_interface) {
2020 dev_warn(dev->dev,
2021 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
2022 "Please update your device tree.\n",
2023 port);
2024 p->interface = dev->compat_interface;
2025 }
2026 }
2027
ksz8_port_setup(struct ksz_device * dev,int port,bool cpu_port)2028 static void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)
2029 {
2030 const u16 *regs = dev->info->regs;
2031 struct dsa_switch *ds = dev->ds;
2032 const u32 *masks;
2033 int offset;
2034 u8 member;
2035
2036 masks = dev->info->masks;
2037
2038 /* enable broadcast storm limit */
2039 offset = P_BCAST_STORM_CTRL;
2040 if (ksz_is_ksz8463(dev))
2041 offset = P1CR1;
2042 ksz_port_cfg(dev, port, offset, PORT_BROADCAST_STORM, true);
2043
2044 ksz8_port_queue_split(dev, port, dev->info->num_tx_queues);
2045
2046 /* replace priority */
2047 offset = P_802_1P_CTRL;
2048 if (ksz_is_ksz8463(dev))
2049 offset = P1CR2;
2050 ksz_port_cfg(dev, port, offset,
2051 masks[PORT_802_1P_REMAPPING], false);
2052
2053 if (cpu_port)
2054 member = dsa_user_ports(ds);
2055 else
2056 member = BIT(dsa_upstream_port(ds, port));
2057
2058 ksz8_cfg_port_member(dev, port, member);
2059
2060 /* Disable all WoL options by default. Otherwise
2061 * ksz_switch_macaddr_get/put logic will not work properly.
2062 * CPU port 4 has no WoL functionality.
2063 */
2064 if (ksz_is_ksz87xx(dev) && !cpu_port)
2065 ksz8_pme_pwrite8(dev, port, regs[REG_PORT_PME_CTRL], 0);
2066 }
2067
ksz8_dsa_port_setup(struct dsa_switch * ds,int port)2068 static int ksz8_dsa_port_setup(struct dsa_switch *ds, int port)
2069 {
2070 struct ksz_device *dev = ds->priv;
2071
2072 if (!dsa_is_user_port(ds, port))
2073 return 0;
2074
2075 ksz8_port_setup(dev, port, false);
2076 return ksz_dcb_init_port(dev, port);
2077 }
2078
ksz88x3_config_rmii_clk(struct ksz_device * dev)2079 static void ksz88x3_config_rmii_clk(struct ksz_device *dev)
2080 {
2081 struct dsa_port *cpu_dp = dsa_to_port(dev->ds, dev->cpu_port);
2082 bool rmii_clk_internal;
2083
2084 if (!ksz_is_ksz88x3(dev))
2085 return;
2086
2087 rmii_clk_internal = of_property_read_bool(cpu_dp->dn,
2088 "microchip,rmii-clk-internal");
2089
2090 ksz_cfg(dev, KSZ88X3_REG_FVID_AND_HOST_MODE,
2091 KSZ88X3_PORT3_RMII_CLK_INTERNAL, rmii_clk_internal);
2092 }
2093
ksz8463_config_cpu_port(struct dsa_switch * ds)2094 static void ksz8463_config_cpu_port(struct dsa_switch *ds)
2095 {
2096 struct ksz_device *dev = ds->priv;
2097 struct ksz_port *p;
2098 u8 fiber_ports = 0;
2099 const u32 *masks;
2100 const u16 *regs;
2101 int i;
2102
2103 masks = dev->info->masks;
2104 regs = dev->info->regs;
2105
2106 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true);
2107
2108 ksz8_port_setup(dev, dev->cpu_port, true);
2109
2110 for (i = 0; i < dev->phy_port_cnt; i++)
2111 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED);
2112
2113 for (i = 0; i < dev->phy_port_cnt; i++) {
2114 p = &dev->ports[i];
2115 ksz_port_cfg(dev, i, regs[P_STP_CTRL], PORT_FORCE_FLOW_CTRL,
2116 p->fiber);
2117 if (p->fiber)
2118 fiber_ports |= (1 << i);
2119 }
2120
2121 /* Setup fiber ports. */
2122 if (fiber_ports) {
2123 fiber_ports &= 3;
2124 regmap_update_bits(ksz_regmap_16(dev), KSZ8463_REG_CFG_CTRL,
2125 fiber_ports << PORT_COPPER_MODE_S,
2126 0);
2127 regmap_update_bits(ksz_regmap_16(dev), KSZ8463_REG_DSP_CTRL_6,
2128 COPPER_RECEIVE_ADJUSTMENT, 0);
2129 }
2130
2131 /* Turn off PTP function as the switch enables it by default */
2132 regmap_update_bits(ksz_regmap_16(dev), KSZ8463_PTP_MSG_CONF1,
2133 PTP_ENABLE, 0);
2134 regmap_update_bits(ksz_regmap_16(dev), KSZ8463_PTP_CLK_CTRL,
2135 PTP_CLK_ENABLE, 0);
2136 }
2137
ksz8_config_cpu_port(struct dsa_switch * ds)2138 static void ksz8_config_cpu_port(struct dsa_switch *ds)
2139 {
2140 struct ksz_device *dev = ds->priv;
2141 struct ksz_port *p;
2142 const u32 *masks;
2143 const u16 *regs;
2144 u8 remote;
2145 int i;
2146
2147 masks = dev->info->masks;
2148 regs = dev->info->regs;
2149
2150 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true);
2151
2152 ksz8_port_setup(dev, dev->cpu_port, true);
2153
2154 ksz8795_cpu_interface_select(dev, dev->cpu_port);
2155 ksz88x3_config_rmii_clk(dev);
2156
2157 for (i = 0; i < dev->phy_port_cnt; i++) {
2158 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED);
2159 }
2160 for (i = 0; i < dev->phy_port_cnt; i++) {
2161 p = &dev->ports[i];
2162
2163 /* For KSZ8795 family. */
2164 if (ksz_is_ksz87xx(dev)) {
2165 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote);
2166 if (remote & KSZ8_PORT_FIBER_MODE)
2167 p->fiber = 1;
2168 }
2169 if (p->fiber)
2170 ksz_port_cfg(dev, i, regs[P_STP_CTRL],
2171 PORT_FORCE_FLOW_CTRL, true);
2172 else
2173 ksz_port_cfg(dev, i, regs[P_STP_CTRL],
2174 PORT_FORCE_FLOW_CTRL, false);
2175 }
2176 }
2177
2178 /**
2179 * ksz8_phy_port_link_up - Configures ports with integrated PHYs
2180 * @dev: The KSZ device instance.
2181 * @port: The port number to configure.
2182 * @duplex: The desired duplex mode.
2183 * @tx_pause: If true, enables transmit pause.
2184 * @rx_pause: If true, enables receive pause.
2185 *
2186 * Description:
2187 * The function configures flow control settings for a given port based on the
2188 * desired settings and current duplex mode.
2189 *
2190 * According to the KSZ8873 datasheet, the PORT_FORCE_FLOW_CTRL bit in the
2191 * Port Control 2 register (0x1A for Port 1, 0x22 for Port 2, 0x32 for Port 3)
2192 * determines how flow control is handled on the port:
2193 * "1 = will always enable full-duplex flow control on the port, regardless
2194 * of AN result.
2195 * 0 = full-duplex flow control is enabled based on AN result."
2196 *
2197 * This means that the flow control behavior depends on the state of this bit:
2198 * - If PORT_FORCE_FLOW_CTRL is set to 1, the switch will ignore AN results and
2199 * force flow control on the port.
2200 * - If PORT_FORCE_FLOW_CTRL is set to 0, the switch will enable or disable
2201 * flow control based on the AN results.
2202 *
2203 * However, there is a potential limitation in this configuration. It is
2204 * currently not possible to force disable flow control on a port if we still
2205 * advertise pause support. While such a configuration is not currently
2206 * supported by Linux, and may not make practical sense, it's important to be
2207 * aware of this limitation when working with the KSZ8873 and similar devices.
2208 */
ksz8_phy_port_link_up(struct ksz_device * dev,int port,int duplex,bool tx_pause,bool rx_pause)2209 static void ksz8_phy_port_link_up(struct ksz_device *dev, int port, int duplex,
2210 bool tx_pause, bool rx_pause)
2211 {
2212 const u16 *regs = dev->info->regs;
2213 u8 sctrl = 0;
2214
2215 /* The KSZ8795 switch differs from the KSZ8873 by supporting
2216 * asymmetric pause control. However, since a single bit is used to
2217 * control both RX and TX pause, we can't enforce asymmetric pause
2218 * control - both TX and RX pause will be either enabled or disabled
2219 * together.
2220 *
2221 * If auto-negotiation is enabled, we usually allow the flow control to
2222 * be determined by the auto-negotiation process based on the
2223 * capabilities of both link partners. However, for KSZ8873, the
2224 * PORT_FORCE_FLOW_CTRL bit may be set by the hardware bootstrap,
2225 * ignoring the auto-negotiation result. Thus, even in auto-negotiation
2226 * mode, we need to ensure that the PORT_FORCE_FLOW_CTRL bit is
2227 * properly cleared.
2228 *
2229 * In the absence of pause auto-negotiation, we will enforce symmetric
2230 * pause control for both variants of switches - KSZ8873 and KSZ8795.
2231 *
2232 * Autoneg Pause Autoneg rx,tx PORT_FORCE_FLOW_CTRL
2233 * 1 1 x 0
2234 * 0 1 x 0 (flow control probably disabled)
2235 * x 0 1 1 (flow control force enabled)
2236 * 1 0 0 0 (flow control still depends on
2237 * aneg result due to hardware)
2238 * 0 0 0 0 (flow control probably disabled)
2239 */
2240 if (dev->ports[port].manual_flow && tx_pause)
2241 sctrl |= PORT_FORCE_FLOW_CTRL;
2242
2243 ksz_prmw8(dev, port, regs[P_STP_CTRL], PORT_FORCE_FLOW_CTRL, sctrl);
2244 }
2245
2246 /**
2247 * ksz8_cpu_port_link_up - Configures the CPU port of the switch.
2248 * @dev: The KSZ device instance.
2249 * @speed: The desired link speed.
2250 * @duplex: The desired duplex mode.
2251 * @tx_pause: If true, enables transmit pause.
2252 * @rx_pause: If true, enables receive pause.
2253 *
2254 * Description:
2255 * The function configures flow control and speed settings for the CPU
2256 * port of the switch based on the desired settings, current duplex mode, and
2257 * speed.
2258 */
ksz8_cpu_port_link_up(struct ksz_device * dev,int speed,int duplex,bool tx_pause,bool rx_pause)2259 static void ksz8_cpu_port_link_up(struct ksz_device *dev, int speed, int duplex,
2260 bool tx_pause, bool rx_pause)
2261 {
2262 const u16 *regs = dev->info->regs;
2263 u8 ctrl = 0;
2264
2265 /* SW_FLOW_CTRL, SW_HALF_DUPLEX, and SW_10_MBIT bits are bootstrappable
2266 * at least on KSZ8873. They can have different values depending on your
2267 * board setup.
2268 */
2269 if (tx_pause || rx_pause)
2270 ctrl |= SW_FLOW_CTRL;
2271
2272 if (duplex == DUPLEX_HALF)
2273 ctrl |= SW_HALF_DUPLEX;
2274
2275 /* This hardware only supports SPEED_10 and SPEED_100. For SPEED_10
2276 * we need to set the SW_10_MBIT bit. Otherwise, we can leave it 0.
2277 */
2278 if (speed == SPEED_10)
2279 ctrl |= SW_10_MBIT;
2280
2281 ksz_rmw8(dev, regs[S_BROADCAST_CTRL], SW_HALF_DUPLEX | SW_FLOW_CTRL |
2282 SW_10_MBIT, ctrl);
2283 }
2284
ksz8_phylink_mac_link_up(struct phylink_config * config,struct phy_device * phydev,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)2285 static void ksz8_phylink_mac_link_up(struct phylink_config *config,
2286 struct phy_device *phydev,
2287 unsigned int mode,
2288 phy_interface_t interface,
2289 int speed, int duplex,
2290 bool tx_pause, bool rx_pause)
2291 {
2292 struct dsa_port *dp = dsa_phylink_to_port(config);
2293 struct ksz_device *dev = dp->ds->priv;
2294 int port = dp->index;
2295
2296 /* If the port is the CPU port, apply special handling. Only the CPU
2297 * port is configured via global registers.
2298 */
2299 if (dev->cpu_port == port)
2300 ksz8_cpu_port_link_up(dev, speed, duplex, tx_pause, rx_pause);
2301 else if (dev->info->internal_phy[port])
2302 ksz8_phy_port_link_up(dev, port, duplex, tx_pause, rx_pause);
2303 }
2304
ksz8_handle_global_errata(struct dsa_switch * ds)2305 static int ksz8_handle_global_errata(struct dsa_switch *ds)
2306 {
2307 struct ksz_device *dev = ds->priv;
2308 int ret = 0;
2309
2310 /* KSZ87xx Errata DS80000687C.
2311 * Module 2: Link drops with some EEE link partners.
2312 * An issue with the EEE next page exchange between the
2313 * KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in
2314 * the link dropping.
2315 */
2316 if (dev->info->ksz87xx_eee_link_erratum)
2317 ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0);
2318
2319 return ret;
2320 }
2321
ksz8_enable_stp_addr(struct ksz_device * dev)2322 static int ksz8_enable_stp_addr(struct ksz_device *dev)
2323 {
2324 struct alu_struct alu;
2325
2326 /* Setup STP address for STP operation. */
2327 memset(&alu, 0, sizeof(alu));
2328 ether_addr_copy(alu.mac, eth_stp_addr);
2329 alu.is_static = true;
2330 alu.is_override = true;
2331 alu.port_forward = dev->info->cpu_ports;
2332
2333 return ksz8_w_sta_mac_table(dev, 0, &alu);
2334 }
2335
ksz88xx_r_mib_stats64(struct ksz_device * dev,int port)2336 static void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port)
2337 {
2338 struct ethtool_pause_stats *pstats;
2339 struct rtnl_link_stats64 *stats;
2340 struct ksz88xx_stats_raw *raw;
2341 struct ksz_port_mib *mib;
2342
2343 mib = &dev->ports[port].mib;
2344 stats = &mib->stats64;
2345 pstats = &mib->pause_stats;
2346 raw = (struct ksz88xx_stats_raw *)mib->counters;
2347
2348 spin_lock(&mib->stats64_lock);
2349
2350 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
2351 raw->rx_pause;
2352 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
2353 raw->tx_pause;
2354
2355 /* HW counters are counting bytes + FCS which is not acceptable
2356 * for rtnl_link_stats64 interface
2357 */
2358 stats->rx_bytes = raw->rx + raw->rx_hi - stats->rx_packets * ETH_FCS_LEN;
2359 stats->tx_bytes = raw->tx + raw->tx_hi - stats->tx_packets * ETH_FCS_LEN;
2360
2361 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
2362 raw->rx_oversize;
2363
2364 stats->rx_crc_errors = raw->rx_crc_err;
2365 stats->rx_frame_errors = raw->rx_align_err;
2366 stats->rx_dropped = raw->rx_discards;
2367 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2368 stats->rx_frame_errors + stats->rx_dropped;
2369
2370 stats->tx_window_errors = raw->tx_late_col;
2371 stats->tx_fifo_errors = raw->tx_discards;
2372 stats->tx_aborted_errors = raw->tx_exc_col;
2373 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
2374 stats->tx_aborted_errors;
2375
2376 stats->multicast = raw->rx_mcast;
2377 stats->collisions = raw->tx_total_col;
2378
2379 pstats->tx_pause_frames = raw->tx_pause;
2380 pstats->rx_pause_frames = raw->rx_pause;
2381
2382 spin_unlock(&mib->stats64_lock);
2383 }
2384
ksz8463_setup(struct dsa_switch * ds)2385 static int ksz8463_setup(struct dsa_switch *ds)
2386 {
2387 struct ksz_device *dev = ds->priv;
2388 u16 storm_mask, storm_rate;
2389 struct ksz_port *p;
2390 const u16 *regs;
2391 int i, ret;
2392
2393 regs = dev->info->regs;
2394
2395 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
2396 dev->info->num_vlans, GFP_KERNEL);
2397 if (!dev->vlan_cache)
2398 return -ENOMEM;
2399
2400 ret = ksz8463_reset_switch(dev);
2401 if (ret) {
2402 dev_err(ds->dev, "failed to reset switch\n");
2403 return ret;
2404 }
2405
2406 /* set broadcast storm protection 10% rate */
2407 storm_mask = BROADCAST_STORM_RATE;
2408 storm_rate = (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100;
2409 storm_mask = swab16(storm_mask);
2410 storm_rate = swab16(storm_rate);
2411 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL],
2412 storm_mask, storm_rate);
2413
2414 ksz8463_config_cpu_port(ds);
2415
2416 ksz8_enable_stp_addr(dev);
2417
2418 ds->num_tx_queues = dev->info->num_tx_queues;
2419
2420 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL],
2421 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
2422
2423 ksz_init_mib_timer(dev);
2424
2425 ds->configure_vlan_while_not_filtering = false;
2426 ds->dscp_prio_mapping_is_global = true;
2427 ds->mtu_enforcement_ingress = true;
2428
2429 /* We rely on software untagging on the CPU port, so that we
2430 * can support both tagged and untagged VLANs
2431 */
2432 ds->untag_bridge_pvid = true;
2433
2434 /* VLAN filtering is partly controlled by the global VLAN
2435 * Enable flag
2436 */
2437 ds->vlan_filtering_is_global = true;
2438
2439 /* Enable automatic fast aging when link changed detected. */
2440 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true);
2441
2442 /* Enable aggressive back off algorithm in half duplex mode. */
2443 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_AGGR_BACKOFF, SW_AGGR_BACKOFF);
2444 if (ret)
2445 return ret;
2446
2447 /*
2448 * Make sure unicast VLAN boundary is set as default and
2449 * enable no excessive collision drop.
2450 */
2451 ret = ksz_rmw8(dev, REG_SW_CTRL_2,
2452 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP,
2453 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP);
2454 if (ret)
2455 return ret;
2456
2457 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false);
2458
2459 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
2460
2461 for (i = 0; i < (dev->info->num_vlans / 4); i++)
2462 ksz8_r_vlan_entries(dev, i);
2463
2464 /* Start with learning disabled on standalone user ports, and enabled
2465 * on the CPU port. In lack of other finer mechanisms, learning on the
2466 * CPU port will avoid flooding bridge local addresses on the network
2467 * in some cases.
2468 */
2469 p = &dev->ports[dev->cpu_port];
2470 p->learning = true;
2471
2472 if (dev->irq > 0) {
2473 ret = ksz8463_girq_setup(dev);
2474 if (ret)
2475 return ret;
2476
2477 ret = ksz8463_ptp_irq_setup(ds);
2478 if (ret)
2479 goto free_girq;
2480
2481 ret = ksz_ptp_clock_register(ds);
2482 if (ret) {
2483 dev_err(dev->dev, "Failed to register PTP clock: %d\n",
2484 ret);
2485 goto free_ptp_irq;
2486 }
2487 }
2488
2489 ret = ksz_mdio_register(dev);
2490 if (ret < 0) {
2491 dev_err(dev->dev, "failed to register the mdio");
2492 goto ptp_clock_unregister;
2493 }
2494
2495 ret = ksz_dcb_init(dev);
2496 if (ret)
2497 goto ptp_clock_unregister;
2498
2499 /* start switch */
2500 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL],
2501 SW_START, SW_START);
2502
2503 return 0;
2504
2505 ptp_clock_unregister:
2506 if (dev->irq > 0)
2507 ksz_ptp_clock_unregister(ds);
2508 free_ptp_irq:
2509 if (dev->irq > 0)
2510 ksz8463_ptp_irq_free(ds);
2511 free_girq:
2512 if (dev->irq > 0)
2513 ksz_irq_free(&dev->girq);
2514
2515 return ret;
2516 }
2517
ksz8463_teardown(struct dsa_switch * ds)2518 static void ksz8463_teardown(struct dsa_switch *ds)
2519 {
2520 struct ksz_device *dev = ds->priv;
2521
2522 if (dev->irq > 0) {
2523 ksz_ptp_clock_unregister(ds);
2524 ksz8463_ptp_irq_free(ds);
2525 ksz_irq_free(&dev->girq);
2526 }
2527 }
2528
2529 /**
2530 * ksz88x3_drive_strength_write() - Set the drive strength configuration for
2531 * KSZ8863 compatible chip variants.
2532 * @dev: ksz device
2533 * @props: Array of drive strength properties to be set
2534 * @num_props: Number of properties in the array
2535 *
2536 * This function applies the specified drive strength settings to KSZ88X3 chip
2537 * variants (KSZ8873, KSZ8863).
2538 * It ensures the configurations align with what the chip variant supports and
2539 * warns or errors out on unsupported settings.
2540 *
2541 * Return: 0 on success, error code otherwise
2542 */
ksz88x3_drive_strength_write(struct ksz_device * dev,struct ksz_driver_strength_prop * props,int num_props)2543 static int ksz88x3_drive_strength_write(struct ksz_device *dev,
2544 struct ksz_driver_strength_prop *props,
2545 int num_props)
2546 {
2547 size_t array_size = ARRAY_SIZE(ksz88x3_drive_strengths);
2548 int microamp;
2549 int i, ret;
2550
2551 for (i = 0; i < num_props; i++) {
2552 if (props[i].value == -1 || i == KSZ_DRIVER_STRENGTH_IO)
2553 continue;
2554
2555 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
2556 props[i].name);
2557 }
2558
2559 microamp = props[KSZ_DRIVER_STRENGTH_IO].value;
2560 ret = ksz_drive_strength_to_reg(ksz88x3_drive_strengths, array_size,
2561 microamp);
2562 if (ret < 0) {
2563 ksz_drive_strength_error(dev, ksz88x3_drive_strengths,
2564 array_size, microamp);
2565 return ret;
2566 }
2567
2568 return ksz_rmw8(dev, KSZ8873_REG_GLOBAL_CTRL_12,
2569 KSZ8873_DRIVE_STRENGTH_16MA, ret);
2570 }
2571
2572 /**
2573 * ksz8_parse_drive_strength() - Extract and apply drive strength configurations
2574 * from device tree properties.
2575 * @dev: ksz device
2576 *
2577 * This function reads the specified drive strength properties from the
2578 * device tree, validates against the supported chip variants, and sets
2579 * them accordingly. An error should be critical here, as the drive strength
2580 * settings are crucial for EMI compliance.
2581 *
2582 * Return: 0 on success, error code otherwise
2583 */
ksz8_parse_drive_strength(struct ksz_device * dev)2584 static int ksz8_parse_drive_strength(struct ksz_device *dev)
2585 {
2586 struct ksz_driver_strength_prop of_props[] = {
2587 [KSZ_DRIVER_STRENGTH_HI] = {
2588 .name = "microchip,hi-drive-strength-microamp",
2589 .offset = SW_HI_SPEED_DRIVE_STRENGTH_S,
2590 .value = -1,
2591 },
2592 [KSZ_DRIVER_STRENGTH_LO] = {
2593 .name = "microchip,lo-drive-strength-microamp",
2594 .offset = SW_LO_SPEED_DRIVE_STRENGTH_S,
2595 .value = -1,
2596 },
2597 [KSZ_DRIVER_STRENGTH_IO] = {
2598 .name = "microchip,io-drive-strength-microamp",
2599 .offset = 0, /* don't care */
2600 .value = -1,
2601 },
2602 };
2603 struct device_node *np = dev->dev->of_node;
2604 bool have_any_prop = false;
2605 int i, ret;
2606
2607 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
2608 ret = of_property_read_u32(np, of_props[i].name,
2609 &of_props[i].value);
2610 if (ret && ret != -EINVAL)
2611 dev_warn(dev->dev, "Failed to read %s\n",
2612 of_props[i].name);
2613 if (ret)
2614 continue;
2615
2616 have_any_prop = true;
2617 }
2618
2619 if (!have_any_prop)
2620 return 0;
2621
2622 switch (dev->chip_id) {
2623 case KSZ88X3_CHIP_ID:
2624 return ksz88x3_drive_strength_write(dev, of_props,
2625 ARRAY_SIZE(of_props));
2626 case KSZ8795_CHIP_ID:
2627 case KSZ8794_CHIP_ID:
2628 case KSZ8765_CHIP_ID:
2629 return ksz_drive_strength_write(dev, of_props,
2630 ARRAY_SIZE(of_props));
2631 default:
2632 /* KSZ8864, KSZ8895 */
2633 for (i = 0; i < ARRAY_SIZE(of_props); i++) {
2634 if (of_props[i].value == -1)
2635 continue;
2636
2637 dev_warn(dev->dev, "%s is not supported by this chip variant\n",
2638 of_props[i].name);
2639 }
2640 }
2641
2642 return 0;
2643 }
2644
ksz8_setup(struct dsa_switch * ds)2645 static int ksz8_setup(struct dsa_switch *ds)
2646 {
2647 struct ksz_device *dev = ds->priv;
2648 u16 storm_mask, storm_rate;
2649 struct dsa_port *dp;
2650 struct ksz_port *p;
2651 const u16 *regs;
2652 int i, ret;
2653
2654 regs = dev->info->regs;
2655
2656 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
2657 dev->info->num_vlans, GFP_KERNEL);
2658 if (!dev->vlan_cache)
2659 return -ENOMEM;
2660
2661 ret = ksz8_reset_switch(dev);
2662 if (ret) {
2663 dev_err(ds->dev, "failed to reset switch\n");
2664 return ret;
2665 }
2666
2667 ret = ksz8_parse_drive_strength(dev);
2668 if (ret)
2669 return ret;
2670
2671 /* set broadcast storm protection 10% rate */
2672 storm_mask = BROADCAST_STORM_RATE;
2673 storm_rate = (BROADCAST_STORM_VALUE * BROADCAST_STORM_PROT_RATE) / 100;
2674 regmap_update_bits(ksz_regmap_16(dev), regs[S_BROADCAST_CTRL],
2675 storm_mask, storm_rate);
2676
2677 ksz8_config_cpu_port(ds);
2678
2679 ksz8_enable_stp_addr(dev);
2680
2681 ds->num_tx_queues = dev->info->num_tx_queues;
2682
2683 regmap_update_bits(ksz_regmap_8(dev), regs[S_MULTICAST_CTRL],
2684 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
2685
2686 ksz_init_mib_timer(dev);
2687
2688 ds->configure_vlan_while_not_filtering = false;
2689 ds->dscp_prio_mapping_is_global = true;
2690 ds->mtu_enforcement_ingress = true;
2691
2692 /* We rely on software untagging on the CPU port, so that we
2693 * can support both tagged and untagged VLANs
2694 */
2695 ds->untag_bridge_pvid = true;
2696
2697 /* VLAN filtering is partly controlled by the global VLAN
2698 * Enable flag
2699 */
2700 ds->vlan_filtering_is_global = true;
2701
2702 /* Enable automatic fast aging when link changed detected. */
2703 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true);
2704
2705 /* Enable aggressive back off algorithm in half duplex mode. */
2706 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_AGGR_BACKOFF, SW_AGGR_BACKOFF);
2707 if (ret)
2708 return ret;
2709
2710 /*
2711 * Make sure unicast VLAN boundary is set as default and
2712 * enable no excessive collision drop.
2713 */
2714 ret = ksz_rmw8(dev, REG_SW_CTRL_2,
2715 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP,
2716 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP);
2717 if (ret)
2718 return ret;
2719
2720 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false);
2721
2722 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
2723
2724 if (!ksz_is_ksz88x3(dev))
2725 ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true);
2726
2727 for (i = 0; i < (dev->info->num_vlans / 4); i++)
2728 ksz8_r_vlan_entries(dev, i);
2729
2730 /* Make sure PME (WoL) is not enabled. If requested, it will
2731 * be enabled by ksz_wol_pre_shutdown(). Otherwise, some PMICs
2732 * do not like PME events changes before shutdown. PME only
2733 * available on KSZ87xx family.
2734 */
2735 if (ksz_is_ksz87xx(dev)) {
2736 ret = ksz8_pme_write8(dev, regs[REG_SW_PME_CTRL], 0);
2737 if (!ret)
2738 ret = ksz_rmw8(dev, REG_INT_ENABLE, INT_PME, 0);
2739 if (ret)
2740 return ret;
2741 }
2742
2743 /* Initialize KSZ87xx short-cable preset control */
2744 dev->eq_init = KSZ87XX_DSP_EQ_INIT_FACTORY;
2745 dev->lpf_bw = KSZ87XX_PHY_LPF_90MHZ;
2746
2747 ret = ksz8_handle_global_errata(ds);
2748 if (ret)
2749 return ret;
2750
2751 /* Start with learning disabled on standalone user ports, and enabled
2752 * on the CPU port. In lack of other finer mechanisms, learning on the
2753 * CPU port will avoid flooding bridge local addresses on the network
2754 * in some cases.
2755 */
2756 p = &dev->ports[dev->cpu_port];
2757 p->learning = true;
2758
2759 if (dev->irq > 0) {
2760 ret = ksz_girq_setup(dev);
2761 if (ret)
2762 return ret;
2763
2764 dsa_switch_for_each_user_port(dp, dev->ds) {
2765 ret = ksz_pirq_setup(dev, dp->index);
2766 if (ret)
2767 goto port_release;
2768
2769 if (dev->info->ptp_capable) {
2770 ret = ksz_ptp_irq_setup(ds, dp->index);
2771 if (ret)
2772 goto pirq_release;
2773 }
2774 }
2775 }
2776
2777 if (dev->info->ptp_capable) {
2778 ret = ksz_ptp_clock_register(ds);
2779 if (ret) {
2780 dev_err(dev->dev, "Failed to register PTP clock: %d\n",
2781 ret);
2782 goto port_release;
2783 }
2784 }
2785
2786 ret = ksz_mdio_register(dev);
2787 if (ret < 0) {
2788 dev_err(dev->dev, "failed to register the mdio");
2789 goto out_ptp_clock_unregister;
2790 }
2791
2792 ret = ksz_dcb_init(dev);
2793 if (ret)
2794 goto out_ptp_clock_unregister;
2795
2796 /* start switch */
2797 regmap_update_bits(ksz_regmap_8(dev), regs[S_START_CTRL],
2798 SW_START, SW_START);
2799
2800 return 0;
2801
2802 out_ptp_clock_unregister:
2803 if (dev->info->ptp_capable)
2804 ksz_ptp_clock_unregister(ds);
2805 port_release:
2806 if (dev->irq > 0) {
2807 dsa_switch_for_each_user_port_continue_reverse(dp, dev->ds) {
2808 if (dev->info->ptp_capable)
2809 ksz_ptp_irq_free(ds, dp->index);
2810 pirq_release:
2811 ksz_irq_free(&dev->ports[dp->index].pirq);
2812 }
2813 ksz_irq_free(&dev->girq);
2814 }
2815
2816 return ret;
2817 }
2818
ksz8_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)2819 static void ksz8_phylink_get_caps(struct dsa_switch *ds, int port,
2820 struct phylink_config *config)
2821 {
2822 struct ksz_device *dev = ds->priv;
2823
2824 config->mac_capabilities = MAC_10 | MAC_100;
2825
2826 /* Silicon Errata Sheet (DS80000830A):
2827 * "Port 1 does not respond to received flow control PAUSE frames"
2828 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3
2829 * switches.
2830 */
2831 if (!ksz_is_ksz88x3(dev) || port)
2832 config->mac_capabilities |= MAC_SYM_PAUSE;
2833
2834 /* Asym pause is not supported on KSZ8863 and KSZ8873 */
2835 if (!ksz_is_ksz88x3(dev))
2836 config->mac_capabilities |= MAC_ASYM_PAUSE;
2837
2838 ksz_phylink_get_caps(ds, port, config);
2839 }
2840
ksz8_get_port_addr(int port,int offset)2841 static u32 ksz8_get_port_addr(int port, int offset)
2842 {
2843 return PORT_CTRL_ADDR(port, offset);
2844 }
2845
ksz8463_get_port_addr(int port,int offset)2846 static u32 ksz8463_get_port_addr(int port, int offset)
2847 {
2848 if (offset >= KSZ8463_PTP_CLK_CTRL)
2849 return offset + 0x20 * port;
2850
2851 return offset + 0x18 * port;
2852 }
2853
ksz8463_get_phy_addr(u16 phy,u16 reg,u16 offset)2854 static u16 ksz8463_get_phy_addr(u16 phy, u16 reg, u16 offset)
2855 {
2856 return offset + reg * 2 + phy * (P2MBCR - P1MBCR);
2857 }
2858
ksz8463_r_phy(struct ksz_device * dev,u16 phy,u16 reg,u16 * val)2859 static int ksz8463_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
2860 {
2861 u16 sw_reg = 0;
2862 u16 data = 0;
2863 int ret;
2864
2865 if (phy > 1)
2866 return -ENOSPC;
2867 switch (reg) {
2868 case MII_PHYSID1:
2869 sw_reg = ksz8463_get_phy_addr(phy, 0, PHY1IHR);
2870 break;
2871 case MII_PHYSID2:
2872 sw_reg = ksz8463_get_phy_addr(phy, 0, PHY1ILR);
2873 break;
2874 case MII_BMCR:
2875 case MII_BMSR:
2876 case MII_ADVERTISE:
2877 case MII_LPA:
2878 sw_reg = ksz8463_get_phy_addr(phy, reg, P1MBCR);
2879 break;
2880 case MII_TPISTATUS:
2881 /* This register holds the PHY interrupt status for simulated
2882 * Micrel KSZ PHY.
2883 */
2884 data = 0x0505;
2885 break;
2886 default:
2887 break;
2888 }
2889 if (sw_reg) {
2890 ret = ksz_read16(dev, sw_reg, &data);
2891 if (ret)
2892 return ret;
2893 }
2894 *val = data;
2895
2896 return 0;
2897 }
2898
ksz8463_phy_read16(struct dsa_switch * ds,int addr,int reg)2899 static int ksz8463_phy_read16(struct dsa_switch *ds, int addr, int reg)
2900 {
2901 struct ksz_device *dev = ds->priv;
2902 u16 val = 0xffff;
2903 int ret;
2904
2905 ret = ksz8463_r_phy(dev, addr, reg, &val);
2906 if (ret)
2907 return ret;
2908
2909 return val;
2910 }
2911
ksz8463_w_phy(struct ksz_device * dev,u16 phy,u16 reg,u16 val)2912 static int ksz8463_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
2913 {
2914 u16 sw_reg = 0;
2915 int ret;
2916
2917 if (phy > 1)
2918 return -ENOSPC;
2919
2920 /* No write to fiber port. */
2921 if (dev->ports[phy].fiber)
2922 return 0;
2923 switch (reg) {
2924 case MII_BMCR:
2925 case MII_ADVERTISE:
2926 sw_reg = ksz8463_get_phy_addr(phy, reg, P1MBCR);
2927 break;
2928 default:
2929 break;
2930 }
2931 if (sw_reg) {
2932 ret = ksz_write16(dev, sw_reg, val);
2933 if (ret)
2934 return ret;
2935 }
2936
2937 return 0;
2938 }
2939
ksz8463_phy_write16(struct dsa_switch * ds,int addr,int reg,u16 val)2940 static int ksz8463_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
2941 {
2942 struct ksz_device *dev = ds->priv;
2943 int ret;
2944
2945 ret = ksz8463_w_phy(dev, addr, reg, val);
2946 if (ret)
2947 return ret;
2948
2949 return 0;
2950 }
2951
ksz88xx_get_phy_flags(struct dsa_switch * ds,int port)2952 static u32 ksz88xx_get_phy_flags(struct dsa_switch *ds, int port)
2953 {
2954 struct ksz_device *dev = ds->priv;
2955
2956 switch (dev->chip_id) {
2957 case KSZ88X3_CHIP_ID:
2958 /* Silicon Errata Sheet (DS80000830A):
2959 * Port 1 does not work with LinkMD Cable-Testing.
2960 * Port 1 does not respond to received PAUSE control frames.
2961 */
2962 if (!port)
2963 return MICREL_KSZ8_P1_ERRATA;
2964 break;
2965 }
2966
2967 return 0;
2968 }
2969
ksz8_switch_init(struct ksz_device * dev)2970 static int ksz8_switch_init(struct ksz_device *dev)
2971 {
2972 dev->cpu_port = fls(dev->info->cpu_ports) - 1;
2973 dev->phy_port_cnt = dev->info->port_cnt - 1;
2974 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports;
2975
2976 return 0;
2977 }
2978
ksz8463_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)2979 static enum dsa_tag_protocol ksz8463_get_tag_protocol(struct dsa_switch *ds,
2980 int port,
2981 enum dsa_tag_protocol mp)
2982 {
2983 return DSA_TAG_PROTO_KSZ8463;
2984 }
2985
ksz8463_connect_tag_protocol(struct dsa_switch * ds,enum dsa_tag_protocol proto)2986 static int ksz8463_connect_tag_protocol(struct dsa_switch *ds,
2987 enum dsa_tag_protocol proto)
2988 {
2989 struct ksz_tagger_data *tagger_data;
2990
2991 if (proto != DSA_TAG_PROTO_KSZ8463)
2992 return -EPROTONOSUPPORT;
2993
2994 tagger_data = ksz_tagger_data(ds);
2995 tagger_data->xmit_work_fn = ksz_port_deferred_xmit;
2996
2997 return 0;
2998 }
2999
ksz87xx_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)3000 static enum dsa_tag_protocol ksz87xx_get_tag_protocol(struct dsa_switch *ds,
3001 int port,
3002 enum dsa_tag_protocol mp)
3003 {
3004 return DSA_TAG_PROTO_KSZ8795;
3005 }
3006
ksz87xx_connect_tag_protocol(struct dsa_switch * ds,enum dsa_tag_protocol proto)3007 static int ksz87xx_connect_tag_protocol(struct dsa_switch *ds,
3008 enum dsa_tag_protocol proto)
3009 {
3010 if (proto != DSA_TAG_PROTO_KSZ8795)
3011 return -EPROTONOSUPPORT;
3012
3013 return 0;
3014 }
3015
ksz88xx_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)3016 static enum dsa_tag_protocol ksz88xx_get_tag_protocol(struct dsa_switch *ds,
3017 int port,
3018 enum dsa_tag_protocol mp)
3019 {
3020 struct ksz_device *dev = ds->priv;
3021
3022 if (ksz_is_8895_family(dev)) /* KSZ8864, KSZ8895 */
3023 return DSA_TAG_PROTO_KSZ8795;
3024
3025 return DSA_TAG_PROTO_KSZ9893;
3026 }
3027
ksz88xx_connect_tag_protocol(struct dsa_switch * ds,enum dsa_tag_protocol proto)3028 static int ksz88xx_connect_tag_protocol(struct dsa_switch *ds,
3029 enum dsa_tag_protocol proto)
3030 {
3031 struct ksz_tagger_data *tagger_data;
3032
3033 if (ksz_is_8895_family(ds->priv)) { /* KSZ8864, KSZ8895 */
3034 if (proto != DSA_TAG_PROTO_KSZ8795)
3035 return -EPROTONOSUPPORT;
3036
3037 return 0;
3038 }
3039
3040 if (proto != DSA_TAG_PROTO_KSZ9893)
3041 return -EPROTONOSUPPORT;
3042
3043 tagger_data = ksz_tagger_data(ds);
3044 tagger_data->xmit_work_fn = ksz_port_deferred_xmit;
3045
3046 return 0;
3047 }
3048
ksz88x3_phylink_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)3049 static void ksz88x3_phylink_mac_config(struct phylink_config *config,
3050 unsigned int mode,
3051 const struct phylink_link_state *state)
3052 {
3053 struct dsa_port *dp = dsa_phylink_to_port(config);
3054 struct ksz_device *dev = dp->ds->priv;
3055
3056 dev->ports[dp->index].manual_flow = !(state->pause & MLO_PAUSE_AN);
3057 }
3058
3059 const struct phylink_mac_ops ksz88x3_phylink_mac_ops = {
3060 .mac_config = ksz88x3_phylink_mac_config,
3061 .mac_link_down = ksz_phylink_mac_link_down,
3062 .mac_link_up = ksz8_phylink_mac_link_up,
3063 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi,
3064 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi,
3065 };
3066
3067 const struct phylink_mac_ops ksz8_phylink_mac_ops = {
3068 .mac_config = ksz_phylink_mac_config,
3069 .mac_link_down = ksz_phylink_mac_link_down,
3070 .mac_link_up = ksz8_phylink_mac_link_up,
3071 .mac_disable_tx_lpi = ksz_phylink_mac_disable_tx_lpi,
3072 .mac_enable_tx_lpi = ksz_phylink_mac_enable_tx_lpi,
3073 };
3074
3075 const struct ksz_dev_ops ksz8463_dev_ops = {
3076 .get_port_addr = ksz8463_get_port_addr,
3077 .cfg_port_member = ksz8_cfg_port_member,
3078 .r_mib_cnt = ksz8_r_mib_cnt,
3079 .r_mib_pkt = ksz8_r_mib_pkt,
3080 .r_mib_stat64 = ksz88xx_r_mib_stats64,
3081 .freeze_mib = ksz8_freeze_mib,
3082 .port_init_cnt = ksz8_port_init_cnt,
3083 .init = ksz8_switch_init,
3084 };
3085
3086 const struct ksz_dev_ops ksz87xx_dev_ops = {
3087 .get_port_addr = ksz8_get_port_addr,
3088 .cfg_port_member = ksz8_cfg_port_member,
3089 .r_mib_cnt = ksz8_r_mib_cnt,
3090 .r_mib_pkt = ksz8_r_mib_pkt,
3091 .r_mib_stat64 = ksz_r_mib_stats64,
3092 .freeze_mib = ksz8_freeze_mib,
3093 .port_init_cnt = ksz8_port_init_cnt,
3094 .init = ksz8_switch_init,
3095 .pme_write8 = ksz8_pme_write8,
3096 .pme_pread8 = ksz8_pme_pread8,
3097 .pme_pwrite8 = ksz8_pme_pwrite8,
3098 };
3099
3100 const struct ksz_dev_ops ksz88xx_dev_ops = {
3101 .get_port_addr = ksz8_get_port_addr,
3102 .cfg_port_member = ksz8_cfg_port_member,
3103 .r_mib_cnt = ksz8_r_mib_cnt,
3104 .r_mib_pkt = ksz8_r_mib_pkt,
3105 .r_mib_stat64 = ksz88xx_r_mib_stats64,
3106 .freeze_mib = ksz8_freeze_mib,
3107 .port_init_cnt = ksz8_port_init_cnt,
3108 .init = ksz8_switch_init,
3109 .pme_write8 = ksz8_pme_write8,
3110 .pme_pread8 = ksz8_pme_pread8,
3111 .pme_pwrite8 = ksz8_pme_pwrite8,
3112 };
3113
3114 const struct dsa_switch_ops ksz8463_switch_ops = {
3115 .get_tag_protocol = ksz8463_get_tag_protocol,
3116 .connect_tag_protocol = ksz8463_connect_tag_protocol,
3117 .setup = ksz8463_setup,
3118 .teardown = ksz8463_teardown,
3119 .phy_read = ksz8463_phy_read16,
3120 .phy_write = ksz8463_phy_write16,
3121 .phylink_get_caps = ksz8_phylink_get_caps,
3122 .port_setup = ksz8_dsa_port_setup,
3123 .get_strings = ksz_get_strings,
3124 .get_ethtool_stats = ksz_get_ethtool_stats,
3125 .get_sset_count = ksz_sset_count,
3126 .port_bridge_join = ksz_port_bridge_join,
3127 .port_bridge_leave = ksz_port_bridge_leave,
3128 .port_set_mac_address = ksz_port_set_mac_address,
3129 .port_stp_state_set = ksz_port_stp_state_set,
3130 .port_pre_bridge_flags = ksz_port_pre_bridge_flags,
3131 .port_bridge_flags = ksz_port_bridge_flags,
3132 .port_fast_age = ksz8_flush_dyn_mac_table,
3133 .port_fdb_dump = ksz8_fdb_dump,
3134 .port_fdb_add = ksz8_fdb_add,
3135 .port_fdb_del = ksz8_fdb_del,
3136 .port_mdb_add = ksz8_mdb_add,
3137 .port_mdb_del = ksz8_mdb_del,
3138 .port_mirror_add = ksz8_port_mirror_add,
3139 .port_mirror_del = ksz8_port_mirror_del,
3140 .get_stats64 = ksz_get_stats64,
3141 .get_pause_stats = ksz_get_pause_stats,
3142 .port_change_mtu = ksz88xx_change_mtu,
3143 .port_max_mtu = ksz88xx_max_mtu,
3144 .suspend = ksz_suspend,
3145 .resume = ksz_resume,
3146 .get_ts_info = ksz8463_get_ts_info,
3147 .port_hwtstamp_get = ksz_hwtstamp_get,
3148 .port_hwtstamp_set = ksz8463_hwtstamp_set,
3149 .port_txtstamp = ksz_port_txtstamp,
3150 .port_rxtstamp = ksz_port_rxtstamp,
3151 .port_setup_tc = ksz8_setup_tc,
3152 .port_get_default_prio = ksz_port_get_default_prio,
3153 .port_set_default_prio = ksz_port_set_default_prio,
3154 .port_get_dscp_prio = ksz_port_get_dscp_prio,
3155 .port_add_dscp_prio = ksz_port_add_dscp_prio,
3156 .port_del_dscp_prio = ksz_port_del_dscp_prio,
3157 .port_get_apptrust = ksz_port_get_apptrust,
3158 .port_set_apptrust = ksz_port_set_apptrust,
3159 };
3160
3161 const struct dsa_switch_ops ksz87xx_switch_ops = {
3162 .get_tag_protocol = ksz87xx_get_tag_protocol,
3163 .connect_tag_protocol = ksz87xx_connect_tag_protocol,
3164 .setup = ksz8_setup,
3165 .teardown = ksz_teardown,
3166 .phy_read = ksz8_phy_read16,
3167 .phy_write = ksz8_phy_write16,
3168 .phylink_get_caps = ksz8_phylink_get_caps,
3169 .port_setup = ksz8_dsa_port_setup,
3170 .get_strings = ksz_get_strings,
3171 .get_ethtool_stats = ksz_get_ethtool_stats,
3172 .get_sset_count = ksz_sset_count,
3173 .port_bridge_join = ksz_port_bridge_join,
3174 .port_bridge_leave = ksz_port_bridge_leave,
3175 .port_set_mac_address = ksz_port_set_mac_address,
3176 .port_stp_state_set = ksz_port_stp_state_set,
3177 .port_pre_bridge_flags = ksz_port_pre_bridge_flags,
3178 .port_bridge_flags = ksz_port_bridge_flags,
3179 .port_fast_age = ksz8_flush_dyn_mac_table,
3180 .port_vlan_filtering = ksz8_port_vlan_filtering,
3181 .port_vlan_add = ksz8_port_vlan_add,
3182 .port_vlan_del = ksz8_port_vlan_del,
3183 .port_fdb_dump = ksz8_fdb_dump,
3184 .port_fdb_add = ksz8_fdb_add,
3185 .port_fdb_del = ksz8_fdb_del,
3186 .port_mdb_add = ksz8_mdb_add,
3187 .port_mdb_del = ksz8_mdb_del,
3188 .port_mirror_add = ksz8_port_mirror_add,
3189 .port_mirror_del = ksz8_port_mirror_del,
3190 .get_stats64 = ksz_get_stats64,
3191 .get_pause_stats = ksz_get_pause_stats,
3192 .port_change_mtu = ksz87xx_change_mtu,
3193 .port_max_mtu = ksz87xx_max_mtu,
3194 .suspend = ksz_suspend,
3195 .resume = ksz_resume,
3196 .get_ts_info = ksz_get_ts_info,
3197 .port_hwtstamp_get = ksz_hwtstamp_get,
3198 .port_hwtstamp_set = ksz_hwtstamp_set,
3199 .port_txtstamp = ksz_port_txtstamp,
3200 .port_rxtstamp = ksz_port_rxtstamp,
3201 .port_setup_tc = ksz87xx_setup_tc,
3202 .port_get_default_prio = ksz_port_get_default_prio,
3203 .port_set_default_prio = ksz_port_set_default_prio,
3204 .port_get_dscp_prio = ksz_port_get_dscp_prio,
3205 .port_add_dscp_prio = ksz_port_add_dscp_prio,
3206 .port_del_dscp_prio = ksz_port_del_dscp_prio,
3207 .port_get_apptrust = ksz_port_get_apptrust,
3208 .port_set_apptrust = ksz_port_set_apptrust,
3209 };
3210
3211 const struct dsa_switch_ops ksz88xx_switch_ops = {
3212 .get_tag_protocol = ksz88xx_get_tag_protocol,
3213 .connect_tag_protocol = ksz88xx_connect_tag_protocol,
3214 .get_phy_flags = ksz88xx_get_phy_flags,
3215 .setup = ksz8_setup,
3216 .teardown = ksz_teardown,
3217 .phy_read = ksz8_phy_read16,
3218 .phy_write = ksz8_phy_write16,
3219 .phylink_get_caps = ksz8_phylink_get_caps,
3220 .port_setup = ksz8_dsa_port_setup,
3221 .get_strings = ksz_get_strings,
3222 .get_ethtool_stats = ksz_get_ethtool_stats,
3223 .get_sset_count = ksz_sset_count,
3224 .port_bridge_join = ksz_port_bridge_join,
3225 .port_bridge_leave = ksz_port_bridge_leave,
3226 .port_set_mac_address = ksz_port_set_mac_address,
3227 .port_stp_state_set = ksz_port_stp_state_set,
3228 .port_pre_bridge_flags = ksz_port_pre_bridge_flags,
3229 .port_bridge_flags = ksz_port_bridge_flags,
3230 .port_fast_age = ksz8_flush_dyn_mac_table,
3231 .port_vlan_filtering = ksz8_port_vlan_filtering,
3232 .port_vlan_add = ksz8_port_vlan_add,
3233 .port_vlan_del = ksz8_port_vlan_del,
3234 .port_fdb_dump = ksz8_fdb_dump,
3235 .port_fdb_add = ksz8_fdb_add,
3236 .port_fdb_del = ksz8_fdb_del,
3237 .port_mdb_add = ksz8_mdb_add,
3238 .port_mdb_del = ksz8_mdb_del,
3239 .port_mirror_add = ksz8_port_mirror_add,
3240 .port_mirror_del = ksz8_port_mirror_del,
3241 .get_stats64 = ksz_get_stats64,
3242 .get_pause_stats = ksz_get_pause_stats,
3243 .port_change_mtu = ksz88xx_change_mtu,
3244 .port_max_mtu = ksz88xx_max_mtu,
3245 .get_wol = ksz_get_wol,
3246 .set_wol = ksz_set_wol,
3247 .suspend = ksz_suspend,
3248 .resume = ksz_resume,
3249 .get_ts_info = ksz_get_ts_info,
3250 .port_hwtstamp_get = ksz_hwtstamp_get,
3251 .port_hwtstamp_set = ksz_hwtstamp_set,
3252 .port_txtstamp = ksz_port_txtstamp,
3253 .port_rxtstamp = ksz_port_rxtstamp,
3254 .port_setup_tc = ksz8_setup_tc,
3255 .port_get_default_prio = ksz_port_get_default_prio,
3256 .port_set_default_prio = ksz_port_set_default_prio,
3257 .port_get_dscp_prio = ksz_port_get_dscp_prio,
3258 .port_add_dscp_prio = ksz_port_add_dscp_prio,
3259 .port_del_dscp_prio = ksz_port_del_dscp_prio,
3260 .port_get_apptrust = ksz_port_get_apptrust,
3261 .port_set_apptrust = ksz_port_set_apptrust,
3262 };
3263
3264 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>");
3265 MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver");
3266 MODULE_LICENSE("GPL");
3267