1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_svm.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 #include "amdgpu_xcp.h" 38 39 #define MQD_SIZE_ALIGNED 768 40 41 /* 42 * kfd_locked is used to lock the kfd driver during suspend or reset 43 * once locked, kfd driver will stop any further GPU execution. 44 * create process (open) will return -EAGAIN. 45 */ 46 static int kfd_locked; 47 48 #ifdef CONFIG_DRM_AMDGPU_CIK 49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 50 #endif 51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 53 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 59 extern const struct kfd2kgd_calls gfx_v12_kfd2kgd; 60 extern const struct kfd2kgd_calls gfx_v12_1_kfd2kgd; 61 62 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 63 unsigned int chunk_size); 64 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 65 66 static int kfd_resume(struct kfd_node *kfd); 67 68 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 69 { 70 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0); 71 72 switch (sdma_version) { 73 case IP_VERSION(4, 0, 0):/* VEGA10 */ 74 case IP_VERSION(4, 0, 1):/* VEGA12 */ 75 case IP_VERSION(4, 1, 0):/* RAVEN */ 76 case IP_VERSION(4, 1, 1):/* RAVEN */ 77 case IP_VERSION(4, 1, 2):/* RENOIR */ 78 case IP_VERSION(5, 2, 1):/* VANGOGH */ 79 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 80 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 81 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 82 kfd->device_info.num_sdma_queues_per_engine = 2; 83 break; 84 case IP_VERSION(4, 2, 0):/* VEGA20 */ 85 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 86 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 87 case IP_VERSION(4, 4, 2): 88 case IP_VERSION(4, 4, 5): 89 case IP_VERSION(4, 4, 4): 90 case IP_VERSION(5, 0, 0):/* NAVI10 */ 91 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 92 case IP_VERSION(5, 0, 2):/* NAVI14 */ 93 case IP_VERSION(5, 0, 5):/* NAVI12 */ 94 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 95 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 96 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 97 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 98 kfd->device_info.num_sdma_queues_per_engine = 8; 99 break; 100 case IP_VERSION(6, 0, 0): 101 case IP_VERSION(6, 0, 1): 102 case IP_VERSION(6, 0, 2): 103 case IP_VERSION(6, 0, 3): 104 case IP_VERSION(6, 1, 0): 105 case IP_VERSION(6, 1, 1): 106 case IP_VERSION(6, 1, 2): 107 case IP_VERSION(6, 1, 3): 108 case IP_VERSION(6, 1, 4): 109 case IP_VERSION(7, 0, 0): 110 case IP_VERSION(7, 0, 1): 111 case IP_VERSION(7, 1, 0): 112 kfd->device_info.num_sdma_queues_per_engine = 8; 113 /* Reserve 1 for paging and 1 for gfx */ 114 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 115 break; 116 default: 117 dev_warn(kfd_device, 118 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 119 sdma_version); 120 kfd->device_info.num_sdma_queues_per_engine = 8; 121 } 122 } 123 124 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 125 { 126 uint32_t gc_version = KFD_GC_VERSION(kfd); 127 128 switch (gc_version) { 129 case IP_VERSION(9, 0, 1): /* VEGA10 */ 130 case IP_VERSION(9, 1, 0): /* RAVEN */ 131 case IP_VERSION(9, 2, 1): /* VEGA12 */ 132 case IP_VERSION(9, 2, 2): /* RAVEN */ 133 case IP_VERSION(9, 3, 0): /* RENOIR */ 134 case IP_VERSION(9, 4, 0): /* VEGA20 */ 135 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 136 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 137 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 138 break; 139 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 140 case IP_VERSION(9, 4, 4): /* GC 9.4.4 */ 141 case IP_VERSION(9, 5, 0): /* GC 9.5.0 */ 142 kfd->device_info.event_interrupt_class = 143 &event_interrupt_class_v9_4_3; 144 break; 145 case IP_VERSION(10, 3, 1): /* VANGOGH */ 146 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 147 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 148 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 149 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 150 case IP_VERSION(10, 1, 4): 151 case IP_VERSION(10, 1, 10): /* NAVI10 */ 152 case IP_VERSION(10, 1, 2): /* NAVI12 */ 153 case IP_VERSION(10, 1, 1): /* NAVI14 */ 154 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 155 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 156 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 157 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 158 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 159 break; 160 case IP_VERSION(11, 0, 0): 161 case IP_VERSION(11, 0, 1): 162 case IP_VERSION(11, 0, 2): 163 case IP_VERSION(11, 0, 3): 164 case IP_VERSION(11, 0, 4): 165 case IP_VERSION(11, 5, 0): 166 case IP_VERSION(11, 5, 1): 167 case IP_VERSION(11, 5, 2): 168 case IP_VERSION(11, 5, 3): 169 case IP_VERSION(11, 5, 4): 170 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 171 break; 172 case IP_VERSION(12, 0, 0): 173 case IP_VERSION(12, 0, 1): 174 /* GFX12_TODO: Change to v12 version. */ 175 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 176 break; 177 case IP_VERSION(12, 1, 0): 178 kfd->device_info.event_interrupt_class = 179 &event_interrupt_class_v12_1; 180 break; 181 default: 182 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 183 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 184 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 185 } 186 } 187 188 static void kfd_device_info_init(struct kfd_dev *kfd, 189 bool vf, uint32_t gfx_target_version) 190 { 191 uint32_t gc_version = KFD_GC_VERSION(kfd); 192 uint32_t asic_type = kfd->adev->asic_type; 193 194 kfd->device_info.max_pasid_bits = 16; 195 kfd->device_info.max_no_of_hqd = 24; 196 kfd->device_info.num_of_watch_points = 4; 197 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 198 kfd->device_info.gfx_target_version = gfx_target_version; 199 200 if (KFD_IS_SOC15(kfd)) { 201 kfd->device_info.doorbell_size = 8; 202 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 203 kfd->device_info.supports_cwsr = true; 204 205 kfd_device_info_set_sdma_info(kfd); 206 207 kfd_device_info_set_event_interrupt_class(kfd); 208 209 if (gc_version < IP_VERSION(11, 0, 0)) { 210 /* Navi2x+, Navi1x+ */ 211 if (gc_version == IP_VERSION(10, 3, 6)) 212 kfd->device_info.no_atomic_fw_version = 14; 213 else if (gc_version == IP_VERSION(10, 3, 7)) 214 kfd->device_info.no_atomic_fw_version = 3; 215 else if (gc_version >= IP_VERSION(10, 3, 0)) 216 kfd->device_info.no_atomic_fw_version = 92; 217 else if (gc_version >= IP_VERSION(10, 1, 1)) 218 kfd->device_info.no_atomic_fw_version = 145; 219 220 /* Navi1x+ */ 221 if (gc_version >= IP_VERSION(10, 1, 1)) 222 kfd->device_info.needs_pci_atomics = true; 223 } else if (gc_version < IP_VERSION(12, 0, 0)) { 224 /* 225 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 226 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 227 * PCIe atomics support. 228 */ 229 kfd->device_info.needs_pci_atomics = true; 230 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 231 } else if (gc_version < IP_VERSION(13, 0, 0)) { 232 kfd->device_info.needs_pci_atomics = true; 233 kfd->device_info.no_atomic_fw_version = 2090; 234 } else { 235 kfd->device_info.needs_pci_atomics = true; 236 } 237 } else { 238 kfd->device_info.doorbell_size = 4; 239 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 240 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 241 kfd->device_info.num_sdma_queues_per_engine = 2; 242 243 if (asic_type != CHIP_KAVERI && 244 asic_type != CHIP_HAWAII && 245 asic_type != CHIP_TONGA) 246 kfd->device_info.supports_cwsr = true; 247 248 if (asic_type != CHIP_HAWAII && !vf) 249 kfd->device_info.needs_pci_atomics = true; 250 } 251 } 252 253 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 254 { 255 struct kfd_dev *kfd = NULL; 256 const struct kfd2kgd_calls *f2g = NULL; 257 uint32_t gfx_target_version = 0; 258 259 switch (adev->asic_type) { 260 #ifdef CONFIG_DRM_AMDGPU_CIK 261 case CHIP_KAVERI: 262 gfx_target_version = 70000; 263 if (!vf) 264 f2g = &gfx_v7_kfd2kgd; 265 break; 266 #endif 267 case CHIP_CARRIZO: 268 gfx_target_version = 80001; 269 if (!vf) 270 f2g = &gfx_v8_kfd2kgd; 271 break; 272 #ifdef CONFIG_DRM_AMDGPU_CIK 273 case CHIP_HAWAII: 274 gfx_target_version = 70001; 275 if (!amdgpu_exp_hw_support) 276 pr_info( 277 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 278 ); 279 else if (!vf) 280 f2g = &gfx_v7_kfd2kgd; 281 break; 282 #endif 283 case CHIP_TONGA: 284 gfx_target_version = 80002; 285 if (!vf) 286 f2g = &gfx_v8_kfd2kgd; 287 break; 288 case CHIP_FIJI: 289 case CHIP_POLARIS10: 290 gfx_target_version = 80003; 291 f2g = &gfx_v8_kfd2kgd; 292 break; 293 case CHIP_POLARIS11: 294 case CHIP_POLARIS12: 295 case CHIP_VEGAM: 296 gfx_target_version = 80003; 297 if (!vf) 298 f2g = &gfx_v8_kfd2kgd; 299 break; 300 default: 301 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 302 /* Vega 10 */ 303 case IP_VERSION(9, 0, 1): 304 gfx_target_version = 90000; 305 f2g = &gfx_v9_kfd2kgd; 306 break; 307 /* Raven */ 308 case IP_VERSION(9, 1, 0): 309 case IP_VERSION(9, 2, 2): 310 gfx_target_version = 90002; 311 if (!vf) 312 f2g = &gfx_v9_kfd2kgd; 313 break; 314 /* Vega12 */ 315 case IP_VERSION(9, 2, 1): 316 gfx_target_version = 90004; 317 if (!vf) 318 f2g = &gfx_v9_kfd2kgd; 319 break; 320 /* Renoir */ 321 case IP_VERSION(9, 3, 0): 322 gfx_target_version = 90012; 323 if (!vf) 324 f2g = &gfx_v9_kfd2kgd; 325 break; 326 /* Vega20 */ 327 case IP_VERSION(9, 4, 0): 328 gfx_target_version = 90006; 329 if (!vf) 330 f2g = &gfx_v9_kfd2kgd; 331 break; 332 /* Arcturus */ 333 case IP_VERSION(9, 4, 1): 334 gfx_target_version = 90008; 335 f2g = &arcturus_kfd2kgd; 336 break; 337 /* Aldebaran */ 338 case IP_VERSION(9, 4, 2): 339 gfx_target_version = 90010; 340 f2g = &aldebaran_kfd2kgd; 341 break; 342 case IP_VERSION(9, 4, 3): 343 case IP_VERSION(9, 4, 4): 344 gfx_target_version = 90402; 345 f2g = &gc_9_4_3_kfd2kgd; 346 break; 347 case IP_VERSION(9, 5, 0): 348 gfx_target_version = 90500; 349 f2g = &gc_9_4_3_kfd2kgd; 350 break; 351 /* Navi10 */ 352 case IP_VERSION(10, 1, 10): 353 gfx_target_version = 100100; 354 if (!vf) 355 f2g = &gfx_v10_kfd2kgd; 356 break; 357 /* Navi12 */ 358 case IP_VERSION(10, 1, 2): 359 gfx_target_version = 100101; 360 f2g = &gfx_v10_kfd2kgd; 361 break; 362 /* Navi14 */ 363 case IP_VERSION(10, 1, 1): 364 gfx_target_version = 100102; 365 if (!vf) 366 f2g = &gfx_v10_kfd2kgd; 367 break; 368 /* Cyan Skillfish */ 369 case IP_VERSION(10, 1, 3): 370 case IP_VERSION(10, 1, 4): 371 gfx_target_version = 100103; 372 if (!vf) 373 f2g = &gfx_v10_kfd2kgd; 374 break; 375 /* Sienna Cichlid */ 376 case IP_VERSION(10, 3, 0): 377 gfx_target_version = 100300; 378 f2g = &gfx_v10_3_kfd2kgd; 379 break; 380 /* Navy Flounder */ 381 case IP_VERSION(10, 3, 2): 382 gfx_target_version = 100301; 383 f2g = &gfx_v10_3_kfd2kgd; 384 break; 385 /* Van Gogh */ 386 case IP_VERSION(10, 3, 1): 387 gfx_target_version = 100303; 388 if (!vf) 389 f2g = &gfx_v10_3_kfd2kgd; 390 break; 391 /* Dimgrey Cavefish */ 392 case IP_VERSION(10, 3, 4): 393 gfx_target_version = 100302; 394 f2g = &gfx_v10_3_kfd2kgd; 395 break; 396 /* Beige Goby */ 397 case IP_VERSION(10, 3, 5): 398 gfx_target_version = 100304; 399 f2g = &gfx_v10_3_kfd2kgd; 400 break; 401 /* Yellow Carp */ 402 case IP_VERSION(10, 3, 3): 403 gfx_target_version = 100305; 404 if (!vf) 405 f2g = &gfx_v10_3_kfd2kgd; 406 break; 407 case IP_VERSION(10, 3, 6): 408 case IP_VERSION(10, 3, 7): 409 gfx_target_version = 100306; 410 if (!vf) 411 f2g = &gfx_v10_3_kfd2kgd; 412 break; 413 case IP_VERSION(11, 0, 0): 414 gfx_target_version = 110000; 415 f2g = &gfx_v11_kfd2kgd; 416 break; 417 case IP_VERSION(11, 0, 1): 418 case IP_VERSION(11, 0, 4): 419 gfx_target_version = 110003; 420 f2g = &gfx_v11_kfd2kgd; 421 break; 422 case IP_VERSION(11, 0, 2): 423 gfx_target_version = 110002; 424 f2g = &gfx_v11_kfd2kgd; 425 break; 426 case IP_VERSION(11, 0, 3): 427 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 428 gfx_target_version = 110001; 429 f2g = &gfx_v11_kfd2kgd; 430 break; 431 case IP_VERSION(11, 5, 0): 432 gfx_target_version = 110500; 433 f2g = &gfx_v11_kfd2kgd; 434 break; 435 case IP_VERSION(11, 5, 1): 436 gfx_target_version = 110501; 437 f2g = &gfx_v11_kfd2kgd; 438 break; 439 case IP_VERSION(11, 5, 2): 440 gfx_target_version = 110502; 441 f2g = &gfx_v11_kfd2kgd; 442 break; 443 case IP_VERSION(11, 5, 3): 444 gfx_target_version = 110503; 445 f2g = &gfx_v11_kfd2kgd; 446 break; 447 case IP_VERSION(11, 5, 4): 448 gfx_target_version = 110504; 449 f2g = &gfx_v11_kfd2kgd; 450 break; 451 case IP_VERSION(12, 0, 0): 452 gfx_target_version = 120000; 453 f2g = &gfx_v12_kfd2kgd; 454 break; 455 case IP_VERSION(12, 0, 1): 456 gfx_target_version = 120001; 457 f2g = &gfx_v12_kfd2kgd; 458 break; 459 case IP_VERSION(12, 1, 0): 460 gfx_target_version = 120500; 461 f2g = &gfx_v12_1_kfd2kgd; 462 break; 463 default: 464 break; 465 } 466 break; 467 } 468 469 if (!f2g) { 470 if (amdgpu_ip_version(adev, GC_HWIP, 0)) 471 dev_info(kfd_device, 472 "GC IP %06x %s not supported in kfd\n", 473 amdgpu_ip_version(adev, GC_HWIP, 0), 474 vf ? "VF" : ""); 475 else 476 dev_info(kfd_device, "%s %s not supported in kfd\n", 477 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 478 return NULL; 479 } 480 481 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL); 482 if (!kfd) 483 return NULL; 484 485 kfd->adev = adev; 486 kfd_device_info_init(kfd, vf, gfx_target_version); 487 kfd->init_complete = false; 488 kfd->kfd2kgd = f2g; 489 atomic_set(&kfd->compute_profile, 0); 490 491 mutex_init(&kfd->doorbell_mutex); 492 493 ida_init(&kfd->doorbell_ida); 494 atomic_set(&kfd->kfd_processes_count, 0); 495 496 return kfd; 497 } 498 499 static void kfd_cwsr_init(struct kfd_dev *kfd) 500 { 501 if (cwsr_enable && kfd->device_info.supports_cwsr) { 502 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 503 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) 504 > KFD_CWSR_TMA_OFFSET); 505 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 506 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 507 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 508 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) 509 > KFD_CWSR_TMA_OFFSET); 510 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 511 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 512 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 513 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) 514 > KFD_CWSR_TMA_OFFSET); 515 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 516 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 517 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 518 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) { 519 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) 520 > KFD_CWSR_TMA_OFFSET); 521 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 522 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 523 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 5, 0)) { 524 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_5_0_hex) > PAGE_SIZE); 525 kfd->cwsr_isa = cwsr_trap_gfx9_5_0_hex; 526 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_5_0_hex); 527 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 528 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) 529 > KFD_CWSR_TMA_OFFSET); 530 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 531 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 532 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 533 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) 534 > KFD_CWSR_TMA_OFFSET); 535 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 536 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 537 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 538 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) 539 > KFD_CWSR_TMA_OFFSET); 540 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 541 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 542 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0)) { 543 /* The gfx11 cwsr trap handler must fit inside a single 544 page. */ 545 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 546 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 547 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 548 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 1, 0)) { 549 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex) 550 > KFD_CWSR_TMA_OFFSET); 551 kfd->cwsr_isa = cwsr_trap_gfx12_hex; 552 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex); 553 } else { 554 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_1_0_hex) 555 > KFD_CWSR_TMA_OFFSET); 556 kfd->cwsr_isa = cwsr_trap_gfx12_1_0_hex; 557 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_1_0_hex); 558 } 559 560 kfd->cwsr_enabled = true; 561 } 562 } 563 564 static int kfd_gws_init(struct kfd_node *node) 565 { 566 int ret = 0; 567 struct kfd_dev *kfd = node->kfd; 568 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 569 570 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 571 return 0; 572 573 if (hws_gws_support || (KFD_IS_SOC15(node) && 574 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 575 && kfd->mec2_fw_version >= 0x81b3) || 576 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 577 && kfd->mec2_fw_version >= 0x1b3) || 578 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 579 && kfd->mec2_fw_version >= 0x30) || 580 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 581 && kfd->mec2_fw_version >= 0x28) || 582 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3) || 583 KFD_GC_VERSION(node) == IP_VERSION(9, 4, 4)) || 584 (KFD_GC_VERSION(node) == IP_VERSION(9, 5, 0)) || 585 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 586 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 587 && kfd->mec2_fw_version >= 0x6b) || 588 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0) 589 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0) 590 && mes_rev >= 68) || 591 (KFD_GC_VERSION(node) >= IP_VERSION(12, 0, 0))))) { 592 if (KFD_GC_VERSION(node) >= IP_VERSION(12, 0, 0)) 593 node->adev->gds.gws_size = 64; 594 ret = amdgpu_amdkfd_alloc_gws(node->adev, 595 node->adev->gds.gws_size, &node->gws); 596 } 597 598 return ret; 599 } 600 601 static void kfd_smi_init(struct kfd_node *dev) 602 { 603 INIT_LIST_HEAD(&dev->smi_clients); 604 spin_lock_init(&dev->smi_lock); 605 } 606 607 static int kfd_init_node(struct kfd_node *node) 608 { 609 int err = -1; 610 611 if (kfd_interrupt_init(node)) { 612 dev_err(kfd_device, "Error initializing interrupts\n"); 613 goto kfd_interrupt_error; 614 } 615 616 node->dqm = device_queue_manager_init(node); 617 if (!node->dqm) { 618 dev_err(kfd_device, "Error initializing queue manager\n"); 619 goto device_queue_manager_error; 620 } 621 622 if (kfd_gws_init(node)) { 623 dev_err(kfd_device, "Could not allocate %d gws\n", 624 node->adev->gds.gws_size); 625 goto gws_error; 626 } 627 628 if (kfd_resume(node)) 629 goto kfd_resume_error; 630 631 if (kfd_topology_add_device(node)) { 632 dev_err(kfd_device, "Error adding device to topology\n"); 633 goto kfd_topology_add_device_error; 634 } 635 636 kfd_smi_init(node); 637 638 return 0; 639 640 kfd_topology_add_device_error: 641 kfd_resume_error: 642 gws_error: 643 device_queue_manager_uninit(node->dqm); 644 device_queue_manager_error: 645 kfd_interrupt_exit(node); 646 kfd_interrupt_error: 647 if (node->gws) 648 amdgpu_amdkfd_free_gws(node->adev, node->gws); 649 650 /* Cleanup the node memory here */ 651 kfree(node); 652 return err; 653 } 654 655 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 656 { 657 struct kfd_node *knode; 658 unsigned int i; 659 660 /* 661 * flush_work ensures that there are no outstanding 662 * work-queue items that will access interrupt_ring. New work items 663 * can't be created because we stopped interrupt handling above. 664 */ 665 flush_workqueue(kfd->ih_wq); 666 destroy_workqueue(kfd->ih_wq); 667 668 for (i = 0; i < num_nodes; i++) { 669 knode = kfd->nodes[i]; 670 device_queue_manager_uninit(knode->dqm); 671 kfd_interrupt_exit(knode); 672 kfd_topology_remove_device(knode); 673 if (knode->gws) 674 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 675 kfree(knode); 676 kfd->nodes[i] = NULL; 677 } 678 } 679 680 static void kfd_setup_interrupt_bitmap(struct kfd_node *node, 681 unsigned int kfd_node_idx) 682 { 683 struct amdgpu_device *adev = node->adev; 684 uint32_t xcc_mask = node->xcc_mask; 685 uint32_t xcc, mapped_xcc; 686 uint32_t bitmap; 687 /* 688 * Interrupt bitmap is setup for processing interrupts from 689 * different XCDs and AIDs. 690 * Interrupt bitmap is defined as follows: 691 * 1. Bits 0-15 - correspond to the NodeId field. 692 * Each bit corresponds to NodeId number. For example, if 693 * a KFD node has interrupt bitmap set to 0x7, then this 694 * KFD node will process interrupts with NodeId = 0, 1 and 2 695 * in the IH cookie. 696 * 2. Bits 16-31 - unused. 697 * 698 * Please note that the kfd_node_idx argument passed to this 699 * function is not related to NodeId field received in the 700 * IH cookie. 701 * 702 * In CPX mode, a KFD node will process an interrupt if: 703 * - the Node Id matches the corresponding bit set in 704 * Bits 0-15. 705 * - AND VMID reported in the interrupt lies within the 706 * VMID range of the node. 707 */ 708 switch (KFD_GC_VERSION(node)) { 709 case IP_VERSION(12, 1, 0): 710 for_each_inst(xcc, xcc_mask) { 711 mapped_xcc = GET_INST(GC, xcc); 712 bitmap = 0x2 | (0x4 << (mapped_xcc % 4)); 713 if (mapped_xcc/4) 714 bitmap = bitmap << 8; 715 node->interrupt_bitmap |= bitmap; 716 } 717 break; 718 default: 719 for_each_inst(xcc, xcc_mask) { 720 mapped_xcc = GET_INST(GC, xcc); 721 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); 722 } 723 break; 724 } 725 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, 726 node->interrupt_bitmap); 727 } 728 729 bool kgd2kfd_device_init(struct kfd_dev *kfd, 730 const struct kgd2kfd_shared_resources *gpu_resources) 731 { 732 unsigned int size, map_process_packet_size, i; 733 struct kfd_node *node; 734 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 735 unsigned int max_proc_per_quantum; 736 int partition_mode; 737 int xcp_idx; 738 739 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 740 KGD_ENGINE_MEC1); 741 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 742 KGD_ENGINE_MEC2); 743 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 744 KGD_ENGINE_SDMA1); 745 kfd->shared_resources = *gpu_resources; 746 747 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 748 749 if (kfd->num_nodes == 0) { 750 dev_err(kfd_device, 751 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 752 kfd->adev->gfx.num_xcc_per_xcp); 753 goto out; 754 } 755 756 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 757 * 32 and 64-bit requests are possible and must be 758 * supported. 759 */ 760 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 761 if (!kfd->pci_atomic_requested && 762 kfd->device_info.needs_pci_atomics && 763 (!kfd->device_info.no_atomic_fw_version || 764 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 765 dev_info(kfd_device, 766 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 767 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 768 kfd->mec_fw_version, 769 kfd->device_info.no_atomic_fw_version); 770 return false; 771 } 772 773 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 774 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 775 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 776 777 /* For multi-partition capable GPUs, we need special handling for VMIDs 778 * depending on partition mode. 779 * In CPX mode, the VMID range needs to be shared between XCDs. 780 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 781 * divide them equally, we change starting VMID to 4 and not use 782 * VMID 3. 783 * If the VMID range changes for multi-partition capable GPUs, then 784 * this code MUST be revisited. 785 */ 786 if (kfd->adev->xcp_mgr && (KFD_GC_VERSION(kfd) != IP_VERSION(12, 1, 0))) { 787 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 788 AMDGPU_XCP_FL_LOCKED); 789 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 790 kfd->num_nodes != 1) { 791 vmid_num_kfd /= 2; 792 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 793 } 794 } 795 796 /* Verify module parameters regarding mapped process number*/ 797 if (hws_max_conc_proc >= 0) 798 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 799 else 800 max_proc_per_quantum = vmid_num_kfd; 801 802 /* calculate max size of mqds needed for queues */ 803 size = max_num_of_queues_per_device * 804 kfd->device_info.mqd_size_aligned; 805 806 /* 807 * calculate max size of runlist packet. 808 * There can be only 2 packets at once 809 */ 810 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 811 sizeof(struct pm4_mes_map_process_aldebaran) : 812 sizeof(struct pm4_mes_map_process); 813 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 814 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 815 + sizeof(struct pm4_mes_runlist)) * 2; 816 817 /* Add size of HIQ & DIQ */ 818 size += KFD_KERNEL_QUEUE_SIZE * 2; 819 820 /* add another 512KB for all other allocations on gart (HPD, fences) */ 821 size += 512 * 1024; 822 823 if (amdgpu_amdkfd_alloc_kernel_mem( 824 kfd->adev, size, AMDGPU_GEM_DOMAIN_GTT, 825 &kfd->gtt_mem, 826 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 827 false)) { 828 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 829 goto alloc_kernel_mem_failure; 830 } 831 832 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 833 834 /* Initialize GTT sa with 512 byte chunk size */ 835 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 836 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 837 goto kfd_gtt_sa_init_error; 838 } 839 840 if (kfd_doorbell_init(kfd)) { 841 dev_err(kfd_device, 842 "Error initializing doorbell aperture\n"); 843 goto kfd_doorbell_error; 844 } 845 846 if (amdgpu_use_xgmi_p2p) 847 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 848 849 /* 850 * For multi-partition capable GPUs, the KFD abstracts all partitions 851 * within a socket as xGMI connected in the topology so assign a unique 852 * hive id per device based on the pci device location if device is in 853 * PCIe mode. 854 */ 855 if (!kfd->hive_id && kfd->num_nodes > 1) 856 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 857 858 kfd->noretry = kfd->adev->gmc.noretry; 859 860 kfd_cwsr_init(kfd); 861 862 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 863 kfd->num_nodes); 864 865 /* Allocate the KFD nodes */ 866 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 867 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL); 868 if (!node) 869 goto node_alloc_error; 870 871 node->node_id = i; 872 node->adev = kfd->adev; 873 node->kfd = kfd; 874 node->kfd2kgd = kfd->kfd2kgd; 875 node->vm_info.vmid_num_kfd = vmid_num_kfd; 876 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 877 /* TODO : Check if error handling is needed */ 878 if (node->xcp) { 879 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 880 &node->xcc_mask); 881 ++xcp_idx; 882 } else { 883 node->xcc_mask = 884 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 885 } 886 887 if (node->xcp) { 888 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 889 node->node_id, node->xcp->mem_id, 890 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 891 } 892 893 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 894 kfd->num_nodes != 1 && 895 (KFD_GC_VERSION(kfd) != IP_VERSION(12, 1, 0))) { 896 /* For multi-partition capable GPUs and CPX mode, first 897 * XCD gets VMID range 4-9 and second XCD gets VMID 898 * range 10-15. 899 */ 900 901 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 902 first_vmid_kfd : 903 first_vmid_kfd+vmid_num_kfd; 904 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 905 last_vmid_kfd-vmid_num_kfd : 906 last_vmid_kfd; 907 node->compute_vmid_bitmap = 908 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 909 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 910 } else { 911 node->vm_info.first_vmid_kfd = first_vmid_kfd; 912 node->vm_info.last_vmid_kfd = last_vmid_kfd; 913 node->compute_vmid_bitmap = 914 gpu_resources->compute_vmid_bitmap; 915 } 916 917 node->max_proc_per_quantum = max_proc_per_quantum; 918 atomic_set(&node->sram_ecc_flag, 0); 919 920 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 921 &node->local_mem_info, node->xcp); 922 923 if (kfd->adev->xcp_mgr) 924 kfd_setup_interrupt_bitmap(node, i); 925 926 /* Initialize the KFD node */ 927 if (kfd_init_node(node)) { 928 dev_err(kfd_device, "Error initializing KFD node\n"); 929 goto node_init_error; 930 } 931 932 spin_lock_init(&node->watch_points_lock); 933 934 kfd->nodes[i] = node; 935 } 936 937 svm_range_set_max_pages(kfd->adev); 938 939 kfd->init_complete = true; 940 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 941 kfd->adev->pdev->device); 942 943 pr_debug("Starting kfd with the following scheduling policy %d\n", 944 node->dqm->sched_policy); 945 946 goto out; 947 948 node_init_error: 949 node_alloc_error: 950 kfd_cleanup_nodes(kfd, i); 951 kfd_doorbell_fini(kfd); 952 kfd_doorbell_error: 953 kfd_gtt_sa_fini(kfd); 954 kfd_gtt_sa_init_error: 955 amdgpu_amdkfd_free_kernel_mem(kfd->adev, &kfd->gtt_mem); 956 alloc_kernel_mem_failure: 957 dev_err(kfd_device, 958 "device %x:%x NOT added due to errors\n", 959 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 960 out: 961 return kfd->init_complete; 962 } 963 964 void kgd2kfd_device_exit(struct kfd_dev *kfd) 965 { 966 if (kfd->init_complete) { 967 /* Cleanup KFD nodes */ 968 kfd_cleanup_nodes(kfd, kfd->num_nodes); 969 /* Cleanup common/shared resources */ 970 kfd_doorbell_fini(kfd); 971 ida_destroy(&kfd->doorbell_ida); 972 kfd_gtt_sa_fini(kfd); 973 amdgpu_amdkfd_free_kernel_mem(kfd->adev, &kfd->gtt_mem); 974 } 975 976 kfree(kfd); 977 978 /* after remove a kfd device unlock kfd driver */ 979 kgd2kfd_unlock_kfd(NULL); 980 } 981 982 int kgd2kfd_pre_reset(struct kfd_dev *kfd, 983 struct amdgpu_reset_context *reset_context) 984 { 985 struct kfd_node *node; 986 int i; 987 988 if (!kfd->init_complete) 989 return 0; 990 991 for (i = 0; i < kfd->num_nodes; i++) { 992 node = kfd->nodes[i]; 993 kfd_smi_event_update_gpu_reset(node, false, reset_context); 994 } 995 996 kgd2kfd_suspend(kfd, true); 997 998 for (i = 0; i < kfd->num_nodes; i++) 999 kfd_signal_reset_event(kfd->nodes[i]); 1000 1001 return 0; 1002 } 1003 1004 /* 1005 * Fix me. KFD won't be able to resume existing process for now. 1006 * We will keep all existing process in a evicted state and 1007 * wait the process to be terminated. 1008 */ 1009 1010 int kgd2kfd_post_reset(struct kfd_dev *kfd) 1011 { 1012 int ret; 1013 struct kfd_node *node; 1014 int i; 1015 1016 if (!kfd->init_complete) 1017 return 0; 1018 1019 for (i = 0; i < kfd->num_nodes; i++) { 1020 ret = kfd_resume(kfd->nodes[i]); 1021 if (ret) 1022 return ret; 1023 } 1024 1025 mutex_lock(&kfd_processes_mutex); 1026 --kfd_locked; 1027 mutex_unlock(&kfd_processes_mutex); 1028 1029 for (i = 0; i < kfd->num_nodes; i++) { 1030 node = kfd->nodes[i]; 1031 atomic_set(&node->sram_ecc_flag, 0); 1032 kfd_smi_event_update_gpu_reset(node, true, NULL); 1033 } 1034 1035 return 0; 1036 } 1037 1038 bool kfd_is_locked(struct kfd_dev *kfd) 1039 { 1040 uint8_t id = 0; 1041 struct kfd_node *dev; 1042 1043 lockdep_assert_held(&kfd_processes_mutex); 1044 1045 /* check reset/suspend lock */ 1046 if (kfd_locked > 0) 1047 return true; 1048 1049 if (kfd) 1050 return kfd->kfd_dev_lock > 0; 1051 1052 /* check lock on all cgroup accessible devices */ 1053 while (kfd_topology_enum_kfd_devices(id++, &dev) == 0) { 1054 if (!dev || kfd_devcgroup_check_permission(dev)) 1055 continue; 1056 1057 if (dev->kfd->kfd_dev_lock > 0) 1058 return true; 1059 } 1060 1061 return false; 1062 } 1063 1064 void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) 1065 { 1066 struct kfd_node *node; 1067 int i; 1068 1069 if (!kfd->init_complete) 1070 return; 1071 1072 if (suspend_proc) 1073 kgd2kfd_suspend_process(kfd); 1074 1075 for (i = 0; i < kfd->num_nodes; i++) { 1076 node = kfd->nodes[i]; 1077 node->dqm->ops.stop(node->dqm); 1078 } 1079 } 1080 1081 int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc) 1082 { 1083 int ret = 0, i; 1084 1085 if (!kfd->init_complete) 1086 return 0; 1087 1088 for (i = 0; i < kfd->num_nodes; i++) { 1089 ret = kfd_resume(kfd->nodes[i]); 1090 if (ret) 1091 return ret; 1092 } 1093 1094 if (resume_proc) 1095 ret = kgd2kfd_resume_process(kfd); 1096 1097 return ret; 1098 } 1099 1100 void kgd2kfd_suspend_process(struct kfd_dev *kfd) 1101 { 1102 if (!kfd->init_complete) 1103 return; 1104 1105 mutex_lock(&kfd_processes_mutex); 1106 /* For first KFD device suspend all the KFD processes */ 1107 if (++kfd_locked == 1) 1108 kfd_suspend_all_processes(); 1109 mutex_unlock(&kfd_processes_mutex); 1110 } 1111 1112 int kgd2kfd_resume_process(struct kfd_dev *kfd) 1113 { 1114 int ret = 0; 1115 1116 if (!kfd->init_complete) 1117 return 0; 1118 1119 mutex_lock(&kfd_processes_mutex); 1120 if (--kfd_locked == 0) 1121 ret = kfd_resume_all_processes(); 1122 WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error"); 1123 mutex_unlock(&kfd_processes_mutex); 1124 1125 return ret; 1126 } 1127 1128 static int kfd_resume(struct kfd_node *node) 1129 { 1130 int err = 0; 1131 1132 err = node->dqm->ops.start(node->dqm); 1133 if (err) 1134 dev_err(kfd_device, 1135 "Error starting queue manager for device %x:%x\n", 1136 node->adev->pdev->vendor, node->adev->pdev->device); 1137 1138 return err; 1139 } 1140 1141 /* This is called directly from KGD at ISR. */ 1142 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1143 { 1144 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1145 bool is_patched = false; 1146 unsigned long flags; 1147 struct kfd_node *node; 1148 1149 if (!kfd->init_complete) 1150 return; 1151 1152 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1153 dev_err_once(kfd_device, "Ring entry too small\n"); 1154 return; 1155 } 1156 1157 for (i = 0; i < kfd->num_nodes; i++) { 1158 /* Race if another thread in b/w 1159 * kfd_cleanup_nodes and kfree(kfd), 1160 * when kfd->nodes[i] = NULL 1161 */ 1162 if (kfd->nodes[i]) 1163 node = kfd->nodes[i]; 1164 else 1165 return; 1166 1167 spin_lock_irqsave(&node->interrupt_lock, flags); 1168 1169 if (node->interrupts_active 1170 && interrupt_is_wanted(node, ih_ring_entry, 1171 patched_ihre, &is_patched) 1172 && enqueue_ih_ring_entry(node, 1173 is_patched ? patched_ihre : ih_ring_entry)) { 1174 queue_work(node->kfd->ih_wq, &node->interrupt_work); 1175 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1176 return; 1177 } 1178 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1179 } 1180 1181 } 1182 1183 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1184 { 1185 struct kfd_process *p; 1186 int r; 1187 1188 /* Because we are called from arbitrary context (workqueue) as opposed 1189 * to process context, kfd_process could attempt to exit while we are 1190 * running so the lookup function increments the process ref count. 1191 */ 1192 p = kfd_lookup_process_by_mm(mm); 1193 if (!p) 1194 return -ESRCH; 1195 1196 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1197 r = kfd_process_evict_queues(p, trigger); 1198 1199 kfd_unref_process(p); 1200 return r; 1201 } 1202 1203 int kgd2kfd_resume_mm(struct mm_struct *mm) 1204 { 1205 struct kfd_process *p; 1206 int r; 1207 1208 /* Because we are called from arbitrary context (workqueue) as opposed 1209 * to process context, kfd_process could attempt to exit while we are 1210 * running so the lookup function increments the process ref count. 1211 */ 1212 p = kfd_lookup_process_by_mm(mm); 1213 if (!p) 1214 return -ESRCH; 1215 1216 r = kfd_process_restore_queues(p); 1217 1218 kfd_unref_process(p); 1219 return r; 1220 } 1221 1222 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1223 * prepare for safe eviction of KFD BOs that belong to the specified 1224 * process. 1225 * 1226 * @mm: mm_struct that identifies a group of KFD processes 1227 * @context_id: an id that identifies a specific KFD context in the above kfd process group 1228 * @fence: eviction fence attached to KFD process BOs 1229 * 1230 */ 1231 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1232 u16 context_id, struct dma_fence *fence) 1233 { 1234 struct kfd_process *p; 1235 unsigned long active_time; 1236 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1237 1238 if (!fence) 1239 return -EINVAL; 1240 1241 if (dma_fence_is_signaled(fence)) 1242 return 0; 1243 1244 p = kfd_lookup_process_by_id(mm, context_id); 1245 if (!p) 1246 return -ENODEV; 1247 1248 if (fence->seqno == p->last_eviction_seqno) 1249 goto out; 1250 1251 p->last_eviction_seqno = fence->seqno; 1252 1253 /* Avoid KFD process starvation. Wait for at least 1254 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1255 */ 1256 active_time = get_jiffies_64() - p->last_restore_timestamp; 1257 if (delay_jiffies > active_time) 1258 delay_jiffies -= active_time; 1259 else 1260 delay_jiffies = 0; 1261 1262 /* During process initialization eviction_work.dwork is initialized 1263 * to kfd_evict_bo_worker 1264 */ 1265 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1266 p->lead_thread->pid, delay_jiffies); 1267 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1268 out: 1269 kfd_unref_process(p); 1270 return 0; 1271 } 1272 1273 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1274 unsigned int chunk_size) 1275 { 1276 if (WARN_ON(buf_size < chunk_size)) 1277 return -EINVAL; 1278 if (WARN_ON(buf_size == 0)) 1279 return -EINVAL; 1280 if (WARN_ON(chunk_size == 0)) 1281 return -EINVAL; 1282 1283 kfd->gtt_sa_chunk_size = chunk_size; 1284 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1285 1286 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1287 GFP_KERNEL); 1288 if (!kfd->gtt_sa_bitmap) 1289 return -ENOMEM; 1290 1291 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1292 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1293 1294 mutex_init(&kfd->gtt_sa_lock); 1295 1296 return 0; 1297 } 1298 1299 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1300 { 1301 mutex_destroy(&kfd->gtt_sa_lock); 1302 bitmap_free(kfd->gtt_sa_bitmap); 1303 } 1304 1305 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1306 unsigned int bit_num, 1307 unsigned int chunk_size) 1308 { 1309 return start_addr + bit_num * chunk_size; 1310 } 1311 1312 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1313 unsigned int bit_num, 1314 unsigned int chunk_size) 1315 { 1316 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1317 } 1318 1319 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1320 struct kfd_mem_obj **mem_obj) 1321 { 1322 unsigned int found, start_search, cur_size; 1323 struct kfd_dev *kfd = node->kfd; 1324 1325 if (size == 0) 1326 return -EINVAL; 1327 1328 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1329 return -ENOMEM; 1330 1331 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 1332 if (!(*mem_obj)) 1333 return -ENOMEM; 1334 1335 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1336 1337 start_search = 0; 1338 1339 mutex_lock(&kfd->gtt_sa_lock); 1340 1341 kfd_gtt_restart_search: 1342 /* Find the first chunk that is free */ 1343 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1344 kfd->gtt_sa_num_of_chunks, 1345 start_search); 1346 1347 pr_debug("Found = %d\n", found); 1348 1349 /* If there wasn't any free chunk, bail out */ 1350 if (found == kfd->gtt_sa_num_of_chunks) 1351 goto kfd_gtt_no_free_chunk; 1352 1353 /* Update fields of mem_obj */ 1354 (*mem_obj)->range_start = found; 1355 (*mem_obj)->range_end = found; 1356 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1357 kfd->gtt_start_gpu_addr, 1358 found, 1359 kfd->gtt_sa_chunk_size); 1360 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1361 kfd->gtt_start_cpu_ptr, 1362 found, 1363 kfd->gtt_sa_chunk_size); 1364 1365 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1366 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1367 1368 /* If we need only one chunk, mark it as allocated and get out */ 1369 if (size <= kfd->gtt_sa_chunk_size) { 1370 pr_debug("Single bit\n"); 1371 __set_bit(found, kfd->gtt_sa_bitmap); 1372 goto kfd_gtt_out; 1373 } 1374 1375 /* Otherwise, try to see if we have enough contiguous chunks */ 1376 cur_size = size - kfd->gtt_sa_chunk_size; 1377 do { 1378 (*mem_obj)->range_end = 1379 find_next_zero_bit(kfd->gtt_sa_bitmap, 1380 kfd->gtt_sa_num_of_chunks, ++found); 1381 /* 1382 * If next free chunk is not contiguous than we need to 1383 * restart our search from the last free chunk we found (which 1384 * wasn't contiguous to the previous ones 1385 */ 1386 if ((*mem_obj)->range_end != found) { 1387 start_search = found; 1388 goto kfd_gtt_restart_search; 1389 } 1390 1391 /* 1392 * If we reached end of buffer, bail out with error 1393 */ 1394 if (found == kfd->gtt_sa_num_of_chunks) 1395 goto kfd_gtt_no_free_chunk; 1396 1397 /* Check if we don't need another chunk */ 1398 if (cur_size <= kfd->gtt_sa_chunk_size) 1399 cur_size = 0; 1400 else 1401 cur_size -= kfd->gtt_sa_chunk_size; 1402 1403 } while (cur_size > 0); 1404 1405 pr_debug("range_start = %d, range_end = %d\n", 1406 (*mem_obj)->range_start, (*mem_obj)->range_end); 1407 1408 /* Mark the chunks as allocated */ 1409 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1410 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1411 1412 kfd_gtt_out: 1413 mutex_unlock(&kfd->gtt_sa_lock); 1414 return 0; 1415 1416 kfd_gtt_no_free_chunk: 1417 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1418 mutex_unlock(&kfd->gtt_sa_lock); 1419 kfree(*mem_obj); 1420 return -ENOMEM; 1421 } 1422 1423 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1424 { 1425 struct kfd_dev *kfd = node->kfd; 1426 1427 /* Act like kfree when trying to free a NULL object */ 1428 if (!mem_obj) 1429 return 0; 1430 1431 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1432 mem_obj, mem_obj->range_start, mem_obj->range_end); 1433 1434 mutex_lock(&kfd->gtt_sa_lock); 1435 1436 /* Mark the chunks as free */ 1437 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1438 mem_obj->range_end - mem_obj->range_start + 1); 1439 1440 mutex_unlock(&kfd->gtt_sa_lock); 1441 1442 kfree(mem_obj); 1443 return 0; 1444 } 1445 1446 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1447 { 1448 /* 1449 * TODO: Currently update SRAM ECC flag for first node. 1450 * This needs to be updated later when we can 1451 * identify SRAM ECC error on other nodes also. 1452 */ 1453 if (kfd) 1454 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1455 } 1456 1457 void kfd_inc_compute_active(struct kfd_node *node) 1458 { 1459 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1460 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1461 } 1462 1463 void kfd_dec_compute_active(struct kfd_node *node) 1464 { 1465 int count = atomic_dec_return(&node->kfd->compute_profile); 1466 1467 if (count == 0) 1468 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1469 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1470 } 1471 1472 static bool kfd_compute_active(struct kfd_node *node) 1473 { 1474 if (atomic_read(&node->kfd->compute_profile)) 1475 return true; 1476 return false; 1477 } 1478 1479 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1480 { 1481 /* 1482 * TODO: For now, raise the throttling event only on first node. 1483 * This will need to change after we are able to determine 1484 * which node raised the throttling event. 1485 */ 1486 if (kfd && kfd->init_complete) 1487 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1488 throttle_bitmask); 1489 } 1490 1491 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1492 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1493 * When the device has more than two engines, we reserve two for PCIe to enable 1494 * full-duplex and the rest are used as XGMI. 1495 */ 1496 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1497 { 1498 /* If XGMI is not supported, all SDMA engines are PCIe */ 1499 if (!node->adev->gmc.xgmi.supported) 1500 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1501 1502 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1503 } 1504 1505 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1506 { 1507 /* After reserved for PCIe, the rest of engines are XGMI */ 1508 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1509 kfd_get_num_sdma_engines(node); 1510 } 1511 1512 int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd) 1513 { 1514 struct kfd_process *p; 1515 int r = 0, temp, idx; 1516 1517 mutex_lock(&kfd_processes_mutex); 1518 1519 /* kfd_processes_count is per kfd_dev, return -EBUSY without 1520 * further check 1521 */ 1522 if (!!atomic_read(&kfd->kfd_processes_count)) { 1523 pr_debug("process_wq_release not finished\n"); 1524 r = -EBUSY; 1525 goto out; 1526 } 1527 1528 if (hash_empty(kfd_processes_table) && !kfd_is_locked(kfd)) 1529 goto out; 1530 1531 /* fail under system reset/resume or kfd device is partition switching. */ 1532 if (kfd_is_locked(kfd)) { 1533 r = -EBUSY; 1534 goto out; 1535 } 1536 1537 /* 1538 * ensure all running processes are cgroup excluded from device before mode switch. 1539 * i.e. no pdd was created on the process socket. 1540 */ 1541 idx = srcu_read_lock(&kfd_processes_srcu); 1542 hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) { 1543 int i; 1544 1545 for (i = 0; i < p->n_pdds; i++) { 1546 if (p->pdds[i]->dev->kfd != kfd) 1547 continue; 1548 1549 r = -EBUSY; 1550 goto proc_check_unlock; 1551 } 1552 } 1553 1554 proc_check_unlock: 1555 srcu_read_unlock(&kfd_processes_srcu, idx); 1556 out: 1557 if (!r) 1558 ++kfd->kfd_dev_lock; 1559 mutex_unlock(&kfd_processes_mutex); 1560 1561 return r; 1562 } 1563 1564 /* unlock a kfd dev or kfd driver */ 1565 void kgd2kfd_unlock_kfd(struct kfd_dev *kfd) 1566 { 1567 mutex_lock(&kfd_processes_mutex); 1568 if (kfd) 1569 --kfd->kfd_dev_lock; 1570 else 1571 --kfd_locked; 1572 mutex_unlock(&kfd_processes_mutex); 1573 } 1574 1575 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id) 1576 { 1577 struct kfd_node *node; 1578 int ret; 1579 1580 if (!kfd->init_complete) 1581 return 0; 1582 1583 if (node_id >= kfd->num_nodes) { 1584 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1585 node_id, kfd->num_nodes - 1); 1586 return -EINVAL; 1587 } 1588 node = kfd->nodes[node_id]; 1589 1590 ret = node->dqm->ops.unhalt(node->dqm); 1591 if (ret) 1592 dev_err(kfd_device, "Error in starting scheduler\n"); 1593 1594 return ret; 1595 } 1596 1597 int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd) 1598 { 1599 struct kfd_node *node; 1600 int i, r; 1601 1602 if (!kfd->init_complete) 1603 return 0; 1604 1605 for (i = 0; i < kfd->num_nodes; i++) { 1606 node = kfd->nodes[i]; 1607 r = node->dqm->ops.unhalt(node->dqm); 1608 if (r) { 1609 dev_err(kfd_device, "Error in starting scheduler\n"); 1610 return r; 1611 } 1612 } 1613 return 0; 1614 } 1615 1616 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) 1617 { 1618 struct kfd_node *node; 1619 1620 if (!kfd->init_complete) 1621 return 0; 1622 1623 if (node_id >= kfd->num_nodes) { 1624 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1625 node_id, kfd->num_nodes - 1); 1626 return -EINVAL; 1627 } 1628 1629 node = kfd->nodes[node_id]; 1630 return node->dqm->ops.halt(node->dqm); 1631 } 1632 1633 int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd) 1634 { 1635 struct kfd_node *node; 1636 int i, r; 1637 1638 if (!kfd->init_complete) 1639 return 0; 1640 1641 for (i = 0; i < kfd->num_nodes; i++) { 1642 node = kfd->nodes[i]; 1643 r = node->dqm->ops.halt(node->dqm); 1644 if (r) 1645 return r; 1646 } 1647 return 0; 1648 } 1649 1650 bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) 1651 { 1652 struct kfd_node *node; 1653 1654 if (!kfd->init_complete) 1655 return false; 1656 1657 if (node_id >= kfd->num_nodes) { 1658 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1659 node_id, kfd->num_nodes - 1); 1660 return false; 1661 } 1662 1663 node = kfd->nodes[node_id]; 1664 1665 return kfd_compute_active(node); 1666 } 1667 1668 /** 1669 * kgd2kfd_vmfault_fast_path() - KFD vm page fault interrupt handling fast path for gmc v9 1670 * @adev: amdgpu device 1671 * @entry: vm fault interrupt vector 1672 * @retry_fault: if this is retry fault 1673 * 1674 * retry fault - 1675 * with CAM enabled, adev primary ring 1676 * | gmc_v9_0_process_interrupt() 1677 * adev soft_ring 1678 * | gmc_v9_0_process_interrupt() worker failed to recover page fault 1679 * KFD node ih_fifo 1680 * | KFD interrupt_wq worker 1681 * kfd_signal_vm_fault_event 1682 * 1683 * without CAM, adev primary ring1 1684 * | gmc_v9_0_process_interrupt worker failed to recvoer page fault 1685 * KFD node ih_fifo 1686 * | KFD interrupt_wq worker 1687 * kfd_signal_vm_fault_event 1688 * 1689 * no-retry fault - 1690 * adev primary ring 1691 * | gmc_v9_0_process_interrupt() 1692 * KFD node ih_fifo 1693 * | KFD interrupt_wq worker 1694 * kfd_signal_vm_fault_event 1695 * 1696 * fast path - After kfd_signal_vm_fault_event, gmc_v9_0_process_interrupt drop the page fault 1697 * of same process, don't copy interrupt to KFD node ih_fifo. 1698 * With gdb debugger enabled, need convert the retry fault to no-retry fault for 1699 * debugger, cannot use the fast path. 1700 * 1701 * Return: 1702 * true - use the fast path to handle this fault 1703 * false - use normal path to handle it 1704 */ 1705 bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, 1706 bool retry_fault) 1707 { 1708 struct kfd_process *p; 1709 u32 cam_index; 1710 u32 src_data_idx; 1711 1712 src_data_idx = (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) ? 1713 3 : 2; 1714 1715 if (entry->ih == &adev->irq.ih_soft || entry->ih == &adev->irq.ih1) { 1716 p = kfd_lookup_process_by_pasid(entry->pasid, NULL); 1717 if (!p) 1718 return true; 1719 1720 if (p->gpu_page_fault && !p->debug_trap_enabled) { 1721 if (retry_fault && adev->irq.retry_cam_enabled) { 1722 cam_index = entry->src_data[src_data_idx] & 0x3ff; 1723 1724 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 1725 } 1726 1727 kfd_unref_process(p); 1728 return true; 1729 } 1730 1731 /* 1732 * This is the first page fault, set flag and then signal user space 1733 */ 1734 p->gpu_page_fault = true; 1735 kfd_unref_process(p); 1736 } 1737 return false; 1738 } 1739 1740 /* check if there is kfd process still uses adev */ 1741 static bool kgd2kfd_check_device_idle(struct amdgpu_device *adev) 1742 { 1743 struct kfd_process *p; 1744 struct hlist_node *p_temp; 1745 unsigned int temp; 1746 struct kfd_node *dev; 1747 1748 mutex_lock(&kfd_processes_mutex); 1749 1750 if (hash_empty(kfd_processes_table)) { 1751 mutex_unlock(&kfd_processes_mutex); 1752 return true; 1753 } 1754 1755 /* check if there is device still use adev */ 1756 hash_for_each_safe(kfd_processes_table, temp, p_temp, p, kfd_processes) { 1757 for (int i = 0; i < p->n_pdds; i++) { 1758 dev = p->pdds[i]->dev; 1759 if (dev->adev == adev) { 1760 mutex_unlock(&kfd_processes_mutex); 1761 return false; 1762 } 1763 } 1764 } 1765 1766 mutex_unlock(&kfd_processes_mutex); 1767 1768 return true; 1769 } 1770 1771 /** kgd2kfd_teardown_processes - gracefully tear down existing 1772 * kfd processes that use adev 1773 * 1774 * @adev: amdgpu_device where kfd processes run on and will be 1775 * teardown 1776 * 1777 */ 1778 void kgd2kfd_teardown_processes(struct amdgpu_device *adev) 1779 { 1780 struct hlist_node *p_temp; 1781 struct kfd_process *p; 1782 struct kfd_node *dev; 1783 unsigned int temp; 1784 1785 mutex_lock(&kfd_processes_mutex); 1786 1787 if (hash_empty(kfd_processes_table)) { 1788 mutex_unlock(&kfd_processes_mutex); 1789 return; 1790 } 1791 1792 hash_for_each_safe(kfd_processes_table, temp, p_temp, p, kfd_processes) { 1793 for (int i = 0; i < p->n_pdds; i++) { 1794 dev = p->pdds[i]->dev; 1795 if (dev->adev == adev) 1796 kfd_signal_process_terminate_event(p); 1797 } 1798 } 1799 1800 mutex_unlock(&kfd_processes_mutex); 1801 1802 /* wait all kfd processes use adev terminate */ 1803 while (!kgd2kfd_check_device_idle(adev)) 1804 cond_resched(); 1805 } 1806 1807 #if defined(CONFIG_DEBUG_FS) 1808 1809 /* This function will send a package to HIQ to hang the HWS 1810 * which will trigger a GPU reset and bring the HWS back to normal state 1811 */ 1812 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1813 { 1814 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1815 pr_err("HWS is not enabled"); 1816 return -EINVAL; 1817 } 1818 1819 if (dev->kfd->shared_resources.enable_mes) { 1820 dev_err(dev->adev->dev, "Inducing MES hang is not supported\n"); 1821 return -EINVAL; 1822 } 1823 1824 return dqm_debugfs_hang_hws(dev->dqm); 1825 } 1826 1827 #endif 1828