1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/pci.h>
27 #include <linux/errno.h>
28 #include <linux/acpi.h>
29 #include <linux/hash.h>
30 #include <linux/cpufreq.h>
31 #include <linux/log2.h>
32 #include <linux/dmi.h>
33 #include <linux/atomic.h>
34 #include <linux/crc16.h>
35
36 #include "kfd_priv.h"
37 #include "kfd_crat.h"
38 #include "kfd_topology.h"
39 #include "kfd_device_queue_manager.h"
40 #include "kfd_svm.h"
41 #include "kfd_debug.h"
42 #include "amdgpu_amdkfd.h"
43 #include "amdgpu_ras.h"
44 #include "amdgpu.h"
45
46 /* topology_device_list - Master list of all topology devices */
47 static struct list_head topology_device_list;
48 static struct kfd_system_properties sys_props;
49
50 static DECLARE_RWSEM(topology_lock);
51 static uint32_t topology_crat_proximity_domain;
52
kfd_topology_device_by_proximity_domain_no_lock(uint32_t proximity_domain)53 struct kfd_topology_device *kfd_topology_device_by_proximity_domain_no_lock(
54 uint32_t proximity_domain)
55 {
56 struct kfd_topology_device *top_dev;
57 struct kfd_topology_device *device = NULL;
58
59 list_for_each_entry(top_dev, &topology_device_list, list)
60 if (top_dev->proximity_domain == proximity_domain) {
61 device = top_dev;
62 break;
63 }
64
65 return device;
66 }
67
kfd_topology_device_by_proximity_domain(uint32_t proximity_domain)68 struct kfd_topology_device *kfd_topology_device_by_proximity_domain(
69 uint32_t proximity_domain)
70 {
71 struct kfd_topology_device *device = NULL;
72
73 down_read(&topology_lock);
74
75 device = kfd_topology_device_by_proximity_domain_no_lock(
76 proximity_domain);
77 up_read(&topology_lock);
78
79 return device;
80 }
81
kfd_topology_device_by_id(uint32_t gpu_id)82 struct kfd_topology_device *kfd_topology_device_by_id(uint32_t gpu_id)
83 {
84 struct kfd_topology_device *top_dev = NULL;
85 struct kfd_topology_device *ret = NULL;
86
87 down_read(&topology_lock);
88
89 list_for_each_entry(top_dev, &topology_device_list, list)
90 if (top_dev->gpu_id == gpu_id) {
91 ret = top_dev;
92 break;
93 }
94
95 up_read(&topology_lock);
96
97 return ret;
98 }
99
kfd_device_by_id(uint32_t gpu_id)100 struct kfd_node *kfd_device_by_id(uint32_t gpu_id)
101 {
102 struct kfd_topology_device *top_dev;
103
104 top_dev = kfd_topology_device_by_id(gpu_id);
105 if (!top_dev)
106 return NULL;
107
108 return top_dev->gpu;
109 }
110
111 /* Called with write topology_lock acquired */
kfd_release_topology_device(struct kfd_topology_device * dev)112 static void kfd_release_topology_device(struct kfd_topology_device *dev)
113 {
114 struct kfd_mem_properties *mem;
115 struct kfd_cache_properties *cache;
116 struct kfd_iolink_properties *iolink;
117 struct kfd_iolink_properties *p2plink;
118 struct kfd_perf_properties *perf;
119
120 list_del(&dev->list);
121
122 while (dev->mem_props.next != &dev->mem_props) {
123 mem = container_of(dev->mem_props.next,
124 struct kfd_mem_properties, list);
125 list_del(&mem->list);
126 kfree(mem);
127 }
128
129 while (dev->cache_props.next != &dev->cache_props) {
130 cache = container_of(dev->cache_props.next,
131 struct kfd_cache_properties, list);
132 list_del(&cache->list);
133 kfree(cache);
134 }
135
136 while (dev->io_link_props.next != &dev->io_link_props) {
137 iolink = container_of(dev->io_link_props.next,
138 struct kfd_iolink_properties, list);
139 list_del(&iolink->list);
140 kfree(iolink);
141 }
142
143 while (dev->p2p_link_props.next != &dev->p2p_link_props) {
144 p2plink = container_of(dev->p2p_link_props.next,
145 struct kfd_iolink_properties, list);
146 list_del(&p2plink->list);
147 kfree(p2plink);
148 }
149
150 while (dev->perf_props.next != &dev->perf_props) {
151 perf = container_of(dev->perf_props.next,
152 struct kfd_perf_properties, list);
153 list_del(&perf->list);
154 kfree(perf);
155 }
156
157 kfree(dev);
158 }
159
kfd_release_topology_device_list(struct list_head * device_list)160 void kfd_release_topology_device_list(struct list_head *device_list)
161 {
162 struct kfd_topology_device *dev;
163
164 while (!list_empty(device_list)) {
165 dev = list_first_entry(device_list,
166 struct kfd_topology_device, list);
167 kfd_release_topology_device(dev);
168 }
169 }
170
kfd_release_live_view(void)171 static void kfd_release_live_view(void)
172 {
173 kfd_release_topology_device_list(&topology_device_list);
174 memset(&sys_props, 0, sizeof(sys_props));
175 }
176
kfd_create_topology_device(struct list_head * device_list)177 struct kfd_topology_device *kfd_create_topology_device(
178 struct list_head *device_list)
179 {
180 struct kfd_topology_device *dev;
181
182 dev = kfd_alloc_struct(dev);
183 if (!dev) {
184 pr_err("No memory to allocate a topology device");
185 return NULL;
186 }
187
188 INIT_LIST_HEAD(&dev->mem_props);
189 INIT_LIST_HEAD(&dev->cache_props);
190 INIT_LIST_HEAD(&dev->io_link_props);
191 INIT_LIST_HEAD(&dev->p2p_link_props);
192 INIT_LIST_HEAD(&dev->perf_props);
193
194 list_add_tail(&dev->list, device_list);
195
196 return dev;
197 }
198
199
200 #define sysfs_show_gen_prop(buffer, offs, fmt, ...) \
201 (offs += snprintf(buffer+offs, PAGE_SIZE-offs, \
202 fmt, __VA_ARGS__))
203 #define sysfs_show_32bit_prop(buffer, offs, name, value) \
204 sysfs_show_gen_prop(buffer, offs, "%s %u\n", name, value)
205 #define sysfs_show_64bit_prop(buffer, offs, name, value) \
206 sysfs_show_gen_prop(buffer, offs, "%s %llu\n", name, value)
207 #define sysfs_show_32bit_val(buffer, offs, value) \
208 sysfs_show_gen_prop(buffer, offs, "%u\n", value)
209 #define sysfs_show_str_val(buffer, offs, value) \
210 sysfs_show_gen_prop(buffer, offs, "%s\n", value)
211
sysprops_show(struct kobject * kobj,struct attribute * attr,char * buffer)212 static ssize_t sysprops_show(struct kobject *kobj, struct attribute *attr,
213 char *buffer)
214 {
215 int offs = 0;
216
217 /* Making sure that the buffer is an empty string */
218 buffer[0] = 0;
219
220 if (attr == &sys_props.attr_genid) {
221 sysfs_show_32bit_val(buffer, offs,
222 sys_props.generation_count);
223 } else if (attr == &sys_props.attr_props) {
224 sysfs_show_64bit_prop(buffer, offs, "platform_oem",
225 sys_props.platform_oem);
226 sysfs_show_64bit_prop(buffer, offs, "platform_id",
227 sys_props.platform_id);
228 sysfs_show_64bit_prop(buffer, offs, "platform_rev",
229 sys_props.platform_rev);
230 } else {
231 offs = -EINVAL;
232 }
233
234 return offs;
235 }
236
kfd_topology_kobj_release(struct kobject * kobj)237 static void kfd_topology_kobj_release(struct kobject *kobj)
238 {
239 kfree(kobj);
240 }
241
242 static const struct sysfs_ops sysprops_ops = {
243 .show = sysprops_show,
244 };
245
246 static const struct kobj_type sysprops_type = {
247 .release = kfd_topology_kobj_release,
248 .sysfs_ops = &sysprops_ops,
249 };
250
iolink_show(struct kobject * kobj,struct attribute * attr,char * buffer)251 static ssize_t iolink_show(struct kobject *kobj, struct attribute *attr,
252 char *buffer)
253 {
254 int offs = 0;
255 struct kfd_iolink_properties *iolink;
256
257 /* Making sure that the buffer is an empty string */
258 buffer[0] = 0;
259
260 iolink = container_of(attr, struct kfd_iolink_properties, attr);
261 if (iolink->gpu && kfd_devcgroup_check_permission(iolink->gpu))
262 return -EPERM;
263 sysfs_show_32bit_prop(buffer, offs, "type", iolink->iolink_type);
264 sysfs_show_32bit_prop(buffer, offs, "version_major", iolink->ver_maj);
265 sysfs_show_32bit_prop(buffer, offs, "version_minor", iolink->ver_min);
266 sysfs_show_32bit_prop(buffer, offs, "node_from", iolink->node_from);
267 sysfs_show_32bit_prop(buffer, offs, "node_to", iolink->node_to);
268 sysfs_show_32bit_prop(buffer, offs, "weight", iolink->weight);
269 sysfs_show_32bit_prop(buffer, offs, "min_latency", iolink->min_latency);
270 sysfs_show_32bit_prop(buffer, offs, "max_latency", iolink->max_latency);
271 sysfs_show_32bit_prop(buffer, offs, "min_bandwidth",
272 iolink->min_bandwidth);
273 sysfs_show_32bit_prop(buffer, offs, "max_bandwidth",
274 iolink->max_bandwidth);
275 sysfs_show_32bit_prop(buffer, offs, "recommended_transfer_size",
276 iolink->rec_transfer_size);
277 sysfs_show_32bit_prop(buffer, offs, "recommended_sdma_engine_id_mask",
278 iolink->rec_sdma_eng_id_mask);
279 sysfs_show_32bit_prop(buffer, offs, "flags", iolink->flags);
280
281 return offs;
282 }
283
284 static const struct sysfs_ops iolink_ops = {
285 .show = iolink_show,
286 };
287
288 static const struct kobj_type iolink_type = {
289 .release = kfd_topology_kobj_release,
290 .sysfs_ops = &iolink_ops,
291 };
292
mem_show(struct kobject * kobj,struct attribute * attr,char * buffer)293 static ssize_t mem_show(struct kobject *kobj, struct attribute *attr,
294 char *buffer)
295 {
296 int offs = 0;
297 struct kfd_mem_properties *mem;
298
299 /* Making sure that the buffer is an empty string */
300 buffer[0] = 0;
301
302 mem = container_of(attr, struct kfd_mem_properties, attr);
303 if (mem->gpu && kfd_devcgroup_check_permission(mem->gpu))
304 return -EPERM;
305 sysfs_show_32bit_prop(buffer, offs, "heap_type", mem->heap_type);
306 sysfs_show_64bit_prop(buffer, offs, "size_in_bytes",
307 mem->size_in_bytes);
308 sysfs_show_32bit_prop(buffer, offs, "flags", mem->flags);
309 sysfs_show_32bit_prop(buffer, offs, "width", mem->width);
310 sysfs_show_32bit_prop(buffer, offs, "mem_clk_max",
311 mem->mem_clk_max);
312
313 return offs;
314 }
315
316 static const struct sysfs_ops mem_ops = {
317 .show = mem_show,
318 };
319
320 static const struct kobj_type mem_type = {
321 .release = kfd_topology_kobj_release,
322 .sysfs_ops = &mem_ops,
323 };
324
kfd_cache_show(struct kobject * kobj,struct attribute * attr,char * buffer)325 static ssize_t kfd_cache_show(struct kobject *kobj, struct attribute *attr,
326 char *buffer)
327 {
328 int offs = 0;
329 uint32_t i, j;
330 struct kfd_cache_properties *cache;
331
332 /* Making sure that the buffer is an empty string */
333 buffer[0] = 0;
334 cache = container_of(attr, struct kfd_cache_properties, attr);
335 if (cache->gpu && kfd_devcgroup_check_permission(cache->gpu))
336 return -EPERM;
337 sysfs_show_32bit_prop(buffer, offs, "processor_id_low",
338 cache->processor_id_low);
339 sysfs_show_32bit_prop(buffer, offs, "level", cache->cache_level);
340 sysfs_show_32bit_prop(buffer, offs, "size", cache->cache_size);
341 sysfs_show_32bit_prop(buffer, offs, "cache_line_size",
342 cache->cacheline_size);
343 sysfs_show_32bit_prop(buffer, offs, "cache_lines_per_tag",
344 cache->cachelines_per_tag);
345 sysfs_show_32bit_prop(buffer, offs, "association", cache->cache_assoc);
346 sysfs_show_32bit_prop(buffer, offs, "latency", cache->cache_latency);
347 sysfs_show_32bit_prop(buffer, offs, "type", cache->cache_type);
348
349 offs += snprintf(buffer+offs, PAGE_SIZE-offs, "sibling_map ");
350 for (i = 0; i < cache->sibling_map_size; i++)
351 for (j = 0; j < sizeof(cache->sibling_map[0])*8; j++)
352 /* Check each bit */
353 offs += snprintf(buffer+offs, PAGE_SIZE-offs, "%d,",
354 (cache->sibling_map[i] >> j) & 1);
355
356 /* Replace the last "," with end of line */
357 buffer[offs-1] = '\n';
358 return offs;
359 }
360
361 static const struct sysfs_ops cache_ops = {
362 .show = kfd_cache_show,
363 };
364
365 static const struct kobj_type cache_type = {
366 .release = kfd_topology_kobj_release,
367 .sysfs_ops = &cache_ops,
368 };
369
370 /****** Sysfs of Performance Counters ******/
371
372 struct kfd_perf_attr {
373 struct kobj_attribute attr;
374 uint32_t data;
375 };
376
perf_show(struct kobject * kobj,struct kobj_attribute * attrs,char * buf)377 static ssize_t perf_show(struct kobject *kobj, struct kobj_attribute *attrs,
378 char *buf)
379 {
380 int offs = 0;
381 struct kfd_perf_attr *attr;
382
383 buf[0] = 0;
384 attr = container_of(attrs, struct kfd_perf_attr, attr);
385 if (!attr->data) /* invalid data for PMC */
386 return 0;
387 else
388 return sysfs_show_32bit_val(buf, offs, attr->data);
389 }
390
391 #define KFD_PERF_DESC(_name, _data) \
392 { \
393 .attr = __ATTR(_name, 0444, perf_show, NULL), \
394 .data = _data, \
395 }
396
397 static struct kfd_perf_attr perf_attr_iommu[] = {
398 KFD_PERF_DESC(max_concurrent, 0),
399 KFD_PERF_DESC(num_counters, 0),
400 KFD_PERF_DESC(counter_ids, 0),
401 };
402 /****************************************/
403
node_show(struct kobject * kobj,struct attribute * attr,char * buffer)404 static ssize_t node_show(struct kobject *kobj, struct attribute *attr,
405 char *buffer)
406 {
407 int offs = 0;
408 struct kfd_topology_device *dev;
409 uint32_t log_max_watch_addr;
410
411 /* Making sure that the buffer is an empty string */
412 buffer[0] = 0;
413
414 if (strcmp(attr->name, "gpu_id") == 0) {
415 dev = container_of(attr, struct kfd_topology_device,
416 attr_gpuid);
417 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu))
418 return -EPERM;
419 return sysfs_show_32bit_val(buffer, offs, dev->gpu_id);
420 }
421
422 if (strcmp(attr->name, "name") == 0) {
423 dev = container_of(attr, struct kfd_topology_device,
424 attr_name);
425
426 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu))
427 return -EPERM;
428 return sysfs_show_str_val(buffer, offs, dev->node_props.name);
429 }
430
431 dev = container_of(attr, struct kfd_topology_device,
432 attr_props);
433 if (dev->gpu && kfd_devcgroup_check_permission(dev->gpu))
434 return -EPERM;
435 sysfs_show_32bit_prop(buffer, offs, "cpu_cores_count",
436 dev->node_props.cpu_cores_count);
437 sysfs_show_32bit_prop(buffer, offs, "simd_count",
438 dev->gpu ? dev->node_props.simd_count : 0);
439 sysfs_show_32bit_prop(buffer, offs, "mem_banks_count",
440 dev->node_props.mem_banks_count);
441 sysfs_show_32bit_prop(buffer, offs, "caches_count",
442 dev->node_props.caches_count);
443 sysfs_show_32bit_prop(buffer, offs, "io_links_count",
444 dev->node_props.io_links_count);
445 sysfs_show_32bit_prop(buffer, offs, "p2p_links_count",
446 dev->node_props.p2p_links_count);
447 sysfs_show_32bit_prop(buffer, offs, "cpu_core_id_base",
448 dev->node_props.cpu_core_id_base);
449 sysfs_show_32bit_prop(buffer, offs, "simd_id_base",
450 dev->node_props.simd_id_base);
451 sysfs_show_32bit_prop(buffer, offs, "max_waves_per_simd",
452 dev->node_props.max_waves_per_simd);
453 sysfs_show_32bit_prop(buffer, offs, "lds_size_in_kb",
454 dev->node_props.lds_size_in_kb);
455 sysfs_show_32bit_prop(buffer, offs, "gds_size_in_kb",
456 dev->node_props.gds_size_in_kb);
457 sysfs_show_32bit_prop(buffer, offs, "num_gws",
458 dev->node_props.num_gws);
459 sysfs_show_32bit_prop(buffer, offs, "wave_front_size",
460 dev->node_props.wave_front_size);
461 sysfs_show_32bit_prop(buffer, offs, "array_count",
462 dev->gpu ? (dev->node_props.array_count *
463 NUM_XCC(dev->gpu->xcc_mask)) : 0);
464 sysfs_show_32bit_prop(buffer, offs, "simd_arrays_per_engine",
465 dev->node_props.simd_arrays_per_engine);
466 sysfs_show_32bit_prop(buffer, offs, "cu_per_simd_array",
467 dev->node_props.cu_per_simd_array);
468 sysfs_show_32bit_prop(buffer, offs, "simd_per_cu",
469 dev->node_props.simd_per_cu);
470 sysfs_show_32bit_prop(buffer, offs, "max_slots_scratch_cu",
471 dev->node_props.max_slots_scratch_cu);
472 sysfs_show_32bit_prop(buffer, offs, "gfx_target_version",
473 dev->node_props.gfx_target_version);
474 sysfs_show_32bit_prop(buffer, offs, "vendor_id",
475 dev->node_props.vendor_id);
476 sysfs_show_32bit_prop(buffer, offs, "device_id",
477 dev->node_props.device_id);
478 sysfs_show_32bit_prop(buffer, offs, "location_id",
479 dev->node_props.location_id);
480 sysfs_show_32bit_prop(buffer, offs, "domain",
481 dev->node_props.domain);
482 sysfs_show_32bit_prop(buffer, offs, "drm_render_minor",
483 dev->node_props.drm_render_minor);
484 sysfs_show_64bit_prop(buffer, offs, "hive_id",
485 dev->node_props.hive_id);
486 sysfs_show_32bit_prop(buffer, offs, "num_sdma_engines",
487 dev->node_props.num_sdma_engines);
488 sysfs_show_32bit_prop(buffer, offs, "num_sdma_xgmi_engines",
489 dev->node_props.num_sdma_xgmi_engines);
490 sysfs_show_32bit_prop(buffer, offs, "num_sdma_queues_per_engine",
491 dev->node_props.num_sdma_queues_per_engine);
492 sysfs_show_32bit_prop(buffer, offs, "num_cp_queues",
493 dev->node_props.num_cp_queues);
494
495 if (dev->gpu) {
496 log_max_watch_addr =
497 __ilog2_u32(dev->gpu->kfd->device_info.num_of_watch_points);
498
499 if (log_max_watch_addr) {
500 dev->node_props.capability |=
501 HSA_CAP_WATCH_POINTS_SUPPORTED;
502
503 dev->node_props.capability |=
504 ((log_max_watch_addr <<
505 HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT) &
506 HSA_CAP_WATCH_POINTS_TOTALBITS_MASK);
507 }
508
509 if (dev->gpu->adev->asic_type == CHIP_TONGA)
510 dev->node_props.capability |=
511 HSA_CAP_AQL_QUEUE_DOUBLE_MAP;
512
513 if (KFD_GC_VERSION(dev->gpu) < IP_VERSION(10, 0, 0) &&
514 (dev->gpu->adev->sdma.supported_reset & AMDGPU_RESET_TYPE_PER_QUEUE))
515 dev->node_props.capability2 |= HSA_CAP2_PER_SDMA_QUEUE_RESET_SUPPORTED;
516
517 sysfs_show_32bit_prop(buffer, offs, "max_engine_clk_fcompute",
518 dev->node_props.max_engine_clk_fcompute);
519
520 sysfs_show_64bit_prop(buffer, offs, "local_mem_size", 0ULL);
521
522 sysfs_show_32bit_prop(buffer, offs, "fw_version",
523 dev->gpu->kfd->mec_fw_version);
524 sysfs_show_32bit_prop(buffer, offs, "capability",
525 dev->node_props.capability);
526 sysfs_show_32bit_prop(buffer, offs, "capability2",
527 dev->node_props.capability2);
528 sysfs_show_64bit_prop(buffer, offs, "debug_prop",
529 dev->node_props.debug_prop);
530 sysfs_show_32bit_prop(buffer, offs, "sdma_fw_version",
531 dev->gpu->kfd->sdma_fw_version);
532 sysfs_show_64bit_prop(buffer, offs, "unique_id",
533 dev->gpu->xcp &&
534 (dev->gpu->xcp->xcp_mgr->mode !=
535 AMDGPU_SPX_PARTITION_MODE) ?
536 dev->gpu->xcp->unique_id :
537 dev->gpu->adev->unique_id);
538 sysfs_show_32bit_prop(buffer, offs, "num_xcc",
539 NUM_XCC(dev->gpu->xcc_mask));
540 }
541
542 return sysfs_show_32bit_prop(buffer, offs, "max_engine_clk_ccompute",
543 cpufreq_quick_get_max(0)/1000);
544 }
545
546 static const struct sysfs_ops node_ops = {
547 .show = node_show,
548 };
549
550 static const struct kobj_type node_type = {
551 .release = kfd_topology_kobj_release,
552 .sysfs_ops = &node_ops,
553 };
554
kfd_remove_sysfs_file(struct kobject * kobj,struct attribute * attr)555 static void kfd_remove_sysfs_file(struct kobject *kobj, struct attribute *attr)
556 {
557 sysfs_remove_file(kobj, attr);
558 kobject_del(kobj);
559 kobject_put(kobj);
560 }
561
kfd_remove_sysfs_node_entry(struct kfd_topology_device * dev)562 static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev)
563 {
564 struct kfd_iolink_properties *p2plink;
565 struct kfd_iolink_properties *iolink;
566 struct kfd_cache_properties *cache;
567 struct kfd_mem_properties *mem;
568 struct kfd_perf_properties *perf;
569
570 if (dev->kobj_iolink) {
571 list_for_each_entry(iolink, &dev->io_link_props, list)
572 if (iolink->kobj) {
573 kfd_remove_sysfs_file(iolink->kobj,
574 &iolink->attr);
575 iolink->kobj = NULL;
576 }
577 kobject_del(dev->kobj_iolink);
578 kobject_put(dev->kobj_iolink);
579 dev->kobj_iolink = NULL;
580 }
581
582 if (dev->kobj_p2plink) {
583 list_for_each_entry(p2plink, &dev->p2p_link_props, list)
584 if (p2plink->kobj) {
585 kfd_remove_sysfs_file(p2plink->kobj,
586 &p2plink->attr);
587 p2plink->kobj = NULL;
588 }
589 kobject_del(dev->kobj_p2plink);
590 kobject_put(dev->kobj_p2plink);
591 dev->kobj_p2plink = NULL;
592 }
593
594 if (dev->kobj_cache) {
595 list_for_each_entry(cache, &dev->cache_props, list)
596 if (cache->kobj) {
597 kfd_remove_sysfs_file(cache->kobj,
598 &cache->attr);
599 cache->kobj = NULL;
600 }
601 kobject_del(dev->kobj_cache);
602 kobject_put(dev->kobj_cache);
603 dev->kobj_cache = NULL;
604 }
605
606 if (dev->kobj_mem) {
607 list_for_each_entry(mem, &dev->mem_props, list)
608 if (mem->kobj) {
609 kfd_remove_sysfs_file(mem->kobj, &mem->attr);
610 mem->kobj = NULL;
611 }
612 kobject_del(dev->kobj_mem);
613 kobject_put(dev->kobj_mem);
614 dev->kobj_mem = NULL;
615 }
616
617 if (dev->kobj_perf) {
618 list_for_each_entry(perf, &dev->perf_props, list) {
619 kfree(perf->attr_group);
620 perf->attr_group = NULL;
621 }
622 kobject_del(dev->kobj_perf);
623 kobject_put(dev->kobj_perf);
624 dev->kobj_perf = NULL;
625 }
626
627 if (dev->kobj_node) {
628 sysfs_remove_file(dev->kobj_node, &dev->attr_gpuid);
629 sysfs_remove_file(dev->kobj_node, &dev->attr_name);
630 sysfs_remove_file(dev->kobj_node, &dev->attr_props);
631 kobject_del(dev->kobj_node);
632 kobject_put(dev->kobj_node);
633 dev->kobj_node = NULL;
634 }
635 }
636
kfd_build_sysfs_node_entry(struct kfd_topology_device * dev,uint32_t id)637 static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev,
638 uint32_t id)
639 {
640 struct kfd_iolink_properties *p2plink;
641 struct kfd_iolink_properties *iolink;
642 struct kfd_cache_properties *cache;
643 struct kfd_mem_properties *mem;
644 struct kfd_perf_properties *perf;
645 int ret;
646 uint32_t i, num_attrs;
647 struct attribute **attrs;
648
649 if (WARN_ON(dev->kobj_node))
650 return -EEXIST;
651
652 /*
653 * Creating the sysfs folders
654 */
655 dev->kobj_node = kfd_alloc_struct(dev->kobj_node);
656 if (!dev->kobj_node)
657 return -ENOMEM;
658
659 ret = kobject_init_and_add(dev->kobj_node, &node_type,
660 sys_props.kobj_nodes, "%d", id);
661 if (ret < 0) {
662 kobject_put(dev->kobj_node);
663 return ret;
664 }
665
666 dev->kobj_mem = kobject_create_and_add("mem_banks", dev->kobj_node);
667 if (!dev->kobj_mem)
668 return -ENOMEM;
669
670 dev->kobj_cache = kobject_create_and_add("caches", dev->kobj_node);
671 if (!dev->kobj_cache)
672 return -ENOMEM;
673
674 dev->kobj_iolink = kobject_create_and_add("io_links", dev->kobj_node);
675 if (!dev->kobj_iolink)
676 return -ENOMEM;
677
678 dev->kobj_p2plink = kobject_create_and_add("p2p_links", dev->kobj_node);
679 if (!dev->kobj_p2plink)
680 return -ENOMEM;
681
682 dev->kobj_perf = kobject_create_and_add("perf", dev->kobj_node);
683 if (!dev->kobj_perf)
684 return -ENOMEM;
685
686 /*
687 * Creating sysfs files for node properties
688 */
689 dev->attr_gpuid.name = "gpu_id";
690 dev->attr_gpuid.mode = KFD_SYSFS_FILE_MODE;
691 sysfs_attr_init(&dev->attr_gpuid);
692 dev->attr_name.name = "name";
693 dev->attr_name.mode = KFD_SYSFS_FILE_MODE;
694 sysfs_attr_init(&dev->attr_name);
695 dev->attr_props.name = "properties";
696 dev->attr_props.mode = KFD_SYSFS_FILE_MODE;
697 sysfs_attr_init(&dev->attr_props);
698 ret = sysfs_create_file(dev->kobj_node, &dev->attr_gpuid);
699 if (ret < 0)
700 return ret;
701 ret = sysfs_create_file(dev->kobj_node, &dev->attr_name);
702 if (ret < 0)
703 return ret;
704 ret = sysfs_create_file(dev->kobj_node, &dev->attr_props);
705 if (ret < 0)
706 return ret;
707
708 i = 0;
709 list_for_each_entry(mem, &dev->mem_props, list) {
710 mem->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
711 if (!mem->kobj)
712 return -ENOMEM;
713 ret = kobject_init_and_add(mem->kobj, &mem_type,
714 dev->kobj_mem, "%d", i);
715 if (ret < 0) {
716 kobject_put(mem->kobj);
717 return ret;
718 }
719
720 mem->attr.name = "properties";
721 mem->attr.mode = KFD_SYSFS_FILE_MODE;
722 sysfs_attr_init(&mem->attr);
723 ret = sysfs_create_file(mem->kobj, &mem->attr);
724 if (ret < 0)
725 return ret;
726 i++;
727 }
728
729 i = 0;
730 list_for_each_entry(cache, &dev->cache_props, list) {
731 cache->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
732 if (!cache->kobj)
733 return -ENOMEM;
734 ret = kobject_init_and_add(cache->kobj, &cache_type,
735 dev->kobj_cache, "%d", i);
736 if (ret < 0) {
737 kobject_put(cache->kobj);
738 return ret;
739 }
740
741 cache->attr.name = "properties";
742 cache->attr.mode = KFD_SYSFS_FILE_MODE;
743 sysfs_attr_init(&cache->attr);
744 ret = sysfs_create_file(cache->kobj, &cache->attr);
745 if (ret < 0)
746 return ret;
747 i++;
748 }
749
750 i = 0;
751 list_for_each_entry(iolink, &dev->io_link_props, list) {
752 iolink->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
753 if (!iolink->kobj)
754 return -ENOMEM;
755 ret = kobject_init_and_add(iolink->kobj, &iolink_type,
756 dev->kobj_iolink, "%d", i);
757 if (ret < 0) {
758 kobject_put(iolink->kobj);
759 return ret;
760 }
761
762 iolink->attr.name = "properties";
763 iolink->attr.mode = KFD_SYSFS_FILE_MODE;
764 sysfs_attr_init(&iolink->attr);
765 ret = sysfs_create_file(iolink->kobj, &iolink->attr);
766 if (ret < 0)
767 return ret;
768 i++;
769 }
770
771 i = 0;
772 list_for_each_entry(p2plink, &dev->p2p_link_props, list) {
773 p2plink->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
774 if (!p2plink->kobj)
775 return -ENOMEM;
776 ret = kobject_init_and_add(p2plink->kobj, &iolink_type,
777 dev->kobj_p2plink, "%d", i);
778 if (ret < 0) {
779 kobject_put(p2plink->kobj);
780 return ret;
781 }
782
783 p2plink->attr.name = "properties";
784 p2plink->attr.mode = KFD_SYSFS_FILE_MODE;
785 sysfs_attr_init(&p2plink->attr);
786 ret = sysfs_create_file(p2plink->kobj, &p2plink->attr);
787 if (ret < 0)
788 return ret;
789 i++;
790 }
791
792 /* All hardware blocks have the same number of attributes. */
793 num_attrs = ARRAY_SIZE(perf_attr_iommu);
794 list_for_each_entry(perf, &dev->perf_props, list) {
795 perf->attr_group = kzalloc(sizeof(struct kfd_perf_attr)
796 * num_attrs + sizeof(struct attribute_group),
797 GFP_KERNEL);
798 if (!perf->attr_group)
799 return -ENOMEM;
800
801 attrs = (struct attribute **)(perf->attr_group + 1);
802 if (!strcmp(perf->block_name, "iommu")) {
803 /* Information of IOMMU's num_counters and counter_ids is shown
804 * under /sys/bus/event_source/devices/amd_iommu. We don't
805 * duplicate here.
806 */
807 perf_attr_iommu[0].data = perf->max_concurrent;
808 for (i = 0; i < num_attrs; i++)
809 attrs[i] = &perf_attr_iommu[i].attr.attr;
810 }
811 perf->attr_group->name = perf->block_name;
812 perf->attr_group->attrs = attrs;
813 ret = sysfs_create_group(dev->kobj_perf, perf->attr_group);
814 if (ret < 0)
815 return ret;
816 }
817
818 return 0;
819 }
820
821 /* Called with write topology lock acquired */
kfd_build_sysfs_node_tree(void)822 static int kfd_build_sysfs_node_tree(void)
823 {
824 struct kfd_topology_device *dev;
825 int ret;
826 uint32_t i = 0;
827
828 list_for_each_entry(dev, &topology_device_list, list) {
829 ret = kfd_build_sysfs_node_entry(dev, i);
830 if (ret < 0)
831 return ret;
832 i++;
833 }
834
835 return 0;
836 }
837
838 /* Called with write topology lock acquired */
kfd_remove_sysfs_node_tree(void)839 static void kfd_remove_sysfs_node_tree(void)
840 {
841 struct kfd_topology_device *dev;
842
843 list_for_each_entry(dev, &topology_device_list, list)
844 kfd_remove_sysfs_node_entry(dev);
845 }
846
kfd_topology_update_sysfs(void)847 static int kfd_topology_update_sysfs(void)
848 {
849 int ret;
850
851 if (!sys_props.kobj_topology) {
852 sys_props.kobj_topology =
853 kfd_alloc_struct(sys_props.kobj_topology);
854 if (!sys_props.kobj_topology)
855 return -ENOMEM;
856
857 ret = kobject_init_and_add(sys_props.kobj_topology,
858 &sysprops_type, &kfd_device->kobj,
859 "topology");
860 if (ret < 0) {
861 kobject_put(sys_props.kobj_topology);
862 return ret;
863 }
864
865 sys_props.kobj_nodes = kobject_create_and_add("nodes",
866 sys_props.kobj_topology);
867 if (!sys_props.kobj_nodes)
868 return -ENOMEM;
869
870 sys_props.attr_genid.name = "generation_id";
871 sys_props.attr_genid.mode = KFD_SYSFS_FILE_MODE;
872 sysfs_attr_init(&sys_props.attr_genid);
873 ret = sysfs_create_file(sys_props.kobj_topology,
874 &sys_props.attr_genid);
875 if (ret < 0)
876 return ret;
877
878 sys_props.attr_props.name = "system_properties";
879 sys_props.attr_props.mode = KFD_SYSFS_FILE_MODE;
880 sysfs_attr_init(&sys_props.attr_props);
881 ret = sysfs_create_file(sys_props.kobj_topology,
882 &sys_props.attr_props);
883 if (ret < 0)
884 return ret;
885 }
886
887 kfd_remove_sysfs_node_tree();
888
889 return kfd_build_sysfs_node_tree();
890 }
891
kfd_topology_release_sysfs(void)892 static void kfd_topology_release_sysfs(void)
893 {
894 kfd_remove_sysfs_node_tree();
895 if (sys_props.kobj_topology) {
896 sysfs_remove_file(sys_props.kobj_topology,
897 &sys_props.attr_genid);
898 sysfs_remove_file(sys_props.kobj_topology,
899 &sys_props.attr_props);
900 if (sys_props.kobj_nodes) {
901 kobject_del(sys_props.kobj_nodes);
902 kobject_put(sys_props.kobj_nodes);
903 sys_props.kobj_nodes = NULL;
904 }
905 kobject_del(sys_props.kobj_topology);
906 kobject_put(sys_props.kobj_topology);
907 sys_props.kobj_topology = NULL;
908 }
909 }
910
911 /* Called with write topology_lock acquired */
kfd_topology_update_device_list(struct list_head * temp_list,struct list_head * master_list)912 static void kfd_topology_update_device_list(struct list_head *temp_list,
913 struct list_head *master_list)
914 {
915 while (!list_empty(temp_list)) {
916 list_move_tail(temp_list->next, master_list);
917 sys_props.num_devices++;
918 }
919 }
920
kfd_debug_print_topology(void)921 static void kfd_debug_print_topology(void)
922 {
923 struct kfd_topology_device *dev;
924
925 down_read(&topology_lock);
926
927 dev = list_last_entry(&topology_device_list,
928 struct kfd_topology_device, list);
929 if (dev) {
930 if (dev->node_props.cpu_cores_count &&
931 dev->node_props.simd_count) {
932 pr_info("Topology: Add APU node [0x%0x:0x%0x]\n",
933 dev->node_props.device_id,
934 dev->node_props.vendor_id);
935 } else if (dev->node_props.cpu_cores_count)
936 pr_info("Topology: Add CPU node\n");
937 else if (dev->node_props.simd_count)
938 pr_info("Topology: Add dGPU node [0x%0x:0x%0x]\n",
939 dev->node_props.device_id,
940 dev->node_props.vendor_id);
941 }
942 up_read(&topology_lock);
943 }
944
945 /* Helper function for intializing platform_xx members of
946 * kfd_system_properties. Uses OEM info from the last CPU/APU node.
947 */
kfd_update_system_properties(void)948 static void kfd_update_system_properties(void)
949 {
950 struct kfd_topology_device *dev;
951
952 down_read(&topology_lock);
953 dev = list_last_entry(&topology_device_list,
954 struct kfd_topology_device, list);
955 if (dev) {
956 sys_props.platform_id = dev->oem_id64;
957 sys_props.platform_oem = *((uint64_t *)dev->oem_table_id);
958 sys_props.platform_rev = dev->oem_revision;
959 }
960 up_read(&topology_lock);
961 }
962
find_system_memory(const struct dmi_header * dm,void * private)963 static void find_system_memory(const struct dmi_header *dm, void *private)
964 {
965 struct dmi_mem_device *memdev = container_of(dm, struct dmi_mem_device, header);
966 struct kfd_mem_properties *mem;
967 struct kfd_topology_device *kdev =
968 (struct kfd_topology_device *)private;
969
970 if (memdev->header.type != DMI_ENTRY_MEM_DEVICE)
971 return;
972 if (memdev->header.length < sizeof(struct dmi_mem_device))
973 return;
974
975 list_for_each_entry(mem, &kdev->mem_props, list) {
976 if (memdev->total_width != 0xFFFF && memdev->total_width != 0)
977 mem->width = memdev->total_width;
978 if (memdev->speed != 0)
979 mem->mem_clk_max = memdev->speed;
980 }
981 }
982
983 /* kfd_add_non_crat_information - Add information that is not currently
984 * defined in CRAT but is necessary for KFD topology
985 * @dev - topology device to which addition info is added
986 */
kfd_add_non_crat_information(struct kfd_topology_device * kdev)987 static void kfd_add_non_crat_information(struct kfd_topology_device *kdev)
988 {
989 /* Check if CPU only node. */
990 if (!kdev->gpu) {
991 /* Add system memory information */
992 dmi_walk(find_system_memory, kdev);
993 }
994 /* TODO: For GPU node, rearrange code from kfd_topology_add_device */
995 }
996
kfd_topology_init(void)997 int kfd_topology_init(void)
998 {
999 void *crat_image = NULL;
1000 size_t image_size = 0;
1001 int ret;
1002 struct list_head temp_topology_device_list;
1003 int cpu_only_node = 0;
1004 struct kfd_topology_device *kdev;
1005 int proximity_domain;
1006
1007 /* topology_device_list - Master list of all topology devices
1008 * temp_topology_device_list - temporary list created while parsing CRAT
1009 * or VCRAT. Once parsing is complete the contents of list is moved to
1010 * topology_device_list
1011 */
1012
1013 /* Initialize the head for the both the lists */
1014 INIT_LIST_HEAD(&topology_device_list);
1015 INIT_LIST_HEAD(&temp_topology_device_list);
1016 init_rwsem(&topology_lock);
1017
1018 memset(&sys_props, 0, sizeof(sys_props));
1019
1020 /* Proximity domains in ACPI CRAT tables start counting at
1021 * 0. The same should be true for virtual CRAT tables created
1022 * at this stage. GPUs added later in kfd_topology_add_device
1023 * use a counter.
1024 */
1025 proximity_domain = 0;
1026
1027 ret = kfd_create_crat_image_virtual(&crat_image, &image_size,
1028 COMPUTE_UNIT_CPU, NULL,
1029 proximity_domain);
1030 cpu_only_node = 1;
1031 if (ret) {
1032 pr_err("Error creating VCRAT table for CPU\n");
1033 return ret;
1034 }
1035
1036 ret = kfd_parse_crat_table(crat_image,
1037 &temp_topology_device_list,
1038 proximity_domain);
1039 if (ret) {
1040 pr_err("Error parsing VCRAT table for CPU\n");
1041 goto err;
1042 }
1043
1044 kdev = list_first_entry(&temp_topology_device_list,
1045 struct kfd_topology_device, list);
1046
1047 down_write(&topology_lock);
1048 kfd_topology_update_device_list(&temp_topology_device_list,
1049 &topology_device_list);
1050 topology_crat_proximity_domain = sys_props.num_devices-1;
1051 ret = kfd_topology_update_sysfs();
1052 up_write(&topology_lock);
1053
1054 if (!ret) {
1055 sys_props.generation_count++;
1056 kfd_update_system_properties();
1057 kfd_debug_print_topology();
1058 } else
1059 pr_err("Failed to update topology in sysfs ret=%d\n", ret);
1060
1061 /* For nodes with GPU, this information gets added
1062 * when GPU is detected (kfd_topology_add_device).
1063 */
1064 if (cpu_only_node) {
1065 /* Add additional information to CPU only node created above */
1066 down_write(&topology_lock);
1067 kdev = list_first_entry(&topology_device_list,
1068 struct kfd_topology_device, list);
1069 up_write(&topology_lock);
1070 kfd_add_non_crat_information(kdev);
1071 }
1072
1073 err:
1074 kfd_destroy_crat_image(crat_image);
1075 return ret;
1076 }
1077
kfd_topology_shutdown(void)1078 void kfd_topology_shutdown(void)
1079 {
1080 down_write(&topology_lock);
1081 kfd_topology_release_sysfs();
1082 kfd_release_live_view();
1083 up_write(&topology_lock);
1084 }
1085
kfd_generate_gpu_id(struct kfd_node * gpu)1086 static uint32_t kfd_generate_gpu_id(struct kfd_node *gpu)
1087 {
1088 uint32_t gpu_id;
1089 uint32_t buf[8];
1090 uint64_t local_mem_size;
1091 struct kfd_topology_device *dev;
1092 bool is_unique;
1093 uint8_t *crc_buf;
1094
1095 if (!gpu)
1096 return 0;
1097
1098 crc_buf = (uint8_t *)&buf;
1099 local_mem_size = gpu->local_mem_info.local_mem_size_private +
1100 gpu->local_mem_info.local_mem_size_public;
1101 buf[0] = gpu->adev->pdev->devfn;
1102 buf[1] = gpu->adev->pdev->subsystem_vendor |
1103 (gpu->adev->pdev->subsystem_device << 16);
1104 buf[2] = pci_domain_nr(gpu->adev->pdev->bus);
1105 buf[3] = gpu->adev->pdev->device;
1106 buf[4] = gpu->adev->pdev->bus->number;
1107 buf[5] = lower_32_bits(local_mem_size);
1108 buf[6] = upper_32_bits(local_mem_size);
1109 buf[7] = (ffs(gpu->xcc_mask) - 1) | (NUM_XCC(gpu->xcc_mask) << 16);
1110
1111 gpu_id = crc16(0, crc_buf, sizeof(buf)) &
1112 ((1 << KFD_GPU_ID_HASH_WIDTH) - 1);
1113
1114 /* There is a very small possibility when generating a
1115 * 16 (KFD_GPU_ID_HASH_WIDTH) bit value from 8 word buffer
1116 * that the value could be 0 or non-unique. So, check if
1117 * it is unique and non-zero. If not unique increment till
1118 * unique one is found. In case of overflow, restart from 1
1119 */
1120
1121 down_read(&topology_lock);
1122 do {
1123 is_unique = true;
1124 if (!gpu_id)
1125 gpu_id = 1;
1126 list_for_each_entry(dev, &topology_device_list, list) {
1127 if (dev->gpu && dev->gpu_id == gpu_id) {
1128 is_unique = false;
1129 break;
1130 }
1131 }
1132 if (unlikely(!is_unique))
1133 gpu_id = (gpu_id + 1) &
1134 ((1 << KFD_GPU_ID_HASH_WIDTH) - 1);
1135 } while (!is_unique);
1136 up_read(&topology_lock);
1137
1138 return gpu_id;
1139 }
1140 /* kfd_assign_gpu - Attach @gpu to the correct kfd topology device. If
1141 * the GPU device is not already present in the topology device
1142 * list then return NULL. This means a new topology device has to
1143 * be created for this GPU.
1144 */
kfd_assign_gpu(struct kfd_node * gpu)1145 static struct kfd_topology_device *kfd_assign_gpu(struct kfd_node *gpu)
1146 {
1147 struct kfd_topology_device *dev;
1148 struct kfd_topology_device *out_dev = NULL;
1149 struct kfd_mem_properties *mem;
1150 struct kfd_cache_properties *cache;
1151 struct kfd_iolink_properties *iolink;
1152 struct kfd_iolink_properties *p2plink;
1153
1154 list_for_each_entry(dev, &topology_device_list, list) {
1155 /* Discrete GPUs need their own topology device list
1156 * entries. Don't assign them to CPU/APU nodes.
1157 */
1158 if (dev->node_props.cpu_cores_count)
1159 continue;
1160
1161 if (!dev->gpu && (dev->node_props.simd_count > 0)) {
1162 dev->gpu = gpu;
1163 out_dev = dev;
1164
1165 list_for_each_entry(mem, &dev->mem_props, list)
1166 mem->gpu = dev->gpu;
1167 list_for_each_entry(cache, &dev->cache_props, list)
1168 cache->gpu = dev->gpu;
1169 list_for_each_entry(iolink, &dev->io_link_props, list)
1170 iolink->gpu = dev->gpu;
1171 list_for_each_entry(p2plink, &dev->p2p_link_props, list)
1172 p2plink->gpu = dev->gpu;
1173 break;
1174 }
1175 }
1176 return out_dev;
1177 }
1178
kfd_notify_gpu_change(uint32_t gpu_id,int arrival)1179 static void kfd_notify_gpu_change(uint32_t gpu_id, int arrival)
1180 {
1181 /*
1182 * TODO: Generate an event for thunk about the arrival/removal
1183 * of the GPU
1184 */
1185 }
1186
1187 /* kfd_fill_mem_clk_max_info - Since CRAT doesn't have memory clock info,
1188 * patch this after CRAT parsing.
1189 */
kfd_fill_mem_clk_max_info(struct kfd_topology_device * dev)1190 static void kfd_fill_mem_clk_max_info(struct kfd_topology_device *dev)
1191 {
1192 struct kfd_mem_properties *mem;
1193 struct kfd_local_mem_info local_mem_info;
1194
1195 if (!dev)
1196 return;
1197
1198 /* Currently, amdgpu driver (amdgpu_mc) deals only with GPUs with
1199 * single bank of VRAM local memory.
1200 * for dGPUs - VCRAT reports only one bank of Local Memory
1201 * for APUs - If CRAT from ACPI reports more than one bank, then
1202 * all the banks will report the same mem_clk_max information
1203 */
1204 amdgpu_amdkfd_get_local_mem_info(dev->gpu->adev, &local_mem_info,
1205 dev->gpu->xcp);
1206
1207 list_for_each_entry(mem, &dev->mem_props, list)
1208 mem->mem_clk_max = local_mem_info.mem_clk_max;
1209 }
1210
kfd_set_iolink_no_atomics(struct kfd_topology_device * dev,struct kfd_topology_device * target_gpu_dev,struct kfd_iolink_properties * link)1211 static void kfd_set_iolink_no_atomics(struct kfd_topology_device *dev,
1212 struct kfd_topology_device *target_gpu_dev,
1213 struct kfd_iolink_properties *link)
1214 {
1215 /* xgmi always supports atomics between links. */
1216 if (link->iolink_type == CRAT_IOLINK_TYPE_XGMI)
1217 return;
1218
1219 /* check pcie support to set cpu(dev) flags for target_gpu_dev link. */
1220 if (target_gpu_dev) {
1221 uint32_t cap;
1222
1223 pcie_capability_read_dword(target_gpu_dev->gpu->adev->pdev,
1224 PCI_EXP_DEVCAP2, &cap);
1225
1226 if (!(cap & (PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
1227 PCI_EXP_DEVCAP2_ATOMIC_COMP64)))
1228 link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT |
1229 CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT;
1230 /* set gpu (dev) flags. */
1231 } else {
1232 if (!dev->gpu->kfd->pci_atomic_requested ||
1233 dev->gpu->adev->asic_type == CHIP_HAWAII)
1234 link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT |
1235 CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT;
1236 }
1237 }
1238
kfd_set_iolink_non_coherent(struct kfd_topology_device * to_dev,struct kfd_iolink_properties * outbound_link,struct kfd_iolink_properties * inbound_link)1239 static void kfd_set_iolink_non_coherent(struct kfd_topology_device *to_dev,
1240 struct kfd_iolink_properties *outbound_link,
1241 struct kfd_iolink_properties *inbound_link)
1242 {
1243 /* CPU -> GPU with PCIe */
1244 if (!to_dev->gpu &&
1245 inbound_link->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS)
1246 inbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
1247
1248 if (to_dev->gpu) {
1249 /* GPU <-> GPU with PCIe and
1250 * Vega20 with XGMI
1251 */
1252 if (inbound_link->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS ||
1253 (inbound_link->iolink_type == CRAT_IOLINK_TYPE_XGMI &&
1254 KFD_GC_VERSION(to_dev->gpu) == IP_VERSION(9, 4, 0))) {
1255 outbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
1256 inbound_link->flags |= CRAT_IOLINK_FLAGS_NON_COHERENT;
1257 }
1258 }
1259 }
1260
1261 #define REC_SDMA_NUM_GPU 8
1262 static const int rec_sdma_eng_map[REC_SDMA_NUM_GPU][REC_SDMA_NUM_GPU] = {
1263 { -1, 14, 12, 2, 4, 8, 10, 6 },
1264 { 14, -1, 2, 10, 8, 4, 6, 12 },
1265 { 10, 2, -1, 12, 14, 6, 4, 8 },
1266 { 2, 12, 10, -1, 6, 14, 8, 4 },
1267 { 4, 8, 14, 6, -1, 10, 12, 2 },
1268 { 8, 4, 6, 14, 12, -1, 2, 10 },
1269 { 10, 6, 4, 8, 12, 2, -1, 14 },
1270 { 6, 12, 8, 4, 2, 10, 14, -1 }};
1271
kfd_set_recommended_sdma_engines(struct kfd_topology_device * to_dev,struct kfd_iolink_properties * outbound_link,struct kfd_iolink_properties * inbound_link)1272 static void kfd_set_recommended_sdma_engines(struct kfd_topology_device *to_dev,
1273 struct kfd_iolink_properties *outbound_link,
1274 struct kfd_iolink_properties *inbound_link)
1275 {
1276 struct kfd_node *gpu = outbound_link->gpu;
1277 struct amdgpu_device *adev = gpu->adev;
1278 unsigned int num_xgmi_nodes = adev->gmc.xgmi.num_physical_nodes;
1279 unsigned int num_xgmi_sdma_engines = kfd_get_num_xgmi_sdma_engines(gpu);
1280 unsigned int num_sdma_engines = kfd_get_num_sdma_engines(gpu);
1281 uint32_t sdma_eng_id_mask = (1 << num_sdma_engines) - 1;
1282 uint32_t xgmi_sdma_eng_id_mask =
1283 ((1 << num_xgmi_sdma_engines) - 1) << num_sdma_engines;
1284
1285 bool support_rec_eng = !amdgpu_sriov_vf(adev) && to_dev->gpu &&
1286 adev->aid_mask && num_xgmi_nodes && gpu->kfd->num_nodes == 1 &&
1287 num_xgmi_sdma_engines >= 6 && (!(adev->flags & AMD_IS_APU) &&
1288 num_xgmi_nodes == 8);
1289
1290 if (support_rec_eng) {
1291 int src_socket_id = adev->gmc.xgmi.physical_node_id;
1292 int dst_socket_id = to_dev->gpu->adev->gmc.xgmi.physical_node_id;
1293 unsigned int reshift = num_xgmi_sdma_engines == 6 ? 1 : 0;
1294
1295 outbound_link->rec_sdma_eng_id_mask =
1296 1 << (rec_sdma_eng_map[src_socket_id][dst_socket_id] >> reshift);
1297 inbound_link->rec_sdma_eng_id_mask =
1298 1 << (rec_sdma_eng_map[dst_socket_id][src_socket_id] >> reshift);
1299
1300 /* If recommended engine is out of range, need to reset the mask */
1301 if (outbound_link->rec_sdma_eng_id_mask & sdma_eng_id_mask)
1302 outbound_link->rec_sdma_eng_id_mask = xgmi_sdma_eng_id_mask;
1303 if (inbound_link->rec_sdma_eng_id_mask & sdma_eng_id_mask)
1304 inbound_link->rec_sdma_eng_id_mask = xgmi_sdma_eng_id_mask;
1305
1306 } else {
1307 uint32_t engine_mask = (outbound_link->iolink_type == CRAT_IOLINK_TYPE_XGMI &&
1308 num_xgmi_sdma_engines && to_dev->gpu) ? xgmi_sdma_eng_id_mask :
1309 sdma_eng_id_mask;
1310
1311 outbound_link->rec_sdma_eng_id_mask = engine_mask;
1312 inbound_link->rec_sdma_eng_id_mask = engine_mask;
1313 }
1314 }
1315
kfd_fill_iolink_non_crat_info(struct kfd_topology_device * dev)1316 static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev)
1317 {
1318 struct kfd_iolink_properties *link, *inbound_link;
1319 struct kfd_topology_device *peer_dev;
1320
1321 if (!dev || !dev->gpu)
1322 return;
1323
1324 /* GPU only creates direct links so apply flags setting to all */
1325 list_for_each_entry(link, &dev->io_link_props, list) {
1326 link->flags = CRAT_IOLINK_FLAGS_ENABLED;
1327 kfd_set_iolink_no_atomics(dev, NULL, link);
1328 peer_dev = kfd_topology_device_by_proximity_domain(
1329 link->node_to);
1330
1331 if (!peer_dev)
1332 continue;
1333
1334 /* Include the CPU peer in GPU hive if connected over xGMI. */
1335 if (!peer_dev->gpu &&
1336 link->iolink_type == CRAT_IOLINK_TYPE_XGMI) {
1337 /*
1338 * If the GPU is not part of a GPU hive, use its pci
1339 * device location as the hive ID to bind with the CPU.
1340 */
1341 if (!dev->node_props.hive_id)
1342 dev->node_props.hive_id = pci_dev_id(dev->gpu->adev->pdev);
1343 peer_dev->node_props.hive_id = dev->node_props.hive_id;
1344 }
1345
1346 list_for_each_entry(inbound_link, &peer_dev->io_link_props,
1347 list) {
1348 if (inbound_link->node_to != link->node_from)
1349 continue;
1350
1351 inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED;
1352 kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link);
1353 kfd_set_iolink_non_coherent(peer_dev, link, inbound_link);
1354 kfd_set_recommended_sdma_engines(peer_dev, link, inbound_link);
1355 }
1356 }
1357
1358 /* Create indirect links so apply flags setting to all */
1359 list_for_each_entry(link, &dev->p2p_link_props, list) {
1360 link->flags = CRAT_IOLINK_FLAGS_ENABLED;
1361 kfd_set_iolink_no_atomics(dev, NULL, link);
1362 peer_dev = kfd_topology_device_by_proximity_domain(
1363 link->node_to);
1364
1365 if (!peer_dev)
1366 continue;
1367
1368 list_for_each_entry(inbound_link, &peer_dev->p2p_link_props,
1369 list) {
1370 if (inbound_link->node_to != link->node_from)
1371 continue;
1372
1373 inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED;
1374 kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link);
1375 kfd_set_iolink_non_coherent(peer_dev, link, inbound_link);
1376 }
1377 }
1378 }
1379
kfd_build_p2p_node_entry(struct kfd_topology_device * dev,struct kfd_iolink_properties * p2plink)1380 static int kfd_build_p2p_node_entry(struct kfd_topology_device *dev,
1381 struct kfd_iolink_properties *p2plink)
1382 {
1383 int ret;
1384
1385 p2plink->kobj = kzalloc(sizeof(struct kobject), GFP_KERNEL);
1386 if (!p2plink->kobj)
1387 return -ENOMEM;
1388
1389 ret = kobject_init_and_add(p2plink->kobj, &iolink_type,
1390 dev->kobj_p2plink, "%d", dev->node_props.p2p_links_count - 1);
1391 if (ret < 0) {
1392 kobject_put(p2plink->kobj);
1393 return ret;
1394 }
1395
1396 p2plink->attr.name = "properties";
1397 p2plink->attr.mode = KFD_SYSFS_FILE_MODE;
1398 sysfs_attr_init(&p2plink->attr);
1399 ret = sysfs_create_file(p2plink->kobj, &p2plink->attr);
1400 if (ret < 0)
1401 return ret;
1402
1403 return 0;
1404 }
1405
kfd_create_indirect_link_prop(struct kfd_topology_device * kdev,int gpu_node)1406 static int kfd_create_indirect_link_prop(struct kfd_topology_device *kdev, int gpu_node)
1407 {
1408 struct kfd_iolink_properties *gpu_link, *tmp_link, *cpu_link;
1409 struct kfd_iolink_properties *props = NULL, *props2 = NULL;
1410 struct kfd_topology_device *cpu_dev;
1411 int ret = 0;
1412 int i, num_cpu;
1413
1414 num_cpu = 0;
1415 list_for_each_entry(cpu_dev, &topology_device_list, list) {
1416 if (cpu_dev->gpu)
1417 break;
1418 num_cpu++;
1419 }
1420
1421 if (list_empty(&kdev->io_link_props))
1422 return -ENODATA;
1423
1424 gpu_link = list_first_entry(&kdev->io_link_props,
1425 struct kfd_iolink_properties, list);
1426
1427 for (i = 0; i < num_cpu; i++) {
1428 /* CPU <--> GPU */
1429 if (gpu_link->node_to == i)
1430 continue;
1431
1432 /* find CPU <--> CPU links */
1433 cpu_link = NULL;
1434 cpu_dev = kfd_topology_device_by_proximity_domain(i);
1435 if (cpu_dev) {
1436 list_for_each_entry(tmp_link,
1437 &cpu_dev->io_link_props, list) {
1438 if (tmp_link->node_to == gpu_link->node_to) {
1439 cpu_link = tmp_link;
1440 break;
1441 }
1442 }
1443 }
1444
1445 if (!cpu_link)
1446 return -ENOMEM;
1447
1448 /* CPU <--> CPU <--> GPU, GPU node*/
1449 props = kfd_alloc_struct(props);
1450 if (!props)
1451 return -ENOMEM;
1452
1453 memcpy(props, gpu_link, sizeof(struct kfd_iolink_properties));
1454 props->weight = gpu_link->weight + cpu_link->weight;
1455 props->min_latency = gpu_link->min_latency + cpu_link->min_latency;
1456 props->max_latency = gpu_link->max_latency + cpu_link->max_latency;
1457 props->min_bandwidth = min(gpu_link->min_bandwidth, cpu_link->min_bandwidth);
1458 props->max_bandwidth = min(gpu_link->max_bandwidth, cpu_link->max_bandwidth);
1459
1460 props->node_from = gpu_node;
1461 props->node_to = i;
1462 kdev->node_props.p2p_links_count++;
1463 list_add_tail(&props->list, &kdev->p2p_link_props);
1464 ret = kfd_build_p2p_node_entry(kdev, props);
1465 if (ret < 0)
1466 return ret;
1467
1468 /* for small Bar, no CPU --> GPU in-direct links */
1469 if (kfd_dev_is_large_bar(kdev->gpu)) {
1470 /* CPU <--> CPU <--> GPU, CPU node*/
1471 props2 = kfd_alloc_struct(props2);
1472 if (!props2)
1473 return -ENOMEM;
1474
1475 memcpy(props2, props, sizeof(struct kfd_iolink_properties));
1476 props2->node_from = i;
1477 props2->node_to = gpu_node;
1478 props2->kobj = NULL;
1479 cpu_dev->node_props.p2p_links_count++;
1480 list_add_tail(&props2->list, &cpu_dev->p2p_link_props);
1481 ret = kfd_build_p2p_node_entry(cpu_dev, props2);
1482 if (ret < 0)
1483 return ret;
1484 }
1485 }
1486 return ret;
1487 }
1488
1489 #if defined(CONFIG_HSA_AMD_P2P)
kfd_add_peer_prop(struct kfd_topology_device * kdev,struct kfd_topology_device * peer,int from,int to)1490 static int kfd_add_peer_prop(struct kfd_topology_device *kdev,
1491 struct kfd_topology_device *peer, int from, int to)
1492 {
1493 struct kfd_iolink_properties *props = NULL;
1494 struct kfd_iolink_properties *iolink1, *iolink2, *iolink3;
1495 struct kfd_topology_device *cpu_dev;
1496 int ret = 0;
1497
1498 if (!amdgpu_device_is_peer_accessible(
1499 kdev->gpu->adev,
1500 peer->gpu->adev))
1501 return ret;
1502
1503 if (list_empty(&kdev->io_link_props))
1504 return -ENODATA;
1505
1506 iolink1 = list_first_entry(&kdev->io_link_props,
1507 struct kfd_iolink_properties, list);
1508
1509 if (list_empty(&peer->io_link_props))
1510 return -ENODATA;
1511
1512 iolink2 = list_first_entry(&peer->io_link_props,
1513 struct kfd_iolink_properties, list);
1514
1515 props = kfd_alloc_struct(props);
1516 if (!props)
1517 return -ENOMEM;
1518
1519 memcpy(props, iolink1, sizeof(struct kfd_iolink_properties));
1520
1521 props->weight = iolink1->weight + iolink2->weight;
1522 props->min_latency = iolink1->min_latency + iolink2->min_latency;
1523 props->max_latency = iolink1->max_latency + iolink2->max_latency;
1524 props->min_bandwidth = min(iolink1->min_bandwidth, iolink2->min_bandwidth);
1525 props->max_bandwidth = min(iolink2->max_bandwidth, iolink2->max_bandwidth);
1526
1527 if (iolink1->node_to != iolink2->node_to) {
1528 /* CPU->CPU link*/
1529 cpu_dev = kfd_topology_device_by_proximity_domain(iolink1->node_to);
1530 if (cpu_dev) {
1531 list_for_each_entry(iolink3, &cpu_dev->io_link_props, list) {
1532 if (iolink3->node_to != iolink2->node_to)
1533 continue;
1534
1535 props->weight += iolink3->weight;
1536 props->min_latency += iolink3->min_latency;
1537 props->max_latency += iolink3->max_latency;
1538 props->min_bandwidth = min(props->min_bandwidth,
1539 iolink3->min_bandwidth);
1540 props->max_bandwidth = min(props->max_bandwidth,
1541 iolink3->max_bandwidth);
1542 break;
1543 }
1544 } else {
1545 WARN(1, "CPU node not found");
1546 }
1547 }
1548
1549 props->node_from = from;
1550 props->node_to = to;
1551 peer->node_props.p2p_links_count++;
1552 list_add_tail(&props->list, &peer->p2p_link_props);
1553 ret = kfd_build_p2p_node_entry(peer, props);
1554
1555 return ret;
1556 }
1557 #endif
1558
kfd_dev_create_p2p_links(void)1559 static int kfd_dev_create_p2p_links(void)
1560 {
1561 struct kfd_topology_device *dev;
1562 struct kfd_topology_device *new_dev;
1563 #if defined(CONFIG_HSA_AMD_P2P)
1564 uint32_t i;
1565 #endif
1566 uint32_t k;
1567 int ret = 0;
1568
1569 k = 0;
1570 list_for_each_entry(dev, &topology_device_list, list)
1571 k++;
1572 if (k < 2)
1573 return 0;
1574
1575 new_dev = list_last_entry(&topology_device_list, struct kfd_topology_device, list);
1576 if (WARN_ON(!new_dev->gpu))
1577 return 0;
1578
1579 k--;
1580
1581 /* create in-direct links */
1582 ret = kfd_create_indirect_link_prop(new_dev, k);
1583 if (ret < 0)
1584 goto out;
1585
1586 /* create p2p links */
1587 #if defined(CONFIG_HSA_AMD_P2P)
1588 i = 0;
1589 list_for_each_entry(dev, &topology_device_list, list) {
1590 if (dev == new_dev)
1591 break;
1592 if (!dev->gpu || !dev->gpu->adev ||
1593 (dev->gpu->kfd->hive_id &&
1594 dev->gpu->kfd->hive_id == new_dev->gpu->kfd->hive_id &&
1595 amdgpu_xgmi_get_is_sharing_enabled(dev->gpu->adev, new_dev->gpu->adev)))
1596 goto next;
1597
1598 /* check if node(s) is/are peer accessible in one direction or bi-direction */
1599 ret = kfd_add_peer_prop(new_dev, dev, i, k);
1600 if (ret < 0)
1601 goto out;
1602
1603 ret = kfd_add_peer_prop(dev, new_dev, k, i);
1604 if (ret < 0)
1605 goto out;
1606 next:
1607 i++;
1608 }
1609 #endif
1610
1611 out:
1612 return ret;
1613 }
1614
1615 /* Helper function. See kfd_fill_gpu_cache_info for parameter description */
fill_in_l1_pcache(struct kfd_cache_properties ** props_ext,struct kfd_gpu_cache_info * pcache_info,int cu_bitmask,int cache_type,unsigned int cu_processor_id,int cu_block)1616 static int fill_in_l1_pcache(struct kfd_cache_properties **props_ext,
1617 struct kfd_gpu_cache_info *pcache_info,
1618 int cu_bitmask,
1619 int cache_type, unsigned int cu_processor_id,
1620 int cu_block)
1621 {
1622 unsigned int cu_sibling_map_mask;
1623 int first_active_cu;
1624 struct kfd_cache_properties *pcache = NULL;
1625
1626 cu_sibling_map_mask = cu_bitmask;
1627 cu_sibling_map_mask >>= cu_block;
1628 cu_sibling_map_mask &= ((1 << pcache_info[cache_type].num_cu_shared) - 1);
1629 first_active_cu = ffs(cu_sibling_map_mask);
1630
1631 /* CU could be inactive. In case of shared cache find the first active
1632 * CU. and incase of non-shared cache check if the CU is inactive. If
1633 * inactive active skip it
1634 */
1635 if (first_active_cu) {
1636 pcache = kfd_alloc_struct(pcache);
1637 if (!pcache)
1638 return -ENOMEM;
1639
1640 memset(pcache, 0, sizeof(struct kfd_cache_properties));
1641 pcache->processor_id_low = cu_processor_id + (first_active_cu - 1);
1642 pcache->cache_level = pcache_info[cache_type].cache_level;
1643 pcache->cache_size = pcache_info[cache_type].cache_size;
1644 pcache->cacheline_size = pcache_info[cache_type].cache_line_size;
1645
1646 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_DATA_CACHE)
1647 pcache->cache_type |= HSA_CACHE_TYPE_DATA;
1648 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_INST_CACHE)
1649 pcache->cache_type |= HSA_CACHE_TYPE_INSTRUCTION;
1650 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_CPU_CACHE)
1651 pcache->cache_type |= HSA_CACHE_TYPE_CPU;
1652 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_SIMD_CACHE)
1653 pcache->cache_type |= HSA_CACHE_TYPE_HSACU;
1654
1655 /* Sibling map is w.r.t processor_id_low, so shift out
1656 * inactive CU
1657 */
1658 cu_sibling_map_mask =
1659 cu_sibling_map_mask >> (first_active_cu - 1);
1660
1661 pcache->sibling_map[0] = (uint8_t)(cu_sibling_map_mask & 0xFF);
1662 pcache->sibling_map[1] =
1663 (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF);
1664 pcache->sibling_map[2] =
1665 (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF);
1666 pcache->sibling_map[3] =
1667 (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF);
1668
1669 pcache->sibling_map_size = 4;
1670 *props_ext = pcache;
1671
1672 return 0;
1673 }
1674 return 1;
1675 }
1676
1677 /* Helper function. See kfd_fill_gpu_cache_info for parameter description */
fill_in_l2_l3_pcache(struct kfd_cache_properties ** props_ext,struct kfd_gpu_cache_info * pcache_info,struct amdgpu_cu_info * cu_info,struct amdgpu_gfx_config * gfx_info,int cache_type,unsigned int cu_processor_id,struct kfd_node * knode)1678 static int fill_in_l2_l3_pcache(struct kfd_cache_properties **props_ext,
1679 struct kfd_gpu_cache_info *pcache_info,
1680 struct amdgpu_cu_info *cu_info,
1681 struct amdgpu_gfx_config *gfx_info,
1682 int cache_type, unsigned int cu_processor_id,
1683 struct kfd_node *knode)
1684 {
1685 unsigned int cu_sibling_map_mask = 0;
1686 int first_active_cu;
1687 int i, j, k, xcc, start, end;
1688 int num_xcc = NUM_XCC(knode->xcc_mask);
1689 struct kfd_cache_properties *pcache = NULL;
1690 enum amdgpu_memory_partition mode;
1691 struct amdgpu_device *adev = knode->adev;
1692 bool found = false;
1693
1694 start = ffs(knode->xcc_mask) - 1;
1695 end = start + num_xcc;
1696
1697 /* To find the bitmap in the first active cu in the first
1698 * xcc, it is based on the assumption that evrey xcc must
1699 * have at least one active cu.
1700 */
1701 for (i = 0; i < gfx_info->max_shader_engines && !found; i++) {
1702 for (j = 0; j < gfx_info->max_sh_per_se && !found; j++) {
1703 if (cu_info->bitmap[start][i % 4][j % 4]) {
1704 cu_sibling_map_mask =
1705 cu_info->bitmap[start][i % 4][j % 4];
1706 found = true;
1707 }
1708 }
1709 }
1710
1711 cu_sibling_map_mask &=
1712 ((1 << pcache_info[cache_type].num_cu_shared) - 1);
1713 first_active_cu = ffs(cu_sibling_map_mask);
1714
1715 /* CU could be inactive. In case of shared cache find the first active
1716 * CU. and incase of non-shared cache check if the CU is inactive. If
1717 * inactive active skip it
1718 */
1719 if (first_active_cu) {
1720 pcache = kfd_alloc_struct(pcache);
1721 if (!pcache)
1722 return -ENOMEM;
1723
1724 memset(pcache, 0, sizeof(struct kfd_cache_properties));
1725 pcache->processor_id_low = cu_processor_id
1726 + (first_active_cu - 1);
1727 pcache->cache_level = pcache_info[cache_type].cache_level;
1728 pcache->cacheline_size = pcache_info[cache_type].cache_line_size;
1729
1730 if (KFD_GC_VERSION(knode) == IP_VERSION(9, 4, 3) ||
1731 KFD_GC_VERSION(knode) == IP_VERSION(9, 4, 4) ||
1732 KFD_GC_VERSION(knode) == IP_VERSION(9, 5, 0))
1733 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
1734 else
1735 mode = UNKNOWN_MEMORY_PARTITION_MODE;
1736
1737 pcache->cache_size = pcache_info[cache_type].cache_size;
1738 /* Partition mode only affects L3 cache size */
1739 if (mode && pcache->cache_level == 3)
1740 pcache->cache_size /= mode;
1741
1742 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_DATA_CACHE)
1743 pcache->cache_type |= HSA_CACHE_TYPE_DATA;
1744 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_INST_CACHE)
1745 pcache->cache_type |= HSA_CACHE_TYPE_INSTRUCTION;
1746 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_CPU_CACHE)
1747 pcache->cache_type |= HSA_CACHE_TYPE_CPU;
1748 if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_SIMD_CACHE)
1749 pcache->cache_type |= HSA_CACHE_TYPE_HSACU;
1750
1751 /* Sibling map is w.r.t processor_id_low, so shift out
1752 * inactive CU
1753 */
1754 cu_sibling_map_mask = cu_sibling_map_mask >> (first_active_cu - 1);
1755 k = 0;
1756
1757 for (xcc = start; xcc < end; xcc++) {
1758 for (i = 0; i < gfx_info->max_shader_engines; i++) {
1759 for (j = 0; j < gfx_info->max_sh_per_se; j++) {
1760 pcache->sibling_map[k] = (uint8_t)(cu_sibling_map_mask & 0xFF);
1761 pcache->sibling_map[k+1] = (uint8_t)((cu_sibling_map_mask >> 8) & 0xFF);
1762 pcache->sibling_map[k+2] = (uint8_t)((cu_sibling_map_mask >> 16) & 0xFF);
1763 pcache->sibling_map[k+3] = (uint8_t)((cu_sibling_map_mask >> 24) & 0xFF);
1764 k += 4;
1765
1766 cu_sibling_map_mask = cu_info->bitmap[xcc][i % 4][j + i / 4];
1767 cu_sibling_map_mask &= ((1 << pcache_info[cache_type].num_cu_shared) - 1);
1768 }
1769 }
1770 }
1771 pcache->sibling_map_size = k;
1772 *props_ext = pcache;
1773 return 0;
1774 }
1775 return 1;
1776 }
1777
1778 #define KFD_MAX_CACHE_TYPES 6
1779
1780 /* kfd_fill_cache_non_crat_info - Fill GPU cache info using kfd_gpu_cache_info
1781 * tables
1782 */
kfd_fill_cache_non_crat_info(struct kfd_topology_device * dev,struct kfd_node * kdev)1783 static void kfd_fill_cache_non_crat_info(struct kfd_topology_device *dev, struct kfd_node *kdev)
1784 {
1785 struct kfd_gpu_cache_info *pcache_info = NULL;
1786 int i, j, k, xcc, start, end;
1787 int ct = 0;
1788 unsigned int cu_processor_id;
1789 int ret;
1790 unsigned int num_cu_shared;
1791 struct amdgpu_cu_info *cu_info = &kdev->adev->gfx.cu_info;
1792 struct amdgpu_gfx_config *gfx_info = &kdev->adev->gfx.config;
1793 int gpu_processor_id;
1794 struct kfd_cache_properties *props_ext = NULL;
1795 int num_of_entries = 0;
1796 int num_of_cache_types = 0;
1797 struct kfd_gpu_cache_info cache_info[KFD_MAX_CACHE_TYPES];
1798
1799
1800 gpu_processor_id = dev->node_props.simd_id_base;
1801
1802 memset(cache_info, 0, sizeof(cache_info));
1803 pcache_info = cache_info;
1804 num_of_cache_types = kfd_get_gpu_cache_info(kdev, &pcache_info);
1805 if (!num_of_cache_types) {
1806 pr_warn("no cache info found\n");
1807 return;
1808 }
1809
1810 /* For each type of cache listed in the kfd_gpu_cache_info table,
1811 * go through all available Compute Units.
1812 * The [i,j,k] loop will
1813 * if kfd_gpu_cache_info.num_cu_shared = 1
1814 * will parse through all available CU
1815 * If (kfd_gpu_cache_info.num_cu_shared != 1)
1816 * then it will consider only one CU from
1817 * the shared unit
1818 */
1819 start = ffs(kdev->xcc_mask) - 1;
1820 end = start + NUM_XCC(kdev->xcc_mask);
1821
1822 for (ct = 0; ct < num_of_cache_types; ct++) {
1823 cu_processor_id = gpu_processor_id;
1824 if (pcache_info[ct].cache_level == 1) {
1825 for (xcc = start; xcc < end; xcc++) {
1826 for (i = 0; i < gfx_info->max_shader_engines; i++) {
1827 for (j = 0; j < gfx_info->max_sh_per_se; j++) {
1828 for (k = 0; k < gfx_info->max_cu_per_sh; k += pcache_info[ct].num_cu_shared) {
1829
1830 ret = fill_in_l1_pcache(&props_ext, pcache_info,
1831 cu_info->bitmap[xcc][i % 4][j + i / 4], ct,
1832 cu_processor_id, k);
1833
1834 if (ret < 0)
1835 break;
1836
1837 if (!ret) {
1838 num_of_entries++;
1839 list_add_tail(&props_ext->list, &dev->cache_props);
1840 }
1841
1842 /* Move to next CU block */
1843 num_cu_shared = ((k + pcache_info[ct].num_cu_shared) <=
1844 gfx_info->max_cu_per_sh) ?
1845 pcache_info[ct].num_cu_shared :
1846 (gfx_info->max_cu_per_sh - k);
1847 cu_processor_id += num_cu_shared;
1848 }
1849 }
1850 }
1851 }
1852 } else {
1853 ret = fill_in_l2_l3_pcache(&props_ext, pcache_info,
1854 cu_info, gfx_info, ct, cu_processor_id, kdev);
1855
1856 if (ret < 0)
1857 break;
1858
1859 if (!ret) {
1860 num_of_entries++;
1861 list_add_tail(&props_ext->list, &dev->cache_props);
1862 }
1863 }
1864 }
1865 dev->node_props.caches_count += num_of_entries;
1866 pr_debug("Added [%d] GPU cache entries\n", num_of_entries);
1867 }
1868
kfd_topology_add_device_locked(struct kfd_node * gpu,struct kfd_topology_device ** dev)1869 static int kfd_topology_add_device_locked(struct kfd_node *gpu,
1870 struct kfd_topology_device **dev)
1871 {
1872 int proximity_domain = ++topology_crat_proximity_domain;
1873 struct list_head temp_topology_device_list;
1874 void *crat_image = NULL;
1875 size_t image_size = 0;
1876 int res;
1877
1878 res = kfd_create_crat_image_virtual(&crat_image, &image_size,
1879 COMPUTE_UNIT_GPU, gpu,
1880 proximity_domain);
1881 if (res) {
1882 dev_err(gpu->adev->dev, "Error creating VCRAT\n");
1883 topology_crat_proximity_domain--;
1884 goto err;
1885 }
1886
1887 INIT_LIST_HEAD(&temp_topology_device_list);
1888
1889 res = kfd_parse_crat_table(crat_image,
1890 &temp_topology_device_list,
1891 proximity_domain);
1892 if (res) {
1893 dev_err(gpu->adev->dev, "Error parsing VCRAT\n");
1894 topology_crat_proximity_domain--;
1895 goto err;
1896 }
1897
1898 kfd_topology_update_device_list(&temp_topology_device_list,
1899 &topology_device_list);
1900
1901 *dev = kfd_assign_gpu(gpu);
1902 if (WARN_ON(!*dev)) {
1903 res = -ENODEV;
1904 goto err;
1905 }
1906
1907 /* Fill the cache affinity information here for the GPUs
1908 * using VCRAT
1909 */
1910 kfd_fill_cache_non_crat_info(*dev, gpu);
1911
1912 /* Update the SYSFS tree, since we added another topology
1913 * device
1914 */
1915 res = kfd_topology_update_sysfs();
1916 if (!res)
1917 sys_props.generation_count++;
1918 else
1919 dev_err(gpu->adev->dev, "Failed to update GPU to sysfs topology. res=%d\n",
1920 res);
1921
1922 err:
1923 kfd_destroy_crat_image(crat_image);
1924 return res;
1925 }
1926
kfd_topology_set_dbg_firmware_support(struct kfd_topology_device * dev)1927 static void kfd_topology_set_dbg_firmware_support(struct kfd_topology_device *dev)
1928 {
1929 bool firmware_supported = true;
1930
1931 if (KFD_GC_VERSION(dev->gpu) >= IP_VERSION(11, 0, 0) &&
1932 KFD_GC_VERSION(dev->gpu) < IP_VERSION(12, 0, 0)) {
1933 uint32_t mes_api_rev = (dev->gpu->adev->mes.sched_version &
1934 AMDGPU_MES_API_VERSION_MASK) >>
1935 AMDGPU_MES_API_VERSION_SHIFT;
1936 uint32_t mes_rev = dev->gpu->adev->mes.sched_version &
1937 AMDGPU_MES_VERSION_MASK;
1938
1939 firmware_supported = (mes_api_rev >= 14) && (mes_rev >= 64);
1940 goto out;
1941 }
1942
1943 /*
1944 * Note: Any unlisted devices here are assumed to support exception handling.
1945 * Add additional checks here as needed.
1946 */
1947 switch (KFD_GC_VERSION(dev->gpu)) {
1948 case IP_VERSION(9, 0, 1):
1949 firmware_supported = dev->gpu->kfd->mec_fw_version >= 459 + 32768;
1950 break;
1951 case IP_VERSION(9, 1, 0):
1952 case IP_VERSION(9, 2, 1):
1953 case IP_VERSION(9, 2, 2):
1954 case IP_VERSION(9, 3, 0):
1955 case IP_VERSION(9, 4, 0):
1956 firmware_supported = dev->gpu->kfd->mec_fw_version >= 459;
1957 break;
1958 case IP_VERSION(9, 4, 1):
1959 firmware_supported = dev->gpu->kfd->mec_fw_version >= 60;
1960 break;
1961 case IP_VERSION(9, 4, 2):
1962 firmware_supported = dev->gpu->kfd->mec_fw_version >= 51;
1963 break;
1964 case IP_VERSION(10, 1, 10):
1965 case IP_VERSION(10, 1, 2):
1966 case IP_VERSION(10, 1, 1):
1967 firmware_supported = dev->gpu->kfd->mec_fw_version >= 144;
1968 break;
1969 case IP_VERSION(10, 3, 0):
1970 case IP_VERSION(10, 3, 2):
1971 case IP_VERSION(10, 3, 1):
1972 case IP_VERSION(10, 3, 4):
1973 case IP_VERSION(10, 3, 5):
1974 firmware_supported = dev->gpu->kfd->mec_fw_version >= 89;
1975 break;
1976 case IP_VERSION(10, 1, 3):
1977 case IP_VERSION(10, 3, 3):
1978 firmware_supported = false;
1979 break;
1980 default:
1981 break;
1982 }
1983
1984 out:
1985 if (firmware_supported)
1986 dev->node_props.capability |= HSA_CAP_TRAP_DEBUG_FIRMWARE_SUPPORTED;
1987 }
1988
kfd_topology_set_capabilities(struct kfd_topology_device * dev)1989 static void kfd_topology_set_capabilities(struct kfd_topology_device *dev)
1990 {
1991 dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_2_0 <<
1992 HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
1993 HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
1994
1995 dev->node_props.capability |= HSA_CAP_TRAP_DEBUG_SUPPORT |
1996 HSA_CAP_TRAP_DEBUG_WAVE_LAUNCH_TRAP_OVERRIDE_SUPPORTED |
1997 HSA_CAP_TRAP_DEBUG_WAVE_LAUNCH_MODE_SUPPORTED;
1998
1999 if (kfd_dbg_has_ttmps_always_setup(dev->gpu))
2000 dev->node_props.debug_prop |= HSA_DBG_DISPATCH_INFO_ALWAYS_VALID;
2001
2002 if (KFD_GC_VERSION(dev->gpu) < IP_VERSION(10, 0, 0)) {
2003 if (KFD_GC_VERSION(dev->gpu) == IP_VERSION(9, 4, 3) ||
2004 KFD_GC_VERSION(dev->gpu) == IP_VERSION(9, 4, 4))
2005 dev->node_props.debug_prop |=
2006 HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX9_4_3 |
2007 HSA_DBG_WATCH_ADDR_MASK_HI_BIT_GFX9_4_3;
2008 else
2009 dev->node_props.debug_prop |=
2010 HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX9 |
2011 HSA_DBG_WATCH_ADDR_MASK_HI_BIT;
2012
2013 if (KFD_GC_VERSION(dev->gpu) >= IP_VERSION(9, 4, 2))
2014 dev->node_props.capability |=
2015 HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED;
2016
2017 if (!amdgpu_sriov_vf(dev->gpu->adev))
2018 dev->node_props.capability |= HSA_CAP_PER_QUEUE_RESET_SUPPORTED;
2019
2020 } else {
2021 dev->node_props.debug_prop |= HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10 |
2022 HSA_DBG_WATCH_ADDR_MASK_HI_BIT;
2023
2024 if (KFD_GC_VERSION(dev->gpu) >= IP_VERSION(12, 0, 0))
2025 dev->node_props.capability |=
2026 HSA_CAP_TRAP_DEBUG_PRECISE_ALU_OPERATIONS_SUPPORTED;
2027 }
2028
2029 kfd_topology_set_dbg_firmware_support(dev);
2030 }
2031
kfd_topology_add_device(struct kfd_node * gpu)2032 int kfd_topology_add_device(struct kfd_node *gpu)
2033 {
2034 uint32_t gpu_id;
2035 struct kfd_topology_device *dev;
2036 int res = 0;
2037 int i;
2038 const char *asic_name = amdgpu_asic_name[gpu->adev->asic_type];
2039 struct amdgpu_gfx_config *gfx_info = &gpu->adev->gfx.config;
2040 struct amdgpu_cu_info *cu_info = &gpu->adev->gfx.cu_info;
2041
2042 if (gpu->xcp && !gpu->xcp->ddev) {
2043 dev_warn(gpu->adev->dev,
2044 "Won't add GPU to topology since it has no drm node assigned.");
2045 return 0;
2046 } else {
2047 dev_dbg(gpu->adev->dev, "Adding new GPU to topology\n");
2048 }
2049
2050 /* Check to see if this gpu device exists in the topology_device_list.
2051 * If so, assign the gpu to that device,
2052 * else create a Virtual CRAT for this gpu device and then parse that
2053 * CRAT to create a new topology device. Once created assign the gpu to
2054 * that topology device
2055 */
2056 down_write(&topology_lock);
2057 dev = kfd_assign_gpu(gpu);
2058 if (!dev)
2059 res = kfd_topology_add_device_locked(gpu, &dev);
2060 up_write(&topology_lock);
2061 if (res)
2062 return res;
2063
2064 gpu_id = kfd_generate_gpu_id(gpu);
2065 dev->gpu_id = gpu_id;
2066 gpu->id = gpu_id;
2067
2068 kfd_dev_create_p2p_links();
2069
2070 /* TODO: Move the following lines to function
2071 * kfd_add_non_crat_information
2072 */
2073
2074 /* Fill-in additional information that is not available in CRAT but
2075 * needed for the topology
2076 */
2077 for (i = 0; i < KFD_TOPOLOGY_PUBLIC_NAME_SIZE-1; i++) {
2078 dev->node_props.name[i] = __tolower(asic_name[i]);
2079 if (asic_name[i] == '\0')
2080 break;
2081 }
2082 dev->node_props.name[i] = '\0';
2083
2084 dev->node_props.simd_arrays_per_engine =
2085 gfx_info->max_sh_per_se;
2086
2087 dev->node_props.gfx_target_version =
2088 gpu->kfd->device_info.gfx_target_version;
2089 dev->node_props.vendor_id = gpu->adev->pdev->vendor;
2090 dev->node_props.device_id = gpu->adev->pdev->device;
2091 dev->node_props.capability |=
2092 ((dev->gpu->adev->rev_id << HSA_CAP_ASIC_REVISION_SHIFT) &
2093 HSA_CAP_ASIC_REVISION_MASK);
2094
2095 dev->node_props.location_id = pci_dev_id(gpu->adev->pdev);
2096 if (gpu->kfd->num_nodes > 1)
2097 dev->node_props.location_id |= dev->gpu->node_id;
2098
2099 dev->node_props.domain = pci_domain_nr(gpu->adev->pdev->bus);
2100 dev->node_props.max_engine_clk_fcompute =
2101 amdgpu_amdkfd_get_max_engine_clock_in_mhz(dev->gpu->adev);
2102 dev->node_props.max_engine_clk_ccompute =
2103 cpufreq_quick_get_max(0) / 1000;
2104
2105 if (gpu->xcp)
2106 dev->node_props.drm_render_minor = gpu->xcp->ddev->render->index;
2107 else
2108 dev->node_props.drm_render_minor =
2109 gpu->kfd->shared_resources.drm_render_minor;
2110
2111 dev->node_props.hive_id = gpu->kfd->hive_id;
2112 dev->node_props.num_sdma_engines = kfd_get_num_sdma_engines(gpu);
2113 dev->node_props.num_sdma_xgmi_engines =
2114 kfd_get_num_xgmi_sdma_engines(gpu);
2115 dev->node_props.num_sdma_queues_per_engine =
2116 gpu->kfd->device_info.num_sdma_queues_per_engine -
2117 gpu->kfd->device_info.num_reserved_sdma_queues_per_engine;
2118 dev->node_props.num_gws = (dev->gpu->gws &&
2119 dev->gpu->dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) ?
2120 dev->gpu->adev->gds.gws_size : 0;
2121 dev->node_props.num_cp_queues = get_cp_queues_num(dev->gpu->dqm);
2122
2123 kfd_fill_mem_clk_max_info(dev);
2124 kfd_fill_iolink_non_crat_info(dev);
2125
2126 switch (dev->gpu->adev->asic_type) {
2127 case CHIP_KAVERI:
2128 case CHIP_HAWAII:
2129 case CHIP_TONGA:
2130 dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_PRE_1_0 <<
2131 HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
2132 HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
2133 break;
2134 case CHIP_CARRIZO:
2135 case CHIP_FIJI:
2136 case CHIP_POLARIS10:
2137 case CHIP_POLARIS11:
2138 case CHIP_POLARIS12:
2139 case CHIP_VEGAM:
2140 pr_debug("Adding doorbell packet type capability\n");
2141 dev->node_props.capability |= ((HSA_CAP_DOORBELL_TYPE_1_0 <<
2142 HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT) &
2143 HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK);
2144 break;
2145 default:
2146 if (KFD_GC_VERSION(dev->gpu) < IP_VERSION(9, 0, 1))
2147 WARN(1, "Unexpected ASIC family %u",
2148 dev->gpu->adev->asic_type);
2149 else
2150 kfd_topology_set_capabilities(dev);
2151 }
2152
2153 /*
2154 * Overwrite ATS capability according to needs_iommu_device to fix
2155 * potential missing corresponding bit in CRAT of BIOS.
2156 */
2157 dev->node_props.capability &= ~HSA_CAP_ATS_PRESENT;
2158
2159 /* Fix errors in CZ CRAT.
2160 * simd_count: Carrizo CRAT reports wrong simd_count, probably
2161 * because it doesn't consider masked out CUs
2162 * max_waves_per_simd: Carrizo reports wrong max_waves_per_simd
2163 */
2164 if (dev->gpu->adev->asic_type == CHIP_CARRIZO) {
2165 dev->node_props.simd_count =
2166 cu_info->simd_per_cu * cu_info->number;
2167 dev->node_props.max_waves_per_simd = 10;
2168 }
2169
2170 /* kfd only concerns sram ecc on GFX and HBM ecc on UMC */
2171 dev->node_props.capability |=
2172 ((dev->gpu->adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__GFX)) != 0) ?
2173 HSA_CAP_SRAM_EDCSUPPORTED : 0;
2174 dev->node_props.capability |=
2175 ((dev->gpu->adev->ras_enabled & BIT(AMDGPU_RAS_BLOCK__UMC)) != 0) ?
2176 HSA_CAP_MEM_EDCSUPPORTED : 0;
2177
2178 if (KFD_GC_VERSION(dev->gpu) != IP_VERSION(9, 0, 1))
2179 dev->node_props.capability |= (dev->gpu->adev->ras_enabled != 0) ?
2180 HSA_CAP_RASEVENTNOTIFY : 0;
2181
2182 if (KFD_IS_SVM_API_SUPPORTED(dev->gpu->adev))
2183 dev->node_props.capability |= HSA_CAP_SVMAPI_SUPPORTED;
2184
2185 if (dev->gpu->adev->gmc.is_app_apu ||
2186 dev->gpu->adev->gmc.xgmi.connected_to_cpu)
2187 dev->node_props.capability |= HSA_CAP_FLAGS_COHERENTHOSTACCESS;
2188
2189 kfd_queue_ctx_save_restore_size(dev);
2190
2191 kfd_debug_print_topology();
2192
2193 kfd_notify_gpu_change(gpu_id, 1);
2194
2195 return 0;
2196 }
2197
2198 /**
2199 * kfd_topology_update_io_links() - Update IO links after device removal.
2200 * @proximity_domain: Proximity domain value of the dev being removed.
2201 *
2202 * The topology list currently is arranged in increasing order of
2203 * proximity domain.
2204 *
2205 * Two things need to be done when a device is removed:
2206 * 1. All the IO links to this device need to be removed.
2207 * 2. All nodes after the current device node need to move
2208 * up once this device node is removed from the topology
2209 * list. As a result, the proximity domain values for
2210 * all nodes after the node being deleted reduce by 1.
2211 * This would also cause the proximity domain values for
2212 * io links to be updated based on new proximity domain
2213 * values.
2214 *
2215 * Context: The caller must hold write topology_lock.
2216 */
kfd_topology_update_io_links(int proximity_domain)2217 static void kfd_topology_update_io_links(int proximity_domain)
2218 {
2219 struct kfd_topology_device *dev;
2220 struct kfd_iolink_properties *iolink, *p2plink, *tmp;
2221
2222 list_for_each_entry(dev, &topology_device_list, list) {
2223 if (dev->proximity_domain > proximity_domain)
2224 dev->proximity_domain--;
2225
2226 list_for_each_entry_safe(iolink, tmp, &dev->io_link_props, list) {
2227 /*
2228 * If there is an io link to the dev being deleted
2229 * then remove that IO link also.
2230 */
2231 if (iolink->node_to == proximity_domain) {
2232 list_del(&iolink->list);
2233 dev->node_props.io_links_count--;
2234 } else {
2235 if (iolink->node_from > proximity_domain)
2236 iolink->node_from--;
2237 if (iolink->node_to > proximity_domain)
2238 iolink->node_to--;
2239 }
2240 }
2241
2242 list_for_each_entry_safe(p2plink, tmp, &dev->p2p_link_props, list) {
2243 /*
2244 * If there is a p2p link to the dev being deleted
2245 * then remove that p2p link also.
2246 */
2247 if (p2plink->node_to == proximity_domain) {
2248 list_del(&p2plink->list);
2249 dev->node_props.p2p_links_count--;
2250 } else {
2251 if (p2plink->node_from > proximity_domain)
2252 p2plink->node_from--;
2253 if (p2plink->node_to > proximity_domain)
2254 p2plink->node_to--;
2255 }
2256 }
2257 }
2258 }
2259
kfd_topology_remove_device(struct kfd_node * gpu)2260 int kfd_topology_remove_device(struct kfd_node *gpu)
2261 {
2262 struct kfd_topology_device *dev, *tmp;
2263 uint32_t gpu_id;
2264 int res = -ENODEV;
2265 int i = 0;
2266
2267 down_write(&topology_lock);
2268
2269 list_for_each_entry_safe(dev, tmp, &topology_device_list, list) {
2270 if (dev->gpu == gpu) {
2271 gpu_id = dev->gpu_id;
2272 kfd_remove_sysfs_node_entry(dev);
2273 kfd_release_topology_device(dev);
2274 sys_props.num_devices--;
2275 kfd_topology_update_io_links(i);
2276 topology_crat_proximity_domain = sys_props.num_devices-1;
2277 sys_props.generation_count++;
2278 res = 0;
2279 if (kfd_topology_update_sysfs() < 0)
2280 kfd_topology_release_sysfs();
2281 break;
2282 }
2283 i++;
2284 }
2285
2286 up_write(&topology_lock);
2287
2288 if (!res)
2289 kfd_notify_gpu_change(gpu_id, 0);
2290
2291 return res;
2292 }
2293
2294 /* kfd_topology_enum_kfd_devices - Enumerate through all devices in KFD
2295 * topology. If GPU device is found @idx, then valid kfd_dev pointer is
2296 * returned through @kdev
2297 * Return - 0: On success (@kdev will be NULL for non GPU nodes)
2298 * -1: If end of list
2299 */
kfd_topology_enum_kfd_devices(uint8_t idx,struct kfd_node ** kdev)2300 int kfd_topology_enum_kfd_devices(uint8_t idx, struct kfd_node **kdev)
2301 {
2302
2303 struct kfd_topology_device *top_dev;
2304 uint8_t device_idx = 0;
2305
2306 *kdev = NULL;
2307 down_read(&topology_lock);
2308
2309 list_for_each_entry(top_dev, &topology_device_list, list) {
2310 if (device_idx == idx) {
2311 *kdev = top_dev->gpu;
2312 up_read(&topology_lock);
2313 return 0;
2314 }
2315
2316 device_idx++;
2317 }
2318
2319 up_read(&topology_lock);
2320
2321 return -1;
2322
2323 }
2324
kfd_cpumask_to_apic_id(const struct cpumask * cpumask)2325 static int kfd_cpumask_to_apic_id(const struct cpumask *cpumask)
2326 {
2327 int first_cpu_of_numa_node;
2328
2329 if (!cpumask || cpumask == cpu_none_mask)
2330 return -1;
2331 first_cpu_of_numa_node = cpumask_first(cpumask);
2332 if (first_cpu_of_numa_node >= nr_cpu_ids)
2333 return -1;
2334 #ifdef CONFIG_X86_64
2335 return cpu_data(first_cpu_of_numa_node).topo.apicid;
2336 #else
2337 return first_cpu_of_numa_node;
2338 #endif
2339 }
2340
2341 /* kfd_numa_node_to_apic_id - Returns the APIC ID of the first logical processor
2342 * of the given NUMA node (numa_node_id)
2343 * Return -1 on failure
2344 */
kfd_numa_node_to_apic_id(int numa_node_id)2345 int kfd_numa_node_to_apic_id(int numa_node_id)
2346 {
2347 if (numa_node_id == -1) {
2348 pr_warn("Invalid NUMA Node. Use online CPU mask\n");
2349 return kfd_cpumask_to_apic_id(cpu_online_mask);
2350 }
2351 return kfd_cpumask_to_apic_id(cpumask_of_node(numa_node_id));
2352 }
2353
2354 #if defined(CONFIG_DEBUG_FS)
2355
kfd_debugfs_hqds_by_device(struct seq_file * m,void * data)2356 int kfd_debugfs_hqds_by_device(struct seq_file *m, void *data)
2357 {
2358 struct kfd_topology_device *dev;
2359 unsigned int i = 0;
2360 int r = 0;
2361
2362 down_read(&topology_lock);
2363
2364 list_for_each_entry(dev, &topology_device_list, list) {
2365 if (!dev->gpu) {
2366 i++;
2367 continue;
2368 }
2369
2370 seq_printf(m, "Node %u, gpu_id %x:\n", i++, dev->gpu->id);
2371 r = dqm_debugfs_hqds(m, dev->gpu->dqm);
2372 if (r)
2373 break;
2374 }
2375
2376 up_read(&topology_lock);
2377
2378 return r;
2379 }
2380
kfd_debugfs_rls_by_device(struct seq_file * m,void * data)2381 int kfd_debugfs_rls_by_device(struct seq_file *m, void *data)
2382 {
2383 struct kfd_topology_device *dev;
2384 unsigned int i = 0;
2385 int r = 0;
2386
2387 down_read(&topology_lock);
2388
2389 list_for_each_entry(dev, &topology_device_list, list) {
2390 if (!dev->gpu) {
2391 i++;
2392 continue;
2393 }
2394
2395 seq_printf(m, "Node %u, gpu_id %x:\n", i++, dev->gpu->id);
2396 r = pm_debugfs_runlist(m, &dev->gpu->dqm->packet_mgr);
2397 if (r)
2398 break;
2399 }
2400
2401 up_read(&topology_lock);
2402
2403 return r;
2404 }
2405
2406 #endif
2407