1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 */ 24 25 #include "kfd_mqd_manager.h" 26 #include "amdgpu_amdkfd.h" 27 #include "kfd_device_queue_manager.h" 28 29 /* Mapping queue priority to pipe priority, indexed by queue priority */ 30 int pipe_priority_map[] = { 31 KFD_PIPE_PRIORITY_CS_LOW, 32 KFD_PIPE_PRIORITY_CS_LOW, 33 KFD_PIPE_PRIORITY_CS_LOW, 34 KFD_PIPE_PRIORITY_CS_LOW, 35 KFD_PIPE_PRIORITY_CS_LOW, 36 KFD_PIPE_PRIORITY_CS_LOW, 37 KFD_PIPE_PRIORITY_CS_LOW, 38 KFD_PIPE_PRIORITY_CS_MEDIUM, 39 KFD_PIPE_PRIORITY_CS_MEDIUM, 40 KFD_PIPE_PRIORITY_CS_MEDIUM, 41 KFD_PIPE_PRIORITY_CS_MEDIUM, 42 KFD_PIPE_PRIORITY_CS_HIGH, 43 KFD_PIPE_PRIORITY_CS_HIGH, 44 KFD_PIPE_PRIORITY_CS_HIGH, 45 KFD_PIPE_PRIORITY_CS_HIGH, 46 KFD_PIPE_PRIORITY_CS_HIGH 47 }; 48 49 struct kfd_mem_obj *allocate_hiq_mqd(struct mqd_manager *mm, struct queue_properties *q) 50 { 51 struct kfd_mem_obj *mqd_mem_obj; 52 struct kfd_node *dev = mm->dev; 53 54 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 55 if (!mqd_mem_obj) 56 return NULL; 57 58 mqd_mem_obj->mem = dev->dqm->hiq_sdma_mqd.mem; 59 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr; 60 mqd_mem_obj->cpu_ptr = dev->dqm->hiq_sdma_mqd.cpu_ptr; 61 62 return mqd_mem_obj; 63 } 64 65 struct kfd_mem_obj *allocate_sdma_mqd(struct mqd_manager *mm, 66 struct queue_properties *q) 67 { 68 struct kfd_mem_obj *mqd_mem_obj; 69 struct kfd_node *dev = mm->dev; 70 uint64_t offset; 71 72 mqd_mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL); 73 if (!mqd_mem_obj) 74 return NULL; 75 76 offset = (q->sdma_engine_id * 77 dev->kfd->device_info.num_sdma_queues_per_engine + 78 q->sdma_queue_id) * 79 dev->dqm->mqd_mgrs[KFD_MQD_TYPE_SDMA]->mqd_size; 80 81 offset += dev->dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size * 82 NUM_XCC(dev->xcc_mask); 83 84 mqd_mem_obj->mem = (void *)((uint64_t)dev->dqm->hiq_sdma_mqd.mem 85 + offset); 86 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset; 87 mqd_mem_obj->cpu_ptr = (uint32_t *)((uint64_t) 88 dev->dqm->hiq_sdma_mqd.cpu_ptr + offset); 89 90 return mqd_mem_obj; 91 } 92 93 void free_mqd_hiq_sdma(struct mqd_manager *mm, void *mqd, 94 struct kfd_mem_obj *mqd_mem_obj) 95 { 96 WARN_ON(!mqd_mem_obj->mem); 97 kfree(mqd_mem_obj); 98 } 99 100 void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm, 101 const uint32_t *cu_mask, uint32_t cu_mask_count, 102 uint32_t *se_mask, uint32_t inst) 103 { 104 struct amdgpu_cu_info *cu_info = &mm->dev->adev->gfx.cu_info; 105 struct amdgpu_gfx_config *gfx_info = &mm->dev->adev->gfx.config; 106 uint32_t cu_per_sh[KFD_MAX_NUM_SE][KFD_MAX_NUM_SH_PER_SE] = {0}; 107 bool wgp_mode_req = KFD_GC_VERSION(mm->dev) >= IP_VERSION(10, 0, 0); 108 uint32_t en_mask = wgp_mode_req ? 0x3 : 0x1; 109 int i, se, sh, cu, cu_bitmap_sh_mul, cu_inc = wgp_mode_req ? 2 : 1; 110 uint32_t cu_active_per_node; 111 int inc = cu_inc * NUM_XCC(mm->dev->xcc_mask); 112 int xcc_inst = inst + ffs(mm->dev->xcc_mask) - 1; 113 114 cu_active_per_node = cu_info->number / mm->dev->kfd->num_nodes; 115 if (cu_mask_count > cu_active_per_node) 116 cu_mask_count = cu_active_per_node; 117 118 /* Exceeding these bounds corrupts the stack and indicates a coding error. 119 * Returning with no CU's enabled will hang the queue, which should be 120 * attention grabbing. 121 */ 122 if (gfx_info->max_shader_engines > KFD_MAX_NUM_SE) { 123 dev_err(mm->dev->adev->dev, 124 "Exceeded KFD_MAX_NUM_SE, chip reports %d\n", 125 gfx_info->max_shader_engines); 126 return; 127 } 128 if (gfx_info->max_sh_per_se > KFD_MAX_NUM_SH_PER_SE) { 129 dev_err(mm->dev->adev->dev, 130 "Exceeded KFD_MAX_NUM_SH, chip reports %d\n", 131 gfx_info->max_sh_per_se * gfx_info->max_shader_engines); 132 return; 133 } 134 135 cu_bitmap_sh_mul = (KFD_GC_VERSION(mm->dev) >= IP_VERSION(11, 0, 0) && 136 KFD_GC_VERSION(mm->dev) < IP_VERSION(13, 0, 0)) ? 2 : 1; 137 138 /* Count active CUs per SH. 139 * 140 * Some CUs in an SH may be disabled. HW expects disabled CUs to be 141 * represented in the high bits of each SH's enable mask (the upper and lower 142 * 16 bits of se_mask) and will take care of the actual distribution of 143 * disabled CUs within each SH automatically. 144 * Each half of se_mask must be filled only on bits 0-cu_per_sh[se][sh]-1. 145 * 146 * See note on Arcturus cu_bitmap layout in gfx_v9_0_get_cu_info. 147 * See note on GFX11 cu_bitmap layout in gfx_v11_0_get_cu_info. 148 */ 149 for (se = 0; se < gfx_info->max_shader_engines; se++) 150 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) 151 cu_per_sh[se][sh] = hweight32( 152 cu_info->bitmap[xcc_inst][se % 4][sh + (se / 4) * 153 cu_bitmap_sh_mul]); 154 155 /* Symmetrically map cu_mask to all SEs & SHs: 156 * se_mask programs up to 2 SH in the upper and lower 16 bits. 157 * 158 * Examples 159 * Assuming 1 SH/SE, 4 SEs: 160 * cu_mask[0] bit0 -> se_mask[0] bit0 161 * cu_mask[0] bit1 -> se_mask[1] bit0 162 * ... 163 * cu_mask[0] bit4 -> se_mask[0] bit1 164 * ... 165 * 166 * Assuming 2 SH/SE, 4 SEs 167 * cu_mask[0] bit0 -> se_mask[0] bit0 (SE0,SH0,CU0) 168 * cu_mask[0] bit1 -> se_mask[1] bit0 (SE1,SH0,CU0) 169 * ... 170 * cu_mask[0] bit4 -> se_mask[0] bit16 (SE0,SH1,CU0) 171 * cu_mask[0] bit5 -> se_mask[1] bit16 (SE1,SH1,CU0) 172 * ... 173 * cu_mask[0] bit8 -> se_mask[0] bit1 (SE0,SH0,CU1) 174 * ... 175 * 176 * For GFX 9.4.3, the following code only looks at a 177 * subset of the cu_mask corresponding to the inst parameter. 178 * If we have n XCCs under one GPU node 179 * cu_mask[0] bit0 -> XCC0 se_mask[0] bit0 (XCC0,SE0,SH0,CU0) 180 * cu_mask[0] bit1 -> XCC1 se_mask[0] bit0 (XCC1,SE0,SH0,CU0) 181 * .. 182 * cu_mask[0] bitn -> XCCn se_mask[0] bit0 (XCCn,SE0,SH0,CU0) 183 * cu_mask[0] bit n+1 -> XCC0 se_mask[1] bit0 (XCC0,SE1,SH0,CU0) 184 * 185 * For example, if there are 6 XCCs under 1 KFD node, this code 186 * running for each inst, will look at the bits as: 187 * inst, inst + 6, inst + 12... 188 * 189 * First ensure all CUs are disabled, then enable user specified CUs. 190 */ 191 for (i = 0; i < gfx_info->max_shader_engines; i++) 192 se_mask[i] = 0; 193 194 i = inst; 195 for (cu = 0; cu < 16; cu += cu_inc) { 196 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) { 197 for (se = 0; se < gfx_info->max_shader_engines; se++) { 198 if (cu_per_sh[se][sh] > cu) { 199 if (cu_mask[i / 32] & (en_mask << (i % 32))) 200 se_mask[se] |= en_mask << (cu + sh * 16); 201 i += inc; 202 if (i >= cu_mask_count) 203 return; 204 } 205 } 206 } 207 } 208 } 209 210 int kfd_hiq_load_mqd_kiq(struct mqd_manager *mm, void *mqd, 211 uint32_t pipe_id, uint32_t queue_id, 212 struct queue_properties *p, struct mm_struct *mms) 213 { 214 return mm->dev->kfd2kgd->hiq_mqd_load(mm->dev->adev, mqd, pipe_id, 215 queue_id, p->doorbell_off, 0); 216 } 217 218 int kfd_destroy_mqd_cp(struct mqd_manager *mm, void *mqd, 219 enum kfd_preempt_type type, unsigned int timeout, 220 uint32_t pipe_id, uint32_t queue_id) 221 { 222 return mm->dev->kfd2kgd->hqd_destroy(mm->dev->adev, mqd, type, timeout, 223 pipe_id, queue_id, 0); 224 } 225 226 void kfd_free_mqd_cp(struct mqd_manager *mm, void *mqd, 227 struct kfd_mem_obj *mqd_mem_obj) 228 { 229 if (mqd_mem_obj->mem) { 230 amdgpu_amdkfd_free_kernel_mem(mm->dev->adev, &mqd_mem_obj->mem); 231 kfree(mqd_mem_obj); 232 } else { 233 kfd_gtt_sa_free(mm->dev, mqd_mem_obj); 234 } 235 } 236 237 bool kfd_is_occupied_cp(struct mqd_manager *mm, void *mqd, 238 uint64_t queue_address, uint32_t pipe_id, 239 uint32_t queue_id) 240 { 241 return mm->dev->kfd2kgd->hqd_is_occupied(mm->dev->adev, queue_address, 242 pipe_id, queue_id, 0); 243 } 244 245 int kfd_load_mqd_sdma(struct mqd_manager *mm, void *mqd, 246 uint32_t pipe_id, uint32_t queue_id, 247 struct queue_properties *p, struct mm_struct *mms) 248 { 249 return mm->dev->kfd2kgd->hqd_sdma_load(mm->dev->adev, mqd, 250 (uint32_t __user *)p->write_ptr, 251 mms); 252 } 253 254 /* 255 * preempt type here is ignored because there is only one way 256 * to preempt sdma queue 257 */ 258 int kfd_destroy_mqd_sdma(struct mqd_manager *mm, void *mqd, 259 enum kfd_preempt_type type, 260 unsigned int timeout, uint32_t pipe_id, 261 uint32_t queue_id) 262 { 263 return mm->dev->kfd2kgd->hqd_sdma_destroy(mm->dev->adev, mqd, timeout); 264 } 265 266 bool kfd_is_occupied_sdma(struct mqd_manager *mm, void *mqd, 267 uint64_t queue_address, uint32_t pipe_id, 268 uint32_t queue_id) 269 { 270 return mm->dev->kfd2kgd->hqd_sdma_is_occupied(mm->dev->adev, mqd); 271 } 272 273 uint64_t kfd_hiq_mqd_stride(struct kfd_node *dev) 274 { 275 return dev->dqm->mqd_mgrs[KFD_MQD_TYPE_HIQ]->mqd_size; 276 } 277 278 void kfd_get_hiq_xcc_mqd(struct kfd_node *dev, struct kfd_mem_obj *mqd_mem_obj, 279 uint32_t virtual_xcc_id) 280 { 281 uint64_t offset; 282 283 offset = kfd_hiq_mqd_stride(dev) * virtual_xcc_id; 284 285 mqd_mem_obj->mem = (virtual_xcc_id == 0) ? 286 dev->dqm->hiq_sdma_mqd.mem : NULL; 287 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset; 288 mqd_mem_obj->cpu_ptr = (uint32_t *)((uintptr_t) 289 dev->dqm->hiq_sdma_mqd.cpu_ptr + offset); 290 } 291 292 uint64_t kfd_mqd_stride(struct mqd_manager *mm, 293 struct queue_properties *q) 294 { 295 if (KFD_GC_VERSION(mm->dev) >= IP_VERSION(11, 0, 0)) 296 return AMDGPU_MQD_SIZE_ALIGN(mm->mqd_size); 297 298 return mm->mqd_size; 299 } 300 301 bool kfd_check_hiq_mqd_doorbell_id(struct kfd_node *node, uint32_t doorbell_id, 302 uint32_t inst) 303 { 304 if (doorbell_id) { 305 struct device *dev = node->adev->dev; 306 307 if (node->adev->xcp_mgr && node->adev->xcp_mgr->num_xcps > 0) 308 dev_err(dev, "XCC %d: Queue preemption failed for queue with doorbell_id: %x\n", 309 inst, doorbell_id); 310 else 311 dev_err(dev, "Queue preemption failed for queue with doorbell_id: %x\n", 312 doorbell_id); 313 return true; 314 } 315 316 return false; 317 } 318