1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /* 3 * Copyright 2014-2022 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/bsearch.h> 25 #include <linux/pci.h> 26 #include <linux/slab.h> 27 #include "kfd_priv.h" 28 #include "kfd_device_queue_manager.h" 29 #include "kfd_pm4_headers_vi.h" 30 #include "kfd_pm4_headers_aldebaran.h" 31 #include "cwsr_trap_handler.h" 32 #include "amdgpu_amdkfd.h" 33 #include "kfd_smi_events.h" 34 #include "kfd_svm.h" 35 #include "kfd_migrate.h" 36 #include "amdgpu.h" 37 #include "amdgpu_xcp.h" 38 39 #define MQD_SIZE_ALIGNED 768 40 41 /* 42 * kfd_locked is used to lock the kfd driver during suspend or reset 43 * once locked, kfd driver will stop any further GPU execution. 44 * create process (open) will return -EAGAIN. 45 */ 46 static int kfd_locked; 47 48 #ifdef CONFIG_DRM_AMDGPU_CIK 49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd; 50 #endif 51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd; 52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd; 53 extern const struct kfd2kgd_calls arcturus_kfd2kgd; 54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd; 55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd; 56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd; 57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd; 58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd; 59 extern const struct kfd2kgd_calls gfx_v12_kfd2kgd; 60 extern const struct kfd2kgd_calls gfx_v12_1_kfd2kgd; 61 62 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 63 unsigned int chunk_size); 64 static void kfd_gtt_sa_fini(struct kfd_dev *kfd); 65 66 static int kfd_resume(struct kfd_node *kfd); 67 68 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd) 69 { 70 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0); 71 72 switch (sdma_version) { 73 case IP_VERSION(4, 0, 0):/* VEGA10 */ 74 case IP_VERSION(4, 0, 1):/* VEGA12 */ 75 case IP_VERSION(4, 1, 0):/* RAVEN */ 76 case IP_VERSION(4, 1, 1):/* RAVEN */ 77 case IP_VERSION(4, 1, 2):/* RENOIR */ 78 case IP_VERSION(5, 2, 1):/* VANGOGH */ 79 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */ 80 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */ 81 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */ 82 kfd->device_info.num_sdma_queues_per_engine = 2; 83 break; 84 case IP_VERSION(4, 2, 0):/* VEGA20 */ 85 case IP_VERSION(4, 2, 2):/* ARCTURUS */ 86 case IP_VERSION(4, 4, 0):/* ALDEBARAN */ 87 case IP_VERSION(4, 4, 2): 88 case IP_VERSION(4, 4, 5): 89 case IP_VERSION(4, 4, 4): 90 case IP_VERSION(5, 0, 0):/* NAVI10 */ 91 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */ 92 case IP_VERSION(5, 0, 2):/* NAVI14 */ 93 case IP_VERSION(5, 0, 5):/* NAVI12 */ 94 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */ 95 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */ 96 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */ 97 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */ 98 kfd->device_info.num_sdma_queues_per_engine = 8; 99 break; 100 case IP_VERSION(6, 0, 0): 101 case IP_VERSION(6, 0, 1): 102 case IP_VERSION(6, 0, 2): 103 case IP_VERSION(6, 0, 3): 104 case IP_VERSION(6, 1, 0): 105 case IP_VERSION(6, 1, 1): 106 case IP_VERSION(6, 1, 2): 107 case IP_VERSION(6, 1, 3): 108 case IP_VERSION(6, 1, 4): 109 case IP_VERSION(6, 4, 0): 110 case IP_VERSION(7, 0, 0): 111 case IP_VERSION(7, 0, 1): 112 case IP_VERSION(7, 1, 0): 113 kfd->device_info.num_sdma_queues_per_engine = 8; 114 /* Reserve 1 for paging and 1 for gfx */ 115 kfd->device_info.num_reserved_sdma_queues_per_engine = 2; 116 break; 117 default: 118 dev_warn(kfd_device, 119 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n", 120 sdma_version); 121 kfd->device_info.num_sdma_queues_per_engine = 8; 122 } 123 } 124 125 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd) 126 { 127 uint32_t gc_version = KFD_GC_VERSION(kfd); 128 129 switch (gc_version) { 130 case IP_VERSION(9, 0, 1): /* VEGA10 */ 131 case IP_VERSION(9, 1, 0): /* RAVEN */ 132 case IP_VERSION(9, 2, 1): /* VEGA12 */ 133 case IP_VERSION(9, 2, 2): /* RAVEN */ 134 case IP_VERSION(9, 3, 0): /* RENOIR */ 135 case IP_VERSION(9, 4, 0): /* VEGA20 */ 136 case IP_VERSION(9, 4, 1): /* ARCTURUS */ 137 case IP_VERSION(9, 4, 2): /* ALDEBARAN */ 138 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 139 break; 140 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */ 141 case IP_VERSION(9, 4, 4): /* GC 9.4.4 */ 142 case IP_VERSION(9, 5, 0): /* GC 9.5.0 */ 143 kfd->device_info.event_interrupt_class = 144 &event_interrupt_class_v9_4_3; 145 break; 146 case IP_VERSION(10, 3, 1): /* VANGOGH */ 147 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */ 148 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */ 149 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */ 150 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */ 151 case IP_VERSION(10, 1, 4): 152 case IP_VERSION(10, 1, 10): /* NAVI10 */ 153 case IP_VERSION(10, 1, 2): /* NAVI12 */ 154 case IP_VERSION(10, 1, 1): /* NAVI14 */ 155 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */ 156 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */ 157 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */ 158 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */ 159 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10; 160 break; 161 case IP_VERSION(11, 0, 0): 162 case IP_VERSION(11, 0, 1): 163 case IP_VERSION(11, 0, 2): 164 case IP_VERSION(11, 0, 3): 165 case IP_VERSION(11, 0, 4): 166 case IP_VERSION(11, 5, 0): 167 case IP_VERSION(11, 5, 1): 168 case IP_VERSION(11, 5, 2): 169 case IP_VERSION(11, 5, 3): 170 case IP_VERSION(11, 5, 4): 171 case IP_VERSION(11, 5, 6): 172 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 173 break; 174 case IP_VERSION(12, 0, 0): 175 case IP_VERSION(12, 0, 1): 176 /* GFX12_TODO: Change to v12 version. */ 177 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11; 178 break; 179 case IP_VERSION(12, 1, 0): 180 kfd->device_info.event_interrupt_class = 181 &event_interrupt_class_v12_1; 182 break; 183 default: 184 dev_warn(kfd_device, "v9 event interrupt handler is set due to " 185 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version); 186 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9; 187 } 188 } 189 190 static void kfd_device_info_init(struct kfd_dev *kfd, 191 bool vf, uint32_t gfx_target_version) 192 { 193 uint32_t gc_version = KFD_GC_VERSION(kfd); 194 uint32_t asic_type = kfd->adev->asic_type; 195 196 kfd->device_info.max_pasid_bits = 16; 197 kfd->device_info.max_no_of_hqd = 24; 198 kfd->device_info.num_of_watch_points = 4; 199 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED; 200 kfd->device_info.gfx_target_version = gfx_target_version; 201 202 if (KFD_IS_SOC15(kfd)) { 203 kfd->device_info.doorbell_size = 8; 204 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t); 205 kfd->device_info.supports_cwsr = true; 206 207 kfd_device_info_set_sdma_info(kfd); 208 209 kfd_device_info_set_event_interrupt_class(kfd); 210 211 if (gc_version < IP_VERSION(11, 0, 0)) { 212 /* Navi2x+, Navi1x+ */ 213 if (gc_version == IP_VERSION(10, 3, 6)) 214 kfd->device_info.no_atomic_fw_version = 14; 215 else if (gc_version == IP_VERSION(10, 3, 7)) 216 kfd->device_info.no_atomic_fw_version = 3; 217 else if (gc_version >= IP_VERSION(10, 3, 0)) 218 kfd->device_info.no_atomic_fw_version = 92; 219 else if (gc_version >= IP_VERSION(10, 1, 1)) 220 kfd->device_info.no_atomic_fw_version = 145; 221 222 /* Navi1x+ */ 223 if (gc_version >= IP_VERSION(10, 1, 1)) 224 kfd->device_info.needs_pci_atomics = true; 225 } else if (gc_version < IP_VERSION(12, 0, 0)) { 226 /* 227 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires 228 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require 229 * PCIe atomics support. 230 */ 231 kfd->device_info.needs_pci_atomics = true; 232 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0; 233 } else if (gc_version < IP_VERSION(13, 0, 0)) { 234 kfd->device_info.needs_pci_atomics = true; 235 kfd->device_info.no_atomic_fw_version = 2090; 236 } else { 237 kfd->device_info.needs_pci_atomics = true; 238 } 239 } else { 240 kfd->device_info.doorbell_size = 4; 241 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t); 242 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik; 243 kfd->device_info.num_sdma_queues_per_engine = 2; 244 245 if (asic_type != CHIP_KAVERI && 246 asic_type != CHIP_HAWAII && 247 asic_type != CHIP_TONGA) 248 kfd->device_info.supports_cwsr = true; 249 250 if (asic_type != CHIP_HAWAII && !vf) 251 kfd->device_info.needs_pci_atomics = true; 252 } 253 } 254 255 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 256 { 257 struct kfd_dev *kfd = NULL; 258 const struct kfd2kgd_calls *f2g = NULL; 259 uint32_t gfx_target_version = 0; 260 261 switch (adev->asic_type) { 262 #ifdef CONFIG_DRM_AMDGPU_CIK 263 case CHIP_KAVERI: 264 gfx_target_version = 70000; 265 if (!vf) 266 f2g = &gfx_v7_kfd2kgd; 267 break; 268 #endif 269 case CHIP_CARRIZO: 270 gfx_target_version = 80001; 271 if (!vf) 272 f2g = &gfx_v8_kfd2kgd; 273 break; 274 #ifdef CONFIG_DRM_AMDGPU_CIK 275 case CHIP_HAWAII: 276 gfx_target_version = 70001; 277 if (!amdgpu_exp_hw_support) 278 pr_info( 279 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n" 280 ); 281 else if (!vf) 282 f2g = &gfx_v7_kfd2kgd; 283 break; 284 #endif 285 case CHIP_TONGA: 286 gfx_target_version = 80002; 287 if (!vf) 288 f2g = &gfx_v8_kfd2kgd; 289 break; 290 case CHIP_FIJI: 291 case CHIP_POLARIS10: 292 gfx_target_version = 80003; 293 f2g = &gfx_v8_kfd2kgd; 294 break; 295 case CHIP_POLARIS11: 296 case CHIP_POLARIS12: 297 case CHIP_VEGAM: 298 gfx_target_version = 80003; 299 if (!vf) 300 f2g = &gfx_v8_kfd2kgd; 301 break; 302 default: 303 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 304 /* Vega 10 */ 305 case IP_VERSION(9, 0, 1): 306 gfx_target_version = 90000; 307 f2g = &gfx_v9_kfd2kgd; 308 break; 309 /* Raven */ 310 case IP_VERSION(9, 1, 0): 311 case IP_VERSION(9, 2, 2): 312 gfx_target_version = 90002; 313 if (!vf) 314 f2g = &gfx_v9_kfd2kgd; 315 break; 316 /* Vega12 */ 317 case IP_VERSION(9, 2, 1): 318 gfx_target_version = 90004; 319 if (!vf) 320 f2g = &gfx_v9_kfd2kgd; 321 break; 322 /* Renoir */ 323 case IP_VERSION(9, 3, 0): 324 gfx_target_version = 90012; 325 if (!vf) 326 f2g = &gfx_v9_kfd2kgd; 327 break; 328 /* Vega20 */ 329 case IP_VERSION(9, 4, 0): 330 gfx_target_version = 90006; 331 if (!vf) 332 f2g = &gfx_v9_kfd2kgd; 333 break; 334 /* Arcturus */ 335 case IP_VERSION(9, 4, 1): 336 gfx_target_version = 90008; 337 f2g = &arcturus_kfd2kgd; 338 break; 339 /* Aldebaran */ 340 case IP_VERSION(9, 4, 2): 341 gfx_target_version = 90010; 342 f2g = &aldebaran_kfd2kgd; 343 break; 344 case IP_VERSION(9, 4, 3): 345 case IP_VERSION(9, 4, 4): 346 gfx_target_version = 90402; 347 f2g = &gc_9_4_3_kfd2kgd; 348 break; 349 case IP_VERSION(9, 5, 0): 350 gfx_target_version = 90500; 351 f2g = &gc_9_4_3_kfd2kgd; 352 break; 353 /* Navi10 */ 354 case IP_VERSION(10, 1, 10): 355 gfx_target_version = 100100; 356 if (!vf) 357 f2g = &gfx_v10_kfd2kgd; 358 break; 359 /* Navi12 */ 360 case IP_VERSION(10, 1, 2): 361 gfx_target_version = 100101; 362 f2g = &gfx_v10_kfd2kgd; 363 break; 364 /* Navi14 */ 365 case IP_VERSION(10, 1, 1): 366 gfx_target_version = 100102; 367 if (!vf) 368 f2g = &gfx_v10_kfd2kgd; 369 break; 370 /* Cyan Skillfish */ 371 case IP_VERSION(10, 1, 3): 372 case IP_VERSION(10, 1, 4): 373 gfx_target_version = 100103; 374 if (!vf) 375 f2g = &gfx_v10_kfd2kgd; 376 break; 377 /* Sienna Cichlid */ 378 case IP_VERSION(10, 3, 0): 379 gfx_target_version = 100300; 380 f2g = &gfx_v10_3_kfd2kgd; 381 break; 382 /* Navy Flounder */ 383 case IP_VERSION(10, 3, 2): 384 gfx_target_version = 100301; 385 f2g = &gfx_v10_3_kfd2kgd; 386 break; 387 /* Van Gogh */ 388 case IP_VERSION(10, 3, 1): 389 gfx_target_version = 100303; 390 if (!vf) 391 f2g = &gfx_v10_3_kfd2kgd; 392 break; 393 /* Dimgrey Cavefish */ 394 case IP_VERSION(10, 3, 4): 395 gfx_target_version = 100302; 396 f2g = &gfx_v10_3_kfd2kgd; 397 break; 398 /* Beige Goby */ 399 case IP_VERSION(10, 3, 5): 400 gfx_target_version = 100304; 401 f2g = &gfx_v10_3_kfd2kgd; 402 break; 403 /* Yellow Carp */ 404 case IP_VERSION(10, 3, 3): 405 gfx_target_version = 100305; 406 if (!vf) 407 f2g = &gfx_v10_3_kfd2kgd; 408 break; 409 case IP_VERSION(10, 3, 6): 410 case IP_VERSION(10, 3, 7): 411 gfx_target_version = 100306; 412 if (!vf) 413 f2g = &gfx_v10_3_kfd2kgd; 414 break; 415 case IP_VERSION(11, 0, 0): 416 gfx_target_version = 110000; 417 f2g = &gfx_v11_kfd2kgd; 418 break; 419 case IP_VERSION(11, 0, 1): 420 case IP_VERSION(11, 0, 4): 421 gfx_target_version = 110003; 422 f2g = &gfx_v11_kfd2kgd; 423 break; 424 case IP_VERSION(11, 0, 2): 425 gfx_target_version = 110002; 426 f2g = &gfx_v11_kfd2kgd; 427 break; 428 case IP_VERSION(11, 0, 3): 429 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */ 430 gfx_target_version = 110001; 431 f2g = &gfx_v11_kfd2kgd; 432 break; 433 case IP_VERSION(11, 5, 0): 434 gfx_target_version = 110500; 435 f2g = &gfx_v11_kfd2kgd; 436 break; 437 case IP_VERSION(11, 5, 1): 438 gfx_target_version = 110501; 439 f2g = &gfx_v11_kfd2kgd; 440 break; 441 case IP_VERSION(11, 5, 2): 442 gfx_target_version = 110502; 443 f2g = &gfx_v11_kfd2kgd; 444 break; 445 case IP_VERSION(11, 5, 3): 446 gfx_target_version = 110503; 447 f2g = &gfx_v11_kfd2kgd; 448 break; 449 case IP_VERSION(11, 5, 4): 450 case IP_VERSION(11, 5, 6): 451 gfx_target_version = 110504; 452 f2g = &gfx_v11_kfd2kgd; 453 break; 454 case IP_VERSION(12, 0, 0): 455 gfx_target_version = 120000; 456 f2g = &gfx_v12_kfd2kgd; 457 break; 458 case IP_VERSION(12, 0, 1): 459 gfx_target_version = 120001; 460 f2g = &gfx_v12_kfd2kgd; 461 break; 462 case IP_VERSION(12, 1, 0): 463 gfx_target_version = 120500; 464 f2g = &gfx_v12_1_kfd2kgd; 465 break; 466 default: 467 break; 468 } 469 break; 470 } 471 472 if (!f2g) { 473 if (amdgpu_ip_version(adev, GC_HWIP, 0)) 474 dev_info(kfd_device, 475 "GC IP %06x %s not supported in kfd\n", 476 amdgpu_ip_version(adev, GC_HWIP, 0), 477 vf ? "VF" : ""); 478 else 479 dev_info(kfd_device, "%s %s not supported in kfd\n", 480 amdgpu_asic_name[adev->asic_type], vf ? "VF" : ""); 481 return NULL; 482 } 483 484 kfd = kzalloc_obj(*kfd); 485 if (!kfd) 486 return NULL; 487 488 kfd->adev = adev; 489 kfd_device_info_init(kfd, vf, gfx_target_version); 490 kfd->init_complete = false; 491 kfd->kfd2kgd = f2g; 492 atomic_set(&kfd->compute_profile, 0); 493 494 mutex_init(&kfd->doorbell_mutex); 495 496 ida_init(&kfd->doorbell_ida); 497 atomic_set(&kfd->kfd_processes_count, 0); 498 499 return kfd; 500 } 501 502 static void kfd_cwsr_init(struct kfd_dev *kfd) 503 { 504 if (cwsr_enable && kfd->device_info.supports_cwsr) { 505 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) { 506 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) 507 > KFD_CWSR_TMA_OFFSET); 508 kfd->cwsr_isa = cwsr_trap_gfx8_hex; 509 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex); 510 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) { 511 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) 512 > KFD_CWSR_TMA_OFFSET); 513 kfd->cwsr_isa = cwsr_trap_arcturus_hex; 514 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex); 515 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) { 516 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) 517 > KFD_CWSR_TMA_OFFSET); 518 kfd->cwsr_isa = cwsr_trap_aldebaran_hex; 519 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex); 520 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) || 521 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) { 522 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) 523 > KFD_CWSR_TMA_OFFSET); 524 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex; 525 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex); 526 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 5, 0)) { 527 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_5_0_hex) > PAGE_SIZE); 528 kfd->cwsr_isa = cwsr_trap_gfx9_5_0_hex; 529 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_5_0_hex); 530 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) { 531 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) 532 > KFD_CWSR_TMA_OFFSET); 533 kfd->cwsr_isa = cwsr_trap_gfx9_hex; 534 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex); 535 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) { 536 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) 537 > KFD_CWSR_TMA_OFFSET); 538 kfd->cwsr_isa = cwsr_trap_nv1x_hex; 539 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex); 540 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) { 541 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) 542 > KFD_CWSR_TMA_OFFSET); 543 kfd->cwsr_isa = cwsr_trap_gfx10_hex; 544 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex); 545 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0)) { 546 /* The gfx11 cwsr trap handler must fit inside a single 547 page. */ 548 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE); 549 kfd->cwsr_isa = cwsr_trap_gfx11_hex; 550 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex); 551 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 1, 0)) { 552 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex) 553 > KFD_CWSR_TMA_OFFSET); 554 kfd->cwsr_isa = cwsr_trap_gfx12_hex; 555 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex); 556 } else { 557 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_1_0_hex) 558 > KFD_CWSR_TMA_OFFSET); 559 kfd->cwsr_isa = cwsr_trap_gfx12_1_0_hex; 560 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_1_0_hex); 561 } 562 563 kfd->cwsr_enabled = true; 564 } 565 } 566 567 static int kfd_gws_init(struct kfd_node *node) 568 { 569 int ret = 0; 570 struct kfd_dev *kfd = node->kfd; 571 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; 572 573 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) 574 return 0; 575 576 if (hws_gws_support || (KFD_IS_SOC15(node) && 577 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1) 578 && kfd->mec2_fw_version >= 0x81b3) || 579 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0) 580 && kfd->mec2_fw_version >= 0x1b3) || 581 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1) 582 && kfd->mec2_fw_version >= 0x30) || 583 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2) 584 && kfd->mec2_fw_version >= 0x28) || 585 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3) || 586 KFD_GC_VERSION(node) == IP_VERSION(9, 4, 4)) || 587 (KFD_GC_VERSION(node) == IP_VERSION(9, 5, 0)) || 588 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0) 589 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0) 590 && kfd->mec2_fw_version >= 0x6b) || 591 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0) 592 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0) 593 && mes_rev >= 68) || 594 (KFD_GC_VERSION(node) >= IP_VERSION(12, 0, 0))))) { 595 if (KFD_GC_VERSION(node) >= IP_VERSION(12, 0, 0)) 596 node->adev->gds.gws_size = 64; 597 ret = amdgpu_amdkfd_alloc_gws(node->adev, 598 node->adev->gds.gws_size, &node->gws); 599 } 600 601 return ret; 602 } 603 604 static void kfd_smi_init(struct kfd_node *dev) 605 { 606 INIT_LIST_HEAD(&dev->smi_clients); 607 spin_lock_init(&dev->smi_lock); 608 } 609 610 static int kfd_init_node(struct kfd_node *node) 611 { 612 int err = -1; 613 614 if (kfd_interrupt_init(node)) { 615 dev_err(kfd_device, "Error initializing interrupts\n"); 616 goto kfd_interrupt_error; 617 } 618 619 node->dqm = device_queue_manager_init(node); 620 if (!node->dqm) { 621 dev_err(kfd_device, "Error initializing queue manager\n"); 622 goto device_queue_manager_error; 623 } 624 625 if (kfd_gws_init(node)) { 626 dev_err(kfd_device, "Could not allocate %d gws\n", 627 node->adev->gds.gws_size); 628 goto gws_error; 629 } 630 631 if (kfd_resume(node)) 632 goto kfd_resume_error; 633 634 if (kfd_topology_add_device(node)) { 635 dev_err(kfd_device, "Error adding device to topology\n"); 636 goto kfd_topology_add_device_error; 637 } 638 639 kfd_smi_init(node); 640 641 return 0; 642 643 kfd_topology_add_device_error: 644 kfd_resume_error: 645 gws_error: 646 device_queue_manager_uninit(node->dqm); 647 device_queue_manager_error: 648 kfd_interrupt_exit(node); 649 kfd_interrupt_error: 650 if (node->gws) 651 amdgpu_amdkfd_free_gws(node->adev, node->gws); 652 653 /* Cleanup the node memory here */ 654 kfree(node); 655 return err; 656 } 657 658 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) 659 { 660 struct kfd_node *knode; 661 unsigned int i; 662 663 /* 664 * flush_work ensures that there are no outstanding 665 * work-queue items that will access interrupt_ring. New work items 666 * can't be created because we stopped interrupt handling above. 667 */ 668 flush_workqueue(kfd->ih_wq); 669 destroy_workqueue(kfd->ih_wq); 670 671 for (i = 0; i < num_nodes; i++) { 672 knode = kfd->nodes[i]; 673 device_queue_manager_uninit(knode->dqm); 674 kfd_interrupt_exit(knode); 675 kfd_topology_remove_device(knode); 676 if (knode->gws) 677 amdgpu_amdkfd_free_gws(knode->adev, knode->gws); 678 kfree(knode); 679 kfd->nodes[i] = NULL; 680 } 681 } 682 683 static void kfd_setup_interrupt_bitmap(struct kfd_node *node, 684 unsigned int kfd_node_idx) 685 { 686 struct amdgpu_device *adev = node->adev; 687 uint32_t xcc_mask = node->xcc_mask; 688 uint32_t xcc, mapped_xcc; 689 uint32_t bitmap; 690 /* 691 * Interrupt bitmap is setup for processing interrupts from 692 * different XCDs and AIDs. 693 * Interrupt bitmap is defined as follows: 694 * 1. Bits 0-15 - correspond to the NodeId field. 695 * Each bit corresponds to NodeId number. For example, if 696 * a KFD node has interrupt bitmap set to 0x7, then this 697 * KFD node will process interrupts with NodeId = 0, 1 and 2 698 * in the IH cookie. 699 * 2. Bits 16-31 - unused. 700 * 701 * Please note that the kfd_node_idx argument passed to this 702 * function is not related to NodeId field received in the 703 * IH cookie. 704 * 705 * In CPX mode, a KFD node will process an interrupt if: 706 * - the Node Id matches the corresponding bit set in 707 * Bits 0-15. 708 * - AND VMID reported in the interrupt lies within the 709 * VMID range of the node. 710 */ 711 switch (KFD_GC_VERSION(node)) { 712 case IP_VERSION(12, 1, 0): 713 for_each_inst(xcc, xcc_mask) { 714 mapped_xcc = GET_INST(GC, xcc); 715 bitmap = 0x2 | (0x4 << (mapped_xcc % 4)); 716 if (mapped_xcc/4) 717 bitmap = bitmap << 8; 718 node->interrupt_bitmap |= bitmap; 719 } 720 break; 721 default: 722 for_each_inst(xcc, xcc_mask) { 723 mapped_xcc = GET_INST(GC, xcc); 724 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2)); 725 } 726 break; 727 } 728 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx, 729 node->interrupt_bitmap); 730 } 731 732 bool kgd2kfd_device_init(struct kfd_dev *kfd, 733 const struct kgd2kfd_shared_resources *gpu_resources) 734 { 735 unsigned int size, map_process_packet_size, i; 736 struct kfd_node *node; 737 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd; 738 unsigned int max_proc_per_quantum; 739 int partition_mode; 740 int xcp_idx; 741 742 kfd->profiler_process = NULL; 743 mutex_init(&kfd->profiler_lock); 744 745 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 746 KGD_ENGINE_MEC1); 747 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 748 KGD_ENGINE_MEC2); 749 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev, 750 KGD_ENGINE_SDMA1); 751 kfd->shared_resources = *gpu_resources; 752 753 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr); 754 755 if (kfd->num_nodes == 0) { 756 dev_err(kfd_device, 757 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n", 758 kfd->adev->gfx.num_xcc_per_xcp); 759 goto out; 760 } 761 762 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps. 763 * 32 and 64-bit requests are possible and must be 764 * supported. 765 */ 766 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev); 767 if (!kfd->pci_atomic_requested && 768 kfd->device_info.needs_pci_atomics && 769 (!kfd->device_info.no_atomic_fw_version || 770 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) { 771 dev_info(kfd_device, 772 "skipped device %x:%x, PCI rejects atomics %d<%d\n", 773 kfd->adev->pdev->vendor, kfd->adev->pdev->device, 774 kfd->mec_fw_version, 775 kfd->device_info.no_atomic_fw_version); 776 return false; 777 } 778 779 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1; 780 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1; 781 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1; 782 783 /* For multi-partition capable GPUs, we need special handling for VMIDs 784 * depending on partition mode. 785 * In CPX mode, the VMID range needs to be shared between XCDs. 786 * Additionally, there are 13 VMIDs (3-15) available for KFD. To 787 * divide them equally, we change starting VMID to 4 and not use 788 * VMID 3. 789 * If the VMID range changes for multi-partition capable GPUs, then 790 * this code MUST be revisited. 791 */ 792 if (kfd->adev->xcp_mgr && (KFD_GC_VERSION(kfd) != IP_VERSION(12, 1, 0))) { 793 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr, 794 AMDGPU_XCP_FL_LOCKED); 795 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 796 kfd->num_nodes != 1) { 797 vmid_num_kfd /= 2; 798 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2; 799 } 800 } 801 802 /* Verify module parameters regarding mapped process number*/ 803 if (hws_max_conc_proc >= 0) 804 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd); 805 else 806 max_proc_per_quantum = vmid_num_kfd; 807 808 /* calculate max size of mqds needed for queues */ 809 size = max_num_of_queues_per_device * 810 kfd->device_info.mqd_size_aligned; 811 812 /* 813 * calculate max size of runlist packet. 814 * There can be only 2 packets at once 815 */ 816 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ? 817 sizeof(struct pm4_mes_map_process_aldebaran) : 818 sizeof(struct pm4_mes_map_process); 819 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size + 820 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues) 821 + sizeof(struct pm4_mes_runlist)) * 2; 822 823 /* Add size of HIQ & DIQ */ 824 size += KFD_KERNEL_QUEUE_SIZE * 2; 825 826 /* add another 512KB for all other allocations on gart (HPD, fences) */ 827 size += 512 * 1024; 828 829 if (amdgpu_amdkfd_alloc_kernel_mem( 830 kfd->adev, size, AMDGPU_GEM_DOMAIN_GTT, 831 &kfd->gtt_mem, 832 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, 833 false)) { 834 dev_err(kfd_device, "Could not allocate %d bytes\n", size); 835 goto alloc_kernel_mem_failure; 836 } 837 838 dev_info(kfd_device, "Allocated %d bytes on gart\n", size); 839 840 /* Initialize GTT sa with 512 byte chunk size */ 841 if (kfd_gtt_sa_init(kfd, size, 512) != 0) { 842 dev_err(kfd_device, "Error initializing gtt sub-allocator\n"); 843 goto kfd_gtt_sa_init_error; 844 } 845 846 if (kfd_doorbell_init(kfd)) { 847 dev_err(kfd_device, 848 "Error initializing doorbell aperture\n"); 849 goto kfd_doorbell_error; 850 } 851 852 if (amdgpu_use_xgmi_p2p) 853 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id; 854 855 /* 856 * For multi-partition capable GPUs, the KFD abstracts all partitions 857 * within a socket as xGMI connected in the topology so assign a unique 858 * hive id per device based on the pci device location if device is in 859 * PCIe mode. 860 */ 861 if (!kfd->hive_id && kfd->num_nodes > 1) 862 kfd->hive_id = pci_dev_id(kfd->adev->pdev); 863 864 kfd->noretry = kfd->adev->gmc.noretry; 865 866 kfd_cwsr_init(kfd); 867 868 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n", 869 kfd->num_nodes); 870 871 /* Allocate the KFD nodes */ 872 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) { 873 node = kzalloc_obj(struct kfd_node); 874 if (!node) 875 goto node_alloc_error; 876 877 node->node_id = i; 878 node->adev = kfd->adev; 879 node->kfd = kfd; 880 node->kfd2kgd = kfd->kfd2kgd; 881 node->vm_info.vmid_num_kfd = vmid_num_kfd; 882 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx); 883 /* TODO : Check if error handling is needed */ 884 if (node->xcp) { 885 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX, 886 &node->xcc_mask); 887 ++xcp_idx; 888 } else { 889 node->xcc_mask = 890 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1; 891 } 892 893 if (node->xcp) { 894 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n", 895 node->node_id, node->xcp->mem_id, 896 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20); 897 } 898 899 if (partition_mode == AMDGPU_CPX_PARTITION_MODE && 900 kfd->num_nodes != 1 && 901 (KFD_GC_VERSION(kfd) != IP_VERSION(12, 1, 0))) { 902 /* For multi-partition capable GPUs and CPX mode, first 903 * XCD gets VMID range 4-9 and second XCD gets VMID 904 * range 10-15. 905 */ 906 907 node->vm_info.first_vmid_kfd = (i%2 == 0) ? 908 first_vmid_kfd : 909 first_vmid_kfd+vmid_num_kfd; 910 node->vm_info.last_vmid_kfd = (i%2 == 0) ? 911 last_vmid_kfd-vmid_num_kfd : 912 last_vmid_kfd; 913 node->compute_vmid_bitmap = 914 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) - 915 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1); 916 } else { 917 node->vm_info.first_vmid_kfd = first_vmid_kfd; 918 node->vm_info.last_vmid_kfd = last_vmid_kfd; 919 node->compute_vmid_bitmap = 920 gpu_resources->compute_vmid_bitmap; 921 } 922 923 node->max_proc_per_quantum = max_proc_per_quantum; 924 atomic_set(&node->sram_ecc_flag, 0); 925 926 amdgpu_amdkfd_get_local_mem_info(kfd->adev, 927 &node->local_mem_info, node->xcp); 928 929 if (kfd->adev->xcp_mgr) 930 kfd_setup_interrupt_bitmap(node, i); 931 932 /* Initialize the KFD node */ 933 if (kfd_init_node(node)) { 934 dev_err(kfd_device, "Error initializing KFD node\n"); 935 goto node_init_error; 936 } 937 938 spin_lock_init(&node->watch_points_lock); 939 940 kfd->nodes[i] = node; 941 } 942 943 svm_range_set_max_pages(kfd->adev); 944 945 kfd->init_complete = true; 946 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor, 947 kfd->adev->pdev->device); 948 949 pr_debug("Starting kfd with the following scheduling policy %d\n", 950 node->dqm->sched_policy); 951 952 goto out; 953 954 node_init_error: 955 node_alloc_error: 956 kfd_cleanup_nodes(kfd, i); 957 kfd_doorbell_fini(kfd); 958 kfd_doorbell_error: 959 kfd_gtt_sa_fini(kfd); 960 kfd_gtt_sa_init_error: 961 amdgpu_amdkfd_free_kernel_mem(kfd->adev, &kfd->gtt_mem); 962 alloc_kernel_mem_failure: 963 dev_err(kfd_device, 964 "device %x:%x NOT added due to errors\n", 965 kfd->adev->pdev->vendor, kfd->adev->pdev->device); 966 out: 967 return kfd->init_complete; 968 } 969 970 void kgd2kfd_device_exit(struct kfd_dev *kfd) 971 { 972 if (kfd->init_complete) { 973 /* Cleanup KFD nodes */ 974 kfd_cleanup_nodes(kfd, kfd->num_nodes); 975 /* Cleanup common/shared resources */ 976 kfd_doorbell_fini(kfd); 977 ida_destroy(&kfd->doorbell_ida); 978 kfd_gtt_sa_fini(kfd); 979 amdgpu_amdkfd_free_kernel_mem(kfd->adev, &kfd->gtt_mem); 980 mutex_destroy(&kfd->profiler_lock); 981 } 982 983 kfree(kfd); 984 985 /* after remove a kfd device unlock kfd driver */ 986 kgd2kfd_unlock_kfd(NULL); 987 } 988 989 int kgd2kfd_pre_reset(struct kfd_dev *kfd, 990 struct amdgpu_reset_context *reset_context) 991 { 992 struct kfd_node *node; 993 int i; 994 995 if (!kfd->init_complete) 996 return 0; 997 998 for (i = 0; i < kfd->num_nodes; i++) { 999 node = kfd->nodes[i]; 1000 kfd_smi_event_update_gpu_reset(node, false, reset_context); 1001 } 1002 1003 kgd2kfd_suspend(kfd, true); 1004 1005 for (i = 0; i < kfd->num_nodes; i++) 1006 kfd_signal_reset_event(kfd->nodes[i]); 1007 1008 return 0; 1009 } 1010 1011 /* 1012 * Fix me. KFD won't be able to resume existing process for now. 1013 * We will keep all existing process in a evicted state and 1014 * wait the process to be terminated. 1015 */ 1016 1017 int kgd2kfd_post_reset(struct kfd_dev *kfd) 1018 { 1019 int ret; 1020 struct kfd_node *node; 1021 int i; 1022 1023 if (!kfd->init_complete) 1024 return 0; 1025 1026 for (i = 0; i < kfd->num_nodes; i++) { 1027 ret = kfd_resume(kfd->nodes[i]); 1028 if (ret) 1029 return ret; 1030 } 1031 1032 mutex_lock(&kfd_processes_mutex); 1033 --kfd_locked; 1034 mutex_unlock(&kfd_processes_mutex); 1035 1036 for (i = 0; i < kfd->num_nodes; i++) { 1037 node = kfd->nodes[i]; 1038 atomic_set(&node->sram_ecc_flag, 0); 1039 kfd_smi_event_update_gpu_reset(node, true, NULL); 1040 } 1041 1042 return 0; 1043 } 1044 1045 bool kfd_is_locked(struct kfd_dev *kfd) 1046 { 1047 uint8_t id = 0; 1048 struct kfd_node *dev; 1049 1050 lockdep_assert_held(&kfd_processes_mutex); 1051 1052 /* check reset/suspend lock */ 1053 if (kfd_locked > 0) 1054 return true; 1055 1056 if (kfd) 1057 return kfd->kfd_dev_lock > 0; 1058 1059 /* check lock on all cgroup accessible devices */ 1060 while (kfd_topology_enum_kfd_devices(id++, &dev) == 0) { 1061 if (!dev || kfd_devcgroup_check_permission(dev)) 1062 continue; 1063 1064 if (dev->kfd->kfd_dev_lock > 0) 1065 return true; 1066 } 1067 1068 return false; 1069 } 1070 1071 void kgd2kfd_suspend(struct kfd_dev *kfd, bool suspend_proc) 1072 { 1073 struct kfd_node *node; 1074 int i; 1075 1076 if (!kfd->init_complete) 1077 return; 1078 1079 if (suspend_proc) 1080 kgd2kfd_suspend_process(kfd); 1081 1082 for (i = 0; i < kfd->num_nodes; i++) { 1083 node = kfd->nodes[i]; 1084 node->dqm->ops.stop(node->dqm); 1085 } 1086 } 1087 1088 int kgd2kfd_resume(struct kfd_dev *kfd, bool resume_proc) 1089 { 1090 int ret = 0, i; 1091 1092 if (!kfd->init_complete) 1093 return 0; 1094 1095 for (i = 0; i < kfd->num_nodes; i++) { 1096 ret = kfd_resume(kfd->nodes[i]); 1097 if (ret) 1098 return ret; 1099 } 1100 1101 if (resume_proc) 1102 ret = kgd2kfd_resume_process(kfd); 1103 1104 return ret; 1105 } 1106 1107 void kgd2kfd_suspend_process(struct kfd_dev *kfd) 1108 { 1109 if (!kfd->init_complete) 1110 return; 1111 1112 mutex_lock(&kfd_processes_mutex); 1113 /* For first KFD device suspend all the KFD processes */ 1114 if (++kfd_locked == 1) 1115 kfd_suspend_all_processes(); 1116 mutex_unlock(&kfd_processes_mutex); 1117 } 1118 1119 int kgd2kfd_resume_process(struct kfd_dev *kfd) 1120 { 1121 int ret = 0; 1122 1123 if (!kfd->init_complete) 1124 return 0; 1125 1126 mutex_lock(&kfd_processes_mutex); 1127 if (--kfd_locked == 0) 1128 ret = kfd_resume_all_processes(); 1129 WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error"); 1130 mutex_unlock(&kfd_processes_mutex); 1131 1132 return ret; 1133 } 1134 1135 static int kfd_resume(struct kfd_node *node) 1136 { 1137 int err = 0; 1138 1139 err = node->dqm->ops.start(node->dqm); 1140 if (err) 1141 dev_err(kfd_device, 1142 "Error starting queue manager for device %x:%x\n", 1143 node->adev->pdev->vendor, node->adev->pdev->device); 1144 1145 return err; 1146 } 1147 1148 /* This is called directly from KGD at ISR. */ 1149 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 1150 { 1151 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i; 1152 bool is_patched = false; 1153 unsigned long flags; 1154 struct kfd_node *node; 1155 1156 if (!kfd->init_complete) 1157 return; 1158 1159 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) { 1160 dev_err_once(kfd_device, "Ring entry too small\n"); 1161 return; 1162 } 1163 1164 for (i = 0; i < kfd->num_nodes; i++) { 1165 /* Race if another thread in b/w 1166 * kfd_cleanup_nodes and kfree(kfd), 1167 * when kfd->nodes[i] = NULL 1168 */ 1169 if (kfd->nodes[i]) 1170 node = kfd->nodes[i]; 1171 else 1172 return; 1173 1174 spin_lock_irqsave(&node->interrupt_lock, flags); 1175 1176 if (node->interrupts_active 1177 && interrupt_is_wanted(node, ih_ring_entry, 1178 patched_ihre, &is_patched) 1179 && enqueue_ih_ring_entry(node, 1180 is_patched ? patched_ihre : ih_ring_entry)) { 1181 queue_work(node->kfd->ih_wq, &node->interrupt_work); 1182 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1183 return; 1184 } 1185 spin_unlock_irqrestore(&node->interrupt_lock, flags); 1186 } 1187 1188 } 1189 1190 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) 1191 { 1192 struct kfd_process *p; 1193 int r; 1194 1195 /* Because we are called from arbitrary context (workqueue) as opposed 1196 * to process context, kfd_process could attempt to exit while we are 1197 * running so the lookup function increments the process ref count. 1198 */ 1199 p = kfd_lookup_process_by_mm(mm); 1200 if (!p) 1201 return -ESRCH; 1202 1203 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); 1204 r = kfd_process_evict_queues(p, trigger); 1205 1206 kfd_unref_process(p); 1207 return r; 1208 } 1209 1210 int kgd2kfd_resume_mm(struct mm_struct *mm) 1211 { 1212 struct kfd_process *p; 1213 int r; 1214 1215 /* Because we are called from arbitrary context (workqueue) as opposed 1216 * to process context, kfd_process could attempt to exit while we are 1217 * running so the lookup function increments the process ref count. 1218 */ 1219 p = kfd_lookup_process_by_mm(mm); 1220 if (!p) 1221 return -ESRCH; 1222 1223 r = kfd_process_restore_queues(p); 1224 1225 kfd_unref_process(p); 1226 return r; 1227 } 1228 1229 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will 1230 * prepare for safe eviction of KFD BOs that belong to the specified 1231 * process. 1232 * 1233 * @mm: mm_struct that identifies a group of KFD processes 1234 * @context_id: an id that identifies a specific KFD context in the above kfd process group 1235 * @fence: eviction fence attached to KFD process BOs 1236 * 1237 */ 1238 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 1239 u16 context_id, struct dma_fence *fence) 1240 { 1241 struct kfd_process *p; 1242 unsigned long active_time; 1243 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS); 1244 1245 if (!fence) 1246 return -EINVAL; 1247 1248 if (dma_fence_is_signaled(fence)) 1249 return 0; 1250 1251 p = kfd_lookup_process_by_id(mm, context_id); 1252 if (!p) 1253 return -ENODEV; 1254 1255 if (fence->seqno == p->last_eviction_seqno) 1256 goto out; 1257 1258 p->last_eviction_seqno = fence->seqno; 1259 1260 /* Avoid KFD process starvation. Wait for at least 1261 * PROCESS_ACTIVE_TIME_MS before evicting the process again 1262 */ 1263 active_time = get_jiffies_64() - p->last_restore_timestamp; 1264 if (delay_jiffies > active_time) 1265 delay_jiffies -= active_time; 1266 else 1267 delay_jiffies = 0; 1268 1269 /* During process initialization eviction_work.dwork is initialized 1270 * to kfd_evict_bo_worker 1271 */ 1272 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies", 1273 p->lead_thread->pid, delay_jiffies); 1274 schedule_delayed_work(&p->eviction_work, delay_jiffies); 1275 out: 1276 kfd_unref_process(p); 1277 return 0; 1278 } 1279 1280 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size, 1281 unsigned int chunk_size) 1282 { 1283 if (WARN_ON(buf_size < chunk_size)) 1284 return -EINVAL; 1285 if (WARN_ON(buf_size == 0)) 1286 return -EINVAL; 1287 if (WARN_ON(chunk_size == 0)) 1288 return -EINVAL; 1289 1290 kfd->gtt_sa_chunk_size = chunk_size; 1291 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size; 1292 1293 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks, 1294 GFP_KERNEL); 1295 if (!kfd->gtt_sa_bitmap) 1296 return -ENOMEM; 1297 1298 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n", 1299 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap); 1300 1301 mutex_init(&kfd->gtt_sa_lock); 1302 1303 return 0; 1304 } 1305 1306 static void kfd_gtt_sa_fini(struct kfd_dev *kfd) 1307 { 1308 mutex_destroy(&kfd->gtt_sa_lock); 1309 bitmap_free(kfd->gtt_sa_bitmap); 1310 } 1311 1312 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr, 1313 unsigned int bit_num, 1314 unsigned int chunk_size) 1315 { 1316 return start_addr + bit_num * chunk_size; 1317 } 1318 1319 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr, 1320 unsigned int bit_num, 1321 unsigned int chunk_size) 1322 { 1323 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size); 1324 } 1325 1326 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size, 1327 struct kfd_mem_obj **mem_obj) 1328 { 1329 unsigned int found, start_search, cur_size; 1330 struct kfd_dev *kfd = node->kfd; 1331 1332 if (size == 0) 1333 return -EINVAL; 1334 1335 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size) 1336 return -ENOMEM; 1337 1338 *mem_obj = kzalloc_obj(struct kfd_mem_obj); 1339 if (!(*mem_obj)) 1340 return -ENOMEM; 1341 1342 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size); 1343 1344 start_search = 0; 1345 1346 mutex_lock(&kfd->gtt_sa_lock); 1347 1348 kfd_gtt_restart_search: 1349 /* Find the first chunk that is free */ 1350 found = find_next_zero_bit(kfd->gtt_sa_bitmap, 1351 kfd->gtt_sa_num_of_chunks, 1352 start_search); 1353 1354 pr_debug("Found = %d\n", found); 1355 1356 /* If there wasn't any free chunk, bail out */ 1357 if (found == kfd->gtt_sa_num_of_chunks) 1358 goto kfd_gtt_no_free_chunk; 1359 1360 /* Update fields of mem_obj */ 1361 (*mem_obj)->range_start = found; 1362 (*mem_obj)->range_end = found; 1363 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr( 1364 kfd->gtt_start_gpu_addr, 1365 found, 1366 kfd->gtt_sa_chunk_size); 1367 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr( 1368 kfd->gtt_start_cpu_ptr, 1369 found, 1370 kfd->gtt_sa_chunk_size); 1371 1372 pr_debug("gpu_addr = %p, cpu_addr = %p\n", 1373 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr); 1374 1375 /* If we need only one chunk, mark it as allocated and get out */ 1376 if (size <= kfd->gtt_sa_chunk_size) { 1377 pr_debug("Single bit\n"); 1378 __set_bit(found, kfd->gtt_sa_bitmap); 1379 goto kfd_gtt_out; 1380 } 1381 1382 /* Otherwise, try to see if we have enough contiguous chunks */ 1383 cur_size = size - kfd->gtt_sa_chunk_size; 1384 do { 1385 (*mem_obj)->range_end = 1386 find_next_zero_bit(kfd->gtt_sa_bitmap, 1387 kfd->gtt_sa_num_of_chunks, ++found); 1388 /* 1389 * If next free chunk is not contiguous than we need to 1390 * restart our search from the last free chunk we found (which 1391 * wasn't contiguous to the previous ones 1392 */ 1393 if ((*mem_obj)->range_end != found) { 1394 start_search = found; 1395 goto kfd_gtt_restart_search; 1396 } 1397 1398 /* 1399 * If we reached end of buffer, bail out with error 1400 */ 1401 if (found == kfd->gtt_sa_num_of_chunks) 1402 goto kfd_gtt_no_free_chunk; 1403 1404 /* Check if we don't need another chunk */ 1405 if (cur_size <= kfd->gtt_sa_chunk_size) 1406 cur_size = 0; 1407 else 1408 cur_size -= kfd->gtt_sa_chunk_size; 1409 1410 } while (cur_size > 0); 1411 1412 pr_debug("range_start = %d, range_end = %d\n", 1413 (*mem_obj)->range_start, (*mem_obj)->range_end); 1414 1415 /* Mark the chunks as allocated */ 1416 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start, 1417 (*mem_obj)->range_end - (*mem_obj)->range_start + 1); 1418 1419 kfd_gtt_out: 1420 mutex_unlock(&kfd->gtt_sa_lock); 1421 return 0; 1422 1423 kfd_gtt_no_free_chunk: 1424 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj); 1425 mutex_unlock(&kfd->gtt_sa_lock); 1426 kfree(*mem_obj); 1427 return -ENOMEM; 1428 } 1429 1430 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj) 1431 { 1432 struct kfd_dev *kfd = node->kfd; 1433 1434 /* Act like kfree when trying to free a NULL object */ 1435 if (!mem_obj) 1436 return 0; 1437 1438 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n", 1439 mem_obj, mem_obj->range_start, mem_obj->range_end); 1440 1441 mutex_lock(&kfd->gtt_sa_lock); 1442 1443 /* Mark the chunks as free */ 1444 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start, 1445 mem_obj->range_end - mem_obj->range_start + 1); 1446 1447 mutex_unlock(&kfd->gtt_sa_lock); 1448 1449 kfree(mem_obj); 1450 return 0; 1451 } 1452 1453 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 1454 { 1455 /* 1456 * TODO: Currently update SRAM ECC flag for first node. 1457 * This needs to be updated later when we can 1458 * identify SRAM ECC error on other nodes also. 1459 */ 1460 if (kfd) 1461 atomic_inc(&kfd->nodes[0]->sram_ecc_flag); 1462 } 1463 1464 void kfd_inc_compute_active(struct kfd_node *node) 1465 { 1466 if (atomic_inc_return(&node->kfd->compute_profile) == 1) 1467 amdgpu_amdkfd_set_compute_idle(node->adev, false); 1468 } 1469 1470 void kfd_dec_compute_active(struct kfd_node *node) 1471 { 1472 int count = atomic_dec_return(&node->kfd->compute_profile); 1473 1474 if (count == 0) 1475 amdgpu_amdkfd_set_compute_idle(node->adev, true); 1476 WARN_ONCE(count < 0, "Compute profile ref. count error"); 1477 } 1478 1479 static bool kfd_compute_active(struct kfd_node *node) 1480 { 1481 if (atomic_read(&node->kfd->compute_profile)) 1482 return true; 1483 return false; 1484 } 1485 1486 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 1487 { 1488 /* 1489 * TODO: For now, raise the throttling event only on first node. 1490 * This will need to change after we are able to determine 1491 * which node raised the throttling event. 1492 */ 1493 if (kfd && kfd->init_complete) 1494 kfd_smi_event_update_thermal_throttling(kfd->nodes[0], 1495 throttle_bitmask); 1496 } 1497 1498 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and 1499 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA. 1500 * When the device has more than two engines, we reserve two for PCIe to enable 1501 * full-duplex and the rest are used as XGMI. 1502 */ 1503 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node) 1504 { 1505 /* If XGMI is not supported, all SDMA engines are PCIe */ 1506 if (!node->adev->gmc.xgmi.supported) 1507 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; 1508 1509 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); 1510 } 1511 1512 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node) 1513 { 1514 /* After reserved for PCIe, the rest of engines are XGMI */ 1515 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - 1516 kfd_get_num_sdma_engines(node); 1517 } 1518 1519 int kgd2kfd_check_and_lock_kfd(struct kfd_dev *kfd) 1520 { 1521 struct kfd_process *p; 1522 int r = 0, temp, idx; 1523 1524 mutex_lock(&kfd_processes_mutex); 1525 1526 /* kfd_processes_count is per kfd_dev, return -EBUSY without 1527 * further check 1528 */ 1529 if (!!atomic_read(&kfd->kfd_processes_count)) { 1530 pr_debug("process_wq_release not finished\n"); 1531 r = -EBUSY; 1532 goto out; 1533 } 1534 1535 if (hash_empty(kfd_processes_table) && !kfd_is_locked(kfd)) 1536 goto out; 1537 1538 /* fail under system reset/resume or kfd device is partition switching. */ 1539 if (kfd_is_locked(kfd)) { 1540 r = -EBUSY; 1541 goto out; 1542 } 1543 1544 /* 1545 * ensure all running processes are cgroup excluded from device before mode switch. 1546 * i.e. no pdd was created on the process socket. 1547 */ 1548 idx = srcu_read_lock(&kfd_processes_srcu); 1549 hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) { 1550 int i; 1551 1552 for (i = 0; i < p->n_pdds; i++) { 1553 if (p->pdds[i]->dev->kfd != kfd) 1554 continue; 1555 1556 r = -EBUSY; 1557 goto proc_check_unlock; 1558 } 1559 } 1560 1561 proc_check_unlock: 1562 srcu_read_unlock(&kfd_processes_srcu, idx); 1563 out: 1564 if (!r) 1565 ++kfd->kfd_dev_lock; 1566 mutex_unlock(&kfd_processes_mutex); 1567 1568 return r; 1569 } 1570 1571 /* unlock a kfd dev or kfd driver */ 1572 void kgd2kfd_unlock_kfd(struct kfd_dev *kfd) 1573 { 1574 mutex_lock(&kfd_processes_mutex); 1575 if (kfd) 1576 --kfd->kfd_dev_lock; 1577 else 1578 --kfd_locked; 1579 mutex_unlock(&kfd_processes_mutex); 1580 } 1581 1582 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id) 1583 { 1584 struct kfd_node *node; 1585 int ret; 1586 1587 if (!kfd->init_complete) 1588 return 0; 1589 1590 if (node_id >= kfd->num_nodes) { 1591 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1592 node_id, kfd->num_nodes - 1); 1593 return -EINVAL; 1594 } 1595 node = kfd->nodes[node_id]; 1596 1597 ret = node->dqm->ops.unhalt(node->dqm); 1598 if (ret) 1599 dev_err(kfd_device, "Error in starting scheduler\n"); 1600 1601 return ret; 1602 } 1603 1604 int kgd2kfd_start_sched_all_nodes(struct kfd_dev *kfd) 1605 { 1606 struct kfd_node *node; 1607 int i, r; 1608 1609 if (!kfd->init_complete) 1610 return 0; 1611 1612 for (i = 0; i < kfd->num_nodes; i++) { 1613 node = kfd->nodes[i]; 1614 r = node->dqm->ops.unhalt(node->dqm); 1615 if (r) { 1616 dev_err(kfd_device, "Error in starting scheduler\n"); 1617 return r; 1618 } 1619 } 1620 return 0; 1621 } 1622 1623 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) 1624 { 1625 struct kfd_node *node; 1626 1627 if (!kfd->init_complete) 1628 return 0; 1629 1630 if (node_id >= kfd->num_nodes) { 1631 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1632 node_id, kfd->num_nodes - 1); 1633 return -EINVAL; 1634 } 1635 1636 node = kfd->nodes[node_id]; 1637 return node->dqm->ops.halt(node->dqm); 1638 } 1639 1640 int kgd2kfd_stop_sched_all_nodes(struct kfd_dev *kfd) 1641 { 1642 struct kfd_node *node; 1643 int i, r; 1644 1645 if (!kfd->init_complete) 1646 return 0; 1647 1648 for (i = 0; i < kfd->num_nodes; i++) { 1649 node = kfd->nodes[i]; 1650 r = node->dqm->ops.halt(node->dqm); 1651 if (r) 1652 return r; 1653 } 1654 return 0; 1655 } 1656 1657 int amdgpu_amdkfd_stop_sched_all(struct amdgpu_device *adev) 1658 { 1659 if (!adev->kfd.init_complete) 1660 return 0; 1661 1662 return kgd2kfd_stop_sched_all_nodes(adev->kfd.dev); 1663 } 1664 1665 int amdgpu_amdkfd_start_sched_all(struct amdgpu_device *adev) 1666 { 1667 if (!adev->kfd.init_complete) 1668 return 0; 1669 1670 return kgd2kfd_start_sched_all_nodes(adev->kfd.dev); 1671 } 1672 1673 bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) 1674 { 1675 struct kfd_node *node; 1676 1677 if (!kfd->init_complete) 1678 return false; 1679 1680 if (node_id >= kfd->num_nodes) { 1681 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", 1682 node_id, kfd->num_nodes - 1); 1683 return false; 1684 } 1685 1686 node = kfd->nodes[node_id]; 1687 1688 return kfd_compute_active(node); 1689 } 1690 1691 /** 1692 * kgd2kfd_vmfault_fast_path() - KFD vm page fault interrupt handling fast path for gmc v9 1693 * @adev: amdgpu device 1694 * @entry: vm fault interrupt vector 1695 * @retry_fault: if this is retry fault 1696 * 1697 * retry fault - 1698 * with CAM enabled, adev primary ring 1699 * | gmc_v9_0_process_interrupt() 1700 * adev soft_ring 1701 * | gmc_v9_0_process_interrupt() worker failed to recover page fault 1702 * KFD node ih_fifo 1703 * | KFD interrupt_wq worker 1704 * kfd_signal_vm_fault_event 1705 * 1706 * without CAM, adev primary ring1 1707 * | gmc_v9_0_process_interrupt worker failed to recvoer page fault 1708 * KFD node ih_fifo 1709 * | KFD interrupt_wq worker 1710 * kfd_signal_vm_fault_event 1711 * 1712 * no-retry fault - 1713 * adev primary ring 1714 * | gmc_v9_0_process_interrupt() 1715 * KFD node ih_fifo 1716 * | KFD interrupt_wq worker 1717 * kfd_signal_vm_fault_event 1718 * 1719 * fast path - After kfd_signal_vm_fault_event, gmc_v9_0_process_interrupt drop the page fault 1720 * of same process, don't copy interrupt to KFD node ih_fifo. 1721 * With gdb debugger enabled, need convert the retry fault to no-retry fault for 1722 * debugger, cannot use the fast path. 1723 * 1724 * Return: 1725 * true - use the fast path to handle this fault 1726 * false - use normal path to handle it 1727 */ 1728 bool kgd2kfd_vmfault_fast_path(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry, 1729 bool retry_fault) 1730 { 1731 struct kfd_process *p; 1732 u32 cam_index; 1733 u32 src_data_idx; 1734 1735 src_data_idx = (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) ? 1736 3 : 2; 1737 1738 if (entry->ih == &adev->irq.ih_soft || entry->ih == &adev->irq.ih1) { 1739 p = kfd_lookup_process_by_pasid(entry->pasid, NULL); 1740 if (!p) 1741 return true; 1742 1743 if (p->gpu_page_fault && !p->debug_trap_enabled) { 1744 if (retry_fault && adev->irq.retry_cam_enabled) { 1745 cam_index = entry->src_data[src_data_idx] & 0x3ff; 1746 1747 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); 1748 } 1749 1750 kfd_unref_process(p); 1751 return true; 1752 } 1753 1754 /* 1755 * This is the first page fault, set flag and then signal user space 1756 */ 1757 p->gpu_page_fault = true; 1758 kfd_unref_process(p); 1759 } 1760 return false; 1761 } 1762 1763 /** kgd2kfd_teardown_processes - gracefully tear down existing 1764 * kfd processes that use adev 1765 * 1766 * @adev: amdgpu_device where kfd processes run on and will be 1767 * teardown 1768 * 1769 */ 1770 void kgd2kfd_teardown_processes(struct amdgpu_device *adev) 1771 { 1772 struct hlist_node *p_temp; 1773 struct kfd_process *p; 1774 struct kfd_node *dev; 1775 unsigned int temp; 1776 1777 mutex_lock(&kfd_processes_mutex); 1778 1779 if (hash_empty(kfd_processes_table)) { 1780 mutex_unlock(&kfd_processes_mutex); 1781 return; 1782 } 1783 1784 hash_for_each_safe(kfd_processes_table, temp, p_temp, p, kfd_processes) { 1785 for (int i = 0; i < p->n_pdds; i++) { 1786 dev = p->pdds[i]->dev; 1787 if (dev->adev == adev) 1788 kfd_signal_process_terminate_event(p); 1789 } 1790 } 1791 1792 mutex_unlock(&kfd_processes_mutex); 1793 1794 /* wait all kfd processes use adev terminate */ 1795 while (!!atomic_read(&adev->kfd.dev->kfd_processes_count)) 1796 cond_resched(); 1797 } 1798 1799 #if defined(CONFIG_DEBUG_FS) 1800 1801 /* This function will send a package to HIQ to hang the HWS 1802 * which will trigger a GPU reset and bring the HWS back to normal state 1803 */ 1804 int kfd_debugfs_hang_hws(struct kfd_node *dev) 1805 { 1806 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) { 1807 pr_err("HWS is not enabled"); 1808 return -EINVAL; 1809 } 1810 1811 if (dev->kfd->shared_resources.enable_mes) { 1812 dev_err(dev->adev->dev, "Inducing MES hang is not supported\n"); 1813 return -EINVAL; 1814 } 1815 1816 return dqm_debugfs_hang_hws(dev->dqm); 1817 } 1818 1819 #endif 1820