1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Sonny Jiang <sonny.jiang@amd.com>
23 */
24
25 #include <linux/firmware.h>
26
27 #include "amdgpu.h"
28 #include "amdgpu_uvd.h"
29 #include "sid.h"
30
31 #include "uvd/uvd_3_1_d.h"
32 #include "uvd/uvd_3_1_sh_mask.h"
33
34 #include "oss/oss_1_0_d.h"
35 #include "oss/oss_1_0_sh_mask.h"
36
37 /**
38 * uvd_v3_1_ring_get_rptr - get read pointer
39 *
40 * @ring: amdgpu_ring pointer
41 *
42 * Returns the current hardware read pointer
43 */
uvd_v3_1_ring_get_rptr(struct amdgpu_ring * ring)44 static uint64_t uvd_v3_1_ring_get_rptr(struct amdgpu_ring *ring)
45 {
46 struct amdgpu_device *adev = ring->adev;
47
48 return RREG32(mmUVD_RBC_RB_RPTR);
49 }
50
51 /**
52 * uvd_v3_1_ring_get_wptr - get write pointer
53 *
54 * @ring: amdgpu_ring pointer
55 *
56 * Returns the current hardware write pointer
57 */
uvd_v3_1_ring_get_wptr(struct amdgpu_ring * ring)58 static uint64_t uvd_v3_1_ring_get_wptr(struct amdgpu_ring *ring)
59 {
60 struct amdgpu_device *adev = ring->adev;
61
62 return RREG32(mmUVD_RBC_RB_WPTR);
63 }
64
65 /**
66 * uvd_v3_1_ring_set_wptr - set write pointer
67 *
68 * @ring: amdgpu_ring pointer
69 *
70 * Commits the write pointer to the hardware
71 */
uvd_v3_1_ring_set_wptr(struct amdgpu_ring * ring)72 static void uvd_v3_1_ring_set_wptr(struct amdgpu_ring *ring)
73 {
74 struct amdgpu_device *adev = ring->adev;
75
76 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
77 }
78
79 /**
80 * uvd_v3_1_ring_emit_ib - execute indirect buffer
81 *
82 * @ring: amdgpu_ring pointer
83 * @job: iob associated with the indirect buffer
84 * @ib: indirect buffer to execute
85 * @flags: flags associated with the indirect buffer
86 *
87 * Write ring commands to execute the indirect buffer
88 */
uvd_v3_1_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)89 static void uvd_v3_1_ring_emit_ib(struct amdgpu_ring *ring,
90 struct amdgpu_job *job,
91 struct amdgpu_ib *ib,
92 uint32_t flags)
93 {
94 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
95 amdgpu_ring_write(ring, ib->gpu_addr);
96 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0));
97 amdgpu_ring_write(ring, ib->length_dw);
98 }
99
100 /**
101 * uvd_v3_1_ring_emit_fence - emit a fence & trap command
102 *
103 * @ring: amdgpu_ring pointer
104 * @addr: address
105 * @seq: sequence number
106 * @flags: fence related flags
107 *
108 * Write a fence and a trap command to the ring.
109 */
uvd_v3_1_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)110 static void uvd_v3_1_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
111 unsigned flags)
112 {
113 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
114
115 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
116 amdgpu_ring_write(ring, seq);
117 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
118 amdgpu_ring_write(ring, addr & 0xffffffff);
119 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
120 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
121 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
122 amdgpu_ring_write(ring, 0);
123
124 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
125 amdgpu_ring_write(ring, 0);
126 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
127 amdgpu_ring_write(ring, 0);
128 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
129 amdgpu_ring_write(ring, 2);
130 }
131
132 /**
133 * uvd_v3_1_ring_test_ring - register write test
134 *
135 * @ring: amdgpu_ring pointer
136 *
137 * Test if we can successfully write to the context register
138 */
uvd_v3_1_ring_test_ring(struct amdgpu_ring * ring)139 static int uvd_v3_1_ring_test_ring(struct amdgpu_ring *ring)
140 {
141 struct amdgpu_device *adev = ring->adev;
142 uint32_t tmp = 0;
143 unsigned i;
144 int r;
145
146 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
147 r = amdgpu_ring_alloc(ring, 3);
148 if (r)
149 return r;
150
151 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
152 amdgpu_ring_write(ring, 0xDEADBEEF);
153 amdgpu_ring_commit(ring);
154 for (i = 0; i < adev->usec_timeout; i++) {
155 tmp = RREG32(mmUVD_CONTEXT_ID);
156 if (tmp == 0xDEADBEEF)
157 break;
158 udelay(1);
159 }
160
161 if (i >= adev->usec_timeout)
162 r = -ETIMEDOUT;
163
164 return r;
165 }
166
uvd_v3_1_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)167 static void uvd_v3_1_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
168 {
169 int i;
170
171 WARN_ON(ring->wptr % 2 || count % 2);
172
173 for (i = 0; i < count / 2; i++) {
174 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0));
175 amdgpu_ring_write(ring, 0);
176 }
177 }
178
179 static const struct amdgpu_ring_funcs uvd_v3_1_ring_funcs = {
180 .type = AMDGPU_RING_TYPE_UVD,
181 .align_mask = 0xf,
182 .support_64bit_ptrs = false,
183 .no_user_fence = true,
184 .get_rptr = uvd_v3_1_ring_get_rptr,
185 .get_wptr = uvd_v3_1_ring_get_wptr,
186 .set_wptr = uvd_v3_1_ring_set_wptr,
187 .parse_cs = amdgpu_uvd_ring_parse_cs,
188 .emit_frame_size =
189 14, /* uvd_v3_1_ring_emit_fence x1 no user fence */
190 .emit_ib_size = 4, /* uvd_v3_1_ring_emit_ib */
191 .emit_ib = uvd_v3_1_ring_emit_ib,
192 .emit_fence = uvd_v3_1_ring_emit_fence,
193 .test_ring = uvd_v3_1_ring_test_ring,
194 .test_ib = amdgpu_uvd_ring_test_ib,
195 .insert_nop = uvd_v3_1_ring_insert_nop,
196 .pad_ib = amdgpu_ring_generic_pad_ib,
197 .begin_use = amdgpu_uvd_ring_begin_use,
198 .end_use = amdgpu_uvd_ring_end_use,
199 };
200
uvd_v3_1_set_ring_funcs(struct amdgpu_device * adev)201 static void uvd_v3_1_set_ring_funcs(struct amdgpu_device *adev)
202 {
203 adev->uvd.inst->ring.funcs = &uvd_v3_1_ring_funcs;
204 }
205
uvd_v3_1_set_dcm(struct amdgpu_device * adev,bool sw_mode)206 static void uvd_v3_1_set_dcm(struct amdgpu_device *adev,
207 bool sw_mode)
208 {
209 u32 tmp, tmp2;
210
211 WREG32_FIELD(UVD_CGC_GATE, REGS, 0);
212
213 tmp = RREG32(mmUVD_CGC_CTRL);
214 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
215 tmp |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
216 (1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT) |
217 (4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT);
218
219 if (sw_mode) {
220 tmp &= ~0x7ffff800;
221 tmp2 = UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK |
222 UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK |
223 (7 << UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT);
224 } else {
225 tmp |= 0x7ffff800;
226 tmp2 = 0;
227 }
228
229 WREG32(mmUVD_CGC_CTRL, tmp);
230 WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2);
231 }
232
233 /**
234 * uvd_v3_1_mc_resume - memory controller programming
235 *
236 * @adev: amdgpu_device pointer
237 *
238 * Let the UVD memory controller know it's offsets
239 */
uvd_v3_1_mc_resume(struct amdgpu_device * adev)240 static void uvd_v3_1_mc_resume(struct amdgpu_device *adev)
241 {
242 uint64_t addr;
243 uint32_t size;
244
245 /* When the keyselect is already set, don't perturb it. */
246 if (RREG32(mmUVD_FW_START))
247 return;
248
249 /* program the VCPU memory controller bits 0-27 */
250 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
251 size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3;
252 WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
253 WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
254
255 addr += size;
256 size = AMDGPU_UVD_HEAP_SIZE >> 3;
257 WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
258 WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
259
260 addr += size;
261 size = (AMDGPU_UVD_STACK_SIZE +
262 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3;
263 WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
264 WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
265
266 /* bits 28-31 */
267 addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF;
268 WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
269
270 /* bits 32-39 */
271 addr = (adev->uvd.inst->gpu_addr >> 32) & 0xFF;
272 WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
273
274 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
275 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
276 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
277 }
278
279 /**
280 * uvd_v3_1_fw_validate - FW validation operation
281 *
282 * @adev: amdgpu_device pointer
283 *
284 * Initialate and check UVD validation.
285 */
uvd_v3_1_fw_validate(struct amdgpu_device * adev)286 static int uvd_v3_1_fw_validate(struct amdgpu_device *adev)
287 {
288 int i;
289 uint32_t keysel = adev->uvd.keyselect;
290
291 if (RREG32(mmUVD_FW_START) & UVD_FW_STATUS__PASS_MASK) {
292 dev_dbg(adev->dev, "UVD keyselect already set: 0x%x (on CPU: 0x%x)\n",
293 RREG32(mmUVD_FW_START), adev->uvd.keyselect);
294 return 0;
295 }
296
297 WREG32(mmUVD_FW_START, keysel);
298
299 for (i = 0; i < 10; ++i) {
300 mdelay(10);
301 if (RREG32(mmUVD_FW_STATUS) & UVD_FW_STATUS__DONE_MASK)
302 break;
303 }
304
305 if (i == 10)
306 return -ETIMEDOUT;
307
308 if (!(RREG32(mmUVD_FW_STATUS) & UVD_FW_STATUS__PASS_MASK))
309 return -EINVAL;
310
311 for (i = 0; i < 10; ++i) {
312 mdelay(10);
313 if (!(RREG32(mmUVD_FW_STATUS) & UVD_FW_STATUS__BUSY_MASK))
314 break;
315 }
316
317 if (i == 10)
318 return -ETIMEDOUT;
319
320 return 0;
321 }
322
323 /**
324 * uvd_v3_1_start - start UVD block
325 *
326 * @adev: amdgpu_device pointer
327 *
328 * Setup and start the UVD block
329 */
uvd_v3_1_start(struct amdgpu_device * adev)330 static int uvd_v3_1_start(struct amdgpu_device *adev)
331 {
332 struct amdgpu_ring *ring = &adev->uvd.inst->ring;
333 uint32_t rb_bufsz;
334 int i, j, r;
335 u32 tmp;
336 /* disable byte swapping */
337 u32 lmi_swap_cntl = 0;
338 u32 mp_swap_cntl = 0;
339
340 /* set uvd busy */
341 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2));
342
343 uvd_v3_1_set_dcm(adev, true);
344 WREG32(mmUVD_CGC_GATE, 0);
345
346 /* take UVD block out of reset */
347 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
348 mdelay(5);
349
350 /* enable VCPU clock */
351 WREG32(mmUVD_VCPU_CNTL, 1 << 9);
352
353 /* disable interrupt */
354 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1));
355
356 #ifdef __BIG_ENDIAN
357 /* swap (8 in 32) RB and IB */
358 lmi_swap_cntl = 0xa;
359 mp_swap_cntl = 0;
360 #endif
361 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
362 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
363
364 /* initialize UVD memory controller */
365 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
366 (1 << 21) | (1 << 9) | (1 << 20));
367
368 tmp = RREG32(mmUVD_MPC_CNTL);
369 WREG32(mmUVD_MPC_CNTL, tmp | 0x10);
370
371 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
372 WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
373 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
374 WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
375 WREG32(mmUVD_MPC_SET_ALU, 0);
376 WREG32(mmUVD_MPC_SET_MUX, 0x88);
377
378 tmp = RREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL);
379 WREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL, tmp & (~0x10));
380
381 /* enable UMC */
382 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8));
383
384 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
385
386 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
387
388 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
389
390 mdelay(10);
391
392 for (i = 0; i < 10; ++i) {
393 uint32_t status;
394 for (j = 0; j < 100; ++j) {
395 status = RREG32(mmUVD_STATUS);
396 if (status & 2)
397 break;
398 mdelay(10);
399 }
400 r = 0;
401 if (status & 2)
402 break;
403
404 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
405 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
406 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
407 mdelay(10);
408 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
409 mdelay(10);
410 r = -1;
411 }
412
413 if (r) {
414 DRM_ERROR("UVD not responding, giving up!!!\n");
415 return r;
416 }
417
418 /* enable interrupt */
419 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1));
420
421 WREG32_P(mmUVD_STATUS, 0, ~(1<<2));
422
423 /* force RBC into idle state */
424 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
425
426 /* Set the write pointer delay */
427 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
428
429 /* Program the 4GB memory segment for rptr and ring buffer */
430 WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
431 (0x7 << 16) | (0x1 << 31));
432
433 /* Initialize the ring buffer's read and write pointers */
434 WREG32(mmUVD_RBC_RB_RPTR, 0x0);
435
436 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR);
437 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
438
439 /* set the ring address */
440 WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);
441
442 /* Set ring buffer size */
443 rb_bufsz = order_base_2(ring->ring_size);
444 rb_bufsz = (0x1 << 8) | rb_bufsz;
445 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
446
447 return 0;
448 }
449
450 /**
451 * uvd_v3_1_stop - stop UVD block
452 *
453 * @adev: amdgpu_device pointer
454 *
455 * stop the UVD block
456 */
uvd_v3_1_stop(struct amdgpu_device * adev)457 static void uvd_v3_1_stop(struct amdgpu_device *adev)
458 {
459 uint32_t i, j;
460 uint32_t status;
461
462 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
463
464 for (i = 0; i < 10; ++i) {
465 for (j = 0; j < 100; ++j) {
466 status = RREG32(mmUVD_STATUS);
467 if (status & 2)
468 break;
469 mdelay(1);
470 }
471 if (status & 2)
472 break;
473 }
474
475 for (i = 0; i < 10; ++i) {
476 for (j = 0; j < 100; ++j) {
477 status = RREG32(mmUVD_LMI_STATUS);
478 if (status & 0xf)
479 break;
480 mdelay(1);
481 }
482 if (status & 0xf)
483 break;
484 }
485
486 /* Stall UMC and register bus before resetting VCPU */
487 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
488
489 for (i = 0; i < 10; ++i) {
490 for (j = 0; j < 100; ++j) {
491 status = RREG32(mmUVD_LMI_STATUS);
492 if (status & 0x240)
493 break;
494 mdelay(1);
495 }
496 if (status & 0x240)
497 break;
498 }
499
500 WREG32_P(0x3D49, 0, ~(1 << 2));
501
502 WREG32_P(mmUVD_VCPU_CNTL, 0, ~(1 << 9));
503
504 /* put LMI, VCPU, RBC etc... into reset */
505 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
506 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
507 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
508
509 WREG32(mmUVD_STATUS, 0);
510
511 uvd_v3_1_set_dcm(adev, false);
512 }
513
uvd_v3_1_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)514 static int uvd_v3_1_set_interrupt_state(struct amdgpu_device *adev,
515 struct amdgpu_irq_src *source,
516 unsigned type,
517 enum amdgpu_interrupt_state state)
518 {
519 return 0;
520 }
521
uvd_v3_1_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)522 static int uvd_v3_1_process_interrupt(struct amdgpu_device *adev,
523 struct amdgpu_irq_src *source,
524 struct amdgpu_iv_entry *entry)
525 {
526 DRM_DEBUG("IH: UVD TRAP\n");
527 amdgpu_fence_process(&adev->uvd.inst->ring);
528 return 0;
529 }
530
531
532 static const struct amdgpu_irq_src_funcs uvd_v3_1_irq_funcs = {
533 .set = uvd_v3_1_set_interrupt_state,
534 .process = uvd_v3_1_process_interrupt,
535 };
536
uvd_v3_1_set_irq_funcs(struct amdgpu_device * adev)537 static void uvd_v3_1_set_irq_funcs(struct amdgpu_device *adev)
538 {
539 adev->uvd.inst->irq.num_types = 1;
540 adev->uvd.inst->irq.funcs = &uvd_v3_1_irq_funcs;
541 }
542
543
uvd_v3_1_early_init(struct amdgpu_ip_block * ip_block)544 static int uvd_v3_1_early_init(struct amdgpu_ip_block *ip_block)
545 {
546 struct amdgpu_device *adev = ip_block->adev;
547 adev->uvd.num_uvd_inst = 1;
548
549 uvd_v3_1_set_ring_funcs(adev);
550 uvd_v3_1_set_irq_funcs(adev);
551
552 return 0;
553 }
554
uvd_v3_1_sw_init(struct amdgpu_ip_block * ip_block)555 static int uvd_v3_1_sw_init(struct amdgpu_ip_block *ip_block)
556 {
557 struct amdgpu_ring *ring;
558 struct amdgpu_device *adev = ip_block->adev;
559 int r;
560 void *ptr;
561 uint32_t ucode_len;
562
563 /* UVD TRAP */
564 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
565 if (r)
566 return r;
567
568 r = amdgpu_uvd_sw_init(adev);
569 if (r)
570 return r;
571
572 ring = &adev->uvd.inst->ring;
573 sprintf(ring->name, "uvd");
574 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0,
575 AMDGPU_RING_PRIO_DEFAULT, NULL);
576 if (r)
577 return r;
578
579 r = amdgpu_uvd_resume(adev);
580 if (r)
581 return r;
582
583 /* Retrieval firmware validate key */
584 ptr = adev->uvd.inst[0].cpu_addr;
585 ptr += 192 + 16;
586 memcpy(&ucode_len, ptr, 4);
587 ptr += ucode_len;
588 memcpy(&adev->uvd.keyselect, ptr, 4);
589
590 return r;
591 }
592
uvd_v3_1_sw_fini(struct amdgpu_ip_block * ip_block)593 static int uvd_v3_1_sw_fini(struct amdgpu_ip_block *ip_block)
594 {
595 int r;
596 struct amdgpu_device *adev = ip_block->adev;
597
598 r = amdgpu_uvd_suspend(adev);
599 if (r)
600 return r;
601
602 return amdgpu_uvd_sw_fini(adev);
603 }
604
uvd_v3_1_enable_mgcg(struct amdgpu_device * adev,bool enable)605 static void uvd_v3_1_enable_mgcg(struct amdgpu_device *adev,
606 bool enable)
607 {
608 u32 orig, data;
609
610 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
611 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
612 data |= 0x3fff;
613 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
614
615 orig = data = RREG32(mmUVD_CGC_CTRL);
616 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
617 if (orig != data)
618 WREG32(mmUVD_CGC_CTRL, data);
619 } else {
620 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
621 data &= ~0x3fff;
622 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
623
624 orig = data = RREG32(mmUVD_CGC_CTRL);
625 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
626 if (orig != data)
627 WREG32(mmUVD_CGC_CTRL, data);
628 }
629 }
630
631 /**
632 * uvd_v3_1_hw_init - start and test UVD block
633 *
634 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
635 *
636 * Initialize the hardware, boot up the VCPU and do some testing.
637 *
638 * On SI, the UVD is meant to be used in a specific power state,
639 * or alternatively the driver can manually enable its clock.
640 * In amdgpu we use the dedicated UVD power state when DPM is enabled.
641 * Calling amdgpu_dpm_enable_uvd makes DPM select the UVD power state
642 * for the SMU and afterwards enables the UVD clock.
643 * This is automatically done by amdgpu_uvd_ring_begin_use when work
644 * is submitted to the UVD ring. Here, we have to call it manually
645 * in order to power up UVD before firmware validation.
646 *
647 * Note that we must not disable the UVD clock here, as that would
648 * cause the ring test to fail. However, UVD is powered off
649 * automatically after the ring test: amdgpu_uvd_ring_end_use calls
650 * the UVD idle work handler which will disable the UVD clock when
651 * all fences are signalled.
652 */
uvd_v3_1_hw_init(struct amdgpu_ip_block * ip_block)653 static int uvd_v3_1_hw_init(struct amdgpu_ip_block *ip_block)
654 {
655 struct amdgpu_device *adev = ip_block->adev;
656 struct amdgpu_ring *ring = &adev->uvd.inst->ring;
657 uint32_t tmp;
658 int r;
659
660 uvd_v3_1_mc_resume(adev);
661 uvd_v3_1_enable_mgcg(adev, true);
662
663 /* Make sure UVD is powered during FW validation.
664 * It's going to be automatically powered off after the ring test.
665 */
666 if (adev->pm.dpm_enabled)
667 amdgpu_dpm_enable_uvd(adev, true);
668 else
669 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
670
671 r = uvd_v3_1_fw_validate(adev);
672 if (r) {
673 drm_err(adev_to_drm(adev), "UVD Firmware validate fail (%d).\n", r);
674 return r;
675 }
676
677 uvd_v3_1_start(adev);
678
679 r = amdgpu_ring_test_helper(ring);
680 if (r) {
681 drm_err(adev_to_drm(adev), "UVD ring test failed (%d).\n", r);
682 goto done;
683 }
684
685 r = amdgpu_ring_alloc(ring, 10);
686 if (r) {
687 drm_err(adev_to_drm(adev), "ring alloc failed (%d).\n", r);
688 goto done;
689 }
690
691 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
692 amdgpu_ring_write(ring, tmp);
693 amdgpu_ring_write(ring, 0xFFFFF);
694
695 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
696 amdgpu_ring_write(ring, tmp);
697 amdgpu_ring_write(ring, 0xFFFFF);
698
699 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
700 amdgpu_ring_write(ring, tmp);
701 amdgpu_ring_write(ring, 0xFFFFF);
702
703 /* Clear timeout status bits */
704 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
705 amdgpu_ring_write(ring, 0x8);
706
707 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
708 amdgpu_ring_write(ring, 3);
709
710 amdgpu_ring_commit(ring);
711
712 done:
713 if (!r)
714 drm_info(adev_to_drm(adev), "UVD initialized successfully.\n");
715
716 return r;
717 }
718
719 /**
720 * uvd_v3_1_hw_fini - stop the hardware block
721 *
722 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
723 *
724 * Stop the UVD block, mark ring as not ready any more
725 */
uvd_v3_1_hw_fini(struct amdgpu_ip_block * ip_block)726 static int uvd_v3_1_hw_fini(struct amdgpu_ip_block *ip_block)
727 {
728 struct amdgpu_device *adev = ip_block->adev;
729
730 cancel_delayed_work_sync(&adev->uvd.idle_work);
731
732 if (RREG32(mmUVD_STATUS) != 0)
733 uvd_v3_1_stop(adev);
734
735 return 0;
736 }
737
uvd_v3_1_prepare_suspend(struct amdgpu_ip_block * ip_block)738 static int uvd_v3_1_prepare_suspend(struct amdgpu_ip_block *ip_block)
739 {
740 struct amdgpu_device *adev = ip_block->adev;
741
742 return amdgpu_uvd_prepare_suspend(adev);
743 }
744
uvd_v3_1_suspend(struct amdgpu_ip_block * ip_block)745 static int uvd_v3_1_suspend(struct amdgpu_ip_block *ip_block)
746 {
747 int r;
748 struct amdgpu_device *adev = ip_block->adev;
749
750 /*
751 * Proper cleanups before halting the HW engine:
752 * - cancel the delayed idle work
753 * - enable powergating
754 * - enable clockgating
755 * - disable dpm
756 *
757 * TODO: to align with the VCN implementation, move the
758 * jobs for clockgating/powergating/dpm setting to
759 * ->set_powergating_state().
760 */
761 cancel_delayed_work_sync(&adev->uvd.idle_work);
762
763 if (adev->pm.dpm_enabled) {
764 amdgpu_dpm_enable_uvd(adev, false);
765 } else {
766 amdgpu_asic_set_uvd_clocks(adev, 0, 0);
767 /* shutdown the UVD block */
768 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
769 AMD_PG_STATE_GATE);
770 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
771 AMD_CG_STATE_GATE);
772 }
773
774 r = uvd_v3_1_hw_fini(ip_block);
775 if (r)
776 return r;
777
778 return amdgpu_uvd_suspend(adev);
779 }
780
uvd_v3_1_resume(struct amdgpu_ip_block * ip_block)781 static int uvd_v3_1_resume(struct amdgpu_ip_block *ip_block)
782 {
783 int r;
784
785 r = amdgpu_uvd_resume(ip_block->adev);
786 if (r)
787 return r;
788
789 return uvd_v3_1_hw_init(ip_block);
790 }
791
uvd_v3_1_is_idle(struct amdgpu_ip_block * ip_block)792 static bool uvd_v3_1_is_idle(struct amdgpu_ip_block *ip_block)
793 {
794 struct amdgpu_device *adev = ip_block->adev;
795
796 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
797 }
798
uvd_v3_1_wait_for_idle(struct amdgpu_ip_block * ip_block)799 static int uvd_v3_1_wait_for_idle(struct amdgpu_ip_block *ip_block)
800 {
801 unsigned i;
802 struct amdgpu_device *adev = ip_block->adev;
803
804 for (i = 0; i < adev->usec_timeout; i++) {
805 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK))
806 return 0;
807 }
808 return -ETIMEDOUT;
809 }
810
uvd_v3_1_soft_reset(struct amdgpu_ip_block * ip_block)811 static int uvd_v3_1_soft_reset(struct amdgpu_ip_block *ip_block)
812 {
813 struct amdgpu_device *adev = ip_block->adev;
814
815 uvd_v3_1_stop(adev);
816
817 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK,
818 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK);
819 mdelay(5);
820
821 return uvd_v3_1_start(adev);
822 }
823
uvd_v3_1_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)824 static int uvd_v3_1_set_clockgating_state(struct amdgpu_ip_block *ip_block,
825 enum amd_clockgating_state state)
826 {
827 return 0;
828 }
829
uvd_v3_1_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)830 static int uvd_v3_1_set_powergating_state(struct amdgpu_ip_block *ip_block,
831 enum amd_powergating_state state)
832 {
833 return 0;
834 }
835
836 static const struct amd_ip_funcs uvd_v3_1_ip_funcs = {
837 .name = "uvd_v3_1",
838 .early_init = uvd_v3_1_early_init,
839 .sw_init = uvd_v3_1_sw_init,
840 .sw_fini = uvd_v3_1_sw_fini,
841 .hw_init = uvd_v3_1_hw_init,
842 .hw_fini = uvd_v3_1_hw_fini,
843 .prepare_suspend = uvd_v3_1_prepare_suspend,
844 .suspend = uvd_v3_1_suspend,
845 .resume = uvd_v3_1_resume,
846 .is_idle = uvd_v3_1_is_idle,
847 .wait_for_idle = uvd_v3_1_wait_for_idle,
848 .soft_reset = uvd_v3_1_soft_reset,
849 .set_clockgating_state = uvd_v3_1_set_clockgating_state,
850 .set_powergating_state = uvd_v3_1_set_powergating_state,
851 };
852
853 const struct amdgpu_ip_block_version uvd_v3_1_ip_block = {
854 .type = AMD_IP_BLOCK_TYPE_UVD,
855 .major = 3,
856 .minor = 1,
857 .rev = 0,
858 .funcs = &uvd_v3_1_ip_funcs,
859 };
860