1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef _XE_HW_ENGINE_TYPES_H_ 7 #define _XE_HW_ENGINE_TYPES_H_ 8 9 #include "xe_force_wake_types.h" 10 #include "xe_lrc_types.h" 11 #include "xe_reg_sr_types.h" 12 13 /* See "Engine ID Definition" struct in the Icelake PRM */ 14 enum xe_engine_class { 15 XE_ENGINE_CLASS_RENDER = 0, 16 XE_ENGINE_CLASS_VIDEO_DECODE = 1, 17 XE_ENGINE_CLASS_VIDEO_ENHANCE = 2, 18 XE_ENGINE_CLASS_COPY = 3, 19 XE_ENGINE_CLASS_OTHER = 4, 20 XE_ENGINE_CLASS_COMPUTE = 5, 21 XE_ENGINE_CLASS_MAX = 6, 22 }; 23 24 enum xe_hw_engine_id { 25 XE_HW_ENGINE_RCS0, 26 #define XE_HW_ENGINE_RCS_MASK GENMASK_ULL(XE_HW_ENGINE_RCS0, XE_HW_ENGINE_RCS0) 27 XE_HW_ENGINE_BCS0, 28 XE_HW_ENGINE_BCS1, 29 XE_HW_ENGINE_BCS2, 30 XE_HW_ENGINE_BCS3, 31 XE_HW_ENGINE_BCS4, 32 XE_HW_ENGINE_BCS5, 33 XE_HW_ENGINE_BCS6, 34 XE_HW_ENGINE_BCS7, 35 XE_HW_ENGINE_BCS8, 36 #define XE_HW_ENGINE_BCS_MASK GENMASK_ULL(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS0) 37 XE_HW_ENGINE_VCS0, 38 XE_HW_ENGINE_VCS1, 39 XE_HW_ENGINE_VCS2, 40 XE_HW_ENGINE_VCS3, 41 XE_HW_ENGINE_VCS4, 42 XE_HW_ENGINE_VCS5, 43 XE_HW_ENGINE_VCS6, 44 XE_HW_ENGINE_VCS7, 45 #define XE_HW_ENGINE_VCS_MASK GENMASK_ULL(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) 46 XE_HW_ENGINE_VECS0, 47 XE_HW_ENGINE_VECS1, 48 XE_HW_ENGINE_VECS2, 49 XE_HW_ENGINE_VECS3, 50 #define XE_HW_ENGINE_VECS_MASK GENMASK_ULL(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) 51 XE_HW_ENGINE_CCS0, 52 XE_HW_ENGINE_CCS1, 53 XE_HW_ENGINE_CCS2, 54 XE_HW_ENGINE_CCS3, 55 #define XE_HW_ENGINE_CCS_MASK GENMASK_ULL(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0) 56 XE_HW_ENGINE_GSCCS0, 57 #define XE_HW_ENGINE_GSCCS_MASK GENMASK_ULL(XE_HW_ENGINE_GSCCS0, XE_HW_ENGINE_GSCCS0) 58 XE_NUM_HW_ENGINES, 59 }; 60 61 /* FIXME: s/XE_HW_ENGINE_MAX_INSTANCE/XE_HW_ENGINE_MAX_COUNT */ 62 #define XE_HW_ENGINE_MAX_INSTANCE 9 63 64 struct xe_bo; 65 struct xe_execlist_port; 66 struct xe_gt; 67 68 /** 69 * struct xe_hw_engine_class_intf - per hw engine class struct interface 70 * 71 * Contains all the hw engine properties per engine class. 72 * 73 * @sched_props: scheduling properties 74 * @defaults: default scheduling properties 75 */ 76 struct xe_hw_engine_class_intf { 77 /** 78 * @sched_props: scheduling properties 79 * @defaults: default scheduling properties 80 */ 81 struct { 82 /** @sched_props.job_timeout_ms: Set job timeout in ms for engine */ 83 u32 job_timeout_ms; 84 /** @sched_props.job_timeout_min: Min job timeout in ms for engine */ 85 u32 job_timeout_min; 86 /** @sched_props.job_timeout_max: Max job timeout in ms for engine */ 87 u32 job_timeout_max; 88 /** @sched_props.timeslice_us: timeslice period in micro-seconds */ 89 u32 timeslice_us; 90 /** @sched_props.timeslice_min: min timeslice period in micro-seconds */ 91 u32 timeslice_min; 92 /** @sched_props.timeslice_max: max timeslice period in micro-seconds */ 93 u32 timeslice_max; 94 /** @sched_props.preempt_timeout_us: preemption timeout in micro-seconds */ 95 u32 preempt_timeout_us; 96 /** @sched_props.preempt_timeout_min: min preemption timeout in micro-seconds */ 97 u32 preempt_timeout_min; 98 /** @sched_props.preempt_timeout_max: max preemption timeout in micro-seconds */ 99 u32 preempt_timeout_max; 100 } sched_props, defaults; 101 }; 102 103 /** 104 * struct xe_hw_engine - Hardware engine 105 * 106 * Contains all the hardware engine state for physical instances. 107 */ 108 struct xe_hw_engine { 109 /** @gt: GT structure this hw engine belongs to */ 110 struct xe_gt *gt; 111 /** @name: name of this hw engine */ 112 const char *name; 113 /** @class: class of this hw engine */ 114 enum xe_engine_class class; 115 /** @instance: physical instance of this hw engine */ 116 u16 instance; 117 /** 118 * @logical_instance: logical instance of this hw engine. 119 * 120 * Note: For GuC usage, always use xe_hwe_guc_logical_instance(). 121 * For GuC usage, we should no longer use the raw logical instance. 122 */ 123 u16 logical_instance; 124 /** @irq_offset: IRQ offset of this hw engine */ 125 u16 irq_offset; 126 /** @irq_page: MEMIRQ page used by this HW engine */ 127 u16 irq_page; 128 /** @mmio_base: MMIO base address of this hw engine*/ 129 u32 mmio_base; 130 /** 131 * @reg_sr: table with registers to be restored on GT init/resume/reset 132 */ 133 struct xe_reg_sr reg_sr; 134 /** 135 * @reg_whitelist: table with registers to be whitelisted 136 */ 137 struct xe_reg_sr reg_whitelist; 138 /** 139 * @oa_whitelist: oa registers to be whitelisted 140 */ 141 struct xe_reg_sr oa_whitelist; 142 /** 143 * @oa_sr: oa nonpriv whitelist registers, changed on oa stream open/close 144 */ 145 struct xe_reg_sr oa_sr; 146 /** 147 * @reg_lrc: LRC workaround registers 148 */ 149 struct xe_reg_sr reg_lrc; 150 /** @domain: force wake domain of this hw engine */ 151 enum xe_force_wake_domains domain; 152 /** @hwsp: hardware status page buffer object */ 153 struct xe_bo *hwsp; 154 /** @exl_port: execlists port */ 155 struct xe_execlist_port *exl_port; 156 /** @fence_irq: fence IRQ to run when a hw engine IRQ is received */ 157 struct xe_hw_fence_irq *fence_irq; 158 /** @irq_handler: IRQ handler to run when hw engine IRQ is received */ 159 void (*irq_handler)(struct xe_hw_engine *hwe, u16 intr_vec); 160 /** @engine_id: id for this hw engine */ 161 enum xe_hw_engine_id engine_id; 162 /** @eclass: pointer to per hw engine class interface */ 163 struct xe_hw_engine_class_intf *eclass; 164 /** @oa_unit: oa unit for this hw engine */ 165 struct xe_oa_unit *oa_unit; 166 /** @hw_engine_group: the group of hw engines this one belongs to */ 167 struct xe_hw_engine_group *hw_engine_group; 168 }; 169 170 enum xe_hw_engine_snapshot_source_id { 171 XE_ENGINE_CAPTURE_SOURCE_MANUAL, 172 XE_ENGINE_CAPTURE_SOURCE_GUC 173 }; 174 175 /** 176 * struct xe_hw_engine_snapshot - Hardware engine snapshot 177 * 178 * Contains the snapshot of useful hardware engine info and registers. 179 */ 180 struct xe_hw_engine_snapshot { 181 /** @name: name of the hw engine */ 182 char *name; 183 /** @hwe: hw engine */ 184 struct xe_hw_engine *hwe; 185 /** @logical_instance: logical instance of this hw engine */ 186 u16 logical_instance; 187 /** @forcewake: Force Wake information snapshot */ 188 struct { 189 /** @forcewake.domain: force wake domain of this hw engine */ 190 enum xe_force_wake_domains domain; 191 /** @forcewake.ref: Forcewake ref for the above domain */ 192 int ref; 193 } forcewake; 194 /** @mmio_base: MMIO base address of this hw engine*/ 195 u32 mmio_base; 196 /** @kernel_reserved: Engine reserved, can't be used by userspace */ 197 bool kernel_reserved; 198 }; 199 200 #endif 201