1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2025 SpacemiT Technology Co. Ltd
4 */
5
6 #include <linux/array_size.h>
7 #include <linux/clk-provider.h>
8 #include <linux/module.h>
9 #include <soc/spacemit/k3-syscon.h>
10
11 #include "ccu_common.h"
12 #include "ccu_pll.h"
13 #include "ccu_mix.h"
14 #include "ccu_ddn.h"
15
16 #include <dt-bindings/clock/spacemit,k3-clocks.h>
17
18 /* APBS clocks start, APBS region contains and only contains all PLL clocks */
19
20 /*
21 * PLL{1,2} must run at fixed frequencies to provide clocks in correct rates for
22 * peripherals.
23 */
24 static const struct ccu_pll_rate_tbl pll1_rate_tbl[] = {
25 CCU_PLLA_RATE(2457600000UL, 0x0b330ccc, 0x0000cd00, 0xa0558989),
26 };
27
28 static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = {
29 CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c),
30 };
31
32 static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = {
33 CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787),
34 };
35
36 static const struct ccu_pll_rate_tbl pll4_rate_tbl[] = {
37 CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787),
38 };
39
40 static const struct ccu_pll_rate_tbl pll5_rate_tbl[] = {
41 CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
42 };
43
44 static const struct ccu_pll_rate_tbl pll6_rate_tbl[] = {
45 CCU_PLLA_RATE(3200000000UL, 0x0b422aaa, 0x0000ab00, 0xa0558e8e),
46 };
47
48 static const struct ccu_pll_rate_tbl pll7_rate_tbl[] = {
49 CCU_PLLA_RATE(2800000000UL, 0x0b3a1555, 0x00005500, 0xa0558b8b),
50 };
51
52 static const struct ccu_pll_rate_tbl pll8_rate_tbl[] = {
53 CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686),
54 };
55
56 CCU_PLLA_DEFINE(pll1, pll1_rate_tbl, APBS_PLL1_SWCR1, APBS_PLL1_SWCR2, APBS_PLL1_SWCR3,
57 MPMU_POSR, POSR_PLL1_LOCK, CLK_SET_RATE_GATE);
58 CCU_PLLA_DEFINE(pll2, pll2_rate_tbl, APBS_PLL2_SWCR1, APBS_PLL2_SWCR2, APBS_PLL2_SWCR3,
59 MPMU_POSR, POSR_PLL2_LOCK, CLK_SET_RATE_GATE);
60 CCU_PLLA_DEFINE(pll3, pll3_rate_tbl, APBS_PLL3_SWCR1, APBS_PLL3_SWCR2, APBS_PLL3_SWCR3,
61 MPMU_POSR, POSR_PLL3_LOCK, CLK_SET_RATE_GATE);
62 CCU_PLLA_DEFINE(pll4, pll4_rate_tbl, APBS_PLL4_SWCR1, APBS_PLL4_SWCR2, APBS_PLL4_SWCR3,
63 MPMU_POSR, POSR_PLL4_LOCK, CLK_SET_RATE_GATE);
64 CCU_PLLA_DEFINE(pll5, pll5_rate_tbl, APBS_PLL5_SWCR1, APBS_PLL5_SWCR2, APBS_PLL5_SWCR3,
65 MPMU_POSR, POSR_PLL5_LOCK, CLK_SET_RATE_GATE);
66 CCU_PLLA_DEFINE(pll6, pll6_rate_tbl, APBS_PLL6_SWCR1, APBS_PLL6_SWCR2, APBS_PLL6_SWCR3,
67 MPMU_POSR, POSR_PLL6_LOCK, CLK_SET_RATE_GATE);
68 CCU_PLLA_DEFINE(pll7, pll7_rate_tbl, APBS_PLL7_SWCR1, APBS_PLL7_SWCR2, APBS_PLL7_SWCR3,
69 MPMU_POSR, POSR_PLL7_LOCK, CLK_SET_RATE_GATE);
70 CCU_PLLA_DEFINE(pll8, pll8_rate_tbl, APBS_PLL8_SWCR1, APBS_PLL8_SWCR2, APBS_PLL8_SWCR3,
71 MPMU_POSR, POSR_PLL8_LOCK, CLK_SET_RATE_GATE);
72
73 CCU_FACTOR_GATE_DEFINE(pll1_d2, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(1), 2, 1);
74 CCU_FACTOR_GATE_DEFINE(pll1_d3, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(2), 3, 1);
75 CCU_FACTOR_GATE_DEFINE(pll1_d4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(3), 4, 1);
76 CCU_FACTOR_GATE_DEFINE(pll1_d5, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(4), 5, 1);
77 CCU_FACTOR_GATE_DEFINE(pll1_d6, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(5), 6, 1);
78 CCU_FACTOR_GATE_DEFINE(pll1_d7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(6), 7, 1);
79 CCU_FACTOR_GATE_FLAGS_DEFINE(pll1_d8, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(7), 8, 1,
80 CLK_IS_CRITICAL);
81 CCU_DIV_GATE_DEFINE(pll1_dx, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, 23, 5, BIT(22), 0);
82 CCU_FACTOR_GATE_DEFINE(pll1_d64_38p4, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(31), 64, 1);
83 CCU_FACTOR_GATE_DEFINE(pll1_aud_245p7, CCU_PARENT_HW(pll1), APBS_PLL1_SWCR2, BIT(21), 10, 1);
84 CCU_FACTOR_DEFINE(pll1_aud_24p5, CCU_PARENT_HW(pll1_aud_245p7), 10, 1);
85
86 CCU_FACTOR_GATE_DEFINE(pll2_d1, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(0), 1, 1);
87 CCU_FACTOR_GATE_DEFINE(pll2_d2, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(1), 2, 1);
88 CCU_FACTOR_GATE_DEFINE(pll2_d3, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(2), 3, 1);
89 CCU_FACTOR_GATE_DEFINE(pll2_d4, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(3), 4, 1);
90 CCU_FACTOR_GATE_DEFINE(pll2_d5, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(4), 5, 1);
91 CCU_FACTOR_GATE_DEFINE(pll2_d6, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(5), 6, 1);
92 CCU_FACTOR_GATE_DEFINE(pll2_d7, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(6), 7, 1);
93 CCU_FACTOR_GATE_DEFINE(pll2_d8, CCU_PARENT_HW(pll2), APBS_PLL2_SWCR2, BIT(7), 8, 1);
94 CCU_FACTOR_DEFINE(pll2_66, CCU_PARENT_HW(pll2_d5), 9, 1);
95 CCU_FACTOR_DEFINE(pll2_33, CCU_PARENT_HW(pll2_66), 2, 1);
96 CCU_FACTOR_DEFINE(pll2_50, CCU_PARENT_HW(pll2_d5), 12, 1);
97 CCU_FACTOR_DEFINE(pll2_25, CCU_PARENT_HW(pll2_50), 2, 1);
98 CCU_FACTOR_DEFINE(pll2_20, CCU_PARENT_HW(pll2_d5), 30, 1);
99 CCU_FACTOR_DEFINE(pll2_d24_125, CCU_PARENT_HW(pll2_d3), 8, 1);
100 CCU_FACTOR_DEFINE(pll2_d120_25, CCU_PARENT_HW(pll2_d3), 40, 1);
101
102 CCU_FACTOR_GATE_DEFINE(pll3_d1, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(0), 1, 1);
103 CCU_FACTOR_GATE_DEFINE(pll3_d2, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(1), 2, 1);
104 CCU_FACTOR_GATE_DEFINE(pll3_d3, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(2), 3, 1);
105 CCU_FACTOR_GATE_DEFINE(pll3_d4, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(3), 4, 1);
106 CCU_FACTOR_GATE_DEFINE(pll3_d5, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(4), 5, 1);
107 CCU_FACTOR_GATE_DEFINE(pll3_d6, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(5), 6, 1);
108 CCU_FACTOR_GATE_DEFINE(pll3_d7, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(6), 7, 1);
109 CCU_FACTOR_GATE_DEFINE(pll3_d8, CCU_PARENT_HW(pll3), APBS_PLL3_SWCR2, BIT(7), 8, 1);
110
111 CCU_FACTOR_GATE_DEFINE(pll4_d1, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(0), 1, 1);
112 CCU_FACTOR_GATE_DEFINE(pll4_d2, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(1), 2, 1);
113 CCU_FACTOR_GATE_DEFINE(pll4_d3, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(2), 3, 1);
114 CCU_FACTOR_GATE_DEFINE(pll4_d4, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(3), 4, 1);
115 CCU_FACTOR_GATE_DEFINE(pll4_d5, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(4), 5, 1);
116 CCU_FACTOR_GATE_DEFINE(pll4_d6, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(5), 6, 1);
117 CCU_FACTOR_GATE_DEFINE(pll4_d7, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(6), 7, 1);
118 CCU_FACTOR_GATE_DEFINE(pll4_d8, CCU_PARENT_HW(pll4), APBS_PLL4_SWCR2, BIT(7), 8, 1);
119
120 CCU_FACTOR_GATE_DEFINE(pll5_d1, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(0), 1, 1);
121 CCU_FACTOR_GATE_DEFINE(pll5_d2, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(1), 2, 1);
122 CCU_FACTOR_GATE_DEFINE(pll5_d3, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(2), 3, 1);
123 CCU_FACTOR_GATE_DEFINE(pll5_d4, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(3), 4, 1);
124 CCU_FACTOR_GATE_DEFINE(pll5_d5, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(4), 5, 1);
125 CCU_FACTOR_GATE_DEFINE(pll5_d6, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(5), 6, 1);
126 CCU_FACTOR_GATE_DEFINE(pll5_d7, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(6), 7, 1);
127 CCU_FACTOR_GATE_DEFINE(pll5_d8, CCU_PARENT_HW(pll5), APBS_PLL5_SWCR2, BIT(7), 8, 1);
128
129 CCU_FACTOR_GATE_DEFINE(pll6_d1, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(0), 1, 1);
130 CCU_FACTOR_GATE_DEFINE(pll6_d2, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(1), 2, 1);
131 CCU_FACTOR_GATE_DEFINE(pll6_d3, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(2), 3, 1);
132 CCU_FACTOR_GATE_DEFINE(pll6_d4, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(3), 4, 1);
133 CCU_FACTOR_GATE_DEFINE(pll6_d5, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(4), 5, 1);
134 CCU_FACTOR_GATE_DEFINE(pll6_d6, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(5), 6, 1);
135 CCU_FACTOR_GATE_DEFINE(pll6_d7, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(6), 7, 1);
136 CCU_FACTOR_GATE_DEFINE(pll6_d8, CCU_PARENT_HW(pll6), APBS_PLL6_SWCR2, BIT(7), 8, 1);
137 CCU_FACTOR_DEFINE(pll6_80, CCU_PARENT_HW(pll6_d5), 8, 1);
138 CCU_FACTOR_DEFINE(pll6_40, CCU_PARENT_HW(pll6_d5), 16, 1);
139 CCU_FACTOR_DEFINE(pll6_20, CCU_PARENT_HW(pll6_d5), 32, 1);
140
141 CCU_FACTOR_GATE_DEFINE(pll7_d1, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(0), 1, 1);
142 CCU_FACTOR_GATE_DEFINE(pll7_d2, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(1), 2, 1);
143 CCU_FACTOR_GATE_DEFINE(pll7_d3, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(2), 3, 1);
144 CCU_FACTOR_GATE_DEFINE(pll7_d4, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(3), 4, 1);
145 CCU_FACTOR_GATE_DEFINE(pll7_d5, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(4), 5, 1);
146 CCU_FACTOR_GATE_DEFINE(pll7_d6, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(5), 6, 1);
147 CCU_FACTOR_GATE_DEFINE(pll7_d7, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(6), 7, 1);
148 CCU_FACTOR_GATE_DEFINE(pll7_d8, CCU_PARENT_HW(pll7), APBS_PLL7_SWCR2, BIT(7), 8, 1);
149
150 CCU_FACTOR_GATE_DEFINE(pll8_d1, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(0), 1, 1);
151 CCU_FACTOR_GATE_DEFINE(pll8_d2, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(1), 2, 1);
152 CCU_FACTOR_GATE_DEFINE(pll8_d3, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(2), 3, 1);
153 CCU_FACTOR_GATE_DEFINE(pll8_d4, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(3), 4, 1);
154 CCU_FACTOR_GATE_DEFINE(pll8_d5, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(4), 5, 1);
155 CCU_FACTOR_GATE_DEFINE(pll8_d6, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(5), 6, 1);
156 CCU_FACTOR_GATE_DEFINE(pll8_d7, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(6), 7, 1);
157 CCU_FACTOR_GATE_DEFINE(pll8_d8, CCU_PARENT_HW(pll8), APBS_PLL8_SWCR2, BIT(7), 8, 1);
158 /* APBS clocks end */
159
160 /* MPMU clocks start */
161 CCU_GATE_DEFINE(pll1_d8_307p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(13), 0);
162 CCU_FACTOR_DEFINE(pll1_d32_76p8, CCU_PARENT_HW(pll1_d8_307p2), 4, 1);
163 CCU_FACTOR_DEFINE(pll1_d40_61p44, CCU_PARENT_HW(pll1_d8_307p2), 5, 1);
164 CCU_FACTOR_DEFINE(pll1_d16_153p6, CCU_PARENT_HW(pll1_d8), 2, 1);
165 CCU_FACTOR_GATE_DEFINE(pll1_d24_102p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(12), 3, 1);
166 CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(7), 6, 1);
167 CCU_FACTOR_GATE_DEFINE(pll1_d48_51p2_ap, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(11), 6, 1);
168 CCU_FACTOR_GATE_DEFINE(pll1_m3d128_57p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(8), 16, 3);
169 CCU_FACTOR_GATE_DEFINE(pll1_d96_25p6, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(4), 12, 1);
170 CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(3), 24, 1);
171 CCU_FACTOR_GATE_DEFINE(pll1_d192_12p8_wdt, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(19), 24, 1);
172 CCU_FACTOR_GATE_DEFINE(pll1_d384_6p4, CCU_PARENT_HW(pll1_d8), MPMU_ACGR, BIT(2), 48, 1);
173
174 CCU_FACTOR_DEFINE(pll1_d768_3p2, CCU_PARENT_HW(pll1_d384_6p4), 2, 1);
175 CCU_FACTOR_DEFINE(pll1_d1536_1p6, CCU_PARENT_HW(pll1_d384_6p4), 4, 1);
176 CCU_FACTOR_DEFINE(pll1_d3072_0p8, CCU_PARENT_HW(pll1_d384_6p4), 8, 1);
177
178 CCU_GATE_DEFINE(pll1_d6_409p6, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(0), 0);
179 CCU_FACTOR_GATE_DEFINE(pll1_d12_204p8, CCU_PARENT_HW(pll1_d6), MPMU_ACGR, BIT(5), 2, 1);
180
181 CCU_GATE_DEFINE(pll1_d5_491p52, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(21), 0);
182 CCU_FACTOR_GATE_DEFINE(pll1_d10_245p76, CCU_PARENT_HW(pll1_d5), MPMU_ACGR, BIT(18), 2, 1);
183
184 CCU_GATE_DEFINE(pll1_d4_614p4, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(15), 0);
185 CCU_FACTOR_GATE_DEFINE(pll1_d52_47p26, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(10), 13, 1);
186 CCU_FACTOR_GATE_DEFINE(pll1_d78_31p5, CCU_PARENT_HW(pll1_d4), MPMU_ACGR, BIT(6), 39, 2);
187
188 CCU_GATE_DEFINE(pll1_d3_819p2, CCU_PARENT_HW(pll1_d3), MPMU_ACGR, BIT(14), 0);
189
190 CCU_GATE_DEFINE(pll1_d2_1228p8, CCU_PARENT_HW(pll1_d2), MPMU_ACGR, BIT(16), 0);
191
192 static const struct clk_parent_data apb_parents[] = {
193 CCU_PARENT_HW(pll1_d96_25p6),
194 CCU_PARENT_HW(pll1_d48_51p2),
195 CCU_PARENT_HW(pll1_d96_25p6),
196 CCU_PARENT_HW(pll1_d24_102p4),
197 };
198 CCU_MUX_DEFINE(apb_clk, apb_parents, MPMU_APBCSCR, 0, 2, 0);
199
200 CCU_GATE_DEFINE(slow_uart, CCU_PARENT_NAME(osc_32k), MPMU_ACGR, BIT(1), CLK_IGNORE_UNUSED);
201 CCU_DDN_DEFINE(slow_uart1_14p74, pll1_d16_153p6, MPMU_SUCCR, 16, 13, 0, 13, 2, 0);
202 CCU_DDN_DEFINE(slow_uart2_48, pll1_d4_614p4, MPMU_SUCCR_1, 16, 13, 0, 13, 2, 0);
203
204 CCU_GATE_DEFINE(wdt_clk, CCU_PARENT_HW(pll1_d96_25p6), MPMU_WDTPCR, BIT(1), 0);
205 CCU_GATE_DEFINE(wdt_bus_clk, CCU_PARENT_HW(apb_clk), MPMU_WDTPCR, BIT(0), 0);
206
207 CCU_GATE_DEFINE(r_ipc_clk, CCU_PARENT_HW(apb_clk), MPMU_RIPCCR, BIT(0), 0);
208
209 CCU_FACTOR_DEFINE(i2s_153p6, CCU_PARENT_HW(pll1_d8_307p2), 2, 1);
210
211 static const struct clk_parent_data i2s_153p6_base_parents[] = {
212 CCU_PARENT_HW(i2s_153p6),
213 CCU_PARENT_HW(pll1_d8_307p2),
214 };
215 CCU_MUX_DEFINE(i2s_153p6_base, i2s_153p6_base_parents, MPMU_FCCR, 29, 1, 0);
216
217 static const struct clk_parent_data i2s_sysclk_src_parents[] = {
218 CCU_PARENT_HW(pll1_d96_25p6),
219 CCU_PARENT_HW(i2s_153p6_base),
220 };
221 CCU_MUX_GATE_DEFINE(i2s_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR1, 30, 1, BIT(31), 0);
222
223 CCU_DDN_DEFINE(i2s_sysclk, i2s_sysclk_src, MPMU_ISCCR1, 0, 15, 15, 12, 1, 0);
224
225 CCU_FACTOR_DEFINE(i2s_bclk_factor, CCU_PARENT_HW(i2s_sysclk), 2, 1);
226 /*
227 * Divider of i2s_bclk always implies a 1/2 factor, which is
228 * described by i2s_bclk_factor.
229 */
230 CCU_DIV_GATE_DEFINE(i2s_bclk, CCU_PARENT_HW(i2s_bclk_factor), MPMU_ISCCR1, 27, 2, BIT(29), 0);
231
232 CCU_MUX_GATE_DEFINE(i2s1_sysclk_src, i2s_sysclk_src_parents, MPMU_ISCCR0, 30, 1, BIT(31), 0);
233 CCU_DDN_DEFINE(i2s1_sysclk, i2s1_sysclk_src, MPMU_ISCCR0, 0, 15, 15, 12, 1, 0);
234
235 static const struct clk_parent_data i2s_sysclk_parents[] = {
236 CCU_PARENT_HW(pll1_d4_614p4),
237 CCU_PARENT_NAME(vctcxo_24m),
238 CCU_PARENT_HW(pll2_d5),
239 CCU_PARENT_NAME(vctcxo_24m),
240 };
241 CCU_MUX_DEFINE(i2s0_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 0, 2, 0);
242 CCU_MUX_DEFINE(i2s2_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 4, 2, 0);
243 CCU_MUX_DEFINE(i2s3_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 12, 2, 0);
244 CCU_MUX_DEFINE(i2s4_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 16, 2, 0);
245 CCU_MUX_DEFINE(i2s5_sysclk_sel, i2s_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 20, 2, 0);
246
247 CCU_DDN_DEFINE(i2s0_sysclk_div, i2s0_sysclk_sel, MPMU_I2S0_SYSCLK, 0, 16, 16, 16, 2, 0);
248 CCU_DDN_DEFINE(i2s2_sysclk_div, i2s2_sysclk_sel, MPMU_I2S2_SYSCLK, 0, 16, 16, 16, 2, 0);
249 CCU_DDN_DEFINE(i2s3_sysclk_div, i2s3_sysclk_sel, MPMU_I2S3_SYSCLK, 0, 16, 16, 16, 2, 0);
250 CCU_DDN_DEFINE(i2s4_sysclk_div, i2s4_sysclk_sel, MPMU_I2S4_SYSCLK, 0, 16, 16, 16, 2, 0);
251 CCU_DDN_DEFINE(i2s5_sysclk_div, i2s5_sysclk_sel, MPMU_I2S5_SYSCLK, 0, 16, 16, 16, 2, 0);
252
253 static const struct clk_parent_data i2s2_sysclk_parents[] = {
254 CCU_PARENT_HW(i2s_sysclk),
255 CCU_PARENT_HW(i2s2_sysclk_div),
256 };
257 CCU_GATE_DEFINE(i2s0_sysclk, CCU_PARENT_HW(i2s0_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(2), 0);
258 CCU_MUX_GATE_DEFINE(i2s2_sysclk, i2s2_sysclk_parents, MPMU_I2S_SYSCLK_CTRL, 8, 1, BIT(6), 0);
259 CCU_GATE_DEFINE(i2s3_sysclk, CCU_PARENT_HW(i2s3_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(14), 0);
260 CCU_GATE_DEFINE(i2s4_sysclk, CCU_PARENT_HW(i2s4_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(18), 0);
261 CCU_GATE_DEFINE(i2s5_sysclk, CCU_PARENT_HW(i2s5_sysclk_div), MPMU_I2S_SYSCLK_CTRL, BIT(22), 0);
262 /* MPMU clocks end */
263
264 /* APBC clocks start */
265 static const struct clk_parent_data uart_clk_parents[] = {
266 CCU_PARENT_HW(pll1_m3d128_57p6),
267 CCU_PARENT_HW(slow_uart1_14p74),
268 CCU_PARENT_HW(slow_uart2_48),
269 };
270 CCU_MUX_GATE_DEFINE(uart0_clk, uart_clk_parents, APBC_UART0_CLK_RST, 4, 3, BIT(1), 0);
271 CCU_MUX_GATE_DEFINE(uart2_clk, uart_clk_parents, APBC_UART2_CLK_RST, 4, 3, BIT(1), 0);
272 CCU_MUX_GATE_DEFINE(uart3_clk, uart_clk_parents, APBC_UART3_CLK_RST, 4, 3, BIT(1), 0);
273 CCU_MUX_GATE_DEFINE(uart4_clk, uart_clk_parents, APBC_UART4_CLK_RST, 4, 3, BIT(1), 0);
274 CCU_MUX_GATE_DEFINE(uart5_clk, uart_clk_parents, APBC_UART5_CLK_RST, 4, 3, BIT(1), 0);
275 CCU_MUX_GATE_DEFINE(uart6_clk, uart_clk_parents, APBC_UART6_CLK_RST, 4, 3, BIT(1), 0);
276 CCU_MUX_GATE_DEFINE(uart7_clk, uart_clk_parents, APBC_UART7_CLK_RST, 4, 3, BIT(1), 0);
277 CCU_MUX_GATE_DEFINE(uart8_clk, uart_clk_parents, APBC_UART8_CLK_RST, 4, 3, BIT(1), 0);
278 CCU_MUX_GATE_DEFINE(uart9_clk, uart_clk_parents, APBC_UART9_CLK_RST, 4, 3, BIT(1), 0);
279 CCU_MUX_GATE_DEFINE(uart10_clk, uart_clk_parents, APBC_UART10_CLK_RST, 4, 3, BIT(1), 0);
280
281 CCU_GATE_DEFINE(uart0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART0_CLK_RST, BIT(0), 0);
282 CCU_GATE_DEFINE(uart2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART2_CLK_RST, BIT(0), 0);
283 CCU_GATE_DEFINE(uart3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART3_CLK_RST, BIT(0), 0);
284 CCU_GATE_DEFINE(uart4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART4_CLK_RST, BIT(0), 0);
285 CCU_GATE_DEFINE(uart5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART5_CLK_RST, BIT(0), 0);
286 CCU_GATE_DEFINE(uart6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART6_CLK_RST, BIT(0), 0);
287 CCU_GATE_DEFINE(uart7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART7_CLK_RST, BIT(0), 0);
288 CCU_GATE_DEFINE(uart8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART8_CLK_RST, BIT(0), 0);
289 CCU_GATE_DEFINE(uart9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART9_CLK_RST, BIT(0), 0);
290 CCU_GATE_DEFINE(uart10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_UART10_CLK_RST, BIT(0), 0);
291
292 CCU_GATE_DEFINE(gpio_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_GPIO_CLK_RST, BIT(1), 0);
293 CCU_GATE_DEFINE(gpio_bus_clk, CCU_PARENT_HW(apb_clk), APBC_GPIO_CLK_RST, BIT(0), 0);
294
295 static const struct clk_parent_data pwm_parents[] = {
296 CCU_PARENT_HW(pll1_d192_12p8),
297 CCU_PARENT_NAME(osc_32k),
298 };
299 CCU_MUX_GATE_DEFINE(pwm0_clk, pwm_parents, APBC_PWM0_CLK_RST, 4, 3, BIT(1), 0);
300 CCU_MUX_GATE_DEFINE(pwm1_clk, pwm_parents, APBC_PWM1_CLK_RST, 4, 3, BIT(1), 0);
301 CCU_MUX_GATE_DEFINE(pwm2_clk, pwm_parents, APBC_PWM2_CLK_RST, 4, 3, BIT(1), 0);
302 CCU_MUX_GATE_DEFINE(pwm3_clk, pwm_parents, APBC_PWM3_CLK_RST, 4, 3, BIT(1), 0);
303 CCU_MUX_GATE_DEFINE(pwm4_clk, pwm_parents, APBC_PWM4_CLK_RST, 4, 3, BIT(1), 0);
304 CCU_MUX_GATE_DEFINE(pwm5_clk, pwm_parents, APBC_PWM5_CLK_RST, 4, 3, BIT(1), 0);
305 CCU_MUX_GATE_DEFINE(pwm6_clk, pwm_parents, APBC_PWM6_CLK_RST, 4, 3, BIT(1), 0);
306 CCU_MUX_GATE_DEFINE(pwm7_clk, pwm_parents, APBC_PWM7_CLK_RST, 4, 3, BIT(1), 0);
307 CCU_MUX_GATE_DEFINE(pwm8_clk, pwm_parents, APBC_PWM8_CLK_RST, 4, 3, BIT(1), 0);
308 CCU_MUX_GATE_DEFINE(pwm9_clk, pwm_parents, APBC_PWM9_CLK_RST, 4, 3, BIT(1), 0);
309 CCU_MUX_GATE_DEFINE(pwm10_clk, pwm_parents, APBC_PWM10_CLK_RST, 4, 3, BIT(1), 0);
310 CCU_MUX_GATE_DEFINE(pwm11_clk, pwm_parents, APBC_PWM11_CLK_RST, 4, 3, BIT(1), 0);
311 CCU_MUX_GATE_DEFINE(pwm12_clk, pwm_parents, APBC_PWM12_CLK_RST, 4, 3, BIT(1), 0);
312 CCU_MUX_GATE_DEFINE(pwm13_clk, pwm_parents, APBC_PWM13_CLK_RST, 4, 3, BIT(1), 0);
313 CCU_MUX_GATE_DEFINE(pwm14_clk, pwm_parents, APBC_PWM14_CLK_RST, 4, 3, BIT(1), 0);
314 CCU_MUX_GATE_DEFINE(pwm15_clk, pwm_parents, APBC_PWM15_CLK_RST, 4, 3, BIT(1), 0);
315 CCU_MUX_GATE_DEFINE(pwm16_clk, pwm_parents, APBC_PWM16_CLK_RST, 4, 3, BIT(1), 0);
316 CCU_MUX_GATE_DEFINE(pwm17_clk, pwm_parents, APBC_PWM17_CLK_RST, 4, 3, BIT(1), 0);
317 CCU_MUX_GATE_DEFINE(pwm18_clk, pwm_parents, APBC_PWM18_CLK_RST, 4, 3, BIT(1), 0);
318 CCU_MUX_GATE_DEFINE(pwm19_clk, pwm_parents, APBC_PWM19_CLK_RST, 4, 3, BIT(1), 0);
319
320 CCU_GATE_DEFINE(pwm0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM0_CLK_RST, BIT(0), 0);
321 CCU_GATE_DEFINE(pwm1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM1_CLK_RST, BIT(0), 0);
322 CCU_GATE_DEFINE(pwm2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM2_CLK_RST, BIT(0), 0);
323 CCU_GATE_DEFINE(pwm3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM3_CLK_RST, BIT(0), 0);
324 CCU_GATE_DEFINE(pwm4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM4_CLK_RST, BIT(0), 0);
325 CCU_GATE_DEFINE(pwm5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM5_CLK_RST, BIT(0), 0);
326 CCU_GATE_DEFINE(pwm6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM6_CLK_RST, BIT(0), 0);
327 CCU_GATE_DEFINE(pwm7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM7_CLK_RST, BIT(0), 0);
328 CCU_GATE_DEFINE(pwm8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM8_CLK_RST, BIT(0), 0);
329 CCU_GATE_DEFINE(pwm9_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM9_CLK_RST, BIT(0), 0);
330 CCU_GATE_DEFINE(pwm10_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM10_CLK_RST, BIT(0), 0);
331 CCU_GATE_DEFINE(pwm11_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM11_CLK_RST, BIT(0), 0);
332 CCU_GATE_DEFINE(pwm12_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM12_CLK_RST, BIT(0), 0);
333 CCU_GATE_DEFINE(pwm13_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM13_CLK_RST, BIT(0), 0);
334 CCU_GATE_DEFINE(pwm14_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM14_CLK_RST, BIT(0), 0);
335 CCU_GATE_DEFINE(pwm15_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM15_CLK_RST, BIT(0), 0);
336 CCU_GATE_DEFINE(pwm16_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM16_CLK_RST, BIT(0), 0);
337 CCU_GATE_DEFINE(pwm17_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM17_CLK_RST, BIT(0), 0);
338 CCU_GATE_DEFINE(pwm18_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM18_CLK_RST, BIT(0), 0);
339 CCU_GATE_DEFINE(pwm19_bus_clk, CCU_PARENT_HW(apb_clk), APBC_PWM19_CLK_RST, BIT(0), 0);
340
341 static const struct clk_parent_data i2s_bclk_parents[] = {
342 CCU_PARENT_NAME(vctcxo_1m),
343 CCU_PARENT_HW(i2s_bclk),
344 };
345 CCU_MUX_DEFINE(spi0_i2s_bclk, i2s_bclk_parents, APBC_SSP0_CLK_RST, 3, 1, 0);
346 CCU_MUX_DEFINE(spi1_i2s_bclk, i2s_bclk_parents, APBC_SSP1_CLK_RST, 3, 1, 0);
347 CCU_MUX_DEFINE(spi3_i2s_bclk, i2s_bclk_parents, APBC_SSP3_CLK_RST, 3, 1, 0);
348
349 static const struct clk_parent_data spi0_parents[] = {
350 CCU_PARENT_HW(pll1_d384_6p4),
351 CCU_PARENT_HW(pll1_d192_12p8),
352 CCU_PARENT_HW(pll1_d96_25p6),
353 CCU_PARENT_HW(pll1_d48_51p2),
354 CCU_PARENT_HW(pll1_d768_3p2),
355 CCU_PARENT_HW(pll1_d1536_1p6),
356 CCU_PARENT_HW(pll1_d3072_0p8),
357 CCU_PARENT_HW(spi0_i2s_bclk),
358 };
359 CCU_MUX_GATE_DEFINE(spi0_clk, spi0_parents, APBC_SSP0_CLK_RST, 4, 3, BIT(1), 0);
360
361 static const struct clk_parent_data spi1_parents[] = {
362 CCU_PARENT_HW(pll1_d384_6p4),
363 CCU_PARENT_HW(pll1_d192_12p8),
364 CCU_PARENT_HW(pll1_d96_25p6),
365 CCU_PARENT_HW(pll1_d48_51p2),
366 CCU_PARENT_HW(pll1_d768_3p2),
367 CCU_PARENT_HW(pll1_d1536_1p6),
368 CCU_PARENT_HW(pll1_d3072_0p8),
369 CCU_PARENT_HW(spi1_i2s_bclk),
370 };
371 CCU_MUX_GATE_DEFINE(spi1_clk, spi1_parents, APBC_SSP1_CLK_RST, 4, 3, BIT(1), 0);
372
373 static const struct clk_parent_data spi3_parents[] = {
374 CCU_PARENT_HW(pll1_d384_6p4),
375 CCU_PARENT_HW(pll1_d192_12p8),
376 CCU_PARENT_HW(pll1_d96_25p6),
377 CCU_PARENT_HW(pll1_d48_51p2),
378 CCU_PARENT_HW(pll1_d768_3p2),
379 CCU_PARENT_HW(pll1_d1536_1p6),
380 CCU_PARENT_HW(pll1_d3072_0p8),
381 CCU_PARENT_HW(spi3_i2s_bclk),
382 };
383 CCU_MUX_GATE_DEFINE(spi3_clk, spi3_parents, APBC_SSP3_CLK_RST, 4, 3, BIT(1), 0);
384
385 CCU_GATE_DEFINE(spi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP0_CLK_RST, BIT(0), 0);
386 CCU_GATE_DEFINE(spi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP1_CLK_RST, BIT(0), 0);
387 CCU_GATE_DEFINE(spi3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSP3_CLK_RST, BIT(0), 0);
388
389
390 CCU_GATE_DEFINE(rtc_clk, CCU_PARENT_NAME(osc_32k), APBC_RTC_CLK_RST,
391 BIT(7) | BIT(1), 0);
392 CCU_GATE_DEFINE(rtc_bus_clk, CCU_PARENT_HW(apb_clk), APBC_RTC_CLK_RST, BIT(0), 0);
393
394 static const struct clk_parent_data twsi_parents[] = {
395 CCU_PARENT_HW(pll1_d78_31p5),
396 CCU_PARENT_HW(pll1_d48_51p2),
397 CCU_PARENT_HW(pll1_d40_61p44),
398 };
399 CCU_MUX_GATE_DEFINE(twsi0_clk, twsi_parents, APBC_TWSI0_CLK_RST, 4, 3, BIT(1), 0);
400 CCU_MUX_GATE_DEFINE(twsi1_clk, twsi_parents, APBC_TWSI1_CLK_RST, 4, 3, BIT(1), 0);
401 CCU_MUX_GATE_DEFINE(twsi2_clk, twsi_parents, APBC_TWSI2_CLK_RST, 4, 3, BIT(1), 0);
402 CCU_MUX_GATE_DEFINE(twsi4_clk, twsi_parents, APBC_TWSI4_CLK_RST, 4, 3, BIT(1), 0);
403 CCU_MUX_GATE_DEFINE(twsi5_clk, twsi_parents, APBC_TWSI5_CLK_RST, 4, 3, BIT(1), 0);
404 CCU_MUX_GATE_DEFINE(twsi6_clk, twsi_parents, APBC_TWSI6_CLK_RST, 4, 3, BIT(1), 0);
405 CCU_MUX_GATE_DEFINE(twsi8_clk, twsi_parents, APBC_TWSI8_CLK_RST, 4, 3, BIT(1), 0);
406
407 CCU_GATE_DEFINE(twsi0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI0_CLK_RST, BIT(0), 0);
408 CCU_GATE_DEFINE(twsi1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI1_CLK_RST, BIT(0), 0);
409 CCU_GATE_DEFINE(twsi2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI2_CLK_RST, BIT(0), 0);
410 CCU_GATE_DEFINE(twsi4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI4_CLK_RST, BIT(0), 0);
411 CCU_GATE_DEFINE(twsi5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI5_CLK_RST, BIT(0), 0);
412 CCU_GATE_DEFINE(twsi6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI6_CLK_RST, BIT(0), 0);
413 CCU_GATE_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI8_CLK_RST, BIT(0), 0);
414
415 static const struct clk_parent_data timer_parents[] = {
416 CCU_PARENT_HW(pll1_d192_12p8),
417 CCU_PARENT_NAME(osc_32k),
418 CCU_PARENT_HW(pll1_d384_6p4),
419 CCU_PARENT_NAME(vctcxo_3m),
420 CCU_PARENT_NAME(vctcxo_1m),
421 };
422 CCU_MUX_GATE_DEFINE(timers0_clk, timer_parents, APBC_TIMERS0_CLK_RST, 4, 3, BIT(1), 0);
423 CCU_MUX_GATE_DEFINE(timers1_clk, timer_parents, APBC_TIMERS1_CLK_RST, 4, 3, BIT(1), 0);
424 CCU_MUX_GATE_DEFINE(timers2_clk, timer_parents, APBC_TIMERS2_CLK_RST, 4, 3, BIT(1), 0);
425 CCU_MUX_GATE_DEFINE(timers3_clk, timer_parents, APBC_TIMERS3_CLK_RST, 4, 3, BIT(1), 0);
426 CCU_MUX_GATE_DEFINE(timers4_clk, timer_parents, APBC_TIMERS4_CLK_RST, 4, 3, BIT(1), 0);
427 CCU_MUX_GATE_DEFINE(timers5_clk, timer_parents, APBC_TIMERS5_CLK_RST, 4, 3, BIT(1), 0);
428 CCU_MUX_GATE_DEFINE(timers6_clk, timer_parents, APBC_TIMERS6_CLK_RST, 4, 3, BIT(1), 0);
429 CCU_MUX_GATE_DEFINE(timers7_clk, timer_parents, APBC_TIMERS7_CLK_RST, 4, 3, BIT(1), 0);
430
431 CCU_GATE_DEFINE(timers0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS0_CLK_RST, BIT(0), 0);
432 CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS1_CLK_RST, BIT(0), 0);
433 CCU_GATE_DEFINE(timers2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS2_CLK_RST, BIT(0), 0);
434 CCU_GATE_DEFINE(timers3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS3_CLK_RST, BIT(0), 0);
435 CCU_GATE_DEFINE(timers4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS4_CLK_RST, BIT(0), 0);
436 CCU_GATE_DEFINE(timers5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS5_CLK_RST, BIT(0), 0);
437 CCU_GATE_DEFINE(timers6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS6_CLK_RST, BIT(0), 0);
438 CCU_GATE_DEFINE(timers7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS7_CLK_RST, BIT(0), 0);
439
440 CCU_GATE_DEFINE(aib_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_AIB_CLK_RST, BIT(1), 0);
441 CCU_GATE_DEFINE(aib_bus_clk, CCU_PARENT_HW(apb_clk), APBC_AIB_CLK_RST, BIT(0), 0);
442
443 CCU_GATE_DEFINE(onewire_clk, CCU_PARENT_NAME(vctcxo_24m), APBC_ONEWIRE_CLK_RST, BIT(1), 0);
444 CCU_GATE_DEFINE(onewire_bus_clk, CCU_PARENT_HW(apb_clk), APBC_ONEWIRE_CLK_RST, BIT(0), 0);
445
446 /*
447 * When i2s_bclk is selected as the parent clock of sspa,
448 * the hardware requires bit3 to be set
449 */
450
451 CCU_MUX_DEFINE(i2s0_i2s_bclk, i2s_bclk_parents, APBC_SSPA0_CLK_RST, 3, 1, 0);
452 CCU_MUX_DEFINE(i2s1_i2s_bclk, i2s_bclk_parents, APBC_SSPA1_CLK_RST, 3, 1, 0);
453 CCU_MUX_DEFINE(i2s2_i2s_bclk, i2s_bclk_parents, APBC_SSPA2_CLK_RST, 3, 1, 0);
454 CCU_MUX_DEFINE(i2s3_i2s_bclk, i2s_bclk_parents, APBC_SSPA3_CLK_RST, 3, 1, 0);
455 CCU_MUX_DEFINE(i2s4_i2s_bclk, i2s_bclk_parents, APBC_SSPA4_CLK_RST, 3, 1, 0);
456 CCU_MUX_DEFINE(i2s5_i2s_bclk, i2s_bclk_parents, APBC_SSPA5_CLK_RST, 3, 1, 0);
457
458 static const struct clk_parent_data i2s0_parents[] = {
459 CCU_PARENT_HW(pll1_d384_6p4),
460 CCU_PARENT_HW(pll1_d192_12p8),
461 CCU_PARENT_HW(pll1_d96_25p6),
462 CCU_PARENT_HW(pll1_d48_51p2),
463 CCU_PARENT_HW(pll1_d768_3p2),
464 CCU_PARENT_HW(pll1_d1536_1p6),
465 CCU_PARENT_HW(pll1_d3072_0p8),
466 CCU_PARENT_HW(i2s0_i2s_bclk),
467 };
468 CCU_MUX_GATE_DEFINE(i2s0_clk, i2s0_parents, APBC_SSPA0_CLK_RST, 4, 3, BIT(1), 0);
469
470 static const struct clk_parent_data i2s1_parents[] = {
471 CCU_PARENT_HW(pll1_d384_6p4),
472 CCU_PARENT_HW(pll1_d192_12p8),
473 CCU_PARENT_HW(pll1_d96_25p6),
474 CCU_PARENT_HW(pll1_d48_51p2),
475 CCU_PARENT_HW(pll1_d768_3p2),
476 CCU_PARENT_HW(pll1_d1536_1p6),
477 CCU_PARENT_HW(pll1_d3072_0p8),
478 CCU_PARENT_HW(i2s1_i2s_bclk),
479 };
480 CCU_MUX_GATE_DEFINE(i2s1_clk, i2s1_parents, APBC_SSPA1_CLK_RST, 4, 3, BIT(1), 0);
481
482 static const struct clk_parent_data i2s2_parents[] = {
483 CCU_PARENT_HW(pll1_d384_6p4),
484 CCU_PARENT_HW(pll1_d192_12p8),
485 CCU_PARENT_HW(pll1_d96_25p6),
486 CCU_PARENT_HW(pll1_d48_51p2),
487 CCU_PARENT_HW(pll1_d768_3p2),
488 CCU_PARENT_HW(pll1_d1536_1p6),
489 CCU_PARENT_HW(pll1_d3072_0p8),
490 CCU_PARENT_HW(i2s2_i2s_bclk),
491 };
492 CCU_MUX_GATE_DEFINE(i2s2_clk, i2s2_parents, APBC_SSPA2_CLK_RST, 4, 3, BIT(1), 0);
493
494 static const struct clk_parent_data i2s3_parents[] = {
495 CCU_PARENT_HW(pll1_d384_6p4),
496 CCU_PARENT_HW(pll1_d192_12p8),
497 CCU_PARENT_HW(pll1_d96_25p6),
498 CCU_PARENT_HW(pll1_d48_51p2),
499 CCU_PARENT_HW(pll1_d768_3p2),
500 CCU_PARENT_HW(pll1_d1536_1p6),
501 CCU_PARENT_HW(pll1_d3072_0p8),
502 CCU_PARENT_HW(i2s3_i2s_bclk),
503 };
504 CCU_MUX_GATE_DEFINE(i2s3_clk, i2s3_parents, APBC_SSPA3_CLK_RST, 4, 3, BIT(1), 0);
505
506 static const struct clk_parent_data i2s4_parents[] = {
507 CCU_PARENT_HW(pll1_d384_6p4),
508 CCU_PARENT_HW(pll1_d192_12p8),
509 CCU_PARENT_HW(pll1_d96_25p6),
510 CCU_PARENT_HW(pll1_d48_51p2),
511 CCU_PARENT_HW(pll1_d768_3p2),
512 CCU_PARENT_HW(pll1_d1536_1p6),
513 CCU_PARENT_HW(pll1_d3072_0p8),
514 CCU_PARENT_HW(i2s4_i2s_bclk),
515 };
516 CCU_MUX_GATE_DEFINE(i2s4_clk, i2s4_parents, APBC_SSPA4_CLK_RST, 4, 3, BIT(1), 0);
517
518 static const struct clk_parent_data i2s5_parents[] = {
519 CCU_PARENT_HW(pll1_d384_6p4),
520 CCU_PARENT_HW(pll1_d192_12p8),
521 CCU_PARENT_HW(pll1_d96_25p6),
522 CCU_PARENT_HW(pll1_d48_51p2),
523 CCU_PARENT_HW(pll1_d768_3p2),
524 CCU_PARENT_HW(pll1_d1536_1p6),
525 CCU_PARENT_HW(pll1_d3072_0p8),
526 CCU_PARENT_HW(i2s5_i2s_bclk),
527 };
528 CCU_MUX_GATE_DEFINE(i2s5_clk, i2s5_parents, APBC_SSPA5_CLK_RST, 4, 3, BIT(1), 0);
529
530 CCU_GATE_DEFINE(i2s0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA0_CLK_RST, BIT(0), 0);
531 CCU_GATE_DEFINE(i2s1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA1_CLK_RST, BIT(0), 0);
532 CCU_GATE_DEFINE(i2s2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA2_CLK_RST, BIT(0), 0);
533 CCU_GATE_DEFINE(i2s3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA3_CLK_RST, BIT(0), 0);
534 CCU_GATE_DEFINE(i2s4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA4_CLK_RST, BIT(0), 0);
535 CCU_GATE_DEFINE(i2s5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_SSPA5_CLK_RST, BIT(0), 0);
536
537 CCU_GATE_DEFINE(dro_clk, CCU_PARENT_HW(apb_clk), APBC_DRO_CLK_RST, BIT(1), 0);
538 CCU_GATE_DEFINE(ir0_clk, CCU_PARENT_HW(apb_clk), APBC_IR0_CLK_RST, BIT(1), 0);
539 CCU_GATE_DEFINE(ir1_clk, CCU_PARENT_HW(apb_clk), APBC_IR1_CLK_RST, BIT(1), 0);
540
541 CCU_GATE_DEFINE(tsen_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(1), 0);
542 CCU_GATE_DEFINE(tsen_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TSEN_CLK_RST, BIT(0), 0);
543
544 CCU_GATE_DEFINE(ipc_ap2rcpu_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(1), 0);
545 CCU_GATE_DEFINE(ipc_ap2rcpu_bus_clk, CCU_PARENT_HW(apb_clk), APBC_IPC_AP2AUD_CLK_RST, BIT(0), 0);
546
547 static const struct clk_parent_data can_parents[] = {
548 CCU_PARENT_HW(pll6_20),
549 CCU_PARENT_HW(pll6_40),
550 CCU_PARENT_HW(pll6_80),
551 };
552 CCU_MUX_GATE_DEFINE(can0_clk, can_parents, APBC_CAN0_CLK_RST, 4, 3, BIT(1), 0);
553 CCU_MUX_GATE_DEFINE(can1_clk, can_parents, APBC_CAN1_CLK_RST, 4, 3, BIT(1), 0);
554 CCU_MUX_GATE_DEFINE(can2_clk, can_parents, APBC_CAN2_CLK_RST, 4, 3, BIT(1), 0);
555 CCU_MUX_GATE_DEFINE(can3_clk, can_parents, APBC_CAN3_CLK_RST, 4, 3, BIT(1), 0);
556 CCU_MUX_GATE_DEFINE(can4_clk, can_parents, APBC_CAN4_CLK_RST, 4, 3, BIT(1), 0);
557
558 CCU_GATE_DEFINE(can0_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN0_CLK_RST, BIT(0), 0);
559 CCU_GATE_DEFINE(can1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN1_CLK_RST, BIT(0), 0);
560 CCU_GATE_DEFINE(can2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN2_CLK_RST, BIT(0), 0);
561 CCU_GATE_DEFINE(can3_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN3_CLK_RST, BIT(0), 0);
562 CCU_GATE_DEFINE(can4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_CAN4_CLK_RST, BIT(0), 0);
563 /* APBC clocks end */
564
565 /* APMU clocks start */
566 static const struct clk_parent_data axi_clk_parents[] = {
567 CCU_PARENT_HW(pll1_d8_307p2),
568 CCU_PARENT_HW(pll1_d6_409p6),
569 };
570 CCU_MUX_DIV_FC_DEFINE(axi_clk, axi_clk_parents, APMU_ACLK_CLK_CTRL, 1, 2, BIT(4), 0, 1, 0);
571
572 static const struct clk_parent_data cci550_clk_parents[] = {
573 CCU_PARENT_HW(pll1_d10_245p76),
574 CCU_PARENT_HW(pll1_d6_409p6),
575 CCU_PARENT_HW(pll1_d4_614p4),
576 CCU_PARENT_HW(pll1_d3_819p2),
577 CCU_PARENT_HW(pll7_d3),
578 CCU_PARENT_HW(pll2_d3),
579 CCU_PARENT_HW(pll1_d2_1228p8),
580 CCU_PARENT_HW(pll7_d2),
581 };
582 CCU_MUX_DIV_FC_DEFINE(cci550_clk, cci550_clk_parents, APMU_CCI550_CLK_CTRL, 8, 2, BIT(12), 0, 3,
583 CLK_IS_CRITICAL);
584
585 static const struct clk_parent_data cpu_c0_clk_parents[] = {
586 CCU_PARENT_HW(pll1_d3_819p2),
587 CCU_PARENT_HW(pll1_d5_491p52),
588 CCU_PARENT_HW(pll1_d4_614p4),
589 CCU_PARENT_HW(pll2_d3),
590 CCU_PARENT_HW(pll3_d2),
591 CCU_PARENT_HW(pll1_d2_1228p8),
592 CCU_PARENT_HW(pll2_d2),
593 CCU_PARENT_HW(pll3_d1),
594 };
595 CCU_MUX_DIV_FC_DEFINE(cpu_c0_core_clk, cpu_c0_clk_parents, APMU_CPU_C0_CLK_CTRL,
596 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL);
597
598 static const struct clk_parent_data cpu_c1_clk_parents[] = {
599 CCU_PARENT_HW(pll1_d3_819p2),
600 CCU_PARENT_HW(pll1_d5_491p52),
601 CCU_PARENT_HW(pll1_d4_614p4),
602 CCU_PARENT_HW(pll2_d3),
603 CCU_PARENT_HW(pll4_d2),
604 CCU_PARENT_HW(pll1_d2_1228p8),
605 CCU_PARENT_HW(pll2_d2),
606 CCU_PARENT_HW(pll4_d1),
607 };
608 CCU_MUX_DIV_FC_DEFINE(cpu_c1_core_clk, cpu_c1_clk_parents, APMU_CPU_C1_CLK_CTRL,
609 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL);
610
611 static const struct clk_parent_data cpu_c2_clk_parents[] = {
612 CCU_PARENT_HW(pll1_d3_819p2),
613 CCU_PARENT_HW(pll1_d5_491p52),
614 CCU_PARENT_HW(pll1_d4_614p4),
615 CCU_PARENT_HW(pll2_d3),
616 CCU_PARENT_HW(pll5_d2),
617 CCU_PARENT_HW(pll1_d2_1228p8),
618 CCU_PARENT_HW(pll2_d2),
619 CCU_PARENT_HW(pll5_d1),
620 };
621 CCU_MUX_DIV_FC_DEFINE(cpu_c2_core_clk, cpu_c2_clk_parents, APMU_CPU_C2_CLK_CTRL,
622 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL);
623
624 static const struct clk_parent_data cpu_c3_clk_parents[] = {
625 CCU_PARENT_HW(pll1_d3_819p2),
626 CCU_PARENT_HW(pll1_d5_491p52),
627 CCU_PARENT_HW(pll1_d4_614p4),
628 CCU_PARENT_HW(pll2_d3),
629 CCU_PARENT_HW(pll8_d2),
630 CCU_PARENT_HW(pll1_d2_1228p8),
631 CCU_PARENT_HW(pll2_d2),
632 CCU_PARENT_HW(pll8_d1),
633 };
634 CCU_MUX_DIV_FC_DEFINE(cpu_c3_core_clk, cpu_c3_clk_parents, APMU_CPU_C3_CLK_CTRL,
635 3, 3, BIT(12), 0, 3, CLK_IS_CRITICAL);
636
637 static const struct clk_parent_data ccic2phy_parents[] = {
638 CCU_PARENT_HW(pll1_d24_102p4),
639 CCU_PARENT_HW(pll1_d48_51p2_ap),
640 };
641 CCU_MUX_GATE_DEFINE(ccic2phy_clk, ccic2phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 7, 1, BIT(5), 0);
642
643 static const struct clk_parent_data ccic3phy_parents[] = {
644 CCU_PARENT_HW(pll1_d24_102p4),
645 CCU_PARENT_HW(pll1_d48_51p2_ap),
646 };
647 CCU_MUX_GATE_DEFINE(ccic3phy_clk, ccic3phy_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 31, 1, BIT(30), 0);
648
649 static const struct clk_parent_data csi_parents[] = {
650 CCU_PARENT_HW(pll1_d5_491p52),
651 CCU_PARENT_HW(pll1_d6_409p6),
652 CCU_PARENT_HW(pll1_d4_614p4),
653 CCU_PARENT_HW(pll1_d3_819p2),
654 CCU_PARENT_HW(pll2_d2),
655 CCU_PARENT_HW(pll2_d3),
656 CCU_PARENT_HW(pll2_d4),
657 CCU_PARENT_HW(pll1_d2_1228p8),
658 };
659 CCU_MUX_DIV_GATE_FC_DEFINE(csi_clk, csi_parents, APMU_CSI_CCIC2_CLK_RES_CTRL, 20, 3, BIT(15),
660 16, 3, BIT(4), 0);
661
662 static const struct clk_parent_data isp_bus_parents[] = {
663 CCU_PARENT_HW(pll1_d6_409p6),
664 CCU_PARENT_HW(pll1_d5_491p52),
665 CCU_PARENT_HW(pll1_d4_614p4),
666 CCU_PARENT_HW(pll1_d10_245p76),
667 };
668 CCU_MUX_DIV_GATE_FC_DEFINE(isp_bus_clk, isp_bus_parents, APMU_ISP_CLK_RES_CTRL, 18, 3, BIT(23),
669 21, 2, BIT(17), 0);
670
671 CCU_GATE_DEFINE(d1p_1228p8, CCU_PARENT_HW(pll1_d2_1228p8), APMU_PMU_CLK_GATE_CTRL, BIT(31), 0);
672 CCU_GATE_DEFINE(d1p_819p2, CCU_PARENT_HW(pll1_d3_819p2), APMU_PMU_CLK_GATE_CTRL, BIT(30), 0);
673 CCU_GATE_DEFINE(d1p_614p4, CCU_PARENT_HW(pll1_d4_614p4), APMU_PMU_CLK_GATE_CTRL, BIT(29), 0);
674 CCU_GATE_DEFINE(d1p_491p52, CCU_PARENT_HW(pll1_d5_491p52), APMU_PMU_CLK_GATE_CTRL, BIT(28), 0);
675 CCU_GATE_DEFINE(d1p_409p6, CCU_PARENT_HW(pll1_d6_409p6), APMU_PMU_CLK_GATE_CTRL, BIT(27), 0);
676 CCU_GATE_DEFINE(d1p_307p2, CCU_PARENT_HW(pll1_d8_307p2), APMU_PMU_CLK_GATE_CTRL, BIT(26), 0);
677 CCU_GATE_DEFINE(d1p_245p76, CCU_PARENT_HW(pll1_d10_245p76), APMU_PMU_CLK_GATE_CTRL, BIT(22), 0);
678
679 static const struct clk_parent_data v2d_parents[] = {
680 CCU_PARENT_HW(pll1_d5_491p52),
681 CCU_PARENT_HW(pll2_d4),
682 CCU_PARENT_HW(pll1_d8_307p2),
683 CCU_PARENT_HW(pll1_d4_614p4),
684 };
685 CCU_MUX_DIV_GATE_FC_DEFINE(v2d_clk, v2d_parents, APMU_LCD_CLK_RES_CTRL1, 9, 3, BIT(28), 12, 2,
686 BIT(8), 0);
687
688 static const struct clk_parent_data dsiesc_parents[] = {
689 CCU_PARENT_HW(pll1_d48_51p2_ap),
690 CCU_PARENT_HW(pll1_d52_47p26),
691 CCU_PARENT_HW(pll1_d96_25p6),
692 CCU_PARENT_HW(pll1_d32_76p8),
693 };
694 CCU_MUX_GATE_DEFINE(dsi_esc_clk, dsiesc_parents, APMU_LCD_CLK_RES_CTRL1, 0, 2, BIT(2), 0);
695
696 CCU_GATE_DEFINE(lcd_hclk, CCU_PARENT_HW(axi_clk), APMU_LCD_CLK_RES_CTRL1, BIT(5), 0);
697
698 static const struct clk_parent_data lcd_dsc_parents[] = {
699 CCU_PARENT_HW(pll1_d4_614p4),
700 CCU_PARENT_HW(pll1_d5_491p52),
701 CCU_PARENT_HW(pll1_d10_245p76),
702 CCU_PARENT_HW(pll7_d5),
703 CCU_PARENT_HW(pll2_d7),
704 CCU_PARENT_HW(pll1_d6_409p6),
705 CCU_PARENT_HW(pll1_d48_51p2_ap),
706 CCU_PARENT_HW(pll2_d8),
707 };
708 CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_dsc_clk, lcd_dsc_parents, APMU_LCD_CLK_RES_CTRL2,
709 APMU_LCD_CLK_RES_CTRL1, 25, 3, BIT(26), 29, 3, BIT(14), 0);
710
711 static const struct clk_parent_data lcdpx_parents[] = {
712 CCU_PARENT_HW(pll1_d4_614p4),
713 CCU_PARENT_HW(pll1_d5_491p52),
714 CCU_PARENT_HW(pll1_d10_245p76),
715 CCU_PARENT_HW(pll7_d5),
716 CCU_PARENT_HW(pll2_d7),
717 CCU_PARENT_HW(pll2_d4),
718 CCU_PARENT_HW(pll1_d48_51p2_ap),
719 CCU_PARENT_HW(pll2_d8),
720 };
721 CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_pxclk, lcdpx_parents, APMU_LCD_CLK_RES_CTRL2,
722 APMU_LCD_CLK_RES_CTRL1, 17, 3, BIT(30), 21, 3, BIT(16), 0);
723
724 static const struct clk_parent_data lcdmclk_parents[] = {
725 CCU_PARENT_HW(pll1_d6_409p6),
726 CCU_PARENT_HW(pll1_d5_491p52),
727 CCU_PARENT_HW(pll1_d4_614p4),
728 CCU_PARENT_HW(pll1_d8_307p2),
729 };
730 CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(lcd_mclk, lcdmclk_parents, APMU_LCD_CLK_RES_CTRL2,
731 APMU_LCD_CLK_RES_CTRL1, 1, 4, BIT(29), 5, 3, BIT(0), 0);
732
733 static const struct clk_parent_data ccic_4x_parents[] = {
734 CCU_PARENT_HW(pll1_d5_491p52),
735 CCU_PARENT_HW(pll1_d6_409p6),
736 CCU_PARENT_HW(pll1_d4_614p4),
737 CCU_PARENT_HW(pll1_d3_819p2),
738 CCU_PARENT_HW(pll2_d2),
739 CCU_PARENT_HW(pll2_d3),
740 CCU_PARENT_HW(pll2_d4),
741 CCU_PARENT_HW(pll1_d2_1228p8),
742 };
743 CCU_MUX_DIV_GATE_FC_DEFINE(ccic_4x_clk, ccic_4x_parents, APMU_CCIC_CLK_RES_CTRL, 18, 3,
744 BIT(15), 23, 2, BIT(4), 0);
745
746 static const struct clk_parent_data ccic1phy_parents[] = {
747 CCU_PARENT_HW(pll1_d24_102p4),
748 CCU_PARENT_HW(pll1_d48_51p2_ap),
749 };
750 CCU_MUX_GATE_DEFINE(ccic1phy_clk, ccic1phy_parents, APMU_CCIC_CLK_RES_CTRL, 7, 1, BIT(5), 0);
751
752
753 static const struct clk_parent_data sc2hclk_parents[] = {
754 CCU_PARENT_HW(pll1_d8_307p2),
755 CCU_PARENT_HW(pll1_d4_614p4),
756 CCU_PARENT_HW(pll1_d5_491p52),
757 CCU_PARENT_HW(pll2_d4),
758 };
759 CCU_MUX_DIV_GATE_FC_DEFINE(sc2_hclk, sc2hclk_parents, APMU_CCIC_CLK_RES_CTRL, 10, 3,
760 BIT(16), 8, 2, BIT(3), 0);
761
762 CCU_GATE_DEFINE(sdh_axi_aclk, CCU_PARENT_HW(axi_clk), APMU_SDH0_CLK_RES_CTRL, BIT(3), 0);
763 static const struct clk_parent_data sdh01_parents[] = {
764 CCU_PARENT_HW(pll1_d6_409p6),
765 CCU_PARENT_HW(pll1_d4_614p4),
766 CCU_PARENT_HW(pll2_d8),
767 CCU_PARENT_HW(pll2_d5),
768 CCU_PARENT_NAME(reserved_clk),
769 CCU_PARENT_NAME(reserved_clk),
770 CCU_PARENT_HW(pll1_dx),
771 };
772 CCU_MUX_DIV_GATE_FC_DEFINE(sdh0_clk, sdh01_parents, APMU_SDH0_CLK_RES_CTRL, 8, 3,
773 BIT(11), 5, 3, BIT(4), 0);
774 CCU_MUX_DIV_GATE_FC_DEFINE(sdh1_clk, sdh01_parents, APMU_SDH1_CLK_RES_CTRL, 8, 3,
775 BIT(11), 5, 3, BIT(4), 0);
776 static const struct clk_parent_data sdh2_parents[] = {
777 CCU_PARENT_HW(pll1_d6_409p6),
778 CCU_PARENT_HW(pll1_d4_614p4),
779 CCU_PARENT_HW(pll2_d8),
780 CCU_PARENT_HW(pll1_d3_819p2),
781 CCU_PARENT_NAME(reserved_clk),
782 CCU_PARENT_NAME(reserved_clk),
783 CCU_PARENT_HW(pll1_dx),
784 };
785 CCU_MUX_DIV_GATE_FC_DEFINE(sdh2_clk, sdh2_parents, APMU_SDH2_CLK_RES_CTRL, 8, 3,
786 BIT(11), 5, 3, BIT(4), 0);
787
788 CCU_GATE_DEFINE(usb2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(1), 0);
789 CCU_GATE_DEFINE(usb3_porta_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(4), 0);
790 CCU_GATE_DEFINE(usb3_portb_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(8), 0);
791 CCU_GATE_DEFINE(usb3_portc_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(12), 0);
792 CCU_GATE_DEFINE(usb3_portd_bus_clk, CCU_PARENT_HW(axi_clk), APMU_USB_CLK_RES_CTRL, BIT(16), 0);
793
794 static const struct clk_parent_data qspi_parents[] = {
795 CCU_PARENT_HW(pll1_d6_409p6),
796 CCU_PARENT_HW(pll2_d8),
797 CCU_PARENT_HW(pll1_d8_307p2),
798 CCU_PARENT_HW(pll1_d10_245p76),
799 CCU_PARENT_NAME(reserved_clk),
800 CCU_PARENT_HW(pll1_dx),
801 CCU_PARENT_HW(pll1_d5_491p52),
802 CCU_PARENT_NAME(reserved_clk),
803 };
804 CCU_MUX_DIV_GATE_FC_DEFINE(qspi_clk, qspi_parents, APMU_QSPI_CLK_RES_CTRL, 9, 3,
805 BIT(12), 6, 3, BIT(4), 0);
806 CCU_GATE_DEFINE(qspi_bus_clk, CCU_PARENT_HW(axi_clk), APMU_QSPI_CLK_RES_CTRL, BIT(3), 0);
807
808 CCU_GATE_DEFINE(dma_clk, CCU_PARENT_HW(axi_clk), APMU_DMA_CLK_RES_CTRL, BIT(3), 0);
809
810 static const struct clk_parent_data aes_wtm_parents[] = {
811 CCU_PARENT_HW(pll1_d12_204p8),
812 CCU_PARENT_HW(pll1_d24_102p4),
813 };
814 CCU_MUX_GATE_DEFINE(aes_wtm_clk, aes_wtm_parents, APMU_AES_CLK_RES_CTRL, 6, 1, BIT(5), 0);
815
816 static const struct clk_parent_data vpu_parents[] = {
817 CCU_PARENT_HW(pll1_d4_614p4),
818 CCU_PARENT_HW(pll1_d5_491p52),
819 CCU_PARENT_HW(pll1_d3_819p2),
820 CCU_PARENT_HW(pll1_d6_409p6),
821 CCU_PARENT_HW(pll1_d2_1228p8),
822 CCU_PARENT_HW(pll2_d3),
823 CCU_PARENT_HW(pll2_d4),
824 CCU_PARENT_HW(pll2_d5),
825 };
826 CCU_MUX_DIV_GATE_FC_DEFINE(vpu_clk, vpu_parents, APMU_VPU_CLK_RES_CTRL, 13, 3,
827 BIT(21), 10, 3, BIT(3), 0);
828
829 CCU_GATE_DEFINE(dtc_clk, CCU_PARENT_HW(axi_clk), APMU_DTC_CLK_RES_CTRL, BIT(3), 0);
830
831 static const struct clk_parent_data gpu_parents[] = {
832 CCU_PARENT_HW(pll1_d4_614p4),
833 CCU_PARENT_HW(pll1_d5_491p52),
834 CCU_PARENT_HW(pll1_d3_819p2),
835 CCU_PARENT_HW(pll1_d6_409p6),
836 CCU_PARENT_HW(pll1_d2_1228p8),
837 CCU_PARENT_HW(pll2_d3),
838 CCU_PARENT_HW(pll2_d4),
839 CCU_PARENT_HW(pll2_d5),
840 };
841 CCU_MUX_DIV_GATE_FC_DEFINE(gpu_clk, gpu_parents, APMU_GPU_CLK_RES_CTRL, 12, 3,
842 BIT(15), 18, 3, BIT(4), 0);
843
844 CCU_GATE_DEFINE(mc_ahb_clk, CCU_PARENT_HW(axi_clk), APMU_PMUA_MC_CTRL, BIT(1), 0);
845
846 static const struct clk_parent_data top_parents[] = {
847 CCU_PARENT_HW(pll1_d8_307p2),
848 CCU_PARENT_HW(pll1_d6_409p6),
849 CCU_PARENT_HW(pll3_d4),
850 CCU_PARENT_HW(pll6_d5),
851 CCU_PARENT_HW(pll7_d4),
852 CCU_PARENT_HW(pll6_d4),
853 CCU_PARENT_HW(pll7_d3),
854 CCU_PARENT_HW(pll6_d3),
855 };
856 CCU_MUX_DIV_GATE_FC_DEFINE(top_dclk, top_parents, APMU_TOP_DCLK_CTRL, 5, 3,
857 BIT(8), 2, 3, BIT(1), CLK_IS_CRITICAL);
858
859 static const struct clk_parent_data ucie_parents[] = {
860 CCU_PARENT_HW(pll1_d8_307p2),
861 CCU_PARENT_HW(pll1_d6_409p6),
862 CCU_PARENT_HW(pll3_d4),
863 CCU_PARENT_HW(pll6_d5),
864 CCU_PARENT_HW(pll7_d4),
865 CCU_PARENT_HW(pll6_d4),
866 };
867 CCU_MUX_GATE_DEFINE(ucie_clk, ucie_parents, APMU_UCIE_CTRL, 4, 3, BIT(0), 0);
868 CCU_GATE_DEFINE(ucie_sbclk, CCU_PARENT_HW(axi_clk), APMU_UCIE_CTRL, BIT(8), 0);
869
870 static const struct clk_parent_data rcpu_clk_parents[] = {
871 CCU_PARENT_HW(pll1_aud_245p7),
872 CCU_PARENT_HW(pll1_d8_307p2),
873 CCU_PARENT_HW(pll1_d5_491p52),
874 CCU_PARENT_HW(pll1_d6_409p6),
875 };
876 CCU_MUX_DIV_GATE_FC_DEFINE(rcpu_clk, rcpu_clk_parents, APMU_RCPU_CLK_RES_CTRL,
877 4, 3, BIT(15), 7, 3, BIT(12), 0);
878
879 static const struct clk_parent_data dsi4ln2_dsi_esc_parents[] = {
880 CCU_PARENT_HW(pll1_d48_51p2_ap),
881 CCU_PARENT_HW(pll1_d52_47p26),
882 CCU_PARENT_HW(pll1_d96_25p6),
883 CCU_PARENT_HW(pll1_d32_76p8),
884 };
885 CCU_MUX_GATE_DEFINE(dsi4ln2_dsi_esc_clk, dsi4ln2_dsi_esc_parents, APMU_LCD_CLK_RES_CTRL3,
886 0, 1, BIT(2), 0);
887
888 static const struct clk_parent_data dsi4ln2_lcd_dsc_parents[] = {
889 CCU_PARENT_HW(pll1_d4_614p4),
890 CCU_PARENT_HW(pll1_d5_491p52),
891 CCU_PARENT_HW(pll7_d5),
892 CCU_PARENT_HW(pll6_d6),
893 CCU_PARENT_HW(pll2_d7),
894 CCU_PARENT_HW(pll1_d6_409p6),
895 CCU_PARENT_HW(pll1_d48_51p2_ap),
896 };
897 CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_dsc_clk, dsi4ln2_lcd_dsc_parents,
898 APMU_LCD_CLK_RES_CTRL4, APMU_LCD_CLK_RES_CTRL3,
899 25, 3, BIT(26), 29, 3, BIT(14), 0);
900
901 static const struct clk_parent_data dsi4ln2_lcdpx_parents[] = {
902 CCU_PARENT_HW(pll1_d4_614p4),
903 CCU_PARENT_HW(pll1_d5_491p52),
904 CCU_PARENT_HW(pll7_d5),
905 CCU_PARENT_HW(pll6_d6),
906 CCU_PARENT_HW(pll2_d7),
907 CCU_PARENT_HW(pll2_d4),
908 CCU_PARENT_HW(pll1_d48_51p2_ap),
909 CCU_PARENT_HW(pll2_d8),
910 };
911 CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_pxclk, dsi4ln2_lcdpx_parents, APMU_LCD_CLK_RES_CTRL4,
912 APMU_LCD_CLK_RES_CTRL3, 17, 3, BIT(30), 21, 3, BIT(16), 0);
913
914 static const struct clk_parent_data dsi4ln2_lcd_mclk_parents[] = {
915 CCU_PARENT_HW(pll1_d6_409p6),
916 CCU_PARENT_HW(pll1_d5_491p52),
917 CCU_PARENT_HW(pll1_d4_614p4),
918 CCU_PARENT_HW(pll1_d8_307p2),
919 };
920 CCU_MUX_DIV_GATE_SPLIT_FC_DEFINE(dsi4ln2_lcd_mclk, dsi4ln2_lcd_mclk_parents, APMU_LCD_CLK_RES_CTRL4,
921 APMU_LCD_CLK_RES_CTRL3, 1, 4, BIT(29), 5, 3, BIT(0), 0);
922
923 static const struct clk_parent_data dpu_aclk_parents[] = {
924 CCU_PARENT_HW(pll1_d6_409p6),
925 CCU_PARENT_HW(pll1_d5_491p52),
926 CCU_PARENT_HW(pll1_d4_614p4),
927 CCU_PARENT_HW(pll1_d8_307p2),
928 CCU_PARENT_HW(pll2_d4),
929 };
930 CCU_MUX_DIV_GATE_FC_DEFINE(dsi4ln2_dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CTRL5,
931 2, 3, BIT(30), 5, 3, BIT(1), 0);
932
933 CCU_MUX_DIV_GATE_FC_DEFINE(dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CTRL5, 17, 3, BIT(31),
934 20, 3, BIT(16), 0);
935
936 static const struct clk_parent_data ufs_aclk_parents[] = {
937 CCU_PARENT_HW(pll1_d5_491p52),
938 CCU_PARENT_HW(pll1_d6_409p6),
939 CCU_PARENT_HW(pll2_d6),
940 CCU_PARENT_HW(pll2_d5),
941 };
942 CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_parents, APMU_UFS_CLK_RES_CTRL, 5, 3, BIT(8),
943 2, 3, BIT(1), 0);
944
945 CCU_FACTOR_DEFINE(ufs_refclk, CCU_PARENT_HW(pll1_d64_38p4), 2, 1);
946
947 static const struct clk_parent_data edp0_pclk_parents[] = {
948 CCU_PARENT_HW(lcd_pxclk),
949 CCU_PARENT_NAME(external_clk),
950 };
951 CCU_MUX_GATE_DEFINE(edp0_pxclk, edp0_pclk_parents, APMU_LCD_EDP_CTRL, 2, 1, BIT(1), 0);
952
953 static const struct clk_parent_data edp1_pclk_parents[] = {
954 CCU_PARENT_HW(dsi4ln2_lcd_pxclk),
955 CCU_PARENT_NAME(external_clk),
956 };
957 CCU_MUX_GATE_DEFINE(edp1_pxclk, edp1_pclk_parents, APMU_LCD_EDP_CTRL, 18, 1, BIT(17), 0);
958
959 CCU_GATE_DEFINE(pciea_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(2), 0);
960 CCU_GATE_DEFINE(pciea_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_A, BIT(1), 0);
961 CCU_GATE_DEFINE(pciea_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_A, BIT(0), 0);
962 CCU_GATE_DEFINE(pcieb_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(2), 0);
963 CCU_GATE_DEFINE(pcieb_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_B, BIT(1), 0);
964 CCU_GATE_DEFINE(pcieb_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_B, BIT(0), 0);
965 CCU_GATE_DEFINE(pciec_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(2), 0);
966 CCU_GATE_DEFINE(pciec_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_C, BIT(1), 0);
967 CCU_GATE_DEFINE(pciec_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_C, BIT(0), 0);
968 CCU_GATE_DEFINE(pcied_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(2), 0);
969 CCU_GATE_DEFINE(pcied_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_D, BIT(1), 0);
970 CCU_GATE_DEFINE(pcied_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_D, BIT(0), 0);
971 CCU_GATE_DEFINE(pciee_mstr_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(2), 0);
972 CCU_GATE_DEFINE(pciee_slv_clk, CCU_PARENT_HW(pll2_d6), APMU_PCIE_CLK_RES_CTRL_E, BIT(1), 0);
973 CCU_GATE_DEFINE(pciee_dbi_clk, CCU_PARENT_HW(axi_clk), APMU_PCIE_CLK_RES_CTRL_E, BIT(0), 0);
974
975 static const struct clk_parent_data emac_1588_parents[] = {
976 CCU_PARENT_NAME(vctcxo_24m),
977 CCU_PARENT_HW(pll2_d24_125),
978 };
979
980 CCU_GATE_DEFINE(emac0_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC0_CLK_RES_CTRL, BIT(0), 0);
981 CCU_GATE_FLAGS_DEFINE(emac0_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMAC0_CLK_RES_CTRL,
982 BIT(14), true, 0);
983 CCU_MUX_DEFINE(emac0_1588_clk, emac_1588_parents, APMU_EMAC0_CLK_RES_CTRL, 15, 1, 0);
984 CCU_GATE_DEFINE(emac0_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC0_CLK_RES_CTRL,
985 BIT(8), 0);
986 CCU_GATE_DEFINE(emac1_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC1_CLK_RES_CTRL, BIT(0), 0);
987 CCU_GATE_FLAGS_DEFINE(emac1_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMAC1_CLK_RES_CTRL,
988 BIT(14), true, 0);
989 CCU_MUX_DEFINE(emac1_1588_clk, emac_1588_parents, APMU_EMAC1_CLK_RES_CTRL, 15, 1, 0);
990 CCU_GATE_DEFINE(emac1_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC1_CLK_RES_CTRL,
991 BIT(8), 0);
992 CCU_GATE_DEFINE(emac2_bus_clk, CCU_PARENT_HW(axi_clk), APMU_EMAC2_CLK_RES_CTRL, BIT(0), 0);
993 CCU_GATE_FLAGS_DEFINE(emac2_ref_clk, CCU_PARENT_HW(pll2_d120_25), APMU_EMAC2_CLK_RES_CTRL,
994 BIT(14), true, 0);
995 CCU_MUX_DEFINE(emac2_1588_clk, emac_1588_parents, APMU_EMAC2_CLK_RES_CTRL, 15, 1, 0);
996 CCU_GATE_DEFINE(emac2_rgmii_tx_clk, CCU_PARENT_HW(pll2_d24_125), APMU_EMAC2_CLK_RES_CTRL,
997 BIT(8), 0);
998
999 static const struct clk_parent_data espi_sclk_src_parents[] = {
1000 CCU_PARENT_HW(pll2_20),
1001 CCU_PARENT_HW(pll2_25),
1002 CCU_PARENT_HW(pll2_33),
1003 CCU_PARENT_HW(pll2_50),
1004 CCU_PARENT_HW(pll2_66),
1005 };
1006 CCU_MUX_DEFINE(espi_sclk_src, espi_sclk_src_parents, APMU_ESPI_CLK_RES_CTRL, 4, 3, 0);
1007
1008 static const struct clk_parent_data espi_sclk_parents[] = {
1009 CCU_PARENT_NAME(external_clk),
1010 CCU_PARENT_HW(espi_sclk_src),
1011 };
1012 CCU_MUX_GATE_DEFINE(espi_sclk, espi_sclk_parents, APMU_ESPI_CLK_RES_CTRL, 7, 1, BIT(3), 0);
1013
1014 CCU_GATE_DEFINE(espi_mclk, CCU_PARENT_HW(axi_clk), APMU_ESPI_CLK_RES_CTRL, BIT(1), 0);
1015
1016 CCU_FACTOR_DEFINE(cam_src1_clk, CCU_PARENT_HW(pll1_d6_409p6), 15, 1);
1017 CCU_FACTOR_DEFINE(cam_src2_clk, CCU_PARENT_HW(pll2_d5), 25, 1);
1018 CCU_FACTOR_DEFINE(cam_src3_clk, CCU_PARENT_HW(pll2_d6), 20, 1);
1019 CCU_FACTOR_DEFINE(cam_src4_clk, CCU_PARENT_HW(pll1_d6_409p6), 16, 1);
1020
1021 static const struct clk_parent_data isim_vclk_parents[] = {
1022 CCU_PARENT_HW(cam_src1_clk),
1023 CCU_PARENT_HW(cam_src2_clk),
1024 CCU_PARENT_HW(cam_src3_clk),
1025 CCU_PARENT_HW(cam_src4_clk),
1026 };
1027 CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out0, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 3, 4,
1028 1, 2, BIT(0), 0);
1029 CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out1, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 11, 4,
1030 9, 2, BIT(8), 0);
1031 CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out2, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 19, 4,
1032 17, 2, BIT(16), 0);
1033 CCU_MUX_DIV_GATE_DEFINE(isim_vclk_out3, isim_vclk_parents, APMU_SNR_ISIM_VCLK_CTRL, 27, 4,
1034 25, 2, BIT(24), 0);
1035 /* APMU clocks end */
1036
1037 /* DCIU clocks start */
1038 CCU_GATE_DEFINE(hdma_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_CLK_EN, BIT(0), CLK_IS_CRITICAL);
1039 CCU_GATE_DEFINE(dma350_clk, CCU_PARENT_HW(axi_clk), DCIU_DMASYS_SDMA_CLK_EN, BIT(0), 0);
1040 CCU_GATE_DEFINE(c2_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C2_TCM_PIPE_CLK, BIT(0), 0);
1041 CCU_GATE_DEFINE(c3_tcm_pipe_clk, CCU_PARENT_HW(axi_clk), DCIU_C3_TCM_PIPE_CLK, BIT(0), 0);
1042 /* DCIU clocks end */
1043
1044 static struct clk_hw *k3_ccu_pll_hws[] = {
1045 [CLK_PLL1] = &pll1.common.hw,
1046 [CLK_PLL2] = &pll2.common.hw,
1047 [CLK_PLL3] = &pll3.common.hw,
1048 [CLK_PLL4] = &pll4.common.hw,
1049 [CLK_PLL5] = &pll5.common.hw,
1050 [CLK_PLL6] = &pll6.common.hw,
1051 [CLK_PLL7] = &pll7.common.hw,
1052 [CLK_PLL8] = &pll8.common.hw,
1053 [CLK_PLL1_D2] = &pll1_d2.common.hw,
1054 [CLK_PLL1_D3] = &pll1_d3.common.hw,
1055 [CLK_PLL1_D4] = &pll1_d4.common.hw,
1056 [CLK_PLL1_D5] = &pll1_d5.common.hw,
1057 [CLK_PLL1_D6] = &pll1_d6.common.hw,
1058 [CLK_PLL1_D7] = &pll1_d7.common.hw,
1059 [CLK_PLL1_D8] = &pll1_d8.common.hw,
1060 [CLK_PLL1_DX] = &pll1_dx.common.hw,
1061 [CLK_PLL1_D64] = &pll1_d64_38p4.common.hw,
1062 [CLK_PLL1_D10_AUD] = &pll1_aud_245p7.common.hw,
1063 [CLK_PLL1_D100_AUD] = &pll1_aud_24p5.common.hw,
1064 [CLK_PLL2_D1] = &pll2_d1.common.hw,
1065 [CLK_PLL2_D2] = &pll2_d2.common.hw,
1066 [CLK_PLL2_D3] = &pll2_d3.common.hw,
1067 [CLK_PLL2_D4] = &pll2_d4.common.hw,
1068 [CLK_PLL2_D5] = &pll2_d5.common.hw,
1069 [CLK_PLL2_D6] = &pll2_d6.common.hw,
1070 [CLK_PLL2_D7] = &pll2_d7.common.hw,
1071 [CLK_PLL2_D8] = &pll2_d8.common.hw,
1072 [CLK_PLL2_66] = &pll2_66.common.hw,
1073 [CLK_PLL2_33] = &pll2_33.common.hw,
1074 [CLK_PLL2_50] = &pll2_50.common.hw,
1075 [CLK_PLL2_25] = &pll2_25.common.hw,
1076 [CLK_PLL2_20] = &pll2_20.common.hw,
1077 [CLK_PLL2_D24_125] = &pll2_d24_125.common.hw,
1078 [CLK_PLL2_D120_25] = &pll2_d120_25.common.hw,
1079 [CLK_PLL3_D1] = &pll3_d1.common.hw,
1080 [CLK_PLL3_D2] = &pll3_d2.common.hw,
1081 [CLK_PLL3_D3] = &pll3_d3.common.hw,
1082 [CLK_PLL3_D4] = &pll3_d4.common.hw,
1083 [CLK_PLL3_D5] = &pll3_d5.common.hw,
1084 [CLK_PLL3_D6] = &pll3_d6.common.hw,
1085 [CLK_PLL3_D7] = &pll3_d7.common.hw,
1086 [CLK_PLL3_D8] = &pll3_d8.common.hw,
1087 [CLK_PLL4_D1] = &pll4_d1.common.hw,
1088 [CLK_PLL4_D2] = &pll4_d2.common.hw,
1089 [CLK_PLL4_D3] = &pll4_d3.common.hw,
1090 [CLK_PLL4_D4] = &pll4_d4.common.hw,
1091 [CLK_PLL4_D5] = &pll4_d5.common.hw,
1092 [CLK_PLL4_D6] = &pll4_d6.common.hw,
1093 [CLK_PLL4_D7] = &pll4_d7.common.hw,
1094 [CLK_PLL4_D8] = &pll4_d8.common.hw,
1095 [CLK_PLL5_D1] = &pll5_d1.common.hw,
1096 [CLK_PLL5_D2] = &pll5_d2.common.hw,
1097 [CLK_PLL5_D3] = &pll5_d3.common.hw,
1098 [CLK_PLL5_D4] = &pll5_d4.common.hw,
1099 [CLK_PLL5_D5] = &pll5_d5.common.hw,
1100 [CLK_PLL5_D6] = &pll5_d6.common.hw,
1101 [CLK_PLL5_D7] = &pll5_d7.common.hw,
1102 [CLK_PLL5_D8] = &pll5_d8.common.hw,
1103 [CLK_PLL6_D1] = &pll6_d1.common.hw,
1104 [CLK_PLL6_D2] = &pll6_d2.common.hw,
1105 [CLK_PLL6_D3] = &pll6_d3.common.hw,
1106 [CLK_PLL6_D4] = &pll6_d4.common.hw,
1107 [CLK_PLL6_D5] = &pll6_d5.common.hw,
1108 [CLK_PLL6_D6] = &pll6_d6.common.hw,
1109 [CLK_PLL6_D7] = &pll6_d7.common.hw,
1110 [CLK_PLL6_D8] = &pll6_d8.common.hw,
1111 [CLK_PLL6_80] = &pll6_80.common.hw,
1112 [CLK_PLL6_40] = &pll6_40.common.hw,
1113 [CLK_PLL6_20] = &pll6_20.common.hw,
1114 [CLK_PLL7_D1] = &pll7_d1.common.hw,
1115 [CLK_PLL7_D2] = &pll7_d2.common.hw,
1116 [CLK_PLL7_D3] = &pll7_d3.common.hw,
1117 [CLK_PLL7_D4] = &pll7_d4.common.hw,
1118 [CLK_PLL7_D5] = &pll7_d5.common.hw,
1119 [CLK_PLL7_D6] = &pll7_d6.common.hw,
1120 [CLK_PLL7_D7] = &pll7_d7.common.hw,
1121 [CLK_PLL7_D8] = &pll7_d8.common.hw,
1122 [CLK_PLL8_D1] = &pll8_d1.common.hw,
1123 [CLK_PLL8_D2] = &pll8_d2.common.hw,
1124 [CLK_PLL8_D3] = &pll8_d3.common.hw,
1125 [CLK_PLL8_D4] = &pll8_d4.common.hw,
1126 [CLK_PLL8_D5] = &pll8_d5.common.hw,
1127 [CLK_PLL8_D6] = &pll8_d6.common.hw,
1128 [CLK_PLL8_D7] = &pll8_d7.common.hw,
1129 [CLK_PLL8_D8] = &pll8_d8.common.hw,
1130 };
1131
1132 static const struct spacemit_ccu_data k3_ccu_pll_data = {
1133 /* The APBS CCU implements PLLs, but no resets */
1134 .hws = k3_ccu_pll_hws,
1135 .num = ARRAY_SIZE(k3_ccu_pll_hws),
1136 };
1137
1138 static struct clk_hw *k3_ccu_mpmu_hws[] = {
1139 [CLK_MPMU_PLL1_307P2] = &pll1_d8_307p2.common.hw,
1140 [CLK_MPMU_PLL1_76P8] = &pll1_d32_76p8.common.hw,
1141 [CLK_MPMU_PLL1_61P44] = &pll1_d40_61p44.common.hw,
1142 [CLK_MPMU_PLL1_153P6] = &pll1_d16_153p6.common.hw,
1143 [CLK_MPMU_PLL1_102P4] = &pll1_d24_102p4.common.hw,
1144 [CLK_MPMU_PLL1_51P2] = &pll1_d48_51p2.common.hw,
1145 [CLK_MPMU_PLL1_51P2_AP] = &pll1_d48_51p2_ap.common.hw,
1146 [CLK_MPMU_PLL1_57P6] = &pll1_m3d128_57p6.common.hw,
1147 [CLK_MPMU_PLL1_25P6] = &pll1_d96_25p6.common.hw,
1148 [CLK_MPMU_PLL1_12P8] = &pll1_d192_12p8.common.hw,
1149 [CLK_MPMU_PLL1_12P8_WDT] = &pll1_d192_12p8_wdt.common.hw,
1150 [CLK_MPMU_PLL1_6P4] = &pll1_d384_6p4.common.hw,
1151 [CLK_MPMU_PLL1_3P2] = &pll1_d768_3p2.common.hw,
1152 [CLK_MPMU_PLL1_1P6] = &pll1_d1536_1p6.common.hw,
1153 [CLK_MPMU_PLL1_0P8] = &pll1_d3072_0p8.common.hw,
1154 [CLK_MPMU_PLL1_409P6] = &pll1_d6_409p6.common.hw,
1155 [CLK_MPMU_PLL1_204P8] = &pll1_d12_204p8.common.hw,
1156 [CLK_MPMU_PLL1_491] = &pll1_d5_491p52.common.hw,
1157 [CLK_MPMU_PLL1_245P76] = &pll1_d10_245p76.common.hw,
1158 [CLK_MPMU_PLL1_614] = &pll1_d4_614p4.common.hw,
1159 [CLK_MPMU_PLL1_47P26] = &pll1_d52_47p26.common.hw,
1160 [CLK_MPMU_PLL1_31P5] = &pll1_d78_31p5.common.hw,
1161 [CLK_MPMU_PLL1_819] = &pll1_d3_819p2.common.hw,
1162 [CLK_MPMU_PLL1_1228] = &pll1_d2_1228p8.common.hw,
1163 [CLK_MPMU_APB] = &apb_clk.common.hw,
1164 [CLK_MPMU_SLOW_UART] = &slow_uart.common.hw,
1165 [CLK_MPMU_SLOW_UART1] = &slow_uart1_14p74.common.hw,
1166 [CLK_MPMU_SLOW_UART2] = &slow_uart2_48.common.hw,
1167 [CLK_MPMU_WDT] = &wdt_clk.common.hw,
1168 [CLK_MPMU_WDT_BUS] = &wdt_bus_clk.common.hw,
1169 [CLK_MPMU_RIPC] = &r_ipc_clk.common.hw,
1170 [CLK_MPMU_I2S_153P6] = &i2s_153p6.common.hw,
1171 [CLK_MPMU_I2S_153P6_BASE] = &i2s_153p6_base.common.hw,
1172 [CLK_MPMU_I2S_SYSCLK_SRC] = &i2s_sysclk_src.common.hw,
1173 [CLK_MPMU_I2S_SYSCLK] = &i2s_sysclk.common.hw,
1174 [CLK_MPMU_I2S_BCLK_FACTOR] = &i2s_bclk_factor.common.hw,
1175 [CLK_MPMU_I2S_BCLK] = &i2s_bclk.common.hw,
1176 [CLK_MPMU_I2S1_SYSCLK_SRC] = &i2s1_sysclk_src.common.hw,
1177 [CLK_MPMU_I2S1_SYSCLK] = &i2s1_sysclk.common.hw,
1178 [CLK_MPMU_I2S0_SYSCLK_SEL] = &i2s0_sysclk_sel.common.hw,
1179 [CLK_MPMU_I2S2_SYSCLK_SEL] = &i2s2_sysclk_sel.common.hw,
1180 [CLK_MPMU_I2S3_SYSCLK_SEL] = &i2s3_sysclk_sel.common.hw,
1181 [CLK_MPMU_I2S4_SYSCLK_SEL] = &i2s4_sysclk_sel.common.hw,
1182 [CLK_MPMU_I2S5_SYSCLK_SEL] = &i2s5_sysclk_sel.common.hw,
1183 [CLK_MPMU_I2S0_SYSCLK_DIV] = &i2s0_sysclk_div.common.hw,
1184 [CLK_MPMU_I2S2_SYSCLK_DIV] = &i2s2_sysclk_div.common.hw,
1185 [CLK_MPMU_I2S3_SYSCLK_DIV] = &i2s3_sysclk_div.common.hw,
1186 [CLK_MPMU_I2S4_SYSCLK_DIV] = &i2s4_sysclk_div.common.hw,
1187 [CLK_MPMU_I2S5_SYSCLK_DIV] = &i2s5_sysclk_div.common.hw,
1188 [CLK_MPMU_I2S0_SYSCLK] = &i2s0_sysclk.common.hw,
1189 [CLK_MPMU_I2S2_SYSCLK] = &i2s2_sysclk.common.hw,
1190 [CLK_MPMU_I2S3_SYSCLK] = &i2s3_sysclk.common.hw,
1191 [CLK_MPMU_I2S4_SYSCLK] = &i2s4_sysclk.common.hw,
1192 [CLK_MPMU_I2S5_SYSCLK] = &i2s5_sysclk.common.hw,
1193 };
1194
1195 static const struct spacemit_ccu_data k3_ccu_mpmu_data = {
1196 .reset_name = "k3-mpmu-reset",
1197 .hws = k3_ccu_mpmu_hws,
1198 .num = ARRAY_SIZE(k3_ccu_mpmu_hws),
1199 };
1200
1201 static struct clk_hw *k3_ccu_apbc_hws[] = {
1202 [CLK_APBC_UART0] = &uart0_clk.common.hw,
1203 [CLK_APBC_UART2] = &uart2_clk.common.hw,
1204 [CLK_APBC_UART3] = &uart3_clk.common.hw,
1205 [CLK_APBC_UART4] = &uart4_clk.common.hw,
1206 [CLK_APBC_UART5] = &uart5_clk.common.hw,
1207 [CLK_APBC_UART6] = &uart6_clk.common.hw,
1208 [CLK_APBC_UART7] = &uart7_clk.common.hw,
1209 [CLK_APBC_UART8] = &uart8_clk.common.hw,
1210 [CLK_APBC_UART9] = &uart9_clk.common.hw,
1211 [CLK_APBC_UART10] = &uart10_clk.common.hw,
1212 [CLK_APBC_UART0_BUS] = &uart0_bus_clk.common.hw,
1213 [CLK_APBC_UART2_BUS] = &uart2_bus_clk.common.hw,
1214 [CLK_APBC_UART3_BUS] = &uart3_bus_clk.common.hw,
1215 [CLK_APBC_UART4_BUS] = &uart4_bus_clk.common.hw,
1216 [CLK_APBC_UART5_BUS] = &uart5_bus_clk.common.hw,
1217 [CLK_APBC_UART6_BUS] = &uart6_bus_clk.common.hw,
1218 [CLK_APBC_UART7_BUS] = &uart7_bus_clk.common.hw,
1219 [CLK_APBC_UART8_BUS] = &uart8_bus_clk.common.hw,
1220 [CLK_APBC_UART9_BUS] = &uart9_bus_clk.common.hw,
1221 [CLK_APBC_UART10_BUS] = &uart10_bus_clk.common.hw,
1222 [CLK_APBC_GPIO] = &gpio_clk.common.hw,
1223 [CLK_APBC_GPIO_BUS] = &gpio_bus_clk.common.hw,
1224 [CLK_APBC_PWM0] = &pwm0_clk.common.hw,
1225 [CLK_APBC_PWM1] = &pwm1_clk.common.hw,
1226 [CLK_APBC_PWM2] = &pwm2_clk.common.hw,
1227 [CLK_APBC_PWM3] = &pwm3_clk.common.hw,
1228 [CLK_APBC_PWM4] = &pwm4_clk.common.hw,
1229 [CLK_APBC_PWM5] = &pwm5_clk.common.hw,
1230 [CLK_APBC_PWM6] = &pwm6_clk.common.hw,
1231 [CLK_APBC_PWM7] = &pwm7_clk.common.hw,
1232 [CLK_APBC_PWM8] = &pwm8_clk.common.hw,
1233 [CLK_APBC_PWM9] = &pwm9_clk.common.hw,
1234 [CLK_APBC_PWM10] = &pwm10_clk.common.hw,
1235 [CLK_APBC_PWM11] = &pwm11_clk.common.hw,
1236 [CLK_APBC_PWM12] = &pwm12_clk.common.hw,
1237 [CLK_APBC_PWM13] = &pwm13_clk.common.hw,
1238 [CLK_APBC_PWM14] = &pwm14_clk.common.hw,
1239 [CLK_APBC_PWM15] = &pwm15_clk.common.hw,
1240 [CLK_APBC_PWM16] = &pwm16_clk.common.hw,
1241 [CLK_APBC_PWM17] = &pwm17_clk.common.hw,
1242 [CLK_APBC_PWM18] = &pwm18_clk.common.hw,
1243 [CLK_APBC_PWM19] = &pwm19_clk.common.hw,
1244 [CLK_APBC_PWM0_BUS] = &pwm0_bus_clk.common.hw,
1245 [CLK_APBC_PWM1_BUS] = &pwm1_bus_clk.common.hw,
1246 [CLK_APBC_PWM2_BUS] = &pwm2_bus_clk.common.hw,
1247 [CLK_APBC_PWM3_BUS] = &pwm3_bus_clk.common.hw,
1248 [CLK_APBC_PWM4_BUS] = &pwm4_bus_clk.common.hw,
1249 [CLK_APBC_PWM5_BUS] = &pwm5_bus_clk.common.hw,
1250 [CLK_APBC_PWM6_BUS] = &pwm6_bus_clk.common.hw,
1251 [CLK_APBC_PWM7_BUS] = &pwm7_bus_clk.common.hw,
1252 [CLK_APBC_PWM8_BUS] = &pwm8_bus_clk.common.hw,
1253 [CLK_APBC_PWM9_BUS] = &pwm9_bus_clk.common.hw,
1254 [CLK_APBC_PWM10_BUS] = &pwm10_bus_clk.common.hw,
1255 [CLK_APBC_PWM11_BUS] = &pwm11_bus_clk.common.hw,
1256 [CLK_APBC_PWM12_BUS] = &pwm12_bus_clk.common.hw,
1257 [CLK_APBC_PWM13_BUS] = &pwm13_bus_clk.common.hw,
1258 [CLK_APBC_PWM14_BUS] = &pwm14_bus_clk.common.hw,
1259 [CLK_APBC_PWM15_BUS] = &pwm15_bus_clk.common.hw,
1260 [CLK_APBC_PWM16_BUS] = &pwm16_bus_clk.common.hw,
1261 [CLK_APBC_PWM17_BUS] = &pwm17_bus_clk.common.hw,
1262 [CLK_APBC_PWM18_BUS] = &pwm18_bus_clk.common.hw,
1263 [CLK_APBC_PWM19_BUS] = &pwm19_bus_clk.common.hw,
1264 [CLK_APBC_SPI0_I2S_BCLK] = &spi0_i2s_bclk.common.hw,
1265 [CLK_APBC_SPI1_I2S_BCLK] = &spi1_i2s_bclk.common.hw,
1266 [CLK_APBC_SPI3_I2S_BCLK] = &spi3_i2s_bclk.common.hw,
1267 [CLK_APBC_SPI0] = &spi0_clk.common.hw,
1268 [CLK_APBC_SPI1] = &spi1_clk.common.hw,
1269 [CLK_APBC_SPI3] = &spi3_clk.common.hw,
1270 [CLK_APBC_SPI0_BUS] = &spi0_bus_clk.common.hw,
1271 [CLK_APBC_SPI1_BUS] = &spi1_bus_clk.common.hw,
1272 [CLK_APBC_SPI3_BUS] = &spi3_bus_clk.common.hw,
1273 [CLK_APBC_RTC] = &rtc_clk.common.hw,
1274 [CLK_APBC_RTC_BUS] = &rtc_bus_clk.common.hw,
1275 [CLK_APBC_TWSI0] = &twsi0_clk.common.hw,
1276 [CLK_APBC_TWSI1] = &twsi1_clk.common.hw,
1277 [CLK_APBC_TWSI2] = &twsi2_clk.common.hw,
1278 [CLK_APBC_TWSI4] = &twsi4_clk.common.hw,
1279 [CLK_APBC_TWSI5] = &twsi5_clk.common.hw,
1280 [CLK_APBC_TWSI6] = &twsi6_clk.common.hw,
1281 [CLK_APBC_TWSI8] = &twsi8_clk.common.hw,
1282 [CLK_APBC_TWSI0_BUS] = &twsi0_bus_clk.common.hw,
1283 [CLK_APBC_TWSI1_BUS] = &twsi1_bus_clk.common.hw,
1284 [CLK_APBC_TWSI2_BUS] = &twsi2_bus_clk.common.hw,
1285 [CLK_APBC_TWSI4_BUS] = &twsi4_bus_clk.common.hw,
1286 [CLK_APBC_TWSI5_BUS] = &twsi5_bus_clk.common.hw,
1287 [CLK_APBC_TWSI6_BUS] = &twsi6_bus_clk.common.hw,
1288 [CLK_APBC_TWSI8_BUS] = &twsi8_bus_clk.common.hw,
1289 [CLK_APBC_TIMERS0] = &timers0_clk.common.hw,
1290 [CLK_APBC_TIMERS1] = &timers1_clk.common.hw,
1291 [CLK_APBC_TIMERS2] = &timers2_clk.common.hw,
1292 [CLK_APBC_TIMERS3] = &timers3_clk.common.hw,
1293 [CLK_APBC_TIMERS4] = &timers4_clk.common.hw,
1294 [CLK_APBC_TIMERS5] = &timers5_clk.common.hw,
1295 [CLK_APBC_TIMERS6] = &timers6_clk.common.hw,
1296 [CLK_APBC_TIMERS7] = &timers7_clk.common.hw,
1297 [CLK_APBC_TIMERS0_BUS] = &timers0_bus_clk.common.hw,
1298 [CLK_APBC_TIMERS1_BUS] = &timers1_bus_clk.common.hw,
1299 [CLK_APBC_TIMERS2_BUS] = &timers2_bus_clk.common.hw,
1300 [CLK_APBC_TIMERS3_BUS] = &timers3_bus_clk.common.hw,
1301 [CLK_APBC_TIMERS4_BUS] = &timers4_bus_clk.common.hw,
1302 [CLK_APBC_TIMERS5_BUS] = &timers5_bus_clk.common.hw,
1303 [CLK_APBC_TIMERS6_BUS] = &timers6_bus_clk.common.hw,
1304 [CLK_APBC_TIMERS7_BUS] = &timers7_bus_clk.common.hw,
1305 [CLK_APBC_AIB] = &aib_clk.common.hw,
1306 [CLK_APBC_AIB_BUS] = &aib_bus_clk.common.hw,
1307 [CLK_APBC_ONEWIRE] = &onewire_clk.common.hw,
1308 [CLK_APBC_ONEWIRE_BUS] = &onewire_bus_clk.common.hw,
1309 [CLK_APBC_I2S0_BCLK] = &i2s0_i2s_bclk.common.hw,
1310 [CLK_APBC_I2S1_BCLK] = &i2s1_i2s_bclk.common.hw,
1311 [CLK_APBC_I2S2_BCLK] = &i2s2_i2s_bclk.common.hw,
1312 [CLK_APBC_I2S3_BCLK] = &i2s3_i2s_bclk.common.hw,
1313 [CLK_APBC_I2S4_BCLK] = &i2s4_i2s_bclk.common.hw,
1314 [CLK_APBC_I2S5_BCLK] = &i2s5_i2s_bclk.common.hw,
1315 [CLK_APBC_I2S0] = &i2s0_clk.common.hw,
1316 [CLK_APBC_I2S1] = &i2s1_clk.common.hw,
1317 [CLK_APBC_I2S2] = &i2s2_clk.common.hw,
1318 [CLK_APBC_I2S3] = &i2s3_clk.common.hw,
1319 [CLK_APBC_I2S4] = &i2s4_clk.common.hw,
1320 [CLK_APBC_I2S5] = &i2s5_clk.common.hw,
1321 [CLK_APBC_I2S0_BUS] = &i2s0_bus_clk.common.hw,
1322 [CLK_APBC_I2S1_BUS] = &i2s1_bus_clk.common.hw,
1323 [CLK_APBC_I2S2_BUS] = &i2s2_bus_clk.common.hw,
1324 [CLK_APBC_I2S3_BUS] = &i2s3_bus_clk.common.hw,
1325 [CLK_APBC_I2S4_BUS] = &i2s4_bus_clk.common.hw,
1326 [CLK_APBC_I2S5_BUS] = &i2s5_bus_clk.common.hw,
1327 [CLK_APBC_DRO] = &dro_clk.common.hw,
1328 [CLK_APBC_IR0] = &ir0_clk.common.hw,
1329 [CLK_APBC_IR1] = &ir1_clk.common.hw,
1330 [CLK_APBC_TSEN] = &tsen_clk.common.hw,
1331 [CLK_APBC_TSEN_BUS] = &tsen_bus_clk.common.hw,
1332 [CLK_APBC_IPC_AP2RCPU] = &ipc_ap2rcpu_clk.common.hw,
1333 [CLK_APBC_IPC_AP2RCPU_BUS] = &ipc_ap2rcpu_bus_clk.common.hw,
1334 [CLK_APBC_CAN0] = &can0_clk.common.hw,
1335 [CLK_APBC_CAN1] = &can1_clk.common.hw,
1336 [CLK_APBC_CAN2] = &can2_clk.common.hw,
1337 [CLK_APBC_CAN3] = &can3_clk.common.hw,
1338 [CLK_APBC_CAN4] = &can4_clk.common.hw,
1339 [CLK_APBC_CAN0_BUS] = &can0_bus_clk.common.hw,
1340 [CLK_APBC_CAN1_BUS] = &can1_bus_clk.common.hw,
1341 [CLK_APBC_CAN2_BUS] = &can2_bus_clk.common.hw,
1342 [CLK_APBC_CAN3_BUS] = &can3_bus_clk.common.hw,
1343 [CLK_APBC_CAN4_BUS] = &can4_bus_clk.common.hw,
1344 };
1345
1346 static const struct spacemit_ccu_data k3_ccu_apbc_data = {
1347 .reset_name = "k3-apbc-reset",
1348 .hws = k3_ccu_apbc_hws,
1349 .num = ARRAY_SIZE(k3_ccu_apbc_hws),
1350 };
1351
1352 static struct clk_hw *k3_ccu_apmu_hws[] = {
1353 [CLK_APMU_AXICLK] = &axi_clk.common.hw,
1354 [CLK_APMU_CCI550] = &cci550_clk.common.hw,
1355 [CLK_APMU_CPU_C0_CORE] = &cpu_c0_core_clk.common.hw,
1356 [CLK_APMU_CPU_C1_CORE] = &cpu_c1_core_clk.common.hw,
1357 [CLK_APMU_CPU_C2_CORE] = &cpu_c2_core_clk.common.hw,
1358 [CLK_APMU_CPU_C3_CORE] = &cpu_c3_core_clk.common.hw,
1359 [CLK_APMU_CCIC2PHY] = &ccic2phy_clk.common.hw,
1360 [CLK_APMU_CCIC3PHY] = &ccic3phy_clk.common.hw,
1361 [CLK_APMU_CSI] = &csi_clk.common.hw,
1362 [CLK_APMU_ISP_BUS] = &isp_bus_clk.common.hw,
1363 [CLK_APMU_D1P_1228P8] = &d1p_1228p8.common.hw,
1364 [CLK_APMU_D1P_819P2] = &d1p_819p2.common.hw,
1365 [CLK_APMU_D1P_614P4] = &d1p_614p4.common.hw,
1366 [CLK_APMU_D1P_491P52] = &d1p_491p52.common.hw,
1367 [CLK_APMU_D1P_409P6] = &d1p_409p6.common.hw,
1368 [CLK_APMU_D1P_307P2] = &d1p_307p2.common.hw,
1369 [CLK_APMU_D1P_245P76] = &d1p_245p76.common.hw,
1370 [CLK_APMU_V2D] = &v2d_clk.common.hw,
1371 [CLK_APMU_DSI_ESC] = &dsi_esc_clk.common.hw,
1372 [CLK_APMU_LCD_HCLK] = &lcd_hclk.common.hw,
1373 [CLK_APMU_LCD_DSC] = &lcd_dsc_clk.common.hw,
1374 [CLK_APMU_LCD_PXCLK] = &lcd_pxclk.common.hw,
1375 [CLK_APMU_LCD_MCLK] = &lcd_mclk.common.hw,
1376 [CLK_APMU_CCIC_4X] = &ccic_4x_clk.common.hw,
1377 [CLK_APMU_CCIC1PHY] = &ccic1phy_clk.common.hw,
1378 [CLK_APMU_SC2_HCLK] = &sc2_hclk.common.hw,
1379 [CLK_APMU_SDH_AXI] = &sdh_axi_aclk.common.hw,
1380 [CLK_APMU_SDH0] = &sdh0_clk.common.hw,
1381 [CLK_APMU_SDH1] = &sdh1_clk.common.hw,
1382 [CLK_APMU_SDH2] = &sdh2_clk.common.hw,
1383 [CLK_APMU_USB2_BUS] = &usb2_bus_clk.common.hw,
1384 [CLK_APMU_USB3_PORTA_BUS] = &usb3_porta_bus_clk.common.hw,
1385 [CLK_APMU_USB3_PORTB_BUS] = &usb3_portb_bus_clk.common.hw,
1386 [CLK_APMU_USB3_PORTC_BUS] = &usb3_portc_bus_clk.common.hw,
1387 [CLK_APMU_USB3_PORTD_BUS] = &usb3_portd_bus_clk.common.hw,
1388 [CLK_APMU_QSPI] = &qspi_clk.common.hw,
1389 [CLK_APMU_QSPI_BUS] = &qspi_bus_clk.common.hw,
1390 [CLK_APMU_DMA] = &dma_clk.common.hw,
1391 [CLK_APMU_AES_WTM] = &aes_wtm_clk.common.hw,
1392 [CLK_APMU_VPU] = &vpu_clk.common.hw,
1393 [CLK_APMU_DTC] = &dtc_clk.common.hw,
1394 [CLK_APMU_GPU] = &gpu_clk.common.hw,
1395 [CLK_APMU_MC_AHB] = &mc_ahb_clk.common.hw,
1396 [CLK_APMU_TOP_DCLK] = &top_dclk.common.hw,
1397 [CLK_APMU_UCIE] = &ucie_clk.common.hw,
1398 [CLK_APMU_UCIE_SBCLK] = &ucie_sbclk.common.hw,
1399 [CLK_APMU_RCPU] = &rcpu_clk.common.hw,
1400 [CLK_APMU_DSI4LN2_DSI_ESC] = &dsi4ln2_dsi_esc_clk.common.hw,
1401 [CLK_APMU_DSI4LN2_LCD_DSC] = &dsi4ln2_lcd_dsc_clk.common.hw,
1402 [CLK_APMU_DSI4LN2_LCD_PXCLK] = &dsi4ln2_lcd_pxclk.common.hw,
1403 [CLK_APMU_DSI4LN2_LCD_MCLK] = &dsi4ln2_lcd_mclk.common.hw,
1404 [CLK_APMU_DSI4LN2_DPU_ACLK] = &dsi4ln2_dpu_aclk.common.hw,
1405 [CLK_APMU_DPU_ACLK] = &dpu_aclk.common.hw,
1406 [CLK_APMU_UFS_ACLK] = &ufs_aclk.common.hw,
1407 [CLK_APMU_UFS_REFCLK] = &ufs_refclk.common.hw,
1408 [CLK_APMU_EDP0_PXCLK] = &edp0_pxclk.common.hw,
1409 [CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw,
1410 [CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw,
1411 [CLK_APMU_PCIE_PORTA_SLV] = &pciea_slv_clk.common.hw,
1412 [CLK_APMU_PCIE_PORTA_DBI] = &pciea_dbi_clk.common.hw,
1413 [CLK_APMU_PCIE_PORTB_MSTE] = &pcieb_mstr_clk.common.hw,
1414 [CLK_APMU_PCIE_PORTB_SLV] = &pcieb_slv_clk.common.hw,
1415 [CLK_APMU_PCIE_PORTB_DBI] = &pcieb_dbi_clk.common.hw,
1416 [CLK_APMU_PCIE_PORTC_MSTE] = &pciec_mstr_clk.common.hw,
1417 [CLK_APMU_PCIE_PORTC_SLV] = &pciec_slv_clk.common.hw,
1418 [CLK_APMU_PCIE_PORTC_DBI] = &pciec_dbi_clk.common.hw,
1419 [CLK_APMU_PCIE_PORTD_MSTE] = &pcied_mstr_clk.common.hw,
1420 [CLK_APMU_PCIE_PORTD_SLV] = &pcied_slv_clk.common.hw,
1421 [CLK_APMU_PCIE_PORTD_DBI] = &pcied_dbi_clk.common.hw,
1422 [CLK_APMU_PCIE_PORTE_MSTE] = &pciee_mstr_clk.common.hw,
1423 [CLK_APMU_PCIE_PORTE_SLV] = &pciee_slv_clk.common.hw,
1424 [CLK_APMU_PCIE_PORTE_DBI] = &pciee_dbi_clk.common.hw,
1425 [CLK_APMU_EMAC0_BUS] = &emac0_bus_clk.common.hw,
1426 [CLK_APMU_EMAC0_REF] = &emac0_ref_clk.common.hw,
1427 [CLK_APMU_EMAC0_1588] = &emac0_1588_clk.common.hw,
1428 [CLK_APMU_EMAC0_RGMII_TX] = &emac0_rgmii_tx_clk.common.hw,
1429 [CLK_APMU_EMAC1_BUS] = &emac1_bus_clk.common.hw,
1430 [CLK_APMU_EMAC1_REF] = &emac1_ref_clk.common.hw,
1431 [CLK_APMU_EMAC1_1588] = &emac1_1588_clk.common.hw,
1432 [CLK_APMU_EMAC1_RGMII_TX] = &emac1_rgmii_tx_clk.common.hw,
1433 [CLK_APMU_EMAC2_BUS] = &emac2_bus_clk.common.hw,
1434 [CLK_APMU_EMAC2_REF] = &emac2_ref_clk.common.hw,
1435 [CLK_APMU_EMAC2_1588] = &emac2_1588_clk.common.hw,
1436 [CLK_APMU_EMAC2_RGMII_TX] = &emac2_rgmii_tx_clk.common.hw,
1437 [CLK_APMU_ESPI_SCLK_SRC] = &espi_sclk_src.common.hw,
1438 [CLK_APMU_ESPI_SCLK] = &espi_sclk.common.hw,
1439 [CLK_APMU_ESPI_MCLK] = &espi_mclk.common.hw,
1440 [CLK_APMU_CAM_SRC1] = &cam_src1_clk.common.hw,
1441 [CLK_APMU_CAM_SRC2] = &cam_src2_clk.common.hw,
1442 [CLK_APMU_CAM_SRC3] = &cam_src3_clk.common.hw,
1443 [CLK_APMU_CAM_SRC4] = &cam_src4_clk.common.hw,
1444 [CLK_APMU_ISIM_VCLK0] = &isim_vclk_out0.common.hw,
1445 [CLK_APMU_ISIM_VCLK1] = &isim_vclk_out1.common.hw,
1446 [CLK_APMU_ISIM_VCLK2] = &isim_vclk_out2.common.hw,
1447 [CLK_APMU_ISIM_VCLK3] = &isim_vclk_out3.common.hw,
1448 };
1449
1450 static const struct spacemit_ccu_data k3_ccu_apmu_data = {
1451 .reset_name = "k3-apmu-reset",
1452 .hws = k3_ccu_apmu_hws,
1453 .num = ARRAY_SIZE(k3_ccu_apmu_hws),
1454 };
1455
1456 static struct clk_hw *k3_ccu_dciu_hws[] = {
1457 [CLK_DCIU_HDMA] = &hdma_clk.common.hw,
1458 [CLK_DCIU_DMA350] = &dma350_clk.common.hw,
1459 [CLK_DCIU_C2_TCM_PIPE] = &c2_tcm_pipe_clk.common.hw,
1460 [CLK_DCIU_C3_TCM_PIPE] = &c3_tcm_pipe_clk.common.hw,
1461 };
1462
1463 static const struct spacemit_ccu_data k3_ccu_dciu_data = {
1464 .reset_name = "k3-dciu-reset",
1465 .hws = k3_ccu_dciu_hws,
1466 .num = ARRAY_SIZE(k3_ccu_dciu_hws),
1467 };
1468
1469 static const struct of_device_id of_k3_ccu_match[] = {
1470 {
1471 .compatible = "spacemit,k3-pll",
1472 .data = &k3_ccu_pll_data,
1473 },
1474 {
1475 .compatible = "spacemit,k3-syscon-mpmu",
1476 .data = &k3_ccu_mpmu_data,
1477 },
1478 {
1479 .compatible = "spacemit,k3-syscon-apbc",
1480 .data = &k3_ccu_apbc_data,
1481 },
1482 {
1483 .compatible = "spacemit,k3-syscon-apmu",
1484 .data = &k3_ccu_apmu_data,
1485 },
1486 {
1487 .compatible = "spacemit,k3-syscon-dciu",
1488 .data = &k3_ccu_dciu_data,
1489 },
1490 { /* sentinel */ }
1491 };
1492 MODULE_DEVICE_TABLE(of, of_k3_ccu_match);
1493
k3_ccu_probe(struct platform_device * pdev)1494 static int k3_ccu_probe(struct platform_device *pdev)
1495 {
1496 return spacemit_ccu_probe(pdev, "spacemit,k3-pll");
1497 }
1498
1499 static struct platform_driver k3_ccu_driver = {
1500 .driver = {
1501 .name = "spacemit,k3-ccu",
1502 .of_match_table = of_k3_ccu_match,
1503 },
1504 .probe = k3_ccu_probe,
1505 };
1506 module_platform_driver(k3_ccu_driver);
1507
1508 MODULE_IMPORT_NS("CLK_SPACEMIT");
1509 MODULE_DESCRIPTION("SpacemiT K3 CCU driver");
1510 MODULE_LICENSE("GPL");
1511