1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // Copyright(c) 2021-2022 Intel Corporation
4 //
5 // Authors: Cezary Rojewski <cezary.rojewski@intel.com>
6 // Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
7 //
8 // Special thanks to:
9 // Krzysztof Hejmowski <krzysztof.hejmowski@intel.com>
10 // Michal Sienkiewicz <michal.sienkiewicz@intel.com>
11 // Filip Proborszcz
12 //
13 // for sharing Intel AudioDSP expertise and helping shape the very
14 // foundation of this driver
15 //
16
17 #include <linux/cleanup.h>
18 #include <linux/acpi.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <acpi/nhlt.h>
22 #include <sound/hda_codec.h>
23 #include <sound/hda_i915.h>
24 #include <sound/hda_register.h>
25 #include <sound/hdaudio.h>
26 #include <sound/hdaudio_ext.h>
27 #include <sound/intel-dsp-config.h>
28 #include "../../codecs/hda.h"
29 #include "avs.h"
30 #include "cldma.h"
31 #include "debug.h"
32 #include "messages.h"
33 #include "pcm.h"
34
35 static u32 pgctl_mask = AZX_PGCTL_LSRMD_MASK;
36 module_param(pgctl_mask, uint, 0444);
37 MODULE_PARM_DESC(pgctl_mask, "PCI PGCTL policy override");
38
39 static u32 cgctl_mask = AZX_CGCTL_MISCBDCGE_MASK;
40 module_param(cgctl_mask, uint, 0444);
41 MODULE_PARM_DESC(cgctl_mask, "PCI CGCTL policy override");
42
43 static void
avs_hda_update_config_dword(struct hdac_bus * bus,u32 reg,u32 mask,u32 value)44 avs_hda_update_config_dword(struct hdac_bus *bus, u32 reg, u32 mask, u32 value)
45 {
46 struct pci_dev *pci = to_pci_dev(bus->dev);
47 u32 data;
48
49 pci_read_config_dword(pci, reg, &data);
50 data &= ~mask;
51 data |= (value & mask);
52 pci_write_config_dword(pci, reg, data);
53 }
54
avs_hda_power_gating_enable(struct avs_dev * adev,bool enable)55 void avs_hda_power_gating_enable(struct avs_dev *adev, bool enable)
56 {
57 u32 value = enable ? 0 : pgctl_mask;
58
59 if (!avs_platattr_test(adev, ACE))
60 avs_hda_update_config_dword(&adev->base.core, AZX_PCIREG_PGCTL, pgctl_mask, value);
61 }
62
avs_hdac_clock_gating_enable(struct hdac_bus * bus,bool enable)63 static void avs_hdac_clock_gating_enable(struct hdac_bus *bus, bool enable)
64 {
65 struct avs_dev *adev = hdac_to_avs(bus);
66 u32 value = enable ? cgctl_mask : 0;
67
68 if (!avs_platattr_test(adev, ACE))
69 avs_hda_update_config_dword(bus, AZX_PCIREG_CGCTL, cgctl_mask, value);
70 }
71
avs_hda_clock_gating_enable(struct avs_dev * adev,bool enable)72 void avs_hda_clock_gating_enable(struct avs_dev *adev, bool enable)
73 {
74 avs_hdac_clock_gating_enable(&adev->base.core, enable);
75 }
76
avs_hda_l1sen_enable(struct avs_dev * adev,bool enable)77 void avs_hda_l1sen_enable(struct avs_dev *adev, bool enable)
78 {
79 if (avs_platattr_test(adev, ACE))
80 return;
81 if (enable) {
82 if (atomic_inc_and_test(&adev->l1sen_counter))
83 snd_hdac_chip_updatel(&adev->base.core, VS_EM2, AZX_VS_EM2_L1SEN,
84 AZX_VS_EM2_L1SEN);
85 } else {
86 if (atomic_dec_return(&adev->l1sen_counter) == -1)
87 snd_hdac_chip_updatel(&adev->base.core, VS_EM2, AZX_VS_EM2_L1SEN, 0);
88 }
89 }
90
avs_hdac_bus_init_streams(struct hdac_bus * bus)91 static int avs_hdac_bus_init_streams(struct hdac_bus *bus)
92 {
93 unsigned int cp_streams, pb_streams;
94 unsigned int gcap;
95 int ret;
96
97 gcap = snd_hdac_chip_readw(bus, GCAP);
98 cp_streams = (gcap >> 8) & 0x0F;
99 pb_streams = (gcap >> 12) & 0x0F;
100 bus->num_streams = cp_streams + pb_streams;
101
102 ret = snd_hdac_ext_stream_init_all(bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE);
103 if (ret)
104 return ret;
105 ret = snd_hdac_ext_stream_init_all(bus, cp_streams, pb_streams, SNDRV_PCM_STREAM_PLAYBACK);
106 if (ret)
107 goto err;
108
109 ret = snd_hdac_bus_alloc_stream_pages(bus);
110 if (ret)
111 goto err;
112
113 return 0;
114 err:
115 snd_hdac_ext_stream_free_all(bus);
116 return ret;
117 }
118
avs_hdac_bus_init_chip(struct hdac_bus * bus,bool full_reset)119 static bool avs_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
120 {
121 struct avs_dev *adev = hdac_to_avs(bus);
122 struct hdac_ext_link *hlink;
123 bool ret;
124
125 avs_hdac_clock_gating_enable(bus, false);
126 ret = snd_hdac_bus_init_chip(bus, full_reset);
127
128 /* Reset stream-to-link mapping */
129 list_for_each_entry(hlink, &bus->hlink_list, list)
130 writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
131
132 avs_hdac_clock_gating_enable(bus, true);
133
134 /* Set DUM bit to address incorrect position reporting for capture
135 * streams. In order to do so, CTRL needs to be out of reset state
136 */
137 if (!avs_platattr_test(adev, ACE))
138 snd_hdac_chip_updatel(bus, VS_EM2, AZX_VS_EM2_DUM, AZX_VS_EM2_DUM);
139
140 return ret;
141 }
142
probe_codec(struct hdac_bus * bus,int addr)143 static int probe_codec(struct hdac_bus *bus, int addr)
144 {
145 struct hda_codec *codec;
146 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
147 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
148 unsigned int res = -1;
149 int ret;
150
151 mutex_lock(&bus->cmd_mutex);
152 snd_hdac_bus_send_cmd(bus, cmd);
153 snd_hdac_bus_get_response(bus, addr, &res);
154 mutex_unlock(&bus->cmd_mutex);
155 if (res == -1)
156 return -EIO;
157
158 dev_dbg(bus->dev, "codec #%d probed OK: 0x%x\n", addr, res);
159
160 codec = snd_hda_codec_device_init(to_hda_bus(bus), addr, "hdaudioB%dD%d", bus->idx, addr);
161 if (IS_ERR(codec)) {
162 dev_err(bus->dev, "init codec failed: %ld\n", PTR_ERR(codec));
163 return PTR_ERR(codec);
164 }
165 /*
166 * Allow avs_core suspend by forcing suspended state on all
167 * of its codec child devices. Component interested in
168 * dealing with hda codecs directly takes pm responsibilities
169 */
170 pm_runtime_set_suspended(hda_codec_dev(codec));
171
172 /* configure effectively creates new ASoC component */
173 ret = snd_hda_codec_configure(codec);
174 if (ret < 0) {
175 dev_warn(bus->dev, "failed to config codec #%d: %d\n", addr, ret);
176 return ret;
177 }
178
179 return 0;
180 }
181
avs_hdac_bus_probe_codecs(struct hdac_bus * bus)182 static void avs_hdac_bus_probe_codecs(struct hdac_bus *bus)
183 {
184 int ret, c;
185
186 /* First try to probe all given codec slots */
187 for (c = 0; c < HDA_MAX_CODECS; c++) {
188 if (!(bus->codec_mask & BIT(c)))
189 continue;
190
191 ret = probe_codec(bus, c);
192 /* Ignore codecs with no supporting driver. */
193 if (!ret || ret == -ENODEV)
194 continue;
195
196 /*
197 * Some BIOSen give you wrong codec addresses
198 * that don't exist
199 */
200 dev_warn(bus->dev, "Codec #%d probe error; disabling it...\n", c);
201 bus->codec_mask &= ~BIT(c);
202 /*
203 * More badly, accessing to a non-existing
204 * codec often screws up the controller bus,
205 * and disturbs the further communications.
206 * Thus if an error occurs during probing,
207 * better to reset the controller bus to get
208 * back to the sanity state.
209 */
210 snd_hdac_bus_stop_chip(bus);
211 avs_hdac_bus_init_chip(bus, true);
212 }
213 }
214
avs_hda_probe_work(struct work_struct * work)215 static void avs_hda_probe_work(struct work_struct *work)
216 {
217 struct avs_dev *adev = container_of(work, struct avs_dev, probe_work);
218 struct hdac_bus *bus = &adev->base.core;
219 struct hdac_ext_link *hlink;
220 int ret;
221
222 pm_runtime_set_active(bus->dev); /* clear runtime_error flag */
223
224 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true);
225 avs_hdac_bus_init_chip(bus, true);
226 avs_hdac_bus_probe_codecs(bus);
227 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
228
229 /* with all codecs probed, links can be powered down */
230 list_for_each_entry(hlink, &bus->hlink_list, list)
231 snd_hdac_ext_bus_link_put(bus, hlink);
232
233 snd_hdac_ext_bus_ppcap_enable(bus, true);
234 snd_hdac_ext_bus_ppcap_int_enable(bus, true);
235 avs_debugfs_init(adev);
236
237 ret = avs_dsp_first_boot_firmware(adev);
238 if (ret < 0)
239 return;
240
241 acpi_nhlt_get_gbl_table();
242
243 avs_register_all_boards(adev);
244
245 /* configure PM */
246 pm_runtime_set_autosuspend_delay(bus->dev, 2000);
247 pm_runtime_use_autosuspend(bus->dev);
248 pm_runtime_put_autosuspend(bus->dev);
249 pm_runtime_allow(bus->dev);
250 }
251
hdac_stream_update_pos(struct hdac_stream * stream,u64 buffer_size)252 static void hdac_stream_update_pos(struct hdac_stream *stream, u64 buffer_size)
253 {
254 u64 prev_pos, pos, num_bytes;
255
256 div64_u64_rem(stream->curr_pos, buffer_size, &prev_pos);
257 pos = snd_hdac_stream_get_pos_posbuf(stream);
258
259 if (pos < prev_pos)
260 num_bytes = (buffer_size - prev_pos) + pos;
261 else
262 num_bytes = pos - prev_pos;
263
264 stream->curr_pos += num_bytes;
265 }
266
267 /* called from IRQ */
hdac_update_stream(struct hdac_bus * bus,struct hdac_stream * stream)268 static void hdac_update_stream(struct hdac_bus *bus, struct hdac_stream *stream)
269 {
270 if (stream->substream) {
271 avs_period_elapsed(stream->substream);
272 } else if (stream->cstream) {
273 u64 buffer_size = stream->cstream->runtime->buffer_size;
274
275 hdac_stream_update_pos(stream, buffer_size);
276 snd_compr_fragment_elapsed(stream->cstream);
277 }
278 }
279
avs_hda_interrupt(struct hdac_bus * bus)280 static irqreturn_t avs_hda_interrupt(struct hdac_bus *bus)
281 {
282 irqreturn_t ret = IRQ_NONE;
283 u32 status;
284
285 status = snd_hdac_chip_readl(bus, INTSTS);
286 if (snd_hdac_bus_handle_stream_irq(bus, status, hdac_update_stream))
287 ret = IRQ_HANDLED;
288
289 guard(spinlock_irq)(&bus->reg_lock);
290 /* Clear RIRB interrupt. */
291 status = snd_hdac_chip_readb(bus, RIRBSTS);
292 if (status & RIRB_INT_MASK) {
293 if (status & RIRB_INT_RESPONSE)
294 snd_hdac_bus_update_rirb(bus);
295 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
296 ret = IRQ_HANDLED;
297 }
298
299 return ret;
300 }
301
avs_hda_irq_handler(int irq,void * dev_id)302 static irqreturn_t avs_hda_irq_handler(int irq, void *dev_id)
303 {
304 struct hdac_bus *bus = dev_id;
305 u32 intsts;
306
307 intsts = snd_hdac_chip_readl(bus, INTSTS);
308 if (intsts == UINT_MAX || !(intsts & AZX_INT_GLOBAL_EN))
309 return IRQ_NONE;
310
311 /* Mask GIE, unmasked in irq_thread(). */
312 snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_GLOBAL_EN, 0);
313
314 return IRQ_WAKE_THREAD;
315 }
316
avs_hda_irq_thread(int irq,void * dev_id)317 static irqreturn_t avs_hda_irq_thread(int irq, void *dev_id)
318 {
319 struct hdac_bus *bus = dev_id;
320 u32 status;
321
322 status = snd_hdac_chip_readl(bus, INTSTS);
323 if (status & ~AZX_INT_GLOBAL_EN)
324 avs_hda_interrupt(bus);
325
326 /* Unmask GIE, masked in irq_handler(). */
327 snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_GLOBAL_EN, AZX_INT_GLOBAL_EN);
328
329 return IRQ_HANDLED;
330 }
331
avs_dsp_irq_handler(int irq,void * dev_id)332 static irqreturn_t avs_dsp_irq_handler(int irq, void *dev_id)
333 {
334 struct avs_dev *adev = dev_id;
335
336 return avs_hda_irq_handler(irq, &adev->base.core);
337 }
338
avs_dsp_irq_thread(int irq,void * dev_id)339 static irqreturn_t avs_dsp_irq_thread(int irq, void *dev_id)
340 {
341 struct avs_dev *adev = dev_id;
342 struct hdac_bus *bus = &adev->base.core;
343 u32 status;
344
345 status = readl(bus->ppcap + AZX_REG_PP_PPSTS);
346 if (status & AZX_PPCTL_PIE)
347 avs_dsp_op(adev, dsp_interrupt);
348
349 /* Unmask GIE, masked in irq_handler(). */
350 snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_GLOBAL_EN, AZX_INT_GLOBAL_EN);
351
352 return IRQ_HANDLED;
353 }
354
avs_hdac_acquire_irq(struct avs_dev * adev)355 static int avs_hdac_acquire_irq(struct avs_dev *adev)
356 {
357 struct hdac_bus *bus = &adev->base.core;
358 struct pci_dev *pci = to_pci_dev(bus->dev);
359 int ret;
360
361 /* request one and check that we only got one interrupt */
362 ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_MSI | PCI_IRQ_INTX);
363 if (ret != 1) {
364 dev_err(adev->dev, "Failed to allocate IRQ vector: %d\n", ret);
365 return ret;
366 }
367
368 ret = pci_request_irq(pci, 0, avs_hda_irq_handler, avs_hda_irq_thread, bus,
369 KBUILD_MODNAME);
370 if (ret < 0) {
371 dev_err(adev->dev, "Failed to request stream IRQ handler: %d\n", ret);
372 goto free_vector;
373 }
374
375 ret = pci_request_irq(pci, 0, avs_dsp_irq_handler, avs_dsp_irq_thread, adev,
376 KBUILD_MODNAME);
377 if (ret < 0) {
378 dev_err(adev->dev, "Failed to request IPC IRQ handler: %d\n", ret);
379 goto free_stream_irq;
380 }
381
382 return 0;
383
384 free_stream_irq:
385 pci_free_irq(pci, 0, bus);
386 free_vector:
387 pci_free_irq_vectors(pci);
388 return ret;
389 }
390
avs_bus_init(struct avs_dev * adev,struct pci_dev * pci,const struct pci_device_id * id)391 static int avs_bus_init(struct avs_dev *adev, struct pci_dev *pci, const struct pci_device_id *id)
392 {
393 struct hda_bus *bus = &adev->base;
394 struct avs_ipc *ipc;
395 struct device *dev = &pci->dev;
396 int ret;
397
398 ipc = devm_kzalloc(dev, sizeof(*ipc), GFP_KERNEL);
399 if (!ipc)
400 return -ENOMEM;
401
402 adev->modcfg_buf = devm_kzalloc(dev, AVS_MAILBOX_SIZE, GFP_KERNEL);
403 if (!adev->modcfg_buf)
404 return -ENOMEM;
405
406 ret = avs_ipc_init(ipc, dev);
407 if (ret < 0)
408 return ret;
409
410 ret = snd_hdac_ext_bus_init(&bus->core, dev, NULL, &soc_hda_ext_bus_ops);
411 if (ret < 0)
412 return ret;
413
414 bus->core.use_posbuf = 1;
415 bus->core.bdl_pos_adj = 0;
416 bus->core.sync_write = 1;
417 bus->pci = pci;
418 bus->mixer_assigned = -1;
419 mutex_init(&bus->prepare_mutex);
420
421 adev->dev = dev;
422 adev->spec = (const struct avs_spec *)id->driver_data;
423 adev->ipc = ipc;
424 adev->hw_cfg.dsp_cores = hweight_long(AVS_MAIN_CORE_MASK);
425 INIT_WORK(&adev->probe_work, avs_hda_probe_work);
426 INIT_LIST_HEAD(&adev->comp_list);
427 INIT_LIST_HEAD(&adev->path_list);
428 INIT_LIST_HEAD(&adev->fw_list);
429 init_completion(&adev->fw_ready);
430 spin_lock_init(&adev->path_list_lock);
431 mutex_init(&adev->modres_mutex);
432 mutex_init(&adev->comp_list_mutex);
433 mutex_init(&adev->path_mutex);
434
435 return 0;
436 }
437
avs_pci_probe(struct pci_dev * pci,const struct pci_device_id * id)438 static int avs_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
439 {
440 struct hdac_bus *bus;
441 struct avs_dev *adev;
442 struct device *dev = &pci->dev;
443 int ret;
444
445 ret = snd_intel_dsp_driver_probe(pci);
446 switch (ret) {
447 case SND_INTEL_DSP_DRIVER_ANY:
448 case SND_INTEL_DSP_DRIVER_SST:
449 case SND_INTEL_DSP_DRIVER_AVS:
450 break;
451 default:
452 return -ENODEV;
453 }
454
455 ret = pcim_enable_device(pci);
456 if (ret < 0)
457 return ret;
458
459 adev = devm_kzalloc(dev, sizeof(*adev), GFP_KERNEL);
460 if (!adev)
461 return -ENOMEM;
462 bus = &adev->base.core;
463
464 ret = avs_bus_init(adev, pci, id);
465 if (ret < 0) {
466 dev_err(dev, "failed to init avs bus: %d\n", ret);
467 return ret;
468 }
469
470 ret = pcim_request_all_regions(pci, "AVS HDAudio");
471 if (ret < 0)
472 goto err_request_regions;
473
474 bus->addr = pci_resource_start(pci, 0);
475 bus->remap_addr = pci_ioremap_bar(pci, 0);
476 if (!bus->remap_addr) {
477 dev_err(bus->dev, "ioremap error\n");
478 ret = -ENXIO;
479 goto err_request_regions;
480 }
481
482 adev->dsp_ba = pci_ioremap_bar(pci, 4);
483 if (!adev->dsp_ba) {
484 dev_err(bus->dev, "ioremap error\n");
485 ret = -ENXIO;
486 goto err_remap_bar4;
487 }
488
489 snd_hdac_bus_parse_capabilities(bus);
490 if (bus->mlcap) {
491 ret = snd_hdac_ext_bus_get_ml_capabilities(bus);
492 if (ret < 0) {
493 dev_err(dev, "failed to get ml capabilities: %d\n", ret);
494 goto err_ml_cap;
495 }
496 }
497
498 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)))
499 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
500 dma_set_max_seg_size(dev, UINT_MAX);
501
502 ret = avs_hdac_bus_init_streams(bus);
503 if (ret < 0) {
504 dev_err(dev, "failed to init streams: %d\n", ret);
505 goto err_init_streams;
506 }
507
508 ret = avs_hdac_acquire_irq(adev);
509 if (ret < 0) {
510 dev_err(bus->dev, "failed to acquire irq: %d\n", ret);
511 goto err_acquire_irq;
512 }
513
514 pci_set_master(pci);
515 pci_set_drvdata(pci, bus);
516 device_disable_async_suspend(dev);
517
518 ret = snd_hdac_i915_init(bus);
519 if (ret == -EPROBE_DEFER)
520 goto err_i915_init;
521 else if (ret < 0)
522 dev_info(bus->dev, "i915 init unsuccessful: %d\n", ret);
523
524 schedule_work(&adev->probe_work);
525
526 return 0;
527
528 err_i915_init:
529 pci_free_irq(pci, 0, adev);
530 pci_free_irq(pci, 0, bus);
531 pci_free_irq_vectors(pci);
532 pci_clear_master(pci);
533 pci_set_drvdata(pci, NULL);
534 err_acquire_irq:
535 snd_hdac_bus_free_stream_pages(bus);
536 snd_hdac_ext_stream_free_all(bus);
537 err_init_streams:
538 snd_hdac_ext_link_free_all(bus);
539 err_ml_cap:
540 iounmap(adev->dsp_ba);
541 err_remap_bar4:
542 iounmap(bus->remap_addr);
543 err_request_regions:
544 snd_hdac_ext_bus_exit(bus);
545 return ret;
546 }
547
avs_pci_shutdown(struct pci_dev * pci)548 static void avs_pci_shutdown(struct pci_dev *pci)
549 {
550 struct hdac_bus *bus = pci_get_drvdata(pci);
551 struct avs_dev *adev = hdac_to_avs(bus);
552
553 cancel_work_sync(&adev->probe_work);
554 avs_ipc_block(adev->ipc);
555
556 snd_hdac_stop_streams(bus);
557 avs_dsp_op(adev, int_control, false);
558 snd_hdac_ext_bus_ppcap_int_enable(bus, false);
559 snd_hdac_ext_bus_link_power_down_all(bus);
560
561 snd_hdac_bus_stop_chip(bus);
562 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
563
564 pci_free_irq(pci, 0, adev);
565 pci_free_irq(pci, 0, bus);
566 pci_free_irq_vectors(pci);
567 }
568
avs_pci_remove(struct pci_dev * pci)569 static void avs_pci_remove(struct pci_dev *pci)
570 {
571 struct hdac_device *hdev, *save;
572 struct hdac_bus *bus = pci_get_drvdata(pci);
573 struct avs_dev *adev = hdac_to_avs(bus);
574
575 cancel_work_sync(&adev->probe_work);
576 avs_ipc_block(adev->ipc);
577
578 avs_unregister_all_boards(adev);
579
580 acpi_nhlt_put_gbl_table();
581 avs_debugfs_exit(adev);
582
583 if (avs_platattr_test(adev, CLDMA))
584 hda_cldma_free(&code_loader);
585
586 snd_hdac_stop_streams_and_chip(bus);
587 avs_dsp_op(adev, int_control, false);
588 snd_hdac_ext_bus_ppcap_int_enable(bus, false);
589
590 /* it is safe to remove all codecs from the system now */
591 list_for_each_entry_safe(hdev, save, &bus->codec_list, list)
592 snd_hda_codec_unregister(hdac_to_hda_codec(hdev));
593
594 snd_hdac_bus_free_stream_pages(bus);
595 snd_hdac_ext_stream_free_all(bus);
596 /* reverse ml_capabilities */
597 snd_hdac_ext_link_free_all(bus);
598 snd_hdac_ext_bus_exit(bus);
599
600 avs_dsp_core_disable(adev, GENMASK(adev->hw_cfg.dsp_cores - 1, 0));
601 snd_hdac_ext_bus_ppcap_enable(bus, false);
602
603 /* snd_hdac_stop_streams_and_chip does that already? */
604 snd_hdac_bus_stop_chip(bus);
605 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
606 if (bus->audio_component)
607 snd_hdac_i915_exit(bus);
608
609 avs_module_info_free(adev);
610 pci_free_irq(pci, 0, adev);
611 pci_free_irq(pci, 0, bus);
612 pci_free_irq_vectors(pci);
613 iounmap(bus->remap_addr);
614 iounmap(adev->dsp_ba);
615
616 /* Firmware is not needed anymore */
617 avs_release_firmwares(adev);
618
619 /* pm_runtime_forbid() can rpm_resume() which we do not want */
620 pm_runtime_disable(&pci->dev);
621 pm_runtime_forbid(&pci->dev);
622 pm_runtime_enable(&pci->dev);
623 pm_runtime_get_noresume(&pci->dev);
624 }
625
avs_suspend_standby(struct avs_dev * adev)626 static int avs_suspend_standby(struct avs_dev *adev)
627 {
628 struct hdac_bus *bus = &adev->base.core;
629 struct pci_dev *pci = adev->base.pci;
630
631 if (bus->cmd_dma_state)
632 snd_hdac_bus_stop_cmd_io(bus);
633
634 snd_hdac_ext_bus_link_power_down_all(bus);
635
636 enable_irq_wake(pci->irq);
637 pci_save_state(pci);
638
639 return 0;
640 }
641
avs_suspend_common(struct avs_dev * adev,bool low_power)642 static int avs_suspend_common(struct avs_dev *adev, bool low_power)
643 {
644 struct hdac_bus *bus = &adev->base.core;
645 int ret;
646
647 flush_work(&adev->probe_work);
648 if (low_power && adev->num_lp_paths)
649 return avs_suspend_standby(adev);
650
651 snd_hdac_ext_bus_link_power_down_all(bus);
652
653 ret = avs_ipc_set_dx(adev, AVS_MAIN_CORE_MASK, false);
654 /*
655 * pm_runtime is blocked on DSP failure but system-wide suspend is not.
656 * Do not block entire system from suspending if that's the case.
657 */
658 if (ret && ret != -EPERM) {
659 dev_err(adev->dev, "set dx failed: %d\n", ret);
660 return AVS_IPC_RET(ret);
661 }
662
663 avs_ipc_block(adev->ipc);
664 avs_dsp_op(adev, int_control, false);
665 snd_hdac_ext_bus_ppcap_int_enable(bus, false);
666
667 ret = avs_dsp_core_disable(adev, AVS_MAIN_CORE_MASK);
668 if (ret < 0) {
669 dev_err(adev->dev, "core_mask %ld disable failed: %d\n", AVS_MAIN_CORE_MASK, ret);
670 return ret;
671 }
672
673 snd_hdac_ext_bus_ppcap_enable(bus, false);
674 /* disable LP SRAM retention */
675 avs_hda_power_gating_enable(adev, false);
676 snd_hdac_bus_stop_chip(bus);
677 /* disable CG when putting controller to reset */
678 avs_hdac_clock_gating_enable(bus, false);
679 snd_hdac_bus_enter_link_reset(bus);
680 avs_hdac_clock_gating_enable(bus, true);
681
682 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
683
684 return 0;
685 }
686
avs_resume_standby(struct avs_dev * adev)687 static int avs_resume_standby(struct avs_dev *adev)
688 {
689 struct hdac_bus *bus = &adev->base.core;
690 struct pci_dev *pci = adev->base.pci;
691
692 pci_restore_state(pci);
693 disable_irq_wake(pci->irq);
694
695 snd_hdac_ext_bus_link_power_up_all(bus);
696
697 if (bus->cmd_dma_state)
698 snd_hdac_bus_init_cmd_io(bus);
699
700 return 0;
701 }
702
avs_resume_common(struct avs_dev * adev,bool low_power,bool purge)703 static int avs_resume_common(struct avs_dev *adev, bool low_power, bool purge)
704 {
705 struct hdac_bus *bus = &adev->base.core;
706 int ret;
707
708 if (low_power && adev->num_lp_paths)
709 return avs_resume_standby(adev);
710
711 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true);
712 avs_hdac_bus_init_chip(bus, true);
713
714 snd_hdac_ext_bus_ppcap_enable(bus, true);
715 snd_hdac_ext_bus_ppcap_int_enable(bus, true);
716
717 ret = avs_dsp_boot_firmware(adev, purge);
718 if (ret < 0) {
719 dev_err(adev->dev, "firmware boot failed: %d\n", ret);
720 return ret;
721 }
722
723 return 0;
724 }
725
avs_suspend(struct device * dev)726 static int avs_suspend(struct device *dev)
727 {
728 return avs_suspend_common(to_avs_dev(dev), true);
729 }
730
avs_resume(struct device * dev)731 static int avs_resume(struct device *dev)
732 {
733 return avs_resume_common(to_avs_dev(dev), true, true);
734 }
735
avs_runtime_suspend(struct device * dev)736 static int avs_runtime_suspend(struct device *dev)
737 {
738 return avs_suspend_common(to_avs_dev(dev), true);
739 }
740
avs_runtime_resume(struct device * dev)741 static int avs_runtime_resume(struct device *dev)
742 {
743 return avs_resume_common(to_avs_dev(dev), true, false);
744 }
745
avs_freeze(struct device * dev)746 static int avs_freeze(struct device *dev)
747 {
748 return avs_suspend_common(to_avs_dev(dev), false);
749 }
avs_thaw(struct device * dev)750 static int avs_thaw(struct device *dev)
751 {
752 return avs_resume_common(to_avs_dev(dev), false, true);
753 }
754
avs_poweroff(struct device * dev)755 static int avs_poweroff(struct device *dev)
756 {
757 return avs_suspend_common(to_avs_dev(dev), false);
758 }
759
avs_restore(struct device * dev)760 static int avs_restore(struct device *dev)
761 {
762 return avs_resume_common(to_avs_dev(dev), false, true);
763 }
764
765 static const struct dev_pm_ops avs_dev_pm = {
766 .suspend = avs_suspend,
767 .resume = avs_resume,
768 .freeze = avs_freeze,
769 .thaw = avs_thaw,
770 .poweroff = avs_poweroff,
771 .restore = avs_restore,
772 RUNTIME_PM_OPS(avs_runtime_suspend, avs_runtime_resume, NULL)
773 };
774
775 static const struct avs_sram_spec skl_sram_spec = {
776 .base_offset = SKL_ADSP_SRAM_BASE_OFFSET,
777 .window_size = SKL_ADSP_SRAM_WINDOW_SIZE,
778 };
779
780 static const struct avs_sram_spec apl_sram_spec = {
781 .base_offset = APL_ADSP_SRAM_BASE_OFFSET,
782 .window_size = APL_ADSP_SRAM_WINDOW_SIZE,
783 };
784
785 static const struct avs_sram_spec mtl_sram_spec = {
786 .base_offset = MTL_ADSP_SRAM_BASE_OFFSET,
787 .window_size = MTL_ADSP_SRAM_WINDOW_SIZE,
788 };
789
790 static const struct avs_hipc_spec skl_hipc_spec = {
791 .req_offset = SKL_ADSP_REG_HIPCI,
792 .req_ext_offset = SKL_ADSP_REG_HIPCIE,
793 .req_busy_mask = SKL_ADSP_HIPCI_BUSY,
794 .ack_offset = SKL_ADSP_REG_HIPCIE,
795 .ack_done_mask = SKL_ADSP_HIPCIE_DONE,
796 .rsp_offset = SKL_ADSP_REG_HIPCT,
797 .rsp_busy_mask = SKL_ADSP_HIPCT_BUSY,
798 .ctl_offset = SKL_ADSP_REG_HIPCCTL,
799 .sts_offset = SKL_ADSP_SRAM_BASE_OFFSET,
800 };
801
802 static const struct avs_hipc_spec apl_hipc_spec = {
803 .req_offset = SKL_ADSP_REG_HIPCI,
804 .req_ext_offset = SKL_ADSP_REG_HIPCIE,
805 .req_busy_mask = SKL_ADSP_HIPCI_BUSY,
806 .ack_offset = SKL_ADSP_REG_HIPCIE,
807 .ack_done_mask = SKL_ADSP_HIPCIE_DONE,
808 .rsp_offset = SKL_ADSP_REG_HIPCT,
809 .rsp_busy_mask = SKL_ADSP_HIPCT_BUSY,
810 .ctl_offset = SKL_ADSP_REG_HIPCCTL,
811 .sts_offset = APL_ADSP_SRAM_BASE_OFFSET,
812 };
813
814 static const struct avs_hipc_spec cnl_hipc_spec = {
815 .req_offset = CNL_ADSP_REG_HIPCIDR,
816 .req_ext_offset = CNL_ADSP_REG_HIPCIDD,
817 .req_busy_mask = CNL_ADSP_HIPCIDR_BUSY,
818 .ack_offset = CNL_ADSP_REG_HIPCIDA,
819 .ack_done_mask = CNL_ADSP_HIPCIDA_DONE,
820 .rsp_offset = CNL_ADSP_REG_HIPCTDR,
821 .rsp_busy_mask = CNL_ADSP_HIPCTDR_BUSY,
822 .ctl_offset = CNL_ADSP_REG_HIPCCTL,
823 .sts_offset = APL_ADSP_SRAM_BASE_OFFSET,
824 };
825
826 static const struct avs_hipc_spec lnl_hipc_spec = {
827 .req_offset = MTL_REG_HfIPCxIDR,
828 .req_ext_offset = MTL_REG_HfIPCxIDD,
829 .req_busy_mask = MTL_HfIPCxIDR_BUSY,
830 .ack_offset = MTL_REG_HfIPCxIDA,
831 .ack_done_mask = MTL_HfIPCxIDA_DONE,
832 .rsp_offset = MTL_REG_HfIPCxTDR,
833 .rsp_busy_mask = MTL_HfIPCxTDR_BUSY,
834 .ctl_offset = MTL_REG_HfIPCxCTL,
835 .sts_offset = LNL_REG_HfDFR(0),
836 };
837
838 static const struct avs_spec skl_desc = {
839 .name = "skl",
840 .min_fw_version = { 9, 21, 0, 4732 },
841 .dsp_ops = &avs_skl_dsp_ops,
842 .core_init_mask = 1,
843 .attributes = AVS_PLATATTR_CLDMA,
844 .sram = &skl_sram_spec,
845 .hipc = &skl_hipc_spec,
846 };
847
848 static const struct avs_spec apl_desc = {
849 .name = "apl",
850 .min_fw_version = { 9, 22, 1, 4323 },
851 .dsp_ops = &avs_apl_dsp_ops,
852 .core_init_mask = 3,
853 .attributes = AVS_PLATATTR_IMR,
854 .sram = &apl_sram_spec,
855 .hipc = &apl_hipc_spec,
856 };
857
858 static const struct avs_spec cnl_desc = {
859 .name = "cnl",
860 .min_fw_version = { 10, 23, 0, 5314 },
861 .dsp_ops = &avs_cnl_dsp_ops,
862 .core_init_mask = 1,
863 .attributes = AVS_PLATATTR_IMR,
864 .sram = &apl_sram_spec,
865 .hipc = &cnl_hipc_spec,
866 };
867
868 static const struct avs_spec icl_desc = {
869 .name = "icl",
870 .min_fw_version = { 10, 23, 0, 5040 },
871 .dsp_ops = &avs_icl_dsp_ops,
872 .core_init_mask = 1,
873 .attributes = AVS_PLATATTR_IMR,
874 .sram = &apl_sram_spec,
875 .hipc = &cnl_hipc_spec,
876 };
877
878 static const struct avs_spec jsl_desc = {
879 .name = "jsl",
880 .min_fw_version = { 10, 26, 0, 5872 },
881 .dsp_ops = &avs_icl_dsp_ops,
882 .core_init_mask = 1,
883 .attributes = AVS_PLATATTR_IMR,
884 .sram = &apl_sram_spec,
885 .hipc = &cnl_hipc_spec,
886 };
887
888 #define AVS_TGL_BASED_SPEC(sname, min) \
889 static const struct avs_spec sname##_desc = { \
890 .name = #sname, \
891 .min_fw_version = { 10, min, 0, 5646 }, \
892 .dsp_ops = &avs_tgl_dsp_ops, \
893 .core_init_mask = 1, \
894 .attributes = AVS_PLATATTR_IMR, \
895 .sram = &apl_sram_spec, \
896 .hipc = &cnl_hipc_spec, \
897 }
898
899 AVS_TGL_BASED_SPEC(lkf, 28);
900 AVS_TGL_BASED_SPEC(tgl, 29);
901 AVS_TGL_BASED_SPEC(ehl, 30);
902 AVS_TGL_BASED_SPEC(adl, 35);
903 AVS_TGL_BASED_SPEC(adl_n, 35);
904
905 static const struct avs_spec fcl_desc = {
906 .name = "fcl",
907 .min_fw_version = { 0 },
908 .dsp_ops = &avs_ptl_dsp_ops,
909 .core_init_mask = 1,
910 .attributes = AVS_PLATATTR_IMR | AVS_PLATATTR_ACE | AVS_PLATATTR_ALTHDA,
911 .sram = &mtl_sram_spec,
912 .hipc = &lnl_hipc_spec,
913 };
914
915 static const struct pci_device_id avs_ids[] = {
916 { PCI_DEVICE_DATA(INTEL, HDA_SKL_LP, &skl_desc) },
917 { PCI_DEVICE_DATA(INTEL, HDA_SKL, &skl_desc) },
918 { PCI_DEVICE_DATA(INTEL, HDA_KBL_LP, &skl_desc) },
919 { PCI_DEVICE_DATA(INTEL, HDA_KBL, &skl_desc) },
920 { PCI_DEVICE_DATA(INTEL, HDA_KBL_H, &skl_desc) },
921 { PCI_DEVICE_DATA(INTEL, HDA_CML_S, &skl_desc) },
922 { PCI_DEVICE_DATA(INTEL, HDA_APL, &apl_desc) },
923 { PCI_DEVICE_DATA(INTEL, HDA_GLK, &apl_desc) },
924 { PCI_DEVICE_DATA(INTEL, HDA_CNL_LP, &cnl_desc) },
925 { PCI_DEVICE_DATA(INTEL, HDA_CNL_H, &cnl_desc) },
926 { PCI_DEVICE_DATA(INTEL, HDA_CML_LP, &cnl_desc) },
927 { PCI_DEVICE_DATA(INTEL, HDA_CML_H, &cnl_desc) },
928 { PCI_DEVICE_DATA(INTEL, HDA_RKL_S, &cnl_desc) },
929 { PCI_DEVICE_DATA(INTEL, HDA_ICL_LP, &icl_desc) },
930 { PCI_DEVICE_DATA(INTEL, HDA_ICL_N, &icl_desc) },
931 { PCI_DEVICE_DATA(INTEL, HDA_ICL_H, &icl_desc) },
932 { PCI_DEVICE_DATA(INTEL, HDA_JSL_N, &jsl_desc) },
933 { PCI_DEVICE_DATA(INTEL, HDA_LKF, &lkf_desc) },
934 { PCI_DEVICE_DATA(INTEL, HDA_TGL_LP, &tgl_desc) },
935 { PCI_DEVICE_DATA(INTEL, HDA_TGL_H, &tgl_desc) },
936 { PCI_DEVICE_DATA(INTEL, HDA_CML_R, &tgl_desc) },
937 { PCI_DEVICE_DATA(INTEL, HDA_EHL_0, &ehl_desc) },
938 { PCI_DEVICE_DATA(INTEL, HDA_EHL_3, &ehl_desc) },
939 { PCI_DEVICE_DATA(INTEL, HDA_ADL_S, &adl_desc) },
940 { PCI_DEVICE_DATA(INTEL, HDA_ADL_P, &adl_desc) },
941 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PS, &adl_desc) },
942 { PCI_DEVICE_DATA(INTEL, HDA_ADL_M, &adl_desc) },
943 { PCI_DEVICE_DATA(INTEL, HDA_ADL_PX, &adl_desc) },
944 { PCI_DEVICE_DATA(INTEL, HDA_ADL_N, &adl_n_desc) },
945 { PCI_DEVICE_DATA(INTEL, HDA_RPL_S, &adl_desc) },
946 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_0, &adl_desc) },
947 { PCI_DEVICE_DATA(INTEL, HDA_RPL_P_1, &adl_desc) },
948 { PCI_DEVICE_DATA(INTEL, HDA_RPL_M, &adl_desc) },
949 { PCI_DEVICE_DATA(INTEL, HDA_RPL_PX, &adl_desc) },
950 { PCI_DEVICE_DATA(INTEL, HDA_FCL, &fcl_desc) },
951 { 0 }
952 };
953 MODULE_DEVICE_TABLE(pci, avs_ids);
954
955 static struct pci_driver avs_pci_driver = {
956 .name = KBUILD_MODNAME,
957 .id_table = avs_ids,
958 .probe = avs_pci_probe,
959 .remove = avs_pci_remove,
960 .shutdown = avs_pci_shutdown,
961 .dev_groups = avs_attr_groups,
962 .driver = {
963 .pm = pm_ptr(&avs_dev_pm),
964 },
965 };
966 module_pci_driver(avs_pci_driver);
967
968 MODULE_AUTHOR("Cezary Rojewski <cezary.rojewski@intel.com>");
969 MODULE_AUTHOR("Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>");
970 MODULE_DESCRIPTION("Intel cAVS sound driver");
971 MODULE_LICENSE("GPL");
972 MODULE_FIRMWARE("intel/avs/skl/dsp_basefw.bin");
973 MODULE_FIRMWARE("intel/avs/apl/dsp_basefw.bin");
974 MODULE_FIRMWARE("intel/avs/cnl/dsp_basefw.bin");
975 MODULE_FIRMWARE("intel/avs/icl/dsp_basefw.bin");
976 MODULE_FIRMWARE("intel/avs/jsl/dsp_basefw.bin");
977 MODULE_FIRMWARE("intel/avs/lkf/dsp_basefw.bin");
978 MODULE_FIRMWARE("intel/avs/tgl/dsp_basefw.bin");
979 MODULE_FIRMWARE("intel/avs/ehl/dsp_basefw.bin");
980 MODULE_FIRMWARE("intel/avs/adl/dsp_basefw.bin");
981 MODULE_FIRMWARE("intel/avs/adl_n/dsp_basefw.bin");
982 MODULE_FIRMWARE("intel/fcl/dsp_basefw.bin");
983