1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * pci-j721e - PCIe controller driver for TI's J721E SoCs 4 * 5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com 6 * Author: Kishon Vijay Abraham I <kishon@ti.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/container_of.h> 12 #include <linux/delay.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/io.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/pci.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/regmap.h> 24 25 #include "../../pci.h" 26 #include "pcie-cadence.h" 27 28 #define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie) 29 30 #define ENABLE_REG_SYS_2 0x108 31 #define ENABLE_CLR_REG_SYS_2 0x308 32 #define STATUS_REG_SYS_2 0x508 33 #define STATUS_CLR_REG_SYS_2 0x708 34 #define LINK_DOWN BIT(1) 35 #define J7200_LINK_DOWN BIT(10) 36 37 #define J721E_PCIE_USER_CMD_STATUS 0x4 38 #define LINK_TRAINING_ENABLE BIT(0) 39 40 #define J721E_PCIE_USER_LINKSTATUS 0x14 41 #define LINK_STATUS GENMASK(1, 0) 42 43 enum link_status { 44 NO_RECEIVERS_DETECTED, 45 LINK_TRAINING_IN_PROGRESS, 46 LINK_UP_DL_IN_PROGRESS, 47 LINK_UP_DL_COMPLETED, 48 }; 49 50 #define J721E_MODE_RC BIT(7) 51 #define LANE_COUNT(n) ((n) << 8) 52 53 #define ACSPCIE_PAD_DISABLE_MASK GENMASK(1, 0) 54 #define GENERATION_SEL_MASK GENMASK(1, 0) 55 56 struct j721e_pcie { 57 struct cdns_pcie *cdns_pcie; 58 struct clk *refclk; 59 u32 mode; 60 u32 num_lanes; 61 u32 max_lanes; 62 struct gpio_desc *reset_gpio; 63 void __iomem *user_cfg_base; 64 void __iomem *intd_cfg_base; 65 u32 linkdown_irq_regfield; 66 }; 67 68 enum j721e_pcie_mode { 69 PCI_MODE_RC, 70 PCI_MODE_EP, 71 }; 72 73 struct j721e_pcie_data { 74 enum j721e_pcie_mode mode; 75 unsigned int quirk_retrain_flag:1; 76 unsigned int quirk_detect_quiet_flag:1; 77 unsigned int quirk_disable_flr:1; 78 u32 linkdown_irq_regfield; 79 unsigned int byte_access_allowed:1; 80 unsigned int max_lanes; 81 }; 82 83 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) 84 { 85 return readl(pcie->user_cfg_base + offset); 86 } 87 88 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, 89 u32 value) 90 { 91 writel(value, pcie->user_cfg_base + offset); 92 } 93 94 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) 95 { 96 return readl(pcie->intd_cfg_base + offset); 97 } 98 99 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset, 100 u32 value) 101 { 102 writel(value, pcie->intd_cfg_base + offset); 103 } 104 105 static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv) 106 { 107 struct j721e_pcie *pcie = priv; 108 struct device *dev = pcie->cdns_pcie->dev; 109 u32 reg; 110 111 reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2); 112 if (!(reg & pcie->linkdown_irq_regfield)) 113 return IRQ_NONE; 114 115 dev_err(dev, "LINK DOWN!\n"); 116 117 j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->linkdown_irq_regfield); 118 return IRQ_HANDLED; 119 } 120 121 static void j721e_pcie_disable_link_irq(struct j721e_pcie *pcie) 122 { 123 u32 reg; 124 125 reg = j721e_pcie_intd_readl(pcie, ENABLE_CLR_REG_SYS_2); 126 reg |= pcie->linkdown_irq_regfield; 127 j721e_pcie_intd_writel(pcie, ENABLE_CLR_REG_SYS_2, reg); 128 } 129 130 static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie) 131 { 132 u32 reg; 133 134 reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2); 135 reg |= pcie->linkdown_irq_regfield; 136 j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg); 137 } 138 139 static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie) 140 { 141 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 142 u32 reg; 143 144 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); 145 reg |= LINK_TRAINING_ENABLE; 146 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); 147 148 return 0; 149 } 150 151 static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie) 152 { 153 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 154 u32 reg; 155 156 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); 157 reg &= ~LINK_TRAINING_ENABLE; 158 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); 159 } 160 161 static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie) 162 { 163 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); 164 u32 reg; 165 166 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS); 167 return (reg & LINK_STATUS) == LINK_UP_DL_COMPLETED; 168 } 169 170 static const struct cdns_pcie_ops j721e_pcie_ops = { 171 .start_link = j721e_pcie_start_link, 172 .stop_link = j721e_pcie_stop_link, 173 .link_up = j721e_pcie_link_up, 174 }; 175 176 static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon, 177 unsigned int offset) 178 { 179 struct device *dev = pcie->cdns_pcie->dev; 180 u32 mask = J721E_MODE_RC; 181 u32 mode = pcie->mode; 182 u32 val = 0; 183 int ret = 0; 184 185 if (mode == PCI_MODE_RC) 186 val = J721E_MODE_RC; 187 188 ret = regmap_update_bits(syscon, offset, mask, val); 189 if (ret) 190 dev_err(dev, "failed to set pcie mode\n"); 191 192 return ret; 193 } 194 195 static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, 196 struct regmap *syscon, unsigned int offset) 197 { 198 struct device *dev = pcie->cdns_pcie->dev; 199 struct device_node *np = dev->of_node; 200 int link_speed; 201 u32 val = 0; 202 int ret; 203 204 link_speed = of_pci_get_max_link_speed(np); 205 if (link_speed < 2) 206 link_speed = 2; 207 208 val = link_speed - 1; 209 ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val); 210 if (ret) 211 dev_err(dev, "failed to set link speed\n"); 212 213 return ret; 214 } 215 216 static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, 217 struct regmap *syscon, unsigned int offset) 218 { 219 struct device *dev = pcie->cdns_pcie->dev; 220 u32 lanes = pcie->num_lanes; 221 u32 mask = BIT(8); 222 u32 val = 0; 223 int ret; 224 225 if (pcie->max_lanes == 4) 226 mask = GENMASK(9, 8); 227 228 val = LANE_COUNT(lanes - 1); 229 ret = regmap_update_bits(syscon, offset, mask, val); 230 if (ret) 231 dev_err(dev, "failed to set link count\n"); 232 233 return ret; 234 } 235 236 static int j721e_enable_acspcie_refclk(struct j721e_pcie *pcie, 237 struct regmap *syscon) 238 { 239 struct device *dev = pcie->cdns_pcie->dev; 240 struct device_node *node = dev->of_node; 241 u32 mask = ACSPCIE_PAD_DISABLE_MASK; 242 struct of_phandle_args args; 243 u32 val; 244 int ret; 245 246 ret = of_parse_phandle_with_fixed_args(node, 247 "ti,syscon-acspcie-proxy-ctrl", 248 1, 0, &args); 249 if (ret) { 250 dev_err(dev, 251 "ti,syscon-acspcie-proxy-ctrl has invalid arguments\n"); 252 return ret; 253 } 254 255 /* Clear PAD IO disable bits to enable refclk output */ 256 val = ~(args.args[0]); 257 ret = regmap_update_bits(syscon, 0, mask, val); 258 if (ret) { 259 dev_err(dev, "failed to enable ACSPCIE refclk: %d\n", ret); 260 return ret; 261 } 262 263 return 0; 264 } 265 266 static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) 267 { 268 struct device *dev = pcie->cdns_pcie->dev; 269 struct device_node *node = dev->of_node; 270 struct of_phandle_args args; 271 unsigned int offset = 0; 272 struct regmap *syscon; 273 int ret; 274 275 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl"); 276 if (IS_ERR(syscon)) { 277 dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n"); 278 return PTR_ERR(syscon); 279 } 280 281 /* Do not error out to maintain old DT compatibility */ 282 ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1, 283 0, &args); 284 if (!ret) 285 offset = args.args[0]; 286 287 /* 288 * The PCIe Controller's registers have different "reset-values" 289 * depending on the "strap" settings programmed into the PCIEn_CTRL 290 * register within the CTRL_MMR memory-mapped register space. 291 * The registers latch onto a "reset-value" based on the "strap" 292 * settings sampled after the PCIe Controller is powered on. 293 * To ensure that the "reset-values" are sampled accurately, power 294 * off the PCIe Controller before programming the "strap" settings 295 * and power it on after that. The runtime PM APIs namely 296 * pm_runtime_put_sync() and pm_runtime_get_sync() will decrement and 297 * increment the usage counter respectively, causing GENPD to power off 298 * and power on the PCIe Controller. 299 */ 300 ret = pm_runtime_put_sync(dev); 301 if (ret < 0) { 302 dev_err(dev, "Failed to power off PCIe Controller\n"); 303 return ret; 304 } 305 306 ret = j721e_pcie_set_mode(pcie, syscon, offset); 307 if (ret < 0) { 308 dev_err(dev, "Failed to set pci mode\n"); 309 return ret; 310 } 311 312 ret = j721e_pcie_set_link_speed(pcie, syscon, offset); 313 if (ret < 0) { 314 dev_err(dev, "Failed to set link speed\n"); 315 return ret; 316 } 317 318 ret = j721e_pcie_set_lane_count(pcie, syscon, offset); 319 if (ret < 0) { 320 dev_err(dev, "Failed to set num-lanes\n"); 321 return ret; 322 } 323 324 ret = pm_runtime_get_sync(dev); 325 if (ret < 0) { 326 dev_err(dev, "Failed to power on PCIe Controller\n"); 327 return ret; 328 } 329 330 /* Enable ACSPCIE refclk output if the optional property exists */ 331 syscon = syscon_regmap_lookup_by_phandle_optional(node, 332 "ti,syscon-acspcie-proxy-ctrl"); 333 if (!syscon) 334 return 0; 335 336 return j721e_enable_acspcie_refclk(pcie, syscon); 337 } 338 339 static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn, 340 int where, int size, u32 *value) 341 { 342 if (pci_is_root_bus(bus)) 343 return pci_generic_config_read32(bus, devfn, where, size, 344 value); 345 346 return pci_generic_config_read(bus, devfn, where, size, value); 347 } 348 349 static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn, 350 int where, int size, u32 value) 351 { 352 if (pci_is_root_bus(bus)) 353 return pci_generic_config_write32(bus, devfn, where, size, 354 value); 355 356 return pci_generic_config_write(bus, devfn, where, size, value); 357 } 358 359 static struct pci_ops cdns_ti_pcie_host_ops = { 360 .map_bus = cdns_pci_map_bus, 361 .read = cdns_ti_pcie_config_read, 362 .write = cdns_ti_pcie_config_write, 363 }; 364 365 static const struct j721e_pcie_data j721e_pcie_rc_data = { 366 .mode = PCI_MODE_RC, 367 .quirk_retrain_flag = true, 368 .byte_access_allowed = false, 369 .linkdown_irq_regfield = LINK_DOWN, 370 .max_lanes = 2, 371 }; 372 373 static const struct j721e_pcie_data j721e_pcie_ep_data = { 374 .mode = PCI_MODE_EP, 375 .linkdown_irq_regfield = LINK_DOWN, 376 .max_lanes = 2, 377 }; 378 379 static const struct j721e_pcie_data j7200_pcie_rc_data = { 380 .mode = PCI_MODE_RC, 381 .quirk_detect_quiet_flag = true, 382 .linkdown_irq_regfield = J7200_LINK_DOWN, 383 .byte_access_allowed = true, 384 .max_lanes = 2, 385 }; 386 387 static const struct j721e_pcie_data j7200_pcie_ep_data = { 388 .mode = PCI_MODE_EP, 389 .quirk_detect_quiet_flag = true, 390 .linkdown_irq_regfield = J7200_LINK_DOWN, 391 .quirk_disable_flr = true, 392 .max_lanes = 2, 393 }; 394 395 static const struct j721e_pcie_data am64_pcie_rc_data = { 396 .mode = PCI_MODE_RC, 397 .linkdown_irq_regfield = J7200_LINK_DOWN, 398 .byte_access_allowed = true, 399 .max_lanes = 1, 400 }; 401 402 static const struct j721e_pcie_data am64_pcie_ep_data = { 403 .mode = PCI_MODE_EP, 404 .linkdown_irq_regfield = J7200_LINK_DOWN, 405 .max_lanes = 1, 406 }; 407 408 static const struct j721e_pcie_data j784s4_pcie_rc_data = { 409 .mode = PCI_MODE_RC, 410 .quirk_retrain_flag = true, 411 .byte_access_allowed = false, 412 .linkdown_irq_regfield = J7200_LINK_DOWN, 413 .max_lanes = 4, 414 }; 415 416 static const struct j721e_pcie_data j784s4_pcie_ep_data = { 417 .mode = PCI_MODE_EP, 418 .linkdown_irq_regfield = J7200_LINK_DOWN, 419 .max_lanes = 4, 420 }; 421 422 static const struct j721e_pcie_data j722s_pcie_rc_data = { 423 .mode = PCI_MODE_RC, 424 .linkdown_irq_regfield = J7200_LINK_DOWN, 425 .byte_access_allowed = true, 426 .max_lanes = 1, 427 }; 428 429 static const struct of_device_id of_j721e_pcie_match[] = { 430 { 431 .compatible = "ti,j721e-pcie-host", 432 .data = &j721e_pcie_rc_data, 433 }, 434 { 435 .compatible = "ti,j721e-pcie-ep", 436 .data = &j721e_pcie_ep_data, 437 }, 438 { 439 .compatible = "ti,j7200-pcie-host", 440 .data = &j7200_pcie_rc_data, 441 }, 442 { 443 .compatible = "ti,j7200-pcie-ep", 444 .data = &j7200_pcie_ep_data, 445 }, 446 { 447 .compatible = "ti,am64-pcie-host", 448 .data = &am64_pcie_rc_data, 449 }, 450 { 451 .compatible = "ti,am64-pcie-ep", 452 .data = &am64_pcie_ep_data, 453 }, 454 { 455 .compatible = "ti,j784s4-pcie-host", 456 .data = &j784s4_pcie_rc_data, 457 }, 458 { 459 .compatible = "ti,j784s4-pcie-ep", 460 .data = &j784s4_pcie_ep_data, 461 }, 462 { 463 .compatible = "ti,j722s-pcie-host", 464 .data = &j722s_pcie_rc_data, 465 }, 466 {}, 467 }; 468 MODULE_DEVICE_TABLE(of, of_j721e_pcie_match); 469 470 static int j721e_pcie_probe(struct platform_device *pdev) 471 { 472 struct device *dev = &pdev->dev; 473 struct device_node *node = dev->of_node; 474 struct pci_host_bridge *bridge; 475 const struct j721e_pcie_data *data; 476 struct cdns_pcie *cdns_pcie; 477 struct j721e_pcie *pcie; 478 struct cdns_pcie_rc *rc = NULL; 479 struct cdns_pcie_ep *ep = NULL; 480 void __iomem *base; 481 u32 num_lanes; 482 u32 mode; 483 int ret; 484 int irq; 485 486 data = of_device_get_match_data(dev); 487 if (!data) 488 return -EINVAL; 489 490 mode = (u32)data->mode; 491 492 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 493 if (!pcie) 494 return -ENOMEM; 495 496 switch (mode) { 497 case PCI_MODE_RC: 498 if (!IS_ENABLED(CONFIG_PCI_J721E_HOST)) 499 return -ENODEV; 500 501 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); 502 if (!bridge) 503 return -ENOMEM; 504 505 if (!data->byte_access_allowed) 506 bridge->ops = &cdns_ti_pcie_host_ops; 507 rc = pci_host_bridge_priv(bridge); 508 rc->quirk_retrain_flag = data->quirk_retrain_flag; 509 rc->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag; 510 511 cdns_pcie = &rc->pcie; 512 cdns_pcie->dev = dev; 513 cdns_pcie->ops = &j721e_pcie_ops; 514 pcie->cdns_pcie = cdns_pcie; 515 break; 516 case PCI_MODE_EP: 517 if (!IS_ENABLED(CONFIG_PCI_J721E_EP)) 518 return -ENODEV; 519 520 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); 521 if (!ep) 522 return -ENOMEM; 523 524 ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag; 525 ep->quirk_disable_flr = data->quirk_disable_flr; 526 527 cdns_pcie = &ep->pcie; 528 cdns_pcie->dev = dev; 529 cdns_pcie->ops = &j721e_pcie_ops; 530 pcie->cdns_pcie = cdns_pcie; 531 break; 532 default: 533 dev_err(dev, "INVALID device type %d\n", mode); 534 return 0; 535 } 536 537 pcie->mode = mode; 538 pcie->linkdown_irq_regfield = data->linkdown_irq_regfield; 539 540 base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg"); 541 if (IS_ERR(base)) 542 return PTR_ERR(base); 543 pcie->intd_cfg_base = base; 544 545 base = devm_platform_ioremap_resource_byname(pdev, "user_cfg"); 546 if (IS_ERR(base)) 547 return PTR_ERR(base); 548 pcie->user_cfg_base = base; 549 550 ret = of_property_read_u32(node, "num-lanes", &num_lanes); 551 if (ret || num_lanes > data->max_lanes) { 552 dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n"); 553 num_lanes = 1; 554 } 555 556 pcie->num_lanes = num_lanes; 557 pcie->max_lanes = data->max_lanes; 558 559 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) 560 return -EINVAL; 561 562 irq = platform_get_irq_byname(pdev, "link_state"); 563 if (irq < 0) 564 return irq; 565 566 dev_set_drvdata(dev, pcie); 567 pm_runtime_enable(dev); 568 ret = pm_runtime_get_sync(dev); 569 if (ret < 0) { 570 dev_err_probe(dev, ret, "pm_runtime_get_sync failed\n"); 571 goto err_get_sync; 572 } 573 574 ret = j721e_pcie_ctrl_init(pcie); 575 if (ret < 0) { 576 dev_err_probe(dev, ret, "j721e_pcie_ctrl_init failed\n"); 577 goto err_get_sync; 578 } 579 580 ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0, 581 "j721e-pcie-link-down-irq", pcie); 582 if (ret < 0) { 583 dev_err_probe(dev, ret, "failed to request link state IRQ %d\n", irq); 584 goto err_get_sync; 585 } 586 587 j721e_pcie_config_link_irq(pcie); 588 589 switch (mode) { 590 case PCI_MODE_RC: 591 pcie->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 592 if (IS_ERR(pcie->reset_gpio)) { 593 ret = dev_err_probe(dev, PTR_ERR(pcie->reset_gpio), 594 "Failed to get reset GPIO\n"); 595 goto err_get_sync; 596 } 597 598 ret = cdns_pcie_init_phy(dev, cdns_pcie); 599 if (ret) { 600 dev_err_probe(dev, ret, "Failed to init phy\n"); 601 goto err_get_sync; 602 } 603 604 pcie->refclk = devm_clk_get_optional_enabled(dev, "pcie_refclk"); 605 if (IS_ERR(pcie->refclk)) { 606 ret = dev_err_probe(dev, PTR_ERR(pcie->refclk), 607 "failed to enable pcie_refclk\n"); 608 goto err_pcie_setup; 609 } 610 611 /* 612 * Section 2.2 of the PCI Express Card Electromechanical 613 * Specification (Revision 5.1) mandates that the deassertion 614 * of the PERST# signal should be delayed by 100 ms (TPVPERL). 615 * This shall ensure that the power and the reference clock 616 * are stable. 617 */ 618 if (pcie->reset_gpio) { 619 msleep(PCIE_T_PVPERL_MS); 620 gpiod_set_value_cansleep(pcie->reset_gpio, 1); 621 } 622 623 ret = cdns_pcie_host_setup(rc); 624 if (ret < 0) 625 goto err_pcie_setup; 626 627 break; 628 case PCI_MODE_EP: 629 ret = cdns_pcie_init_phy(dev, cdns_pcie); 630 if (ret) { 631 dev_err_probe(dev, ret, "Failed to init phy\n"); 632 goto err_get_sync; 633 } 634 635 ret = cdns_pcie_ep_setup(ep); 636 if (ret < 0) 637 goto err_pcie_setup; 638 639 break; 640 } 641 642 return 0; 643 644 err_pcie_setup: 645 cdns_pcie_disable_phy(cdns_pcie); 646 647 err_get_sync: 648 pm_runtime_put(dev); 649 pm_runtime_disable(dev); 650 651 return ret; 652 } 653 654 static void j721e_pcie_remove(struct platform_device *pdev) 655 { 656 struct j721e_pcie *pcie = platform_get_drvdata(pdev); 657 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; 658 struct device *dev = &pdev->dev; 659 struct cdns_pcie_ep *ep; 660 struct cdns_pcie_rc *rc; 661 662 if (pcie->mode == PCI_MODE_RC) { 663 rc = container_of(cdns_pcie, struct cdns_pcie_rc, pcie); 664 cdns_pcie_host_disable(rc); 665 } else { 666 ep = container_of(cdns_pcie, struct cdns_pcie_ep, pcie); 667 cdns_pcie_ep_disable(ep); 668 } 669 670 gpiod_set_value_cansleep(pcie->reset_gpio, 0); 671 672 cdns_pcie_disable_phy(cdns_pcie); 673 j721e_pcie_disable_link_irq(pcie); 674 pm_runtime_put(dev); 675 pm_runtime_disable(dev); 676 } 677 678 static int j721e_pcie_suspend_noirq(struct device *dev) 679 { 680 struct j721e_pcie *pcie = dev_get_drvdata(dev); 681 682 if (pcie->mode == PCI_MODE_RC) { 683 gpiod_set_value_cansleep(pcie->reset_gpio, 0); 684 clk_disable_unprepare(pcie->refclk); 685 } 686 687 cdns_pcie_disable_phy(pcie->cdns_pcie); 688 689 return 0; 690 } 691 692 static int j721e_pcie_resume_noirq(struct device *dev) 693 { 694 struct j721e_pcie *pcie = dev_get_drvdata(dev); 695 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; 696 int ret; 697 698 ret = j721e_pcie_ctrl_init(pcie); 699 if (ret < 0) 700 return ret; 701 702 j721e_pcie_config_link_irq(pcie); 703 704 /* 705 * This is not called explicitly in the probe, it is called by 706 * cdns_pcie_init_phy(). 707 */ 708 ret = cdns_pcie_enable_phy(pcie->cdns_pcie); 709 if (ret < 0) 710 return ret; 711 712 if (pcie->mode == PCI_MODE_RC) { 713 struct cdns_pcie_rc *rc = cdns_pcie_to_rc(cdns_pcie); 714 715 ret = clk_prepare_enable(pcie->refclk); 716 if (ret < 0) 717 return ret; 718 719 /* 720 * Section 2.2 of the PCI Express Card Electromechanical 721 * Specification (Revision 5.1) mandates that the deassertion 722 * of the PERST# signal should be delayed by 100 ms (TPVPERL). 723 * This shall ensure that the power and the reference clock 724 * are stable. 725 */ 726 if (pcie->reset_gpio) { 727 msleep(PCIE_T_PVPERL_MS); 728 gpiod_set_value_cansleep(pcie->reset_gpio, 1); 729 } 730 731 ret = cdns_pcie_host_link_setup(rc); 732 if (ret < 0) { 733 clk_disable_unprepare(pcie->refclk); 734 return ret; 735 } 736 737 /* 738 * Reset internal status of BARs to force reinitialization in 739 * cdns_pcie_host_init(). 740 */ 741 for (enum cdns_pcie_rp_bar bar = RP_BAR0; bar <= RP_NO_BAR; bar++) 742 rc->avail_ib_bar[bar] = true; 743 744 ret = cdns_pcie_host_init(rc); 745 if (ret) { 746 clk_disable_unprepare(pcie->refclk); 747 return ret; 748 } 749 } 750 751 return 0; 752 } 753 754 static DEFINE_NOIRQ_DEV_PM_OPS(j721e_pcie_pm_ops, 755 j721e_pcie_suspend_noirq, 756 j721e_pcie_resume_noirq); 757 758 static struct platform_driver j721e_pcie_driver = { 759 .probe = j721e_pcie_probe, 760 .remove = j721e_pcie_remove, 761 .driver = { 762 .name = "j721e-pcie", 763 .of_match_table = of_j721e_pcie_match, 764 .suppress_bind_attrs = true, 765 .pm = pm_sleep_ptr(&j721e_pcie_pm_ops), 766 }, 767 }; 768 module_platform_driver(j721e_pcie_driver); 769 770 MODULE_LICENSE("GPL"); 771 MODULE_DESCRIPTION("PCIe controller driver for TI's J721E and related SoCs"); 772 MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>"); 773