1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2025 Intel Corporation */
3
4 #include "ixd.h"
5 #include "ixd_lan_regs.h"
6
7 /**
8 * ixd_ctlq_reg_init - Initialize default mailbox registers
9 * @adapter: PCI device driver-specific private data
10 * @ctlq_reg_tx: Transmit queue registers info to be filled
11 * @ctlq_reg_rx: Receive queue registers info to be filled
12 */
ixd_ctlq_reg_init(struct ixd_adapter * adapter,struct libie_ctlq_reg * ctlq_reg_tx,struct libie_ctlq_reg * ctlq_reg_rx)13 void ixd_ctlq_reg_init(struct ixd_adapter *adapter,
14 struct libie_ctlq_reg *ctlq_reg_tx,
15 struct libie_ctlq_reg *ctlq_reg_rx)
16 {
17 struct libie_mmio_info *mmio_info = &adapter->cp_ctx.mmio_info;
18 *ctlq_reg_tx = (struct libie_ctlq_reg) {
19 .head = libie_pci_get_mmio_addr(mmio_info, PF_FW_ATQH),
20 .tail = libie_pci_get_mmio_addr(mmio_info, PF_FW_ATQT),
21 .len = libie_pci_get_mmio_addr(mmio_info, PF_FW_ATQLEN),
22 .addr_high = libie_pci_get_mmio_addr(mmio_info, PF_FW_ATQBAH),
23 .addr_low = libie_pci_get_mmio_addr(mmio_info, PF_FW_ATQBAL),
24 .len_mask = PF_FW_ATQLEN_ATQLEN_M,
25 .len_ena_mask = PF_FW_ATQLEN_ATQENABLE_M,
26 .head_mask = PF_FW_ATQH_ATQH_M,
27 };
28
29 *ctlq_reg_rx = (struct libie_ctlq_reg) {
30 .head = libie_pci_get_mmio_addr(mmio_info, PF_FW_ARQH),
31 .tail = libie_pci_get_mmio_addr(mmio_info, PF_FW_ARQT),
32 .len = libie_pci_get_mmio_addr(mmio_info, PF_FW_ARQLEN),
33 .addr_high = libie_pci_get_mmio_addr(mmio_info, PF_FW_ARQBAH),
34 .addr_low = libie_pci_get_mmio_addr(mmio_info, PF_FW_ARQBAL),
35 .len_mask = PF_FW_ARQLEN_ARQLEN_M,
36 .len_ena_mask = PF_FW_ARQLEN_ARQENABLE_M,
37 .head_mask = PF_FW_ARQH_ARQH_M,
38 };
39 }
40
41 static const struct ixd_reset_reg ixd_reset_reg = {
42 .rstat = PFGEN_RSTAT,
43 .rstat_m = PFGEN_RSTAT_PFR_STATE_M,
44 .rstat_ok_v = 0b01,
45 .rtrigger = PFGEN_CTRL,
46 .rtrigger_m = PFGEN_CTRL_PFSWR,
47 };
48
49 /**
50 * ixd_trigger_reset - Trigger PFR reset
51 * @adapter: the device with mapped reset register
52 */
ixd_trigger_reset(struct ixd_adapter * adapter)53 void ixd_trigger_reset(struct ixd_adapter *adapter)
54 {
55 void __iomem *addr;
56 u32 reg_val;
57
58 addr = libie_pci_get_mmio_addr(&adapter->cp_ctx.mmio_info,
59 ixd_reset_reg.rtrigger);
60 reg_val = readl(addr);
61 writel(reg_val | ixd_reset_reg.rtrigger_m, addr);
62 }
63
64 /**
65 * ixd_check_reset_complete - Check if the PFR reset is completed
66 * @adapter: CPF being reset
67 *
68 * Return: %true if the register read indicates reset has been finished,
69 * %false otherwise
70 */
ixd_check_reset_complete(struct ixd_adapter * adapter)71 bool ixd_check_reset_complete(struct ixd_adapter *adapter)
72 {
73 u32 reg_val, reset_status;
74 void __iomem *addr;
75
76 addr = libie_pci_get_mmio_addr(&adapter->cp_ctx.mmio_info,
77 ixd_reset_reg.rstat);
78 reg_val = readl(addr);
79 reset_status = reg_val & ixd_reset_reg.rstat_m;
80
81 /* 0xFFFFFFFF might be read if the other side hasn't cleared
82 * the register for us yet.
83 */
84 if (reg_val != GENMASK(31, 0) &&
85 reset_status == ixd_reset_reg.rstat_ok_v)
86 return true;
87
88 return false;
89 }
90