1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /*
3 * Copyright (C) 2003-2015, 2018-2025 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
7 #ifndef __iwl_trans_int_pcie_h__
8 #define __iwl_trans_int_pcie_h__
9
10 #include <linux/spinlock.h>
11 #include <linux/interrupt.h>
12 #include <linux/skbuff.h>
13 #include <linux/wait.h>
14 #include <linux/pci.h>
15 #include <linux/timer.h>
16 #include <linux/cpu.h>
17
18 #include "iwl-fh.h"
19 #include "iwl-csr.h"
20 #include "iwl-trans.h"
21 #include "iwl-debug.h"
22 #include "iwl-io.h"
23 #include "iwl-op-mode.h"
24 #include "iwl-drv.h"
25 #include "iwl-context-info.h"
26
27 /*
28 * RX related structures and functions
29 */
30 #define RX_NUM_QUEUES 1
31 #define RX_POST_REQ_ALLOC 2
32 #define RX_CLAIM_REQ_ALLOC 8
33 #define RX_PENDING_WATERMARK 16
34 #define FIRST_RX_QUEUE 512
35
36 struct iwl_host_cmd;
37
38 /*This file includes the declaration that are internal to the
39 * trans_pcie layer */
40
41 /**
42 * struct iwl_rx_mem_buffer
43 * @page_dma: bus address of rxb page
44 * @page: driver's pointer to the rxb page
45 * @list: list entry for the membuffer
46 * @invalid: rxb is in driver ownership - not owned by HW
47 * @vid: index of this rxb in the global table
48 * @offset: indicates which offset of the page (in bytes)
49 * this buffer uses (if multiple RBs fit into one page)
50 */
51 struct iwl_rx_mem_buffer {
52 dma_addr_t page_dma;
53 struct page *page;
54 struct list_head list;
55 u32 offset;
56 u16 vid;
57 bool invalid;
58 };
59
60 /* interrupt statistics */
61 struct isr_statistics {
62 u32 hw;
63 u32 sw;
64 u32 err_code;
65 u32 sch;
66 u32 alive;
67 u32 rfkill;
68 u32 ctkill;
69 u32 wakeup;
70 u32 rx;
71 u32 tx;
72 u32 unhandled;
73 };
74
75 /**
76 * struct iwl_rx_transfer_desc - transfer descriptor
77 * @addr: ptr to free buffer start address
78 * @rbid: unique tag of the buffer
79 * @reserved: reserved
80 */
81 struct iwl_rx_transfer_desc {
82 __le16 rbid;
83 __le16 reserved[3];
84 __le64 addr;
85 } __packed;
86
87 #define IWL_RX_CD_FLAGS_FRAGMENTED BIT(0)
88
89 /**
90 * struct iwl_rx_completion_desc - completion descriptor
91 * @reserved1: reserved
92 * @rbid: unique tag of the received buffer
93 * @flags: flags (0: fragmented, all others: reserved)
94 * @reserved2: reserved
95 */
96 struct iwl_rx_completion_desc {
97 __le32 reserved1;
98 __le16 rbid;
99 u8 flags;
100 u8 reserved2[25];
101 } __packed;
102
103 /**
104 * struct iwl_rx_completion_desc_bz - Bz completion descriptor
105 * @rbid: unique tag of the received buffer
106 * @flags: flags (0: fragmented, all others: reserved)
107 * @reserved: reserved
108 */
109 struct iwl_rx_completion_desc_bz {
110 __le16 rbid;
111 u8 flags;
112 u8 reserved[1];
113 } __packed;
114
115 /**
116 * struct iwl_rxq - Rx queue
117 * @id: queue index
118 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd).
119 * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices.
120 * In AX210 devices it is a pointer to a list of iwl_rx_transfer_desc's
121 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
122 * @used_bd: driver's pointer to buffer of used receive buffer descriptors (rbd)
123 * @used_bd_dma: physical address of buffer of used receive buffer descriptors (rbd)
124 * @read: Shared index to newest available Rx buffer
125 * @write: Shared index to oldest written Rx packet
126 * @write_actual: actual write pointer written to device, since we update in
127 * blocks of 8 only
128 * @free_count: Number of pre-allocated buffers in rx_free
129 * @used_count: Number of RBDs handled to allocator to use for allocation
130 * @write_actual:
131 * @rx_free: list of RBDs with allocated RB ready for use
132 * @rx_used: list of RBDs with no RB attached
133 * @need_update: flag to indicate we need to update read/write index
134 * @rb_stts: driver's pointer to receive buffer status
135 * @rb_stts_dma: bus address of receive buffer status
136 * @lock: per-queue lock
137 * @queue: actual rx queue. Not used for multi-rx queue.
138 * @next_rb_is_fragment: indicates that the previous RB that we handled set
139 * the fragmented flag, so the next one is still another fragment
140 * @napi: NAPI struct for this queue
141 * @queue_size: size of this queue
142 *
143 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers
144 */
145 struct iwl_rxq {
146 int id;
147 void *bd;
148 dma_addr_t bd_dma;
149 void *used_bd;
150 dma_addr_t used_bd_dma;
151 u32 read;
152 u32 write;
153 u32 free_count;
154 u32 used_count;
155 u32 write_actual;
156 u32 queue_size;
157 struct list_head rx_free;
158 struct list_head rx_used;
159 bool need_update, next_rb_is_fragment;
160 void *rb_stts;
161 dma_addr_t rb_stts_dma;
162 spinlock_t lock;
163 struct napi_struct napi;
164 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE];
165 };
166
167 /**
168 * struct iwl_rb_allocator - Rx allocator
169 * @req_pending: number of requests the allcator had not processed yet
170 * @req_ready: number of requests honored and ready for claiming
171 * @rbd_allocated: RBDs with pages allocated and ready to be handled to
172 * the queue. This is a list of &struct iwl_rx_mem_buffer
173 * @rbd_empty: RBDs with no page attached for allocator use. This is a list
174 * of &struct iwl_rx_mem_buffer
175 * @lock: protects the rbd_allocated and rbd_empty lists
176 * @alloc_wq: work queue for background calls
177 * @rx_alloc: work struct for background calls
178 */
179 struct iwl_rb_allocator {
180 atomic_t req_pending;
181 atomic_t req_ready;
182 struct list_head rbd_allocated;
183 struct list_head rbd_empty;
184 spinlock_t lock;
185 struct workqueue_struct *alloc_wq;
186 struct work_struct rx_alloc;
187 };
188
189 /**
190 * iwl_get_closed_rb_stts - get closed rb stts from different structs
191 * @trans: transport pointer (for configuration)
192 * @rxq: the rxq to get the rb stts from
193 */
iwl_get_closed_rb_stts(struct iwl_trans * trans,struct iwl_rxq * rxq)194 static inline u16 iwl_get_closed_rb_stts(struct iwl_trans *trans,
195 struct iwl_rxq *rxq)
196 {
197 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) {
198 __le16 *rb_stts = rxq->rb_stts;
199
200 return le16_to_cpu(READ_ONCE(*rb_stts));
201 } else {
202 struct iwl_rb_status *rb_stts = rxq->rb_stts;
203
204 return le16_to_cpu(READ_ONCE(rb_stts->closed_rb_num)) & 0xFFF;
205 }
206 }
207
208 #ifdef CONFIG_IWLWIFI_DEBUGFS
209 /**
210 * enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data
211 * debugfs file
212 *
213 * @IWL_FW_MON_DBGFS_STATE_CLOSED: the file is closed.
214 * @IWL_FW_MON_DBGFS_STATE_OPEN: the file is open.
215 * @IWL_FW_MON_DBGFS_STATE_DISABLED: the file is disabled, once this state is
216 * set the file can no longer be used.
217 */
218 enum iwl_fw_mon_dbgfs_state {
219 IWL_FW_MON_DBGFS_STATE_CLOSED,
220 IWL_FW_MON_DBGFS_STATE_OPEN,
221 IWL_FW_MON_DBGFS_STATE_DISABLED,
222 };
223 #endif
224
225 /**
226 * enum iwl_shared_irq_flags - level of sharing for irq
227 * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes.
228 * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue.
229 */
230 enum iwl_shared_irq_flags {
231 IWL_SHARED_IRQ_NON_RX = BIT(0),
232 IWL_SHARED_IRQ_FIRST_RSS = BIT(1),
233 };
234
235 /**
236 * enum iwl_image_response_code - image response values
237 * @IWL_IMAGE_RESP_DEF: the default value of the register
238 * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully
239 * @IWL_IMAGE_RESP_FAIL: iml reading failed
240 */
241 enum iwl_image_response_code {
242 IWL_IMAGE_RESP_DEF = 0,
243 IWL_IMAGE_RESP_SUCCESS = 1,
244 IWL_IMAGE_RESP_FAIL = 2,
245 };
246
247 #ifdef CONFIG_IWLWIFI_DEBUGFS
248 /**
249 * struct cont_rec: continuous recording data structure
250 * @prev_wr_ptr: the last address that was read in monitor_data
251 * debugfs file
252 * @prev_wrap_cnt: the wrap count that was used during the last read in
253 * monitor_data debugfs file
254 * @state: the state of monitor_data debugfs file as described
255 * in &iwl_fw_mon_dbgfs_state enum
256 * @mutex: locked while reading from monitor_data debugfs file
257 */
258 struct cont_rec {
259 u32 prev_wr_ptr;
260 u32 prev_wrap_cnt;
261 u8 state;
262 /* Used to sync monitor_data debugfs file with driver unload flow */
263 struct mutex mutex;
264 };
265 #endif
266
267 enum iwl_pcie_fw_reset_state {
268 FW_RESET_IDLE,
269 FW_RESET_REQUESTED,
270 FW_RESET_OK,
271 FW_RESET_ERROR,
272 FW_RESET_TOP_REQUESTED,
273 };
274
275 /**
276 * enum iwl_pcie_imr_status - imr dma transfer state
277 * @IMR_D2S_IDLE: default value of the dma transfer
278 * @IMR_D2S_REQUESTED: dma transfer requested
279 * @IMR_D2S_COMPLETED: dma transfer completed
280 * @IMR_D2S_ERROR: dma transfer error
281 */
282 enum iwl_pcie_imr_status {
283 IMR_D2S_IDLE,
284 IMR_D2S_REQUESTED,
285 IMR_D2S_COMPLETED,
286 IMR_D2S_ERROR,
287 };
288
289 /**
290 * struct iwl_pcie_txqs - TX queues data
291 *
292 * @queue_used: bit mask of used queues
293 * @queue_stopped: bit mask of stopped queues
294 * @txq: array of TXQ data structures representing the TXQs
295 * @scd_bc_tbls: gen1 pointer to the byte count table of the scheduler
296 * @bc_pool: bytecount DMA allocations pool
297 * @bc_tbl_size: bytecount table size
298 * @tso_hdr_page: page allocated (per CPU) for A-MSDU headers when doing TSO
299 * (and similar usage)
300 * @tfd: TFD data
301 * @tfd.max_tbs: max number of buffers per TFD
302 * @tfd.size: TFD size
303 * @tfd.addr_size: TFD/TB address size
304 */
305 struct iwl_pcie_txqs {
306 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
307 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)];
308 struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES];
309 struct dma_pool *bc_pool;
310 size_t bc_tbl_size;
311 struct iwl_tso_hdr_page __percpu *tso_hdr_page;
312
313 struct {
314 u8 max_tbs;
315 u16 size;
316 u8 addr_size;
317 } tfd;
318
319 struct iwl_dma_ptr scd_bc_tbls;
320 };
321
322 /**
323 * struct iwl_trans_pcie - PCIe transport specific data
324 * @rxq: all the RX queue data
325 * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues
326 * @global_table: table mapping received VID from hw to rxb
327 * @rba: allocator for RX replenishing
328 * @ctxt_info: context information for FW self init
329 * @ctxt_info_v2: context information for v1 devices
330 * @prph_info: prph info for self init
331 * @prph_scratch: prph scratch for self init
332 * @ctxt_info_dma_addr: dma addr of context information
333 * @prph_info_dma_addr: dma addr of prph info
334 * @prph_scratch_dma_addr: dma addr of prph scratch
335 * @ctxt_info_dma_addr: dma addr of context information
336 * @iml: image loader image virtual address
337 * @iml_len: image loader image size
338 * @iml_dma_addr: image loader image DMA address
339 * @trans: pointer to the generic transport area
340 * @scd_base_addr: scheduler sram base address in SRAM
341 * @kw: keep warm address
342 * @pnvm_data: holds info about pnvm payloads allocated in DRAM
343 * @reduced_tables_data: holds info about power reduced tablse
344 * payloads allocated in DRAM
345 * @pci_dev: basic pci-network driver stuff
346 * @hw_base: pci hardware address support
347 * @ucode_write_complete: indicates that the ucode has been copied.
348 * @ucode_write_waitq: wait queue for uCode load
349 * @rx_page_order: page order for receive buffer size
350 * @rx_buf_bytes: RX buffer (RB) size in bytes
351 * @reg_lock: protect hw register access
352 * @mutex: to protect stop_device / start_fw / start_hw
353 * @fw_mon_data: fw continuous recording data
354 * @cmd_hold_nic_awake: indicates NIC is held awake for APMG workaround
355 * during commands in flight
356 * @msix_entries: array of MSI-X entries
357 * @msix_enabled: true if managed to enable MSI-X
358 * @shared_vec_mask: the type of causes the shared vector handles
359 * (see iwl_shared_irq_flags).
360 * @alloc_vecs: the number of interrupt vectors allocated by the OS
361 * @def_irq: default irq for non rx causes
362 * @fh_init_mask: initial unmasked fh causes
363 * @hw_init_mask: initial unmasked hw causes
364 * @fh_mask: current unmasked fh causes
365 * @hw_mask: current unmasked hw causes
366 * @in_rescan: true if we have triggered a device rescan
367 * @base_rb_stts: base virtual address of receive buffer status for all queues
368 * @base_rb_stts_dma: base physical address of receive buffer status
369 * @supported_dma_mask: DMA mask to validate the actual address against,
370 * will be DMA_BIT_MASK(11) or DMA_BIT_MASK(12) depending on the device
371 * @alloc_page_lock: spinlock for the page allocator
372 * @alloc_page: allocated page to still use parts of
373 * @alloc_page_used: how much of the allocated page was already used (bytes)
374 * @imr_status: imr dma state machine
375 * @imr_waitq: imr wait queue for dma completion
376 * @rf_name: name/version of the CRF, if any
377 * @use_ict: whether or not ICT (interrupt table) is used
378 * @ict_index: current ICT read index
379 * @ict_tbl: ICT table pointer
380 * @ict_tbl_dma: ICT table DMA address
381 * @inta_mask: interrupt (INT-A) mask
382 * @irq_lock: lock to synchronize IRQ handling
383 * @txq_memory: TXQ allocation array
384 * @sx_waitq: waitqueue for Sx transitions
385 * @sx_complete: completion for Sx transitions
386 * @pcie_dbg_dumped_once: indicates PCIe regs were dumped already
387 * @opmode_down: indicates opmode went away
388 * @num_rx_bufs: number of RX buffers to allocate/use
389 * @affinity_mask: IRQ affinity mask for each RX queue
390 * @debug_rfkill: RF-kill debugging state, -1 for unset, 0/1 for radio
391 * enable/disable
392 * @fw_reset_state: state of FW reset handshake
393 * @fw_reset_waitq: waitqueue for FW reset handshake
394 * @is_down: indicates the NIC is down
395 * @isr_stats: interrupt statistics
396 * @napi_dev: (fake) netdev for NAPI registration
397 * @txqs: transport tx queues data.
398 * @me_present: WiAMT/CSME is detected as present (1), not present (0)
399 * or unknown (-1, so can still use it as a boolean safely)
400 * @me_recheck_wk: worker to recheck WiAMT/CSME presence
401 * @invalid_tx_cmd: invalid TX command buffer
402 * @wait_command_queue: wait queue for sync commands
403 */
404 struct iwl_trans_pcie {
405 struct iwl_rxq *rxq;
406 struct iwl_rx_mem_buffer *rx_pool;
407 struct iwl_rx_mem_buffer **global_table;
408 struct iwl_rb_allocator rba;
409 union {
410 struct iwl_context_info *ctxt_info;
411 struct iwl_context_info_v2 *ctxt_info_v2;
412 };
413 struct iwl_prph_info *prph_info;
414 struct iwl_prph_scratch *prph_scratch;
415 void *iml;
416 size_t iml_len;
417 dma_addr_t ctxt_info_dma_addr;
418 dma_addr_t prph_info_dma_addr;
419 dma_addr_t prph_scratch_dma_addr;
420 dma_addr_t iml_dma_addr;
421 struct iwl_trans *trans;
422
423 struct net_device *napi_dev;
424
425 /* INT ICT Table */
426 __le32 *ict_tbl;
427 dma_addr_t ict_tbl_dma;
428 int ict_index;
429 bool use_ict;
430 bool is_down, opmode_down;
431 s8 debug_rfkill;
432 struct isr_statistics isr_stats;
433
434 spinlock_t irq_lock;
435 struct mutex mutex;
436 u32 inta_mask;
437 u32 scd_base_addr;
438 struct iwl_dma_ptr kw;
439
440 /* pnvm data */
441 struct iwl_dram_regions pnvm_data;
442 struct iwl_dram_regions reduced_tables_data;
443
444 struct iwl_txq *txq_memory;
445
446 /* PCI bus related data */
447 struct pci_dev *pci_dev;
448 u8 __iomem *hw_base;
449
450 bool ucode_write_complete;
451 bool sx_complete;
452 wait_queue_head_t ucode_write_waitq;
453 wait_queue_head_t sx_waitq;
454
455 u16 num_rx_bufs;
456
457 bool pcie_dbg_dumped_once;
458 u32 rx_page_order;
459 u32 rx_buf_bytes;
460 u32 supported_dma_mask;
461
462 /* allocator lock for the two values below */
463 spinlock_t alloc_page_lock;
464 struct page *alloc_page;
465 u32 alloc_page_used;
466
467 /*protect hw register */
468 spinlock_t reg_lock;
469 bool cmd_hold_nic_awake;
470
471 #ifdef CONFIG_IWLWIFI_DEBUGFS
472 struct cont_rec fw_mon_data;
473 #endif
474
475 struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES];
476 bool msix_enabled;
477 u8 shared_vec_mask;
478 u32 alloc_vecs;
479 u32 def_irq;
480 u32 fh_init_mask;
481 u32 hw_init_mask;
482 u32 fh_mask;
483 u32 hw_mask;
484 cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES];
485 u16 tx_cmd_queue_size;
486 bool in_rescan;
487
488 void *base_rb_stts;
489 dma_addr_t base_rb_stts_dma;
490
491 enum iwl_pcie_fw_reset_state fw_reset_state;
492 wait_queue_head_t fw_reset_waitq;
493 enum iwl_pcie_imr_status imr_status;
494 wait_queue_head_t imr_waitq;
495 char rf_name[32];
496
497 struct iwl_pcie_txqs txqs;
498
499 s8 me_present;
500 struct delayed_work me_recheck_wk;
501
502 struct iwl_dma_ptr invalid_tx_cmd;
503
504 wait_queue_head_t wait_command_queue;
505 };
506
507 static inline struct iwl_trans_pcie *
IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans * trans)508 IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans)
509 {
510 return (void *)trans->trans_specific;
511 }
512
iwl_pcie_clear_irq(struct iwl_trans * trans,int queue)513 static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, int queue)
514 {
515 /*
516 * Before sending the interrupt the HW disables it to prevent
517 * a nested interrupt. This is done by writing 1 to the corresponding
518 * bit in the mask register. After handling the interrupt, it should be
519 * re-enabled by clearing this bit. This register is defined as
520 * write 1 clear (W1C) register, meaning that it's being clear
521 * by writing 1 to the bit.
522 */
523 iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue));
524 }
525
526 static inline struct iwl_trans *
iwl_trans_pcie_get_trans(struct iwl_trans_pcie * trans_pcie)527 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie)
528 {
529 return container_of((void *)trans_pcie, struct iwl_trans,
530 trans_specific);
531 }
532
533 /*
534 * Convention: trans API functions: iwl_trans_pcie_XXX
535 * Other functions: iwl_pcie_XXX
536 */
537 struct iwl_trans
538 *iwl_trans_pcie_alloc(struct pci_dev *pdev,
539 const struct iwl_mac_cfg *mac_cfg,
540 struct iwl_trans_info *info);
541 void iwl_trans_pcie_free(struct iwl_trans *trans);
542 void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions,
543 struct device *dev);
544
545 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent);
546 #define _iwl_trans_pcie_grab_nic_access(trans, silent) \
547 __cond_lock(nic_access_nobh, \
548 likely(__iwl_trans_pcie_grab_nic_access(trans, silent)))
549
550 void iwl_trans_pcie_check_product_reset_status(struct pci_dev *pdev);
551 void iwl_trans_pcie_check_product_reset_mode(struct pci_dev *pdev);
552
553 /*****************************************************
554 * RX
555 ******************************************************/
556 int iwl_pcie_rx_init(struct iwl_trans *trans);
557 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans);
558 irqreturn_t iwl_pcie_msix_isr(int irq, void *data);
559 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id);
560 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id);
561 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id);
562 int iwl_pcie_rx_stop(struct iwl_trans *trans);
563 void iwl_pcie_rx_free(struct iwl_trans *trans);
564 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans);
565 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq);
566 void iwl_pcie_rx_napi_sync(struct iwl_trans *trans);
567 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
568 struct iwl_rxq *rxq);
569
570 /*****************************************************
571 * ICT - interrupt handling
572 ******************************************************/
573 irqreturn_t iwl_pcie_isr(int irq, void *data);
574 int iwl_pcie_alloc_ict(struct iwl_trans *trans);
575 void iwl_pcie_free_ict(struct iwl_trans *trans);
576 void iwl_pcie_reset_ict(struct iwl_trans *trans);
577 void iwl_pcie_disable_ict(struct iwl_trans *trans);
578
579 /*****************************************************
580 * TX / HCMD
581 ******************************************************/
582 /* We need 2 entries for the TX command and header, and another one might
583 * be needed for potential data in the SKB's head. The remaining ones can
584 * be used for frags.
585 */
586 #define IWL_TRANS_PCIE_MAX_FRAGS(trans_pcie) ((trans_pcie)->txqs.tfd.max_tbs - 3)
587
588 struct iwl_tso_hdr_page {
589 struct page *page;
590 u8 *pos;
591 };
592
593 /*
594 * Note that we put this struct *last* in the page. By doing that, we ensure
595 * that no TB referencing this page can trigger the 32-bit boundary hardware
596 * bug.
597 */
598 struct iwl_tso_page_info {
599 dma_addr_t dma_addr;
600 struct page *next;
601 refcount_t use_count;
602 };
603
604 #define IWL_TSO_PAGE_DATA_SIZE (PAGE_SIZE - sizeof(struct iwl_tso_page_info))
605 #define IWL_TSO_PAGE_INFO(addr) \
606 ((struct iwl_tso_page_info *)(((unsigned long)addr & PAGE_MASK) + \
607 IWL_TSO_PAGE_DATA_SIZE))
608
609 int iwl_pcie_tx_init(struct iwl_trans *trans);
610 void iwl_pcie_tx_start(struct iwl_trans *trans);
611 int iwl_pcie_tx_stop(struct iwl_trans *trans);
612 void iwl_pcie_tx_free(struct iwl_trans *trans);
613 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn,
614 const struct iwl_trans_txq_scd_cfg *cfg,
615 unsigned int wdg_timeout);
616 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue,
617 bool configure_scd);
618 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
619 bool shared_mode);
620 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
621 struct iwl_device_tx_cmd *dev_cmd, int txq_id);
622 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans);
623 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
624 struct iwl_rx_cmd_buffer *rxb);
625 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans);
626 int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq,
627 int slots_num, bool cmd_queue);
628
629 dma_addr_t iwl_pcie_get_sgt_tb_phys(struct sg_table *sgt, unsigned int offset,
630 unsigned int len);
631 struct sg_table *iwl_pcie_prep_tso(struct iwl_trans *trans, struct sk_buff *skb,
632 struct iwl_cmd_meta *cmd_meta,
633 u8 **hdr, unsigned int hdr_room,
634 unsigned int offset);
635
636 void iwl_pcie_free_tso_pages(struct iwl_trans *trans, struct sk_buff *skb,
637 struct iwl_cmd_meta *cmd_meta);
638
iwl_pcie_get_tso_page_phys(void * addr)639 static inline dma_addr_t iwl_pcie_get_tso_page_phys(void *addr)
640 {
641 dma_addr_t res;
642
643 res = IWL_TSO_PAGE_INFO(addr)->dma_addr;
644 res += (unsigned long)addr & ~PAGE_MASK;
645
646 return res;
647 }
648
649 static inline dma_addr_t
iwl_txq_get_first_tb_dma(struct iwl_txq * txq,int idx)650 iwl_txq_get_first_tb_dma(struct iwl_txq *txq, int idx)
651 {
652 return txq->first_tb_dma +
653 sizeof(struct iwl_pcie_first_tb_buf) * idx;
654 }
655
iwl_txq_get_cmd_index(const struct iwl_txq * q,u32 index)656 static inline u16 iwl_txq_get_cmd_index(const struct iwl_txq *q, u32 index)
657 {
658 return index & (q->n_window - 1);
659 }
660
iwl_txq_get_tfd(struct iwl_trans * trans,struct iwl_txq * txq,int idx)661 static inline void *iwl_txq_get_tfd(struct iwl_trans *trans,
662 struct iwl_txq *txq, int idx)
663 {
664 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
665
666 if (trans->mac_cfg->gen2)
667 idx = iwl_txq_get_cmd_index(txq, idx);
668
669 return (u8 *)txq->tfds + trans_pcie->txqs.tfd.size * idx;
670 }
671
672 /*
673 * We need this inline in case dma_addr_t is only 32-bits - since the
674 * hardware is always 64-bit, the issue can still occur in that case,
675 * so use u64 for 'phys' here to force the addition in 64-bit.
676 */
iwl_txq_crosses_4g_boundary(u64 phys,u16 len)677 static inline bool iwl_txq_crosses_4g_boundary(u64 phys, u16 len)
678 {
679 return upper_32_bits(phys) != upper_32_bits(phys + len);
680 }
681
682 int iwl_txq_space(struct iwl_trans *trans, const struct iwl_txq *q);
683
iwl_txq_stop(struct iwl_trans * trans,struct iwl_txq * txq)684 static inline void iwl_txq_stop(struct iwl_trans *trans, struct iwl_txq *txq)
685 {
686 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
687
688 if (!test_and_set_bit(txq->id, trans_pcie->txqs.queue_stopped)) {
689 iwl_op_mode_queue_full(trans->op_mode, txq->id);
690 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id);
691 } else {
692 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n",
693 txq->id);
694 }
695 }
696
697 /**
698 * iwl_txq_inc_wrap - increment queue index, wrap back to beginning
699 * @trans: the transport (for configuration data)
700 * @index: current index
701 */
iwl_txq_inc_wrap(struct iwl_trans * trans,int index)702 static inline int iwl_txq_inc_wrap(struct iwl_trans *trans, int index)
703 {
704 return ++index &
705 (trans->mac_cfg->base->max_tfd_queue_size - 1);
706 }
707
708 /**
709 * iwl_txq_dec_wrap - decrement queue index, wrap back to end
710 * @trans: the transport (for configuration data)
711 * @index: current index
712 */
iwl_txq_dec_wrap(struct iwl_trans * trans,int index)713 static inline int iwl_txq_dec_wrap(struct iwl_trans *trans, int index)
714 {
715 return --index &
716 (trans->mac_cfg->base->max_tfd_queue_size - 1);
717 }
718
719 void iwl_txq_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq);
720
721 static inline void
iwl_trans_pcie_wake_queue(struct iwl_trans * trans,struct iwl_txq * txq)722 iwl_trans_pcie_wake_queue(struct iwl_trans *trans, struct iwl_txq *txq)
723 {
724 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
725
726 if (test_and_clear_bit(txq->id, trans_pcie->txqs.queue_stopped)) {
727 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id);
728 iwl_op_mode_queue_not_full(trans->op_mode, txq->id);
729 }
730 }
731
732 int iwl_txq_gen2_set_tb(struct iwl_trans *trans,
733 struct iwl_tfh_tfd *tfd, dma_addr_t addr,
734 u16 len);
735
iwl_txq_set_tfd_invalid_gen2(struct iwl_trans * trans,struct iwl_tfh_tfd * tfd)736 static inline void iwl_txq_set_tfd_invalid_gen2(struct iwl_trans *trans,
737 struct iwl_tfh_tfd *tfd)
738 {
739 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
740
741 tfd->num_tbs = 0;
742
743 iwl_txq_gen2_set_tb(trans, tfd, trans_pcie->invalid_tx_cmd.dma,
744 trans_pcie->invalid_tx_cmd.size);
745 }
746
747 void iwl_txq_gen2_tfd_unmap(struct iwl_trans *trans,
748 struct iwl_cmd_meta *meta,
749 struct iwl_tfh_tfd *tfd);
750
751 int iwl_txq_dyn_alloc(struct iwl_trans *trans, u32 flags,
752 u32 sta_mask, u8 tid,
753 int size, unsigned int timeout);
754
755 int iwl_txq_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb,
756 struct iwl_device_tx_cmd *dev_cmd, int txq_id);
757
758 void iwl_txq_dyn_free(struct iwl_trans *trans, int queue);
759 void iwl_txq_gen2_tx_free(struct iwl_trans *trans);
760 int iwl_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
761 int slots_num, bool cmd_queue);
762 int iwl_txq_gen2_init(struct iwl_trans *trans, int txq_id,
763 int queue_size);
764
iwl_txq_gen1_tfd_tb_get_len(struct iwl_trans * trans,void * _tfd,u8 idx)765 static inline u16 iwl_txq_gen1_tfd_tb_get_len(struct iwl_trans *trans,
766 void *_tfd, u8 idx)
767 {
768 struct iwl_tfd *tfd;
769 struct iwl_tfd_tb *tb;
770
771 if (trans->mac_cfg->gen2) {
772 struct iwl_tfh_tfd *tfh_tfd = _tfd;
773 struct iwl_tfh_tb *tfh_tb = &tfh_tfd->tbs[idx];
774
775 return le16_to_cpu(tfh_tb->tb_len);
776 }
777
778 tfd = (struct iwl_tfd *)_tfd;
779 tb = &tfd->tbs[idx];
780
781 return le16_to_cpu(tb->hi_n_len) >> 4;
782 }
783
784 void iwl_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
785 struct sk_buff_head *skbs, bool is_flush);
786 void iwl_pcie_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr);
787 void iwl_pcie_freeze_txq_timer(struct iwl_trans *trans,
788 unsigned long txqs, bool freeze);
789 int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx);
790 int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm);
791
792 /*****************************************************
793 * Error handling
794 ******************************************************/
795 void iwl_pcie_dump_csr(struct iwl_trans *trans);
796
797 /*****************************************************
798 * Helpers
799 ******************************************************/
_iwl_disable_interrupts(struct iwl_trans * trans)800 static inline void _iwl_disable_interrupts(struct iwl_trans *trans)
801 {
802 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
803
804 clear_bit(STATUS_INT_ENABLED, &trans->status);
805 if (!trans_pcie->msix_enabled) {
806 /* disable interrupts from uCode/NIC to host */
807 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
808
809 /* acknowledge/clear/reset any interrupts still pending
810 * from uCode or flow handler (Rx/Tx DMA) */
811 iwl_write32(trans, CSR_INT, 0xffffffff);
812 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff);
813 } else {
814 /* disable all the interrupt we might use */
815 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
816 trans_pcie->fh_init_mask);
817 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
818 trans_pcie->hw_init_mask);
819 }
820 IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
821 }
822
iwl_pcie_get_num_sections(const struct fw_img * fw,int start)823 static inline int iwl_pcie_get_num_sections(const struct fw_img *fw,
824 int start)
825 {
826 int i = 0;
827
828 while (start < fw->num_sec &&
829 fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION &&
830 fw->sec[start].offset != PAGING_SEPARATOR_SECTION) {
831 start++;
832 i++;
833 }
834
835 return i;
836 }
837
iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans * trans)838 static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans)
839 {
840 struct iwl_self_init_dram *dram = &trans->init_dram;
841 int i;
842
843 if (!dram->fw) {
844 WARN_ON(dram->fw_cnt);
845 return;
846 }
847
848 for (i = 0; i < dram->fw_cnt; i++)
849 dma_free_coherent(trans->dev, dram->fw[i].size,
850 dram->fw[i].block, dram->fw[i].physical);
851
852 kfree(dram->fw);
853 dram->fw_cnt = 0;
854 dram->fw = NULL;
855 }
856
iwl_disable_interrupts(struct iwl_trans * trans)857 static inline void iwl_disable_interrupts(struct iwl_trans *trans)
858 {
859 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
860
861 spin_lock_bh(&trans_pcie->irq_lock);
862 _iwl_disable_interrupts(trans);
863 spin_unlock_bh(&trans_pcie->irq_lock);
864 }
865
_iwl_enable_interrupts(struct iwl_trans * trans)866 static inline void _iwl_enable_interrupts(struct iwl_trans *trans)
867 {
868 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
869
870 IWL_DEBUG_ISR(trans, "Enabling interrupts\n");
871 set_bit(STATUS_INT_ENABLED, &trans->status);
872 if (!trans_pcie->msix_enabled) {
873 trans_pcie->inta_mask = CSR_INI_SET_MASK;
874 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
875 } else {
876 /*
877 * fh/hw_mask keeps all the unmasked causes.
878 * Unlike msi, in msix cause is enabled when it is unset.
879 */
880 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
881 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
882 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
883 ~trans_pcie->fh_mask);
884 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
885 ~trans_pcie->hw_mask);
886 }
887 }
888
iwl_enable_interrupts(struct iwl_trans * trans)889 static inline void iwl_enable_interrupts(struct iwl_trans *trans)
890 {
891 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
892
893 spin_lock_bh(&trans_pcie->irq_lock);
894 _iwl_enable_interrupts(trans);
895 spin_unlock_bh(&trans_pcie->irq_lock);
896 }
iwl_enable_hw_int_msk_msix(struct iwl_trans * trans,u32 msk)897 static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk)
898 {
899 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
900
901 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk);
902 trans_pcie->hw_mask = msk;
903 }
904
iwl_enable_fh_int_msk_msix(struct iwl_trans * trans,u32 msk)905 static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk)
906 {
907 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
908
909 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk);
910 trans_pcie->fh_mask = msk;
911 }
912
iwl_enable_fw_load_int(struct iwl_trans * trans)913 static inline void iwl_enable_fw_load_int(struct iwl_trans *trans)
914 {
915 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
916
917 IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n");
918 if (!trans_pcie->msix_enabled) {
919 trans_pcie->inta_mask = CSR_INT_BIT_FH_TX;
920 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
921 } else {
922 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD,
923 trans_pcie->hw_init_mask);
924 iwl_enable_fh_int_msk_msix(trans,
925 MSIX_FH_INT_CAUSES_D2S_CH0_NUM);
926 }
927 }
928
iwl_enable_fw_load_int_ctx_info(struct iwl_trans * trans,bool top_reset)929 static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans *trans,
930 bool top_reset)
931 {
932 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
933
934 IWL_DEBUG_ISR(trans, "Enabling %s interrupt only\n",
935 top_reset ? "RESET" : "ALIVE");
936
937 if (!trans_pcie->msix_enabled) {
938 /*
939 * When we'll receive the ALIVE interrupt, the ISR will call
940 * iwl_enable_fw_load_int_ctx_info again to set the ALIVE
941 * interrupt (which is not really needed anymore) but also the
942 * RX interrupt which will allow us to receive the ALIVE
943 * notification (which is Rx) and continue the flow.
944 */
945 if (top_reset)
946 trans_pcie->inta_mask = CSR_INT_BIT_RESET_DONE;
947 else
948 trans_pcie->inta_mask = CSR_INT_BIT_ALIVE |
949 CSR_INT_BIT_FH_RX;
950 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
951 } else {
952 u32 val = top_reset ? MSIX_HW_INT_CAUSES_REG_RESET_DONE
953 : MSIX_HW_INT_CAUSES_REG_ALIVE;
954
955 iwl_enable_hw_int_msk_msix(trans, val);
956
957 if (top_reset)
958 return;
959 /*
960 * Leave all the FH causes enabled to get the ALIVE
961 * notification.
962 */
963 iwl_enable_fh_int_msk_msix(trans, trans_pcie->fh_init_mask);
964 }
965 }
966
queue_name(struct device * dev,struct iwl_trans_pcie * trans_p,int i)967 static inline const char *queue_name(struct device *dev,
968 struct iwl_trans_pcie *trans_p, int i)
969 {
970 if (trans_p->shared_vec_mask) {
971 int vec = trans_p->shared_vec_mask &
972 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
973
974 if (i == 0)
975 return DRV_NAME ":shared_IRQ";
976
977 return devm_kasprintf(dev, GFP_KERNEL,
978 DRV_NAME ":queue_%d", i + vec);
979 }
980 if (i == 0)
981 return DRV_NAME ":default_queue";
982
983 if (i == trans_p->alloc_vecs - 1)
984 return DRV_NAME ":exception";
985
986 return devm_kasprintf(dev, GFP_KERNEL,
987 DRV_NAME ":queue_%d", i);
988 }
989
iwl_enable_rfkill_int(struct iwl_trans * trans)990 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans)
991 {
992 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
993
994 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n");
995 if (!trans_pcie->msix_enabled) {
996 trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL;
997 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask);
998 } else {
999 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD,
1000 trans_pcie->fh_init_mask);
1001 iwl_enable_hw_int_msk_msix(trans,
1002 MSIX_HW_INT_CAUSES_REG_RF_KILL);
1003 }
1004
1005 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_9000) {
1006 /*
1007 * On 9000-series devices this bit isn't enabled by default, so
1008 * when we power down the device we need set the bit to allow it
1009 * to wake up the PCI-E bus for RF-kill interrupts.
1010 */
1011 iwl_set_bit(trans, CSR_GP_CNTRL,
1012 CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN);
1013 }
1014 }
1015
1016 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans, bool from_irq);
1017
iwl_is_rfkill_set(struct iwl_trans * trans)1018 static inline bool iwl_is_rfkill_set(struct iwl_trans *trans)
1019 {
1020 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1021
1022 lockdep_assert_held(&trans_pcie->mutex);
1023
1024 if (trans_pcie->debug_rfkill == 1)
1025 return true;
1026
1027 return !(iwl_read32(trans, CSR_GP_CNTRL) &
1028 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1029 }
1030
__iwl_trans_pcie_set_bits_mask(struct iwl_trans * trans,u32 reg,u32 mask,u32 value)1031 static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
1032 u32 reg, u32 mask, u32 value)
1033 {
1034 u32 v;
1035
1036 #ifdef CONFIG_IWLWIFI_DEBUG
1037 WARN_ON_ONCE(value & ~mask);
1038 #endif
1039
1040 v = iwl_read32(trans, reg);
1041 v &= ~mask;
1042 v |= value;
1043 iwl_write32(trans, reg, v);
1044 }
1045
__iwl_trans_pcie_clear_bit(struct iwl_trans * trans,u32 reg,u32 mask)1046 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
1047 u32 reg, u32 mask)
1048 {
1049 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
1050 }
1051
__iwl_trans_pcie_set_bit(struct iwl_trans * trans,u32 reg,u32 mask)1052 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
1053 u32 reg, u32 mask)
1054 {
1055 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
1056 }
1057
iwl_pcie_dbg_on(struct iwl_trans * trans)1058 static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans)
1059 {
1060 return (trans->dbg.dest_tlv || iwl_trans_dbg_ini_valid(trans));
1061 }
1062
1063 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state, bool from_irq);
1064 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans);
1065
1066 #ifdef CONFIG_IWLWIFI_DEBUGFS
1067 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans);
1068 void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans);
1069 #else
iwl_trans_pcie_dbgfs_register(struct iwl_trans * trans)1070 static inline void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) { }
1071 #endif
1072
1073 void iwl_pcie_rx_allocator_work(struct work_struct *data);
1074
1075 /* common trans ops for all generations transports */
1076 void iwl_trans_pcie_op_mode_enter(struct iwl_trans *trans);
1077 int iwl_trans_pcie_start_hw(struct iwl_trans *trans);
1078 void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans);
1079 void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val);
1080 void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val);
1081 u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs);
1082 u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg);
1083 void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, u32 val);
1084 int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1085 void *buf, int dwords);
1086 int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1087 const void *buf, int dwords);
1088 int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, bool retake_ownership);
1089 struct iwl_trans_dump_data *
1090 iwl_trans_pcie_dump_data(struct iwl_trans *trans, u32 dump_mask,
1091 const struct iwl_dump_sanitize_ops *sanitize_ops,
1092 void *sanitize_ctx);
1093 int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1094 enum iwl_d3_status *status,
1095 bool test, bool reset);
1096 int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, bool reset);
1097 void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable);
1098 void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans);
1099 void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1100 u32 mask, u32 value);
1101 int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs,
1102 u32 *val);
1103 bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans);
1104 void __releases(nic_access_nobh)
1105 iwl_trans_pcie_release_nic_access(struct iwl_trans *trans);
1106 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power);
1107
1108 /* transport gen 1 exported functions */
1109 void iwl_trans_pcie_fw_alive(struct iwl_trans *trans);
1110 int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1111 const struct iwl_fw *fw,
1112 const struct fw_img *img,
1113 bool run_in_rfkill);
1114 void iwl_trans_pcie_stop_device(struct iwl_trans *trans);
1115
1116 /* common functions that are used by gen2 transport */
1117 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans);
1118 void iwl_pcie_apm_config(struct iwl_trans *trans);
1119 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans);
1120 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans);
1121 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans);
1122 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1123 bool was_in_rfkill);
1124 void iwl_pcie_apm_stop_master(struct iwl_trans *trans);
1125 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie);
1126 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
1127 struct iwl_dma_ptr *ptr, size_t size);
1128 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr);
1129 void iwl_pcie_apply_destination(struct iwl_trans *trans);
1130
1131 /* transport gen 2 exported functions */
1132 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans,
1133 const struct iwl_fw *fw,
1134 const struct fw_img *img,
1135 bool run_in_rfkill);
1136 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans);
1137 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans);
1138 int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans,
1139 struct iwl_host_cmd *cmd);
1140 int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1141 struct iwl_host_cmd *cmd);
1142 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans,
1143 u32 dst_addr, u64 src_addr, u32 byte_cnt);
1144 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans,
1145 u32 dst_addr, u64 src_addr, u32 byte_cnt);
1146 int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
1147 struct iwl_trans_rxq_dma_data *data);
1148
1149 #endif /* __iwl_trans_int_pcie_h__ */
1150