1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * it87.c - Part of lm_sensors, Linux kernel modules for hardware 4 * monitoring. 5 * 6 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a 7 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in 8 * addition to an Environment Controller (Enhanced Hardware Monitor and 9 * Fan Controller) 10 * 11 * This driver supports only the Environment Controller in the IT8705F and 12 * similar parts. The other devices are supported by different drivers. 13 * 14 * Supports: IT8603E Super I/O chip w/LPC interface 15 * IT8620E Super I/O chip w/LPC interface 16 * IT8622E Super I/O chip w/LPC interface 17 * IT8623E Super I/O chip w/LPC interface 18 * IT8628E Super I/O chip w/LPC interface 19 * IT8689E Super I/O chip w/LPC interface 20 * IT8705F Super I/O chip w/LPC interface 21 * IT8712F Super I/O chip w/LPC interface 22 * IT8716F Super I/O chip w/LPC interface 23 * IT8718F Super I/O chip w/LPC interface 24 * IT8720F Super I/O chip w/LPC interface 25 * IT8721F Super I/O chip w/LPC interface 26 * IT8726F Super I/O chip w/LPC interface 27 * IT8728F Super I/O chip w/LPC interface 28 * IT8732F Super I/O chip w/LPC interface 29 * IT8758E Super I/O chip w/LPC interface 30 * IT8771E Super I/O chip w/LPC interface 31 * IT8772E Super I/O chip w/LPC interface 32 * IT8781F Super I/O chip w/LPC interface 33 * IT8782F Super I/O chip w/LPC interface 34 * IT8783E/F Super I/O chip w/LPC interface 35 * IT8786E Super I/O chip w/LPC interface 36 * IT8790E Super I/O chip w/LPC interface 37 * IT8792E Super I/O chip w/LPC interface 38 * IT87952E Super I/O chip w/LPC interface 39 * Sis950 A clone of the IT8705F 40 * 41 * Copyright (C) 2001 Chris Gauthron 42 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de> 43 */ 44 45 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 46 47 #include <linux/bitops.h> 48 #include <linux/module.h> 49 #include <linux/init.h> 50 #include <linux/slab.h> 51 #include <linux/jiffies.h> 52 #include <linux/platform_device.h> 53 #include <linux/hwmon.h> 54 #include <linux/hwmon-sysfs.h> 55 #include <linux/hwmon-vid.h> 56 #include <linux/err.h> 57 #include <linux/mutex.h> 58 #include <linux/sysfs.h> 59 #include <linux/string.h> 60 #include <linux/dmi.h> 61 #include <linux/acpi.h> 62 #include <linux/io.h> 63 64 #define DRVNAME "it87" 65 66 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732, 67 it8771, it8772, it8781, it8782, it8783, it8786, it8790, 68 it8792, it8603, it8620, it8622, it8628, it8689, it87952 }; 69 70 static struct platform_device *it87_pdev[2]; 71 72 #define REG_2E 0x2e /* The register to read/write */ 73 #define REG_4E 0x4e /* Secondary register to read/write */ 74 75 #define DEV 0x07 /* Register: Logical device select */ 76 #define PME 0x04 /* The device with the fan registers in it */ 77 78 /* The device with the IT8718F/IT8720F VID value in it */ 79 #define GPIO 0x07 80 81 #define DEVID 0x20 /* Register: Device ID */ 82 #define DEVREV 0x22 /* Register: Device Revision */ 83 84 static inline void __superio_enter(int ioreg) 85 { 86 outb(0x87, ioreg); 87 outb(0x01, ioreg); 88 outb(0x55, ioreg); 89 outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg); 90 } 91 92 static inline int superio_inb(int ioreg, int reg) 93 { 94 outb(reg, ioreg); 95 return inb(ioreg + 1); 96 } 97 98 static inline void superio_outb(int ioreg, int reg, int val) 99 { 100 outb(reg, ioreg); 101 outb(val, ioreg + 1); 102 } 103 104 static int superio_inw(int ioreg, int reg) 105 { 106 int val; 107 108 outb(reg++, ioreg); 109 val = inb(ioreg + 1) << 8; 110 outb(reg, ioreg); 111 val |= inb(ioreg + 1); 112 return val; 113 } 114 115 static inline void superio_select(int ioreg, int ldn) 116 { 117 outb(DEV, ioreg); 118 outb(ldn, ioreg + 1); 119 } 120 121 static inline int superio_enter(int ioreg, bool noentry) 122 { 123 /* 124 * Try to reserve ioreg and ioreg + 1 for exclusive access. 125 */ 126 if (!request_muxed_region(ioreg, 2, DRVNAME)) 127 return -EBUSY; 128 129 if (!noentry) 130 __superio_enter(ioreg); 131 return 0; 132 } 133 134 static inline void superio_exit(int ioreg, bool noexit) 135 { 136 if (!noexit) { 137 outb(0x02, ioreg); 138 outb(0x02, ioreg + 1); 139 } 140 release_region(ioreg, 2); 141 } 142 143 /* Logical device 4 registers */ 144 #define IT8712F_DEVID 0x8712 145 #define IT8705F_DEVID 0x8705 146 #define IT8716F_DEVID 0x8716 147 #define IT8718F_DEVID 0x8718 148 #define IT8720F_DEVID 0x8720 149 #define IT8721F_DEVID 0x8721 150 #define IT8726F_DEVID 0x8726 151 #define IT8728F_DEVID 0x8728 152 #define IT8732F_DEVID 0x8732 153 #define IT8792E_DEVID 0x8733 154 #define IT8771E_DEVID 0x8771 155 #define IT8772E_DEVID 0x8772 156 #define IT8781F_DEVID 0x8781 157 #define IT8782F_DEVID 0x8782 158 #define IT8783E_DEVID 0x8783 159 #define IT8786E_DEVID 0x8786 160 #define IT8790E_DEVID 0x8790 161 #define IT8603E_DEVID 0x8603 162 #define IT8620E_DEVID 0x8620 163 #define IT8622E_DEVID 0x8622 164 #define IT8623E_DEVID 0x8623 165 #define IT8628E_DEVID 0x8628 166 #define IT8689E_DEVID 0x8689 167 #define IT87952E_DEVID 0x8695 168 169 /* Logical device 4 (Environmental Monitor) registers */ 170 #define IT87_ACT_REG 0x30 171 #define IT87_BASE_REG 0x60 172 #define IT87_SPECIAL_CFG_REG 0xf3 /* special configuration register */ 173 174 /* Logical device 7 registers (IT8712F and later) */ 175 #define IT87_SIO_GPIO1_REG 0x25 176 #define IT87_SIO_GPIO2_REG 0x26 177 #define IT87_SIO_GPIO3_REG 0x27 178 #define IT87_SIO_GPIO4_REG 0x28 179 #define IT87_SIO_GPIO5_REG 0x29 180 #define IT87_SIO_PINX1_REG 0x2a /* Pin selection */ 181 #define IT87_SIO_PINX2_REG 0x2c /* Pin selection */ 182 #define IT87_SIO_SPI_REG 0xef /* SPI function pin select */ 183 #define IT87_SIO_VID_REG 0xfc /* VID value */ 184 #define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */ 185 186 /* Force chip IDs to specified values. Should only be used for testing */ 187 static unsigned short force_id[2]; 188 static unsigned int force_id_cnt; 189 190 /* ACPI resource conflicts are ignored if this parameter is set to 1 */ 191 static bool ignore_resource_conflict; 192 193 /* Update battery voltage after every reading if true */ 194 static bool update_vbat; 195 196 /* Not all BIOSes properly configure the PWM registers */ 197 static bool fix_pwm_polarity; 198 199 /* Many IT87 constants specified below */ 200 201 /* Length of ISA address segment */ 202 #define IT87_EXTENT 8 203 204 /* Length of ISA address segment for Environmental Controller */ 205 #define IT87_EC_EXTENT 2 206 207 /* Offset of EC registers from ISA base address */ 208 #define IT87_EC_OFFSET 5 209 210 /* Where are the ISA address/data registers relative to the EC base address */ 211 #define IT87_ADDR_REG_OFFSET 0 212 #define IT87_DATA_REG_OFFSET 1 213 214 /*----- The IT87 registers -----*/ 215 216 #define IT87_REG_CONFIG 0x00 217 218 #define IT87_REG_ALARM1 0x01 219 #define IT87_REG_ALARM2 0x02 220 #define IT87_REG_ALARM3 0x03 221 222 /* 223 * The IT8718F and IT8720F have the VID value in a different register, in 224 * Super-I/O configuration space. 225 */ 226 #define IT87_REG_VID 0x0a 227 228 /* Interface Selection register on other chips */ 229 #define IT87_REG_IFSEL 0x0a 230 231 /* 232 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b 233 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer 234 * mode. 235 */ 236 #define IT87_REG_FAN_DIV 0x0b 237 #define IT87_REG_FAN_16BIT 0x0c 238 239 /* 240 * Monitors: 241 * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12) 242 * - up to 6 temp (1 to 6) 243 * - up to 6 fan (1 to 6) 244 */ 245 246 static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c }; 247 static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e }; 248 static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d }; 249 static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f }; 250 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59 }; 251 252 #define IT87_REG_FAN_MAIN_CTRL 0x13 253 #define IT87_REG_FAN_CTL 0x14 254 static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf }; 255 static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab }; 256 257 static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 258 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e }; 259 260 #define IT87_REG_TEMP(nr) (0x29 + (nr)) 261 262 #define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2) 263 #define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2) 264 #define IT87_REG_TEMP_HIGH(nr) (0x40 + (nr) * 2) 265 #define IT87_REG_TEMP_LOW(nr) (0x41 + (nr) * 2) 266 267 #define IT87_REG_VIN_ENABLE 0x50 268 #define IT87_REG_TEMP_ENABLE 0x51 269 #define IT87_REG_TEMP_EXTRA 0x55 270 #define IT87_REG_BEEP_ENABLE 0x5c 271 272 #define IT87_REG_CHIPID 0x58 273 274 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 }; 275 276 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i)) 277 #define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i)) 278 279 #define IT87_REG_TEMP456_ENABLE 0x77 280 281 #define NUM_VIN ARRAY_SIZE(IT87_REG_VIN) 282 #define NUM_VIN_LIMIT 8 283 #define NUM_TEMP 6 284 #define NUM_TEMP_OFFSET ARRAY_SIZE(IT87_REG_TEMP_OFFSET) 285 #define NUM_TEMP_LIMIT 3 286 #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN) 287 #define NUM_FAN_DIV 3 288 #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM) 289 #define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM) 290 291 struct it87_devices { 292 const char *name; 293 const char * const model; 294 u32 features; 295 u8 peci_mask; 296 u8 old_peci_mask; 297 u8 smbus_bitmap; /* SMBus enable bits in extra config register */ 298 u8 ec_special_config; 299 }; 300 301 #define FEAT_12MV_ADC BIT(0) 302 #define FEAT_NEWER_AUTOPWM BIT(1) 303 #define FEAT_OLD_AUTOPWM BIT(2) 304 #define FEAT_16BIT_FANS BIT(3) 305 #define FEAT_TEMP_OFFSET BIT(4) 306 #define FEAT_TEMP_PECI BIT(5) 307 #define FEAT_TEMP_OLD_PECI BIT(6) 308 #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */ 309 #define FEAT_FIVE_FANS BIT(8) /* Supports five fans */ 310 #define FEAT_VID BIT(9) /* Set if chip supports VID */ 311 #define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */ 312 #define FEAT_SIX_FANS BIT(11) /* Supports six fans */ 313 #define FEAT_10_9MV_ADC BIT(12) 314 #define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */ 315 #define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */ 316 #define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */ 317 #define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */ 318 #define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */ 319 #define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */ 320 /* 321 * Disabling configuration mode on some chips can result in system 322 * hang-ups and access failures to the Super-IO chip at the 323 * second SIO address. Never exit configuration mode on these 324 * chips to avoid the problem. 325 */ 326 #define FEAT_NOCONF BIT(19) /* Chip conf mode enabled on startup */ 327 #define FEAT_FOUR_FANS BIT(20) /* Supports four fans */ 328 #define FEAT_FOUR_PWM BIT(21) /* Supports four fan controls */ 329 #define FEAT_FOUR_TEMP BIT(22) 330 #define FEAT_FANCTL_ONOFF BIT(23) /* chip has FAN_CTL ON/OFF */ 331 332 static const struct it87_devices it87_devices[] = { 333 [it87] = { 334 .name = "it87", 335 .model = "IT87F", 336 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF, 337 /* may need to overwrite */ 338 }, 339 [it8712] = { 340 .name = "it8712", 341 .model = "IT8712F", 342 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF, 343 /* may need to overwrite */ 344 }, 345 [it8716] = { 346 .name = "it8716", 347 .model = "IT8716F", 348 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID 349 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2 350 | FEAT_FANCTL_ONOFF, 351 }, 352 [it8718] = { 353 .name = "it8718", 354 .model = "IT8718F", 355 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID 356 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS 357 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, 358 .old_peci_mask = 0x4, 359 }, 360 [it8720] = { 361 .name = "it8720", 362 .model = "IT8720F", 363 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET | FEAT_VID 364 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS 365 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, 366 .old_peci_mask = 0x4, 367 }, 368 [it8721] = { 369 .name = "it8721", 370 .model = "IT8721F", 371 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 372 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI 373 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL 374 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, 375 .peci_mask = 0x05, 376 .old_peci_mask = 0x02, /* Actually reports PCH */ 377 }, 378 [it8728] = { 379 .name = "it8728", 380 .model = "IT8728F", 381 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 382 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS 383 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 384 | FEAT_FANCTL_ONOFF, 385 .peci_mask = 0x07, 386 }, 387 [it8732] = { 388 .name = "it8732", 389 .model = "IT8732F", 390 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS 391 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI 392 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS 393 | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF, 394 .peci_mask = 0x07, 395 .old_peci_mask = 0x02, /* Actually reports PCH */ 396 }, 397 [it8771] = { 398 .name = "it8771", 399 .model = "IT8771E", 400 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 401 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 402 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, 403 /* PECI: guesswork */ 404 /* 12mV ADC (OHM) */ 405 /* 16 bit fans (OHM) */ 406 /* three fans, always 16 bit (guesswork) */ 407 .peci_mask = 0x07, 408 }, 409 [it8772] = { 410 .name = "it8772", 411 .model = "IT8772E", 412 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 413 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 414 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, 415 /* PECI (coreboot) */ 416 /* 12mV ADC (HWSensors4, OHM) */ 417 /* 16 bit fans (HWSensors4, OHM) */ 418 /* three fans, always 16 bit (datasheet) */ 419 .peci_mask = 0x07, 420 }, 421 [it8781] = { 422 .name = "it8781", 423 .model = "IT8781F", 424 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET 425 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2 426 | FEAT_FANCTL_ONOFF, 427 .old_peci_mask = 0x4, 428 }, 429 [it8782] = { 430 .name = "it8782", 431 .model = "IT8782F", 432 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET 433 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2 434 | FEAT_FANCTL_ONOFF, 435 .old_peci_mask = 0x4, 436 }, 437 [it8783] = { 438 .name = "it8783", 439 .model = "IT8783E/F", 440 .features = FEAT_16BIT_FANS | FEAT_TEMP_OFFSET 441 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2 442 | FEAT_FANCTL_ONOFF, 443 .old_peci_mask = 0x4, 444 }, 445 [it8786] = { 446 .name = "it8786", 447 .model = "IT8786E", 448 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 449 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 450 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF, 451 .peci_mask = 0x07, 452 }, 453 [it8790] = { 454 .name = "it8790", 455 .model = "IT8790E", 456 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 457 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 458 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF | FEAT_NOCONF, 459 .peci_mask = 0x07, 460 }, 461 [it8792] = { 462 .name = "it8792", 463 .model = "IT8792E/IT8795E", 464 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS 465 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI 466 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FANCTL_ONOFF 467 | FEAT_NOCONF, 468 .peci_mask = 0x07, 469 .old_peci_mask = 0x02, /* Actually reports PCH */ 470 }, 471 [it8603] = { 472 .name = "it8603", 473 .model = "IT8603E", 474 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 475 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL 476 | FEAT_AVCC3 | FEAT_PWM_FREQ2, 477 .peci_mask = 0x07, 478 }, 479 [it8620] = { 480 .name = "it8620", 481 .model = "IT8620E", 482 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 483 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS 484 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 485 | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_FANCTL_ONOFF, 486 .peci_mask = 0x07, 487 }, 488 [it8622] = { 489 .name = "it8622", 490 .model = "IT8622E", 491 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 492 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_FIVE_FANS 493 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 494 | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_FOUR_TEMP, 495 .peci_mask = 0x07, 496 .smbus_bitmap = BIT(1) | BIT(2), 497 }, 498 [it8628] = { 499 .name = "it8628", 500 .model = "IT8628E", 501 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 502 | FEAT_TEMP_OFFSET | FEAT_TEMP_PECI | FEAT_SIX_FANS 503 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2 504 | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_FANCTL_ONOFF, 505 .peci_mask = 0x07, 506 }, 507 [it8689] = { 508 .name = "it8689", 509 .model = "IT8689E", 510 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS 511 | FEAT_TEMP_OFFSET | FEAT_SIX_FANS | FEAT_IN7_INTERNAL 512 | FEAT_SIX_PWM | FEAT_PWM_FREQ2 | FEAT_SIX_TEMP | FEAT_AVCC3 513 | FEAT_FANCTL_ONOFF, 514 .smbus_bitmap = BIT(1) | BIT(2), 515 }, 516 [it87952] = { 517 .name = "it87952", 518 .model = "IT87952E", 519 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS 520 | FEAT_TEMP_OFFSET | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI 521 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FANCTL_ONOFF 522 | FEAT_NOCONF, 523 .peci_mask = 0x07, 524 .old_peci_mask = 0x02, /* Actually reports PCH */ 525 }, 526 }; 527 528 #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS) 529 #define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC) 530 #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC) 531 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM) 532 #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM) 533 #define has_temp_offset(data) ((data)->features & FEAT_TEMP_OFFSET) 534 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \ 535 ((data)->peci_mask & BIT(nr))) 536 #define has_temp_old_peci(data, nr) \ 537 (((data)->features & FEAT_TEMP_OLD_PECI) && \ 538 ((data)->old_peci_mask & BIT(nr))) 539 #define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG) 540 #define has_four_fans(data) ((data)->features & (FEAT_FOUR_FANS | \ 541 FEAT_FIVE_FANS | \ 542 FEAT_SIX_FANS)) 543 #define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \ 544 FEAT_SIX_FANS)) 545 #define has_six_fans(data) ((data)->features & FEAT_SIX_FANS) 546 #define has_vid(data) ((data)->features & FEAT_VID) 547 #define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL) 548 #define has_avcc3(data) ((data)->features & FEAT_AVCC3) 549 #define has_four_pwm(data) ((data)->features & (FEAT_FOUR_PWM | \ 550 FEAT_FIVE_PWM | \ 551 FEAT_SIX_PWM)) 552 #define has_five_pwm(data) ((data)->features & (FEAT_FIVE_PWM | \ 553 FEAT_SIX_PWM)) 554 #define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM) 555 #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2) 556 #define has_four_temp(data) ((data)->features & FEAT_FOUR_TEMP) 557 #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP) 558 #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V) 559 #define has_noconf(data) ((data)->features & FEAT_NOCONF) 560 #define has_scaling(data) ((data)->features & (FEAT_12MV_ADC | \ 561 FEAT_10_9MV_ADC)) 562 #define has_fanctl_onoff(data) ((data)->features & FEAT_FANCTL_ONOFF) 563 564 struct it87_sio_data { 565 int sioaddr; 566 enum chips type; 567 /* Values read from Super-I/O config space */ 568 u8 revision; 569 u8 vid_value; 570 u8 beep_pin; 571 u8 internal; /* Internal sensors can be labeled */ 572 bool need_in7_reroute; 573 /* Features skipped based on config or DMI */ 574 u16 skip_in; 575 u8 skip_vid; 576 u8 skip_fan; 577 u8 skip_pwm; 578 u8 skip_temp; 579 u8 smbus_bitmap; 580 u8 ec_special_config; 581 }; 582 583 /* 584 * For each registered chip, we need to keep some data in memory. 585 * The structure is dynamically allocated. 586 */ 587 struct it87_data { 588 const struct attribute_group *groups[7]; 589 int sioaddr; 590 enum chips type; 591 u32 features; 592 u8 peci_mask; 593 u8 old_peci_mask; 594 595 u8 smbus_bitmap; /* !=0 if SMBus needs to be disabled */ 596 u8 ec_special_config; /* EC special config register restore value */ 597 598 unsigned short addr; 599 const char *name; 600 struct mutex update_lock; 601 bool valid; /* true if following fields are valid */ 602 unsigned long last_updated; /* In jiffies */ 603 604 u16 in_scaled; /* Internal voltage sensors are scaled */ 605 u16 in_internal; /* Bitfield, internal sensors (for labels) */ 606 u16 has_in; /* Bitfield, voltage sensors enabled */ 607 u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */ 608 bool need_in7_reroute; 609 u8 has_fan; /* Bitfield, fans enabled */ 610 u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */ 611 u8 has_temp; /* Bitfield, temp sensors enabled */ 612 s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */ 613 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */ 614 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */ 615 u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */ 616 bool has_vid; /* True if VID supported */ 617 u8 vid; /* Register encoding, combined */ 618 u8 vrm; 619 u32 alarms; /* Register encoding, combined */ 620 bool has_beep; /* true if beep supported */ 621 u8 beeps; /* Register encoding */ 622 u8 fan_main_ctrl; /* Register value */ 623 u8 fan_ctl; /* Register value */ 624 625 /* 626 * The following 3 arrays correspond to the same registers up to 627 * the IT8720F. The meaning of bits 6-0 depends on the value of bit 628 * 7, and we want to preserve settings on mode changes, so we have 629 * to track all values separately. 630 * Starting with the IT8721F, the manual PWM duty cycles are stored 631 * in separate registers (8-bit values), so the separate tracking 632 * is no longer needed, but it is still done to keep the driver 633 * simple. 634 */ 635 u8 has_pwm; /* Bitfield, pwm control enabled */ 636 u8 pwm_ctrl[NUM_PWM]; /* Register value */ 637 u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */ 638 u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */ 639 640 /* Automatic fan speed control registers */ 641 u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */ 642 s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */ 643 }; 644 645 /* Board specific settings from DMI matching */ 646 struct it87_dmi_data { 647 u8 skip_pwm; /* pwm channels to skip for this board */ 648 }; 649 650 /* Global for results from DMI matching, if needed */ 651 static struct it87_dmi_data *dmi_data; 652 653 static int adc_lsb(const struct it87_data *data, int nr) 654 { 655 int lsb; 656 657 if (has_12mv_adc(data)) 658 lsb = 120; 659 else if (has_10_9mv_adc(data)) 660 lsb = 109; 661 else 662 lsb = 160; 663 if (data->in_scaled & BIT(nr)) 664 lsb <<= 1; 665 return lsb; 666 } 667 668 static u8 in_to_reg(const struct it87_data *data, int nr, long val) 669 { 670 val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr)); 671 return clamp_val(val, 0, 255); 672 } 673 674 static int in_from_reg(const struct it87_data *data, int nr, int val) 675 { 676 return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10); 677 } 678 679 static inline u8 FAN_TO_REG(long rpm, int div) 680 { 681 if (rpm == 0) 682 return 255; 683 rpm = clamp_val(rpm, 1, 1000000); 684 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254); 685 } 686 687 static inline u16 FAN16_TO_REG(long rpm) 688 { 689 if (rpm == 0) 690 return 0xffff; 691 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe); 692 } 693 694 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \ 695 1350000 / ((val) * (div))) 696 /* The divider is fixed to 2 in 16-bit mode */ 697 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \ 698 1350000 / ((val) * 2)) 699 700 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \ 701 ((val) + 500) / 1000), -128, 127)) 702 #define TEMP_FROM_REG(val) ((val) * 1000) 703 704 static u8 pwm_to_reg(const struct it87_data *data, long val) 705 { 706 if (has_newer_autopwm(data)) 707 return val; 708 else 709 return val >> 1; 710 } 711 712 static int pwm_from_reg(const struct it87_data *data, u8 reg) 713 { 714 if (has_newer_autopwm(data)) 715 return reg; 716 else 717 return (reg & 0x7f) << 1; 718 } 719 720 static int DIV_TO_REG(int val) 721 { 722 int answer = 0; 723 724 while (answer < 7 && (val >>= 1)) 725 answer++; 726 return answer; 727 } 728 729 #define DIV_FROM_REG(val) BIT(val) 730 731 /* 732 * PWM base frequencies. The frequency has to be divided by either 128 or 256, 733 * depending on the chip type, to calculate the actual PWM frequency. 734 * 735 * Some of the chip datasheets suggest a base frequency of 51 kHz instead 736 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency 737 * of 200 Hz. Sometimes both PWM frequency select registers are affected, 738 * sometimes just one. It is unknown if this is a datasheet error or real, 739 * so this is ignored for now. 740 */ 741 static const unsigned int pwm_freq[8] = { 742 48000000, 743 24000000, 744 12000000, 745 8000000, 746 6000000, 747 3000000, 748 1500000, 749 750000, 750 }; 751 752 static int smbus_disable(struct it87_data *data) 753 { 754 int err; 755 756 if (data->smbus_bitmap) { 757 err = superio_enter(data->sioaddr, has_noconf(data)); 758 if (err) 759 return err; 760 superio_select(data->sioaddr, PME); 761 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG, 762 data->ec_special_config & ~data->smbus_bitmap); 763 superio_exit(data->sioaddr, has_noconf(data)); 764 } 765 return 0; 766 } 767 768 static int smbus_enable(struct it87_data *data) 769 { 770 int err; 771 772 if (data->smbus_bitmap) { 773 err = superio_enter(data->sioaddr, has_noconf(data)); 774 if (err) 775 return err; 776 777 superio_select(data->sioaddr, PME); 778 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG, 779 data->ec_special_config); 780 superio_exit(data->sioaddr, has_noconf(data)); 781 } 782 return 0; 783 } 784 785 /* 786 * Must be called with data->update_lock held, except during initialization. 787 * Must be called with SMBus accesses disabled. 788 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks, 789 * would slow down the IT87 access and should not be necessary. 790 */ 791 static int it87_read_value(struct it87_data *data, u8 reg) 792 { 793 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); 794 return inb_p(data->addr + IT87_DATA_REG_OFFSET); 795 } 796 797 /* 798 * Must be called with data->update_lock held, except during initialization. 799 * Must be called with SMBus accesses disabled. 800 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks, 801 * would slow down the IT87 access and should not be necessary. 802 */ 803 static void it87_write_value(struct it87_data *data, u8 reg, u8 value) 804 { 805 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET); 806 outb_p(value, data->addr + IT87_DATA_REG_OFFSET); 807 } 808 809 static void it87_update_pwm_ctrl(struct it87_data *data, int nr) 810 { 811 data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM[nr]); 812 if (has_newer_autopwm(data)) { 813 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; 814 data->pwm_duty[nr] = it87_read_value(data, 815 IT87_REG_PWM_DUTY[nr]); 816 } else { 817 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */ 818 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; 819 else /* Manual mode */ 820 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f; 821 } 822 823 if (has_old_autopwm(data)) { 824 int i; 825 826 for (i = 0; i < 5 ; i++) 827 data->auto_temp[nr][i] = it87_read_value(data, 828 IT87_REG_AUTO_TEMP(nr, i)); 829 for (i = 0; i < 3 ; i++) 830 data->auto_pwm[nr][i] = it87_read_value(data, 831 IT87_REG_AUTO_PWM(nr, i)); 832 } else if (has_newer_autopwm(data)) { 833 int i; 834 835 /* 836 * 0: temperature hysteresis (base + 5) 837 * 1: fan off temperature (base + 0) 838 * 2: fan start temperature (base + 1) 839 * 3: fan max temperature (base + 2) 840 */ 841 data->auto_temp[nr][0] = 842 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5)); 843 844 for (i = 0; i < 3 ; i++) 845 data->auto_temp[nr][i + 1] = 846 it87_read_value(data, 847 IT87_REG_AUTO_TEMP(nr, i)); 848 /* 849 * 0: start pwm value (base + 3) 850 * 1: pwm slope (base + 4, 1/8th pwm) 851 */ 852 data->auto_pwm[nr][0] = 853 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3)); 854 data->auto_pwm[nr][1] = 855 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4)); 856 } 857 } 858 859 static int it87_lock(struct it87_data *data) 860 { 861 int err; 862 863 mutex_lock(&data->update_lock); 864 err = smbus_disable(data); 865 if (err) 866 mutex_unlock(&data->update_lock); 867 return err; 868 } 869 870 static void it87_unlock(struct it87_data *data) 871 { 872 smbus_enable(data); 873 mutex_unlock(&data->update_lock); 874 } 875 876 static struct it87_data *it87_update_device(struct device *dev) 877 { 878 struct it87_data *data = dev_get_drvdata(dev); 879 struct it87_data *ret = data; 880 int err; 881 int i; 882 883 mutex_lock(&data->update_lock); 884 885 if (time_after(jiffies, data->last_updated + HZ + HZ / 2) || 886 !data->valid) { 887 err = smbus_disable(data); 888 if (err) { 889 ret = ERR_PTR(err); 890 goto unlock; 891 } 892 if (update_vbat) { 893 /* 894 * Cleared after each update, so reenable. Value 895 * returned by this read will be previous value 896 */ 897 it87_write_value(data, IT87_REG_CONFIG, 898 it87_read_value(data, IT87_REG_CONFIG) | 0x40); 899 } 900 for (i = 0; i < NUM_VIN; i++) { 901 if (!(data->has_in & BIT(i))) 902 continue; 903 904 data->in[i][0] = 905 it87_read_value(data, IT87_REG_VIN[i]); 906 907 /* VBAT and AVCC don't have limit registers */ 908 if (i >= NUM_VIN_LIMIT) 909 continue; 910 911 data->in[i][1] = 912 it87_read_value(data, IT87_REG_VIN_MIN(i)); 913 data->in[i][2] = 914 it87_read_value(data, IT87_REG_VIN_MAX(i)); 915 } 916 917 for (i = 0; i < NUM_FAN; i++) { 918 /* Skip disabled fans */ 919 if (!(data->has_fan & BIT(i))) 920 continue; 921 922 data->fan[i][1] = 923 it87_read_value(data, IT87_REG_FAN_MIN[i]); 924 data->fan[i][0] = it87_read_value(data, 925 IT87_REG_FAN[i]); 926 /* Add high byte if in 16-bit mode */ 927 if (has_16bit_fans(data)) { 928 data->fan[i][0] |= it87_read_value(data, 929 IT87_REG_FANX[i]) << 8; 930 data->fan[i][1] |= it87_read_value(data, 931 IT87_REG_FANX_MIN[i]) << 8; 932 } 933 } 934 for (i = 0; i < NUM_TEMP; i++) { 935 if (!(data->has_temp & BIT(i))) 936 continue; 937 data->temp[i][0] = 938 it87_read_value(data, IT87_REG_TEMP(i)); 939 940 if (has_temp_offset(data) && i < NUM_TEMP_OFFSET) 941 data->temp[i][3] = 942 it87_read_value(data, 943 IT87_REG_TEMP_OFFSET[i]); 944 945 if (i >= NUM_TEMP_LIMIT) 946 continue; 947 948 data->temp[i][1] = 949 it87_read_value(data, IT87_REG_TEMP_LOW(i)); 950 data->temp[i][2] = 951 it87_read_value(data, IT87_REG_TEMP_HIGH(i)); 952 } 953 954 /* Newer chips don't have clock dividers */ 955 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) { 956 i = it87_read_value(data, IT87_REG_FAN_DIV); 957 data->fan_div[0] = i & 0x07; 958 data->fan_div[1] = (i >> 3) & 0x07; 959 data->fan_div[2] = (i & 0x40) ? 3 : 1; 960 } 961 962 data->alarms = 963 it87_read_value(data, IT87_REG_ALARM1) | 964 (it87_read_value(data, IT87_REG_ALARM2) << 8) | 965 (it87_read_value(data, IT87_REG_ALARM3) << 16); 966 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE); 967 968 data->fan_main_ctrl = it87_read_value(data, 969 IT87_REG_FAN_MAIN_CTRL); 970 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL); 971 for (i = 0; i < NUM_PWM; i++) { 972 if (!(data->has_pwm & BIT(i))) 973 continue; 974 it87_update_pwm_ctrl(data, i); 975 } 976 977 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE); 978 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); 979 /* 980 * The IT8705F does not have VID capability. 981 * The IT8718F and later don't use IT87_REG_VID for the 982 * same purpose. 983 */ 984 if (data->type == it8712 || data->type == it8716) { 985 data->vid = it87_read_value(data, IT87_REG_VID); 986 /* 987 * The older IT8712F revisions had only 5 VID pins, 988 * but we assume it is always safe to read 6 bits. 989 */ 990 data->vid &= 0x3f; 991 } 992 data->last_updated = jiffies; 993 data->valid = true; 994 smbus_enable(data); 995 } 996 unlock: 997 mutex_unlock(&data->update_lock); 998 return ret; 999 } 1000 1001 static ssize_t show_in(struct device *dev, struct device_attribute *attr, 1002 char *buf) 1003 { 1004 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1005 struct it87_data *data = it87_update_device(dev); 1006 int index = sattr->index; 1007 int nr = sattr->nr; 1008 1009 if (IS_ERR(data)) 1010 return PTR_ERR(data); 1011 1012 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index])); 1013 } 1014 1015 static ssize_t set_in(struct device *dev, struct device_attribute *attr, 1016 const char *buf, size_t count) 1017 { 1018 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1019 struct it87_data *data = dev_get_drvdata(dev); 1020 int index = sattr->index; 1021 int nr = sattr->nr; 1022 unsigned long val; 1023 int err; 1024 1025 if (kstrtoul(buf, 10, &val) < 0) 1026 return -EINVAL; 1027 1028 err = it87_lock(data); 1029 if (err) 1030 return err; 1031 1032 data->in[nr][index] = in_to_reg(data, nr, val); 1033 it87_write_value(data, 1034 index == 1 ? IT87_REG_VIN_MIN(nr) 1035 : IT87_REG_VIN_MAX(nr), 1036 data->in[nr][index]); 1037 it87_unlock(data); 1038 return count; 1039 } 1040 1041 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0); 1042 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in, 1043 0, 1); 1044 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in, 1045 0, 2); 1046 1047 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0); 1048 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in, 1049 1, 1); 1050 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in, 1051 1, 2); 1052 1053 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0); 1054 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in, 1055 2, 1); 1056 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in, 1057 2, 2); 1058 1059 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0); 1060 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in, 1061 3, 1); 1062 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in, 1063 3, 2); 1064 1065 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0); 1066 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in, 1067 4, 1); 1068 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in, 1069 4, 2); 1070 1071 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0); 1072 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in, 1073 5, 1); 1074 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in, 1075 5, 2); 1076 1077 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0); 1078 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in, 1079 6, 1); 1080 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in, 1081 6, 2); 1082 1083 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0); 1084 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in, 1085 7, 1); 1086 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in, 1087 7, 2); 1088 1089 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0); 1090 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0); 1091 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0); 1092 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0); 1093 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0); 1094 1095 /* Up to 6 temperatures */ 1096 static ssize_t show_temp(struct device *dev, struct device_attribute *attr, 1097 char *buf) 1098 { 1099 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1100 int nr = sattr->nr; 1101 int index = sattr->index; 1102 struct it87_data *data = it87_update_device(dev); 1103 1104 if (IS_ERR(data)) 1105 return PTR_ERR(data); 1106 1107 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index])); 1108 } 1109 1110 static ssize_t set_temp(struct device *dev, struct device_attribute *attr, 1111 const char *buf, size_t count) 1112 { 1113 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1114 int nr = sattr->nr; 1115 int index = sattr->index; 1116 struct it87_data *data = dev_get_drvdata(dev); 1117 long val; 1118 u8 reg, regval; 1119 int err; 1120 1121 if (kstrtol(buf, 10, &val) < 0) 1122 return -EINVAL; 1123 1124 err = it87_lock(data); 1125 if (err) 1126 return err; 1127 1128 switch (index) { 1129 default: 1130 case 1: 1131 reg = IT87_REG_TEMP_LOW(nr); 1132 break; 1133 case 2: 1134 reg = IT87_REG_TEMP_HIGH(nr); 1135 break; 1136 case 3: 1137 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE); 1138 if (!(regval & 0x80)) { 1139 regval |= 0x80; 1140 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval); 1141 } 1142 data->valid = false; 1143 reg = IT87_REG_TEMP_OFFSET[nr]; 1144 break; 1145 } 1146 1147 data->temp[nr][index] = TEMP_TO_REG(val); 1148 it87_write_value(data, reg, data->temp[nr][index]); 1149 it87_unlock(data); 1150 return count; 1151 } 1152 1153 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0); 1154 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp, 1155 0, 1); 1156 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp, 1157 0, 2); 1158 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp, 1159 set_temp, 0, 3); 1160 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0); 1161 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp, 1162 1, 1); 1163 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp, 1164 1, 2); 1165 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp, 1166 set_temp, 1, 3); 1167 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0); 1168 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp, 1169 2, 1); 1170 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp, 1171 2, 2); 1172 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp, 1173 set_temp, 2, 3); 1174 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0); 1175 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0); 1176 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0); 1177 1178 static int get_temp_type(struct it87_data *data, int index) 1179 { 1180 /* 1181 * 2 is deprecated; 1182 * 3 = thermal diode; 1183 * 4 = thermistor; 1184 * 5 = AMDTSI; 1185 * 6 = Intel PECI; 1186 * 0 = disabled 1187 */ 1188 u8 reg, extra; 1189 int ttype, type = 0; 1190 1191 /* Detect PECI vs. AMDTSI */ 1192 ttype = 6; 1193 if ((has_temp_peci(data, index)) || data->type == it8721 || 1194 data->type == it8720) { 1195 extra = it87_read_value(data, IT87_REG_IFSEL); 1196 if ((extra & 0x70) == 0x40) 1197 ttype = 5; 1198 } 1199 1200 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE); 1201 1202 /* Per chip special detection */ 1203 switch (data->type) { 1204 case it8622: 1205 if (!(reg & 0xc0) && index == 3) 1206 type = ttype; 1207 break; 1208 default: 1209 break; 1210 } 1211 1212 if (type || index >= 3) 1213 return type; 1214 1215 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); 1216 1217 if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) || 1218 (has_temp_old_peci(data, index) && (extra & 0x80))) 1219 type = ttype; /* Intel PECI or AMDTSI */ 1220 else if (reg & BIT(index)) 1221 type = 3; /* thermal diode */ 1222 else if (reg & BIT(index + 3)) 1223 type = 4; /* thermistor */ 1224 1225 return type; 1226 } 1227 1228 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr, 1229 char *buf) 1230 { 1231 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1232 struct it87_data *data = it87_update_device(dev); 1233 1234 if (IS_ERR(data)) 1235 return PTR_ERR(data); 1236 1237 return sprintf(buf, "%d\n", get_temp_type(data, sensor_attr->index)); 1238 } 1239 1240 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr, 1241 const char *buf, size_t count) 1242 { 1243 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1244 int nr = sensor_attr->index; 1245 1246 struct it87_data *data = dev_get_drvdata(dev); 1247 long val; 1248 u8 reg, extra; 1249 int err; 1250 1251 if (kstrtol(buf, 10, &val) < 0) 1252 return -EINVAL; 1253 1254 err = it87_lock(data); 1255 if (err) 1256 return err; 1257 1258 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE); 1259 reg &= ~(1 << nr); 1260 reg &= ~(8 << nr); 1261 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6)) 1262 reg &= 0x3f; 1263 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA); 1264 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6)) 1265 extra &= 0x7f; 1266 if (val == 2) { /* backwards compatibility */ 1267 dev_warn(dev, 1268 "Sensor type 2 is deprecated, please use 4 instead\n"); 1269 val = 4; 1270 } 1271 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */ 1272 if (val == 3) 1273 reg |= 1 << nr; 1274 else if (val == 4) 1275 reg |= 8 << nr; 1276 else if (has_temp_peci(data, nr) && val == 6) 1277 reg |= (nr + 1) << 6; 1278 else if (has_temp_old_peci(data, nr) && val == 6) 1279 extra |= 0x80; 1280 else if (val != 0) { 1281 count = -EINVAL; 1282 goto unlock; 1283 } 1284 1285 data->sensor = reg; 1286 data->extra = extra; 1287 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor); 1288 if (has_temp_old_peci(data, nr)) 1289 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra); 1290 data->valid = false; /* Force cache refresh */ 1291 unlock: 1292 it87_unlock(data); 1293 return count; 1294 } 1295 1296 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type, 1297 set_temp_type, 0); 1298 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type, 1299 set_temp_type, 1); 1300 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type, 1301 set_temp_type, 2); 1302 1303 /* 6 Fans */ 1304 1305 static int pwm_mode(const struct it87_data *data, int nr) 1306 { 1307 if (has_fanctl_onoff(data) && nr < 3 && 1308 !(data->fan_main_ctrl & BIT(nr))) 1309 return 0; /* Full speed */ 1310 if (data->pwm_ctrl[nr] & 0x80) 1311 return 2; /* Automatic mode */ 1312 if ((!has_fanctl_onoff(data) || nr >= 3) && 1313 data->pwm_duty[nr] == pwm_to_reg(data, 0xff)) 1314 return 0; /* Full speed */ 1315 1316 return 1; /* Manual mode */ 1317 } 1318 1319 static ssize_t show_fan(struct device *dev, struct device_attribute *attr, 1320 char *buf) 1321 { 1322 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1323 int nr = sattr->nr; 1324 int index = sattr->index; 1325 int speed; 1326 struct it87_data *data = it87_update_device(dev); 1327 1328 if (IS_ERR(data)) 1329 return PTR_ERR(data); 1330 1331 speed = has_16bit_fans(data) ? 1332 FAN16_FROM_REG(data->fan[nr][index]) : 1333 FAN_FROM_REG(data->fan[nr][index], 1334 DIV_FROM_REG(data->fan_div[nr])); 1335 return sprintf(buf, "%d\n", speed); 1336 } 1337 1338 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr, 1339 char *buf) 1340 { 1341 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1342 struct it87_data *data = it87_update_device(dev); 1343 int nr = sensor_attr->index; 1344 1345 if (IS_ERR(data)) 1346 return PTR_ERR(data); 1347 1348 return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr])); 1349 } 1350 1351 static ssize_t show_pwm_enable(struct device *dev, 1352 struct device_attribute *attr, char *buf) 1353 { 1354 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1355 struct it87_data *data = it87_update_device(dev); 1356 int nr = sensor_attr->index; 1357 1358 if (IS_ERR(data)) 1359 return PTR_ERR(data); 1360 1361 return sprintf(buf, "%d\n", pwm_mode(data, nr)); 1362 } 1363 1364 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr, 1365 char *buf) 1366 { 1367 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1368 struct it87_data *data = it87_update_device(dev); 1369 int nr = sensor_attr->index; 1370 1371 if (IS_ERR(data)) 1372 return PTR_ERR(data); 1373 1374 return sprintf(buf, "%d\n", 1375 pwm_from_reg(data, data->pwm_duty[nr])); 1376 } 1377 1378 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr, 1379 char *buf) 1380 { 1381 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1382 struct it87_data *data = it87_update_device(dev); 1383 int nr = sensor_attr->index; 1384 unsigned int freq; 1385 int index; 1386 1387 if (IS_ERR(data)) 1388 return PTR_ERR(data); 1389 1390 if (has_pwm_freq2(data) && nr == 1) 1391 index = (data->extra >> 4) & 0x07; 1392 else 1393 index = (data->fan_ctl >> 4) & 0x07; 1394 1395 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128); 1396 1397 return sprintf(buf, "%u\n", freq); 1398 } 1399 1400 static ssize_t set_fan(struct device *dev, struct device_attribute *attr, 1401 const char *buf, size_t count) 1402 { 1403 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); 1404 int nr = sattr->nr; 1405 int index = sattr->index; 1406 1407 struct it87_data *data = dev_get_drvdata(dev); 1408 long val; 1409 int err; 1410 u8 reg; 1411 1412 if (kstrtol(buf, 10, &val) < 0) 1413 return -EINVAL; 1414 1415 err = it87_lock(data); 1416 if (err) 1417 return err; 1418 1419 if (has_16bit_fans(data)) { 1420 data->fan[nr][index] = FAN16_TO_REG(val); 1421 it87_write_value(data, IT87_REG_FAN_MIN[nr], 1422 data->fan[nr][index] & 0xff); 1423 it87_write_value(data, IT87_REG_FANX_MIN[nr], 1424 data->fan[nr][index] >> 8); 1425 } else { 1426 reg = it87_read_value(data, IT87_REG_FAN_DIV); 1427 switch (nr) { 1428 case 0: 1429 data->fan_div[nr] = reg & 0x07; 1430 break; 1431 case 1: 1432 data->fan_div[nr] = (reg >> 3) & 0x07; 1433 break; 1434 case 2: 1435 data->fan_div[nr] = (reg & 0x40) ? 3 : 1; 1436 break; 1437 } 1438 data->fan[nr][index] = 1439 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr])); 1440 it87_write_value(data, IT87_REG_FAN_MIN[nr], 1441 data->fan[nr][index]); 1442 } 1443 1444 it87_unlock(data); 1445 return count; 1446 } 1447 1448 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr, 1449 const char *buf, size_t count) 1450 { 1451 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1452 struct it87_data *data = dev_get_drvdata(dev); 1453 int nr = sensor_attr->index; 1454 unsigned long val; 1455 int min, err; 1456 u8 old; 1457 1458 if (kstrtoul(buf, 10, &val) < 0) 1459 return -EINVAL; 1460 1461 err = it87_lock(data); 1462 if (err) 1463 return err; 1464 1465 old = it87_read_value(data, IT87_REG_FAN_DIV); 1466 1467 /* Save fan min limit */ 1468 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr])); 1469 1470 switch (nr) { 1471 case 0: 1472 case 1: 1473 data->fan_div[nr] = DIV_TO_REG(val); 1474 break; 1475 case 2: 1476 if (val < 8) 1477 data->fan_div[nr] = 1; 1478 else 1479 data->fan_div[nr] = 3; 1480 } 1481 val = old & 0x80; 1482 val |= (data->fan_div[0] & 0x07); 1483 val |= (data->fan_div[1] & 0x07) << 3; 1484 if (data->fan_div[2] == 3) 1485 val |= 0x1 << 6; 1486 it87_write_value(data, IT87_REG_FAN_DIV, val); 1487 1488 /* Restore fan min limit */ 1489 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr])); 1490 it87_write_value(data, IT87_REG_FAN_MIN[nr], data->fan[nr][1]); 1491 1492 it87_unlock(data); 1493 return count; 1494 } 1495 1496 /* Returns 0 if OK, -EINVAL otherwise */ 1497 static int check_trip_points(struct device *dev, int nr) 1498 { 1499 const struct it87_data *data = dev_get_drvdata(dev); 1500 int i, err = 0; 1501 1502 if (has_old_autopwm(data)) { 1503 for (i = 0; i < 3; i++) { 1504 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1]) 1505 err = -EINVAL; 1506 } 1507 for (i = 0; i < 2; i++) { 1508 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1]) 1509 err = -EINVAL; 1510 } 1511 } else if (has_newer_autopwm(data)) { 1512 for (i = 1; i < 3; i++) { 1513 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1]) 1514 err = -EINVAL; 1515 } 1516 } 1517 1518 if (err) { 1519 dev_err(dev, 1520 "Inconsistent trip points, not switching to automatic mode\n"); 1521 dev_err(dev, "Adjust the trip points and try again\n"); 1522 } 1523 return err; 1524 } 1525 1526 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr, 1527 const char *buf, size_t count) 1528 { 1529 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1530 struct it87_data *data = dev_get_drvdata(dev); 1531 int nr = sensor_attr->index; 1532 long val; 1533 int err; 1534 1535 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2) 1536 return -EINVAL; 1537 1538 /* Check trip points before switching to automatic mode */ 1539 if (val == 2) { 1540 if (check_trip_points(dev, nr) < 0) 1541 return -EINVAL; 1542 } 1543 1544 err = it87_lock(data); 1545 if (err) 1546 return err; 1547 1548 if (val == 0) { 1549 if (nr < 3 && has_fanctl_onoff(data)) { 1550 int tmp; 1551 /* make sure the fan is on when in on/off mode */ 1552 tmp = it87_read_value(data, IT87_REG_FAN_CTL); 1553 it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr)); 1554 /* set on/off mode */ 1555 data->fan_main_ctrl &= ~BIT(nr); 1556 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, 1557 data->fan_main_ctrl); 1558 } else { 1559 u8 ctrl; 1560 1561 /* No on/off mode, set maximum pwm value */ 1562 data->pwm_duty[nr] = pwm_to_reg(data, 0xff); 1563 it87_write_value(data, IT87_REG_PWM_DUTY[nr], 1564 data->pwm_duty[nr]); 1565 /* and set manual mode */ 1566 if (has_newer_autopwm(data)) { 1567 ctrl = (data->pwm_ctrl[nr] & 0x7c) | 1568 data->pwm_temp_map[nr]; 1569 } else { 1570 ctrl = data->pwm_duty[nr]; 1571 } 1572 data->pwm_ctrl[nr] = ctrl; 1573 it87_write_value(data, IT87_REG_PWM[nr], ctrl); 1574 } 1575 } else { 1576 u8 ctrl; 1577 1578 if (has_newer_autopwm(data)) { 1579 ctrl = (data->pwm_ctrl[nr] & 0x7c) | 1580 data->pwm_temp_map[nr]; 1581 if (val != 1) 1582 ctrl |= 0x80; 1583 } else { 1584 ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80); 1585 } 1586 data->pwm_ctrl[nr] = ctrl; 1587 it87_write_value(data, IT87_REG_PWM[nr], ctrl); 1588 1589 if (has_fanctl_onoff(data) && nr < 3) { 1590 /* set SmartGuardian mode */ 1591 data->fan_main_ctrl |= BIT(nr); 1592 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, 1593 data->fan_main_ctrl); 1594 } 1595 } 1596 1597 it87_unlock(data); 1598 return count; 1599 } 1600 1601 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, 1602 const char *buf, size_t count) 1603 { 1604 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1605 struct it87_data *data = dev_get_drvdata(dev); 1606 int nr = sensor_attr->index; 1607 long val; 1608 int err; 1609 1610 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255) 1611 return -EINVAL; 1612 1613 err = it87_lock(data); 1614 if (err) 1615 return err; 1616 1617 it87_update_pwm_ctrl(data, nr); 1618 if (has_newer_autopwm(data)) { 1619 /* 1620 * If we are in automatic mode, the PWM duty cycle register 1621 * is read-only so we can't write the value. 1622 */ 1623 if (data->pwm_ctrl[nr] & 0x80) { 1624 count = -EBUSY; 1625 goto unlock; 1626 } 1627 data->pwm_duty[nr] = pwm_to_reg(data, val); 1628 it87_write_value(data, IT87_REG_PWM_DUTY[nr], 1629 data->pwm_duty[nr]); 1630 } else { 1631 data->pwm_duty[nr] = pwm_to_reg(data, val); 1632 /* 1633 * If we are in manual mode, write the duty cycle immediately; 1634 * otherwise, just store it for later use. 1635 */ 1636 if (!(data->pwm_ctrl[nr] & 0x80)) { 1637 data->pwm_ctrl[nr] = data->pwm_duty[nr]; 1638 it87_write_value(data, IT87_REG_PWM[nr], 1639 data->pwm_ctrl[nr]); 1640 } 1641 } 1642 unlock: 1643 it87_unlock(data); 1644 return count; 1645 } 1646 1647 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr, 1648 const char *buf, size_t count) 1649 { 1650 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1651 struct it87_data *data = dev_get_drvdata(dev); 1652 int nr = sensor_attr->index; 1653 unsigned long val; 1654 int err; 1655 int i; 1656 1657 if (kstrtoul(buf, 10, &val) < 0) 1658 return -EINVAL; 1659 1660 val = clamp_val(val, 0, 1000000); 1661 val *= has_newer_autopwm(data) ? 256 : 128; 1662 1663 /* Search for the nearest available frequency */ 1664 for (i = 0; i < 7; i++) { 1665 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2) 1666 break; 1667 } 1668 1669 err = it87_lock(data); 1670 if (err) 1671 return err; 1672 1673 if (nr == 0) { 1674 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f; 1675 data->fan_ctl |= i << 4; 1676 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl); 1677 } else { 1678 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f; 1679 data->extra |= i << 4; 1680 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra); 1681 } 1682 it87_unlock(data); 1683 1684 return count; 1685 } 1686 1687 static ssize_t show_pwm_temp_map(struct device *dev, 1688 struct device_attribute *attr, char *buf) 1689 { 1690 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1691 struct it87_data *data = it87_update_device(dev); 1692 int nr = sensor_attr->index; 1693 int map; 1694 1695 if (IS_ERR(data)) 1696 return PTR_ERR(data); 1697 1698 map = data->pwm_temp_map[nr]; 1699 if (map >= 3) 1700 map = 0; /* Should never happen */ 1701 if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */ 1702 map += 3; 1703 1704 return sprintf(buf, "%d\n", (int)BIT(map)); 1705 } 1706 1707 static ssize_t set_pwm_temp_map(struct device *dev, 1708 struct device_attribute *attr, const char *buf, 1709 size_t count) 1710 { 1711 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1712 struct it87_data *data = dev_get_drvdata(dev); 1713 int nr = sensor_attr->index; 1714 long val; 1715 int err; 1716 u8 reg; 1717 1718 if (kstrtol(buf, 10, &val) < 0) 1719 return -EINVAL; 1720 1721 if (nr >= 3) 1722 val -= 3; 1723 1724 switch (val) { 1725 case BIT(0): 1726 reg = 0x00; 1727 break; 1728 case BIT(1): 1729 reg = 0x01; 1730 break; 1731 case BIT(2): 1732 reg = 0x02; 1733 break; 1734 default: 1735 return -EINVAL; 1736 } 1737 1738 err = it87_lock(data); 1739 if (err) 1740 return err; 1741 1742 it87_update_pwm_ctrl(data, nr); 1743 data->pwm_temp_map[nr] = reg; 1744 /* 1745 * If we are in automatic mode, write the temp mapping immediately; 1746 * otherwise, just store it for later use. 1747 */ 1748 if (data->pwm_ctrl[nr] & 0x80) { 1749 data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & 0xfc) | 1750 data->pwm_temp_map[nr]; 1751 it87_write_value(data, IT87_REG_PWM[nr], data->pwm_ctrl[nr]); 1752 } 1753 it87_unlock(data); 1754 return count; 1755 } 1756 1757 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr, 1758 char *buf) 1759 { 1760 struct it87_data *data = it87_update_device(dev); 1761 struct sensor_device_attribute_2 *sensor_attr = 1762 to_sensor_dev_attr_2(attr); 1763 int nr = sensor_attr->nr; 1764 int point = sensor_attr->index; 1765 1766 if (IS_ERR(data)) 1767 return PTR_ERR(data); 1768 1769 return sprintf(buf, "%d\n", 1770 pwm_from_reg(data, data->auto_pwm[nr][point])); 1771 } 1772 1773 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr, 1774 const char *buf, size_t count) 1775 { 1776 struct it87_data *data = dev_get_drvdata(dev); 1777 struct sensor_device_attribute_2 *sensor_attr = 1778 to_sensor_dev_attr_2(attr); 1779 int nr = sensor_attr->nr; 1780 int point = sensor_attr->index; 1781 int regaddr; 1782 long val; 1783 int err; 1784 1785 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255) 1786 return -EINVAL; 1787 1788 err = it87_lock(data); 1789 if (err) 1790 return err; 1791 1792 data->auto_pwm[nr][point] = pwm_to_reg(data, val); 1793 if (has_newer_autopwm(data)) 1794 regaddr = IT87_REG_AUTO_TEMP(nr, 3); 1795 else 1796 regaddr = IT87_REG_AUTO_PWM(nr, point); 1797 it87_write_value(data, regaddr, data->auto_pwm[nr][point]); 1798 it87_unlock(data); 1799 return count; 1800 } 1801 1802 static ssize_t show_auto_pwm_slope(struct device *dev, 1803 struct device_attribute *attr, char *buf) 1804 { 1805 struct it87_data *data = it87_update_device(dev); 1806 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1807 int nr = sensor_attr->index; 1808 1809 if (IS_ERR(data)) 1810 return PTR_ERR(data); 1811 1812 return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f); 1813 } 1814 1815 static ssize_t set_auto_pwm_slope(struct device *dev, 1816 struct device_attribute *attr, 1817 const char *buf, size_t count) 1818 { 1819 struct it87_data *data = dev_get_drvdata(dev); 1820 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr); 1821 int nr = sensor_attr->index; 1822 unsigned long val; 1823 int err; 1824 1825 if (kstrtoul(buf, 10, &val) < 0 || val > 127) 1826 return -EINVAL; 1827 1828 err = it87_lock(data); 1829 if (err) 1830 return err; 1831 1832 data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val; 1833 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4), 1834 data->auto_pwm[nr][1]); 1835 it87_unlock(data); 1836 return count; 1837 } 1838 1839 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr, 1840 char *buf) 1841 { 1842 struct it87_data *data = it87_update_device(dev); 1843 struct sensor_device_attribute_2 *sensor_attr = 1844 to_sensor_dev_attr_2(attr); 1845 int nr = sensor_attr->nr; 1846 int point = sensor_attr->index; 1847 int reg; 1848 1849 if (IS_ERR(data)) 1850 return PTR_ERR(data); 1851 1852 if (has_old_autopwm(data) || point) 1853 reg = data->auto_temp[nr][point]; 1854 else 1855 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f); 1856 1857 return sprintf(buf, "%d\n", TEMP_FROM_REG(reg)); 1858 } 1859 1860 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr, 1861 const char *buf, size_t count) 1862 { 1863 struct it87_data *data = dev_get_drvdata(dev); 1864 struct sensor_device_attribute_2 *sensor_attr = 1865 to_sensor_dev_attr_2(attr); 1866 int nr = sensor_attr->nr; 1867 int point = sensor_attr->index; 1868 long val; 1869 int reg; 1870 int err; 1871 1872 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000) 1873 return -EINVAL; 1874 1875 err = it87_lock(data); 1876 if (err) 1877 return err; 1878 1879 if (has_newer_autopwm(data) && !point) { 1880 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val); 1881 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0); 1882 data->auto_temp[nr][0] = reg; 1883 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg); 1884 } else { 1885 reg = TEMP_TO_REG(val); 1886 data->auto_temp[nr][point] = reg; 1887 if (has_newer_autopwm(data)) 1888 point--; 1889 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg); 1890 } 1891 it87_unlock(data); 1892 return count; 1893 } 1894 1895 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0); 1896 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1897 0, 1); 1898 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div, 1899 set_fan_div, 0); 1900 1901 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0); 1902 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1903 1, 1); 1904 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div, 1905 set_fan_div, 1); 1906 1907 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0); 1908 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1909 2, 1); 1910 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div, 1911 set_fan_div, 2); 1912 1913 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0); 1914 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1915 3, 1); 1916 1917 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0); 1918 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1919 4, 1); 1920 1921 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0); 1922 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan, 1923 5, 1); 1924 1925 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, 1926 show_pwm_enable, set_pwm_enable, 0); 1927 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0); 1928 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq, 1929 set_pwm_freq, 0); 1930 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO, 1931 show_pwm_temp_map, set_pwm_temp_map, 0); 1932 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR, 1933 show_auto_pwm, set_auto_pwm, 0, 0); 1934 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR, 1935 show_auto_pwm, set_auto_pwm, 0, 1); 1936 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR, 1937 show_auto_pwm, set_auto_pwm, 0, 2); 1938 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO, 1939 show_auto_pwm, NULL, 0, 3); 1940 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR, 1941 show_auto_temp, set_auto_temp, 0, 1); 1942 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1943 show_auto_temp, set_auto_temp, 0, 0); 1944 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR, 1945 show_auto_temp, set_auto_temp, 0, 2); 1946 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR, 1947 show_auto_temp, set_auto_temp, 0, 3); 1948 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR, 1949 show_auto_temp, set_auto_temp, 0, 4); 1950 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR, 1951 show_auto_pwm, set_auto_pwm, 0, 0); 1952 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR, 1953 show_auto_pwm_slope, set_auto_pwm_slope, 0); 1954 1955 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR, 1956 show_pwm_enable, set_pwm_enable, 1); 1957 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1); 1958 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1); 1959 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO, 1960 show_pwm_temp_map, set_pwm_temp_map, 1); 1961 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR, 1962 show_auto_pwm, set_auto_pwm, 1, 0); 1963 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR, 1964 show_auto_pwm, set_auto_pwm, 1, 1); 1965 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR, 1966 show_auto_pwm, set_auto_pwm, 1, 2); 1967 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO, 1968 show_auto_pwm, NULL, 1, 3); 1969 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR, 1970 show_auto_temp, set_auto_temp, 1, 1); 1971 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 1972 show_auto_temp, set_auto_temp, 1, 0); 1973 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR, 1974 show_auto_temp, set_auto_temp, 1, 2); 1975 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR, 1976 show_auto_temp, set_auto_temp, 1, 3); 1977 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR, 1978 show_auto_temp, set_auto_temp, 1, 4); 1979 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR, 1980 show_auto_pwm, set_auto_pwm, 1, 0); 1981 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR, 1982 show_auto_pwm_slope, set_auto_pwm_slope, 1); 1983 1984 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR, 1985 show_pwm_enable, set_pwm_enable, 2); 1986 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2); 1987 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2); 1988 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO, 1989 show_pwm_temp_map, set_pwm_temp_map, 2); 1990 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR, 1991 show_auto_pwm, set_auto_pwm, 2, 0); 1992 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR, 1993 show_auto_pwm, set_auto_pwm, 2, 1); 1994 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR, 1995 show_auto_pwm, set_auto_pwm, 2, 2); 1996 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO, 1997 show_auto_pwm, NULL, 2, 3); 1998 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR, 1999 show_auto_temp, set_auto_temp, 2, 1); 2000 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 2001 show_auto_temp, set_auto_temp, 2, 0); 2002 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR, 2003 show_auto_temp, set_auto_temp, 2, 2); 2004 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR, 2005 show_auto_temp, set_auto_temp, 2, 3); 2006 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR, 2007 show_auto_temp, set_auto_temp, 2, 4); 2008 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR, 2009 show_auto_pwm, set_auto_pwm, 2, 0); 2010 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR, 2011 show_auto_pwm_slope, set_auto_pwm_slope, 2); 2012 2013 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR, 2014 show_pwm_enable, set_pwm_enable, 3); 2015 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3); 2016 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3); 2017 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO, 2018 show_pwm_temp_map, set_pwm_temp_map, 3); 2019 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR, 2020 show_auto_temp, set_auto_temp, 2, 1); 2021 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 2022 show_auto_temp, set_auto_temp, 2, 0); 2023 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR, 2024 show_auto_temp, set_auto_temp, 2, 2); 2025 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR, 2026 show_auto_temp, set_auto_temp, 2, 3); 2027 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR, 2028 show_auto_pwm, set_auto_pwm, 3, 0); 2029 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR, 2030 show_auto_pwm_slope, set_auto_pwm_slope, 3); 2031 2032 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR, 2033 show_pwm_enable, set_pwm_enable, 4); 2034 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4); 2035 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4); 2036 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO, 2037 show_pwm_temp_map, set_pwm_temp_map, 4); 2038 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR, 2039 show_auto_temp, set_auto_temp, 2, 1); 2040 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 2041 show_auto_temp, set_auto_temp, 2, 0); 2042 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR, 2043 show_auto_temp, set_auto_temp, 2, 2); 2044 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR, 2045 show_auto_temp, set_auto_temp, 2, 3); 2046 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR, 2047 show_auto_pwm, set_auto_pwm, 4, 0); 2048 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR, 2049 show_auto_pwm_slope, set_auto_pwm_slope, 4); 2050 2051 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR, 2052 show_pwm_enable, set_pwm_enable, 5); 2053 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5); 2054 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5); 2055 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO, 2056 show_pwm_temp_map, set_pwm_temp_map, 5); 2057 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR, 2058 show_auto_temp, set_auto_temp, 2, 1); 2059 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, 2060 show_auto_temp, set_auto_temp, 2, 0); 2061 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR, 2062 show_auto_temp, set_auto_temp, 2, 2); 2063 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR, 2064 show_auto_temp, set_auto_temp, 2, 3); 2065 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR, 2066 show_auto_pwm, set_auto_pwm, 5, 0); 2067 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR, 2068 show_auto_pwm_slope, set_auto_pwm_slope, 5); 2069 2070 /* Alarms */ 2071 static ssize_t alarms_show(struct device *dev, struct device_attribute *attr, 2072 char *buf) 2073 { 2074 struct it87_data *data = it87_update_device(dev); 2075 2076 if (IS_ERR(data)) 2077 return PTR_ERR(data); 2078 2079 return sprintf(buf, "%u\n", data->alarms); 2080 } 2081 static DEVICE_ATTR_RO(alarms); 2082 2083 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, 2084 char *buf) 2085 { 2086 struct it87_data *data = it87_update_device(dev); 2087 int bitnr = to_sensor_dev_attr(attr)->index; 2088 2089 if (IS_ERR(data)) 2090 return PTR_ERR(data); 2091 2092 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1); 2093 } 2094 2095 static ssize_t clear_intrusion(struct device *dev, 2096 struct device_attribute *attr, const char *buf, 2097 size_t count) 2098 { 2099 struct it87_data *data = dev_get_drvdata(dev); 2100 int err, config; 2101 long val; 2102 2103 if (kstrtol(buf, 10, &val) < 0 || val != 0) 2104 return -EINVAL; 2105 2106 err = it87_lock(data); 2107 if (err) 2108 return err; 2109 2110 config = it87_read_value(data, IT87_REG_CONFIG); 2111 if (config < 0) { 2112 count = config; 2113 } else { 2114 config |= BIT(5); 2115 it87_write_value(data, IT87_REG_CONFIG, config); 2116 /* Invalidate cache to force re-read */ 2117 data->valid = false; 2118 } 2119 it87_unlock(data); 2120 return count; 2121 } 2122 2123 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8); 2124 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9); 2125 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10); 2126 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11); 2127 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12); 2128 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13); 2129 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14); 2130 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15); 2131 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0); 2132 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1); 2133 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2); 2134 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3); 2135 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6); 2136 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7); 2137 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16); 2138 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17); 2139 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18); 2140 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR, 2141 show_alarm, clear_intrusion, 4); 2142 2143 static ssize_t show_beep(struct device *dev, struct device_attribute *attr, 2144 char *buf) 2145 { 2146 struct it87_data *data = it87_update_device(dev); 2147 int bitnr = to_sensor_dev_attr(attr)->index; 2148 2149 if (IS_ERR(data)) 2150 return PTR_ERR(data); 2151 2152 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1); 2153 } 2154 2155 static ssize_t set_beep(struct device *dev, struct device_attribute *attr, 2156 const char *buf, size_t count) 2157 { 2158 int bitnr = to_sensor_dev_attr(attr)->index; 2159 struct it87_data *data = dev_get_drvdata(dev); 2160 long val; 2161 int err; 2162 2163 if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1)) 2164 return -EINVAL; 2165 2166 err = it87_lock(data); 2167 if (err) 2168 return err; 2169 2170 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE); 2171 if (val) 2172 data->beeps |= BIT(bitnr); 2173 else 2174 data->beeps &= ~BIT(bitnr); 2175 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps); 2176 it87_unlock(data); 2177 return count; 2178 } 2179 2180 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR, 2181 show_beep, set_beep, 1); 2182 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1); 2183 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1); 2184 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1); 2185 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1); 2186 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1); 2187 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1); 2188 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1); 2189 /* fanX_beep writability is set later */ 2190 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0); 2191 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0); 2192 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0); 2193 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0); 2194 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0); 2195 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0); 2196 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR, 2197 show_beep, set_beep, 2); 2198 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2); 2199 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2); 2200 2201 static ssize_t vrm_show(struct device *dev, struct device_attribute *attr, 2202 char *buf) 2203 { 2204 struct it87_data *data = dev_get_drvdata(dev); 2205 2206 return sprintf(buf, "%u\n", data->vrm); 2207 } 2208 2209 static ssize_t vrm_store(struct device *dev, struct device_attribute *attr, 2210 const char *buf, size_t count) 2211 { 2212 struct it87_data *data = dev_get_drvdata(dev); 2213 unsigned long val; 2214 2215 if (kstrtoul(buf, 10, &val) < 0) 2216 return -EINVAL; 2217 2218 data->vrm = val; 2219 2220 return count; 2221 } 2222 static DEVICE_ATTR_RW(vrm); 2223 2224 static ssize_t cpu0_vid_show(struct device *dev, 2225 struct device_attribute *attr, char *buf) 2226 { 2227 struct it87_data *data = it87_update_device(dev); 2228 2229 if (IS_ERR(data)) 2230 return PTR_ERR(data); 2231 2232 return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm)); 2233 } 2234 static DEVICE_ATTR_RO(cpu0_vid); 2235 2236 static ssize_t show_label(struct device *dev, struct device_attribute *attr, 2237 char *buf) 2238 { 2239 static const char * const labels[] = { 2240 "+5V", 2241 "5VSB", 2242 "Vbat", 2243 "AVCC", 2244 }; 2245 static const char * const labels_it8721[] = { 2246 "+3.3V", 2247 "3VSB", 2248 "Vbat", 2249 "+3.3V", 2250 }; 2251 struct it87_data *data = dev_get_drvdata(dev); 2252 int nr = to_sensor_dev_attr(attr)->index; 2253 const char *label; 2254 2255 if (has_vin3_5v(data) && nr == 0) 2256 label = labels[0]; 2257 else if (has_scaling(data)) 2258 label = labels_it8721[nr]; 2259 else 2260 label = labels[nr]; 2261 2262 return sprintf(buf, "%s\n", label); 2263 } 2264 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0); 2265 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1); 2266 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2); 2267 /* AVCC3 */ 2268 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3); 2269 2270 static umode_t it87_in_is_visible(struct kobject *kobj, 2271 struct attribute *attr, int index) 2272 { 2273 struct device *dev = kobj_to_dev(kobj); 2274 struct it87_data *data = dev_get_drvdata(dev); 2275 int i = index / 5; /* voltage index */ 2276 int a = index % 5; /* attribute index */ 2277 2278 if (index >= 40) { /* in8 and higher only have input attributes */ 2279 i = index - 40 + 8; 2280 a = 0; 2281 } 2282 2283 if (!(data->has_in & BIT(i))) 2284 return 0; 2285 2286 if (a == 4 && !data->has_beep) 2287 return 0; 2288 2289 return attr->mode; 2290 } 2291 2292 static struct attribute *it87_attributes_in[] = { 2293 &sensor_dev_attr_in0_input.dev_attr.attr, 2294 &sensor_dev_attr_in0_min.dev_attr.attr, 2295 &sensor_dev_attr_in0_max.dev_attr.attr, 2296 &sensor_dev_attr_in0_alarm.dev_attr.attr, 2297 &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */ 2298 2299 &sensor_dev_attr_in1_input.dev_attr.attr, 2300 &sensor_dev_attr_in1_min.dev_attr.attr, 2301 &sensor_dev_attr_in1_max.dev_attr.attr, 2302 &sensor_dev_attr_in1_alarm.dev_attr.attr, 2303 &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */ 2304 2305 &sensor_dev_attr_in2_input.dev_attr.attr, 2306 &sensor_dev_attr_in2_min.dev_attr.attr, 2307 &sensor_dev_attr_in2_max.dev_attr.attr, 2308 &sensor_dev_attr_in2_alarm.dev_attr.attr, 2309 &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */ 2310 2311 &sensor_dev_attr_in3_input.dev_attr.attr, 2312 &sensor_dev_attr_in3_min.dev_attr.attr, 2313 &sensor_dev_attr_in3_max.dev_attr.attr, 2314 &sensor_dev_attr_in3_alarm.dev_attr.attr, 2315 &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */ 2316 2317 &sensor_dev_attr_in4_input.dev_attr.attr, 2318 &sensor_dev_attr_in4_min.dev_attr.attr, 2319 &sensor_dev_attr_in4_max.dev_attr.attr, 2320 &sensor_dev_attr_in4_alarm.dev_attr.attr, 2321 &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */ 2322 2323 &sensor_dev_attr_in5_input.dev_attr.attr, 2324 &sensor_dev_attr_in5_min.dev_attr.attr, 2325 &sensor_dev_attr_in5_max.dev_attr.attr, 2326 &sensor_dev_attr_in5_alarm.dev_attr.attr, 2327 &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */ 2328 2329 &sensor_dev_attr_in6_input.dev_attr.attr, 2330 &sensor_dev_attr_in6_min.dev_attr.attr, 2331 &sensor_dev_attr_in6_max.dev_attr.attr, 2332 &sensor_dev_attr_in6_alarm.dev_attr.attr, 2333 &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */ 2334 2335 &sensor_dev_attr_in7_input.dev_attr.attr, 2336 &sensor_dev_attr_in7_min.dev_attr.attr, 2337 &sensor_dev_attr_in7_max.dev_attr.attr, 2338 &sensor_dev_attr_in7_alarm.dev_attr.attr, 2339 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */ 2340 2341 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */ 2342 &sensor_dev_attr_in9_input.dev_attr.attr, 2343 &sensor_dev_attr_in10_input.dev_attr.attr, 2344 &sensor_dev_attr_in11_input.dev_attr.attr, 2345 &sensor_dev_attr_in12_input.dev_attr.attr, 2346 NULL 2347 }; 2348 2349 static const struct attribute_group it87_group_in = { 2350 .attrs = it87_attributes_in, 2351 .is_visible = it87_in_is_visible, 2352 }; 2353 2354 static umode_t it87_temp_is_visible(struct kobject *kobj, 2355 struct attribute *attr, int index) 2356 { 2357 struct device *dev = kobj_to_dev(kobj); 2358 struct it87_data *data = dev_get_drvdata(dev); 2359 int i = index / 7; /* temperature index */ 2360 int a = index % 7; /* attribute index */ 2361 2362 if (index >= 21) { 2363 i = index - 21 + 3; 2364 a = 0; 2365 } 2366 2367 if (!(data->has_temp & BIT(i))) 2368 return 0; 2369 2370 if (a == 3) { 2371 if (get_temp_type(data, i) == 0) 2372 return 0; 2373 return attr->mode; 2374 } 2375 2376 if (a == 5 && !has_temp_offset(data)) 2377 return 0; 2378 2379 if (a == 6 && !data->has_beep) 2380 return 0; 2381 2382 return attr->mode; 2383 } 2384 2385 static struct attribute *it87_attributes_temp[] = { 2386 &sensor_dev_attr_temp1_input.dev_attr.attr, 2387 &sensor_dev_attr_temp1_max.dev_attr.attr, 2388 &sensor_dev_attr_temp1_min.dev_attr.attr, 2389 &sensor_dev_attr_temp1_type.dev_attr.attr, 2390 &sensor_dev_attr_temp1_alarm.dev_attr.attr, 2391 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */ 2392 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */ 2393 2394 &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */ 2395 &sensor_dev_attr_temp2_max.dev_attr.attr, 2396 &sensor_dev_attr_temp2_min.dev_attr.attr, 2397 &sensor_dev_attr_temp2_type.dev_attr.attr, 2398 &sensor_dev_attr_temp2_alarm.dev_attr.attr, 2399 &sensor_dev_attr_temp2_offset.dev_attr.attr, 2400 &sensor_dev_attr_temp2_beep.dev_attr.attr, 2401 2402 &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */ 2403 &sensor_dev_attr_temp3_max.dev_attr.attr, 2404 &sensor_dev_attr_temp3_min.dev_attr.attr, 2405 &sensor_dev_attr_temp3_type.dev_attr.attr, 2406 &sensor_dev_attr_temp3_alarm.dev_attr.attr, 2407 &sensor_dev_attr_temp3_offset.dev_attr.attr, 2408 &sensor_dev_attr_temp3_beep.dev_attr.attr, 2409 2410 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */ 2411 &sensor_dev_attr_temp5_input.dev_attr.attr, 2412 &sensor_dev_attr_temp6_input.dev_attr.attr, 2413 NULL 2414 }; 2415 2416 static const struct attribute_group it87_group_temp = { 2417 .attrs = it87_attributes_temp, 2418 .is_visible = it87_temp_is_visible, 2419 }; 2420 2421 static umode_t it87_is_visible(struct kobject *kobj, 2422 struct attribute *attr, int index) 2423 { 2424 struct device *dev = kobj_to_dev(kobj); 2425 struct it87_data *data = dev_get_drvdata(dev); 2426 2427 if ((index == 2 || index == 3) && !data->has_vid) 2428 return 0; 2429 2430 if (index > 3 && !(data->in_internal & BIT(index - 4))) 2431 return 0; 2432 2433 return attr->mode; 2434 } 2435 2436 static struct attribute *it87_attributes[] = { 2437 &dev_attr_alarms.attr, 2438 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr, 2439 &dev_attr_vrm.attr, /* 2 */ 2440 &dev_attr_cpu0_vid.attr, /* 3 */ 2441 &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */ 2442 &sensor_dev_attr_in7_label.dev_attr.attr, 2443 &sensor_dev_attr_in8_label.dev_attr.attr, 2444 &sensor_dev_attr_in9_label.dev_attr.attr, 2445 NULL 2446 }; 2447 2448 static const struct attribute_group it87_group = { 2449 .attrs = it87_attributes, 2450 .is_visible = it87_is_visible, 2451 }; 2452 2453 static umode_t it87_fan_is_visible(struct kobject *kobj, 2454 struct attribute *attr, int index) 2455 { 2456 struct device *dev = kobj_to_dev(kobj); 2457 struct it87_data *data = dev_get_drvdata(dev); 2458 int i = index / 5; /* fan index */ 2459 int a = index % 5; /* attribute index */ 2460 2461 if (index >= 15) { /* fan 4..6 don't have divisor attributes */ 2462 i = (index - 15) / 4 + 3; 2463 a = (index - 15) % 4; 2464 } 2465 2466 if (!(data->has_fan & BIT(i))) 2467 return 0; 2468 2469 if (a == 3) { /* beep */ 2470 if (!data->has_beep) 2471 return 0; 2472 /* first fan beep attribute is writable */ 2473 if (i == __ffs(data->has_fan)) 2474 return attr->mode | S_IWUSR; 2475 } 2476 2477 if (a == 4 && has_16bit_fans(data)) /* divisor */ 2478 return 0; 2479 2480 return attr->mode; 2481 } 2482 2483 static struct attribute *it87_attributes_fan[] = { 2484 &sensor_dev_attr_fan1_input.dev_attr.attr, 2485 &sensor_dev_attr_fan1_min.dev_attr.attr, 2486 &sensor_dev_attr_fan1_alarm.dev_attr.attr, 2487 &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */ 2488 &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */ 2489 2490 &sensor_dev_attr_fan2_input.dev_attr.attr, 2491 &sensor_dev_attr_fan2_min.dev_attr.attr, 2492 &sensor_dev_attr_fan2_alarm.dev_attr.attr, 2493 &sensor_dev_attr_fan2_beep.dev_attr.attr, 2494 &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */ 2495 2496 &sensor_dev_attr_fan3_input.dev_attr.attr, 2497 &sensor_dev_attr_fan3_min.dev_attr.attr, 2498 &sensor_dev_attr_fan3_alarm.dev_attr.attr, 2499 &sensor_dev_attr_fan3_beep.dev_attr.attr, 2500 &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */ 2501 2502 &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */ 2503 &sensor_dev_attr_fan4_min.dev_attr.attr, 2504 &sensor_dev_attr_fan4_alarm.dev_attr.attr, 2505 &sensor_dev_attr_fan4_beep.dev_attr.attr, 2506 2507 &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */ 2508 &sensor_dev_attr_fan5_min.dev_attr.attr, 2509 &sensor_dev_attr_fan5_alarm.dev_attr.attr, 2510 &sensor_dev_attr_fan5_beep.dev_attr.attr, 2511 2512 &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */ 2513 &sensor_dev_attr_fan6_min.dev_attr.attr, 2514 &sensor_dev_attr_fan6_alarm.dev_attr.attr, 2515 &sensor_dev_attr_fan6_beep.dev_attr.attr, 2516 NULL 2517 }; 2518 2519 static const struct attribute_group it87_group_fan = { 2520 .attrs = it87_attributes_fan, 2521 .is_visible = it87_fan_is_visible, 2522 }; 2523 2524 static umode_t it87_pwm_is_visible(struct kobject *kobj, 2525 struct attribute *attr, int index) 2526 { 2527 struct device *dev = kobj_to_dev(kobj); 2528 struct it87_data *data = dev_get_drvdata(dev); 2529 int i = index / 4; /* pwm index */ 2530 int a = index % 4; /* attribute index */ 2531 2532 if (!(data->has_pwm & BIT(i))) 2533 return 0; 2534 2535 /* pwmX_auto_channels_temp is only writable if auto pwm is supported */ 2536 if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data))) 2537 return attr->mode | S_IWUSR; 2538 2539 /* pwm2_freq is writable if there are two pwm frequency selects */ 2540 if (has_pwm_freq2(data) && i == 1 && a == 2) 2541 return attr->mode | S_IWUSR; 2542 2543 return attr->mode; 2544 } 2545 2546 static struct attribute *it87_attributes_pwm[] = { 2547 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 2548 &sensor_dev_attr_pwm1.dev_attr.attr, 2549 &sensor_dev_attr_pwm1_freq.dev_attr.attr, 2550 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr, 2551 2552 &sensor_dev_attr_pwm2_enable.dev_attr.attr, 2553 &sensor_dev_attr_pwm2.dev_attr.attr, 2554 &sensor_dev_attr_pwm2_freq.dev_attr.attr, 2555 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr, 2556 2557 &sensor_dev_attr_pwm3_enable.dev_attr.attr, 2558 &sensor_dev_attr_pwm3.dev_attr.attr, 2559 &sensor_dev_attr_pwm3_freq.dev_attr.attr, 2560 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr, 2561 2562 &sensor_dev_attr_pwm4_enable.dev_attr.attr, 2563 &sensor_dev_attr_pwm4.dev_attr.attr, 2564 &sensor_dev_attr_pwm4_freq.dev_attr.attr, 2565 &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr, 2566 2567 &sensor_dev_attr_pwm5_enable.dev_attr.attr, 2568 &sensor_dev_attr_pwm5.dev_attr.attr, 2569 &sensor_dev_attr_pwm5_freq.dev_attr.attr, 2570 &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr, 2571 2572 &sensor_dev_attr_pwm6_enable.dev_attr.attr, 2573 &sensor_dev_attr_pwm6.dev_attr.attr, 2574 &sensor_dev_attr_pwm6_freq.dev_attr.attr, 2575 &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr, 2576 2577 NULL 2578 }; 2579 2580 static const struct attribute_group it87_group_pwm = { 2581 .attrs = it87_attributes_pwm, 2582 .is_visible = it87_pwm_is_visible, 2583 }; 2584 2585 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj, 2586 struct attribute *attr, int index) 2587 { 2588 struct device *dev = kobj_to_dev(kobj); 2589 struct it87_data *data = dev_get_drvdata(dev); 2590 int i = index / 11; /* pwm index */ 2591 int a = index % 11; /* attribute index */ 2592 2593 if (index >= 33) { /* pwm 4..6 */ 2594 i = (index - 33) / 6 + 3; 2595 a = (index - 33) % 6 + 4; 2596 } 2597 2598 if (!(data->has_pwm & BIT(i))) 2599 return 0; 2600 2601 if (has_newer_autopwm(data)) { 2602 if (a < 4) /* no auto point pwm */ 2603 return 0; 2604 if (a == 8) /* no auto_point4 */ 2605 return 0; 2606 } 2607 if (has_old_autopwm(data)) { 2608 if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */ 2609 return 0; 2610 } 2611 2612 return attr->mode; 2613 } 2614 2615 static struct attribute *it87_attributes_auto_pwm[] = { 2616 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, 2617 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, 2618 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr, 2619 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr, 2620 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr, 2621 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr, 2622 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr, 2623 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr, 2624 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr, 2625 &sensor_dev_attr_pwm1_auto_start.dev_attr.attr, 2626 &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr, 2627 2628 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */ 2629 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, 2630 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr, 2631 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr, 2632 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr, 2633 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr, 2634 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr, 2635 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr, 2636 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr, 2637 &sensor_dev_attr_pwm2_auto_start.dev_attr.attr, 2638 &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr, 2639 2640 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */ 2641 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, 2642 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr, 2643 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr, 2644 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr, 2645 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr, 2646 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr, 2647 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr, 2648 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr, 2649 &sensor_dev_attr_pwm3_auto_start.dev_attr.attr, 2650 &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr, 2651 2652 &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */ 2653 &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr, 2654 &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr, 2655 &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr, 2656 &sensor_dev_attr_pwm4_auto_start.dev_attr.attr, 2657 &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr, 2658 2659 &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr, 2660 &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr, 2661 &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr, 2662 &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr, 2663 &sensor_dev_attr_pwm5_auto_start.dev_attr.attr, 2664 &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr, 2665 2666 &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr, 2667 &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr, 2668 &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr, 2669 &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr, 2670 &sensor_dev_attr_pwm6_auto_start.dev_attr.attr, 2671 &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr, 2672 2673 NULL, 2674 }; 2675 2676 static const struct attribute_group it87_group_auto_pwm = { 2677 .attrs = it87_attributes_auto_pwm, 2678 .is_visible = it87_auto_pwm_is_visible, 2679 }; 2680 2681 /* 2682 * Original explanation: 2683 * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip 2684 * (IT8792E) needs to be in configuration mode before accessing the first 2685 * due to a bug in IT8792E which otherwise results in LPC bus access errors. 2686 * This needs to be done before accessing the first Super-IO chip since 2687 * the second chip may have been accessed prior to loading this driver. 2688 * 2689 * The problem is also reported to affect IT8795E, which is used on X299 boards 2690 * and has the same chip ID as IT8792E (0x8733). It also appears to affect 2691 * systems with IT8790E, which is used on some Z97X-Gaming boards as well as 2692 * Z87X-OC. 2693 * 2694 * From other information supplied: 2695 * ChipIDs 0x8733, 0x8695 (early ID for IT87952E) and 0x8790 are initialized 2696 * and left in configuration mode, and entering and/or exiting configuration 2697 * mode is what causes the crash. 2698 * 2699 * The recommendation is to look up the chipID before doing any mode swap 2700 * and then act accordingly. 2701 */ 2702 /* SuperIO detection - will change isa_address if a chip is found */ 2703 static int __init it87_find(int sioaddr, unsigned short *address, 2704 struct it87_sio_data *sio_data, int chip_cnt) 2705 { 2706 int err; 2707 u16 chip_type; 2708 const struct it87_devices *config = NULL; 2709 bool enabled = false; 2710 2711 /* First step, lock memory but don't enter configuration mode */ 2712 err = superio_enter(sioaddr, true); 2713 if (err) 2714 return err; 2715 2716 err = -ENODEV; 2717 chip_type = superio_inw(sioaddr, DEVID); 2718 /* Check for a valid chip before forcing chip id */ 2719 if (chip_type == 0xffff) { 2720 /* Enter configuration mode */ 2721 __superio_enter(sioaddr); 2722 enabled = true; 2723 /* and then try again */ 2724 chip_type = superio_inw(sioaddr, DEVID); 2725 if (chip_type == 0xffff) 2726 goto exit; 2727 } 2728 2729 if (force_id_cnt == 1) { 2730 /* If only one value given use for all chips */ 2731 if (force_id[0]) 2732 chip_type = force_id[0]; 2733 } else if (force_id[chip_cnt]) 2734 chip_type = force_id[chip_cnt]; 2735 2736 switch (chip_type) { 2737 case IT8705F_DEVID: 2738 sio_data->type = it87; 2739 break; 2740 case IT8712F_DEVID: 2741 sio_data->type = it8712; 2742 break; 2743 case IT8716F_DEVID: 2744 case IT8726F_DEVID: 2745 sio_data->type = it8716; 2746 break; 2747 case IT8718F_DEVID: 2748 sio_data->type = it8718; 2749 break; 2750 case IT8720F_DEVID: 2751 sio_data->type = it8720; 2752 break; 2753 case IT8721F_DEVID: 2754 sio_data->type = it8721; 2755 break; 2756 case IT8728F_DEVID: 2757 sio_data->type = it8728; 2758 break; 2759 case IT8732F_DEVID: 2760 sio_data->type = it8732; 2761 break; 2762 case IT8792E_DEVID: 2763 sio_data->type = it8792; 2764 break; 2765 case IT8771E_DEVID: 2766 sio_data->type = it8771; 2767 break; 2768 case IT8772E_DEVID: 2769 sio_data->type = it8772; 2770 break; 2771 case IT8781F_DEVID: 2772 sio_data->type = it8781; 2773 break; 2774 case IT8782F_DEVID: 2775 sio_data->type = it8782; 2776 break; 2777 case IT8783E_DEVID: 2778 sio_data->type = it8783; 2779 break; 2780 case IT8786E_DEVID: 2781 sio_data->type = it8786; 2782 break; 2783 case IT8790E_DEVID: 2784 sio_data->type = it8790; 2785 break; 2786 case IT8603E_DEVID: 2787 case IT8623E_DEVID: 2788 sio_data->type = it8603; 2789 break; 2790 case IT8620E_DEVID: 2791 sio_data->type = it8620; 2792 break; 2793 case IT8622E_DEVID: 2794 sio_data->type = it8622; 2795 break; 2796 case IT8628E_DEVID: 2797 sio_data->type = it8628; 2798 break; 2799 case IT8689E_DEVID: 2800 sio_data->type = it8689; 2801 break; 2802 case IT87952E_DEVID: 2803 sio_data->type = it87952; 2804 break; 2805 case 0xffff: /* No device at all */ 2806 goto exit; 2807 default: 2808 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type); 2809 goto exit; 2810 } 2811 2812 config = &it87_devices[sio_data->type]; 2813 2814 /* 2815 * If previously we didn't enter configuration mode and it isn't a 2816 * chip we know is initialised in configuration mode, then enter 2817 * configuration mode. 2818 * 2819 * I don't know if any such chips can exist but be defensive. 2820 */ 2821 if (!enabled && !has_noconf(config)) { 2822 __superio_enter(sioaddr); 2823 enabled = true; 2824 } 2825 2826 superio_select(sioaddr, PME); 2827 if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) { 2828 pr_info("Device (chip %s ioreg 0x%x) not activated, skipping\n", 2829 config->model, sioaddr); 2830 goto exit; 2831 } 2832 2833 *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1); 2834 if (*address == 0) { 2835 pr_info("Base address not set (chip %s ioreg 0x%x), skipping\n", 2836 config->model, sioaddr); 2837 goto exit; 2838 } 2839 2840 err = 0; 2841 sio_data->sioaddr = sioaddr; 2842 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f; 2843 pr_info("Found %s chip at 0x%x, revision %d\n", 2844 it87_devices[sio_data->type].model, 2845 *address, sio_data->revision); 2846 2847 /* in7 (VSB or VCCH5V) is always internal on some chips */ 2848 if (has_in7_internal(config)) 2849 sio_data->internal |= BIT(1); 2850 2851 /* in8 (Vbat) is always internal */ 2852 sio_data->internal |= BIT(2); 2853 2854 /* in9 (AVCC3), always internal if supported */ 2855 if (has_avcc3(config)) 2856 sio_data->internal |= BIT(3); /* in9 is AVCC */ 2857 else 2858 sio_data->skip_in |= BIT(9); 2859 2860 if (!has_four_pwm(config)) 2861 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5); 2862 else if (!has_five_pwm(config)) 2863 sio_data->skip_pwm |= BIT(4) | BIT(5); 2864 else if (!has_six_pwm(config)) 2865 sio_data->skip_pwm |= BIT(5); 2866 2867 if (!has_vid(config)) 2868 sio_data->skip_vid = 1; 2869 2870 /* Read GPIO config and VID value from LDN 7 (GPIO) */ 2871 if (sio_data->type == it87) { 2872 /* The IT8705F has a different LD number for GPIO */ 2873 superio_select(sioaddr, 5); 2874 sio_data->beep_pin = superio_inb(sioaddr, 2875 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2876 } else if (sio_data->type == it8783) { 2877 int reg25, reg27, reg2a, reg2c, regef; 2878 2879 superio_select(sioaddr, GPIO); 2880 2881 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); 2882 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2883 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG); 2884 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 2885 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG); 2886 2887 /* Check if fan3 is there or not */ 2888 if ((reg27 & BIT(0)) || !(reg2c & BIT(2))) 2889 sio_data->skip_fan |= BIT(2); 2890 if ((reg25 & BIT(4)) || 2891 (!(reg2a & BIT(1)) && (regef & BIT(0)))) 2892 sio_data->skip_pwm |= BIT(2); 2893 2894 /* Check if fan2 is there or not */ 2895 if (reg27 & BIT(7)) 2896 sio_data->skip_fan |= BIT(1); 2897 if (reg27 & BIT(3)) 2898 sio_data->skip_pwm |= BIT(1); 2899 2900 /* VIN5 */ 2901 if ((reg27 & BIT(0)) || (reg2c & BIT(2))) 2902 sio_data->skip_in |= BIT(5); /* No VIN5 */ 2903 2904 /* VIN6 */ 2905 if (reg27 & BIT(1)) 2906 sio_data->skip_in |= BIT(6); /* No VIN6 */ 2907 2908 /* 2909 * VIN7 2910 * Does not depend on bit 2 of Reg2C, contrary to datasheet. 2911 */ 2912 if (reg27 & BIT(2)) { 2913 /* 2914 * The data sheet is a bit unclear regarding the 2915 * internal voltage divider for VCCH5V. It says 2916 * "This bit enables and switches VIN7 (pin 91) to the 2917 * internal voltage divider for VCCH5V". 2918 * This is different to other chips, where the internal 2919 * voltage divider would connect VIN7 to an internal 2920 * voltage source. Maybe that is the case here as well. 2921 * 2922 * Since we don't know for sure, re-route it if that is 2923 * not the case, and ask the user to report if the 2924 * resulting voltage is sane. 2925 */ 2926 if (!(reg2c & BIT(1))) { 2927 reg2c |= BIT(1); 2928 superio_outb(sioaddr, IT87_SIO_PINX2_REG, 2929 reg2c); 2930 sio_data->need_in7_reroute = true; 2931 pr_notice("Routing internal VCCH5V to in7.\n"); 2932 } 2933 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n"); 2934 pr_notice("Please report if it displays a reasonable voltage.\n"); 2935 } 2936 2937 if (reg2c & BIT(0)) 2938 sio_data->internal |= BIT(0); 2939 if (reg2c & BIT(1)) 2940 sio_data->internal |= BIT(1); 2941 2942 sio_data->beep_pin = superio_inb(sioaddr, 2943 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2944 } else if (sio_data->type == it8603) { 2945 int reg27, reg29; 2946 2947 superio_select(sioaddr, GPIO); 2948 2949 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2950 2951 /* Check if fan3 is there or not */ 2952 if (reg27 & BIT(6)) 2953 sio_data->skip_pwm |= BIT(2); 2954 if (reg27 & BIT(7)) 2955 sio_data->skip_fan |= BIT(2); 2956 2957 /* Check if fan2 is there or not */ 2958 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 2959 if (reg29 & BIT(1)) 2960 sio_data->skip_pwm |= BIT(1); 2961 if (reg29 & BIT(2)) 2962 sio_data->skip_fan |= BIT(1); 2963 2964 sio_data->skip_in |= BIT(5); /* No VIN5 */ 2965 sio_data->skip_in |= BIT(6); /* No VIN6 */ 2966 2967 sio_data->beep_pin = superio_inb(sioaddr, 2968 IT87_SIO_BEEP_PIN_REG) & 0x3f; 2969 } else if (sio_data->type == it8620 || sio_data->type == it8628) { 2970 int reg; 2971 2972 superio_select(sioaddr, GPIO); 2973 2974 /* Check for pwm5 */ 2975 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); 2976 if (reg & BIT(6)) 2977 sio_data->skip_pwm |= BIT(4); 2978 2979 /* Check for fan4, fan5 */ 2980 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); 2981 if (!(reg & BIT(5))) 2982 sio_data->skip_fan |= BIT(3); 2983 if (!(reg & BIT(4))) 2984 sio_data->skip_fan |= BIT(4); 2985 2986 /* Check for pwm3, fan3 */ 2987 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 2988 if (reg & BIT(6)) 2989 sio_data->skip_pwm |= BIT(2); 2990 if (reg & BIT(7)) 2991 sio_data->skip_fan |= BIT(2); 2992 2993 /* Check for pwm4 */ 2994 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG); 2995 if (reg & BIT(2)) 2996 sio_data->skip_pwm |= BIT(3); 2997 2998 /* Check for pwm2, fan2 */ 2999 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 3000 if (reg & BIT(1)) 3001 sio_data->skip_pwm |= BIT(1); 3002 if (reg & BIT(2)) 3003 sio_data->skip_fan |= BIT(1); 3004 /* Check for pwm6, fan6 */ 3005 if (!(reg & BIT(7))) { 3006 sio_data->skip_pwm |= BIT(5); 3007 sio_data->skip_fan |= BIT(5); 3008 } 3009 3010 /* Check if AVCC is on VIN3 */ 3011 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 3012 if (reg & BIT(0)) 3013 sio_data->internal |= BIT(0); 3014 else 3015 sio_data->skip_in |= BIT(9); 3016 3017 sio_data->beep_pin = superio_inb(sioaddr, 3018 IT87_SIO_BEEP_PIN_REG) & 0x3f; 3019 } else if (sio_data->type == it8689) { 3020 int reg; 3021 3022 superio_select(sioaddr, GPIO); 3023 3024 /* Check for pwm5 */ 3025 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); 3026 if (reg & BIT(6)) 3027 sio_data->skip_pwm |= BIT(4); 3028 3029 /* Check for fan4, fan5 */ 3030 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); 3031 if (!(reg & BIT(5))) 3032 sio_data->skip_fan |= BIT(3); 3033 if (!(reg & BIT(4))) 3034 sio_data->skip_fan |= BIT(4); 3035 3036 /* Check for pwm3, fan3 */ 3037 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 3038 if (reg & BIT(6)) 3039 sio_data->skip_pwm |= BIT(2); 3040 if (reg & BIT(7)) 3041 sio_data->skip_fan |= BIT(2); 3042 3043 /* Check for pwm4 */ 3044 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG); 3045 if (reg & BIT(2)) 3046 sio_data->skip_pwm |= BIT(3); 3047 3048 /* Check for pwm2, fan2 */ 3049 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 3050 if (reg & BIT(1)) 3051 sio_data->skip_pwm |= BIT(1); 3052 if (reg & BIT(2)) 3053 sio_data->skip_fan |= BIT(1); 3054 /* Check for pwm6, fan6 */ 3055 if (!(reg & BIT(7))) { 3056 sio_data->skip_pwm |= BIT(5); 3057 sio_data->skip_fan |= BIT(5); 3058 } 3059 3060 /* in9 (AVCC3) is always internal, no PINX2 check needed */ 3061 3062 sio_data->beep_pin = superio_inb(sioaddr, 3063 IT87_SIO_BEEP_PIN_REG) & 0x3f; 3064 } else if (sio_data->type == it8622) { 3065 int reg; 3066 3067 superio_select(sioaddr, GPIO); 3068 3069 /* Check for pwm4, fan4 */ 3070 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG); 3071 if (reg & BIT(6)) 3072 sio_data->skip_fan |= BIT(3); 3073 if (reg & BIT(5)) 3074 sio_data->skip_pwm |= BIT(3); 3075 3076 /* Check for pwm3, fan3, pwm5, fan5 */ 3077 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 3078 if (reg & BIT(6)) 3079 sio_data->skip_pwm |= BIT(2); 3080 if (reg & BIT(7)) 3081 sio_data->skip_fan |= BIT(2); 3082 if (reg & BIT(3)) 3083 sio_data->skip_pwm |= BIT(4); 3084 if (reg & BIT(1)) 3085 sio_data->skip_fan |= BIT(4); 3086 3087 /* Check for pwm2, fan2 */ 3088 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 3089 if (reg & BIT(1)) 3090 sio_data->skip_pwm |= BIT(1); 3091 if (reg & BIT(2)) 3092 sio_data->skip_fan |= BIT(1); 3093 3094 /* Check for AVCC */ 3095 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 3096 if (!(reg & BIT(0))) 3097 sio_data->skip_in |= BIT(9); 3098 3099 sio_data->beep_pin = superio_inb(sioaddr, 3100 IT87_SIO_BEEP_PIN_REG) & 0x3f; 3101 } else if (sio_data->type == it8732) { 3102 int reg; 3103 3104 superio_select(sioaddr, GPIO); 3105 3106 /* Check for pwm2, fan2 */ 3107 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 3108 if (reg & BIT(1)) 3109 sio_data->skip_pwm |= BIT(1); 3110 if (reg & BIT(2)) 3111 sio_data->skip_fan |= BIT(1); 3112 3113 /* Check for pwm3, fan3, fan4 */ 3114 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 3115 if (reg & BIT(6)) 3116 sio_data->skip_pwm |= BIT(2); 3117 if (reg & BIT(7)) 3118 sio_data->skip_fan |= BIT(2); 3119 if (reg & BIT(5)) 3120 sio_data->skip_fan |= BIT(3); 3121 3122 /* Check if AVCC is on VIN3 */ 3123 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 3124 if (reg & BIT(0)) 3125 sio_data->internal |= BIT(0); 3126 3127 sio_data->beep_pin = superio_inb(sioaddr, 3128 IT87_SIO_BEEP_PIN_REG) & 0x3f; 3129 } else { 3130 int reg; 3131 bool uart6; 3132 3133 superio_select(sioaddr, GPIO); 3134 3135 /* Check for fan4, fan5 */ 3136 if (has_five_fans(config)) { 3137 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG); 3138 switch (sio_data->type) { 3139 case it8718: 3140 if (reg & BIT(5)) 3141 sio_data->skip_fan |= BIT(3); 3142 if (reg & BIT(4)) 3143 sio_data->skip_fan |= BIT(4); 3144 break; 3145 case it8720: 3146 case it8721: 3147 case it8728: 3148 if (!(reg & BIT(5))) 3149 sio_data->skip_fan |= BIT(3); 3150 if (!(reg & BIT(4))) 3151 sio_data->skip_fan |= BIT(4); 3152 break; 3153 default: 3154 break; 3155 } 3156 } 3157 3158 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG); 3159 if (!sio_data->skip_vid) { 3160 /* We need at least 4 VID pins */ 3161 if (reg & 0x0f) { 3162 pr_info("VID is disabled (pins used for GPIO)\n"); 3163 sio_data->skip_vid = 1; 3164 } 3165 } 3166 3167 /* Check if fan3 is there or not */ 3168 if (reg & BIT(6)) 3169 sio_data->skip_pwm |= BIT(2); 3170 if (reg & BIT(7)) 3171 sio_data->skip_fan |= BIT(2); 3172 3173 /* Check if fan2 is there or not */ 3174 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG); 3175 if (reg & BIT(1)) 3176 sio_data->skip_pwm |= BIT(1); 3177 if (reg & BIT(2)) 3178 sio_data->skip_fan |= BIT(1); 3179 3180 if ((sio_data->type == it8718 || sio_data->type == it8720) && 3181 !(sio_data->skip_vid)) 3182 sio_data->vid_value = superio_inb(sioaddr, 3183 IT87_SIO_VID_REG); 3184 3185 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG); 3186 3187 uart6 = sio_data->type == it8782 && (reg & BIT(2)); 3188 3189 /* 3190 * The IT8720F has no VIN7 pin, so VCCH5V should always be 3191 * routed internally to VIN7 with an internal divider. 3192 * Curiously, there still is a configuration bit to control 3193 * this, which means it can be set incorrectly. And even 3194 * more curiously, many boards out there are improperly 3195 * configured, even though the IT8720F datasheet claims 3196 * that the internal routing of VCCH5V to VIN7 is the default 3197 * setting. So we force the internal routing in this case. 3198 * 3199 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins. 3200 * If UART6 is enabled, re-route VIN7 to the internal divider 3201 * if that is not already the case. 3202 */ 3203 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) { 3204 reg |= BIT(1); 3205 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg); 3206 sio_data->need_in7_reroute = true; 3207 pr_notice("Routing internal VCCH5V to in7\n"); 3208 } 3209 if (reg & BIT(0)) 3210 sio_data->internal |= BIT(0); 3211 if (reg & BIT(1)) 3212 sio_data->internal |= BIT(1); 3213 3214 /* 3215 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7. 3216 * While VIN7 can be routed to the internal voltage divider, 3217 * VIN5 and VIN6 are not available if UART6 is enabled. 3218 * 3219 * Also, temp3 is not available if UART6 is enabled and TEMPIN3 3220 * is the temperature source. Since we can not read the 3221 * temperature source here, skip_temp is preliminary. 3222 */ 3223 if (uart6) { 3224 sio_data->skip_in |= BIT(5) | BIT(6); 3225 sio_data->skip_temp |= BIT(2); 3226 } 3227 3228 sio_data->beep_pin = superio_inb(sioaddr, 3229 IT87_SIO_BEEP_PIN_REG) & 0x3f; 3230 } 3231 if (sio_data->beep_pin) 3232 pr_info("Beeping is supported\n"); 3233 3234 /* Set values based on DMI matches */ 3235 if (dmi_data) 3236 sio_data->skip_pwm |= dmi_data->skip_pwm; 3237 3238 if (config->smbus_bitmap) { 3239 u8 reg; 3240 3241 superio_select(sioaddr, PME); 3242 reg = superio_inb(sioaddr, IT87_SPECIAL_CFG_REG); 3243 sio_data->ec_special_config = reg; 3244 sio_data->smbus_bitmap = reg & config->smbus_bitmap; 3245 } 3246 3247 exit: 3248 superio_exit(sioaddr, !enabled); 3249 return err; 3250 } 3251 3252 /* 3253 * Some chips seem to have default value 0xff for all limit 3254 * registers. For low voltage limits it makes no sense and triggers 3255 * alarms, so change to 0 instead. For high temperature limits, it 3256 * means -1 degree C, which surprisingly doesn't trigger an alarm, 3257 * but is still confusing, so change to 127 degrees C. 3258 */ 3259 static void it87_check_limit_regs(struct it87_data *data) 3260 { 3261 int i, reg; 3262 3263 for (i = 0; i < NUM_VIN_LIMIT; i++) { 3264 reg = it87_read_value(data, IT87_REG_VIN_MIN(i)); 3265 if (reg == 0xff) 3266 it87_write_value(data, IT87_REG_VIN_MIN(i), 0); 3267 } 3268 for (i = 0; i < NUM_TEMP_LIMIT; i++) { 3269 reg = it87_read_value(data, IT87_REG_TEMP_HIGH(i)); 3270 if (reg == 0xff) 3271 it87_write_value(data, IT87_REG_TEMP_HIGH(i), 127); 3272 } 3273 } 3274 3275 /* Check if voltage monitors are reset manually or by some reason */ 3276 static void it87_check_voltage_monitors_reset(struct it87_data *data) 3277 { 3278 int reg; 3279 3280 reg = it87_read_value(data, IT87_REG_VIN_ENABLE); 3281 if ((reg & 0xff) == 0) { 3282 /* Enable all voltage monitors */ 3283 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff); 3284 } 3285 } 3286 3287 /* Check if tachometers are reset manually or by some reason */ 3288 static void it87_check_tachometers_reset(struct platform_device *pdev) 3289 { 3290 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev); 3291 struct it87_data *data = platform_get_drvdata(pdev); 3292 u8 mask, fan_main_ctrl; 3293 3294 mask = 0x70 & ~(sio_data->skip_fan << 4); 3295 fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL); 3296 if ((fan_main_ctrl & mask) == 0) { 3297 /* Enable all fan tachometers */ 3298 fan_main_ctrl |= mask; 3299 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL, 3300 fan_main_ctrl); 3301 } 3302 } 3303 3304 /* Set tachometers to 16-bit mode if needed */ 3305 static void it87_check_tachometers_16bit_mode(struct platform_device *pdev) 3306 { 3307 struct it87_data *data = platform_get_drvdata(pdev); 3308 int reg; 3309 3310 if (!has_fan16_config(data)) 3311 return; 3312 3313 reg = it87_read_value(data, IT87_REG_FAN_16BIT); 3314 if (~reg & 0x07 & data->has_fan) { 3315 dev_dbg(&pdev->dev, 3316 "Setting fan1-3 to 16-bit mode\n"); 3317 it87_write_value(data, IT87_REG_FAN_16BIT, 3318 reg | 0x07); 3319 } 3320 } 3321 3322 static void it87_start_monitoring(struct it87_data *data) 3323 { 3324 it87_write_value(data, IT87_REG_CONFIG, 3325 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e) 3326 | (update_vbat ? 0x41 : 0x01)); 3327 } 3328 3329 /* Called when we have found a new IT87. */ 3330 static void it87_init_device(struct platform_device *pdev) 3331 { 3332 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev); 3333 struct it87_data *data = platform_get_drvdata(pdev); 3334 int tmp, i; 3335 3336 /* 3337 * For each PWM channel: 3338 * - If it is in automatic mode, setting to manual mode should set 3339 * the fan to full speed by default. 3340 * - If it is in manual mode, we need a mapping to temperature 3341 * channels to use when later setting to automatic mode later. 3342 * Use a 1:1 mapping by default (we are clueless.) 3343 * In both cases, the value can (and should) be changed by the user 3344 * prior to switching to a different mode. 3345 * Note that this is no longer needed for the IT8721F and later, as 3346 * these have separate registers for the temperature mapping and the 3347 * manual duty cycle. 3348 */ 3349 for (i = 0; i < NUM_AUTO_PWM; i++) { 3350 data->pwm_temp_map[i] = i; 3351 data->pwm_duty[i] = 0x7f; /* Full speed */ 3352 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */ 3353 } 3354 3355 it87_check_limit_regs(data); 3356 3357 /* 3358 * Temperature channels are not forcibly enabled, as they can be 3359 * set to two different sensor types and we can't guess which one 3360 * is correct for a given system. These channels can be enabled at 3361 * run-time through the temp{1-3}_type sysfs accessors if needed. 3362 */ 3363 3364 it87_check_voltage_monitors_reset(data); 3365 3366 it87_check_tachometers_reset(pdev); 3367 3368 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL); 3369 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07; 3370 3371 it87_check_tachometers_16bit_mode(pdev); 3372 3373 /* Check for additional fans */ 3374 tmp = it87_read_value(data, IT87_REG_FAN_16BIT); 3375 3376 if (has_four_fans(data) && (tmp & BIT(4))) 3377 data->has_fan |= BIT(3); /* fan4 enabled */ 3378 if (has_five_fans(data) && (tmp & BIT(5))) 3379 data->has_fan |= BIT(4); /* fan5 enabled */ 3380 if (has_six_fans(data) && (tmp & BIT(2))) 3381 data->has_fan |= BIT(5); /* fan6 enabled */ 3382 3383 /* Fan input pins may be used for alternative functions */ 3384 data->has_fan &= ~sio_data->skip_fan; 3385 3386 /* Check if pwm5, pwm6 are enabled */ 3387 if (has_six_pwm(data)) { 3388 /* The following code may be IT8620E specific */ 3389 tmp = it87_read_value(data, IT87_REG_FAN_DIV); 3390 if ((tmp & 0xc0) == 0xc0) 3391 sio_data->skip_pwm |= BIT(4); 3392 if (!(tmp & BIT(3))) 3393 sio_data->skip_pwm |= BIT(5); 3394 } 3395 3396 it87_start_monitoring(data); 3397 } 3398 3399 /* Return 1 if and only if the PWM interface is safe to use */ 3400 static int it87_check_pwm(struct device *dev) 3401 { 3402 struct it87_data *data = dev_get_drvdata(dev); 3403 /* 3404 * Some BIOSes fail to correctly configure the IT87 fans. All fans off 3405 * and polarity set to active low is sign that this is the case so we 3406 * disable pwm control to protect the user. 3407 */ 3408 int tmp = it87_read_value(data, IT87_REG_FAN_CTL); 3409 3410 if ((tmp & 0x87) == 0) { 3411 if (fix_pwm_polarity) { 3412 /* 3413 * The user asks us to attempt a chip reconfiguration. 3414 * This means switching to active high polarity and 3415 * inverting all fan speed values. 3416 */ 3417 int i; 3418 u8 pwm[3]; 3419 3420 for (i = 0; i < ARRAY_SIZE(pwm); i++) 3421 pwm[i] = it87_read_value(data, 3422 IT87_REG_PWM[i]); 3423 3424 /* 3425 * If any fan is in automatic pwm mode, the polarity 3426 * might be correct, as suspicious as it seems, so we 3427 * better don't change anything (but still disable the 3428 * PWM interface). 3429 */ 3430 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) { 3431 dev_info(dev, 3432 "Reconfiguring PWM to active high polarity\n"); 3433 it87_write_value(data, IT87_REG_FAN_CTL, 3434 tmp | 0x87); 3435 for (i = 0; i < 3; i++) 3436 it87_write_value(data, 3437 IT87_REG_PWM[i], 3438 0x7f & ~pwm[i]); 3439 return 1; 3440 } 3441 3442 dev_info(dev, 3443 "PWM configuration is too broken to be fixed\n"); 3444 } 3445 3446 return 0; 3447 } else if (fix_pwm_polarity) { 3448 dev_info(dev, 3449 "PWM configuration looks sane, won't touch\n"); 3450 } 3451 3452 return 1; 3453 } 3454 3455 static int it87_probe(struct platform_device *pdev) 3456 { 3457 struct it87_data *data; 3458 struct resource *res; 3459 struct device *dev = &pdev->dev; 3460 struct it87_sio_data *sio_data = dev_get_platdata(dev); 3461 int enable_pwm_interface; 3462 struct device *hwmon_dev; 3463 int err; 3464 3465 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 3466 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT, 3467 DRVNAME)) { 3468 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n", 3469 (unsigned long)res->start, 3470 (unsigned long)(res->start + IT87_EC_EXTENT - 1)); 3471 return -EBUSY; 3472 } 3473 3474 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL); 3475 if (!data) 3476 return -ENOMEM; 3477 3478 data->addr = res->start; 3479 data->sioaddr = sio_data->sioaddr; 3480 data->type = sio_data->type; 3481 data->smbus_bitmap = sio_data->smbus_bitmap; 3482 data->ec_special_config = sio_data->ec_special_config; 3483 data->features = it87_devices[sio_data->type].features; 3484 data->peci_mask = it87_devices[sio_data->type].peci_mask; 3485 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask; 3486 /* 3487 * IT8705F Datasheet 0.4.1, 3h == Version G. 3488 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J. 3489 * These are the first revisions with 16-bit tachometer support. 3490 */ 3491 switch (data->type) { 3492 case it87: 3493 if (sio_data->revision >= 0x03) { 3494 data->features &= ~FEAT_OLD_AUTOPWM; 3495 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS; 3496 } 3497 break; 3498 case it8712: 3499 if (sio_data->revision >= 0x08) { 3500 data->features &= ~FEAT_OLD_AUTOPWM; 3501 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS | 3502 FEAT_FIVE_FANS; 3503 } 3504 break; 3505 default: 3506 break; 3507 } 3508 3509 platform_set_drvdata(pdev, data); 3510 3511 mutex_init(&data->update_lock); 3512 3513 err = smbus_disable(data); 3514 if (err) 3515 return err; 3516 3517 /* Now, we do the remaining detection. */ 3518 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) || 3519 it87_read_value(data, IT87_REG_CHIPID) != 0x90) { 3520 smbus_enable(data); 3521 return -ENODEV; 3522 } 3523 3524 /* Check PWM configuration */ 3525 enable_pwm_interface = it87_check_pwm(dev); 3526 if (!enable_pwm_interface) 3527 dev_info(dev, 3528 "Detected broken BIOS defaults, disabling PWM interface\n"); 3529 3530 /* Starting with IT8721F, we handle scaling of internal voltages */ 3531 if (has_scaling(data)) { 3532 if (sio_data->internal & BIT(0)) 3533 data->in_scaled |= BIT(3); /* in3 is AVCC */ 3534 if (sio_data->internal & BIT(1)) 3535 data->in_scaled |= BIT(7); /* in7 is VSB */ 3536 if (sio_data->internal & BIT(2)) 3537 data->in_scaled |= BIT(8); /* in8 is Vbat */ 3538 if (sio_data->internal & BIT(3)) 3539 data->in_scaled |= BIT(9); /* in9 is AVCC */ 3540 } else if (sio_data->type == it8781 || sio_data->type == it8782 || 3541 sio_data->type == it8783) { 3542 if (sio_data->internal & BIT(0)) 3543 data->in_scaled |= BIT(3); /* in3 is VCC5V */ 3544 if (sio_data->internal & BIT(1)) 3545 data->in_scaled |= BIT(7); /* in7 is VCCH5V */ 3546 } 3547 3548 data->has_temp = 0x07; 3549 if (sio_data->skip_temp & BIT(2)) { 3550 if (sio_data->type == it8782 && 3551 !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80)) 3552 data->has_temp &= ~BIT(2); 3553 } 3554 3555 data->in_internal = sio_data->internal; 3556 data->need_in7_reroute = sio_data->need_in7_reroute; 3557 data->has_in = 0x3ff & ~sio_data->skip_in; 3558 3559 if (has_four_temp(data)) { 3560 data->has_temp |= BIT(3); 3561 } else if (has_six_temp(data)) { 3562 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE); 3563 3564 /* Check for additional temperature sensors */ 3565 if ((reg & 0x03) >= 0x02) 3566 data->has_temp |= BIT(3); 3567 if (((reg >> 2) & 0x03) >= 0x02) 3568 data->has_temp |= BIT(4); 3569 if (((reg >> 4) & 0x03) >= 0x02) 3570 data->has_temp |= BIT(5); 3571 3572 /* Check for additional voltage sensors */ 3573 if ((reg & 0x03) == 0x01) 3574 data->has_in |= BIT(10); 3575 if (((reg >> 2) & 0x03) == 0x01) 3576 data->has_in |= BIT(11); 3577 if (((reg >> 4) & 0x03) == 0x01) 3578 data->has_in |= BIT(12); 3579 } 3580 3581 data->has_beep = !!sio_data->beep_pin; 3582 3583 /* Initialize the IT87 chip */ 3584 it87_init_device(pdev); 3585 3586 smbus_enable(data); 3587 3588 if (!sio_data->skip_vid) { 3589 data->has_vid = true; 3590 data->vrm = vid_which_vrm(); 3591 /* VID reading from Super-I/O config space if available */ 3592 data->vid = sio_data->vid_value; 3593 } 3594 3595 /* Prepare for sysfs hooks */ 3596 data->groups[0] = &it87_group; 3597 data->groups[1] = &it87_group_in; 3598 data->groups[2] = &it87_group_temp; 3599 data->groups[3] = &it87_group_fan; 3600 3601 if (enable_pwm_interface) { 3602 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1; 3603 data->has_pwm &= ~sio_data->skip_pwm; 3604 3605 data->groups[4] = &it87_group_pwm; 3606 if (has_old_autopwm(data) || has_newer_autopwm(data)) 3607 data->groups[5] = &it87_group_auto_pwm; 3608 } 3609 3610 hwmon_dev = devm_hwmon_device_register_with_groups(dev, 3611 it87_devices[sio_data->type].name, 3612 data, data->groups); 3613 return PTR_ERR_OR_ZERO(hwmon_dev); 3614 } 3615 3616 static void it87_resume_sio(struct platform_device *pdev) 3617 { 3618 struct it87_data *data = dev_get_drvdata(&pdev->dev); 3619 int err; 3620 int reg2c; 3621 3622 if (!data->need_in7_reroute) 3623 return; 3624 3625 err = superio_enter(data->sioaddr, has_noconf(data)); 3626 if (err) { 3627 dev_warn(&pdev->dev, 3628 "Unable to enter Super I/O to reroute in7 (%d)", 3629 err); 3630 return; 3631 } 3632 3633 superio_select(data->sioaddr, GPIO); 3634 3635 reg2c = superio_inb(data->sioaddr, IT87_SIO_PINX2_REG); 3636 if (!(reg2c & BIT(1))) { 3637 dev_dbg(&pdev->dev, 3638 "Routing internal VCCH5V to in7 again"); 3639 3640 reg2c |= BIT(1); 3641 superio_outb(data->sioaddr, IT87_SIO_PINX2_REG, 3642 reg2c); 3643 } 3644 3645 superio_exit(data->sioaddr, has_noconf(data)); 3646 } 3647 3648 static int it87_resume(struct device *dev) 3649 { 3650 struct platform_device *pdev = to_platform_device(dev); 3651 struct it87_data *data = dev_get_drvdata(dev); 3652 int err; 3653 3654 it87_resume_sio(pdev); 3655 3656 err = it87_lock(data); 3657 if (err) 3658 return err; 3659 3660 it87_check_pwm(dev); 3661 it87_check_limit_regs(data); 3662 it87_check_voltage_monitors_reset(data); 3663 it87_check_tachometers_reset(pdev); 3664 it87_check_tachometers_16bit_mode(pdev); 3665 3666 it87_start_monitoring(data); 3667 3668 /* force update */ 3669 data->valid = false; 3670 3671 it87_unlock(data); 3672 3673 it87_update_device(dev); 3674 3675 return 0; 3676 } 3677 3678 static DEFINE_SIMPLE_DEV_PM_OPS(it87_dev_pm_ops, NULL, it87_resume); 3679 3680 static struct platform_driver it87_driver = { 3681 .driver = { 3682 .name = DRVNAME, 3683 .pm = pm_sleep_ptr(&it87_dev_pm_ops), 3684 }, 3685 .probe = it87_probe, 3686 }; 3687 3688 static int __init it87_device_add(int index, unsigned short address, 3689 const struct it87_sio_data *sio_data) 3690 { 3691 struct platform_device *pdev; 3692 struct resource res = { 3693 .start = address + IT87_EC_OFFSET, 3694 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1, 3695 .name = DRVNAME, 3696 .flags = IORESOURCE_IO, 3697 }; 3698 int err; 3699 3700 err = acpi_check_resource_conflict(&res); 3701 if (err) { 3702 if (!ignore_resource_conflict) 3703 return err; 3704 } 3705 3706 pdev = platform_device_alloc(DRVNAME, address); 3707 if (!pdev) 3708 return -ENOMEM; 3709 3710 err = platform_device_add_resources(pdev, &res, 1); 3711 if (err) { 3712 pr_err("Device resource addition failed (%d)\n", err); 3713 goto exit_device_put; 3714 } 3715 3716 err = platform_device_add_data(pdev, sio_data, 3717 sizeof(struct it87_sio_data)); 3718 if (err) { 3719 pr_err("Platform data allocation failed\n"); 3720 goto exit_device_put; 3721 } 3722 3723 err = platform_device_add(pdev); 3724 if (err) { 3725 pr_err("Device addition failed (%d)\n", err); 3726 goto exit_device_put; 3727 } 3728 3729 it87_pdev[index] = pdev; 3730 return 0; 3731 3732 exit_device_put: 3733 platform_device_put(pdev); 3734 return err; 3735 } 3736 3737 /* callback function for DMI */ 3738 static int it87_dmi_cb(const struct dmi_system_id *dmi_entry) 3739 { 3740 dmi_data = dmi_entry->driver_data; 3741 3742 if (dmi_data && dmi_data->skip_pwm) 3743 pr_info("Disabling pwm2 due to hardware constraints\n"); 3744 3745 return 1; 3746 } 3747 3748 /* 3749 * On the Shuttle SN68PT, FAN_CTL2 is apparently not 3750 * connected to a fan, but to something else. One user 3751 * has reported instant system power-off when changing 3752 * the PWM2 duty cycle, so we disable it. 3753 * I use the board name string as the trigger in case 3754 * the same board is ever used in other systems. 3755 */ 3756 static struct it87_dmi_data nvidia_fn68pt = { 3757 .skip_pwm = BIT(1), 3758 }; 3759 3760 #define IT87_DMI_MATCH_VND(vendor, name, cb, data) \ 3761 { \ 3762 .callback = cb, \ 3763 .matches = { \ 3764 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, vendor), \ 3765 DMI_EXACT_MATCH(DMI_BOARD_NAME, name), \ 3766 }, \ 3767 .driver_data = data, \ 3768 } 3769 3770 static const struct dmi_system_id it87_dmi_table[] __initconst = { 3771 IT87_DMI_MATCH_VND("nVIDIA", "FN68PT", it87_dmi_cb, &nvidia_fn68pt), 3772 { } 3773 3774 }; 3775 MODULE_DEVICE_TABLE(dmi, it87_dmi_table); 3776 3777 static int __init sm_it87_init(void) 3778 { 3779 int sioaddr[2] = { REG_2E, REG_4E }; 3780 struct it87_sio_data sio_data; 3781 unsigned short isa_address[2]; 3782 bool found = false; 3783 int i, err; 3784 3785 err = platform_driver_register(&it87_driver); 3786 if (err) 3787 return err; 3788 3789 dmi_check_system(it87_dmi_table); 3790 3791 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) { 3792 memset(&sio_data, 0, sizeof(struct it87_sio_data)); 3793 isa_address[i] = 0; 3794 err = it87_find(sioaddr[i], &isa_address[i], &sio_data, i); 3795 if (err || isa_address[i] == 0) 3796 continue; 3797 /* 3798 * Don't register second chip if its ISA address matches 3799 * the first chip's ISA address. 3800 */ 3801 if (i && isa_address[i] == isa_address[0]) 3802 break; 3803 3804 err = it87_device_add(i, isa_address[i], &sio_data); 3805 if (err) 3806 goto exit_dev_unregister; 3807 3808 found = true; 3809 3810 /* 3811 * IT8705F may respond on both SIO addresses. 3812 * Stop probing after finding one. 3813 */ 3814 if (sio_data.type == it87) 3815 break; 3816 } 3817 3818 if (!found) { 3819 err = -ENODEV; 3820 goto exit_unregister; 3821 } 3822 return 0; 3823 3824 exit_dev_unregister: 3825 /* NULL check handled by platform_device_unregister */ 3826 platform_device_unregister(it87_pdev[0]); 3827 exit_unregister: 3828 platform_driver_unregister(&it87_driver); 3829 return err; 3830 } 3831 3832 static void __exit sm_it87_exit(void) 3833 { 3834 /* NULL check handled by platform_device_unregister */ 3835 platform_device_unregister(it87_pdev[1]); 3836 platform_device_unregister(it87_pdev[0]); 3837 platform_driver_unregister(&it87_driver); 3838 } 3839 3840 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>"); 3841 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver"); 3842 3843 module_param_array(force_id, ushort, &force_id_cnt, 0); 3844 MODULE_PARM_DESC(force_id, "Override one or more detected device ID(s)"); 3845 3846 module_param(ignore_resource_conflict, bool, 0); 3847 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict"); 3848 3849 module_param(update_vbat, bool, 0); 3850 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value"); 3851 3852 module_param(fix_pwm_polarity, bool, 0); 3853 MODULE_PARM_DESC(fix_pwm_polarity, 3854 "Force PWM polarity to active high (DANGEROUS)"); 3855 3856 MODULE_LICENSE("GPL"); 3857 3858 module_init(sm_it87_init); 3859 module_exit(sm_it87_exit); 3860