1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA driver for RME Hammerfall DSP MADI audio interface(s) 4 * 5 * Copyright (c) 2003 Winfried Ritsch (IEM) 6 * code based on hdsp.c Paul Davis 7 * Marcus Andersson 8 * Thomas Charbonnel 9 * Modified 2006-06-01 for AES32 support by Remy Bruno 10 * <remy.bruno@trinnov.com> 11 * 12 * Modified 2009-04-13 for proper metering by Florian Faber 13 * <faber@faberman.de> 14 * 15 * Modified 2009-04-14 for native float support by Florian Faber 16 * <faber@faberman.de> 17 * 18 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber 19 * <faber@faberman.de> 20 * 21 * Modified 2009-04-30 added hw serial number support by Florian Faber 22 * 23 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth 24 * 25 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth 26 * 27 * Modified 2019-05-23 fix AIO single speed ADAT capture and playback 28 * by Philippe.Bekaert@uhasselt.be 29 */ 30 31 /* ************* Register Documentation ******************************************************* 32 * 33 * Work in progress! Documentation is based on the code in this file. 34 * 35 * --------- HDSPM_controlRegister --------- 36 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte 37 * :||||.||||:||||.||||:||||.||||:||||.||||: 38 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number 39 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31 40 * :||||.||||:||||.||||:||||.||||:||||.||||: 41 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit 42 * : . : . : . : x . : HDSPM_AudioInterruptEnable \_ setting both bits 43 * : . : . : . : . x: HDSPM_Start / enables audio IO 44 * : . : . : . : x. : HDSPM_ClockModeMaster - 1: Master, 0: Slave 45 * : . : . : . : .210 : HDSPM_LatencyMask - 3 Bit value for latency 46 * : . : . : . : . : 0:64, 1:128, 2:256, 3:512, 47 * : . : . : . : . : 4:1024, 5:2048, 6:4096, 7:8192 48 * :x . : . : . x:xx . : HDSPM_FrequencyMask 49 * : . : . : . :10 . : HDSPM_Frequency1|HDSPM_Frequency0: 1=32K,2=44.1K,3=48K,0=?? 50 * : . : . : . x: . : <MADI> HDSPM_DoubleSpeed 51 * :x . : . : . : . : <MADI> HDSPM_QuadSpeed 52 * : . 3 : . 10: 2 . : . : HDSPM_SyncRefMask : 53 * : . : . x: . : . : HDSPM_SyncRef0 54 * : . : . x : . : . : HDSPM_SyncRef1 55 * : . : . : x . : . : <AES32> HDSPM_SyncRef2 56 * : . x : . : . : . : <AES32> HDSPM_SyncRef3 57 * : . : . 10: . : . : <MADI> sync ref: 0:WC, 1:Madi, 2:TCO, 3:SyncIn 58 * : . 3 : . 10: 2 . : . : <AES32> 0:WC, 1:AES1 ... 8:AES8, 9: TCO, 10:SyncIn? 59 * : . x : . : . : . : <MADIe> HDSPe_FLOAT_FORMAT 60 * : . : . : x . : . : <MADI> HDSPM_InputSelect0 : 0=optical,1=coax 61 * : . : . :x . : . : <MADI> HDSPM_InputSelect1 62 * : . : .x : . : . : <MADI> HDSPM_clr_tms 63 * : . : . : . x : . : <MADI> HDSPM_TX_64ch 64 * : . : . : . x : . : <AES32> HDSPM_Emphasis 65 * : . : . : .x : . : <MADI> HDSPM_AutoInp 66 * : . : . x : . : . : <MADI> HDSPM_SMUX 67 * : . : .x : . : . : <MADI> HDSPM_clr_tms 68 * : . : x. : . : . : <MADI> HDSPM_taxi_reset 69 * : . x: . : . : . : <MADI> HDSPM_LineOut 70 * : . x: . : . : . : <AES32> ?????????????????? 71 * : . : x. : . : . : <AES32> HDSPM_WCK48 72 * : . : . : .x : . : <AES32> HDSPM_Dolby 73 * : . : x . : . : . : HDSPM_Midi0InterruptEnable 74 * : . :x . : . : . : HDSPM_Midi1InterruptEnable 75 * : . : x . : . : . : HDSPM_Midi2InterruptEnable 76 * : . x : . : . : . : <MADI> HDSPM_Midi3InterruptEnable 77 * : . x : . : . : . : <AES32> HDSPM_DS_DoubleWire 78 * : .x : . : . : . : <AES32> HDSPM_QS_DoubleWire 79 * : x. : . : . : . : <AES32> HDSPM_QS_QuadWire 80 * : . : . : . x : . : <AES32> HDSPM_Professional 81 * : x . : . : . : . : HDSPM_wclk_sel 82 * : . : . : . : . : 83 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte 84 * :||||.||||:||||.||||:||||.||||:||||.||||: 85 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number 86 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31 87 * :||||.||||:||||.||||:||||.||||:||||.||||: 88 * :8421.8421:8421.8421:8421.8421:8421.8421:hex digit 89 * 90 * 91 * 92 * AIO / RayDAT only 93 * 94 * ------------ HDSPM_WR_SETTINGS ---------- 95 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte 96 * :1098.7654:3210.9876:5432.1098:7654.3210: 97 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number 98 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31 99 * :||||.||||:||||.||||:||||.||||:||||.||||: 100 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit 101 * : . : . : . : . x: HDSPM_c0Master 1: Master, 0: Slave 102 * : . : . : . : . x : HDSPM_c0_SyncRef0 103 * : . : . : . : . x : HDSPM_c0_SyncRef1 104 * : . : . : . : .x : HDSPM_c0_SyncRef2 105 * : . : . : . : x. : HDSPM_c0_SyncRef3 106 * : . : . : . : 3.210 : HDSPM_c0_SyncRefMask: 107 * : . : . : . : . : RayDat: 0:WC, 1:AES, 2:SPDIF, 3..6: ADAT1..4, 108 * : . : . : . : . : 9:TCO, 10:SyncIn 109 * : . : . : . : . : AIO: 0:WC, 1:AES, 2: SPDIF, 3: ATAT, 110 * : . : . : . : . : 9:TCO, 10:SyncIn 111 * : . : . : . : . : 112 * : . : . : . : . : 113 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte 114 * :1098.7654:3210.9876:5432.1098:7654.3210: 115 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number 116 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31 117 * :||||.||||:||||.||||:||||.||||:||||.||||: 118 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit 119 * 120 */ 121 #include <linux/init.h> 122 #include <linux/delay.h> 123 #include <linux/interrupt.h> 124 #include <linux/module.h> 125 #include <linux/slab.h> 126 #include <linux/pci.h> 127 #include <linux/math64.h> 128 #include <linux/io.h> 129 #include <linux/nospec.h> 130 131 #include <sound/core.h> 132 #include <sound/control.h> 133 #include <sound/pcm.h> 134 #include <sound/pcm_params.h> 135 #include <sound/info.h> 136 #include <sound/asoundef.h> 137 #include <sound/rawmidi.h> 138 #include <sound/hwdep.h> 139 #include <sound/initval.h> 140 141 #include <sound/hdspm.h> 142 143 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 144 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 145 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ 146 147 module_param_array(index, int, NULL, 0444); 148 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface."); 149 150 module_param_array(id, charp, NULL, 0444); 151 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface."); 152 153 module_param_array(enable, bool, NULL, 0444); 154 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards."); 155 156 157 MODULE_AUTHOR 158 ( 159 "Winfried Ritsch <ritsch_AT_iem.at>, " 160 "Paul Davis <paul@linuxaudiosystems.com>, " 161 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, " 162 "Remy Bruno <remy.bruno@trinnov.com>, " 163 "Florian Faber <faberman@linuxproaudio.org>, " 164 "Adrian Knoth <adi@drcomp.erfurt.thur.de>" 165 ); 166 MODULE_DESCRIPTION("RME HDSPM"); 167 MODULE_LICENSE("GPL"); 168 169 /* --- Write registers. --- 170 These are defined as byte-offsets from the iobase value. */ 171 172 #define HDSPM_WR_SETTINGS 0 173 #define HDSPM_outputBufferAddress 32 174 #define HDSPM_inputBufferAddress 36 175 #define HDSPM_controlRegister 64 176 #define HDSPM_interruptConfirmation 96 177 #define HDSPM_control2Reg 256 /* not in specs ???????? */ 178 #define HDSPM_freqReg 256 /* for setting arbitrary clock values (DDS feature) */ 179 #define HDSPM_midiDataOut0 352 /* just believe in old code */ 180 #define HDSPM_midiDataOut1 356 181 #define HDSPM_eeprom_wr 384 /* for AES32 */ 182 183 /* DMA enable for 64 channels, only Bit 0 is relevant */ 184 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ 185 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ 186 187 /* 16 page addresses for each of the 64 channels DMA buffer in and out 188 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */ 189 #define HDSPM_pageAddressBufferOut 8192 190 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) 191 192 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ 193 194 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ 195 196 /* --- Read registers. --- 197 These are defined as byte-offsets from the iobase value */ 198 #define HDSPM_statusRegister 0 199 /*#define HDSPM_statusRegister2 96 */ 200 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at 201 * offset 192, for AES32 *and* MADI 202 * => need to check that offset 192 is working on MADI */ 203 #define HDSPM_statusRegister2 192 204 #define HDSPM_timecodeRegister 128 205 206 /* AIO, RayDAT */ 207 #define HDSPM_RD_STATUS_0 0 208 #define HDSPM_RD_STATUS_1 64 209 #define HDSPM_RD_STATUS_2 128 210 #define HDSPM_RD_STATUS_3 192 211 212 #define HDSPM_RD_TCO 256 213 #define HDSPM_RD_PLL_FREQ 512 214 #define HDSPM_WR_TCO 128 215 216 #define HDSPM_TCO1_TCO_lock 0x00000001 217 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002 218 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004 219 #define HDSPM_TCO1_LTC_Input_valid 0x00000008 220 #define HDSPM_TCO1_WCK_Input_valid 0x00000010 221 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020 222 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040 223 224 #define HDSPM_TCO1_set_TC 0x00000100 225 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200 226 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400 227 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800 228 229 #define HDSPM_TCO2_TC_run 0x00010000 230 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000 231 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000 232 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000 233 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000 234 #define HDSPM_TCO2_set_jam_sync 0x00200000 235 #define HDSPM_TCO2_set_flywheel 0x00400000 236 237 #define HDSPM_TCO2_set_01_4 0x01000000 238 #define HDSPM_TCO2_set_pull_down 0x02000000 239 #define HDSPM_TCO2_set_pull_up 0x04000000 240 #define HDSPM_TCO2_set_freq 0x08000000 241 #define HDSPM_TCO2_set_term_75R 0x10000000 242 #define HDSPM_TCO2_set_input_LSB 0x20000000 243 #define HDSPM_TCO2_set_input_MSB 0x40000000 244 #define HDSPM_TCO2_set_freq_from_app 0x80000000 245 246 247 #define HDSPM_midiDataOut0 352 248 #define HDSPM_midiDataOut1 356 249 #define HDSPM_midiDataOut2 368 250 251 #define HDSPM_midiDataIn0 360 252 #define HDSPM_midiDataIn1 364 253 #define HDSPM_midiDataIn2 372 254 #define HDSPM_midiDataIn3 376 255 256 /* status is data bytes in MIDI-FIFO (0-128) */ 257 #define HDSPM_midiStatusOut0 384 258 #define HDSPM_midiStatusOut1 388 259 #define HDSPM_midiStatusOut2 400 260 261 #define HDSPM_midiStatusIn0 392 262 #define HDSPM_midiStatusIn1 396 263 #define HDSPM_midiStatusIn2 404 264 #define HDSPM_midiStatusIn3 408 265 266 267 /* the meters are regular i/o-mapped registers, but offset 268 considerably from the rest. the peak registers are reset 269 when read; the least-significant 4 bits are full-scale counters; 270 the actual peak value is in the most-significant 24 bits. 271 */ 272 273 #define HDSPM_MADI_INPUT_PEAK 4096 274 #define HDSPM_MADI_PLAYBACK_PEAK 4352 275 #define HDSPM_MADI_OUTPUT_PEAK 4608 276 277 #define HDSPM_MADI_INPUT_RMS_L 6144 278 #define HDSPM_MADI_PLAYBACK_RMS_L 6400 279 #define HDSPM_MADI_OUTPUT_RMS_L 6656 280 281 #define HDSPM_MADI_INPUT_RMS_H 7168 282 #define HDSPM_MADI_PLAYBACK_RMS_H 7424 283 #define HDSPM_MADI_OUTPUT_RMS_H 7680 284 285 /* --- Control Register bits --------- */ 286 #define HDSPM_Start (1<<0) /* start engine */ 287 288 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ 289 #define HDSPM_Latency1 (1<<2) /* where n is defined */ 290 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ 291 292 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */ 293 #define HDSPM_c0Master 0x1 /* Master clock bit in settings 294 register [RayDAT, AIO] */ 295 296 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ 297 298 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ 299 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ 300 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 301 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */ 302 303 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ 304 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1, 305 56channelMODE=0 */ /* MADI ONLY*/ 306 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ 307 308 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode, 309 0=off, 1=on */ /* MADI ONLY */ 310 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ 311 312 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax 313 * -- MADI ONLY 314 */ 315 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */ 316 317 #define HDSPM_SyncRef2 (1<<13) 318 #define HDSPM_SyncRef3 (1<<25) 319 320 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ 321 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use 322 AES additional bits in 323 lower 5 Audiodatabits ??? */ 324 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ 325 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ 326 327 #define HDSPM_Midi0InterruptEnable 0x0400000 328 #define HDSPM_Midi1InterruptEnable 0x0800000 329 #define HDSPM_Midi2InterruptEnable 0x0200000 330 #define HDSPM_Midi3InterruptEnable 0x4000000 331 332 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ 333 #define HDSPe_FLOAT_FORMAT 0x2000000 334 335 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ 336 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ 337 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ 338 339 #define HDSPM_wclk_sel (1<<30) 340 341 /* additional control register bits for AIO*/ 342 #define HDSPM_c0_Wck48 0x20 /* also RayDAT */ 343 #define HDSPM_c0_Input0 0x1000 344 #define HDSPM_c0_Input1 0x2000 345 #define HDSPM_c0_Spdif_Opt 0x4000 346 #define HDSPM_c0_Pro 0x8000 347 #define HDSPM_c0_clr_tms 0x10000 348 #define HDSPM_c0_AEB1 0x20000 349 #define HDSPM_c0_AEB2 0x40000 350 #define HDSPM_c0_LineOut 0x80000 351 #define HDSPM_c0_AD_GAIN0 0x100000 352 #define HDSPM_c0_AD_GAIN1 0x200000 353 #define HDSPM_c0_DA_GAIN0 0x400000 354 #define HDSPM_c0_DA_GAIN1 0x800000 355 #define HDSPM_c0_PH_GAIN0 0x1000000 356 #define HDSPM_c0_PH_GAIN1 0x2000000 357 #define HDSPM_c0_Sym6db 0x4000000 358 359 360 /* --- bit helper defines */ 361 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) 362 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\ 363 HDSPM_DoubleSpeed|HDSPM_QuadSpeed) 364 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) 365 #define HDSPM_InputOptical 0 366 #define HDSPM_InputCoaxial (HDSPM_InputSelect0) 367 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\ 368 HDSPM_SyncRef2|HDSPM_SyncRef3) 369 370 #define HDSPM_c0_SyncRef0 0x2 371 #define HDSPM_c0_SyncRef1 0x4 372 #define HDSPM_c0_SyncRef2 0x8 373 #define HDSPM_c0_SyncRef3 0x10 374 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\ 375 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3) 376 377 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ 378 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ 379 #define HDSPM_SYNC_FROM_TCO 2 380 #define HDSPM_SYNC_FROM_SYNC_IN 3 381 382 #define HDSPM_Frequency32KHz HDSPM_Frequency0 383 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1 384 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) 385 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) 386 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) 387 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\ 388 HDSPM_Frequency0) 389 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) 390 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) 391 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\ 392 HDSPM_Frequency0) 393 394 395 /* Synccheck Status */ 396 #define HDSPM_SYNC_CHECK_NO_LOCK 0 397 #define HDSPM_SYNC_CHECK_LOCK 1 398 #define HDSPM_SYNC_CHECK_SYNC 2 399 400 /* AutoSync References - used by "autosync_ref" control switch */ 401 #define HDSPM_AUTOSYNC_FROM_WORD 0 402 #define HDSPM_AUTOSYNC_FROM_MADI 1 403 #define HDSPM_AUTOSYNC_FROM_TCO 2 404 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3 405 #define HDSPM_AUTOSYNC_FROM_NONE 4 406 407 /* Possible sources of MADI input */ 408 #define HDSPM_OPTICAL 0 /* optical */ 409 #define HDSPM_COAXIAL 1 /* BNC */ 410 411 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) 412 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1)) 413 414 #define hdspm_encode_in(x) (((x)&0x3)<<14) 415 #define hdspm_decode_in(x) (((x)>>14)&0x3) 416 417 /* --- control2 register bits --- */ 418 #define HDSPM_TMS (1<<0) 419 #define HDSPM_TCK (1<<1) 420 #define HDSPM_TDI (1<<2) 421 #define HDSPM_JTAG (1<<3) 422 #define HDSPM_PWDN (1<<4) 423 #define HDSPM_PROGRAM (1<<5) 424 #define HDSPM_CONFIG_MODE_0 (1<<6) 425 #define HDSPM_CONFIG_MODE_1 (1<<7) 426 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/ 427 #define HDSPM_BIGENDIAN_MODE (1<<9) 428 #define HDSPM_RD_MULTIPLE (1<<10) 429 430 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and 431 that do not conflict with specific bits for AES32 seem to be valid also 432 for the AES32 433 */ 434 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ 435 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ 436 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 437 * (like inp0) 438 */ 439 440 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ 441 #define HDSPM_madiSync (1<<18) /* MADI is in sync */ 442 443 #define HDSPM_tcoLockMadi 0x00000020 /* Optional TCO locked status for HDSPe MADI*/ 444 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/ 445 446 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */ 447 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */ 448 449 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 450 /* since 64byte accurate, last 6 bits are not used */ 451 452 453 454 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ 455 456 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ 457 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ 458 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ 459 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ 460 461 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with 462 * Interrupt 463 */ 464 #define HDSPM_tco_detect 0x08000000 465 #define HDSPM_tcoLockAes 0x20000000 /* Optional TCO locked status for HDSPe AES */ 466 467 #define HDSPM_s2_tco_detect 0x00000040 468 #define HDSPM_s2_AEBO_D 0x00000080 469 #define HDSPM_s2_AEBI_D 0x00000100 470 471 472 #define HDSPM_midi0IRQPending 0x40000000 473 #define HDSPM_midi1IRQPending 0x80000000 474 #define HDSPM_midi2IRQPending 0x20000000 475 #define HDSPM_midi2IRQPendingAES 0x00000020 476 #define HDSPM_midi3IRQPending 0x00200000 477 478 /* --- status bit helpers */ 479 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\ 480 HDSPM_madiFreq2|HDSPM_madiFreq3) 481 #define HDSPM_madiFreq32 (HDSPM_madiFreq0) 482 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1) 483 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) 484 #define HDSPM_madiFreq64 (HDSPM_madiFreq2) 485 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) 486 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) 487 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) 488 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3) 489 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) 490 491 /* Status2 Register bits */ /* MADI ONLY */ 492 493 #define HDSPM_version0 (1<<0) /* not really defined but I guess */ 494 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */ 495 #define HDSPM_version2 (1<<2) 496 497 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ 498 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ 499 500 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ 501 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ 502 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, 111=128 */ 503 #define HDSPM_wc_freq3 0x800 /* 1000=176.4, 1001=192 */ 504 505 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */ 506 #define HDSPM_SyncRef1 0x20000 507 508 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */ 509 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ 510 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ 511 512 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) 513 514 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\ 515 HDSPM_wc_freq3) 516 #define HDSPM_wcFreq32 (HDSPM_wc_freq0) 517 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1) 518 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) 519 #define HDSPM_wcFreq64 (HDSPM_wc_freq2) 520 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) 521 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) 522 #define HDSPM_wcFreq128 (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) 523 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3) 524 #define HDSPM_wcFreq192 (HDSPM_wc_freq0|HDSPM_wc_freq3) 525 526 #define HDSPM_status1_F_0 0x0400000 527 #define HDSPM_status1_F_1 0x0800000 528 #define HDSPM_status1_F_2 0x1000000 529 #define HDSPM_status1_F_3 0x2000000 530 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3) 531 532 533 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 534 HDSPM_SelSyncRef2) 535 #define HDSPM_SelSyncRef_WORD 0 536 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) 537 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1) 538 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1) 539 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 540 HDSPM_SelSyncRef2) 541 542 /* 543 For AES32, bits for status, status2 and timecode are different 544 */ 545 /* status */ 546 #define HDSPM_AES32_wcLock 0x0200000 547 #define HDSPM_AES32_wcSync 0x0100000 548 #define HDSPM_AES32_wcFreq_bit 22 549 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function 550 HDSPM_bit2freq */ 551 #define HDSPM_AES32_syncref_bit 16 552 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */ 553 554 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0 555 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1 556 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2 557 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3 558 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4 559 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5 560 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6 561 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7 562 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8 563 #define HDSPM_AES32_AUTOSYNC_FROM_TCO 9 564 #define HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN 10 565 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 11 566 567 /* status2 */ 568 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */ 569 #define HDSPM_LockAES 0x80 570 #define HDSPM_LockAES1 0x80 571 #define HDSPM_LockAES2 0x40 572 #define HDSPM_LockAES3 0x20 573 #define HDSPM_LockAES4 0x10 574 #define HDSPM_LockAES5 0x8 575 #define HDSPM_LockAES6 0x4 576 #define HDSPM_LockAES7 0x2 577 #define HDSPM_LockAES8 0x1 578 /* 579 Timecode 580 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on 581 AES i+1 582 bits 3210 583 0001 32kHz 584 0010 44.1kHz 585 0011 48kHz 586 0100 64kHz 587 0101 88.2kHz 588 0110 96kHz 589 0111 128kHz 590 1000 176.4kHz 591 1001 192kHz 592 NB: Timecode register doesn't seem to work on AES32 card revision 230 593 */ 594 595 /* Mixer Values */ 596 #define UNITY_GAIN 32768 /* = 65536/2 */ 597 #define MINUS_INFINITY_GAIN 0 598 599 /* Number of channels for different Speed Modes */ 600 #define MADI_SS_CHANNELS 64 601 #define MADI_DS_CHANNELS 32 602 #define MADI_QS_CHANNELS 16 603 604 #define RAYDAT_SS_CHANNELS 36 605 #define RAYDAT_DS_CHANNELS 20 606 #define RAYDAT_QS_CHANNELS 12 607 608 #define AIO_IN_SS_CHANNELS 14 609 #define AIO_IN_DS_CHANNELS 10 610 #define AIO_IN_QS_CHANNELS 8 611 #define AIO_OUT_SS_CHANNELS 16 612 #define AIO_OUT_DS_CHANNELS 12 613 #define AIO_OUT_QS_CHANNELS 10 614 615 #define AES32_CHANNELS 16 616 617 /* the size of a substream (1 mono data stream) */ 618 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) 619 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) 620 621 /* the size of the area we need to allocate for DMA transfers. the 622 size is the same regardless of the number of channels, and 623 also the latency to use. 624 for one direction !!! 625 */ 626 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) 627 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) 628 629 #define HDSPM_RAYDAT_REV 211 630 #define HDSPM_AIO_REV 212 631 #define HDSPM_MADIFACE_REV 213 632 633 /* speed factor modes */ 634 #define HDSPM_SPEED_SINGLE 0 635 #define HDSPM_SPEED_DOUBLE 1 636 #define HDSPM_SPEED_QUAD 2 637 638 /* names for speed modes */ 639 static const char * const hdspm_speed_names[] = { "single", "double", "quad" }; 640 641 static const char *const texts_autosync_aes_tco[] = { "Word Clock", 642 "AES1", "AES2", "AES3", "AES4", 643 "AES5", "AES6", "AES7", "AES8", 644 "TCO", "Sync In" 645 }; 646 static const char *const texts_autosync_aes[] = { "Word Clock", 647 "AES1", "AES2", "AES3", "AES4", 648 "AES5", "AES6", "AES7", "AES8", 649 "Sync In" 650 }; 651 static const char *const texts_autosync_madi_tco[] = { "Word Clock", 652 "MADI", "TCO", "Sync In" }; 653 static const char *const texts_autosync_madi[] = { "Word Clock", 654 "MADI", "Sync In" }; 655 656 static const char *const texts_autosync_raydat_tco[] = { 657 "Word Clock", 658 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 659 "AES", "SPDIF", "TCO", "Sync In" 660 }; 661 static const char *const texts_autosync_raydat[] = { 662 "Word Clock", 663 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 664 "AES", "SPDIF", "Sync In" 665 }; 666 static const char *const texts_autosync_aio_tco[] = { 667 "Word Clock", 668 "ADAT", "AES", "SPDIF", "TCO", "Sync In" 669 }; 670 static const char *const texts_autosync_aio[] = { "Word Clock", 671 "ADAT", "AES", "SPDIF", "Sync In" }; 672 673 static const char *const texts_freq[] = { 674 "No Lock", 675 "32 kHz", 676 "44.1 kHz", 677 "48 kHz", 678 "64 kHz", 679 "88.2 kHz", 680 "96 kHz", 681 "128 kHz", 682 "176.4 kHz", 683 "192 kHz" 684 }; 685 686 static const char * const texts_ports_madi[] = { 687 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6", 688 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12", 689 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18", 690 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24", 691 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30", 692 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36", 693 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42", 694 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48", 695 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54", 696 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60", 697 "MADI.61", "MADI.62", "MADI.63", "MADI.64", 698 }; 699 700 701 static const char * const texts_ports_raydat_ss[] = { 702 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6", 703 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 704 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2", 705 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8", 706 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6", 707 "ADAT4.7", "ADAT4.8", 708 "AES.L", "AES.R", 709 "SPDIF.L", "SPDIF.R" 710 }; 711 712 static const char * const texts_ports_raydat_ds[] = { 713 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", 714 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 715 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4", 716 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", 717 "AES.L", "AES.R", 718 "SPDIF.L", "SPDIF.R" 719 }; 720 721 static const char * const texts_ports_raydat_qs[] = { 722 "ADAT1.1", "ADAT1.2", 723 "ADAT2.1", "ADAT2.2", 724 "ADAT3.1", "ADAT3.2", 725 "ADAT4.1", "ADAT4.2", 726 "AES.L", "AES.R", 727 "SPDIF.L", "SPDIF.R" 728 }; 729 730 731 static const char * const texts_ports_aio_in_ss[] = { 732 "Analogue.L", "Analogue.R", 733 "AES.L", "AES.R", 734 "SPDIF.L", "SPDIF.R", 735 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 736 "ADAT.7", "ADAT.8", 737 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 738 }; 739 740 static const char * const texts_ports_aio_out_ss[] = { 741 "Analogue.L", "Analogue.R", 742 "AES.L", "AES.R", 743 "SPDIF.L", "SPDIF.R", 744 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 745 "ADAT.7", "ADAT.8", 746 "Phone.L", "Phone.R", 747 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 748 }; 749 750 static const char * const texts_ports_aio_in_ds[] = { 751 "Analogue.L", "Analogue.R", 752 "AES.L", "AES.R", 753 "SPDIF.L", "SPDIF.R", 754 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 755 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 756 }; 757 758 static const char * const texts_ports_aio_out_ds[] = { 759 "Analogue.L", "Analogue.R", 760 "AES.L", "AES.R", 761 "SPDIF.L", "SPDIF.R", 762 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 763 "Phone.L", "Phone.R", 764 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 765 }; 766 767 static const char * const texts_ports_aio_in_qs[] = { 768 "Analogue.L", "Analogue.R", 769 "AES.L", "AES.R", 770 "SPDIF.L", "SPDIF.R", 771 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 772 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 773 }; 774 775 static const char * const texts_ports_aio_out_qs[] = { 776 "Analogue.L", "Analogue.R", 777 "AES.L", "AES.R", 778 "SPDIF.L", "SPDIF.R", 779 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 780 "Phone.L", "Phone.R", 781 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 782 }; 783 784 static const char * const texts_ports_aes32[] = { 785 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7", 786 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14", 787 "AES.15", "AES.16" 788 }; 789 790 /* These tables map the ALSA channels 1..N to the channels that we 791 need to use in order to find the relevant channel buffer. RME 792 refers to this kind of mapping as between "the ADAT channel and 793 the DMA channel." We index it using the logical audio channel, 794 and the value is the DMA channel (i.e. channel buffer number) 795 where the data for that channel can be read/written from/to. 796 */ 797 798 static const char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = { 799 0, 1, 2, 3, 4, 5, 6, 7, 800 8, 9, 10, 11, 12, 13, 14, 15, 801 16, 17, 18, 19, 20, 21, 22, 23, 802 24, 25, 26, 27, 28, 29, 30, 31, 803 32, 33, 34, 35, 36, 37, 38, 39, 804 40, 41, 42, 43, 44, 45, 46, 47, 805 48, 49, 50, 51, 52, 53, 54, 55, 806 56, 57, 58, 59, 60, 61, 62, 63 807 }; 808 809 static const char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = { 810 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */ 811 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */ 812 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */ 813 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */ 814 0, 1, /* AES */ 815 2, 3, /* SPDIF */ 816 -1, -1, -1, -1, 817 -1, -1, -1, -1, -1, -1, -1, -1, 818 -1, -1, -1, -1, -1, -1, -1, -1, 819 -1, -1, -1, -1, -1, -1, -1, -1, 820 }; 821 822 static const char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = { 823 4, 5, 6, 7, /* ADAT 1 */ 824 8, 9, 10, 11, /* ADAT 2 */ 825 12, 13, 14, 15, /* ADAT 3 */ 826 16, 17, 18, 19, /* ADAT 4 */ 827 0, 1, /* AES */ 828 2, 3, /* SPDIF */ 829 -1, -1, -1, -1, 830 -1, -1, -1, -1, -1, -1, -1, -1, 831 -1, -1, -1, -1, -1, -1, -1, -1, 832 -1, -1, -1, -1, -1, -1, -1, -1, 833 -1, -1, -1, -1, -1, -1, -1, -1, 834 -1, -1, -1, -1, -1, -1, -1, -1, 835 }; 836 837 static const char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = { 838 4, 5, /* ADAT 1 */ 839 6, 7, /* ADAT 2 */ 840 8, 9, /* ADAT 3 */ 841 10, 11, /* ADAT 4 */ 842 0, 1, /* AES */ 843 2, 3, /* SPDIF */ 844 -1, -1, -1, -1, 845 -1, -1, -1, -1, -1, -1, -1, -1, 846 -1, -1, -1, -1, -1, -1, -1, -1, 847 -1, -1, -1, -1, -1, -1, -1, -1, 848 -1, -1, -1, -1, -1, -1, -1, -1, 849 -1, -1, -1, -1, -1, -1, -1, -1, 850 -1, -1, -1, -1, -1, -1, -1, -1, 851 }; 852 853 static const char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = { 854 0, 1, /* line in */ 855 8, 9, /* aes in, */ 856 10, 11, /* spdif in */ 857 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */ 858 2, 3, 4, 5, /* AEB */ 859 -1, -1, -1, -1, -1, -1, 860 -1, -1, -1, -1, -1, -1, -1, -1, 861 -1, -1, -1, -1, -1, -1, -1, -1, 862 -1, -1, -1, -1, -1, -1, -1, -1, 863 -1, -1, -1, -1, -1, -1, -1, -1, 864 -1, -1, -1, -1, -1, -1, -1, -1, 865 }; 866 867 static const char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = { 868 0, 1, /* line out */ 869 8, 9, /* aes out */ 870 10, 11, /* spdif out */ 871 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */ 872 6, 7, /* phone out */ 873 2, 3, 4, 5, /* AEB */ 874 -1, -1, -1, -1, 875 -1, -1, -1, -1, -1, -1, -1, -1, 876 -1, -1, -1, -1, -1, -1, -1, -1, 877 -1, -1, -1, -1, -1, -1, -1, -1, 878 -1, -1, -1, -1, -1, -1, -1, -1, 879 -1, -1, -1, -1, -1, -1, -1, -1, 880 }; 881 882 static const char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = { 883 0, 1, /* line in */ 884 8, 9, /* aes in */ 885 10, 11, /* spdif in */ 886 12, 14, 16, 18, /* adat in */ 887 2, 3, 4, 5, /* AEB */ 888 -1, -1, 889 -1, -1, -1, -1, -1, -1, -1, -1, 890 -1, -1, -1, -1, -1, -1, -1, -1, 891 -1, -1, -1, -1, -1, -1, -1, -1, 892 -1, -1, -1, -1, -1, -1, -1, -1, 893 -1, -1, -1, -1, -1, -1, -1, -1, 894 -1, -1, -1, -1, -1, -1, -1, -1 895 }; 896 897 static const char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = { 898 0, 1, /* line out */ 899 8, 9, /* aes out */ 900 10, 11, /* spdif out */ 901 12, 14, 16, 18, /* adat out */ 902 6, 7, /* phone out */ 903 2, 3, 4, 5, /* AEB */ 904 -1, -1, -1, -1, -1, -1, -1, -1, 905 -1, -1, -1, -1, -1, -1, -1, -1, 906 -1, -1, -1, -1, -1, -1, -1, -1, 907 -1, -1, -1, -1, -1, -1, -1, -1, 908 -1, -1, -1, -1, -1, -1, -1, -1, 909 -1, -1, -1, -1, -1, -1, -1, -1 910 }; 911 912 static const char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = { 913 0, 1, /* line in */ 914 8, 9, /* aes in */ 915 10, 11, /* spdif in */ 916 12, 16, /* adat in */ 917 2, 3, 4, 5, /* AEB */ 918 -1, -1, -1, -1, 919 -1, -1, -1, -1, -1, -1, -1, -1, 920 -1, -1, -1, -1, -1, -1, -1, -1, 921 -1, -1, -1, -1, -1, -1, -1, -1, 922 -1, -1, -1, -1, -1, -1, -1, -1, 923 -1, -1, -1, -1, -1, -1, -1, -1, 924 -1, -1, -1, -1, -1, -1, -1, -1 925 }; 926 927 static const char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = { 928 0, 1, /* line out */ 929 8, 9, /* aes out */ 930 10, 11, /* spdif out */ 931 12, 16, /* adat out */ 932 6, 7, /* phone out */ 933 2, 3, 4, 5, /* AEB */ 934 -1, -1, 935 -1, -1, -1, -1, -1, -1, -1, -1, 936 -1, -1, -1, -1, -1, -1, -1, -1, 937 -1, -1, -1, -1, -1, -1, -1, -1, 938 -1, -1, -1, -1, -1, -1, -1, -1, 939 -1, -1, -1, -1, -1, -1, -1, -1, 940 -1, -1, -1, -1, -1, -1, -1, -1 941 }; 942 943 static const char channel_map_aes32[HDSPM_MAX_CHANNELS] = { 944 0, 1, 2, 3, 4, 5, 6, 7, 945 8, 9, 10, 11, 12, 13, 14, 15, 946 -1, -1, -1, -1, -1, -1, -1, -1, 947 -1, -1, -1, -1, -1, -1, -1, -1, 948 -1, -1, -1, -1, -1, -1, -1, -1, 949 -1, -1, -1, -1, -1, -1, -1, -1, 950 -1, -1, -1, -1, -1, -1, -1, -1, 951 -1, -1, -1, -1, -1, -1, -1, -1 952 }; 953 954 struct hdspm_midi { 955 struct hdspm *hdspm; 956 int id; 957 struct snd_rawmidi *rmidi; 958 struct snd_rawmidi_substream *input; 959 struct snd_rawmidi_substream *output; 960 char istimer; /* timer in use */ 961 struct timer_list timer; 962 spinlock_t lock; 963 int pending; 964 int dataIn; 965 int statusIn; 966 int dataOut; 967 int statusOut; 968 int ie; 969 int irq; 970 }; 971 972 struct hdspm_tco { 973 int input; /* 0: LTC, 1:Video, 2: WC*/ 974 int framerate; /* 0=24, 1=25, 2=29.97, 3=29.97d, 4=30, 5=30d */ 975 int wordclock; /* 0=1:1, 1=44.1->48, 2=48->44.1 */ 976 int samplerate; /* 0=44.1, 1=48, 2= freq from app */ 977 int pull; /* 0=0, 1=+0.1%, 2=-0.1%, 3=+4%, 4=-4%*/ 978 int term; /* 0 = off, 1 = on */ 979 }; 980 981 struct hdspm { 982 spinlock_t lock; 983 /* only one playback and/or capture stream */ 984 struct snd_pcm_substream *capture_substream; 985 struct snd_pcm_substream *playback_substream; 986 987 char *card_name; /* for procinfo */ 988 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/ 989 990 uint8_t io_type; 991 992 int monitor_outs; /* set up monitoring outs init flag */ 993 994 u32 control_register; /* cached value */ 995 u32 control2_register; /* cached value */ 996 u32 settings_register; /* cached value for AIO / RayDat (sync reference, master/slave) */ 997 998 struct hdspm_midi midi[4]; 999 struct work_struct midi_work; 1000 1001 size_t period_bytes; 1002 unsigned char ss_in_channels; 1003 unsigned char ds_in_channels; 1004 unsigned char qs_in_channels; 1005 unsigned char ss_out_channels; 1006 unsigned char ds_out_channels; 1007 unsigned char qs_out_channels; 1008 1009 unsigned char max_channels_in; 1010 unsigned char max_channels_out; 1011 1012 const signed char *channel_map_in; 1013 const signed char *channel_map_out; 1014 1015 const signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs; 1016 const signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs; 1017 1018 const char * const *port_names_in; 1019 const char * const *port_names_out; 1020 1021 const char * const *port_names_in_ss; 1022 const char * const *port_names_in_ds; 1023 const char * const *port_names_in_qs; 1024 const char * const *port_names_out_ss; 1025 const char * const *port_names_out_ds; 1026 const char * const *port_names_out_qs; 1027 1028 unsigned char *playback_buffer; /* suitably aligned address */ 1029 unsigned char *capture_buffer; /* suitably aligned address */ 1030 1031 pid_t capture_pid; /* process id which uses capture */ 1032 pid_t playback_pid; /* process id which uses capture */ 1033 int running; /* running status */ 1034 1035 int last_external_sample_rate; /* samplerate mystic ... */ 1036 int last_internal_sample_rate; 1037 int system_sample_rate; 1038 1039 int dev; /* Hardware vars... */ 1040 int irq; 1041 unsigned long port; 1042 void __iomem *iobase; 1043 1044 int irq_count; /* for debug */ 1045 int midiPorts; 1046 1047 struct snd_card *card; /* one card */ 1048 struct snd_pcm *pcm; /* has one pcm */ 1049 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */ 1050 struct pci_dev *pci; /* and an pci info */ 1051 1052 /* Mixer vars */ 1053 /* fast alsa mixer */ 1054 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; 1055 /* but input to much, so not used */ 1056 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; 1057 /* full mixer accessible over mixer ioctl or hwdep-device */ 1058 struct hdspm_mixer *mixer; 1059 1060 struct hdspm_tco *tco; /* NULL if no TCO detected */ 1061 1062 const char *const *texts_autosync; 1063 int texts_autosync_items; 1064 1065 cycles_t last_interrupt; 1066 1067 unsigned int serial; 1068 1069 struct hdspm_peak_rms peak_rms; 1070 }; 1071 1072 1073 static const struct pci_device_id snd_hdspm_ids[] = { 1074 { PCI_DEVICE(PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI) }, 1075 { PCI_DEVICE(0x1d18, 0x3fc6) }, /* RME HDSPe AIO PCI express audio */ 1076 {0,} 1077 }; 1078 1079 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids); 1080 1081 /* prototypes */ 1082 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 1083 struct hdspm *hdspm); 1084 static int snd_hdspm_create_pcm(struct snd_card *card, 1085 struct hdspm *hdspm); 1086 1087 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm); 1088 static inline int hdspm_get_pll_freq(struct hdspm *hdspm); 1089 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm); 1090 static int hdspm_autosync_ref(struct hdspm *hdspm); 1091 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out); 1092 static int snd_hdspm_set_defaults(struct hdspm *hdspm); 1093 static int hdspm_system_clock_mode(struct hdspm *hdspm); 1094 static void hdspm_set_channel_dma_addr(struct hdspm *hdspm, 1095 struct snd_pcm_substream *substream, 1096 unsigned int reg, int channels); 1097 1098 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx); 1099 static int hdspm_wc_sync_check(struct hdspm *hdspm); 1100 static int hdspm_tco_sync_check(struct hdspm *hdspm); 1101 static int hdspm_sync_in_sync_check(struct hdspm *hdspm); 1102 1103 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index); 1104 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm); 1105 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm); 1106 1107 1108 1109 static inline int HDSPM_bit2freq(int n) 1110 { 1111 static const int bit2freq_tab[] = { 1112 0, 32000, 44100, 48000, 64000, 88200, 1113 96000, 128000, 176400, 192000 }; 1114 if (n < 1 || n > 9) 1115 return 0; 1116 return bit2freq_tab[n]; 1117 } 1118 1119 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm) 1120 { 1121 return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type)); 1122 } 1123 1124 1125 /* Write/read to/from HDSPM with Adresses in Bytes 1126 not words but only 32Bit writes are allowed */ 1127 1128 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, 1129 unsigned int val) 1130 { 1131 writel(val, hdspm->iobase + reg); 1132 } 1133 1134 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) 1135 { 1136 return readl(hdspm->iobase + reg); 1137 } 1138 1139 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader 1140 mixer is write only on hardware so we have to cache him for read 1141 each fader is a u32, but uses only the first 16 bit */ 1142 1143 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan, 1144 unsigned int in) 1145 { 1146 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1147 return 0; 1148 1149 return hdspm->mixer->ch[chan].in[in]; 1150 } 1151 1152 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan, 1153 unsigned int pb) 1154 { 1155 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1156 return 0; 1157 return hdspm->mixer->ch[chan].pb[pb]; 1158 } 1159 1160 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan, 1161 unsigned int in, unsigned short data) 1162 { 1163 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1164 return -1; 1165 1166 hdspm_write(hdspm, 1167 HDSPM_MADI_mixerBase + 1168 ((in + 128 * chan) * sizeof(u32)), 1169 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF)); 1170 return 0; 1171 } 1172 1173 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan, 1174 unsigned int pb, unsigned short data) 1175 { 1176 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1177 return -1; 1178 1179 hdspm_write(hdspm, 1180 HDSPM_MADI_mixerBase + 1181 ((64 + pb + 128 * chan) * sizeof(u32)), 1182 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF)); 1183 return 0; 1184 } 1185 1186 1187 /* enable DMA for specific channels, now available for DSP-MADI */ 1188 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v) 1189 { 1190 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v); 1191 } 1192 1193 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v) 1194 { 1195 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v); 1196 } 1197 1198 /* check if same process is writing and reading */ 1199 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm) 1200 { 1201 guard(spinlock_irqsave)(&hdspm->lock); 1202 if ((hdspm->playback_pid != hdspm->capture_pid) && 1203 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) 1204 return 0; 1205 return 1; 1206 } 1207 1208 /* round arbitrary sample rates to commonly known rates */ 1209 static int hdspm_round_frequency(int rate) 1210 { 1211 if (rate < 38050) 1212 return 32000; 1213 if (rate < 46008) 1214 return 44100; 1215 else 1216 return 48000; 1217 } 1218 1219 /* QS and DS rates normally can not be detected 1220 * automatically by the card. Only exception is MADI 1221 * in 96k frame mode. 1222 * 1223 * So if we read SS values (32 .. 48k), check for 1224 * user-provided DS/QS bits in the control register 1225 * and multiply the base frequency accordingly. 1226 */ 1227 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate) 1228 { 1229 if (rate <= 48000) { 1230 if (hdspm->control_register & HDSPM_QuadSpeed) 1231 return rate * 4; 1232 else if (hdspm->control_register & 1233 HDSPM_DoubleSpeed) 1234 return rate * 2; 1235 } 1236 return rate; 1237 } 1238 1239 /* check for external sample rate, returns the sample rate in Hz*/ 1240 static int hdspm_external_sample_rate(struct hdspm *hdspm) 1241 { 1242 unsigned int status, status2; 1243 int syncref, rate = 0, rate_bits; 1244 1245 switch (hdspm->io_type) { 1246 case AES32: 1247 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1248 status = hdspm_read(hdspm, HDSPM_statusRegister); 1249 1250 syncref = hdspm_autosync_ref(hdspm); 1251 switch (syncref) { 1252 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 1253 /* Check WC sync and get sample rate */ 1254 if (hdspm_wc_sync_check(hdspm)) 1255 return HDSPM_bit2freq(hdspm_get_wc_sample_rate(hdspm)); 1256 break; 1257 1258 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 1259 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 1260 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 1261 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 1262 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 1263 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 1264 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 1265 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 1266 /* Check AES sync and get sample rate */ 1267 if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)) 1268 return HDSPM_bit2freq(hdspm_get_aes_sample_rate(hdspm, 1269 syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)); 1270 break; 1271 1272 1273 case HDSPM_AES32_AUTOSYNC_FROM_TCO: 1274 /* Check TCO sync and get sample rate */ 1275 if (hdspm_tco_sync_check(hdspm)) 1276 return HDSPM_bit2freq(hdspm_get_tco_sample_rate(hdspm)); 1277 break; 1278 default: 1279 return 0; 1280 } /* end switch(syncref) */ 1281 break; 1282 1283 case MADIface: 1284 status = hdspm_read(hdspm, HDSPM_statusRegister); 1285 1286 if (!(status & HDSPM_madiLock)) { 1287 rate = 0; /* no lock */ 1288 } else { 1289 switch (status & (HDSPM_status1_freqMask)) { 1290 case HDSPM_status1_F_0*1: 1291 rate = 32000; break; 1292 case HDSPM_status1_F_0*2: 1293 rate = 44100; break; 1294 case HDSPM_status1_F_0*3: 1295 rate = 48000; break; 1296 case HDSPM_status1_F_0*4: 1297 rate = 64000; break; 1298 case HDSPM_status1_F_0*5: 1299 rate = 88200; break; 1300 case HDSPM_status1_F_0*6: 1301 rate = 96000; break; 1302 case HDSPM_status1_F_0*7: 1303 rate = 128000; break; 1304 case HDSPM_status1_F_0*8: 1305 rate = 176400; break; 1306 case HDSPM_status1_F_0*9: 1307 rate = 192000; break; 1308 default: 1309 rate = 0; break; 1310 } 1311 } 1312 1313 break; 1314 1315 case MADI: 1316 case AIO: 1317 case RayDAT: 1318 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1319 status = hdspm_read(hdspm, HDSPM_statusRegister); 1320 rate = 0; 1321 1322 /* if wordclock has synced freq and wordclock is valid */ 1323 if ((status2 & HDSPM_wcLock) != 0 && 1324 (status2 & HDSPM_SelSyncRef0) == 0) { 1325 1326 rate_bits = status2 & HDSPM_wcFreqMask; 1327 1328 1329 switch (rate_bits) { 1330 case HDSPM_wcFreq32: 1331 rate = 32000; 1332 break; 1333 case HDSPM_wcFreq44_1: 1334 rate = 44100; 1335 break; 1336 case HDSPM_wcFreq48: 1337 rate = 48000; 1338 break; 1339 case HDSPM_wcFreq64: 1340 rate = 64000; 1341 break; 1342 case HDSPM_wcFreq88_2: 1343 rate = 88200; 1344 break; 1345 case HDSPM_wcFreq96: 1346 rate = 96000; 1347 break; 1348 case HDSPM_wcFreq128: 1349 rate = 128000; 1350 break; 1351 case HDSPM_wcFreq176_4: 1352 rate = 176400; 1353 break; 1354 case HDSPM_wcFreq192: 1355 rate = 192000; 1356 break; 1357 default: 1358 rate = 0; 1359 break; 1360 } 1361 } 1362 1363 /* if rate detected and Syncref is Word than have it, 1364 * word has priority to MADI 1365 */ 1366 if (rate != 0 && 1367 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD) 1368 return hdspm_rate_multiplier(hdspm, rate); 1369 1370 /* maybe a madi input (which is taken if sel sync is madi) */ 1371 if (status & HDSPM_madiLock) { 1372 rate_bits = status & HDSPM_madiFreqMask; 1373 1374 switch (rate_bits) { 1375 case HDSPM_madiFreq32: 1376 rate = 32000; 1377 break; 1378 case HDSPM_madiFreq44_1: 1379 rate = 44100; 1380 break; 1381 case HDSPM_madiFreq48: 1382 rate = 48000; 1383 break; 1384 case HDSPM_madiFreq64: 1385 rate = 64000; 1386 break; 1387 case HDSPM_madiFreq88_2: 1388 rate = 88200; 1389 break; 1390 case HDSPM_madiFreq96: 1391 rate = 96000; 1392 break; 1393 case HDSPM_madiFreq128: 1394 rate = 128000; 1395 break; 1396 case HDSPM_madiFreq176_4: 1397 rate = 176400; 1398 break; 1399 case HDSPM_madiFreq192: 1400 rate = 192000; 1401 break; 1402 default: 1403 rate = 0; 1404 break; 1405 } 1406 1407 } /* endif HDSPM_madiLock */ 1408 1409 /* check sample rate from TCO or SYNC_IN */ 1410 { 1411 bool is_valid_input = 0; 1412 bool has_sync = 0; 1413 1414 syncref = hdspm_autosync_ref(hdspm); 1415 if (HDSPM_AUTOSYNC_FROM_TCO == syncref) { 1416 is_valid_input = 1; 1417 has_sync = (HDSPM_SYNC_CHECK_SYNC == 1418 hdspm_tco_sync_check(hdspm)); 1419 } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) { 1420 is_valid_input = 1; 1421 has_sync = (HDSPM_SYNC_CHECK_SYNC == 1422 hdspm_sync_in_sync_check(hdspm)); 1423 } 1424 1425 if (is_valid_input && has_sync) { 1426 rate = hdspm_round_frequency( 1427 hdspm_get_pll_freq(hdspm)); 1428 } 1429 } 1430 1431 rate = hdspm_rate_multiplier(hdspm, rate); 1432 1433 break; 1434 } 1435 1436 return rate; 1437 } 1438 1439 /* return latency in samples per period */ 1440 static int hdspm_get_latency(struct hdspm *hdspm) 1441 { 1442 int n; 1443 1444 n = hdspm_decode_latency(hdspm->control_register); 1445 1446 /* Special case for new RME cards with 32 samples period size. 1447 * The three latency bits in the control register 1448 * (HDSP_LatencyMask) encode latency values of 64 samples as 1449 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7 1450 * denotes 8192 samples, but on new cards like RayDAT or AIO, 1451 * it corresponds to 32 samples. 1452 */ 1453 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type)) 1454 n = -1; 1455 1456 return 1 << (n + 6); 1457 } 1458 1459 /* Latency function */ 1460 static inline void hdspm_compute_period_size(struct hdspm *hdspm) 1461 { 1462 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm); 1463 } 1464 1465 1466 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm) 1467 { 1468 int position; 1469 1470 position = hdspm_read(hdspm, HDSPM_statusRegister); 1471 1472 switch (hdspm->io_type) { 1473 case RayDAT: 1474 case AIO: 1475 position &= HDSPM_BufferPositionMask; 1476 position /= 4; /* Bytes per sample */ 1477 break; 1478 default: 1479 position = (position & HDSPM_BufferID) ? 1480 (hdspm->period_bytes / 4) : 0; 1481 } 1482 1483 return position; 1484 } 1485 1486 1487 static inline void hdspm_start_audio(struct hdspm * s) 1488 { 1489 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); 1490 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1491 } 1492 1493 static inline void hdspm_stop_audio(struct hdspm * s) 1494 { 1495 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); 1496 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1497 } 1498 1499 /* should I silence all or only opened ones ? doit all for first even is 4MB*/ 1500 static void hdspm_silence_playback(struct hdspm *hdspm) 1501 { 1502 int i; 1503 int n = hdspm->period_bytes; 1504 void *buf = hdspm->playback_buffer; 1505 1506 if (!buf) 1507 return; 1508 1509 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 1510 memset(buf, 0, n); 1511 buf += HDSPM_CHANNEL_BUFFER_BYTES; 1512 } 1513 } 1514 1515 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames) 1516 { 1517 int n; 1518 1519 guard(spinlock_irq)(&s->lock); 1520 1521 if (32 == frames) { 1522 /* Special case for new RME cards like RayDAT/AIO which 1523 * support period sizes of 32 samples. Since latency is 1524 * encoded in the three bits of HDSP_LatencyMask, we can only 1525 * have values from 0 .. 7. While 0 still means 64 samples and 1526 * 6 represents 4096 samples on all cards, 7 represents 8192 1527 * on older cards and 32 samples on new cards. 1528 * 1529 * In other words, period size in samples is calculated by 1530 * 2^(n+6) with n ranging from 0 .. 7. 1531 */ 1532 n = 7; 1533 } else { 1534 frames >>= 7; 1535 n = 0; 1536 while (frames) { 1537 n++; 1538 frames >>= 1; 1539 } 1540 } 1541 1542 s->control_register &= ~HDSPM_LatencyMask; 1543 s->control_register |= hdspm_encode_latency(n); 1544 1545 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1546 1547 hdspm_compute_period_size(s); 1548 1549 return 0; 1550 } 1551 1552 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period) 1553 { 1554 u64 freq_const; 1555 1556 if (period == 0) 1557 return 0; 1558 1559 switch (hdspm->io_type) { 1560 case MADI: 1561 case AES32: 1562 freq_const = 110069313433624ULL; 1563 break; 1564 case RayDAT: 1565 case AIO: 1566 freq_const = 104857600000000ULL; 1567 break; 1568 case MADIface: 1569 freq_const = 131072000000000ULL; 1570 break; 1571 default: 1572 snd_BUG(); 1573 return 0; 1574 } 1575 1576 return div_u64(freq_const, period); 1577 } 1578 1579 1580 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) 1581 { 1582 u64 n; 1583 1584 if (snd_BUG_ON(rate <= 0)) 1585 return; 1586 1587 if (rate >= 112000) 1588 rate /= 4; 1589 else if (rate >= 56000) 1590 rate /= 2; 1591 1592 switch (hdspm->io_type) { 1593 case MADIface: 1594 n = 131072000000000ULL; /* 125 MHz */ 1595 break; 1596 case MADI: 1597 case AES32: 1598 n = 110069313433624ULL; /* 105 MHz */ 1599 break; 1600 case RayDAT: 1601 case AIO: 1602 n = 104857600000000ULL; /* 100 MHz */ 1603 break; 1604 default: 1605 snd_BUG(); 1606 return; 1607 } 1608 1609 n = div_u64(n, rate); 1610 /* n should be less than 2^32 for being written to FREQ register */ 1611 snd_BUG_ON(n >> 32); 1612 hdspm_write(hdspm, HDSPM_freqReg, (u32)n); 1613 } 1614 1615 /* dummy set rate lets see what happens */ 1616 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) 1617 { 1618 int current_rate; 1619 int rate_bits; 1620 int not_set = 0; 1621 int current_speed, target_speed; 1622 1623 /* ASSUMPTION: hdspm->lock is either set, or there is no need for 1624 it (e.g. during module initialization). 1625 */ 1626 1627 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { 1628 1629 /* SLAVE --- */ 1630 if (called_internally) { 1631 1632 /* request from ctl or card initialization 1633 just make a warning an remember setting 1634 for future master mode switching */ 1635 1636 dev_warn(hdspm->card->dev, 1637 "Warning: device is not running as a clock master.\n"); 1638 not_set = 1; 1639 } else { 1640 1641 /* hw_param request while in AutoSync mode */ 1642 int external_freq = 1643 hdspm_external_sample_rate(hdspm); 1644 1645 if (hdspm_autosync_ref(hdspm) == 1646 HDSPM_AUTOSYNC_FROM_NONE) { 1647 1648 dev_warn(hdspm->card->dev, 1649 "Detected no External Sync\n"); 1650 not_set = 1; 1651 1652 } else if (rate != external_freq) { 1653 1654 dev_warn(hdspm->card->dev, 1655 "Warning: No AutoSync source for requested rate\n"); 1656 not_set = 1; 1657 } 1658 } 1659 } 1660 1661 current_rate = hdspm->system_sample_rate; 1662 1663 /* Changing between Singe, Double and Quad speed is not 1664 allowed if any substreams are open. This is because such a change 1665 causes a shift in the location of the DMA buffers and a reduction 1666 in the number of available buffers. 1667 1668 Note that a similar but essentially insoluble problem exists for 1669 externally-driven rate changes. All we can do is to flag rate 1670 changes in the read/write routines. 1671 */ 1672 1673 if (current_rate <= 48000) 1674 current_speed = HDSPM_SPEED_SINGLE; 1675 else if (current_rate <= 96000) 1676 current_speed = HDSPM_SPEED_DOUBLE; 1677 else 1678 current_speed = HDSPM_SPEED_QUAD; 1679 1680 if (rate <= 48000) 1681 target_speed = HDSPM_SPEED_SINGLE; 1682 else if (rate <= 96000) 1683 target_speed = HDSPM_SPEED_DOUBLE; 1684 else 1685 target_speed = HDSPM_SPEED_QUAD; 1686 1687 switch (rate) { 1688 case 32000: 1689 rate_bits = HDSPM_Frequency32KHz; 1690 break; 1691 case 44100: 1692 rate_bits = HDSPM_Frequency44_1KHz; 1693 break; 1694 case 48000: 1695 rate_bits = HDSPM_Frequency48KHz; 1696 break; 1697 case 64000: 1698 rate_bits = HDSPM_Frequency64KHz; 1699 break; 1700 case 88200: 1701 rate_bits = HDSPM_Frequency88_2KHz; 1702 break; 1703 case 96000: 1704 rate_bits = HDSPM_Frequency96KHz; 1705 break; 1706 case 128000: 1707 rate_bits = HDSPM_Frequency128KHz; 1708 break; 1709 case 176400: 1710 rate_bits = HDSPM_Frequency176_4KHz; 1711 break; 1712 case 192000: 1713 rate_bits = HDSPM_Frequency192KHz; 1714 break; 1715 default: 1716 return -EINVAL; 1717 } 1718 1719 if (current_speed != target_speed 1720 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) { 1721 dev_err(hdspm->card->dev, 1722 "cannot change from %s speed to %s speed mode (capture PID = %d, playback PID = %d)\n", 1723 hdspm_speed_names[current_speed], 1724 hdspm_speed_names[target_speed], 1725 hdspm->capture_pid, hdspm->playback_pid); 1726 return -EBUSY; 1727 } 1728 1729 hdspm->control_register &= ~HDSPM_FrequencyMask; 1730 hdspm->control_register |= rate_bits; 1731 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1732 1733 /* For AES32, need to set DDS value in FREQ register 1734 For MADI, also apparently */ 1735 hdspm_set_dds_value(hdspm, rate); 1736 1737 if (AES32 == hdspm->io_type && rate != current_rate) 1738 hdspm_write(hdspm, HDSPM_eeprom_wr, 0); 1739 1740 hdspm->system_sample_rate = rate; 1741 1742 if (rate <= 48000) { 1743 hdspm->channel_map_in = hdspm->channel_map_in_ss; 1744 hdspm->channel_map_out = hdspm->channel_map_out_ss; 1745 hdspm->max_channels_in = hdspm->ss_in_channels; 1746 hdspm->max_channels_out = hdspm->ss_out_channels; 1747 hdspm->port_names_in = hdspm->port_names_in_ss; 1748 hdspm->port_names_out = hdspm->port_names_out_ss; 1749 } else if (rate <= 96000) { 1750 hdspm->channel_map_in = hdspm->channel_map_in_ds; 1751 hdspm->channel_map_out = hdspm->channel_map_out_ds; 1752 hdspm->max_channels_in = hdspm->ds_in_channels; 1753 hdspm->max_channels_out = hdspm->ds_out_channels; 1754 hdspm->port_names_in = hdspm->port_names_in_ds; 1755 hdspm->port_names_out = hdspm->port_names_out_ds; 1756 } else { 1757 hdspm->channel_map_in = hdspm->channel_map_in_qs; 1758 hdspm->channel_map_out = hdspm->channel_map_out_qs; 1759 hdspm->max_channels_in = hdspm->qs_in_channels; 1760 hdspm->max_channels_out = hdspm->qs_out_channels; 1761 hdspm->port_names_in = hdspm->port_names_in_qs; 1762 hdspm->port_names_out = hdspm->port_names_out_qs; 1763 } 1764 1765 if (not_set != 0) 1766 return -1; 1767 1768 return 0; 1769 } 1770 1771 /* mainly for init to 0 on load */ 1772 static void all_in_all_mixer(struct hdspm * hdspm, int sgain) 1773 { 1774 int i, j; 1775 unsigned int gain; 1776 1777 if (sgain > UNITY_GAIN) 1778 gain = UNITY_GAIN; 1779 else if (sgain < 0) 1780 gain = 0; 1781 else 1782 gain = sgain; 1783 1784 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) 1785 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) { 1786 hdspm_write_in_gain(hdspm, i, j, gain); 1787 hdspm_write_pb_gain(hdspm, i, j, gain); 1788 } 1789 } 1790 1791 /*---------------------------------------------------------------------------- 1792 MIDI 1793 ----------------------------------------------------------------------------*/ 1794 1795 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, 1796 int id) 1797 { 1798 /* the hardware already does the relevant bit-mask with 0xff */ 1799 return hdspm_read(hdspm, hdspm->midi[id].dataIn); 1800 } 1801 1802 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, 1803 int val) 1804 { 1805 /* the hardware already does the relevant bit-mask with 0xff */ 1806 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val); 1807 } 1808 1809 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id) 1810 { 1811 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF; 1812 } 1813 1814 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id) 1815 { 1816 int fifo_bytes_used; 1817 1818 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF; 1819 1820 if (fifo_bytes_used < 128) 1821 return 128 - fifo_bytes_used; 1822 else 1823 return 0; 1824 } 1825 1826 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id) 1827 { 1828 int count = 256; 1829 1830 while (snd_hdspm_midi_input_available(hdspm, id) && --count) 1831 snd_hdspm_midi_read_byte(hdspm, id); 1832 } 1833 1834 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi) 1835 { 1836 int n_pending; 1837 int to_write; 1838 int i; 1839 unsigned char buf[128]; 1840 1841 /* Output is not interrupt driven */ 1842 1843 guard(spinlock_irqsave)(&hmidi->lock); 1844 if (hmidi->output && 1845 !snd_rawmidi_transmit_empty (hmidi->output)) { 1846 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, 1847 hmidi->id); 1848 if (n_pending > 0) { 1849 if (n_pending > (int)sizeof (buf)) 1850 n_pending = sizeof (buf); 1851 1852 to_write = snd_rawmidi_transmit (hmidi->output, buf, 1853 n_pending); 1854 if (to_write > 0) { 1855 for (i = 0; i < to_write; ++i) 1856 snd_hdspm_midi_write_byte (hmidi->hdspm, 1857 hmidi->id, 1858 buf[i]); 1859 } 1860 } 1861 } 1862 return 0; 1863 } 1864 1865 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi) 1866 { 1867 unsigned char buf[128]; /* this buffer is designed to match the MIDI 1868 * input FIFO size 1869 */ 1870 int n_pending; 1871 int i; 1872 1873 scoped_guard(spinlock_irqsave, &hmidi->lock) { 1874 n_pending = snd_hdspm_midi_input_available(hmidi->hdspm, hmidi->id); 1875 if (n_pending > 0) { 1876 if (hmidi->input) { 1877 if (n_pending > (int)sizeof(buf)) 1878 n_pending = sizeof(buf); 1879 for (i = 0; i < n_pending; ++i) 1880 buf[i] = snd_hdspm_midi_read_byte(hmidi->hdspm, 1881 hmidi->id); 1882 if (n_pending) 1883 snd_rawmidi_receive(hmidi->input, buf, 1884 n_pending); 1885 } else { 1886 /* flush the MIDI input FIFO */ 1887 while (n_pending--) 1888 snd_hdspm_midi_read_byte(hmidi->hdspm, 1889 hmidi->id); 1890 } 1891 } 1892 hmidi->pending = 0; 1893 } 1894 1895 scoped_guard(spinlock_irqsave, &hmidi->hdspm->lock) { 1896 hmidi->hdspm->control_register |= hmidi->ie; 1897 hdspm_write(hmidi->hdspm, HDSPM_controlRegister, 1898 hmidi->hdspm->control_register); 1899 } 1900 1901 return snd_hdspm_midi_output_write (hmidi); 1902 } 1903 1904 static void 1905 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1906 { 1907 struct hdspm *hdspm; 1908 struct hdspm_midi *hmidi; 1909 1910 hmidi = substream->rmidi->private_data; 1911 hdspm = hmidi->hdspm; 1912 1913 guard(spinlock_irqsave)(&hdspm->lock); 1914 if (up) { 1915 if (!(hdspm->control_register & hmidi->ie)) { 1916 snd_hdspm_flush_midi_input (hdspm, hmidi->id); 1917 hdspm->control_register |= hmidi->ie; 1918 } 1919 } else { 1920 hdspm->control_register &= ~hmidi->ie; 1921 } 1922 1923 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1924 } 1925 1926 static void snd_hdspm_midi_output_timer(struct timer_list *t) 1927 { 1928 struct hdspm_midi *hmidi = timer_container_of(hmidi, t, timer); 1929 1930 snd_hdspm_midi_output_write(hmidi); 1931 guard(spinlock_irqsave)(&hmidi->lock); 1932 1933 /* this does not bump hmidi->istimer, because the 1934 kernel automatically removed the timer when it 1935 expired, and we are now adding it back, thus 1936 leaving istimer wherever it was set before. 1937 */ 1938 1939 if (hmidi->istimer) 1940 mod_timer(&hmidi->timer, 1 + jiffies); 1941 } 1942 1943 static void 1944 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1945 { 1946 struct hdspm_midi *hmidi; 1947 1948 hmidi = substream->rmidi->private_data; 1949 scoped_guard(spinlock_irqsave, &hmidi->lock) { 1950 if (up) { 1951 if (!hmidi->istimer) { 1952 timer_setup(&hmidi->timer, 1953 snd_hdspm_midi_output_timer, 0); 1954 mod_timer(&hmidi->timer, 1 + jiffies); 1955 hmidi->istimer++; 1956 } 1957 } else { 1958 if (hmidi->istimer && --hmidi->istimer <= 0) 1959 timer_delete(&hmidi->timer); 1960 } 1961 } 1962 if (up) 1963 snd_hdspm_midi_output_write(hmidi); 1964 } 1965 1966 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream) 1967 { 1968 struct hdspm_midi *hmidi; 1969 1970 hmidi = substream->rmidi->private_data; 1971 guard(spinlock_irq)(&hmidi->lock); 1972 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id); 1973 hmidi->input = substream; 1974 1975 return 0; 1976 } 1977 1978 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream) 1979 { 1980 struct hdspm_midi *hmidi; 1981 1982 hmidi = substream->rmidi->private_data; 1983 guard(spinlock_irq)(&hmidi->lock); 1984 hmidi->output = substream; 1985 1986 return 0; 1987 } 1988 1989 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream) 1990 { 1991 struct hdspm_midi *hmidi; 1992 1993 snd_hdspm_midi_input_trigger (substream, 0); 1994 1995 hmidi = substream->rmidi->private_data; 1996 guard(spinlock_irq)(&hmidi->lock); 1997 hmidi->input = NULL; 1998 1999 return 0; 2000 } 2001 2002 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream) 2003 { 2004 struct hdspm_midi *hmidi; 2005 2006 snd_hdspm_midi_output_trigger (substream, 0); 2007 2008 hmidi = substream->rmidi->private_data; 2009 guard(spinlock_irq)(&hmidi->lock); 2010 hmidi->output = NULL; 2011 2012 return 0; 2013 } 2014 2015 static const struct snd_rawmidi_ops snd_hdspm_midi_output = 2016 { 2017 .open = snd_hdspm_midi_output_open, 2018 .close = snd_hdspm_midi_output_close, 2019 .trigger = snd_hdspm_midi_output_trigger, 2020 }; 2021 2022 static const struct snd_rawmidi_ops snd_hdspm_midi_input = 2023 { 2024 .open = snd_hdspm_midi_input_open, 2025 .close = snd_hdspm_midi_input_close, 2026 .trigger = snd_hdspm_midi_input_trigger, 2027 }; 2028 2029 static int snd_hdspm_create_midi(struct snd_card *card, 2030 struct hdspm *hdspm, int id) 2031 { 2032 int err; 2033 char buf[64]; 2034 2035 hdspm->midi[id].id = id; 2036 hdspm->midi[id].hdspm = hdspm; 2037 spin_lock_init (&hdspm->midi[id].lock); 2038 2039 if (0 == id) { 2040 if (MADIface == hdspm->io_type) { 2041 /* MIDI-over-MADI on HDSPe MADIface */ 2042 hdspm->midi[0].dataIn = HDSPM_midiDataIn2; 2043 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2; 2044 hdspm->midi[0].dataOut = HDSPM_midiDataOut2; 2045 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2; 2046 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable; 2047 hdspm->midi[0].irq = HDSPM_midi2IRQPending; 2048 } else { 2049 hdspm->midi[0].dataIn = HDSPM_midiDataIn0; 2050 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0; 2051 hdspm->midi[0].dataOut = HDSPM_midiDataOut0; 2052 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0; 2053 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable; 2054 hdspm->midi[0].irq = HDSPM_midi0IRQPending; 2055 } 2056 } else if (1 == id) { 2057 hdspm->midi[1].dataIn = HDSPM_midiDataIn1; 2058 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1; 2059 hdspm->midi[1].dataOut = HDSPM_midiDataOut1; 2060 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1; 2061 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable; 2062 hdspm->midi[1].irq = HDSPM_midi1IRQPending; 2063 } else if ((2 == id) && (MADI == hdspm->io_type)) { 2064 /* MIDI-over-MADI on HDSPe MADI */ 2065 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 2066 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 2067 hdspm->midi[2].dataOut = HDSPM_midiDataOut2; 2068 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2; 2069 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 2070 hdspm->midi[2].irq = HDSPM_midi2IRQPending; 2071 } else if (2 == id) { 2072 /* TCO MTC, read only */ 2073 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 2074 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 2075 hdspm->midi[2].dataOut = -1; 2076 hdspm->midi[2].statusOut = -1; 2077 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 2078 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES; 2079 } else if (3 == id) { 2080 /* TCO MTC on HDSPe MADI */ 2081 hdspm->midi[3].dataIn = HDSPM_midiDataIn3; 2082 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3; 2083 hdspm->midi[3].dataOut = -1; 2084 hdspm->midi[3].statusOut = -1; 2085 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable; 2086 hdspm->midi[3].irq = HDSPM_midi3IRQPending; 2087 } 2088 2089 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) || 2090 (MADIface == hdspm->io_type)))) { 2091 if ((id == 0) && (MADIface == hdspm->io_type)) { 2092 snprintf(buf, sizeof(buf), "%s MIDIoverMADI", 2093 card->shortname); 2094 } else if ((id == 2) && (MADI == hdspm->io_type)) { 2095 snprintf(buf, sizeof(buf), "%s MIDIoverMADI", 2096 card->shortname); 2097 } else { 2098 snprintf(buf, sizeof(buf), "%s MIDI %d", 2099 card->shortname, id+1); 2100 } 2101 err = snd_rawmidi_new(card, buf, id, 1, 1, 2102 &hdspm->midi[id].rmidi); 2103 if (err < 0) 2104 return err; 2105 2106 snprintf(hdspm->midi[id].rmidi->name, 2107 sizeof(hdspm->midi[id].rmidi->name), 2108 "%s MIDI %d", card->id, id+1); 2109 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 2110 2111 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2112 SNDRV_RAWMIDI_STREAM_OUTPUT, 2113 &snd_hdspm_midi_output); 2114 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2115 SNDRV_RAWMIDI_STREAM_INPUT, 2116 &snd_hdspm_midi_input); 2117 2118 hdspm->midi[id].rmidi->info_flags |= 2119 SNDRV_RAWMIDI_INFO_OUTPUT | 2120 SNDRV_RAWMIDI_INFO_INPUT | 2121 SNDRV_RAWMIDI_INFO_DUPLEX; 2122 } else { 2123 /* TCO MTC, read only */ 2124 snprintf(buf, sizeof(buf), "%s MTC %d", 2125 card->shortname, id+1); 2126 err = snd_rawmidi_new(card, buf, id, 1, 1, 2127 &hdspm->midi[id].rmidi); 2128 if (err < 0) 2129 return err; 2130 2131 snprintf(hdspm->midi[id].rmidi->name, 2132 sizeof(hdspm->midi[id].rmidi->name), 2133 "%s MTC %d", card->id, id+1); 2134 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 2135 2136 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2137 SNDRV_RAWMIDI_STREAM_INPUT, 2138 &snd_hdspm_midi_input); 2139 2140 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT; 2141 } 2142 2143 return 0; 2144 } 2145 2146 2147 static void hdspm_midi_work(struct work_struct *work) 2148 { 2149 struct hdspm *hdspm = container_of(work, struct hdspm, midi_work); 2150 int i = 0; 2151 2152 while (i < hdspm->midiPorts) { 2153 if (hdspm->midi[i].pending) 2154 snd_hdspm_midi_input_read(&hdspm->midi[i]); 2155 2156 i++; 2157 } 2158 } 2159 2160 2161 /*----------------------------------------------------------------------------- 2162 Status Interface 2163 ----------------------------------------------------------------------------*/ 2164 2165 /* get the system sample rate which is set */ 2166 2167 2168 static inline int hdspm_get_pll_freq(struct hdspm *hdspm) 2169 { 2170 unsigned int period, rate; 2171 2172 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 2173 rate = hdspm_calc_dds_value(hdspm, period); 2174 2175 return rate; 2176 } 2177 2178 /* 2179 * Calculate the real sample rate from the 2180 * current DDS value. 2181 */ 2182 static int hdspm_get_system_sample_rate(struct hdspm *hdspm) 2183 { 2184 unsigned int rate; 2185 2186 rate = hdspm_get_pll_freq(hdspm); 2187 2188 if (rate > 207000) { 2189 /* Unreasonable high sample rate as seen on PCI MADI cards. */ 2190 if (0 == hdspm_system_clock_mode(hdspm)) { 2191 /* master mode, return internal sample rate */ 2192 rate = hdspm->system_sample_rate; 2193 } else { 2194 /* slave mode, return external sample rate */ 2195 rate = hdspm_external_sample_rate(hdspm); 2196 if (!rate) 2197 rate = hdspm->system_sample_rate; 2198 } 2199 } 2200 2201 return rate; 2202 } 2203 2204 2205 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \ 2206 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2207 .name = xname, \ 2208 .index = xindex, \ 2209 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2210 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2211 .info = snd_hdspm_info_system_sample_rate, \ 2212 .put = snd_hdspm_put_system_sample_rate, \ 2213 .get = snd_hdspm_get_system_sample_rate \ 2214 } 2215 2216 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol, 2217 struct snd_ctl_elem_info *uinfo) 2218 { 2219 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2220 uinfo->count = 1; 2221 uinfo->value.integer.min = 27000; 2222 uinfo->value.integer.max = 207000; 2223 uinfo->value.integer.step = 1; 2224 return 0; 2225 } 2226 2227 2228 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol, 2229 struct snd_ctl_elem_value * 2230 ucontrol) 2231 { 2232 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2233 2234 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm); 2235 return 0; 2236 } 2237 2238 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol, 2239 struct snd_ctl_elem_value * 2240 ucontrol) 2241 { 2242 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2243 int rate = ucontrol->value.integer.value[0]; 2244 2245 if (rate < 27000 || rate > 207000) 2246 return -EINVAL; 2247 hdspm_set_dds_value(hdspm, ucontrol->value.integer.value[0]); 2248 return 0; 2249 } 2250 2251 2252 /* 2253 * Returns the WordClock sample rate class for the given card. 2254 */ 2255 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm) 2256 { 2257 int status; 2258 2259 switch (hdspm->io_type) { 2260 case RayDAT: 2261 case AIO: 2262 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2263 return (status >> 16) & 0xF; 2264 case AES32: 2265 status = hdspm_read(hdspm, HDSPM_statusRegister); 2266 return (status >> HDSPM_AES32_wcFreq_bit) & 0xF; 2267 default: 2268 break; 2269 } 2270 2271 2272 return 0; 2273 } 2274 2275 2276 /* 2277 * Returns the TCO sample rate class for the given card. 2278 */ 2279 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm) 2280 { 2281 int status; 2282 2283 if (hdspm->tco) { 2284 switch (hdspm->io_type) { 2285 case RayDAT: 2286 case AIO: 2287 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2288 return (status >> 20) & 0xF; 2289 case AES32: 2290 status = hdspm_read(hdspm, HDSPM_statusRegister); 2291 return (status >> 1) & 0xF; 2292 default: 2293 break; 2294 } 2295 } 2296 2297 return 0; 2298 } 2299 2300 2301 /* 2302 * Returns the SYNC_IN sample rate class for the given card. 2303 */ 2304 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm) 2305 { 2306 int status; 2307 2308 if (hdspm->tco) { 2309 switch (hdspm->io_type) { 2310 case RayDAT: 2311 case AIO: 2312 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2313 return (status >> 12) & 0xF; 2314 default: 2315 break; 2316 } 2317 } 2318 2319 return 0; 2320 } 2321 2322 /* 2323 * Returns the AES sample rate class for the given card. 2324 */ 2325 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index) 2326 { 2327 int timecode; 2328 2329 switch (hdspm->io_type) { 2330 case AES32: 2331 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 2332 return (timecode >> (4*index)) & 0xF; 2333 default: 2334 break; 2335 } 2336 return 0; 2337 } 2338 2339 /* 2340 * Returns the sample rate class for input source <idx> for 2341 * 'new style' cards like the AIO and RayDAT. 2342 */ 2343 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx) 2344 { 2345 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2346 2347 return (status >> (idx*4)) & 0xF; 2348 } 2349 2350 #define ENUMERATED_CTL_INFO(info, texts) \ 2351 snd_ctl_enum_info(info, 1, ARRAY_SIZE(texts), texts) 2352 2353 2354 /* Helper function to query the external sample rate and return the 2355 * corresponding enum to be returned to userspace. 2356 */ 2357 static int hdspm_external_rate_to_enum(struct hdspm *hdspm) 2358 { 2359 int rate = hdspm_external_sample_rate(hdspm); 2360 int i, selected_rate = 0; 2361 for (i = 1; i < 10; i++) 2362 if (HDSPM_bit2freq(i) == rate) { 2363 selected_rate = i; 2364 break; 2365 } 2366 return selected_rate; 2367 } 2368 2369 2370 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 2371 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2372 .name = xname, \ 2373 .private_value = xindex, \ 2374 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2375 .info = snd_hdspm_info_autosync_sample_rate, \ 2376 .get = snd_hdspm_get_autosync_sample_rate \ 2377 } 2378 2379 2380 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2381 struct snd_ctl_elem_info *uinfo) 2382 { 2383 ENUMERATED_CTL_INFO(uinfo, texts_freq); 2384 return 0; 2385 } 2386 2387 2388 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2389 struct snd_ctl_elem_value * 2390 ucontrol) 2391 { 2392 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2393 2394 switch (hdspm->io_type) { 2395 case RayDAT: 2396 switch (kcontrol->private_value) { 2397 case 0: 2398 ucontrol->value.enumerated.item[0] = 2399 hdspm_get_wc_sample_rate(hdspm); 2400 break; 2401 case 7: 2402 ucontrol->value.enumerated.item[0] = 2403 hdspm_get_tco_sample_rate(hdspm); 2404 break; 2405 case 8: 2406 ucontrol->value.enumerated.item[0] = 2407 hdspm_get_sync_in_sample_rate(hdspm); 2408 break; 2409 default: 2410 ucontrol->value.enumerated.item[0] = 2411 hdspm_get_s1_sample_rate(hdspm, 2412 kcontrol->private_value-1); 2413 } 2414 break; 2415 2416 case AIO: 2417 switch (kcontrol->private_value) { 2418 case 0: /* WC */ 2419 ucontrol->value.enumerated.item[0] = 2420 hdspm_get_wc_sample_rate(hdspm); 2421 break; 2422 case 4: /* TCO */ 2423 ucontrol->value.enumerated.item[0] = 2424 hdspm_get_tco_sample_rate(hdspm); 2425 break; 2426 case 5: /* SYNC_IN */ 2427 ucontrol->value.enumerated.item[0] = 2428 hdspm_get_sync_in_sample_rate(hdspm); 2429 break; 2430 default: 2431 ucontrol->value.enumerated.item[0] = 2432 hdspm_get_s1_sample_rate(hdspm, 2433 kcontrol->private_value-1); 2434 } 2435 break; 2436 2437 case AES32: 2438 2439 switch (kcontrol->private_value) { 2440 case 0: /* WC */ 2441 ucontrol->value.enumerated.item[0] = 2442 hdspm_get_wc_sample_rate(hdspm); 2443 break; 2444 case 9: /* TCO */ 2445 ucontrol->value.enumerated.item[0] = 2446 hdspm_get_tco_sample_rate(hdspm); 2447 break; 2448 case 10: /* SYNC_IN */ 2449 ucontrol->value.enumerated.item[0] = 2450 hdspm_get_sync_in_sample_rate(hdspm); 2451 break; 2452 case 11: /* External Rate */ 2453 ucontrol->value.enumerated.item[0] = 2454 hdspm_external_rate_to_enum(hdspm); 2455 break; 2456 default: /* AES1 to AES8 */ 2457 ucontrol->value.enumerated.item[0] = 2458 hdspm_get_aes_sample_rate(hdspm, 2459 kcontrol->private_value - 2460 HDSPM_AES32_AUTOSYNC_FROM_AES1); 2461 break; 2462 } 2463 break; 2464 2465 case MADI: 2466 case MADIface: 2467 ucontrol->value.enumerated.item[0] = 2468 hdspm_external_rate_to_enum(hdspm); 2469 break; 2470 default: 2471 break; 2472 } 2473 2474 return 0; 2475 } 2476 2477 2478 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \ 2479 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2480 .name = xname, \ 2481 .index = xindex, \ 2482 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2483 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2484 .info = snd_hdspm_info_system_clock_mode, \ 2485 .get = snd_hdspm_get_system_clock_mode, \ 2486 .put = snd_hdspm_put_system_clock_mode, \ 2487 } 2488 2489 2490 /* 2491 * Returns the system clock mode for the given card. 2492 * @returns 0 - master, 1 - slave 2493 */ 2494 static int hdspm_system_clock_mode(struct hdspm *hdspm) 2495 { 2496 switch (hdspm->io_type) { 2497 case AIO: 2498 case RayDAT: 2499 if (hdspm->settings_register & HDSPM_c0Master) 2500 return 0; 2501 break; 2502 2503 default: 2504 if (hdspm->control_register & HDSPM_ClockModeMaster) 2505 return 0; 2506 } 2507 2508 return 1; 2509 } 2510 2511 2512 /* 2513 * Sets the system clock mode. 2514 * @param mode 0 - master, 1 - slave 2515 */ 2516 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode) 2517 { 2518 hdspm_set_toggle_setting(hdspm, 2519 (hdspm_is_raydat_or_aio(hdspm)) ? 2520 HDSPM_c0Master : HDSPM_ClockModeMaster, 2521 (0 == mode)); 2522 } 2523 2524 2525 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol, 2526 struct snd_ctl_elem_info *uinfo) 2527 { 2528 static const char *const texts[] = { "Master", "AutoSync" }; 2529 ENUMERATED_CTL_INFO(uinfo, texts); 2530 return 0; 2531 } 2532 2533 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol, 2534 struct snd_ctl_elem_value *ucontrol) 2535 { 2536 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2537 2538 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm); 2539 return 0; 2540 } 2541 2542 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol, 2543 struct snd_ctl_elem_value *ucontrol) 2544 { 2545 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2546 int val; 2547 2548 if (!snd_hdspm_use_is_exclusive(hdspm)) 2549 return -EBUSY; 2550 2551 val = ucontrol->value.enumerated.item[0]; 2552 if (val < 0) 2553 val = 0; 2554 else if (val > 1) 2555 val = 1; 2556 2557 hdspm_set_system_clock_mode(hdspm, val); 2558 2559 return 0; 2560 } 2561 2562 2563 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \ 2564 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2565 .name = xname, \ 2566 .index = xindex, \ 2567 .info = snd_hdspm_info_clock_source, \ 2568 .get = snd_hdspm_get_clock_source, \ 2569 .put = snd_hdspm_put_clock_source \ 2570 } 2571 2572 2573 static int hdspm_clock_source(struct hdspm * hdspm) 2574 { 2575 switch (hdspm->system_sample_rate) { 2576 case 32000: return 0; 2577 case 44100: return 1; 2578 case 48000: return 2; 2579 case 64000: return 3; 2580 case 88200: return 4; 2581 case 96000: return 5; 2582 case 128000: return 6; 2583 case 176400: return 7; 2584 case 192000: return 8; 2585 } 2586 2587 return -1; 2588 } 2589 2590 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode) 2591 { 2592 int rate; 2593 switch (mode) { 2594 case 0: 2595 rate = 32000; break; 2596 case 1: 2597 rate = 44100; break; 2598 case 2: 2599 rate = 48000; break; 2600 case 3: 2601 rate = 64000; break; 2602 case 4: 2603 rate = 88200; break; 2604 case 5: 2605 rate = 96000; break; 2606 case 6: 2607 rate = 128000; break; 2608 case 7: 2609 rate = 176400; break; 2610 case 8: 2611 rate = 192000; break; 2612 default: 2613 rate = 48000; 2614 } 2615 hdspm_set_rate(hdspm, rate, 1); 2616 return 0; 2617 } 2618 2619 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol, 2620 struct snd_ctl_elem_info *uinfo) 2621 { 2622 return snd_ctl_enum_info(uinfo, 1, 9, texts_freq + 1); 2623 } 2624 2625 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol, 2626 struct snd_ctl_elem_value *ucontrol) 2627 { 2628 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2629 2630 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm); 2631 return 0; 2632 } 2633 2634 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol, 2635 struct snd_ctl_elem_value *ucontrol) 2636 { 2637 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2638 int change; 2639 int val; 2640 2641 if (!snd_hdspm_use_is_exclusive(hdspm)) 2642 return -EBUSY; 2643 val = ucontrol->value.enumerated.item[0]; 2644 if (val < 0) 2645 val = 0; 2646 if (val > 9) 2647 val = 9; 2648 guard(spinlock_irq)(&hdspm->lock); 2649 if (val != hdspm_clock_source(hdspm)) 2650 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; 2651 else 2652 change = 0; 2653 return change; 2654 } 2655 2656 2657 #define HDSPM_PREF_SYNC_REF(xname, xindex) \ 2658 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2659 .name = xname, \ 2660 .index = xindex, \ 2661 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2662 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2663 .info = snd_hdspm_info_pref_sync_ref, \ 2664 .get = snd_hdspm_get_pref_sync_ref, \ 2665 .put = snd_hdspm_put_pref_sync_ref \ 2666 } 2667 2668 2669 /* 2670 * Returns the current preferred sync reference setting. 2671 * The semantics of the return value are depending on the 2672 * card, please see the comments for clarification. 2673 */ 2674 static int hdspm_pref_sync_ref(struct hdspm * hdspm) 2675 { 2676 switch (hdspm->io_type) { 2677 case AES32: 2678 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2679 case 0: return 0; /* WC */ 2680 case HDSPM_SyncRef0: return 1; /* AES 1 */ 2681 case HDSPM_SyncRef1: return 2; /* AES 2 */ 2682 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */ 2683 case HDSPM_SyncRef2: return 4; /* AES 4 */ 2684 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */ 2685 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */ 2686 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: 2687 return 7; /* AES 7 */ 2688 case HDSPM_SyncRef3: return 8; /* AES 8 */ 2689 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */ 2690 } 2691 break; 2692 2693 case MADI: 2694 case MADIface: 2695 if (hdspm->tco) { 2696 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2697 case 0: return 0; /* WC */ 2698 case HDSPM_SyncRef0: return 1; /* MADI */ 2699 case HDSPM_SyncRef1: return 2; /* TCO */ 2700 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2701 return 3; /* SYNC_IN */ 2702 } 2703 } else { 2704 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2705 case 0: return 0; /* WC */ 2706 case HDSPM_SyncRef0: return 1; /* MADI */ 2707 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2708 return 2; /* SYNC_IN */ 2709 } 2710 } 2711 break; 2712 2713 case RayDAT: 2714 if (hdspm->tco) { 2715 switch ((hdspm->settings_register & 2716 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2717 case 0: return 0; /* WC */ 2718 case 3: return 1; /* ADAT 1 */ 2719 case 4: return 2; /* ADAT 2 */ 2720 case 5: return 3; /* ADAT 3 */ 2721 case 6: return 4; /* ADAT 4 */ 2722 case 1: return 5; /* AES */ 2723 case 2: return 6; /* SPDIF */ 2724 case 9: return 7; /* TCO */ 2725 case 10: return 8; /* SYNC_IN */ 2726 } 2727 } else { 2728 switch ((hdspm->settings_register & 2729 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2730 case 0: return 0; /* WC */ 2731 case 3: return 1; /* ADAT 1 */ 2732 case 4: return 2; /* ADAT 2 */ 2733 case 5: return 3; /* ADAT 3 */ 2734 case 6: return 4; /* ADAT 4 */ 2735 case 1: return 5; /* AES */ 2736 case 2: return 6; /* SPDIF */ 2737 case 10: return 7; /* SYNC_IN */ 2738 } 2739 } 2740 2741 break; 2742 2743 case AIO: 2744 if (hdspm->tco) { 2745 switch ((hdspm->settings_register & 2746 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2747 case 0: return 0; /* WC */ 2748 case 3: return 1; /* ADAT */ 2749 case 1: return 2; /* AES */ 2750 case 2: return 3; /* SPDIF */ 2751 case 9: return 4; /* TCO */ 2752 case 10: return 5; /* SYNC_IN */ 2753 } 2754 } else { 2755 switch ((hdspm->settings_register & 2756 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2757 case 0: return 0; /* WC */ 2758 case 3: return 1; /* ADAT */ 2759 case 1: return 2; /* AES */ 2760 case 2: return 3; /* SPDIF */ 2761 case 10: return 4; /* SYNC_IN */ 2762 } 2763 } 2764 2765 break; 2766 } 2767 2768 return -1; 2769 } 2770 2771 2772 /* 2773 * Set the preferred sync reference to <pref>. The semantics 2774 * of <pref> are depending on the card type, see the comments 2775 * for clarification. 2776 */ 2777 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref) 2778 { 2779 int p = 0; 2780 2781 switch (hdspm->io_type) { 2782 case AES32: 2783 hdspm->control_register &= ~HDSPM_SyncRefMask; 2784 switch (pref) { 2785 case 0: /* WC */ 2786 break; 2787 case 1: /* AES 1 */ 2788 hdspm->control_register |= HDSPM_SyncRef0; 2789 break; 2790 case 2: /* AES 2 */ 2791 hdspm->control_register |= HDSPM_SyncRef1; 2792 break; 2793 case 3: /* AES 3 */ 2794 hdspm->control_register |= 2795 HDSPM_SyncRef1+HDSPM_SyncRef0; 2796 break; 2797 case 4: /* AES 4 */ 2798 hdspm->control_register |= HDSPM_SyncRef2; 2799 break; 2800 case 5: /* AES 5 */ 2801 hdspm->control_register |= 2802 HDSPM_SyncRef2+HDSPM_SyncRef0; 2803 break; 2804 case 6: /* AES 6 */ 2805 hdspm->control_register |= 2806 HDSPM_SyncRef2+HDSPM_SyncRef1; 2807 break; 2808 case 7: /* AES 7 */ 2809 hdspm->control_register |= 2810 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0; 2811 break; 2812 case 8: /* AES 8 */ 2813 hdspm->control_register |= HDSPM_SyncRef3; 2814 break; 2815 case 9: /* TCO */ 2816 hdspm->control_register |= 2817 HDSPM_SyncRef3+HDSPM_SyncRef0; 2818 break; 2819 default: 2820 return -1; 2821 } 2822 2823 break; 2824 2825 case MADI: 2826 case MADIface: 2827 hdspm->control_register &= ~HDSPM_SyncRefMask; 2828 if (hdspm->tco) { 2829 switch (pref) { 2830 case 0: /* WC */ 2831 break; 2832 case 1: /* MADI */ 2833 hdspm->control_register |= HDSPM_SyncRef0; 2834 break; 2835 case 2: /* TCO */ 2836 hdspm->control_register |= HDSPM_SyncRef1; 2837 break; 2838 case 3: /* SYNC_IN */ 2839 hdspm->control_register |= 2840 HDSPM_SyncRef0+HDSPM_SyncRef1; 2841 break; 2842 default: 2843 return -1; 2844 } 2845 } else { 2846 switch (pref) { 2847 case 0: /* WC */ 2848 break; 2849 case 1: /* MADI */ 2850 hdspm->control_register |= HDSPM_SyncRef0; 2851 break; 2852 case 2: /* SYNC_IN */ 2853 hdspm->control_register |= 2854 HDSPM_SyncRef0+HDSPM_SyncRef1; 2855 break; 2856 default: 2857 return -1; 2858 } 2859 } 2860 2861 break; 2862 2863 case RayDAT: 2864 if (hdspm->tco) { 2865 switch (pref) { 2866 case 0: p = 0; break; /* WC */ 2867 case 1: p = 3; break; /* ADAT 1 */ 2868 case 2: p = 4; break; /* ADAT 2 */ 2869 case 3: p = 5; break; /* ADAT 3 */ 2870 case 4: p = 6; break; /* ADAT 4 */ 2871 case 5: p = 1; break; /* AES */ 2872 case 6: p = 2; break; /* SPDIF */ 2873 case 7: p = 9; break; /* TCO */ 2874 case 8: p = 10; break; /* SYNC_IN */ 2875 default: return -1; 2876 } 2877 } else { 2878 switch (pref) { 2879 case 0: p = 0; break; /* WC */ 2880 case 1: p = 3; break; /* ADAT 1 */ 2881 case 2: p = 4; break; /* ADAT 2 */ 2882 case 3: p = 5; break; /* ADAT 3 */ 2883 case 4: p = 6; break; /* ADAT 4 */ 2884 case 5: p = 1; break; /* AES */ 2885 case 6: p = 2; break; /* SPDIF */ 2886 case 7: p = 10; break; /* SYNC_IN */ 2887 default: return -1; 2888 } 2889 } 2890 break; 2891 2892 case AIO: 2893 if (hdspm->tco) { 2894 switch (pref) { 2895 case 0: p = 0; break; /* WC */ 2896 case 1: p = 3; break; /* ADAT */ 2897 case 2: p = 1; break; /* AES */ 2898 case 3: p = 2; break; /* SPDIF */ 2899 case 4: p = 9; break; /* TCO */ 2900 case 5: p = 10; break; /* SYNC_IN */ 2901 default: return -1; 2902 } 2903 } else { 2904 switch (pref) { 2905 case 0: p = 0; break; /* WC */ 2906 case 1: p = 3; break; /* ADAT */ 2907 case 2: p = 1; break; /* AES */ 2908 case 3: p = 2; break; /* SPDIF */ 2909 case 4: p = 10; break; /* SYNC_IN */ 2910 default: return -1; 2911 } 2912 } 2913 break; 2914 } 2915 2916 switch (hdspm->io_type) { 2917 case RayDAT: 2918 case AIO: 2919 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask; 2920 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p; 2921 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2922 break; 2923 2924 case MADI: 2925 case MADIface: 2926 case AES32: 2927 hdspm_write(hdspm, HDSPM_controlRegister, 2928 hdspm->control_register); 2929 } 2930 2931 return 0; 2932 } 2933 2934 2935 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol, 2936 struct snd_ctl_elem_info *uinfo) 2937 { 2938 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2939 2940 snd_ctl_enum_info(uinfo, 1, hdspm->texts_autosync_items, hdspm->texts_autosync); 2941 2942 return 0; 2943 } 2944 2945 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol, 2946 struct snd_ctl_elem_value *ucontrol) 2947 { 2948 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2949 int psf = hdspm_pref_sync_ref(hdspm); 2950 2951 if (psf >= 0) { 2952 ucontrol->value.enumerated.item[0] = psf; 2953 return 0; 2954 } 2955 2956 return -1; 2957 } 2958 2959 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol, 2960 struct snd_ctl_elem_value *ucontrol) 2961 { 2962 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2963 int val, change = 0; 2964 2965 if (!snd_hdspm_use_is_exclusive(hdspm)) 2966 return -EBUSY; 2967 2968 val = ucontrol->value.enumerated.item[0]; 2969 2970 if (val < 0) 2971 val = 0; 2972 else if (val >= hdspm->texts_autosync_items) 2973 val = hdspm->texts_autosync_items-1; 2974 2975 guard(spinlock_irq)(&hdspm->lock); 2976 if (val != hdspm_pref_sync_ref(hdspm)) 2977 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0; 2978 2979 return change; 2980 } 2981 2982 2983 #define HDSPM_AUTOSYNC_REF(xname, xindex) \ 2984 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2985 .name = xname, \ 2986 .index = xindex, \ 2987 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2988 .info = snd_hdspm_info_autosync_ref, \ 2989 .get = snd_hdspm_get_autosync_ref, \ 2990 } 2991 2992 static int hdspm_autosync_ref(struct hdspm *hdspm) 2993 { 2994 /* This looks at the autosync selected sync reference */ 2995 if (AES32 == hdspm->io_type) { 2996 2997 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); 2998 unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF; 2999 /* syncref >= HDSPM_AES32_AUTOSYNC_FROM_WORD is always true */ 3000 if (syncref <= HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN) { 3001 return syncref; 3002 } 3003 return HDSPM_AES32_AUTOSYNC_FROM_NONE; 3004 3005 } else if (MADI == hdspm->io_type) { 3006 3007 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3008 switch (status2 & HDSPM_SelSyncRefMask) { 3009 case HDSPM_SelSyncRef_WORD: 3010 return HDSPM_AUTOSYNC_FROM_WORD; 3011 case HDSPM_SelSyncRef_MADI: 3012 return HDSPM_AUTOSYNC_FROM_MADI; 3013 case HDSPM_SelSyncRef_TCO: 3014 return HDSPM_AUTOSYNC_FROM_TCO; 3015 case HDSPM_SelSyncRef_SyncIn: 3016 return HDSPM_AUTOSYNC_FROM_SYNC_IN; 3017 case HDSPM_SelSyncRef_NVALID: 3018 return HDSPM_AUTOSYNC_FROM_NONE; 3019 default: 3020 return HDSPM_AUTOSYNC_FROM_NONE; 3021 } 3022 3023 } 3024 return 0; 3025 } 3026 3027 3028 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol, 3029 struct snd_ctl_elem_info *uinfo) 3030 { 3031 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3032 3033 if (AES32 == hdspm->io_type) { 3034 static const char *const texts[] = { "WordClock", "AES1", "AES2", "AES3", 3035 "AES4", "AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"}; 3036 3037 ENUMERATED_CTL_INFO(uinfo, texts); 3038 } else if (MADI == hdspm->io_type) { 3039 static const char *const texts[] = {"Word Clock", "MADI", "TCO", 3040 "Sync In", "None" }; 3041 3042 ENUMERATED_CTL_INFO(uinfo, texts); 3043 } 3044 return 0; 3045 } 3046 3047 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol, 3048 struct snd_ctl_elem_value *ucontrol) 3049 { 3050 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3051 3052 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm); 3053 return 0; 3054 } 3055 3056 3057 3058 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname) \ 3059 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3060 .name = xname, \ 3061 .access = SNDRV_CTL_ELEM_ACCESS_READ |\ 3062 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3063 .info = snd_hdspm_info_tco_video_input_format, \ 3064 .get = snd_hdspm_get_tco_video_input_format, \ 3065 } 3066 3067 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol, 3068 struct snd_ctl_elem_info *uinfo) 3069 { 3070 static const char *const texts[] = {"No video", "NTSC", "PAL"}; 3071 ENUMERATED_CTL_INFO(uinfo, texts); 3072 return 0; 3073 } 3074 3075 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol, 3076 struct snd_ctl_elem_value *ucontrol) 3077 { 3078 u32 status; 3079 int ret = 0; 3080 3081 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3082 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3083 switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC | 3084 HDSPM_TCO1_Video_Input_Format_PAL)) { 3085 case HDSPM_TCO1_Video_Input_Format_NTSC: 3086 /* ntsc */ 3087 ret = 1; 3088 break; 3089 case HDSPM_TCO1_Video_Input_Format_PAL: 3090 /* pal */ 3091 ret = 2; 3092 break; 3093 default: 3094 /* no video */ 3095 ret = 0; 3096 break; 3097 } 3098 ucontrol->value.enumerated.item[0] = ret; 3099 return 0; 3100 } 3101 3102 3103 3104 #define HDSPM_TCO_LTC_FRAMES(xname) \ 3105 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3106 .name = xname, \ 3107 .access = SNDRV_CTL_ELEM_ACCESS_READ |\ 3108 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3109 .info = snd_hdspm_info_tco_ltc_frames, \ 3110 .get = snd_hdspm_get_tco_ltc_frames, \ 3111 } 3112 3113 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol, 3114 struct snd_ctl_elem_info *uinfo) 3115 { 3116 static const char *const texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps", 3117 "30 fps"}; 3118 ENUMERATED_CTL_INFO(uinfo, texts); 3119 return 0; 3120 } 3121 3122 static int hdspm_tco_ltc_frames(struct hdspm *hdspm) 3123 { 3124 u32 status; 3125 int ret = 0; 3126 3127 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3128 if (status & HDSPM_TCO1_LTC_Input_valid) { 3129 switch (status & (HDSPM_TCO1_LTC_Format_LSB | 3130 HDSPM_TCO1_LTC_Format_MSB)) { 3131 case 0: 3132 /* 24 fps */ 3133 ret = fps_24; 3134 break; 3135 case HDSPM_TCO1_LTC_Format_LSB: 3136 /* 25 fps */ 3137 ret = fps_25; 3138 break; 3139 case HDSPM_TCO1_LTC_Format_MSB: 3140 /* 29.97 fps */ 3141 ret = fps_2997; 3142 break; 3143 default: 3144 /* 30 fps */ 3145 ret = fps_30; 3146 break; 3147 } 3148 } 3149 3150 return ret; 3151 } 3152 3153 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol, 3154 struct snd_ctl_elem_value *ucontrol) 3155 { 3156 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3157 3158 ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm); 3159 return 0; 3160 } 3161 3162 #define HDSPM_TOGGLE_SETTING(xname, xindex) \ 3163 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3164 .name = xname, \ 3165 .private_value = xindex, \ 3166 .info = snd_hdspm_info_toggle_setting, \ 3167 .get = snd_hdspm_get_toggle_setting, \ 3168 .put = snd_hdspm_put_toggle_setting \ 3169 } 3170 3171 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask) 3172 { 3173 u32 reg; 3174 3175 if (hdspm_is_raydat_or_aio(hdspm)) 3176 reg = hdspm->settings_register; 3177 else 3178 reg = hdspm->control_register; 3179 3180 return (reg & regmask) ? 1 : 0; 3181 } 3182 3183 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out) 3184 { 3185 u32 *reg; 3186 u32 target_reg; 3187 3188 if (hdspm_is_raydat_or_aio(hdspm)) { 3189 reg = &(hdspm->settings_register); 3190 target_reg = HDSPM_WR_SETTINGS; 3191 } else { 3192 reg = &(hdspm->control_register); 3193 target_reg = HDSPM_controlRegister; 3194 } 3195 3196 if (out) 3197 *reg |= regmask; 3198 else 3199 *reg &= ~regmask; 3200 3201 hdspm_write(hdspm, target_reg, *reg); 3202 3203 return 0; 3204 } 3205 3206 #define snd_hdspm_info_toggle_setting snd_ctl_boolean_mono_info 3207 3208 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol, 3209 struct snd_ctl_elem_value *ucontrol) 3210 { 3211 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3212 u32 regmask = kcontrol->private_value; 3213 3214 guard(spinlock_irq)(&hdspm->lock); 3215 ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask); 3216 return 0; 3217 } 3218 3219 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol, 3220 struct snd_ctl_elem_value *ucontrol) 3221 { 3222 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3223 u32 regmask = kcontrol->private_value; 3224 int change; 3225 unsigned int val; 3226 3227 if (!snd_hdspm_use_is_exclusive(hdspm)) 3228 return -EBUSY; 3229 val = ucontrol->value.integer.value[0] & 1; 3230 guard(spinlock_irq)(&hdspm->lock); 3231 change = (int) val != hdspm_toggle_setting(hdspm, regmask); 3232 hdspm_set_toggle_setting(hdspm, regmask, val); 3233 return change; 3234 } 3235 3236 #define HDSPM_INPUT_SELECT(xname, xindex) \ 3237 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3238 .name = xname, \ 3239 .index = xindex, \ 3240 .info = snd_hdspm_info_input_select, \ 3241 .get = snd_hdspm_get_input_select, \ 3242 .put = snd_hdspm_put_input_select \ 3243 } 3244 3245 static int hdspm_input_select(struct hdspm * hdspm) 3246 { 3247 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0; 3248 } 3249 3250 static int hdspm_set_input_select(struct hdspm * hdspm, int out) 3251 { 3252 if (out) 3253 hdspm->control_register |= HDSPM_InputSelect0; 3254 else 3255 hdspm->control_register &= ~HDSPM_InputSelect0; 3256 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3257 3258 return 0; 3259 } 3260 3261 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol, 3262 struct snd_ctl_elem_info *uinfo) 3263 { 3264 static const char *const texts[] = { "optical", "coaxial" }; 3265 ENUMERATED_CTL_INFO(uinfo, texts); 3266 return 0; 3267 } 3268 3269 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol, 3270 struct snd_ctl_elem_value *ucontrol) 3271 { 3272 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3273 3274 guard(spinlock_irq)(&hdspm->lock); 3275 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm); 3276 return 0; 3277 } 3278 3279 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol, 3280 struct snd_ctl_elem_value *ucontrol) 3281 { 3282 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3283 int change; 3284 unsigned int val; 3285 3286 if (!snd_hdspm_use_is_exclusive(hdspm)) 3287 return -EBUSY; 3288 val = ucontrol->value.integer.value[0] & 1; 3289 guard(spinlock_irq)(&hdspm->lock); 3290 change = (int) val != hdspm_input_select(hdspm); 3291 hdspm_set_input_select(hdspm, val); 3292 return change; 3293 } 3294 3295 3296 #define HDSPM_DS_WIRE(xname, xindex) \ 3297 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3298 .name = xname, \ 3299 .index = xindex, \ 3300 .info = snd_hdspm_info_ds_wire, \ 3301 .get = snd_hdspm_get_ds_wire, \ 3302 .put = snd_hdspm_put_ds_wire \ 3303 } 3304 3305 static int hdspm_ds_wire(struct hdspm * hdspm) 3306 { 3307 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0; 3308 } 3309 3310 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds) 3311 { 3312 if (ds) 3313 hdspm->control_register |= HDSPM_DS_DoubleWire; 3314 else 3315 hdspm->control_register &= ~HDSPM_DS_DoubleWire; 3316 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3317 3318 return 0; 3319 } 3320 3321 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol, 3322 struct snd_ctl_elem_info *uinfo) 3323 { 3324 static const char *const texts[] = { "Single", "Double" }; 3325 ENUMERATED_CTL_INFO(uinfo, texts); 3326 return 0; 3327 } 3328 3329 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol, 3330 struct snd_ctl_elem_value *ucontrol) 3331 { 3332 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3333 3334 guard(spinlock_irq)(&hdspm->lock); 3335 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm); 3336 return 0; 3337 } 3338 3339 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol, 3340 struct snd_ctl_elem_value *ucontrol) 3341 { 3342 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3343 int change; 3344 unsigned int val; 3345 3346 if (!snd_hdspm_use_is_exclusive(hdspm)) 3347 return -EBUSY; 3348 val = ucontrol->value.integer.value[0] & 1; 3349 guard(spinlock_irq)(&hdspm->lock); 3350 change = (int) val != hdspm_ds_wire(hdspm); 3351 hdspm_set_ds_wire(hdspm, val); 3352 return change; 3353 } 3354 3355 3356 #define HDSPM_QS_WIRE(xname, xindex) \ 3357 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3358 .name = xname, \ 3359 .index = xindex, \ 3360 .info = snd_hdspm_info_qs_wire, \ 3361 .get = snd_hdspm_get_qs_wire, \ 3362 .put = snd_hdspm_put_qs_wire \ 3363 } 3364 3365 static int hdspm_qs_wire(struct hdspm * hdspm) 3366 { 3367 if (hdspm->control_register & HDSPM_QS_DoubleWire) 3368 return 1; 3369 if (hdspm->control_register & HDSPM_QS_QuadWire) 3370 return 2; 3371 return 0; 3372 } 3373 3374 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode) 3375 { 3376 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire); 3377 switch (mode) { 3378 case 0: 3379 break; 3380 case 1: 3381 hdspm->control_register |= HDSPM_QS_DoubleWire; 3382 break; 3383 case 2: 3384 hdspm->control_register |= HDSPM_QS_QuadWire; 3385 break; 3386 } 3387 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3388 3389 return 0; 3390 } 3391 3392 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol, 3393 struct snd_ctl_elem_info *uinfo) 3394 { 3395 static const char *const texts[] = { "Single", "Double", "Quad" }; 3396 ENUMERATED_CTL_INFO(uinfo, texts); 3397 return 0; 3398 } 3399 3400 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol, 3401 struct snd_ctl_elem_value *ucontrol) 3402 { 3403 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3404 3405 guard(spinlock_irq)(&hdspm->lock); 3406 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm); 3407 return 0; 3408 } 3409 3410 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol, 3411 struct snd_ctl_elem_value *ucontrol) 3412 { 3413 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3414 int change; 3415 int val; 3416 3417 if (!snd_hdspm_use_is_exclusive(hdspm)) 3418 return -EBUSY; 3419 val = ucontrol->value.integer.value[0]; 3420 if (val < 0) 3421 val = 0; 3422 if (val > 2) 3423 val = 2; 3424 guard(spinlock_irq)(&hdspm->lock); 3425 change = val != hdspm_qs_wire(hdspm); 3426 hdspm_set_qs_wire(hdspm, val); 3427 return change; 3428 } 3429 3430 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \ 3431 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3432 .name = xname, \ 3433 .private_value = xindex, \ 3434 .info = snd_hdspm_info_tristate, \ 3435 .get = snd_hdspm_get_tristate, \ 3436 .put = snd_hdspm_put_tristate \ 3437 } 3438 3439 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask) 3440 { 3441 u32 reg = hdspm->settings_register & (regmask * 3); 3442 return reg / regmask; 3443 } 3444 3445 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask) 3446 { 3447 hdspm->settings_register &= ~(regmask * 3); 3448 hdspm->settings_register |= (regmask * mode); 3449 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 3450 3451 return 0; 3452 } 3453 3454 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol, 3455 struct snd_ctl_elem_info *uinfo) 3456 { 3457 u32 regmask = kcontrol->private_value; 3458 3459 static const char *const texts_spdif[] = { "Optical", "Coaxial", "Internal" }; 3460 static const char *const texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" }; 3461 3462 switch (regmask) { 3463 case HDSPM_c0_Input0: 3464 ENUMERATED_CTL_INFO(uinfo, texts_spdif); 3465 break; 3466 default: 3467 ENUMERATED_CTL_INFO(uinfo, texts_levels); 3468 break; 3469 } 3470 return 0; 3471 } 3472 3473 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol, 3474 struct snd_ctl_elem_value *ucontrol) 3475 { 3476 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3477 u32 regmask = kcontrol->private_value; 3478 3479 guard(spinlock_irq)(&hdspm->lock); 3480 ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask); 3481 return 0; 3482 } 3483 3484 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol, 3485 struct snd_ctl_elem_value *ucontrol) 3486 { 3487 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3488 u32 regmask = kcontrol->private_value; 3489 int change; 3490 int val; 3491 3492 if (!snd_hdspm_use_is_exclusive(hdspm)) 3493 return -EBUSY; 3494 val = ucontrol->value.integer.value[0]; 3495 if (val < 0) 3496 val = 0; 3497 if (val > 2) 3498 val = 2; 3499 3500 guard(spinlock_irq)(&hdspm->lock); 3501 change = val != hdspm_tristate(hdspm, regmask); 3502 hdspm_set_tristate(hdspm, val, regmask); 3503 return change; 3504 } 3505 3506 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \ 3507 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3508 .name = xname, \ 3509 .index = xindex, \ 3510 .info = snd_hdspm_info_madi_speedmode, \ 3511 .get = snd_hdspm_get_madi_speedmode, \ 3512 .put = snd_hdspm_put_madi_speedmode \ 3513 } 3514 3515 static int hdspm_madi_speedmode(struct hdspm *hdspm) 3516 { 3517 if (hdspm->control_register & HDSPM_QuadSpeed) 3518 return 2; 3519 if (hdspm->control_register & HDSPM_DoubleSpeed) 3520 return 1; 3521 return 0; 3522 } 3523 3524 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode) 3525 { 3526 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed); 3527 switch (mode) { 3528 case 0: 3529 break; 3530 case 1: 3531 hdspm->control_register |= HDSPM_DoubleSpeed; 3532 break; 3533 case 2: 3534 hdspm->control_register |= HDSPM_QuadSpeed; 3535 break; 3536 } 3537 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3538 3539 return 0; 3540 } 3541 3542 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol, 3543 struct snd_ctl_elem_info *uinfo) 3544 { 3545 static const char *const texts[] = { "Single", "Double", "Quad" }; 3546 ENUMERATED_CTL_INFO(uinfo, texts); 3547 return 0; 3548 } 3549 3550 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol, 3551 struct snd_ctl_elem_value *ucontrol) 3552 { 3553 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3554 3555 guard(spinlock_irq)(&hdspm->lock); 3556 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm); 3557 return 0; 3558 } 3559 3560 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol, 3561 struct snd_ctl_elem_value *ucontrol) 3562 { 3563 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3564 int change; 3565 int val; 3566 3567 if (!snd_hdspm_use_is_exclusive(hdspm)) 3568 return -EBUSY; 3569 val = ucontrol->value.integer.value[0]; 3570 if (val < 0) 3571 val = 0; 3572 if (val > 2) 3573 val = 2; 3574 guard(spinlock_irq)(&hdspm->lock); 3575 change = val != hdspm_madi_speedmode(hdspm); 3576 hdspm_set_madi_speedmode(hdspm, val); 3577 return change; 3578 } 3579 3580 #define HDSPM_MIXER(xname, xindex) \ 3581 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 3582 .name = xname, \ 3583 .index = xindex, \ 3584 .device = 0, \ 3585 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3586 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3587 .info = snd_hdspm_info_mixer, \ 3588 .get = snd_hdspm_get_mixer, \ 3589 .put = snd_hdspm_put_mixer \ 3590 } 3591 3592 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol, 3593 struct snd_ctl_elem_info *uinfo) 3594 { 3595 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3596 uinfo->count = 3; 3597 uinfo->value.integer.min = 0; 3598 uinfo->value.integer.max = 65535; 3599 uinfo->value.integer.step = 1; 3600 return 0; 3601 } 3602 3603 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol, 3604 struct snd_ctl_elem_value *ucontrol) 3605 { 3606 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3607 int source; 3608 int destination; 3609 3610 source = ucontrol->value.integer.value[0]; 3611 if (source < 0) 3612 source = 0; 3613 else if (source >= 2 * HDSPM_MAX_CHANNELS) 3614 source = 2 * HDSPM_MAX_CHANNELS - 1; 3615 3616 destination = ucontrol->value.integer.value[1]; 3617 if (destination < 0) 3618 destination = 0; 3619 else if (destination >= HDSPM_MAX_CHANNELS) 3620 destination = HDSPM_MAX_CHANNELS - 1; 3621 3622 guard(spinlock_irq)(&hdspm->lock); 3623 if (source >= HDSPM_MAX_CHANNELS) 3624 ucontrol->value.integer.value[2] = 3625 hdspm_read_pb_gain(hdspm, destination, 3626 source - HDSPM_MAX_CHANNELS); 3627 else 3628 ucontrol->value.integer.value[2] = 3629 hdspm_read_in_gain(hdspm, destination, source); 3630 3631 return 0; 3632 } 3633 3634 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol, 3635 struct snd_ctl_elem_value *ucontrol) 3636 { 3637 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3638 int change; 3639 int source; 3640 int destination; 3641 int gain; 3642 3643 if (!snd_hdspm_use_is_exclusive(hdspm)) 3644 return -EBUSY; 3645 3646 source = ucontrol->value.integer.value[0]; 3647 destination = ucontrol->value.integer.value[1]; 3648 3649 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS) 3650 return -1; 3651 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS) 3652 return -1; 3653 3654 gain = ucontrol->value.integer.value[2]; 3655 3656 guard(spinlock_irq)(&hdspm->lock); 3657 3658 if (source >= HDSPM_MAX_CHANNELS) 3659 change = gain != hdspm_read_pb_gain(hdspm, destination, 3660 source - 3661 HDSPM_MAX_CHANNELS); 3662 else 3663 change = gain != hdspm_read_in_gain(hdspm, destination, 3664 source); 3665 3666 if (change) { 3667 if (source >= HDSPM_MAX_CHANNELS) 3668 hdspm_write_pb_gain(hdspm, destination, 3669 source - HDSPM_MAX_CHANNELS, 3670 gain); 3671 else 3672 hdspm_write_in_gain(hdspm, destination, source, 3673 gain); 3674 } 3675 3676 return change; 3677 } 3678 3679 /* The simple mixer control(s) provide gain control for the 3680 basic 1:1 mappings of playback streams to output 3681 streams. 3682 */ 3683 3684 #define HDSPM_PLAYBACK_MIXER \ 3685 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3686 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \ 3687 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3688 .info = snd_hdspm_info_playback_mixer, \ 3689 .get = snd_hdspm_get_playback_mixer, \ 3690 .put = snd_hdspm_put_playback_mixer \ 3691 } 3692 3693 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol, 3694 struct snd_ctl_elem_info *uinfo) 3695 { 3696 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3697 uinfo->count = 1; 3698 uinfo->value.integer.min = 0; 3699 uinfo->value.integer.max = 64; 3700 uinfo->value.integer.step = 1; 3701 return 0; 3702 } 3703 3704 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol, 3705 struct snd_ctl_elem_value *ucontrol) 3706 { 3707 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3708 int channel; 3709 3710 channel = ucontrol->id.index - 1; 3711 3712 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3713 return -EINVAL; 3714 3715 guard(spinlock_irq)(&hdspm->lock); 3716 ucontrol->value.integer.value[0] = 3717 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN; 3718 3719 return 0; 3720 } 3721 3722 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol, 3723 struct snd_ctl_elem_value *ucontrol) 3724 { 3725 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3726 int change; 3727 int channel; 3728 int gain; 3729 3730 if (!snd_hdspm_use_is_exclusive(hdspm)) 3731 return -EBUSY; 3732 3733 channel = ucontrol->id.index - 1; 3734 3735 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3736 return -EINVAL; 3737 3738 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64; 3739 3740 guard(spinlock_irq)(&hdspm->lock); 3741 change = 3742 gain != hdspm_read_pb_gain(hdspm, channel, 3743 channel); 3744 if (change) 3745 hdspm_write_pb_gain(hdspm, channel, channel, 3746 gain); 3747 return change; 3748 } 3749 3750 #define HDSPM_SYNC_CHECK(xname, xindex) \ 3751 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3752 .name = xname, \ 3753 .private_value = xindex, \ 3754 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3755 .info = snd_hdspm_info_sync_check, \ 3756 .get = snd_hdspm_get_sync_check \ 3757 } 3758 3759 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \ 3760 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3761 .name = xname, \ 3762 .private_value = xindex, \ 3763 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3764 .info = snd_hdspm_tco_info_lock_check, \ 3765 .get = snd_hdspm_get_sync_check \ 3766 } 3767 3768 3769 3770 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol, 3771 struct snd_ctl_elem_info *uinfo) 3772 { 3773 static const char *const texts[] = { "No Lock", "Lock", "Sync", "N/A" }; 3774 ENUMERATED_CTL_INFO(uinfo, texts); 3775 return 0; 3776 } 3777 3778 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol, 3779 struct snd_ctl_elem_info *uinfo) 3780 { 3781 static const char *const texts[] = { "No Lock", "Lock" }; 3782 ENUMERATED_CTL_INFO(uinfo, texts); 3783 return 0; 3784 } 3785 3786 static int hdspm_wc_sync_check(struct hdspm *hdspm) 3787 { 3788 int status, status2; 3789 3790 switch (hdspm->io_type) { 3791 case AES32: 3792 status = hdspm_read(hdspm, HDSPM_statusRegister); 3793 if (status & HDSPM_AES32_wcLock) { 3794 if (status & HDSPM_AES32_wcSync) 3795 return 2; 3796 else 3797 return 1; 3798 } 3799 return 0; 3800 3801 case MADI: 3802 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3803 if (status2 & HDSPM_wcLock) { 3804 if (status2 & HDSPM_wcSync) 3805 return 2; 3806 else 3807 return 1; 3808 } 3809 return 0; 3810 3811 case RayDAT: 3812 case AIO: 3813 status = hdspm_read(hdspm, HDSPM_statusRegister); 3814 3815 if (status & 0x2000000) 3816 return 2; 3817 else if (status & 0x1000000) 3818 return 1; 3819 return 0; 3820 3821 case MADIface: 3822 break; 3823 } 3824 3825 3826 return 3; 3827 } 3828 3829 3830 static int hdspm_madi_sync_check(struct hdspm *hdspm) 3831 { 3832 int status = hdspm_read(hdspm, HDSPM_statusRegister); 3833 if (status & HDSPM_madiLock) { 3834 if (status & HDSPM_madiSync) 3835 return 2; 3836 else 3837 return 1; 3838 } 3839 return 0; 3840 } 3841 3842 3843 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx) 3844 { 3845 int status, lock, sync; 3846 3847 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3848 3849 lock = (status & (0x1<<idx)) ? 1 : 0; 3850 sync = (status & (0x100<<idx)) ? 1 : 0; 3851 3852 if (lock && sync) 3853 return 2; 3854 else if (lock) 3855 return 1; 3856 return 0; 3857 } 3858 3859 3860 static int hdspm_sync_in_sync_check(struct hdspm *hdspm) 3861 { 3862 int status, lock = 0, sync = 0; 3863 3864 switch (hdspm->io_type) { 3865 case RayDAT: 3866 case AIO: 3867 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3); 3868 lock = (status & 0x400) ? 1 : 0; 3869 sync = (status & 0x800) ? 1 : 0; 3870 break; 3871 3872 case MADI: 3873 status = hdspm_read(hdspm, HDSPM_statusRegister); 3874 lock = (status & HDSPM_syncInLock) ? 1 : 0; 3875 sync = (status & HDSPM_syncInSync) ? 1 : 0; 3876 break; 3877 3878 case AES32: 3879 status = hdspm_read(hdspm, HDSPM_statusRegister2); 3880 lock = (status & 0x100000) ? 1 : 0; 3881 sync = (status & 0x200000) ? 1 : 0; 3882 break; 3883 3884 case MADIface: 3885 break; 3886 } 3887 3888 if (lock && sync) 3889 return 2; 3890 else if (lock) 3891 return 1; 3892 3893 return 0; 3894 } 3895 3896 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx) 3897 { 3898 int status2, lock, sync; 3899 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3900 3901 lock = (status2 & (0x0080 >> idx)) ? 1 : 0; 3902 sync = (status2 & (0x8000 >> idx)) ? 1 : 0; 3903 3904 if (sync) 3905 return 2; 3906 else if (lock) 3907 return 1; 3908 return 0; 3909 } 3910 3911 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask) 3912 { 3913 u32 status; 3914 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3915 3916 return (status & mask) ? 1 : 0; 3917 } 3918 3919 3920 static int hdspm_tco_sync_check(struct hdspm *hdspm) 3921 { 3922 int status; 3923 3924 if (hdspm->tco) { 3925 switch (hdspm->io_type) { 3926 case MADI: 3927 status = hdspm_read(hdspm, HDSPM_statusRegister); 3928 if (status & HDSPM_tcoLockMadi) { 3929 if (status & HDSPM_tcoSync) 3930 return 2; 3931 else 3932 return 1; 3933 } 3934 return 0; 3935 case AES32: 3936 status = hdspm_read(hdspm, HDSPM_statusRegister); 3937 if (status & HDSPM_tcoLockAes) { 3938 if (status & HDSPM_tcoSync) 3939 return 2; 3940 else 3941 return 1; 3942 } 3943 return 0; 3944 case RayDAT: 3945 case AIO: 3946 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3947 3948 if (status & 0x8000000) 3949 return 2; /* Sync */ 3950 if (status & 0x4000000) 3951 return 1; /* Lock */ 3952 return 0; /* No signal */ 3953 3954 default: 3955 break; 3956 } 3957 } 3958 3959 return 3; /* N/A */ 3960 } 3961 3962 3963 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol, 3964 struct snd_ctl_elem_value *ucontrol) 3965 { 3966 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3967 int val = -1; 3968 3969 switch (hdspm->io_type) { 3970 case RayDAT: 3971 switch (kcontrol->private_value) { 3972 case 0: /* WC */ 3973 val = hdspm_wc_sync_check(hdspm); break; 3974 case 7: /* TCO */ 3975 val = hdspm_tco_sync_check(hdspm); break; 3976 case 8: /* SYNC IN */ 3977 val = hdspm_sync_in_sync_check(hdspm); break; 3978 default: 3979 val = hdspm_s1_sync_check(hdspm, 3980 kcontrol->private_value-1); 3981 } 3982 break; 3983 3984 case AIO: 3985 switch (kcontrol->private_value) { 3986 case 0: /* WC */ 3987 val = hdspm_wc_sync_check(hdspm); break; 3988 case 4: /* TCO */ 3989 val = hdspm_tco_sync_check(hdspm); break; 3990 case 5: /* SYNC IN */ 3991 val = hdspm_sync_in_sync_check(hdspm); break; 3992 default: 3993 val = hdspm_s1_sync_check(hdspm, 3994 kcontrol->private_value-1); 3995 } 3996 break; 3997 3998 case MADI: 3999 switch (kcontrol->private_value) { 4000 case 0: /* WC */ 4001 val = hdspm_wc_sync_check(hdspm); break; 4002 case 1: /* MADI */ 4003 val = hdspm_madi_sync_check(hdspm); break; 4004 case 2: /* TCO */ 4005 val = hdspm_tco_sync_check(hdspm); break; 4006 case 3: /* SYNC_IN */ 4007 val = hdspm_sync_in_sync_check(hdspm); break; 4008 } 4009 break; 4010 4011 case MADIface: 4012 val = hdspm_madi_sync_check(hdspm); /* MADI */ 4013 break; 4014 4015 case AES32: 4016 switch (kcontrol->private_value) { 4017 case 0: /* WC */ 4018 val = hdspm_wc_sync_check(hdspm); break; 4019 case 9: /* TCO */ 4020 val = hdspm_tco_sync_check(hdspm); break; 4021 case 10 /* SYNC IN */: 4022 val = hdspm_sync_in_sync_check(hdspm); break; 4023 default: /* AES1 to AES8 */ 4024 val = hdspm_aes_sync_check(hdspm, 4025 kcontrol->private_value-1); 4026 } 4027 break; 4028 4029 } 4030 4031 if (hdspm->tco) { 4032 switch (kcontrol->private_value) { 4033 case 11: 4034 /* Check TCO for lock state of its current input */ 4035 val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock); 4036 break; 4037 case 12: 4038 /* Check TCO for valid time code on LTC input. */ 4039 val = hdspm_tco_input_check(hdspm, 4040 HDSPM_TCO1_LTC_Input_valid); 4041 break; 4042 default: 4043 break; 4044 } 4045 } 4046 4047 if (-1 == val) 4048 val = 3; 4049 4050 ucontrol->value.enumerated.item[0] = val; 4051 return 0; 4052 } 4053 4054 4055 4056 /* 4057 * TCO controls 4058 */ 4059 static void hdspm_tco_write(struct hdspm *hdspm) 4060 { 4061 unsigned int tc[4] = { 0, 0, 0, 0}; 4062 4063 switch (hdspm->tco->input) { 4064 case 0: 4065 tc[2] |= HDSPM_TCO2_set_input_MSB; 4066 break; 4067 case 1: 4068 tc[2] |= HDSPM_TCO2_set_input_LSB; 4069 break; 4070 default: 4071 break; 4072 } 4073 4074 switch (hdspm->tco->framerate) { 4075 case 1: 4076 tc[1] |= HDSPM_TCO1_LTC_Format_LSB; 4077 break; 4078 case 2: 4079 tc[1] |= HDSPM_TCO1_LTC_Format_MSB; 4080 break; 4081 case 3: 4082 tc[1] |= HDSPM_TCO1_LTC_Format_MSB + 4083 HDSPM_TCO1_set_drop_frame_flag; 4084 break; 4085 case 4: 4086 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 4087 HDSPM_TCO1_LTC_Format_MSB; 4088 break; 4089 case 5: 4090 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 4091 HDSPM_TCO1_LTC_Format_MSB + 4092 HDSPM_TCO1_set_drop_frame_flag; 4093 break; 4094 default: 4095 break; 4096 } 4097 4098 switch (hdspm->tco->wordclock) { 4099 case 1: 4100 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB; 4101 break; 4102 case 2: 4103 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB; 4104 break; 4105 default: 4106 break; 4107 } 4108 4109 switch (hdspm->tco->samplerate) { 4110 case 1: 4111 tc[2] |= HDSPM_TCO2_set_freq; 4112 break; 4113 case 2: 4114 tc[2] |= HDSPM_TCO2_set_freq_from_app; 4115 break; 4116 default: 4117 break; 4118 } 4119 4120 switch (hdspm->tco->pull) { 4121 case 1: 4122 tc[2] |= HDSPM_TCO2_set_pull_up; 4123 break; 4124 case 2: 4125 tc[2] |= HDSPM_TCO2_set_pull_down; 4126 break; 4127 case 3: 4128 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4; 4129 break; 4130 case 4: 4131 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4; 4132 break; 4133 default: 4134 break; 4135 } 4136 4137 if (1 == hdspm->tco->term) { 4138 tc[2] |= HDSPM_TCO2_set_term_75R; 4139 } 4140 4141 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]); 4142 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]); 4143 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]); 4144 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]); 4145 } 4146 4147 4148 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \ 4149 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4150 .name = xname, \ 4151 .index = xindex, \ 4152 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4153 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4154 .info = snd_hdspm_info_tco_sample_rate, \ 4155 .get = snd_hdspm_get_tco_sample_rate, \ 4156 .put = snd_hdspm_put_tco_sample_rate \ 4157 } 4158 4159 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol, 4160 struct snd_ctl_elem_info *uinfo) 4161 { 4162 /* TODO freq from app could be supported here, see tco->samplerate */ 4163 static const char *const texts[] = { "44.1 kHz", "48 kHz" }; 4164 ENUMERATED_CTL_INFO(uinfo, texts); 4165 return 0; 4166 } 4167 4168 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol, 4169 struct snd_ctl_elem_value *ucontrol) 4170 { 4171 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4172 4173 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate; 4174 4175 return 0; 4176 } 4177 4178 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol, 4179 struct snd_ctl_elem_value *ucontrol) 4180 { 4181 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4182 4183 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) { 4184 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0]; 4185 4186 hdspm_tco_write(hdspm); 4187 4188 return 1; 4189 } 4190 4191 return 0; 4192 } 4193 4194 4195 #define HDSPM_TCO_PULL(xname, xindex) \ 4196 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4197 .name = xname, \ 4198 .index = xindex, \ 4199 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4200 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4201 .info = snd_hdspm_info_tco_pull, \ 4202 .get = snd_hdspm_get_tco_pull, \ 4203 .put = snd_hdspm_put_tco_pull \ 4204 } 4205 4206 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol, 4207 struct snd_ctl_elem_info *uinfo) 4208 { 4209 static const char *const texts[] = { "0", "+ 0.1 %", "- 0.1 %", 4210 "+ 4 %", "- 4 %" }; 4211 ENUMERATED_CTL_INFO(uinfo, texts); 4212 return 0; 4213 } 4214 4215 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol, 4216 struct snd_ctl_elem_value *ucontrol) 4217 { 4218 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4219 4220 ucontrol->value.enumerated.item[0] = hdspm->tco->pull; 4221 4222 return 0; 4223 } 4224 4225 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol, 4226 struct snd_ctl_elem_value *ucontrol) 4227 { 4228 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4229 4230 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) { 4231 hdspm->tco->pull = ucontrol->value.enumerated.item[0]; 4232 4233 hdspm_tco_write(hdspm); 4234 4235 return 1; 4236 } 4237 4238 return 0; 4239 } 4240 4241 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \ 4242 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4243 .name = xname, \ 4244 .index = xindex, \ 4245 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4246 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4247 .info = snd_hdspm_info_tco_wck_conversion, \ 4248 .get = snd_hdspm_get_tco_wck_conversion, \ 4249 .put = snd_hdspm_put_tco_wck_conversion \ 4250 } 4251 4252 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4253 struct snd_ctl_elem_info *uinfo) 4254 { 4255 static const char *const texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" }; 4256 ENUMERATED_CTL_INFO(uinfo, texts); 4257 return 0; 4258 } 4259 4260 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4261 struct snd_ctl_elem_value *ucontrol) 4262 { 4263 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4264 4265 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock; 4266 4267 return 0; 4268 } 4269 4270 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4271 struct snd_ctl_elem_value *ucontrol) 4272 { 4273 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4274 4275 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) { 4276 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0]; 4277 4278 hdspm_tco_write(hdspm); 4279 4280 return 1; 4281 } 4282 4283 return 0; 4284 } 4285 4286 4287 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \ 4288 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4289 .name = xname, \ 4290 .index = xindex, \ 4291 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4292 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4293 .info = snd_hdspm_info_tco_frame_rate, \ 4294 .get = snd_hdspm_get_tco_frame_rate, \ 4295 .put = snd_hdspm_put_tco_frame_rate \ 4296 } 4297 4298 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol, 4299 struct snd_ctl_elem_info *uinfo) 4300 { 4301 static const char *const texts[] = { "24 fps", "25 fps", "29.97fps", 4302 "29.97 dfps", "30 fps", "30 dfps" }; 4303 ENUMERATED_CTL_INFO(uinfo, texts); 4304 return 0; 4305 } 4306 4307 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol, 4308 struct snd_ctl_elem_value *ucontrol) 4309 { 4310 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4311 4312 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate; 4313 4314 return 0; 4315 } 4316 4317 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol, 4318 struct snd_ctl_elem_value *ucontrol) 4319 { 4320 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4321 4322 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) { 4323 hdspm->tco->framerate = ucontrol->value.enumerated.item[0]; 4324 4325 hdspm_tco_write(hdspm); 4326 4327 return 1; 4328 } 4329 4330 return 0; 4331 } 4332 4333 4334 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \ 4335 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4336 .name = xname, \ 4337 .index = xindex, \ 4338 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4339 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4340 .info = snd_hdspm_info_tco_sync_source, \ 4341 .get = snd_hdspm_get_tco_sync_source, \ 4342 .put = snd_hdspm_put_tco_sync_source \ 4343 } 4344 4345 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol, 4346 struct snd_ctl_elem_info *uinfo) 4347 { 4348 static const char *const texts[] = { "LTC", "Video", "WCK" }; 4349 ENUMERATED_CTL_INFO(uinfo, texts); 4350 return 0; 4351 } 4352 4353 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol, 4354 struct snd_ctl_elem_value *ucontrol) 4355 { 4356 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4357 4358 ucontrol->value.enumerated.item[0] = hdspm->tco->input; 4359 4360 return 0; 4361 } 4362 4363 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol, 4364 struct snd_ctl_elem_value *ucontrol) 4365 { 4366 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4367 4368 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) { 4369 hdspm->tco->input = ucontrol->value.enumerated.item[0]; 4370 4371 hdspm_tco_write(hdspm); 4372 4373 return 1; 4374 } 4375 4376 return 0; 4377 } 4378 4379 4380 #define HDSPM_TCO_WORD_TERM(xname, xindex) \ 4381 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4382 .name = xname, \ 4383 .index = xindex, \ 4384 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4385 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4386 .info = snd_hdspm_info_tco_word_term, \ 4387 .get = snd_hdspm_get_tco_word_term, \ 4388 .put = snd_hdspm_put_tco_word_term \ 4389 } 4390 4391 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol, 4392 struct snd_ctl_elem_info *uinfo) 4393 { 4394 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 4395 uinfo->count = 1; 4396 uinfo->value.integer.min = 0; 4397 uinfo->value.integer.max = 1; 4398 4399 return 0; 4400 } 4401 4402 4403 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol, 4404 struct snd_ctl_elem_value *ucontrol) 4405 { 4406 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4407 4408 ucontrol->value.integer.value[0] = hdspm->tco->term; 4409 4410 return 0; 4411 } 4412 4413 4414 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol, 4415 struct snd_ctl_elem_value *ucontrol) 4416 { 4417 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4418 4419 if (hdspm->tco->term != ucontrol->value.integer.value[0]) { 4420 hdspm->tco->term = ucontrol->value.integer.value[0]; 4421 4422 hdspm_tco_write(hdspm); 4423 4424 return 1; 4425 } 4426 4427 return 0; 4428 } 4429 4430 4431 4432 4433 static const struct snd_kcontrol_new snd_hdspm_controls_madi[] = { 4434 HDSPM_MIXER("Mixer", 0), 4435 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4436 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4437 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4438 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4439 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4440 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4441 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4442 HDSPM_SYNC_CHECK("MADI SyncCheck", 1), 4443 HDSPM_SYNC_CHECK("TCO SyncCheck", 2), 4444 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3), 4445 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4446 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4447 HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX), 4448 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4449 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4450 HDSPM_INPUT_SELECT("Input Select", 0), 4451 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4452 }; 4453 4454 4455 static const struct snd_kcontrol_new snd_hdspm_controls_madiface[] = { 4456 HDSPM_MIXER("Mixer", 0), 4457 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4458 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4459 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4460 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4461 HDSPM_SYNC_CHECK("MADI SyncCheck", 0), 4462 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4463 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4464 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4465 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4466 }; 4467 4468 static const struct snd_kcontrol_new snd_hdspm_controls_aio[] = { 4469 HDSPM_MIXER("Mixer", 0), 4470 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4471 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4472 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4473 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4474 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4475 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4476 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4477 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4478 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3), 4479 HDSPM_SYNC_CHECK("TCO SyncCheck", 4), 4480 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5), 4481 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4482 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4483 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4484 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3), 4485 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4), 4486 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5), 4487 HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0), 4488 HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt), 4489 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro), 4490 HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1), 4491 HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db), 4492 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48), 4493 HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0), 4494 HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0), 4495 HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0) 4496 4497 /* 4498 HDSPM_INPUT_SELECT("Input Select", 0), 4499 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0), 4500 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0); 4501 HDSPM_SPDIF_IN("SPDIF In", 0); 4502 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0); 4503 HDSPM_INPUT_LEVEL("Input Level", 0); 4504 HDSPM_OUTPUT_LEVEL("Output Level", 0); 4505 HDSPM_PHONES("Phones", 0); 4506 */ 4507 }; 4508 4509 static const struct snd_kcontrol_new snd_hdspm_controls_raydat[] = { 4510 HDSPM_MIXER("Mixer", 0), 4511 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4512 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0), 4513 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0), 4514 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4515 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4516 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4517 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4518 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3), 4519 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4), 4520 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5), 4521 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6), 4522 HDSPM_SYNC_CHECK("TCO SyncCheck", 7), 4523 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8), 4524 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4525 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4526 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4527 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3), 4528 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4), 4529 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5), 4530 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6), 4531 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7), 4532 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8), 4533 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro), 4534 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48) 4535 }; 4536 4537 static const struct snd_kcontrol_new snd_hdspm_controls_aes32[] = { 4538 HDSPM_MIXER("Mixer", 0), 4539 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4540 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4541 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4542 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4543 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4544 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 11), 4545 HDSPM_SYNC_CHECK("WC Sync Check", 0), 4546 HDSPM_SYNC_CHECK("AES1 Sync Check", 1), 4547 HDSPM_SYNC_CHECK("AES2 Sync Check", 2), 4548 HDSPM_SYNC_CHECK("AES3 Sync Check", 3), 4549 HDSPM_SYNC_CHECK("AES4 Sync Check", 4), 4550 HDSPM_SYNC_CHECK("AES5 Sync Check", 5), 4551 HDSPM_SYNC_CHECK("AES6 Sync Check", 6), 4552 HDSPM_SYNC_CHECK("AES7 Sync Check", 7), 4553 HDSPM_SYNC_CHECK("AES8 Sync Check", 8), 4554 HDSPM_SYNC_CHECK("TCO Sync Check", 9), 4555 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10), 4556 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4557 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1), 4558 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2), 4559 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3), 4560 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4), 4561 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5), 4562 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6), 4563 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7), 4564 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8), 4565 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9), 4566 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10), 4567 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4568 HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis), 4569 HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby), 4570 HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional), 4571 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4572 HDSPM_DS_WIRE("Double Speed Wire Mode", 0), 4573 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0), 4574 }; 4575 4576 4577 4578 /* Control elements for the optional TCO module */ 4579 static const struct snd_kcontrol_new snd_hdspm_controls_tco[] = { 4580 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0), 4581 HDSPM_TCO_PULL("TCO Pull", 0), 4582 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0), 4583 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0), 4584 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0), 4585 HDSPM_TCO_WORD_TERM("TCO Word Term", 0), 4586 HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11), 4587 HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12), 4588 HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate"), 4589 HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format") 4590 }; 4591 4592 4593 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER; 4594 4595 4596 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm) 4597 { 4598 int i; 4599 4600 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) { 4601 if (hdspm->system_sample_rate > 48000) { 4602 hdspm->playback_mixer_ctls[i]->vd[0].access = 4603 SNDRV_CTL_ELEM_ACCESS_INACTIVE | 4604 SNDRV_CTL_ELEM_ACCESS_READ | 4605 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4606 } else { 4607 hdspm->playback_mixer_ctls[i]->vd[0].access = 4608 SNDRV_CTL_ELEM_ACCESS_READWRITE | 4609 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4610 } 4611 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE | 4612 SNDRV_CTL_EVENT_MASK_INFO, 4613 &hdspm->playback_mixer_ctls[i]->id); 4614 } 4615 4616 return 0; 4617 } 4618 4619 4620 static int snd_hdspm_create_controls(struct snd_card *card, 4621 struct hdspm *hdspm) 4622 { 4623 unsigned int idx, limit; 4624 int err; 4625 struct snd_kcontrol *kctl; 4626 const struct snd_kcontrol_new *list = NULL; 4627 4628 switch (hdspm->io_type) { 4629 case MADI: 4630 list = snd_hdspm_controls_madi; 4631 limit = ARRAY_SIZE(snd_hdspm_controls_madi); 4632 break; 4633 case MADIface: 4634 list = snd_hdspm_controls_madiface; 4635 limit = ARRAY_SIZE(snd_hdspm_controls_madiface); 4636 break; 4637 case AIO: 4638 list = snd_hdspm_controls_aio; 4639 limit = ARRAY_SIZE(snd_hdspm_controls_aio); 4640 break; 4641 case RayDAT: 4642 list = snd_hdspm_controls_raydat; 4643 limit = ARRAY_SIZE(snd_hdspm_controls_raydat); 4644 break; 4645 case AES32: 4646 list = snd_hdspm_controls_aes32; 4647 limit = ARRAY_SIZE(snd_hdspm_controls_aes32); 4648 break; 4649 } 4650 4651 if (list) { 4652 for (idx = 0; idx < limit; idx++) { 4653 err = snd_ctl_add(card, 4654 snd_ctl_new1(&list[idx], hdspm)); 4655 if (err < 0) 4656 return err; 4657 } 4658 } 4659 4660 4661 /* create simple 1:1 playback mixer controls */ 4662 snd_hdspm_playback_mixer.name = "Chn"; 4663 if (hdspm->system_sample_rate >= 128000) { 4664 limit = hdspm->qs_out_channels; 4665 } else if (hdspm->system_sample_rate >= 64000) { 4666 limit = hdspm->ds_out_channels; 4667 } else { 4668 limit = hdspm->ss_out_channels; 4669 } 4670 for (idx = 0; idx < limit; ++idx) { 4671 snd_hdspm_playback_mixer.index = idx + 1; 4672 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm); 4673 err = snd_ctl_add(card, kctl); 4674 if (err < 0) 4675 return err; 4676 hdspm->playback_mixer_ctls[idx] = kctl; 4677 } 4678 4679 4680 if (hdspm->tco) { 4681 /* add tco control elements */ 4682 list = snd_hdspm_controls_tco; 4683 limit = ARRAY_SIZE(snd_hdspm_controls_tco); 4684 for (idx = 0; idx < limit; idx++) { 4685 err = snd_ctl_add(card, 4686 snd_ctl_new1(&list[idx], hdspm)); 4687 if (err < 0) 4688 return err; 4689 } 4690 } 4691 4692 return 0; 4693 } 4694 4695 /*------------------------------------------------------------ 4696 /proc interface 4697 ------------------------------------------------------------*/ 4698 4699 static void 4700 snd_hdspm_proc_read_tco(struct snd_info_entry *entry, 4701 struct snd_info_buffer *buffer) 4702 { 4703 struct hdspm *hdspm = entry->private_data; 4704 unsigned int status, control; 4705 int a, ltc, frames, seconds, minutes, hours; 4706 unsigned int period; 4707 u64 freq_const = 0; 4708 u32 rate; 4709 4710 snd_iprintf(buffer, "--- TCO ---\n"); 4711 4712 status = hdspm_read(hdspm, HDSPM_statusRegister); 4713 control = hdspm->control_register; 4714 4715 4716 if (status & HDSPM_tco_detect) { 4717 snd_iprintf(buffer, "TCO module detected.\n"); 4718 a = hdspm_read(hdspm, HDSPM_RD_TCO+4); 4719 if (a & HDSPM_TCO1_LTC_Input_valid) { 4720 snd_iprintf(buffer, " LTC valid, "); 4721 switch (a & (HDSPM_TCO1_LTC_Format_LSB | 4722 HDSPM_TCO1_LTC_Format_MSB)) { 4723 case 0: 4724 snd_iprintf(buffer, "24 fps, "); 4725 break; 4726 case HDSPM_TCO1_LTC_Format_LSB: 4727 snd_iprintf(buffer, "25 fps, "); 4728 break; 4729 case HDSPM_TCO1_LTC_Format_MSB: 4730 snd_iprintf(buffer, "29.97 fps, "); 4731 break; 4732 default: 4733 snd_iprintf(buffer, "30 fps, "); 4734 break; 4735 } 4736 if (a & HDSPM_TCO1_set_drop_frame_flag) { 4737 snd_iprintf(buffer, "drop frame\n"); 4738 } else { 4739 snd_iprintf(buffer, "full frame\n"); 4740 } 4741 } else { 4742 snd_iprintf(buffer, " no LTC\n"); 4743 } 4744 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) { 4745 snd_iprintf(buffer, " Video: NTSC\n"); 4746 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) { 4747 snd_iprintf(buffer, " Video: PAL\n"); 4748 } else { 4749 snd_iprintf(buffer, " No video\n"); 4750 } 4751 if (a & HDSPM_TCO1_TCO_lock) { 4752 snd_iprintf(buffer, " Sync: lock\n"); 4753 } else { 4754 snd_iprintf(buffer, " Sync: no lock\n"); 4755 } 4756 4757 switch (hdspm->io_type) { 4758 case MADI: 4759 case AES32: 4760 freq_const = 110069313433624ULL; 4761 break; 4762 case RayDAT: 4763 case AIO: 4764 freq_const = 104857600000000ULL; 4765 break; 4766 case MADIface: 4767 break; /* no TCO possible */ 4768 } 4769 4770 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 4771 snd_iprintf(buffer, " period: %u\n", period); 4772 4773 4774 /* rate = freq_const/period; */ 4775 rate = div_u64(freq_const, period); 4776 4777 if (control & HDSPM_QuadSpeed) { 4778 rate *= 4; 4779 } else if (control & HDSPM_DoubleSpeed) { 4780 rate *= 2; 4781 } 4782 4783 snd_iprintf(buffer, " Frequency: %u Hz\n", 4784 (unsigned int) rate); 4785 4786 ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 4787 frames = ltc & 0xF; 4788 ltc >>= 4; 4789 frames += (ltc & 0x3) * 10; 4790 ltc >>= 4; 4791 seconds = ltc & 0xF; 4792 ltc >>= 4; 4793 seconds += (ltc & 0x7) * 10; 4794 ltc >>= 4; 4795 minutes = ltc & 0xF; 4796 ltc >>= 4; 4797 minutes += (ltc & 0x7) * 10; 4798 ltc >>= 4; 4799 hours = ltc & 0xF; 4800 ltc >>= 4; 4801 hours += (ltc & 0x3) * 10; 4802 snd_iprintf(buffer, 4803 " LTC In: %02d:%02d:%02d:%02d\n", 4804 hours, minutes, seconds, frames); 4805 4806 } else { 4807 snd_iprintf(buffer, "No TCO module detected.\n"); 4808 } 4809 } 4810 4811 static void 4812 snd_hdspm_proc_read_madi(struct snd_info_entry *entry, 4813 struct snd_info_buffer *buffer) 4814 { 4815 struct hdspm *hdspm = entry->private_data; 4816 unsigned int status, status2; 4817 4818 char *pref_sync_ref; 4819 char *autosync_ref; 4820 char *system_clock_mode; 4821 int x, x2; 4822 4823 status = hdspm_read(hdspm, HDSPM_statusRegister); 4824 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4825 4826 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n", 4827 hdspm->card_name, hdspm->card->number + 1, 4828 hdspm->firmware_rev, 4829 (status2 & HDSPM_version0) | 4830 (status2 & HDSPM_version1) | (status2 & 4831 HDSPM_version2)); 4832 4833 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n", 4834 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF, 4835 hdspm->serial); 4836 4837 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4838 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4839 4840 snd_iprintf(buffer, "--- System ---\n"); 4841 4842 snd_iprintf(buffer, 4843 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4844 status & HDSPM_audioIRQPending, 4845 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4846 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4847 hdspm->irq_count); 4848 snd_iprintf(buffer, 4849 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4850 "estimated= %ld (bytes)\n", 4851 ((status & HDSPM_BufferID) ? 1 : 0), 4852 (status & HDSPM_BufferPositionMask), 4853 (status & HDSPM_BufferPositionMask) % 4854 (2 * (int)hdspm->period_bytes), 4855 ((status & HDSPM_BufferPositionMask) - 64) % 4856 (2 * (int)hdspm->period_bytes), 4857 (long) hdspm_hw_pointer(hdspm) * 4); 4858 4859 snd_iprintf(buffer, 4860 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4861 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4862 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4863 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4864 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4865 snd_iprintf(buffer, 4866 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4867 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4868 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4869 snd_iprintf(buffer, 4870 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4871 "status2=0x%x\n", 4872 hdspm->control_register, hdspm->control2_register, 4873 status, status2); 4874 4875 4876 snd_iprintf(buffer, "--- Settings ---\n"); 4877 4878 x = hdspm_get_latency(hdspm); 4879 4880 snd_iprintf(buffer, 4881 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4882 x, (unsigned long) hdspm->period_bytes); 4883 4884 snd_iprintf(buffer, "Line out: %s\n", 4885 str_on_off(hdspm->control_register & HDSPM_LineOut)); 4886 4887 snd_iprintf(buffer, 4888 "ClearTrackMarker = %s, Transmit in %s Channel Mode, " 4889 "Auto Input %s\n", 4890 str_on_off(hdspm->control_register & HDSPM_clr_tms), 4891 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56", 4892 str_on_off(hdspm->control_register & HDSPM_AutoInp)); 4893 4894 4895 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) 4896 system_clock_mode = "AutoSync"; 4897 else 4898 system_clock_mode = "Master"; 4899 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode); 4900 4901 switch (hdspm_pref_sync_ref(hdspm)) { 4902 case HDSPM_SYNC_FROM_WORD: 4903 pref_sync_ref = "Word Clock"; 4904 break; 4905 case HDSPM_SYNC_FROM_MADI: 4906 pref_sync_ref = "MADI Sync"; 4907 break; 4908 case HDSPM_SYNC_FROM_TCO: 4909 pref_sync_ref = "TCO"; 4910 break; 4911 case HDSPM_SYNC_FROM_SYNC_IN: 4912 pref_sync_ref = "Sync In"; 4913 break; 4914 default: 4915 pref_sync_ref = "XXXX Clock"; 4916 break; 4917 } 4918 snd_iprintf(buffer, "Preferred Sync Reference: %s\n", 4919 pref_sync_ref); 4920 4921 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4922 hdspm->system_sample_rate); 4923 4924 4925 snd_iprintf(buffer, "--- Status:\n"); 4926 4927 x = status & HDSPM_madiSync; 4928 x2 = status2 & HDSPM_wcSync; 4929 4930 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n", 4931 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") : 4932 "NoLock", 4933 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") : 4934 "NoLock"); 4935 4936 switch (hdspm_autosync_ref(hdspm)) { 4937 case HDSPM_AUTOSYNC_FROM_SYNC_IN: 4938 autosync_ref = "Sync In"; 4939 break; 4940 case HDSPM_AUTOSYNC_FROM_TCO: 4941 autosync_ref = "TCO"; 4942 break; 4943 case HDSPM_AUTOSYNC_FROM_WORD: 4944 autosync_ref = "Word Clock"; 4945 break; 4946 case HDSPM_AUTOSYNC_FROM_MADI: 4947 autosync_ref = "MADI Sync"; 4948 break; 4949 case HDSPM_AUTOSYNC_FROM_NONE: 4950 autosync_ref = "Input not valid"; 4951 break; 4952 default: 4953 autosync_ref = "---"; 4954 break; 4955 } 4956 snd_iprintf(buffer, 4957 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n", 4958 autosync_ref, hdspm_external_sample_rate(hdspm), 4959 (status & HDSPM_madiFreqMask) >> 22, 4960 (status2 & HDSPM_wcFreqMask) >> 5); 4961 4962 snd_iprintf(buffer, "Input: %s, Mode=%s\n", 4963 (status & HDSPM_AB_int) ? "Coax" : "Optical", 4964 (status & HDSPM_RX_64ch) ? "64 channels" : 4965 "56 channels"); 4966 4967 /* call readout function for TCO specific status */ 4968 snd_hdspm_proc_read_tco(entry, buffer); 4969 4970 snd_iprintf(buffer, "\n"); 4971 } 4972 4973 static void 4974 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry, 4975 struct snd_info_buffer *buffer) 4976 { 4977 struct hdspm *hdspm = entry->private_data; 4978 unsigned int status; 4979 unsigned int status2; 4980 unsigned int timecode; 4981 unsigned int wcLock, wcSync; 4982 int pref_syncref; 4983 char *autosync_ref; 4984 int x; 4985 4986 status = hdspm_read(hdspm, HDSPM_statusRegister); 4987 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4988 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 4989 4990 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n", 4991 hdspm->card_name, hdspm->card->number + 1, 4992 hdspm->firmware_rev); 4993 4994 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4995 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4996 4997 snd_iprintf(buffer, "--- System ---\n"); 4998 4999 snd_iprintf(buffer, 5000 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 5001 status & HDSPM_audioIRQPending, 5002 (status & HDSPM_midi0IRQPending) ? 1 : 0, 5003 (status & HDSPM_midi1IRQPending) ? 1 : 0, 5004 hdspm->irq_count); 5005 snd_iprintf(buffer, 5006 "HW pointer: id = %d, rawptr = %d (%d->%d) " 5007 "estimated= %ld (bytes)\n", 5008 ((status & HDSPM_BufferID) ? 1 : 0), 5009 (status & HDSPM_BufferPositionMask), 5010 (status & HDSPM_BufferPositionMask) % 5011 (2 * (int)hdspm->period_bytes), 5012 ((status & HDSPM_BufferPositionMask) - 64) % 5013 (2 * (int)hdspm->period_bytes), 5014 (long) hdspm_hw_pointer(hdspm) * 4); 5015 5016 snd_iprintf(buffer, 5017 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 5018 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 5019 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 5020 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 5021 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 5022 snd_iprintf(buffer, 5023 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 5024 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 5025 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 5026 snd_iprintf(buffer, 5027 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 5028 "status2=0x%x\n", 5029 hdspm->control_register, hdspm->control2_register, 5030 status, status2); 5031 5032 snd_iprintf(buffer, "--- Settings ---\n"); 5033 5034 x = hdspm_get_latency(hdspm); 5035 5036 snd_iprintf(buffer, 5037 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 5038 x, (unsigned long) hdspm->period_bytes); 5039 5040 snd_iprintf(buffer, "Line out: %s\n", 5041 (hdspm-> 5042 control_register & HDSPM_LineOut) ? "on " : "off"); 5043 5044 snd_iprintf(buffer, 5045 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n", 5046 str_on_off(hdspm->control_register & HDSPM_clr_tms), 5047 str_on_off(hdspm->control_register & HDSPM_Emphasis), 5048 str_on_off(hdspm->control_register & HDSPM_Dolby)); 5049 5050 5051 pref_syncref = hdspm_pref_sync_ref(hdspm); 5052 if (pref_syncref == 0) 5053 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n"); 5054 else 5055 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n", 5056 pref_syncref); 5057 5058 snd_iprintf(buffer, "System Clock Frequency: %d\n", 5059 hdspm->system_sample_rate); 5060 5061 snd_iprintf(buffer, "Double speed: %s\n", 5062 hdspm->control_register & HDSPM_DS_DoubleWire? 5063 "Double wire" : "Single wire"); 5064 snd_iprintf(buffer, "Quad speed: %s\n", 5065 hdspm->control_register & HDSPM_QS_DoubleWire? 5066 "Double wire" : 5067 hdspm->control_register & HDSPM_QS_QuadWire? 5068 "Quad wire" : "Single wire"); 5069 5070 snd_iprintf(buffer, "--- Status:\n"); 5071 5072 wcLock = status & HDSPM_AES32_wcLock; 5073 wcSync = wcLock && (status & HDSPM_AES32_wcSync); 5074 5075 snd_iprintf(buffer, "Word: %s Frequency: %d\n", 5076 (wcLock) ? (wcSync ? "Sync " : "Lock ") : "No Lock", 5077 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF)); 5078 5079 for (x = 0; x < 8; x++) { 5080 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n", 5081 x+1, 5082 (status2 & (HDSPM_LockAES >> x)) ? 5083 "Sync " : "No Lock", 5084 HDSPM_bit2freq((timecode >> (4*x)) & 0xF)); 5085 } 5086 5087 switch (hdspm_autosync_ref(hdspm)) { 5088 case HDSPM_AES32_AUTOSYNC_FROM_NONE: 5089 autosync_ref = "None"; break; 5090 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 5091 autosync_ref = "Word Clock"; break; 5092 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 5093 autosync_ref = "AES1"; break; 5094 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 5095 autosync_ref = "AES2"; break; 5096 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 5097 autosync_ref = "AES3"; break; 5098 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 5099 autosync_ref = "AES4"; break; 5100 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 5101 autosync_ref = "AES5"; break; 5102 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 5103 autosync_ref = "AES6"; break; 5104 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 5105 autosync_ref = "AES7"; break; 5106 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 5107 autosync_ref = "AES8"; break; 5108 case HDSPM_AES32_AUTOSYNC_FROM_TCO: 5109 autosync_ref = "TCO"; break; 5110 case HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN: 5111 autosync_ref = "Sync In"; break; 5112 default: 5113 autosync_ref = "---"; break; 5114 } 5115 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref); 5116 5117 /* call readout function for TCO specific status */ 5118 snd_hdspm_proc_read_tco(entry, buffer); 5119 5120 snd_iprintf(buffer, "\n"); 5121 } 5122 5123 static void 5124 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry, 5125 struct snd_info_buffer *buffer) 5126 { 5127 struct hdspm *hdspm = entry->private_data; 5128 unsigned int status1, status2, status3, i; 5129 unsigned int lock, sync; 5130 5131 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */ 5132 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */ 5133 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */ 5134 5135 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1); 5136 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2); 5137 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3); 5138 5139 5140 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n"); 5141 5142 snd_iprintf(buffer, "Clock mode : %s\n", 5143 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave"); 5144 snd_iprintf(buffer, "System frequency: %d Hz\n", 5145 hdspm_get_system_sample_rate(hdspm)); 5146 5147 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n"); 5148 5149 lock = 0x1; 5150 sync = 0x100; 5151 5152 for (i = 0; i < 8; i++) { 5153 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n", 5154 i, 5155 (status1 & lock) ? 1 : 0, 5156 (status1 & sync) ? 1 : 0, 5157 texts_freq[(status2 >> (i * 4)) & 0xF]); 5158 5159 lock = lock<<1; 5160 sync = sync<<1; 5161 } 5162 5163 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n", 5164 (status1 & 0x1000000) ? 1 : 0, 5165 (status1 & 0x2000000) ? 1 : 0, 5166 texts_freq[(status1 >> 16) & 0xF]); 5167 5168 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n", 5169 (status1 & 0x4000000) ? 1 : 0, 5170 (status1 & 0x8000000) ? 1 : 0, 5171 texts_freq[(status1 >> 20) & 0xF]); 5172 5173 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n", 5174 (status3 & 0x400) ? 1 : 0, 5175 (status3 & 0x800) ? 1 : 0, 5176 texts_freq[(status2 >> 12) & 0xF]); 5177 5178 } 5179 5180 #ifdef CONFIG_SND_DEBUG 5181 static void 5182 snd_hdspm_proc_read_debug(struct snd_info_entry *entry, 5183 struct snd_info_buffer *buffer) 5184 { 5185 struct hdspm *hdspm = entry->private_data; 5186 5187 int j,i; 5188 5189 for (i = 0; i < 256 /* 1024*64 */; i += j) { 5190 snd_iprintf(buffer, "0x%08X: ", i); 5191 for (j = 0; j < 16; j += 4) 5192 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j)); 5193 snd_iprintf(buffer, "\n"); 5194 } 5195 } 5196 #endif 5197 5198 5199 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry, 5200 struct snd_info_buffer *buffer) 5201 { 5202 struct hdspm *hdspm = entry->private_data; 5203 int i; 5204 5205 snd_iprintf(buffer, "# generated by hdspm\n"); 5206 5207 for (i = 0; i < hdspm->max_channels_in; i++) { 5208 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]); 5209 } 5210 } 5211 5212 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry, 5213 struct snd_info_buffer *buffer) 5214 { 5215 struct hdspm *hdspm = entry->private_data; 5216 int i; 5217 5218 snd_iprintf(buffer, "# generated by hdspm\n"); 5219 5220 for (i = 0; i < hdspm->max_channels_out; i++) { 5221 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]); 5222 } 5223 } 5224 5225 5226 static void snd_hdspm_proc_init(struct hdspm *hdspm) 5227 { 5228 void (*read)(struct snd_info_entry *, struct snd_info_buffer *) = NULL; 5229 5230 switch (hdspm->io_type) { 5231 case AES32: 5232 read = snd_hdspm_proc_read_aes32; 5233 break; 5234 case MADI: 5235 read = snd_hdspm_proc_read_madi; 5236 break; 5237 case MADIface: 5238 /* read = snd_hdspm_proc_read_madiface; */ 5239 break; 5240 case RayDAT: 5241 read = snd_hdspm_proc_read_raydat; 5242 break; 5243 case AIO: 5244 break; 5245 } 5246 5247 snd_card_ro_proc_new(hdspm->card, "hdspm", hdspm, read); 5248 snd_card_ro_proc_new(hdspm->card, "ports.in", hdspm, 5249 snd_hdspm_proc_ports_in); 5250 snd_card_ro_proc_new(hdspm->card, "ports.out", hdspm, 5251 snd_hdspm_proc_ports_out); 5252 5253 #ifdef CONFIG_SND_DEBUG 5254 /* debug file to read all hdspm registers */ 5255 snd_card_ro_proc_new(hdspm->card, "debug", hdspm, 5256 snd_hdspm_proc_read_debug); 5257 #endif 5258 } 5259 5260 /*------------------------------------------------------------ 5261 hdspm intitialize 5262 ------------------------------------------------------------*/ 5263 5264 static int snd_hdspm_set_defaults(struct hdspm * hdspm) 5265 { 5266 /* ASSUMPTION: hdspm->lock is either held, or there is no need to 5267 hold it (e.g. during module initialization). 5268 */ 5269 5270 /* set defaults: */ 5271 5272 hdspm->settings_register = 0; 5273 5274 switch (hdspm->io_type) { 5275 case MADI: 5276 case MADIface: 5277 hdspm->control_register = 5278 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5279 break; 5280 5281 case RayDAT: 5282 case AIO: 5283 hdspm->settings_register = 0x1 + 0x1000; 5284 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0, 5285 * line_out */ 5286 hdspm->control_register = 5287 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5288 break; 5289 5290 case AES32: 5291 hdspm->control_register = 5292 HDSPM_ClockModeMaster | /* Master Clock Mode on */ 5293 hdspm_encode_latency(7) | /* latency max=8192samples */ 5294 HDSPM_SyncRef0 | /* AES1 is syncclock */ 5295 HDSPM_LineOut | /* Analog output in */ 5296 HDSPM_Professional; /* Professional mode */ 5297 break; 5298 } 5299 5300 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5301 5302 if (AES32 == hdspm->io_type) { 5303 /* No control2 register for AES32 */ 5304 #ifdef SNDRV_BIG_ENDIAN 5305 hdspm->control2_register = HDSPM_BIGENDIAN_MODE; 5306 #else 5307 hdspm->control2_register = 0; 5308 #endif 5309 5310 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register); 5311 } 5312 hdspm_compute_period_size(hdspm); 5313 5314 /* silence everything */ 5315 5316 all_in_all_mixer(hdspm, 0 * UNITY_GAIN); 5317 5318 if (hdspm_is_raydat_or_aio(hdspm)) 5319 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 5320 5321 /* set a default rate so that the channel map is set up. */ 5322 hdspm_set_rate(hdspm, 48000, 1); 5323 5324 return 0; 5325 } 5326 5327 5328 /*------------------------------------------------------------ 5329 interrupt 5330 ------------------------------------------------------------*/ 5331 5332 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id) 5333 { 5334 struct hdspm *hdspm = (struct hdspm *) dev_id; 5335 unsigned int status; 5336 int i, audio, midi, schedule = 0; 5337 /* cycles_t now; */ 5338 5339 status = hdspm_read(hdspm, HDSPM_statusRegister); 5340 5341 audio = status & HDSPM_audioIRQPending; 5342 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending | 5343 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending); 5344 5345 /* now = get_cycles(); */ 5346 /* 5347 * LAT_2..LAT_0 period counter (win) counter (mac) 5348 * 6 4096 ~256053425 ~514672358 5349 * 5 2048 ~128024983 ~257373821 5350 * 4 1024 ~64023706 ~128718089 5351 * 3 512 ~32005945 ~64385999 5352 * 2 256 ~16003039 ~32260176 5353 * 1 128 ~7998738 ~16194507 5354 * 0 64 ~3998231 ~8191558 5355 */ 5356 /* 5357 dev_info(hdspm->card->dev, "snd_hdspm_interrupt %llu @ %llx\n", 5358 now-hdspm->last_interrupt, status & 0xFFC0); 5359 hdspm->last_interrupt = now; 5360 */ 5361 5362 if (!audio && !midi) 5363 return IRQ_NONE; 5364 5365 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0); 5366 hdspm->irq_count++; 5367 5368 5369 if (audio) { 5370 if (hdspm->capture_substream) 5371 snd_pcm_period_elapsed(hdspm->capture_substream); 5372 5373 if (hdspm->playback_substream) 5374 snd_pcm_period_elapsed(hdspm->playback_substream); 5375 } 5376 5377 if (midi) { 5378 i = 0; 5379 while (i < hdspm->midiPorts) { 5380 if ((hdspm_read(hdspm, 5381 hdspm->midi[i].statusIn) & 0xff) && 5382 (status & hdspm->midi[i].irq)) { 5383 /* we disable interrupts for this input until 5384 * processing is done 5385 */ 5386 hdspm->control_register &= ~hdspm->midi[i].ie; 5387 hdspm_write(hdspm, HDSPM_controlRegister, 5388 hdspm->control_register); 5389 hdspm->midi[i].pending = 1; 5390 schedule = 1; 5391 } 5392 5393 i++; 5394 } 5395 5396 if (schedule) 5397 queue_work(system_highpri_wq, &hdspm->midi_work); 5398 } 5399 5400 return IRQ_HANDLED; 5401 } 5402 5403 /*------------------------------------------------------------ 5404 pcm interface 5405 ------------------------------------------------------------*/ 5406 5407 5408 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream 5409 *substream) 5410 { 5411 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5412 return hdspm_hw_pointer(hdspm); 5413 } 5414 5415 5416 static int snd_hdspm_reset(struct snd_pcm_substream *substream) 5417 { 5418 struct snd_pcm_runtime *runtime = substream->runtime; 5419 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5420 struct snd_pcm_substream *other; 5421 5422 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5423 other = hdspm->capture_substream; 5424 else 5425 other = hdspm->playback_substream; 5426 5427 if (hdspm->running) 5428 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm); 5429 else 5430 runtime->status->hw_ptr = 0; 5431 if (other) { 5432 struct snd_pcm_substream *s; 5433 struct snd_pcm_runtime *oruntime = other->runtime; 5434 snd_pcm_group_for_each_entry(s, substream) { 5435 if (s == other) { 5436 oruntime->status->hw_ptr = 5437 runtime->status->hw_ptr; 5438 break; 5439 } 5440 } 5441 } 5442 return 0; 5443 } 5444 5445 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream, 5446 struct snd_pcm_hw_params *params) 5447 { 5448 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5449 int err; 5450 int i; 5451 pid_t this_pid; 5452 pid_t other_pid; 5453 5454 scoped_guard(spinlock_irq, &hdspm->lock) { 5455 5456 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5457 this_pid = hdspm->playback_pid; 5458 other_pid = hdspm->capture_pid; 5459 } else { 5460 this_pid = hdspm->capture_pid; 5461 other_pid = hdspm->playback_pid; 5462 } 5463 5464 if (other_pid > 0 && this_pid != other_pid) { 5465 5466 /* The other stream is open, and not by the same 5467 task as this one. Make sure that the parameters 5468 that matter are the same. 5469 */ 5470 5471 if (params_rate(params) != hdspm->system_sample_rate) { 5472 _snd_pcm_hw_param_setempty(params, 5473 SNDRV_PCM_HW_PARAM_RATE); 5474 return -EBUSY; 5475 } 5476 5477 if (params_period_size(params) != hdspm->period_bytes / 4) { 5478 _snd_pcm_hw_param_setempty(params, 5479 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5480 return -EBUSY; 5481 } 5482 5483 } 5484 } 5485 /* We're fine. */ 5486 5487 /* how to make sure that the rate matches an externally-set one ? */ 5488 5489 scoped_guard(spinlock_irq, &hdspm->lock) { 5490 err = hdspm_set_rate(hdspm, params_rate(params), 0); 5491 if (err < 0) { 5492 dev_info(hdspm->card->dev, "err on hdspm_set_rate: %d\n", err); 5493 _snd_pcm_hw_param_setempty(params, 5494 SNDRV_PCM_HW_PARAM_RATE); 5495 return err; 5496 } 5497 } 5498 5499 err = hdspm_set_interrupt_interval(hdspm, 5500 params_period_size(params)); 5501 if (err < 0) { 5502 dev_info(hdspm->card->dev, 5503 "err on hdspm_set_interrupt_interval: %d\n", err); 5504 _snd_pcm_hw_param_setempty(params, 5505 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5506 return err; 5507 } 5508 5509 /* Memory allocation, takashi's method, dont know if we should 5510 * spinlock 5511 */ 5512 /* malloc all buffer even if not enabled to get sure */ 5513 /* Update for MADI rev 204: we need to allocate for all channels, 5514 * otherwise it doesn't work at 96kHz */ 5515 5516 err = 5517 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES); 5518 if (err < 0) { 5519 dev_info(hdspm->card->dev, 5520 "err on snd_pcm_lib_malloc_pages: %d\n", err); 5521 return err; 5522 } 5523 5524 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5525 5526 for (i = 0; i < params_channels(params); ++i) { 5527 int c = hdspm->channel_map_out[i]; 5528 5529 if (c < 0) 5530 continue; /* just make sure */ 5531 hdspm_set_channel_dma_addr(hdspm, substream, 5532 HDSPM_pageAddressBufferOut, 5533 c); 5534 snd_hdspm_enable_out(hdspm, c, 1); 5535 } 5536 5537 hdspm->playback_buffer = 5538 (unsigned char *) substream->runtime->dma_area; 5539 dev_dbg(hdspm->card->dev, 5540 "Allocated sample buffer for playback at %p\n", 5541 hdspm->playback_buffer); 5542 } else { 5543 for (i = 0; i < params_channels(params); ++i) { 5544 int c = hdspm->channel_map_in[i]; 5545 5546 if (c < 0) 5547 continue; 5548 hdspm_set_channel_dma_addr(hdspm, substream, 5549 HDSPM_pageAddressBufferIn, 5550 c); 5551 snd_hdspm_enable_in(hdspm, c, 1); 5552 } 5553 5554 hdspm->capture_buffer = 5555 (unsigned char *) substream->runtime->dma_area; 5556 dev_dbg(hdspm->card->dev, 5557 "Allocated sample buffer for capture at %p\n", 5558 hdspm->capture_buffer); 5559 } 5560 5561 /* 5562 dev_dbg(hdspm->card->dev, 5563 "Allocated sample buffer for %s at 0x%08X\n", 5564 snd_pcm_direction_name(substream->stream), 5565 snd_pcm_sgbuf_get_addr(substream, 0)); 5566 */ 5567 /* 5568 dev_dbg(hdspm->card->dev, 5569 "set_hwparams: %s %d Hz, %d channels, bs = %d\n", 5570 snd_pcm_direction_name(substream->stream), 5571 params_rate(params), params_channels(params), 5572 params_buffer_size(params)); 5573 */ 5574 5575 5576 /* For AES cards, the float format bit is the same as the 5577 * preferred sync reference. Since we don't want to break 5578 * sync settings, we have to skip the remaining part of this 5579 * function. 5580 */ 5581 if (hdspm->io_type == AES32) { 5582 return 0; 5583 } 5584 5585 5586 /* Switch to native float format if requested */ 5587 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) { 5588 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT)) 5589 dev_info(hdspm->card->dev, 5590 "Switching to native 32bit LE float format.\n"); 5591 5592 hdspm->control_register |= HDSPe_FLOAT_FORMAT; 5593 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) { 5594 if (hdspm->control_register & HDSPe_FLOAT_FORMAT) 5595 dev_info(hdspm->card->dev, 5596 "Switching to native 32bit LE integer format.\n"); 5597 5598 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT; 5599 } 5600 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5601 5602 return 0; 5603 } 5604 5605 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream) 5606 { 5607 int i; 5608 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5609 5610 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5611 /* Just disable all channels. The saving when disabling a */ 5612 /* smaller set is not worth the trouble. */ 5613 for (i = 0; i < HDSPM_MAX_CHANNELS; ++i) 5614 snd_hdspm_enable_out(hdspm, i, 0); 5615 5616 hdspm->playback_buffer = NULL; 5617 } else { 5618 for (i = 0; i < HDSPM_MAX_CHANNELS; ++i) 5619 snd_hdspm_enable_in(hdspm, i, 0); 5620 5621 hdspm->capture_buffer = NULL; 5622 } 5623 5624 snd_pcm_lib_free_pages(substream); 5625 5626 return 0; 5627 } 5628 5629 5630 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream, 5631 struct snd_pcm_channel_info *info) 5632 { 5633 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5634 unsigned int channel = info->channel; 5635 5636 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5637 if (snd_BUG_ON(channel >= hdspm->max_channels_out)) { 5638 dev_info(hdspm->card->dev, 5639 "snd_hdspm_channel_info: output channel out of range (%d)\n", 5640 channel); 5641 return -EINVAL; 5642 } 5643 5644 channel = array_index_nospec(channel, hdspm->max_channels_out); 5645 if (hdspm->channel_map_out[channel] < 0) { 5646 dev_info(hdspm->card->dev, 5647 "snd_hdspm_channel_info: output channel %d mapped out\n", 5648 channel); 5649 return -EINVAL; 5650 } 5651 5652 info->offset = hdspm->channel_map_out[channel] * 5653 HDSPM_CHANNEL_BUFFER_BYTES; 5654 } else { 5655 if (snd_BUG_ON(channel >= hdspm->max_channels_in)) { 5656 dev_info(hdspm->card->dev, 5657 "snd_hdspm_channel_info: input channel out of range (%d)\n", 5658 channel); 5659 return -EINVAL; 5660 } 5661 5662 channel = array_index_nospec(channel, hdspm->max_channels_in); 5663 if (hdspm->channel_map_in[channel] < 0) { 5664 dev_info(hdspm->card->dev, 5665 "snd_hdspm_channel_info: input channel %d mapped out\n", 5666 channel); 5667 return -EINVAL; 5668 } 5669 5670 info->offset = hdspm->channel_map_in[channel] * 5671 HDSPM_CHANNEL_BUFFER_BYTES; 5672 } 5673 5674 info->first = 0; 5675 info->step = 32; 5676 return 0; 5677 } 5678 5679 5680 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream, 5681 unsigned int cmd, void *arg) 5682 { 5683 switch (cmd) { 5684 case SNDRV_PCM_IOCTL1_RESET: 5685 return snd_hdspm_reset(substream); 5686 5687 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 5688 { 5689 struct snd_pcm_channel_info *info = arg; 5690 return snd_hdspm_channel_info(substream, info); 5691 } 5692 default: 5693 break; 5694 } 5695 5696 return snd_pcm_lib_ioctl(substream, cmd, arg); 5697 } 5698 5699 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd) 5700 { 5701 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5702 struct snd_pcm_substream *other; 5703 int running; 5704 5705 guard(spinlock)(&hdspm->lock); 5706 running = hdspm->running; 5707 switch (cmd) { 5708 case SNDRV_PCM_TRIGGER_START: 5709 running |= 1 << substream->stream; 5710 break; 5711 case SNDRV_PCM_TRIGGER_STOP: 5712 running &= ~(1 << substream->stream); 5713 break; 5714 default: 5715 snd_BUG(); 5716 return -EINVAL; 5717 } 5718 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5719 other = hdspm->capture_substream; 5720 else 5721 other = hdspm->playback_substream; 5722 5723 if (other) { 5724 struct snd_pcm_substream *s; 5725 snd_pcm_group_for_each_entry(s, substream) { 5726 if (s == other) { 5727 snd_pcm_trigger_done(s, substream); 5728 if (cmd == SNDRV_PCM_TRIGGER_START) 5729 running |= 1 << s->stream; 5730 else 5731 running &= ~(1 << s->stream); 5732 goto _ok; 5733 } 5734 } 5735 if (cmd == SNDRV_PCM_TRIGGER_START) { 5736 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) 5737 && substream->stream == 5738 SNDRV_PCM_STREAM_CAPTURE) 5739 hdspm_silence_playback(hdspm); 5740 } else { 5741 if (running && 5742 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5743 hdspm_silence_playback(hdspm); 5744 } 5745 } else { 5746 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 5747 hdspm_silence_playback(hdspm); 5748 } 5749 _ok: 5750 snd_pcm_trigger_done(substream, substream); 5751 if (!hdspm->running && running) 5752 hdspm_start_audio(hdspm); 5753 else if (hdspm->running && !running) 5754 hdspm_stop_audio(hdspm); 5755 hdspm->running = running; 5756 5757 return 0; 5758 } 5759 5760 static int snd_hdspm_prepare(struct snd_pcm_substream *substream) 5761 { 5762 return 0; 5763 } 5764 5765 static const struct snd_pcm_hardware snd_hdspm_playback_subinfo = { 5766 .info = (SNDRV_PCM_INFO_MMAP | 5767 SNDRV_PCM_INFO_MMAP_VALID | 5768 SNDRV_PCM_INFO_NONINTERLEAVED | 5769 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE), 5770 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5771 .rates = (SNDRV_PCM_RATE_32000 | 5772 SNDRV_PCM_RATE_44100 | 5773 SNDRV_PCM_RATE_48000 | 5774 SNDRV_PCM_RATE_64000 | 5775 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5776 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ), 5777 .rate_min = 32000, 5778 .rate_max = 192000, 5779 .channels_min = 1, 5780 .channels_max = HDSPM_MAX_CHANNELS, 5781 .buffer_bytes_max = 5782 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5783 .period_bytes_min = (32 * 4), 5784 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5785 .periods_min = 2, 5786 .periods_max = 512, 5787 .fifo_size = 0 5788 }; 5789 5790 static const struct snd_pcm_hardware snd_hdspm_capture_subinfo = { 5791 .info = (SNDRV_PCM_INFO_MMAP | 5792 SNDRV_PCM_INFO_MMAP_VALID | 5793 SNDRV_PCM_INFO_NONINTERLEAVED | 5794 SNDRV_PCM_INFO_SYNC_START), 5795 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5796 .rates = (SNDRV_PCM_RATE_32000 | 5797 SNDRV_PCM_RATE_44100 | 5798 SNDRV_PCM_RATE_48000 | 5799 SNDRV_PCM_RATE_64000 | 5800 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5801 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000), 5802 .rate_min = 32000, 5803 .rate_max = 192000, 5804 .channels_min = 1, 5805 .channels_max = HDSPM_MAX_CHANNELS, 5806 .buffer_bytes_max = 5807 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5808 .period_bytes_min = (32 * 4), 5809 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5810 .periods_min = 2, 5811 .periods_max = 512, 5812 .fifo_size = 0 5813 }; 5814 5815 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 5816 struct snd_pcm_hw_rule *rule) 5817 { 5818 struct hdspm *hdspm = rule->private; 5819 struct snd_interval *c = 5820 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5821 struct snd_interval *r = 5822 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5823 5824 if (r->min > 96000 && r->max <= 192000) { 5825 struct snd_interval t = { 5826 .min = hdspm->qs_in_channels, 5827 .max = hdspm->qs_in_channels, 5828 .integer = 1, 5829 }; 5830 return snd_interval_refine(c, &t); 5831 } else if (r->min > 48000 && r->max <= 96000) { 5832 struct snd_interval t = { 5833 .min = hdspm->ds_in_channels, 5834 .max = hdspm->ds_in_channels, 5835 .integer = 1, 5836 }; 5837 return snd_interval_refine(c, &t); 5838 } else if (r->max < 64000) { 5839 struct snd_interval t = { 5840 .min = hdspm->ss_in_channels, 5841 .max = hdspm->ss_in_channels, 5842 .integer = 1, 5843 }; 5844 return snd_interval_refine(c, &t); 5845 } 5846 5847 return 0; 5848 } 5849 5850 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 5851 struct snd_pcm_hw_rule * rule) 5852 { 5853 struct hdspm *hdspm = rule->private; 5854 struct snd_interval *c = 5855 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5856 struct snd_interval *r = 5857 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5858 5859 if (r->min > 96000 && r->max <= 192000) { 5860 struct snd_interval t = { 5861 .min = hdspm->qs_out_channels, 5862 .max = hdspm->qs_out_channels, 5863 .integer = 1, 5864 }; 5865 return snd_interval_refine(c, &t); 5866 } else if (r->min > 48000 && r->max <= 96000) { 5867 struct snd_interval t = { 5868 .min = hdspm->ds_out_channels, 5869 .max = hdspm->ds_out_channels, 5870 .integer = 1, 5871 }; 5872 return snd_interval_refine(c, &t); 5873 } else if (r->max < 64000) { 5874 struct snd_interval t = { 5875 .min = hdspm->ss_out_channels, 5876 .max = hdspm->ss_out_channels, 5877 .integer = 1, 5878 }; 5879 return snd_interval_refine(c, &t); 5880 } else { 5881 } 5882 return 0; 5883 } 5884 5885 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 5886 struct snd_pcm_hw_rule * rule) 5887 { 5888 struct hdspm *hdspm = rule->private; 5889 struct snd_interval *c = 5890 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5891 struct snd_interval *r = 5892 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5893 5894 if (c->min >= hdspm->ss_in_channels) { 5895 struct snd_interval t = { 5896 .min = 32000, 5897 .max = 48000, 5898 .integer = 1, 5899 }; 5900 return snd_interval_refine(r, &t); 5901 } else if (c->max <= hdspm->qs_in_channels) { 5902 struct snd_interval t = { 5903 .min = 128000, 5904 .max = 192000, 5905 .integer = 1, 5906 }; 5907 return snd_interval_refine(r, &t); 5908 } else if (c->max <= hdspm->ds_in_channels) { 5909 struct snd_interval t = { 5910 .min = 64000, 5911 .max = 96000, 5912 .integer = 1, 5913 }; 5914 return snd_interval_refine(r, &t); 5915 } 5916 5917 return 0; 5918 } 5919 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 5920 struct snd_pcm_hw_rule *rule) 5921 { 5922 struct hdspm *hdspm = rule->private; 5923 struct snd_interval *c = 5924 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5925 struct snd_interval *r = 5926 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5927 5928 if (c->min >= hdspm->ss_out_channels) { 5929 struct snd_interval t = { 5930 .min = 32000, 5931 .max = 48000, 5932 .integer = 1, 5933 }; 5934 return snd_interval_refine(r, &t); 5935 } else if (c->max <= hdspm->qs_out_channels) { 5936 struct snd_interval t = { 5937 .min = 128000, 5938 .max = 192000, 5939 .integer = 1, 5940 }; 5941 return snd_interval_refine(r, &t); 5942 } else if (c->max <= hdspm->ds_out_channels) { 5943 struct snd_interval t = { 5944 .min = 64000, 5945 .max = 96000, 5946 .integer = 1, 5947 }; 5948 return snd_interval_refine(r, &t); 5949 } 5950 5951 return 0; 5952 } 5953 5954 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params, 5955 struct snd_pcm_hw_rule *rule) 5956 { 5957 unsigned int list[3]; 5958 struct hdspm *hdspm = rule->private; 5959 struct snd_interval *c = hw_param_interval(params, 5960 SNDRV_PCM_HW_PARAM_CHANNELS); 5961 5962 list[0] = hdspm->qs_in_channels; 5963 list[1] = hdspm->ds_in_channels; 5964 list[2] = hdspm->ss_in_channels; 5965 return snd_interval_list(c, 3, list, 0); 5966 } 5967 5968 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params, 5969 struct snd_pcm_hw_rule *rule) 5970 { 5971 unsigned int list[3]; 5972 struct hdspm *hdspm = rule->private; 5973 struct snd_interval *c = hw_param_interval(params, 5974 SNDRV_PCM_HW_PARAM_CHANNELS); 5975 5976 list[0] = hdspm->qs_out_channels; 5977 list[1] = hdspm->ds_out_channels; 5978 list[2] = hdspm->ss_out_channels; 5979 return snd_interval_list(c, 3, list, 0); 5980 } 5981 5982 static int snd_hdspm_open(struct snd_pcm_substream *substream) 5983 { 5984 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5985 struct snd_pcm_runtime *runtime = substream->runtime; 5986 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 5987 5988 scoped_guard(spinlock_irq, &hdspm->lock) { 5989 snd_pcm_set_sync(substream); 5990 runtime->hw = (playback) ? snd_hdspm_playback_subinfo : 5991 snd_hdspm_capture_subinfo; 5992 5993 if (playback) { 5994 if (!hdspm->capture_substream) 5995 hdspm_stop_audio(hdspm); 5996 5997 hdspm->playback_pid = current->pid; 5998 hdspm->playback_substream = substream; 5999 } else { 6000 if (!hdspm->playback_substream) 6001 hdspm_stop_audio(hdspm); 6002 6003 hdspm->capture_pid = current->pid; 6004 hdspm->capture_substream = substream; 6005 } 6006 } 6007 6008 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 6009 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 6010 6011 switch (hdspm->io_type) { 6012 case AIO: 6013 case RayDAT: 6014 snd_pcm_hw_constraint_minmax(runtime, 6015 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 6016 32, 4096); 6017 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */ 6018 snd_pcm_hw_constraint_single(runtime, 6019 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 6020 16384); 6021 break; 6022 6023 default: 6024 snd_pcm_hw_constraint_minmax(runtime, 6025 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 6026 64, 8192); 6027 snd_pcm_hw_constraint_single(runtime, 6028 SNDRV_PCM_HW_PARAM_PERIODS, 2); 6029 break; 6030 } 6031 6032 if (AES32 == hdspm->io_type) { 6033 runtime->hw.rates |= SNDRV_PCM_RATE_128000; 6034 } else { 6035 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 6036 (playback ? 6037 snd_hdspm_hw_rule_rate_out_channels : 6038 snd_hdspm_hw_rule_rate_in_channels), hdspm, 6039 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 6040 } 6041 6042 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 6043 (playback ? snd_hdspm_hw_rule_out_channels : 6044 snd_hdspm_hw_rule_in_channels), hdspm, 6045 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 6046 6047 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 6048 (playback ? snd_hdspm_hw_rule_out_channels_rate : 6049 snd_hdspm_hw_rule_in_channels_rate), hdspm, 6050 SNDRV_PCM_HW_PARAM_RATE, -1); 6051 6052 return 0; 6053 } 6054 6055 static int snd_hdspm_release(struct snd_pcm_substream *substream) 6056 { 6057 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 6058 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 6059 6060 guard(spinlock_irq)(&hdspm->lock); 6061 6062 if (playback) { 6063 hdspm->playback_pid = -1; 6064 hdspm->playback_substream = NULL; 6065 } else { 6066 hdspm->capture_pid = -1; 6067 hdspm->capture_substream = NULL; 6068 } 6069 6070 return 0; 6071 } 6072 6073 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) 6074 { 6075 /* we have nothing to initialize but the call is required */ 6076 return 0; 6077 } 6078 6079 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, 6080 unsigned int cmd, unsigned long arg) 6081 { 6082 void __user *argp = (void __user *)arg; 6083 struct hdspm *hdspm = hw->private_data; 6084 struct hdspm_mixer_ioctl mixer; 6085 struct hdspm_config info; 6086 struct hdspm_status status; 6087 struct hdspm_version hdspm_version; 6088 struct hdspm_peak_rms *levels; 6089 struct hdspm_ltc ltc; 6090 unsigned int statusregister; 6091 long unsigned int s; 6092 int i = 0; 6093 6094 switch (cmd) { 6095 6096 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS: 6097 levels = &hdspm->peak_rms; 6098 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 6099 levels->input_peaks[i] = 6100 readl(hdspm->iobase + 6101 HDSPM_MADI_INPUT_PEAK + i*4); 6102 levels->playback_peaks[i] = 6103 readl(hdspm->iobase + 6104 HDSPM_MADI_PLAYBACK_PEAK + i*4); 6105 levels->output_peaks[i] = 6106 readl(hdspm->iobase + 6107 HDSPM_MADI_OUTPUT_PEAK + i*4); 6108 6109 levels->input_rms[i] = 6110 ((uint64_t) readl(hdspm->iobase + 6111 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) | 6112 (uint64_t) readl(hdspm->iobase + 6113 HDSPM_MADI_INPUT_RMS_L + i*4); 6114 levels->playback_rms[i] = 6115 ((uint64_t)readl(hdspm->iobase + 6116 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) | 6117 (uint64_t)readl(hdspm->iobase + 6118 HDSPM_MADI_PLAYBACK_RMS_L + i*4); 6119 levels->output_rms[i] = 6120 ((uint64_t)readl(hdspm->iobase + 6121 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) | 6122 (uint64_t)readl(hdspm->iobase + 6123 HDSPM_MADI_OUTPUT_RMS_L + i*4); 6124 } 6125 6126 if (hdspm->system_sample_rate > 96000) { 6127 levels->speed = qs; 6128 } else if (hdspm->system_sample_rate > 48000) { 6129 levels->speed = ds; 6130 } else { 6131 levels->speed = ss; 6132 } 6133 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 6134 6135 s = copy_to_user(argp, levels, sizeof(*levels)); 6136 if (0 != s) { 6137 /* dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu 6138 [Levels]\n", sizeof(struct hdspm_peak_rms), s); 6139 */ 6140 return -EFAULT; 6141 } 6142 break; 6143 6144 case SNDRV_HDSPM_IOCTL_GET_LTC: 6145 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 6146 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 6147 if (i & HDSPM_TCO1_LTC_Input_valid) { 6148 switch (i & (HDSPM_TCO1_LTC_Format_LSB | 6149 HDSPM_TCO1_LTC_Format_MSB)) { 6150 case 0: 6151 ltc.format = fps_24; 6152 break; 6153 case HDSPM_TCO1_LTC_Format_LSB: 6154 ltc.format = fps_25; 6155 break; 6156 case HDSPM_TCO1_LTC_Format_MSB: 6157 ltc.format = fps_2997; 6158 break; 6159 default: 6160 ltc.format = fps_30; 6161 break; 6162 } 6163 if (i & HDSPM_TCO1_set_drop_frame_flag) { 6164 ltc.frame = drop_frame; 6165 } else { 6166 ltc.frame = full_frame; 6167 } 6168 } else { 6169 ltc.format = format_invalid; 6170 ltc.frame = frame_invalid; 6171 } 6172 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) { 6173 ltc.input_format = ntsc; 6174 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) { 6175 ltc.input_format = pal; 6176 } else { 6177 ltc.input_format = no_video; 6178 } 6179 6180 s = copy_to_user(argp, <c, sizeof(ltc)); 6181 if (0 != s) { 6182 /* 6183 dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */ 6184 return -EFAULT; 6185 } 6186 6187 break; 6188 6189 case SNDRV_HDSPM_IOCTL_GET_CONFIG: 6190 6191 memset(&info, 0, sizeof(info)); 6192 scoped_guard(spinlock_irq, &hdspm->lock) { 6193 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm); 6194 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm); 6195 6196 info.system_sample_rate = hdspm->system_sample_rate; 6197 info.autosync_sample_rate = 6198 hdspm_external_sample_rate(hdspm); 6199 info.system_clock_mode = hdspm_system_clock_mode(hdspm); 6200 info.clock_source = hdspm_clock_source(hdspm); 6201 info.autosync_ref = hdspm_autosync_ref(hdspm); 6202 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut); 6203 info.passthru = 0; 6204 } 6205 if (copy_to_user(argp, &info, sizeof(info))) 6206 return -EFAULT; 6207 break; 6208 6209 case SNDRV_HDSPM_IOCTL_GET_STATUS: 6210 memset(&status, 0, sizeof(status)); 6211 6212 status.card_type = hdspm->io_type; 6213 6214 status.autosync_source = hdspm_autosync_ref(hdspm); 6215 6216 status.card_clock = 110069313433624ULL; 6217 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 6218 6219 switch (hdspm->io_type) { 6220 case MADI: 6221 case MADIface: 6222 status.card_specific.madi.sync_wc = 6223 hdspm_wc_sync_check(hdspm); 6224 status.card_specific.madi.sync_madi = 6225 hdspm_madi_sync_check(hdspm); 6226 status.card_specific.madi.sync_tco = 6227 hdspm_tco_sync_check(hdspm); 6228 status.card_specific.madi.sync_in = 6229 hdspm_sync_in_sync_check(hdspm); 6230 6231 statusregister = 6232 hdspm_read(hdspm, HDSPM_statusRegister); 6233 status.card_specific.madi.madi_input = 6234 (statusregister & HDSPM_AB_int) ? 1 : 0; 6235 status.card_specific.madi.channel_format = 6236 (statusregister & HDSPM_RX_64ch) ? 1 : 0; 6237 /* TODO: Mac driver sets it when f_s>48kHz */ 6238 status.card_specific.madi.frame_format = 0; 6239 break; 6240 6241 default: 6242 break; 6243 } 6244 6245 if (copy_to_user(argp, &status, sizeof(status))) 6246 return -EFAULT; 6247 6248 6249 break; 6250 6251 case SNDRV_HDSPM_IOCTL_GET_VERSION: 6252 memset(&hdspm_version, 0, sizeof(hdspm_version)); 6253 6254 hdspm_version.card_type = hdspm->io_type; 6255 strscpy(hdspm_version.cardname, hdspm->card_name, 6256 sizeof(hdspm_version.cardname)); 6257 hdspm_version.serial = hdspm->serial; 6258 hdspm_version.firmware_rev = hdspm->firmware_rev; 6259 hdspm_version.addons = 0; 6260 if (hdspm->tco) 6261 hdspm_version.addons |= HDSPM_ADDON_TCO; 6262 6263 if (copy_to_user(argp, &hdspm_version, 6264 sizeof(hdspm_version))) 6265 return -EFAULT; 6266 break; 6267 6268 case SNDRV_HDSPM_IOCTL_GET_MIXER: 6269 if (copy_from_user(&mixer, argp, sizeof(mixer))) 6270 return -EFAULT; 6271 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer, 6272 sizeof(*mixer.mixer))) 6273 return -EFAULT; 6274 break; 6275 6276 default: 6277 return -EINVAL; 6278 } 6279 return 0; 6280 } 6281 6282 static const struct snd_pcm_ops snd_hdspm_ops = { 6283 .open = snd_hdspm_open, 6284 .close = snd_hdspm_release, 6285 .ioctl = snd_hdspm_ioctl, 6286 .hw_params = snd_hdspm_hw_params, 6287 .hw_free = snd_hdspm_hw_free, 6288 .prepare = snd_hdspm_prepare, 6289 .trigger = snd_hdspm_trigger, 6290 .pointer = snd_hdspm_hw_pointer, 6291 }; 6292 6293 static int snd_hdspm_create_hwdep(struct snd_card *card, 6294 struct hdspm *hdspm) 6295 { 6296 struct snd_hwdep *hw; 6297 int err; 6298 6299 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw); 6300 if (err < 0) 6301 return err; 6302 6303 hdspm->hwdep = hw; 6304 hw->private_data = hdspm; 6305 strscpy(hw->name, "HDSPM hwdep interface"); 6306 6307 hw->ops.open = snd_hdspm_hwdep_dummy_op; 6308 hw->ops.ioctl = snd_hdspm_hwdep_ioctl; 6309 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl; 6310 hw->ops.release = snd_hdspm_hwdep_dummy_op; 6311 6312 return 0; 6313 } 6314 6315 6316 /*------------------------------------------------------------ 6317 memory interface 6318 ------------------------------------------------------------*/ 6319 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm) 6320 { 6321 struct snd_pcm *pcm; 6322 size_t wanted; 6323 6324 pcm = hdspm->pcm; 6325 6326 wanted = HDSPM_DMA_AREA_BYTES; 6327 6328 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, 6329 &hdspm->pci->dev, 6330 wanted, wanted); 6331 dev_dbg(hdspm->card->dev, " Preallocated %zd Bytes\n", wanted); 6332 return 0; 6333 } 6334 6335 /* Inform the card what DMA addresses to use for the indicated channel. */ 6336 /* Each channel got 16 4K pages allocated for DMA transfers. */ 6337 static void hdspm_set_channel_dma_addr(struct hdspm *hdspm, 6338 struct snd_pcm_substream *substream, 6339 unsigned int reg, int channel) 6340 { 6341 int i; 6342 6343 for (i = channel * 16; i < channel * 16 + 16; i++) 6344 hdspm_write(hdspm, reg + 4 * i, 6345 snd_pcm_sgbuf_get_addr(substream, 4096 * i)); 6346 } 6347 6348 6349 /* ------------- ALSA Devices ---------------------------- */ 6350 static int snd_hdspm_create_pcm(struct snd_card *card, 6351 struct hdspm *hdspm) 6352 { 6353 struct snd_pcm *pcm; 6354 int err; 6355 6356 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm); 6357 if (err < 0) 6358 return err; 6359 6360 hdspm->pcm = pcm; 6361 pcm->private_data = hdspm; 6362 strscpy(pcm->name, hdspm->card_name); 6363 6364 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 6365 &snd_hdspm_ops); 6366 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 6367 &snd_hdspm_ops); 6368 6369 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 6370 6371 err = snd_hdspm_preallocate_memory(hdspm); 6372 if (err < 0) 6373 return err; 6374 6375 return 0; 6376 } 6377 6378 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm) 6379 { 6380 int i; 6381 6382 for (i = 0; i < hdspm->midiPorts; i++) 6383 snd_hdspm_flush_midi_input(hdspm, i); 6384 } 6385 6386 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 6387 struct hdspm *hdspm) 6388 { 6389 int err, i; 6390 6391 dev_dbg(card->dev, "Create card...\n"); 6392 err = snd_hdspm_create_pcm(card, hdspm); 6393 if (err < 0) 6394 return err; 6395 6396 i = 0; 6397 while (i < hdspm->midiPorts) { 6398 err = snd_hdspm_create_midi(card, hdspm, i); 6399 if (err < 0) { 6400 return err; 6401 } 6402 i++; 6403 } 6404 6405 err = snd_hdspm_create_controls(card, hdspm); 6406 if (err < 0) 6407 return err; 6408 6409 err = snd_hdspm_create_hwdep(card, hdspm); 6410 if (err < 0) 6411 return err; 6412 6413 dev_dbg(card->dev, "proc init...\n"); 6414 snd_hdspm_proc_init(hdspm); 6415 6416 hdspm->system_sample_rate = -1; 6417 hdspm->last_external_sample_rate = -1; 6418 hdspm->last_internal_sample_rate = -1; 6419 hdspm->playback_pid = -1; 6420 hdspm->capture_pid = -1; 6421 hdspm->capture_substream = NULL; 6422 hdspm->playback_substream = NULL; 6423 6424 dev_dbg(card->dev, "Set defaults...\n"); 6425 err = snd_hdspm_set_defaults(hdspm); 6426 if (err < 0) 6427 return err; 6428 6429 dev_dbg(card->dev, "Update mixer controls...\n"); 6430 hdspm_update_simple_mixer_controls(hdspm); 6431 6432 dev_dbg(card->dev, "Initializing complete?\n"); 6433 6434 err = snd_card_register(card); 6435 if (err < 0) { 6436 dev_err(card->dev, "error registering card\n"); 6437 return err; 6438 } 6439 6440 dev_dbg(card->dev, "... yes now\n"); 6441 6442 return 0; 6443 } 6444 6445 static int snd_hdspm_create(struct snd_card *card, 6446 struct hdspm *hdspm) 6447 { 6448 6449 struct pci_dev *pci = hdspm->pci; 6450 int err; 6451 unsigned long io_extent; 6452 6453 hdspm->irq = -1; 6454 hdspm->card = card; 6455 6456 spin_lock_init(&hdspm->lock); 6457 INIT_WORK(&hdspm->midi_work, hdspm_midi_work); 6458 6459 pci_read_config_word(hdspm->pci, 6460 PCI_CLASS_REVISION, &hdspm->firmware_rev); 6461 6462 strscpy(card->mixername, "Xilinx FPGA"); 6463 strscpy(card->driver, "HDSPM"); 6464 6465 switch (hdspm->firmware_rev) { 6466 case HDSPM_RAYDAT_REV: 6467 hdspm->io_type = RayDAT; 6468 hdspm->card_name = "RME RayDAT"; 6469 hdspm->midiPorts = 2; 6470 break; 6471 case HDSPM_AIO_REV: 6472 hdspm->io_type = AIO; 6473 hdspm->card_name = "RME AIO"; 6474 hdspm->midiPorts = 1; 6475 break; 6476 case HDSPM_MADIFACE_REV: 6477 hdspm->io_type = MADIface; 6478 hdspm->card_name = "RME MADIface"; 6479 hdspm->midiPorts = 1; 6480 break; 6481 default: 6482 if ((hdspm->firmware_rev == 0xf0) || 6483 ((hdspm->firmware_rev >= 0xe6) && 6484 (hdspm->firmware_rev <= 0xea))) { 6485 hdspm->io_type = AES32; 6486 hdspm->card_name = "RME AES32"; 6487 hdspm->midiPorts = 2; 6488 } else if ((hdspm->firmware_rev == 0xd2) || 6489 ((hdspm->firmware_rev >= 0xc8) && 6490 (hdspm->firmware_rev <= 0xcf))) { 6491 hdspm->io_type = MADI; 6492 hdspm->card_name = "RME MADI"; 6493 hdspm->midiPorts = 3; 6494 } else { 6495 dev_err(card->dev, 6496 "unknown firmware revision %x\n", 6497 hdspm->firmware_rev); 6498 return -ENODEV; 6499 } 6500 } 6501 6502 err = pcim_enable_device(pci); 6503 if (err < 0) 6504 return err; 6505 6506 pci_set_master(hdspm->pci); 6507 6508 hdspm->iobase = pcim_iomap_region(pci, 0, "hdspm"); 6509 if (IS_ERR(hdspm->iobase)) 6510 return PTR_ERR(hdspm->iobase); 6511 6512 hdspm->port = pci_resource_start(pci, 0); 6513 io_extent = pci_resource_len(pci, 0); 6514 dev_dbg(card->dev, "remapped region (0x%lx) 0x%lx-0x%lx\n", 6515 (unsigned long)hdspm->iobase, hdspm->port, 6516 hdspm->port + io_extent - 1); 6517 6518 if (devm_request_irq(&pci->dev, pci->irq, snd_hdspm_interrupt, 6519 IRQF_SHARED, KBUILD_MODNAME, hdspm)) { 6520 dev_err(card->dev, "unable to use IRQ %d\n", pci->irq); 6521 return -EBUSY; 6522 } 6523 6524 dev_dbg(card->dev, "use IRQ %d\n", pci->irq); 6525 6526 hdspm->irq = pci->irq; 6527 card->sync_irq = hdspm->irq; 6528 6529 dev_dbg(card->dev, "kmalloc Mixer memory of %zd Bytes\n", 6530 sizeof(*hdspm->mixer)); 6531 hdspm->mixer = devm_kzalloc(&pci->dev, sizeof(*hdspm->mixer), GFP_KERNEL); 6532 if (!hdspm->mixer) 6533 return -ENOMEM; 6534 6535 hdspm->port_names_in = NULL; 6536 hdspm->port_names_out = NULL; 6537 6538 switch (hdspm->io_type) { 6539 case AES32: 6540 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS; 6541 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS; 6542 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS; 6543 6544 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6545 channel_map_aes32; 6546 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6547 channel_map_aes32; 6548 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6549 channel_map_aes32; 6550 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6551 texts_ports_aes32; 6552 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6553 texts_ports_aes32; 6554 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6555 texts_ports_aes32; 6556 6557 hdspm->max_channels_out = hdspm->max_channels_in = 6558 AES32_CHANNELS; 6559 hdspm->port_names_in = hdspm->port_names_out = 6560 texts_ports_aes32; 6561 hdspm->channel_map_in = hdspm->channel_map_out = 6562 channel_map_aes32; 6563 6564 break; 6565 6566 case MADI: 6567 case MADIface: 6568 hdspm->ss_in_channels = hdspm->ss_out_channels = 6569 MADI_SS_CHANNELS; 6570 hdspm->ds_in_channels = hdspm->ds_out_channels = 6571 MADI_DS_CHANNELS; 6572 hdspm->qs_in_channels = hdspm->qs_out_channels = 6573 MADI_QS_CHANNELS; 6574 6575 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6576 channel_map_unity_ss; 6577 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6578 channel_map_unity_ss; 6579 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6580 channel_map_unity_ss; 6581 6582 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6583 texts_ports_madi; 6584 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6585 texts_ports_madi; 6586 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6587 texts_ports_madi; 6588 break; 6589 6590 case AIO: 6591 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS; 6592 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS; 6593 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS; 6594 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS; 6595 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS; 6596 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS; 6597 6598 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) { 6599 dev_info(card->dev, "AEB input board found\n"); 6600 hdspm->ss_in_channels += 4; 6601 hdspm->ds_in_channels += 4; 6602 hdspm->qs_in_channels += 4; 6603 } 6604 6605 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBO_D)) { 6606 dev_info(card->dev, "AEB output board found\n"); 6607 hdspm->ss_out_channels += 4; 6608 hdspm->ds_out_channels += 4; 6609 hdspm->qs_out_channels += 4; 6610 } 6611 6612 hdspm->channel_map_out_ss = channel_map_aio_out_ss; 6613 hdspm->channel_map_out_ds = channel_map_aio_out_ds; 6614 hdspm->channel_map_out_qs = channel_map_aio_out_qs; 6615 6616 hdspm->channel_map_in_ss = channel_map_aio_in_ss; 6617 hdspm->channel_map_in_ds = channel_map_aio_in_ds; 6618 hdspm->channel_map_in_qs = channel_map_aio_in_qs; 6619 6620 hdspm->port_names_in_ss = texts_ports_aio_in_ss; 6621 hdspm->port_names_out_ss = texts_ports_aio_out_ss; 6622 hdspm->port_names_in_ds = texts_ports_aio_in_ds; 6623 hdspm->port_names_out_ds = texts_ports_aio_out_ds; 6624 hdspm->port_names_in_qs = texts_ports_aio_in_qs; 6625 hdspm->port_names_out_qs = texts_ports_aio_out_qs; 6626 6627 break; 6628 6629 case RayDAT: 6630 hdspm->ss_in_channels = hdspm->ss_out_channels = 6631 RAYDAT_SS_CHANNELS; 6632 hdspm->ds_in_channels = hdspm->ds_out_channels = 6633 RAYDAT_DS_CHANNELS; 6634 hdspm->qs_in_channels = hdspm->qs_out_channels = 6635 RAYDAT_QS_CHANNELS; 6636 6637 hdspm->max_channels_in = RAYDAT_SS_CHANNELS; 6638 hdspm->max_channels_out = RAYDAT_SS_CHANNELS; 6639 6640 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6641 channel_map_raydat_ss; 6642 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6643 channel_map_raydat_ds; 6644 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6645 channel_map_raydat_qs; 6646 hdspm->channel_map_in = hdspm->channel_map_out = 6647 channel_map_raydat_ss; 6648 6649 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6650 texts_ports_raydat_ss; 6651 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6652 texts_ports_raydat_ds; 6653 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6654 texts_ports_raydat_qs; 6655 6656 6657 break; 6658 6659 } 6660 6661 /* TCO detection */ 6662 switch (hdspm->io_type) { 6663 case AIO: 6664 case RayDAT: 6665 if (hdspm_read(hdspm, HDSPM_statusRegister2) & 6666 HDSPM_s2_tco_detect) { 6667 hdspm->midiPorts++; 6668 hdspm->tco = kzalloc_obj(*hdspm->tco); 6669 if (hdspm->tco) 6670 hdspm_tco_write(hdspm); 6671 6672 dev_info(card->dev, "AIO/RayDAT TCO module found\n"); 6673 } else { 6674 hdspm->tco = NULL; 6675 } 6676 break; 6677 6678 case MADI: 6679 case AES32: 6680 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) { 6681 hdspm->midiPorts++; 6682 hdspm->tco = kzalloc_obj(*hdspm->tco); 6683 if (hdspm->tco) 6684 hdspm_tco_write(hdspm); 6685 6686 dev_info(card->dev, "MADI/AES TCO module found\n"); 6687 } else { 6688 hdspm->tco = NULL; 6689 } 6690 break; 6691 6692 default: 6693 hdspm->tco = NULL; 6694 } 6695 6696 /* texts */ 6697 switch (hdspm->io_type) { 6698 case AES32: 6699 if (hdspm->tco) { 6700 hdspm->texts_autosync = texts_autosync_aes_tco; 6701 hdspm->texts_autosync_items = 6702 ARRAY_SIZE(texts_autosync_aes_tco); 6703 } else { 6704 hdspm->texts_autosync = texts_autosync_aes; 6705 hdspm->texts_autosync_items = 6706 ARRAY_SIZE(texts_autosync_aes); 6707 } 6708 break; 6709 6710 case MADI: 6711 if (hdspm->tco) { 6712 hdspm->texts_autosync = texts_autosync_madi_tco; 6713 hdspm->texts_autosync_items = 4; 6714 } else { 6715 hdspm->texts_autosync = texts_autosync_madi; 6716 hdspm->texts_autosync_items = 3; 6717 } 6718 break; 6719 6720 case MADIface: 6721 6722 break; 6723 6724 case RayDAT: 6725 if (hdspm->tco) { 6726 hdspm->texts_autosync = texts_autosync_raydat_tco; 6727 hdspm->texts_autosync_items = 9; 6728 } else { 6729 hdspm->texts_autosync = texts_autosync_raydat; 6730 hdspm->texts_autosync_items = 8; 6731 } 6732 break; 6733 6734 case AIO: 6735 if (hdspm->tco) { 6736 hdspm->texts_autosync = texts_autosync_aio_tco; 6737 hdspm->texts_autosync_items = 6; 6738 } else { 6739 hdspm->texts_autosync = texts_autosync_aio; 6740 hdspm->texts_autosync_items = 5; 6741 } 6742 break; 6743 6744 } 6745 6746 if (hdspm->io_type != MADIface) { 6747 hdspm->serial = (hdspm_read(hdspm, 6748 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF; 6749 /* id contains either a user-provided value or the default 6750 * NULL. If it's the default, we're safe to 6751 * fill card->id with the serial number. 6752 * 6753 * If the serial number is 0xFFFFFF, then we're dealing with 6754 * an old PCI revision that comes without a sane number. In 6755 * this case, we don't set card->id to avoid collisions 6756 * when running with multiple cards. 6757 */ 6758 if (!id[hdspm->dev] && hdspm->serial != 0xFFFFFF) { 6759 snprintf(card->id, sizeof(card->id), 6760 "HDSPMx%06x", hdspm->serial); 6761 snd_card_set_id(card, card->id); 6762 } 6763 } 6764 6765 dev_dbg(card->dev, "create alsa devices.\n"); 6766 err = snd_hdspm_create_alsa_devices(card, hdspm); 6767 if (err < 0) 6768 return err; 6769 6770 snd_hdspm_initialize_midi_flush(hdspm); 6771 6772 return 0; 6773 } 6774 6775 6776 static void snd_hdspm_card_free(struct snd_card *card) 6777 { 6778 struct hdspm *hdspm = card->private_data; 6779 6780 if (hdspm->port) { 6781 cancel_work_sync(&hdspm->midi_work); 6782 6783 /* stop th audio, and cancel all interrupts */ 6784 hdspm->control_register &= 6785 ~(HDSPM_Start | HDSPM_AudioInterruptEnable | 6786 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable | 6787 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable); 6788 hdspm_write(hdspm, HDSPM_controlRegister, 6789 hdspm->control_register); 6790 } 6791 } 6792 6793 6794 static int snd_hdspm_probe(struct pci_dev *pci, 6795 const struct pci_device_id *pci_id) 6796 { 6797 static int dev; 6798 struct hdspm *hdspm; 6799 struct snd_card *card; 6800 int err; 6801 6802 if (dev >= SNDRV_CARDS) 6803 return -ENODEV; 6804 if (!enable[dev]) { 6805 dev++; 6806 return -ENOENT; 6807 } 6808 6809 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], 6810 THIS_MODULE, sizeof(*hdspm), &card); 6811 if (err < 0) 6812 return err; 6813 6814 hdspm = card->private_data; 6815 card->private_free = snd_hdspm_card_free; 6816 hdspm->dev = dev; 6817 hdspm->pci = pci; 6818 6819 err = snd_hdspm_create(card, hdspm); 6820 if (err < 0) 6821 goto error; 6822 6823 if (hdspm->io_type != MADIface) { 6824 snprintf(card->shortname, sizeof(card->shortname), "%s_%x", 6825 hdspm->card_name, hdspm->serial); 6826 snprintf(card->longname, sizeof(card->longname), 6827 "%s S/N 0x%x at 0x%lx, irq %d", 6828 hdspm->card_name, hdspm->serial, 6829 hdspm->port, hdspm->irq); 6830 } else { 6831 snprintf(card->shortname, sizeof(card->shortname), "%s", 6832 hdspm->card_name); 6833 snprintf(card->longname, sizeof(card->longname), 6834 "%s at 0x%lx, irq %d", 6835 hdspm->card_name, hdspm->port, hdspm->irq); 6836 } 6837 6838 err = snd_card_register(card); 6839 if (err < 0) 6840 goto error; 6841 6842 pci_set_drvdata(pci, card); 6843 6844 dev++; 6845 return 0; 6846 6847 error: 6848 snd_card_free(card); 6849 return err; 6850 } 6851 6852 static struct pci_driver hdspm_driver = { 6853 .name = KBUILD_MODNAME, 6854 .id_table = snd_hdspm_ids, 6855 .probe = snd_hdspm_probe, 6856 }; 6857 6858 module_pci_driver(hdspm_driver); 6859