1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
7 *
8 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9 */
10
11 #ifndef __SOF_AMD_ACP_H
12 #define __SOF_AMD_ACP_H
13
14 #include <linux/dmi.h>
15 #include <linux/soundwire/sdw_amd.h>
16 #include "../sof-priv.h"
17 #include "../sof-audio.h"
18
19 #define ACP_MAX_STREAM 8
20
21 #define ACP_DSP_BAR 0
22
23 #define ACP_HW_SEM_RETRY_COUNT 10000
24 #define ACP_REG_POLL_INTERVAL 500
25 #define ACP_REG_POLL_TIMEOUT_US 2000
26 #define ACP_DMA_COMPLETE_TIMEOUT_US 5000
27
28 #define ACP3X_PGFSM_CNTL_POWER_ON_MASK 0x01
29 #define ACP3X_PGFSM_STATUS_MASK 0x03
30 #define ACP6X_PGFSM_CNTL_POWER_ON_MASK 0x07
31 #define ACP6X_PGFSM_STATUS_MASK 0x0F
32 #define ACP70_PGFSM_CNTL_POWER_ON_MASK 0x1F
33 #define ACP70_PGFSM_STATUS_MASK 0xFF
34
35 #define ACP_POWERED_ON 0x00
36 #define ACP_ASSERT_RESET 0x01
37 #define ACP_RELEASE_RESET 0x00
38 #define ACP_SOFT_RESET_DONE_MASK 0x00010001
39 #define ACP_DSP_ASSERT_RESET 0x04
40 #define ACP_DSP_RELEASE_RESET 0x00
41 #define ACP_DSP_SOFT_RESET_DONE_MASK 0x00050004
42
43 #define ACP_DSP_INTR_EN_MASK 0x00000001
44 #define ACP3X_SRAM_PTE_OFFSET 0x02050000
45 #define ACP5X_SRAM_PTE_OFFSET 0x02050000
46 #define ACP6X_SRAM_PTE_OFFSET 0x03800000
47 #define ACP70_SRAM_PTE_OFFSET ACP6X_SRAM_PTE_OFFSET
48 #define PAGE_SIZE_4K_ENABLE 0x2
49 #define ACP_PAGE_SIZE 0x1000
50 #define ACP_DMA_CH_RUN 0x02
51 #define ACP_MAX_DESC_CNT 0x02
52 #define DSP_FW_RUN_ENABLE 0x01
53 #define ACP_SHA_RUN 0x01
54 #define ACP_SHA_RESET 0x02
55 #define ACP_SHA_HEADER 0x01
56 #define ACP_DMA_CH_RST 0x01
57 #define ACP_DMA_CH_GRACEFUL_RST_EN 0x10
58 #define ACP_ATU_CACHE_INVALID 0x01
59 #define ACP_MAX_DESC 128
60 #define ACPBUS_REG_BASE_OFFSET ACP_DMA_CNTL_0
61
62 #define ACP_DEFAULT_DRAM_LENGTH 0x00080000
63 #define ACP3X_SCRATCH_MEMORY_ADDRESS 0x02050000
64 #define ACP_SYSTEM_MEMORY_WINDOW 0x4000000
65 #define ACP_IRAM_BASE_ADDRESS 0x000000
66 #define ACP_DRAM_BASE_ADDRESS 0x01000000
67 #define ACP_DRAM_PAGE_COUNT 128
68 #define ACP_SRAM_BASE_ADDRESS 0x3806000
69 #define ACP7X_SRAM_BASE_ADDRESS 0x380C000
70 #define ACP_DSP_TO_HOST_IRQ 0x04
71
72 #define ACP_RN_PCI_ID 0x01
73 #define ACP_VANGOGH_PCI_ID 0x50
74 #define ACP_RMB_PCI_ID 0x6F
75 #define ACP63_PCI_ID 0x63
76 #define ACP70_PCI_ID 0x70
77
78 #define HOST_BRIDGE_CZN 0x1630
79 #define HOST_BRIDGE_VGH 0x1645
80 #define HOST_BRIDGE_RMB 0x14B5
81 #define HOST_BRIDGE_ACP63 0x14E8
82 #define HOST_BRIDGE_ACP70 0x1507
83 #define ACP_SHA_STAT 0x8000
84 #define ACP_PSP_TIMEOUT_US 1000000
85 #define ACP_EXT_INTR_ERROR_STAT 0x20000000
86 #define MP0_C2PMSG_114_REG 0x3810AC8
87 #define MP0_C2PMSG_73_REG 0x3810A24
88 #define MBOX_ACP_SHA_DMA_COMMAND 0x70000
89 #define MBOX_ACP_IRAM_DRAM_FENCE_COMMAND 0x80000
90 #define MBOX_DELAY_US 1000
91 #define MBOX_READY_MASK 0x80000000
92 #define MBOX_STATUS_MASK 0xFFFF
93 #define MBOX_ISREADY_FLAG 0x40000000
94 #define IRAM_DRAM_FENCE_0 0X0
95 #define IRAM_DRAM_FENCE_1 0X01
96 #define IRAM_DRAM_FENCE_2 0X02
97
98 #define BOX_SIZE_512 0x200
99 #define BOX_SIZE_1024 0x400
100
101 #define EXCEPT_MAX_HDR_SIZE 0x400
102 #define AMD_STACK_DUMP_SIZE 32
103
104 #define SRAM1_SIZE 0x280000
105 #define PROBE_STATUS_BIT BIT(31)
106
107 #define ACP_FIRMWARE_SIGNATURE 0x100
108 #define ACP_ERROR_IRQ_MASK BIT(29)
109 #define ACP_SDW0_IRQ_MASK BIT(21)
110 #define ACP_SDW1_IRQ_MASK BIT(2)
111 #define SDW_ACPI_ADDR_ACP63 5
112 #define ACP_DEFAULT_SRAM_LENGTH 0x00080000
113 #define ACP_SRAM_PAGE_COUNT 128
114 #define ACP6X_SDW_MAX_MANAGER_COUNT 2
115
116 enum clock_source {
117 ACP_CLOCK_96M = 0,
118 ACP_CLOCK_48M,
119 ACP_CLOCK_24M,
120 ACP_CLOCK_ACLK,
121 ACP_CLOCK_MCLK,
122 };
123
124 struct acp_atu_grp_pte {
125 u32 low;
126 u32 high;
127 };
128
129 union dma_tx_cnt {
130 struct {
131 unsigned int count : 19;
132 unsigned int reserved : 12;
133 unsigned ioc : 1;
134 } bitfields, bits;
135 unsigned int u32_all;
136 signed int i32_all;
137 };
138
139 struct dma_descriptor {
140 unsigned int src_addr;
141 unsigned int dest_addr;
142 union dma_tx_cnt tx_cnt;
143 unsigned int reserved;
144 };
145
146 /* Scratch memory structure for communication b/w host and dsp */
147 struct scratch_ipc_conf {
148 /* Debug memory */
149 u8 sof_debug_box[1024];
150 /* Exception memory*/
151 u8 sof_except_box[1024];
152 /* Stream buffer */
153 u8 sof_stream_box[1024];
154 /* Trace buffer */
155 u8 sof_trace_box[1024];
156 /* Host msg flag */
157 u32 sof_host_msg_write;
158 /* Host ack flag*/
159 u32 sof_host_ack_write;
160 /* DSP msg flag */
161 u32 sof_dsp_msg_write;
162 /* Dsp ack flag */
163 u32 sof_dsp_ack_write;
164 };
165
166 struct scratch_reg_conf {
167 struct scratch_ipc_conf info;
168 struct acp_atu_grp_pte grp1_pte[16];
169 struct acp_atu_grp_pte grp2_pte[16];
170 struct acp_atu_grp_pte grp3_pte[16];
171 struct acp_atu_grp_pte grp4_pte[16];
172 struct acp_atu_grp_pte grp5_pte[16];
173 struct acp_atu_grp_pte grp6_pte[16];
174 struct acp_atu_grp_pte grp7_pte[16];
175 struct acp_atu_grp_pte grp8_pte[16];
176 struct dma_descriptor dma_desc[64];
177 unsigned int reg_offset[8];
178 unsigned int buf_size[8];
179 u8 acp_tx_fifo_buf[256];
180 u8 acp_rx_fifo_buf[256];
181 unsigned int reserve[];
182 };
183
184 struct acp_dsp_stream {
185 struct list_head list;
186 struct snd_sof_dev *sdev;
187 struct snd_pcm_substream *substream;
188 struct snd_dma_buffer *dmab;
189 int num_pages;
190 int stream_tag;
191 int active;
192 unsigned int reg_offset;
193 size_t posn_offset;
194 struct snd_compr_stream *cstream;
195 u64 cstream_posn;
196 };
197
198 struct sof_amd_acp_desc {
199 const char *name;
200 unsigned int host_bridge_id;
201 u32 pgfsm_base;
202 u32 ext_intr_enb;
203 u32 ext_intr_cntl;
204 u32 ext_intr_stat;
205 u32 ext_intr_stat1;
206 u32 dsp_intr_base;
207 u32 sram_pte_offset;
208 u32 hw_semaphore_offset;
209 u32 acp_clkmux_sel;
210 u32 fusion_dsp_offset;
211 u32 probe_reg_offset;
212 u32 reg_start_addr;
213 u32 reg_end_addr;
214 u32 acp_error_stat;
215 u32 acp_sw0_i2s_err_reason;
216 u32 sdw_max_link_count;
217 u64 sdw_acpi_dev_addr;
218 };
219
220 struct acp_quirk_entry {
221 bool signed_fw_image;
222 bool skip_iram_dram_size_mod;
223 };
224
225 /* Common device data struct for ACP devices */
226 struct acp_dev_data {
227 struct snd_sof_dev *dev;
228 const struct firmware *fw_dbin;
229 /* DMIC device */
230 struct platform_device *dmic_dev;
231 /* mutex lock to protect ACP common registers access */
232 struct mutex acp_lock;
233 /* ACPI information stored between scan and probe steps */
234 struct sdw_amd_acpi_info info;
235 /* sdw context allocated by SoundWire driver */
236 struct sdw_amd_ctx *sdw;
237 unsigned int fw_bin_size;
238 unsigned int fw_data_bin_size;
239 unsigned int fw_sram_data_bin_size;
240 const char *fw_code_bin;
241 const char *fw_data_bin;
242 const char *fw_sram_data_bin;
243 u32 fw_bin_page_count;
244 u32 fw_data_bin_page_count;
245 u32 addr;
246 u32 reg_range;
247 u32 blk_type;
248 dma_addr_t sha_dma_addr;
249 u8 *bin_buf;
250 dma_addr_t dma_addr;
251 u8 *data_buf;
252 dma_addr_t sram_dma_addr;
253 u8 *sram_data_buf;
254 struct acp_quirk_entry *quirks;
255 struct dma_descriptor dscr_info[ACP_MAX_DESC];
256 struct acp_dsp_stream stream_buf[ACP_MAX_STREAM];
257 struct acp_dsp_stream *dtrace_stream;
258 struct pci_dev *smn_dev;
259 struct acp_dsp_stream *probe_stream;
260 bool enable_fw_debug;
261 bool is_dram_in_use;
262 bool is_sram_in_use;
263 bool sdw_en_stat;
264 unsigned int pci_rev;
265 };
266
267 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes);
268 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes);
269
270 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch);
271 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr,
272 unsigned int dest_addr, int dsp_data_size);
273 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr,
274 unsigned int start_addr, unsigned int dest_addr,
275 unsigned int image_length);
276
277 /* ACP device probe/remove */
278 int amd_sof_acp_probe(struct snd_sof_dev *sdev);
279 void amd_sof_acp_remove(struct snd_sof_dev *sdev);
280
281 /* DSP Loader callbacks */
282 int acp_sof_dsp_run(struct snd_sof_dev *sdev);
283 int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev);
284 int acp_sof_load_signed_firmware(struct snd_sof_dev *sdev);
285 int acp_get_bar_index(struct snd_sof_dev *sdev, u32 type);
286
287 /* Block IO callbacks */
288 int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
289 u32 offset, void *src, size_t size);
290 int acp_dsp_block_read(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_type,
291 u32 offset, void *dest, size_t size);
292
293 /* IPC callbacks */
294 irqreturn_t acp_sof_ipc_irq_thread(int irq, void *context);
295 int acp_sof_ipc_msg_data(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps,
296 void *p, size_t sz);
297 int acp_set_stream_data_offset(struct snd_sof_dev *sdev,
298 struct snd_sof_pcm_stream *sps,
299 size_t posn_offset);
300 int acp_sof_ipc_send_msg(struct snd_sof_dev *sdev,
301 struct snd_sof_ipc_msg *msg);
302 int acp_sof_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
303 int acp_sof_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
304 void acp_mailbox_write(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
305 void acp_mailbox_read(struct snd_sof_dev *sdev, u32 offset, void *message, size_t bytes);
306
307 /* ACP - DSP stream callbacks */
308 int acp_dsp_stream_config(struct snd_sof_dev *sdev, struct acp_dsp_stream *stream);
309 int acp_dsp_stream_init(struct snd_sof_dev *sdev);
310 struct acp_dsp_stream *acp_dsp_stream_get(struct snd_sof_dev *sdev, int tag);
311 int acp_dsp_stream_put(struct snd_sof_dev *sdev, struct acp_dsp_stream *acp_stream);
312
313 /*
314 * DSP PCM Operations.
315 */
316 int acp_pcm_open(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
317 int acp_pcm_close(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream);
318 int acp_pcm_hw_params(struct snd_sof_dev *sdev, struct snd_pcm_substream *substream,
319 struct snd_pcm_hw_params *params,
320 struct snd_sof_platform_stream_params *platform_params);
321 snd_pcm_uframes_t acp_pcm_pointer(struct snd_sof_dev *sdev,
322 struct snd_pcm_substream *substream);
323
324 extern const struct snd_sof_dsp_ops sof_acp_common_ops;
325
326 extern struct snd_sof_dsp_ops sof_renoir_ops;
327 int sof_renoir_ops_init(struct snd_sof_dev *sdev);
328 extern struct snd_sof_dsp_ops sof_vangogh_ops;
329 int sof_vangogh_ops_init(struct snd_sof_dev *sdev);
330 extern struct snd_sof_dsp_ops sof_rembrandt_ops;
331 int sof_rembrandt_ops_init(struct snd_sof_dev *sdev);
332 extern struct snd_sof_dsp_ops sof_acp63_ops;
333 int sof_acp63_ops_init(struct snd_sof_dev *sdev);
334
335 extern struct snd_sof_dsp_ops sof_acp70_ops;
336 int sof_acp70_ops_init(struct snd_sof_dev *sdev);
337
338 struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev);
339 /* Machine configuration */
340 int snd_amd_acp_find_config(struct pci_dev *pci);
341
342 /* Trace */
343 int acp_sof_trace_init(struct snd_sof_dev *sdev, struct snd_dma_buffer *dmab,
344 struct sof_ipc_dma_trace_params_ext *dtrace_params);
345 int acp_sof_trace_release(struct snd_sof_dev *sdev);
346
347 /* PM Callbacks */
348 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state);
349 int amd_sof_acp_resume(struct snd_sof_dev *sdev);
350
351 void amd_sof_ipc_dump(struct snd_sof_dev *sdev);
352 void amd_sof_dump(struct snd_sof_dev *sdev, u32 flags);
353
get_chip_info(struct snd_sof_pdata * pdata)354 static inline const struct sof_amd_acp_desc *get_chip_info(struct snd_sof_pdata *pdata)
355 {
356 const struct sof_dev_desc *desc = pdata->desc;
357
358 return desc->chip_info;
359 }
360
361 int acp_probes_register(struct snd_sof_dev *sdev);
362 void acp_probes_unregister(struct snd_sof_dev *sdev);
363
364 extern struct snd_soc_acpi_mach snd_soc_acpi_amd_vangogh_sof_machines[];
365 extern const struct dmi_system_id acp_sof_quirk_table[];
366 #endif
367