xref: /linux/drivers/media/platform/allegro-dvt/allegro-mail.h (revision 0ea5c948cb64bab5bc7a5516774eb8536f05aa0d)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) 2019 Pengutronix, Michael Tretter <kernel@pengutronix.de>
4  *
5  * Allegro VCU firmware mailbox mail definitions
6  */
7 
8 #ifndef ALLEGRO_MAIL_H
9 #define ALLEGRO_MAIL_H
10 
11 #include <linux/kernel.h>
12 
13 enum mcu_msg_type {
14 	MCU_MSG_TYPE_INIT = 0x0000,
15 	MCU_MSG_TYPE_CREATE_CHANNEL = 0x0005,
16 	MCU_MSG_TYPE_DESTROY_CHANNEL = 0x0006,
17 	MCU_MSG_TYPE_ENCODE_FRAME = 0x0007,
18 	MCU_MSG_TYPE_PUT_STREAM_BUFFER = 0x0012,
19 	MCU_MSG_TYPE_PUSH_BUFFER_INTERMEDIATE = 0x000e,
20 	MCU_MSG_TYPE_PUSH_BUFFER_REFERENCE = 0x000f,
21 };
22 
23 enum mcu_msg_version {
24 	MCU_MSG_VERSION_2018_2,
25 	MCU_MSG_VERSION_2019_2,
26 };
27 
28 const char *msg_type_name(enum mcu_msg_type type);
29 
30 struct mcu_msg_header {
31 	enum mcu_msg_type type;
32 	enum mcu_msg_version version;
33 };
34 
35 struct mcu_msg_init_request {
36 	struct mcu_msg_header header;
37 	u32 reserved0;		/* maybe a unused channel id */
38 	u32 suballoc_dma;
39 	u32 suballoc_size;
40 	s32 encoder_buffer_size;
41 	s32 encoder_buffer_color_depth;
42 	s32 num_cores;
43 	s32 clk_rate;
44 };
45 
46 struct mcu_msg_init_response {
47 	struct mcu_msg_header header;
48 	u32 reserved0;
49 };
50 
51 struct create_channel_param {
52 	enum mcu_msg_version version;
53 	u32 layer_id;
54 	u16 width;
55 	u16 height;
56 	u32 videomode;
57 	u32 format;
58 	u32 colorspace;
59 	u32 src_mode;
60 	u32 src_bit_depth;
61 	u8 profile;
62 	u16 constraint_set_flags;
63 	u32 codec;
64 	u16 level;
65 	u16 tier;
66 	u32 log2_max_poc;
67 	u32 log2_max_frame_num;
68 	u32 temporal_mvp_enable;
69 	u32 enable_reordering;
70 	u32 dbf_ovr_en;
71 	u32 override_lf;
72 	u32 num_ref_idx_l0;
73 	u32 num_ref_idx_l1;
74 	u32 custom_lda;
75 	u32 rdo_cost_mode;
76 	u32 lf;
77 	u32 lf_x_tile;
78 	u32 lf_x_slice;
79 	s8 beta_offset;
80 	s8 tc_offset;
81 	u16 reserved10;
82 	u32 unknown11;
83 	u32 unknown12;
84 	u16 num_slices;
85 	u32 encoder_buffer_offset;
86 	u32 encoder_buffer_enabled;
87 	u16 clip_hrz_range;
88 	u16 clip_vrt_range;
89 	u16 me_range[4];
90 	u8 max_cu_size;
91 	u8 min_cu_size;
92 	u8 max_tu_size;
93 	u8 min_tu_size;
94 	u8 max_transfo_depth_inter;
95 	u8 max_transfo_depth_intra;
96 	u16 reserved20;
97 	u32 entropy_mode;
98 	u32 wp_mode;
99 
100 	/* rate control param */
101 	u32 rate_control_mode;
102 	u32 initial_rem_delay;
103 	u32 cpb_size;
104 	u16 framerate;
105 	u16 clk_ratio;
106 	u32 target_bitrate;
107 	u32 max_bitrate;
108 	u16 initial_qp;
109 	u16 min_qp;
110 	u16 max_qp;
111 	s16 ip_delta;
112 	s16 pb_delta;
113 	u16 golden_ref;
114 	u16 golden_delta;
115 	u16 golden_ref_frequency;
116 	u32 rate_control_option;
117 	u32 num_pixel;
118 	u16 max_psnr;
119 	u16 max_pixel_value;
120 	u32 maxpicturesize[3];
121 
122 	/* gop param */
123 	u32 gop_ctrl_mode;
124 	u32 freq_idr;
125 	u32 freq_lt;
126 	u32 gdr_mode;
127 	u16 gop_length;
128 	u8 num_b;
129 	u8 freq_golden_ref;
130 	u32 enable_lt;
131 	u32 tmpdqp;
132 
133 	u32 subframe_latency;
134 	u32 lda_control_mode;
135 	u32 unknown41;
136 
137 	u32 lda_factors[6];
138 
139 	u32 max_num_merge_cand;
140 };
141 
142 struct mcu_msg_create_channel {
143 	struct mcu_msg_header header;
144 	u32 user_id;
145 	u32 *blob;
146 	size_t blob_size;
147 	u32 blob_mcu_addr;
148 	u32 ep1_addr;
149 };
150 
151 struct mcu_msg_create_channel_response {
152 	struct mcu_msg_header header;
153 	u32 channel_id;
154 	u32 user_id;
155 	u32 options;
156 	u32 num_core;
157 	u32 num_ref_idx_l0;
158 	u32 num_ref_idx_l1;
159 	u32 int_buffers_count;
160 	u32 int_buffers_size;
161 	u32 rec_buffers_count;
162 	u32 rec_buffers_size;
163 	u32 reserved;
164 	u32 error_code;
165 };
166 
167 struct mcu_msg_destroy_channel {
168 	struct mcu_msg_header header;
169 	u32 channel_id;
170 };
171 
172 struct mcu_msg_destroy_channel_response {
173 	struct mcu_msg_header header;
174 	u32 channel_id;
175 };
176 
177 struct mcu_msg_push_buffers_internal_buffer {
178 	u32 dma_addr;
179 	u32 mcu_addr;
180 	u32 size;
181 };
182 
183 struct mcu_msg_push_buffers_internal {
184 	struct mcu_msg_header header;
185 	u32 channel_id;
186 	size_t num_buffers;
187 	struct mcu_msg_push_buffers_internal_buffer buffer[] __counted_by(num_buffers);
188 };
189 
190 struct mcu_msg_put_stream_buffer {
191 	struct mcu_msg_header header;
192 	u32 channel_id;
193 	u32 dma_addr;
194 	u32 mcu_addr;
195 	u32 size;
196 	u32 offset;
197 	u64 dst_handle;
198 };
199 
200 struct mcu_msg_encode_frame {
201 	struct mcu_msg_header header;
202 	u32 channel_id;
203 	u32 reserved;
204 
205 	u32 encoding_options;
206 #define AL_OPT_USE_QP_TABLE		BIT(0)
207 #define AL_OPT_FORCE_LOAD		BIT(1)
208 #define AL_OPT_USE_L2			BIT(2)
209 #define AL_OPT_DISABLE_INTRA		BIT(3)
210 #define AL_OPT_DEPENDENT_SLICES		BIT(4)
211 
212 	s16 pps_qp;
213 	u16 padding;
214 	u64 user_param;
215 	u64 src_handle;
216 
217 	u32 request_options;
218 #define AL_OPT_SCENE_CHANGE		BIT(0)
219 #define AL_OPT_RESTART_GOP		BIT(1)
220 #define AL_OPT_USE_LONG_TERM		BIT(2)
221 #define AL_OPT_UPDATE_PARAMS		BIT(3)
222 
223 	/* u32 scene_change_delay (optional) */
224 	/* rate control param (optional) */
225 	/* gop param (optional) */
226 	/* dynamic resolution params (optional) */
227 	u32 src_y;
228 	u32 src_uv;
229 	u32 is_10_bit;
230 	u32 stride;
231 	u32 format;
232 	u32 ep2;
233 	u64 ep2_v;
234 };
235 
236 struct mcu_msg_encode_frame_response {
237 	struct mcu_msg_header header;
238 	u32 channel_id;
239 	u64 dst_handle;		/* see mcu_msg_put_stream_buffer */
240 	u64 user_param;		/* see mcu_msg_encode_frame */
241 	u64 src_handle;		/* see mcu_msg_encode_frame */
242 	u16 skip;
243 	u16 is_ref;
244 	u32 initial_removal_delay;
245 	u32 dpb_output_delay;
246 	u32 size;
247 	u32 frame_tag_size;
248 	s32 stuffing;
249 	s32 filler;
250 	u16 num_column;
251 	u16 num_row;
252 	u16 qp;
253 	u8 num_ref_idx_l0;
254 	u8 num_ref_idx_l1;
255 	u32 partition_table_offset;
256 	s32 partition_table_size;
257 	u32 sum_complex;
258 	s32 tile_width[4];
259 	s32 tile_height[22];
260 	u32 error_code;
261 
262 	u32 slice_type;
263 #define AL_ENC_SLICE_TYPE_B             0
264 #define AL_ENC_SLICE_TYPE_P             1
265 #define AL_ENC_SLICE_TYPE_I             2
266 
267 	u32 pic_struct;
268 	u8 is_idr;
269 	u8 is_first_slice;
270 	u8 is_last_slice;
271 	u8 reserved;
272 	u16 pps_qp;
273 	u16 reserved1;
274 	u32 reserved2;
275 	u32 reserved3;
276 	u32 reserved4;
277 	u32 reserved5;
278 	u32 reserved6;
279 };
280 
281 union mcu_msg_response {
282 	struct mcu_msg_header header;
283 	struct mcu_msg_init_response init;
284 	struct mcu_msg_create_channel_response create_channel;
285 	struct mcu_msg_destroy_channel_response destroy_channel;
286 	struct mcu_msg_encode_frame_response encode_frame;
287 };
288 
289 ssize_t allegro_encode_config_blob(u32 *dst, struct create_channel_param *param);
290 ssize_t allegro_decode_config_blob(struct create_channel_param *param,
291 				   struct mcu_msg_create_channel_response *msg,
292 				   u32 *src);
293 
294 int allegro_decode_mail(void *msg, u32 *src);
295 ssize_t allegro_encode_mail(u32 *dst, void *msg);
296 
297 #endif
298