1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_INTF_H 8 #define _DPU_HW_INTF_H 9 10 #include "dpu_hw_catalog.h" 11 #include "dpu_hw_mdss.h" 12 #include "dpu_hw_util.h" 13 14 struct dpu_hw_intf; 15 struct dpu_vsync_source_cfg; 16 17 /* intf timing settings */ 18 struct dpu_hw_intf_timing_params { 19 u32 width; /* active width */ 20 u32 height; /* active height */ 21 u32 xres; /* Display panel width */ 22 u32 yres; /* Display panel height */ 23 24 u32 h_back_porch; 25 u32 h_front_porch; 26 u32 v_back_porch; 27 u32 v_front_porch; 28 u32 hsync_pulse_width; 29 u32 vsync_pulse_width; 30 u32 hsync_polarity; 31 u32 vsync_polarity; 32 u32 border_clr; 33 u32 underflow_clr; 34 u32 hsync_skew; 35 36 bool wide_bus_en; 37 bool compression_en; 38 }; 39 40 struct dpu_hw_intf_prog_fetch { 41 u8 enable; 42 /* vsync counter for the front porch pixel line */ 43 u32 fetch_start; 44 }; 45 46 struct dpu_hw_intf_status { 47 u8 is_en; /* interface timing engine is enabled or not */ 48 u8 is_prog_fetch_en; /* interface prog fetch counter is enabled or not */ 49 u32 frame_count; /* frame count since timing engine enabled */ 50 u32 line_count; /* current line count including blanking */ 51 }; 52 53 struct dpu_hw_intf_cmd_mode_cfg { 54 u8 data_compress; /* enable data compress between dpu and dsi */ 55 u8 wide_bus_en; /* enable databus widen mode */ 56 }; 57 58 /** 59 * struct dpu_hw_intf_ops : Interface to the interface Hw driver functions 60 * Assumption is these functions will be called after clocks are enabled 61 * @setup_timing_gen : programs the timing engine 62 * @setup_prg_fetch : enables/disables the programmable fetch logic 63 * @enable_timing: enable/disable timing engine 64 * @get_status: returns if timing engine is enabled or not 65 * @get_line_count: reads current vertical line counter 66 * @bind_pingpong_blk: enable/disable the connection with pingpong which will 67 * feed pixels to this interface 68 * @setup_misr: enable/disable MISR 69 * @collect_misr: read MISR signature 70 * @enable_tearcheck: Enables vsync generation and sets up init value of read 71 * pointer and programs the tear check configuration 72 * @disable_tearcheck: Disables tearcheck block 73 * @connect_external_te: Read, modify, write to either set or clear listening to external TE 74 * Returns 1 if TE was originally connected, 0 if not, or -ERROR 75 * @vsync_sel: Select vsync signal for tear-effect configuration 76 * @disable_autorefresh: Disable autorefresh if enabled 77 * @program_intf_cmd_cfg: Program the DPU to interface datapath for command mode 78 */ 79 struct dpu_hw_intf_ops { 80 void (*setup_timing_gen)(struct dpu_hw_intf *intf, 81 const struct dpu_hw_intf_timing_params *p, 82 const struct msm_format *fmt); 83 84 void (*setup_prg_fetch)(struct dpu_hw_intf *intf, 85 const struct dpu_hw_intf_prog_fetch *fetch); 86 87 void (*enable_timing)(struct dpu_hw_intf *intf, 88 u8 enable); 89 90 void (*get_status)(struct dpu_hw_intf *intf, 91 struct dpu_hw_intf_status *status); 92 93 u32 (*get_line_count)(struct dpu_hw_intf *intf); 94 95 void (*bind_pingpong_blk)(struct dpu_hw_intf *intf, 96 const enum dpu_pingpong pp); 97 void (*setup_misr)(struct dpu_hw_intf *intf); 98 int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value); 99 100 // Tearcheck on INTF since DPU 5.0.0 101 102 int (*enable_tearcheck)(struct dpu_hw_intf *intf, struct dpu_hw_tear_check *cfg); 103 104 int (*disable_tearcheck)(struct dpu_hw_intf *intf); 105 106 int (*connect_external_te)(struct dpu_hw_intf *intf, bool enable_external_te); 107 108 void (*vsync_sel)(struct dpu_hw_intf *intf, struct dpu_vsync_source_cfg *cfg); 109 110 void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t encoder_id, u16 vdisplay); 111 112 void (*program_intf_cmd_cfg)(struct dpu_hw_intf *intf, 113 struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg); 114 }; 115 116 struct dpu_hw_intf { 117 struct dpu_hw_blk_reg_map hw; 118 119 /* intf */ 120 enum dpu_intf idx; 121 const struct dpu_intf_cfg *cap; 122 123 const struct dpu_mdss_version *mdss_ver; 124 125 /* ops */ 126 struct dpu_hw_intf_ops ops; 127 }; 128 129 struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev, 130 const struct dpu_intf_cfg *cfg, 131 void __iomem *addr, 132 const struct dpu_mdss_version *mdss_rev); 133 134 #endif /*_DPU_HW_INTF_H */ 135