1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 /* 24 * link_encoder.h 25 * 26 * Created on: Oct 6, 2015 27 * Author: yonsun 28 */ 29 30 #ifndef LINK_ENCODER_H_ 31 #define LINK_ENCODER_H_ 32 33 #include "grph_object_defs.h" 34 #include "signal_types.h" 35 #include "dc_types.h" 36 37 struct dc_context; 38 struct encoder_set_dp_phy_pattern_param; 39 struct link_mst_stream_allocation_table; 40 struct dc_link_settings; 41 struct link_training_settings; 42 struct pipe_ctx; 43 44 struct encoder_init_data { 45 enum channel_id channel; 46 struct graphics_object_id connector; 47 struct gpio *hpd_gpio; 48 enum hpd_source_id hpd_source; 49 /* TODO: in DAL2, here was pointer to EventManagerInterface */ 50 struct graphics_object_id encoder; 51 struct graphics_object_id analog_encoder; 52 enum engine_id analog_engine; 53 struct dc_context *ctx; 54 enum transmitter transmitter; 55 }; 56 57 struct encoder_feature_support { 58 union { 59 struct { 60 uint32_t IS_HBR2_CAPABLE:1; 61 uint32_t IS_HBR3_CAPABLE:1; 62 uint32_t IS_TPS3_CAPABLE:1; 63 uint32_t IS_TPS4_CAPABLE:1; 64 uint32_t HDMI_6GB_EN:1; 65 uint32_t IS_DP2_CAPABLE:1; 66 uint32_t IS_UHBR10_CAPABLE:1; 67 uint32_t IS_UHBR13_5_CAPABLE:1; 68 uint32_t IS_UHBR20_CAPABLE:1; 69 uint32_t DP_IS_USB_C:1; 70 } bits; 71 uint32_t raw; 72 } flags; 73 74 enum dc_color_depth max_hdmi_deep_color; 75 unsigned int max_hdmi_pixel_clock; 76 bool hdmi_ycbcr420_supported; 77 bool dp_ycbcr420_supported; 78 bool fec_supported; 79 }; 80 81 struct link_encoder { 82 const struct link_encoder_funcs *funcs; 83 int32_t aux_channel_offset; 84 struct dc_context *ctx; 85 struct graphics_object_id id; 86 struct graphics_object_id analog_id; 87 struct graphics_object_id connector; 88 uint32_t output_signals; 89 enum engine_id preferred_engine; 90 enum engine_id analog_engine; 91 struct encoder_feature_support features; 92 enum transmitter transmitter; 93 struct gpio *hpd_gpio; 94 enum hpd_source_id hpd_source; 95 bool usbc_combo_phy; 96 }; 97 98 struct link_enc_state { 99 100 uint32_t dphy_fec_en; 101 uint32_t dphy_fec_ready_shadow; 102 uint32_t dphy_fec_active_status; 103 uint32_t dp_link_training_complete; 104 105 }; 106 107 enum encoder_type_select { 108 ENCODER_TYPE_DIG = 0, 109 ENCODER_TYPE_HDMI_FRL = 1, 110 ENCODER_TYPE_DP_128B132B = 2 111 }; 112 113 struct link_encoder_funcs { 114 void (*read_state)( 115 struct link_encoder *enc, struct link_enc_state *s); 116 bool (*validate_output_with_stream)( 117 struct link_encoder *enc, const struct dc_stream_state *stream); 118 void (*hw_init)(struct link_encoder *enc); 119 void (*setup)(struct link_encoder *enc, 120 enum signal_type signal); 121 void (*enable_tmds_output)(struct link_encoder *enc, 122 enum clock_source_id clock_source, 123 enum dc_color_depth color_depth, 124 enum signal_type signal, 125 uint32_t pixel_clock); 126 void (*enable_dp_output)(struct link_encoder *enc, 127 const struct dc_link_settings *link_settings, 128 enum clock_source_id clock_source); 129 void (*enable_dp_mst_output)(struct link_encoder *enc, 130 const struct dc_link_settings *link_settings, 131 enum clock_source_id clock_source); 132 void (*enable_lvds_output)(struct link_encoder *enc, 133 enum clock_source_id clock_source, 134 uint32_t pixel_clock); 135 void (*enable_analog_output)(struct link_encoder *enc, 136 uint32_t pixel_clock); 137 void (*disable_output)(struct link_encoder *link_enc, 138 enum signal_type signal); 139 void (*dp_set_lane_settings)(struct link_encoder *enc, 140 const struct dc_link_settings *link_settings, 141 const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]); 142 void (*dp_set_phy_pattern)(struct link_encoder *enc, 143 const struct encoder_set_dp_phy_pattern_param *para); 144 void (*update_mst_stream_allocation_table)( 145 struct link_encoder *enc, 146 const struct link_mst_stream_allocation_table *table); 147 void (*psr_program_dp_dphy_fast_training)(struct link_encoder *enc, 148 bool exit_link_training_required); 149 void (*psr_program_secondary_packet)(struct link_encoder *enc, 150 unsigned int sdp_transmit_line_num_deadline); 151 void (*connect_dig_be_to_fe)(struct link_encoder *enc, 152 enum engine_id engine, 153 bool connect); 154 void (*enable_hpd)(struct link_encoder *enc); 155 void (*disable_hpd)(struct link_encoder *enc); 156 bool (*is_dig_enabled)(struct link_encoder *enc); 157 unsigned int (*get_dig_frontend)(struct link_encoder *enc); 158 void (*destroy)(struct link_encoder **enc); 159 160 void (*fec_set_enable)(struct link_encoder *enc, 161 bool enable); 162 163 void (*fec_set_ready)(struct link_encoder *enc, 164 bool ready); 165 166 bool (*fec_is_active)(struct link_encoder *enc); 167 bool (*is_in_alt_mode) (struct link_encoder *enc); 168 169 void (*get_max_link_cap)(struct link_encoder *enc, 170 struct dc_link_settings *link_settings); 171 172 enum signal_type (*get_dig_mode)( 173 struct link_encoder *enc); 174 175 void (*set_dio_phy_mux)( 176 struct link_encoder *enc, 177 enum encoder_type_select sel, 178 uint32_t hpo_inst); 179 void (*enable_dpia_output)(struct link_encoder *enc, 180 const struct dc_link_settings *link_settings, 181 uint8_t dpia_id, 182 uint8_t digmode, 183 uint8_t fec_rdy); 184 void (*disable_dpia_output)(struct link_encoder *link_enc, 185 uint8_t dpia_id, 186 uint8_t digmode); 187 bool (*get_hpd_state)(struct link_encoder *enc); 188 bool (*program_hpd_filter)(struct link_encoder *enc, int delay_on_connect_in_ms, int delay_on_disconnect_in_ms); 189 }; 190 191 /* 192 * Used to track assignments of links (display endpoints) to link encoders. 193 * 194 * Entry in link_enc_assignments table in struct resource_context. 195 * Entries only marked valid once encoder assigned to a link and invalidated once unassigned. 196 * Uses engine ID as identifier since PHY ID not relevant for USB4 DPIA endpoint. 197 */ 198 struct link_enc_assignment { 199 bool valid; 200 struct display_endpoint_id ep_id; 201 enum engine_id eng_id; 202 struct dc_stream_state *stream; 203 }; 204 205 enum link_enc_cfg_mode { 206 LINK_ENC_CFG_STEADY, /* Normal operation - use current_state. */ 207 LINK_ENC_CFG_TRANSIENT /* During commit state - use state to be committed. */ 208 }; 209 210 enum dp2_link_mode { 211 DP2_LINK_TRAINING_TPS1, 212 DP2_LINK_TRAINING_TPS2, 213 DP2_LINK_ACTIVE, 214 DP2_TEST_PATTERN 215 }; 216 217 enum dp2_phy_tp_select { 218 DP_DPHY_TP_SELECT_TPS1, 219 DP_DPHY_TP_SELECT_TPS2, 220 DP_DPHY_TP_SELECT_PRBS, 221 DP_DPHY_TP_SELECT_CUSTOM, 222 DP_DPHY_TP_SELECT_SQUARE 223 }; 224 225 enum dp2_phy_tp_prbs { 226 DP_DPHY_TP_PRBS7, 227 DP_DPHY_TP_PRBS9, 228 DP_DPHY_TP_PRBS11, 229 DP_DPHY_TP_PRBS15, 230 DP_DPHY_TP_PRBS23, 231 DP_DPHY_TP_PRBS31 232 }; 233 234 struct hpo_dp_link_enc_state { 235 uint32_t link_enc_enabled; 236 uint32_t link_mode; 237 uint32_t lane_count; 238 uint32_t slot_count[4]; 239 uint32_t stream_src[4]; 240 uint32_t vc_rate_x[4]; 241 uint32_t vc_rate_y[4]; 242 }; 243 244 struct hpo_dp_link_encoder { 245 const struct hpo_dp_link_encoder_funcs *funcs; 246 struct dc_context *ctx; 247 int inst; 248 enum engine_id preferred_engine; 249 enum transmitter transmitter; 250 enum hpd_source_id hpd_source; 251 }; 252 253 struct hpo_dp_link_encoder_funcs { 254 255 void (*enable_link_phy)(struct hpo_dp_link_encoder *enc, 256 const struct dc_link_settings *link_settings, 257 enum transmitter transmitter, 258 enum hpd_source_id hpd_source); 259 260 void (*disable_link_phy)(struct hpo_dp_link_encoder *link_enc, 261 enum signal_type signal); 262 263 void (*link_enable)( 264 struct hpo_dp_link_encoder *enc, 265 enum dc_lane_count num_lanes); 266 267 void (*link_disable)( 268 struct hpo_dp_link_encoder *enc); 269 270 void (*set_link_test_pattern)( 271 struct hpo_dp_link_encoder *enc, 272 struct encoder_set_dp_phy_pattern_param *tp_params); 273 274 void (*update_stream_allocation_table)( 275 struct hpo_dp_link_encoder *enc, 276 const struct link_mst_stream_allocation_table *table); 277 278 void (*set_throttled_vcp_size)( 279 struct hpo_dp_link_encoder *enc, 280 uint32_t stream_encoder_inst, 281 struct fixed31_32 avg_time_slots_per_mtp); 282 283 bool (*is_in_alt_mode) ( 284 struct hpo_dp_link_encoder *enc); 285 286 void (*read_state)( 287 struct hpo_dp_link_encoder *enc, 288 struct hpo_dp_link_enc_state *state); 289 290 void (*set_ffe)( 291 struct hpo_dp_link_encoder *enc, 292 const struct dc_link_settings *link_settings, 293 uint8_t ffe_preset); 294 }; 295 296 #endif /* LINK_ENCODER_H_ */ 297