1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022-2023 Intel Corporation 4 */ 5 6 #ifndef _XE_DEVICE_TYPES_H_ 7 #define _XE_DEVICE_TYPES_H_ 8 9 #include <linux/pci.h> 10 11 #include <drm/drm_device.h> 12 #include <drm/drm_file.h> 13 #include <drm/ttm/ttm_device.h> 14 15 #include "xe_devcoredump_types.h" 16 #include "xe_heci_gsc.h" 17 #include "xe_gt_types.h" 18 #include "xe_lmtt_types.h" 19 #include "xe_memirq_types.h" 20 #include "xe_oa.h" 21 #include "xe_platform_types.h" 22 #include "xe_pt_types.h" 23 #include "xe_sriov_types.h" 24 #include "xe_step_types.h" 25 26 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG) 27 #define TEST_VM_OPS_ERROR 28 #endif 29 30 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) 31 #include "soc/intel_pch.h" 32 #include "intel_display_core.h" 33 #include "intel_display_device.h" 34 #endif 35 36 struct xe_ggtt; 37 struct xe_pat_ops; 38 39 #define XE_BO_INVALID_OFFSET LONG_MAX 40 41 #define GRAPHICS_VER(xe) ((xe)->info.graphics_verx100 / 100) 42 #define MEDIA_VER(xe) ((xe)->info.media_verx100 / 100) 43 #define GRAPHICS_VERx100(xe) ((xe)->info.graphics_verx100) 44 #define MEDIA_VERx100(xe) ((xe)->info.media_verx100) 45 #define IS_DGFX(xe) ((xe)->info.is_dgfx) 46 #define HAS_HECI_GSCFI(xe) ((xe)->info.has_heci_gscfi) 47 #define HAS_HECI_CSCFI(xe) ((xe)->info.has_heci_cscfi) 48 49 #define XE_VRAM_FLAGS_NEED64K BIT(0) 50 51 #define XE_GT0 0 52 #define XE_GT1 1 53 #define XE_MAX_TILES_PER_DEVICE (XE_GT1 + 1) 54 55 #define XE_MAX_ASID (BIT(20)) 56 57 #define IS_PLATFORM_STEP(_xe, _platform, min_step, max_step) \ 58 ((_xe)->info.platform == (_platform) && \ 59 (_xe)->info.step.graphics >= (min_step) && \ 60 (_xe)->info.step.graphics < (max_step)) 61 #define IS_SUBPLATFORM_STEP(_xe, _platform, sub, min_step, max_step) \ 62 ((_xe)->info.platform == (_platform) && \ 63 (_xe)->info.subplatform == (sub) && \ 64 (_xe)->info.step.graphics >= (min_step) && \ 65 (_xe)->info.step.graphics < (max_step)) 66 67 #define tile_to_xe(tile__) \ 68 _Generic(tile__, \ 69 const struct xe_tile * : (const struct xe_device *)((tile__)->xe), \ 70 struct xe_tile * : (tile__)->xe) 71 72 /** 73 * struct xe_mem_region - memory region structure 74 * This is used to describe a memory region in xe 75 * device, such as HBM memory or CXL extension memory. 76 */ 77 struct xe_mem_region { 78 /** @io_start: IO start address of this VRAM instance */ 79 resource_size_t io_start; 80 /** 81 * @io_size: IO size of this VRAM instance 82 * 83 * This represents how much of this VRAM we can access 84 * via the CPU through the VRAM BAR. This can be smaller 85 * than @usable_size, in which case only part of VRAM is CPU 86 * accessible (typically the first 256M). This 87 * configuration is known as small-bar. 88 */ 89 resource_size_t io_size; 90 /** @dpa_base: This memory regions's DPA (device physical address) base */ 91 resource_size_t dpa_base; 92 /** 93 * @usable_size: usable size of VRAM 94 * 95 * Usable size of VRAM excluding reserved portions 96 * (e.g stolen mem) 97 */ 98 resource_size_t usable_size; 99 /** 100 * @actual_physical_size: Actual VRAM size 101 * 102 * Actual VRAM size including reserved portions 103 * (e.g stolen mem) 104 */ 105 resource_size_t actual_physical_size; 106 /** @mapping: pointer to VRAM mappable space */ 107 void __iomem *mapping; 108 }; 109 110 /** 111 * struct xe_tile - hardware tile structure 112 * 113 * From a driver perspective, a "tile" is effectively a complete GPU, containing 114 * an SGunit, 1-2 GTs, and (for discrete platforms) VRAM. 115 * 116 * Multi-tile platforms effectively bundle multiple GPUs behind a single PCI 117 * device and designate one "root" tile as being responsible for external PCI 118 * communication. PCI BAR0 exposes the GGTT and MMIO register space for each 119 * tile in a stacked layout, and PCI BAR2 exposes the local memory associated 120 * with each tile similarly. Device-wide interrupts can be enabled/disabled 121 * at the root tile, and the MSTR_TILE_INTR register will report which tiles 122 * have interrupts that need servicing. 123 */ 124 struct xe_tile { 125 /** @xe: Backpointer to tile's PCI device */ 126 struct xe_device *xe; 127 128 /** @id: ID of the tile */ 129 u8 id; 130 131 /** 132 * @primary_gt: Primary GT 133 */ 134 struct xe_gt *primary_gt; 135 136 /** 137 * @media_gt: Media GT 138 * 139 * Only present on devices with media version >= 13. 140 */ 141 struct xe_gt *media_gt; 142 143 /** 144 * @mmio: MMIO info for a tile. 145 * 146 * Each tile has its own 16MB space in BAR0, laid out as: 147 * * 0-4MB: registers 148 * * 4MB-8MB: reserved 149 * * 8MB-16MB: global GTT 150 */ 151 struct { 152 /** @mmio.size: size of tile's MMIO space */ 153 size_t size; 154 155 /** @mmio.regs: pointer to tile's MMIO space (starting with registers) */ 156 void __iomem *regs; 157 } mmio; 158 159 /** 160 * @mmio_ext: MMIO-extension info for a tile. 161 * 162 * Each tile has its own additional 256MB (28-bit) MMIO-extension space. 163 */ 164 struct { 165 /** @mmio_ext.size: size of tile's additional MMIO-extension space */ 166 size_t size; 167 168 /** @mmio_ext.regs: pointer to tile's additional MMIO-extension space */ 169 void __iomem *regs; 170 } mmio_ext; 171 172 /** @mem: memory management info for tile */ 173 struct { 174 /** 175 * @mem.vram: VRAM info for tile. 176 * 177 * Although VRAM is associated with a specific tile, it can 178 * still be accessed by all tiles' GTs. 179 */ 180 struct xe_mem_region vram; 181 182 /** @mem.vram_mgr: VRAM TTM manager */ 183 struct xe_ttm_vram_mgr *vram_mgr; 184 185 /** @mem.ggtt: Global graphics translation table */ 186 struct xe_ggtt *ggtt; 187 188 /** 189 * @mem.kernel_bb_pool: Pool from which batchbuffers are allocated. 190 * 191 * Media GT shares a pool with its primary GT. 192 */ 193 struct xe_sa_manager *kernel_bb_pool; 194 } mem; 195 196 /** @sriov: tile level virtualization data */ 197 union { 198 struct { 199 /** @sriov.pf.lmtt: Local Memory Translation Table. */ 200 struct xe_lmtt lmtt; 201 } pf; 202 struct { 203 /** @sriov.vf.memirq: Memory Based Interrupts. */ 204 struct xe_memirq memirq; 205 206 /** @sriov.vf.ggtt_balloon: GGTT regions excluded from use. */ 207 struct xe_ggtt_node *ggtt_balloon[2]; 208 } vf; 209 } sriov; 210 211 /** @pcode: tile's PCODE */ 212 struct { 213 /** @pcode.lock: protecting tile's PCODE mailbox data */ 214 struct mutex lock; 215 } pcode; 216 217 /** @migrate: Migration helper for vram blits and clearing */ 218 struct xe_migrate *migrate; 219 220 /** @sysfs: sysfs' kobj used by xe_tile_sysfs */ 221 struct kobject *sysfs; 222 }; 223 224 /** 225 * struct xe_device - Top level struct of XE device 226 */ 227 struct xe_device { 228 /** @drm: drm device */ 229 struct drm_device drm; 230 231 /** @devcoredump: device coredump */ 232 struct xe_devcoredump devcoredump; 233 234 /** @info: device info */ 235 struct intel_device_info { 236 /** @info.platform_name: platform name */ 237 const char *platform_name; 238 /** @info.graphics_name: graphics IP name */ 239 const char *graphics_name; 240 /** @info.media_name: media IP name */ 241 const char *media_name; 242 /** @info.tile_mmio_ext_size: size of MMIO extension space, per-tile */ 243 u32 tile_mmio_ext_size; 244 /** @info.graphics_verx100: graphics IP version */ 245 u32 graphics_verx100; 246 /** @info.media_verx100: media IP version */ 247 u32 media_verx100; 248 /** @info.mem_region_mask: mask of valid memory regions */ 249 u32 mem_region_mask; 250 /** @info.platform: XE platform enum */ 251 enum xe_platform platform; 252 /** @info.subplatform: XE subplatform enum */ 253 enum xe_subplatform subplatform; 254 /** @info.devid: device ID */ 255 u16 devid; 256 /** @info.revid: device revision */ 257 u8 revid; 258 /** @info.step: stepping information for each IP */ 259 struct xe_step_info step; 260 /** @info.dma_mask_size: DMA address bits */ 261 u8 dma_mask_size; 262 /** @info.vram_flags: Vram flags */ 263 u8 vram_flags; 264 /** @info.tile_count: Number of tiles */ 265 u8 tile_count; 266 /** @info.gt_count: Total number of GTs for entire device */ 267 u8 gt_count; 268 /** @info.vm_max_level: Max VM level */ 269 u8 vm_max_level; 270 /** @info.va_bits: Maximum bits of a virtual address */ 271 u8 va_bits; 272 273 /** @info.is_dgfx: is discrete device */ 274 u8 is_dgfx:1; 275 /** @info.has_asid: Has address space ID */ 276 u8 has_asid:1; 277 /** @info.force_execlist: Forced execlist submission */ 278 u8 force_execlist:1; 279 /** @info.has_flat_ccs: Whether flat CCS metadata is used */ 280 u8 has_flat_ccs:1; 281 /** @info.has_llc: Device has a shared CPU+GPU last level cache */ 282 u8 has_llc:1; 283 /** @info.has_mmio_ext: Device has extra MMIO address range */ 284 u8 has_mmio_ext:1; 285 /** @info.has_range_tlb_invalidation: Has range based TLB invalidations */ 286 u8 has_range_tlb_invalidation:1; 287 /** @info.has_sriov: Supports SR-IOV */ 288 u8 has_sriov:1; 289 /** @info.has_usm: Device has unified shared memory support */ 290 u8 has_usm:1; 291 /** 292 * @info.probe_display: Probe display hardware. If set to 293 * false, the driver will behave as if there is no display 294 * hardware present and will not try to read/write to it in any 295 * way. The display hardware, if it exists, will not be 296 * exposed to userspace and will be left untouched in whatever 297 * state the firmware or bootloader left it in. 298 */ 299 u8 probe_display:1; 300 /** @info.skip_mtcfg: skip Multi-Tile configuration from MTCFG register */ 301 u8 skip_mtcfg:1; 302 /** @info.skip_pcode: skip access to PCODE uC */ 303 u8 skip_pcode:1; 304 /** @info.has_heci_gscfi: device has heci gscfi */ 305 u8 has_heci_gscfi:1; 306 /** @info.has_heci_cscfi: device has heci cscfi */ 307 u8 has_heci_cscfi:1; 308 /** @info.skip_guc_pc: Skip GuC based PM feature init */ 309 u8 skip_guc_pc:1; 310 /** @info.has_atomic_enable_pte_bit: Device has atomic enable PTE bit */ 311 u8 has_atomic_enable_pte_bit:1; 312 /** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */ 313 u8 has_device_atomics_on_smem:1; 314 } info; 315 316 /** @irq: device interrupt state */ 317 struct { 318 /** @irq.lock: lock for processing irq's on this device */ 319 spinlock_t lock; 320 321 /** @irq.enabled: interrupts enabled on this device */ 322 bool enabled; 323 } irq; 324 325 /** @ttm: ttm device */ 326 struct ttm_device ttm; 327 328 /** @mmio: mmio info for device */ 329 struct { 330 /** @mmio.size: size of MMIO space for device */ 331 size_t size; 332 /** @mmio.regs: pointer to MMIO space for device */ 333 void __iomem *regs; 334 } mmio; 335 336 /** @mem: memory info for device */ 337 struct { 338 /** @mem.vram: VRAM info for device */ 339 struct xe_mem_region vram; 340 /** @mem.sys_mgr: system TTM manager */ 341 struct ttm_resource_manager sys_mgr; 342 } mem; 343 344 /** @sriov: device level virtualization data */ 345 struct { 346 /** @sriov.__mode: SR-IOV mode (Don't access directly!) */ 347 enum xe_sriov_mode __mode; 348 349 /** @sriov.pf: PF specific data */ 350 struct xe_device_pf pf; 351 352 /** @sriov.wq: workqueue used by the virtualization workers */ 353 struct workqueue_struct *wq; 354 } sriov; 355 356 /** @clients: drm clients info */ 357 struct { 358 /** @clients.lock: Protects drm clients info */ 359 spinlock_t lock; 360 361 /** @clients.count: number of drm clients */ 362 u64 count; 363 } clients; 364 365 /** @usm: unified memory state */ 366 struct { 367 /** @usm.asid: convert a ASID to VM */ 368 struct xarray asid_to_vm; 369 /** @usm.next_asid: next ASID, used to cyclical alloc asids */ 370 u32 next_asid; 371 /** @usm.lock: protects UM state */ 372 struct mutex lock; 373 } usm; 374 375 /** @pinned: pinned BO state */ 376 struct { 377 /** @pinned.lock: protected pinned BO list state */ 378 spinlock_t lock; 379 /** @pinned.kernel_bo_present: pinned kernel BO that are present */ 380 struct list_head kernel_bo_present; 381 /** @pinned.evicted: pinned BO that have been evicted */ 382 struct list_head evicted; 383 /** @pinned.external_vram: pinned external BO in vram*/ 384 struct list_head external_vram; 385 } pinned; 386 387 /** @ufence_wq: user fence wait queue */ 388 wait_queue_head_t ufence_wq; 389 390 /** @preempt_fence_wq: used to serialize preempt fences */ 391 struct workqueue_struct *preempt_fence_wq; 392 393 /** @ordered_wq: used to serialize compute mode resume */ 394 struct workqueue_struct *ordered_wq; 395 396 /** @unordered_wq: used to serialize unordered work, mostly display */ 397 struct workqueue_struct *unordered_wq; 398 399 /** @tiles: device tiles */ 400 struct xe_tile tiles[XE_MAX_TILES_PER_DEVICE]; 401 402 /** 403 * @mem_access: keep track of memory access in the device, possibly 404 * triggering additional actions when they occur. 405 */ 406 struct { 407 /** 408 * @mem_access.vram_userfault: Encapsulate vram_userfault 409 * related stuff 410 */ 411 struct { 412 /** 413 * @mem_access.vram_userfault.lock: Protects access to 414 * @vram_usefault.list Using mutex instead of spinlock 415 * as lock is applied to entire list operation which 416 * may sleep 417 */ 418 struct mutex lock; 419 420 /** 421 * @mem_access.vram_userfault.list: Keep list of userfaulted 422 * vram bo, which require to release their mmap mappings 423 * at runtime suspend path 424 */ 425 struct list_head list; 426 } vram_userfault; 427 } mem_access; 428 429 /** 430 * @pat: Encapsulate PAT related stuff 431 */ 432 struct { 433 /** @pat.ops: Internal operations to abstract platforms */ 434 const struct xe_pat_ops *ops; 435 /** @pat.table: PAT table to program in the HW */ 436 const struct xe_pat_table_entry *table; 437 /** @pat.n_entries: Number of PAT entries */ 438 int n_entries; 439 u32 idx[__XE_CACHE_LEVEL_COUNT]; 440 } pat; 441 442 /** @d3cold: Encapsulate d3cold related stuff */ 443 struct { 444 /** @d3cold.capable: Indicates if root port is d3cold capable */ 445 bool capable; 446 447 /** @d3cold.allowed: Indicates if d3cold is a valid device state */ 448 bool allowed; 449 450 /** 451 * @d3cold.vram_threshold: 452 * 453 * This represents the permissible threshold(in megabytes) 454 * for vram save/restore. d3cold will be disallowed, 455 * when vram_usages is above or equals the threshold value 456 * to avoid the vram save/restore latency. 457 * Default threshold value is 300mb. 458 */ 459 u32 vram_threshold; 460 /** @d3cold.lock: protect vram_threshold */ 461 struct mutex lock; 462 } d3cold; 463 464 /** 465 * @pm_callback_task: Track the active task that is running in either 466 * the runtime_suspend or runtime_resume callbacks. 467 */ 468 struct task_struct *pm_callback_task; 469 470 /** @hwmon: hwmon subsystem integration */ 471 struct xe_hwmon *hwmon; 472 473 /** @heci_gsc: graphics security controller */ 474 struct xe_heci_gsc heci_gsc; 475 476 /** @oa: oa observation subsystem */ 477 struct xe_oa oa; 478 479 /** @needs_flr_on_fini: requests function-reset on fini */ 480 bool needs_flr_on_fini; 481 482 /** @wedged: Struct to control Wedged States and mode */ 483 struct { 484 /** @wedged.flag: Xe device faced a critical error and is now blocked. */ 485 atomic_t flag; 486 /** @wedged.mode: Mode controlled by kernel parameter and debugfs */ 487 int mode; 488 } wedged; 489 490 #ifdef TEST_VM_OPS_ERROR 491 /** 492 * @vm_inject_error_position: inject errors at different places in VM 493 * bind IOCTL based on this value 494 */ 495 u8 vm_inject_error_position; 496 #endif 497 498 /* private: */ 499 500 #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) 501 /* 502 * Any fields below this point are the ones used by display. 503 * They are temporarily added here so xe_device can be desguised as 504 * drm_i915_private during build. After cleanup these should go away, 505 * migrating to the right sub-structs 506 */ 507 struct intel_display display; 508 enum intel_pch pch_type; 509 u16 pch_id; 510 511 struct dram_info { 512 bool wm_lv_0_adjust_needed; 513 u8 num_channels; 514 bool symmetric_memory; 515 enum intel_dram_type { 516 INTEL_DRAM_UNKNOWN, 517 INTEL_DRAM_DDR3, 518 INTEL_DRAM_DDR4, 519 INTEL_DRAM_LPDDR3, 520 INTEL_DRAM_LPDDR4, 521 INTEL_DRAM_DDR5, 522 INTEL_DRAM_LPDDR5, 523 INTEL_DRAM_GDDR, 524 } type; 525 u8 num_qgv_points; 526 u8 num_psf_gv_points; 527 } dram_info; 528 529 /* 530 * edram size in MB. 531 * Cannot be determined by PCIID. You must always read a register. 532 */ 533 u32 edram_size_mb; 534 535 /* To shut up runtime pm macros.. */ 536 struct xe_runtime_pm {} runtime_pm; 537 538 /* only to allow build, not used functionally */ 539 u32 irq_mask; 540 541 struct intel_uncore { 542 spinlock_t lock; 543 } uncore; 544 545 /* only to allow build, not used functionally */ 546 struct { 547 unsigned int hpll_freq; 548 unsigned int czclk_freq; 549 unsigned int fsb_freq, mem_freq, is_ddr3; 550 }; 551 552 void *pxp; 553 #endif 554 }; 555 556 /** 557 * struct xe_file - file handle for XE driver 558 */ 559 struct xe_file { 560 /** @xe: xe DEVICE **/ 561 struct xe_device *xe; 562 563 /** @drm: base DRM file */ 564 struct drm_file *drm; 565 566 /** @vm: VM state for file */ 567 struct { 568 /** @vm.xe: xarray to store VMs */ 569 struct xarray xa; 570 /** @vm.lock: protects file VM state */ 571 struct mutex lock; 572 } vm; 573 574 /** @exec_queue: Submission exec queue state for file */ 575 struct { 576 /** @exec_queue.xe: xarray to store engines */ 577 struct xarray xa; 578 /** @exec_queue.lock: protects file engine state */ 579 struct mutex lock; 580 } exec_queue; 581 582 /** @run_ticks: hw engine class run time in ticks for this drm client */ 583 u64 run_ticks[XE_ENGINE_CLASS_MAX]; 584 585 /** @client: drm client */ 586 struct xe_drm_client *client; 587 588 /** 589 * @process_name: process name for file handle, used to safely output 590 * during error situations where xe file can outlive process 591 */ 592 char *process_name; 593 594 /** 595 * @pid: pid for file handle, used to safely output uring error 596 * situations where xe file can outlive process 597 */ 598 pid_t pid; 599 600 /** @refcount: ref count of this xe file */ 601 struct kref refcount; 602 }; 603 604 #endif 605