1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Azoteq IQS7222A/B/C/D Capacitive Touch Controller
4 *
5 * Copyright (C) 2022 Jeff LaBundy <jeff@labundy.com>
6 */
7
8 #include <linux/bits.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/i2c.h>
14 #include <linux/input.h>
15 #include <linux/input/touchscreen.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/ktime.h>
19 #include <linux/mod_devicetable.h>
20 #include <linux/module.h>
21 #include <linux/property.h>
22 #include <linux/slab.h>
23 #include <linux/unaligned.h>
24
25 #define IQS7222_PROD_NUM 0x00
26 #define IQS7222_PROD_NUM_A 840
27 #define IQS7222_PROD_NUM_B 698
28 #define IQS7222_PROD_NUM_C 863
29 #define IQS7222_PROD_NUM_D 1046
30
31 #define IQS7222_SYS_STATUS 0x10
32 #define IQS7222_SYS_STATUS_RESET BIT(3)
33 #define IQS7222_SYS_STATUS_ATI_ERROR BIT(1)
34 #define IQS7222_SYS_STATUS_ATI_ACTIVE BIT(0)
35
36 #define IQS7222_CHAN_SETUP_0_REF_MODE_MASK GENMASK(15, 14)
37 #define IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW BIT(15)
38 #define IQS7222_CHAN_SETUP_0_REF_MODE_REF BIT(14)
39 #define IQS7222_CHAN_SETUP_0_CHAN_EN BIT(8)
40
41 #define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK GENMASK(2, 0)
42 #define IQS7222_SLDR_SETUP_2_RES_MASK GENMASK(15, 8)
43 #define IQS7222_SLDR_SETUP_2_RES_SHIFT 8
44 #define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK GENMASK(7, 0)
45
46 #define IQS7222_GPIO_SETUP_0_GPIO_EN BIT(0)
47
48 #define IQS7222_SYS_SETUP 0xD0
49 #define IQS7222_SYS_SETUP_INTF_MODE_MASK GENMASK(7, 6)
50 #define IQS7222_SYS_SETUP_INTF_MODE_TOUCH BIT(7)
51 #define IQS7222_SYS_SETUP_INTF_MODE_EVENT BIT(6)
52 #define IQS7222_SYS_SETUP_PWR_MODE_MASK GENMASK(5, 4)
53 #define IQS7222_SYS_SETUP_PWR_MODE_AUTO IQS7222_SYS_SETUP_PWR_MODE_MASK
54 #define IQS7222_SYS_SETUP_REDO_ATI BIT(2)
55 #define IQS7222_SYS_SETUP_ACK_RESET BIT(0)
56
57 #define IQS7222_EVENT_MASK_ATI BIT(12)
58 #define IQS7222_EVENT_MASK_SLDR BIT(10)
59 #define IQS7222_EVENT_MASK_TPAD IQS7222_EVENT_MASK_SLDR
60 #define IQS7222_EVENT_MASK_TOUCH BIT(1)
61 #define IQS7222_EVENT_MASK_PROX BIT(0)
62
63 #define IQS7222_COMMS_HOLD BIT(0)
64 #define IQS7222_COMMS_ERROR 0xEEEE
65 #define IQS7222_COMMS_RETRY_MS 50
66 #define IQS7222_COMMS_TIMEOUT_MS 100
67 #define IQS7222_RESET_TIMEOUT_MS 250
68 #define IQS7222_ATI_TIMEOUT_MS 2000
69
70 #define IQS7222_MAX_COLS_STAT 8
71 #define IQS7222_MAX_COLS_CYCLE 3
72 #define IQS7222_MAX_COLS_GLBL 3
73 #define IQS7222_MAX_COLS_BTN 3
74 #define IQS7222_MAX_COLS_CHAN 6
75 #define IQS7222_MAX_COLS_FILT 2
76 #define IQS7222_MAX_COLS_SLDR 11
77 #define IQS7222_MAX_COLS_TPAD 24
78 #define IQS7222_MAX_COLS_GPIO 3
79 #define IQS7222_MAX_COLS_SYS 13
80
81 #define IQS7222_MAX_CHAN 20
82 #define IQS7222_MAX_SLDR 2
83
84 #define IQS7222_NUM_RETRIES 5
85 #define IQS7222_REG_OFFSET 0x100
86
87 enum iqs7222_reg_key_id {
88 IQS7222_REG_KEY_NONE,
89 IQS7222_REG_KEY_PROX,
90 IQS7222_REG_KEY_TOUCH,
91 IQS7222_REG_KEY_DEBOUNCE,
92 IQS7222_REG_KEY_TAP,
93 IQS7222_REG_KEY_TAP_LEGACY,
94 IQS7222_REG_KEY_AXIAL,
95 IQS7222_REG_KEY_AXIAL_LEGACY,
96 IQS7222_REG_KEY_WHEEL,
97 IQS7222_REG_KEY_NO_WHEEL,
98 IQS7222_REG_KEY_RESERVED
99 };
100
101 enum iqs7222_reg_grp_id {
102 IQS7222_REG_GRP_STAT,
103 IQS7222_REG_GRP_CYCLE,
104 IQS7222_REG_GRP_GLBL,
105 IQS7222_REG_GRP_BTN,
106 IQS7222_REG_GRP_CHAN,
107 IQS7222_REG_GRP_FILT,
108 IQS7222_REG_GRP_SLDR,
109 IQS7222_REG_GRP_TPAD,
110 IQS7222_REG_GRP_GPIO,
111 IQS7222_REG_GRP_SYS,
112 IQS7222_NUM_REG_GRPS
113 };
114
115 static const char * const iqs7222_reg_grp_names[IQS7222_NUM_REG_GRPS] = {
116 [IQS7222_REG_GRP_CYCLE] = "cycle-%d",
117 [IQS7222_REG_GRP_CHAN] = "channel-%d",
118 [IQS7222_REG_GRP_SLDR] = "slider-%d",
119 [IQS7222_REG_GRP_TPAD] = "trackpad",
120 [IQS7222_REG_GRP_GPIO] = "gpio-%d",
121 };
122
123 static const unsigned int iqs7222_max_cols[IQS7222_NUM_REG_GRPS] = {
124 [IQS7222_REG_GRP_STAT] = IQS7222_MAX_COLS_STAT,
125 [IQS7222_REG_GRP_CYCLE] = IQS7222_MAX_COLS_CYCLE,
126 [IQS7222_REG_GRP_GLBL] = IQS7222_MAX_COLS_GLBL,
127 [IQS7222_REG_GRP_BTN] = IQS7222_MAX_COLS_BTN,
128 [IQS7222_REG_GRP_CHAN] = IQS7222_MAX_COLS_CHAN,
129 [IQS7222_REG_GRP_FILT] = IQS7222_MAX_COLS_FILT,
130 [IQS7222_REG_GRP_SLDR] = IQS7222_MAX_COLS_SLDR,
131 [IQS7222_REG_GRP_TPAD] = IQS7222_MAX_COLS_TPAD,
132 [IQS7222_REG_GRP_GPIO] = IQS7222_MAX_COLS_GPIO,
133 [IQS7222_REG_GRP_SYS] = IQS7222_MAX_COLS_SYS,
134 };
135
136 static const unsigned int iqs7222_gpio_links[] = { 2, 5, 6, };
137
138 struct iqs7222_event_desc {
139 const char *name;
140 u16 link;
141 u16 mask;
142 u16 val;
143 u16 strict;
144 u16 enable;
145 enum iqs7222_reg_key_id reg_key;
146 };
147
148 static const struct iqs7222_event_desc iqs7222_kp_events[] = {
149 {
150 .name = "event-prox",
151 .enable = IQS7222_EVENT_MASK_PROX,
152 .reg_key = IQS7222_REG_KEY_PROX,
153 },
154 {
155 .name = "event-touch",
156 .enable = IQS7222_EVENT_MASK_TOUCH,
157 .reg_key = IQS7222_REG_KEY_TOUCH,
158 },
159 };
160
161 static const struct iqs7222_event_desc iqs7222_sl_events[] = {
162 { .name = "event-press", },
163 {
164 .name = "event-tap",
165 .mask = BIT(0),
166 .val = BIT(0),
167 .enable = BIT(0),
168 .reg_key = IQS7222_REG_KEY_TAP,
169 },
170 {
171 .name = "event-swipe-pos",
172 .mask = BIT(5) | BIT(1),
173 .val = BIT(1),
174 .enable = BIT(1),
175 .reg_key = IQS7222_REG_KEY_AXIAL,
176 },
177 {
178 .name = "event-swipe-neg",
179 .mask = BIT(5) | BIT(1),
180 .val = BIT(5) | BIT(1),
181 .enable = BIT(1),
182 .reg_key = IQS7222_REG_KEY_AXIAL,
183 },
184 {
185 .name = "event-flick-pos",
186 .mask = BIT(5) | BIT(2),
187 .val = BIT(2),
188 .enable = BIT(2),
189 .reg_key = IQS7222_REG_KEY_AXIAL,
190 },
191 {
192 .name = "event-flick-neg",
193 .mask = BIT(5) | BIT(2),
194 .val = BIT(5) | BIT(2),
195 .enable = BIT(2),
196 .reg_key = IQS7222_REG_KEY_AXIAL,
197 },
198 };
199
200 static const struct iqs7222_event_desc iqs7222_tp_events[] = {
201 {
202 .name = "event-press",
203 .link = BIT(7),
204 },
205 {
206 .name = "event-tap",
207 .link = BIT(0),
208 .mask = BIT(0),
209 .val = BIT(0),
210 .enable = BIT(0),
211 .reg_key = IQS7222_REG_KEY_TAP,
212 },
213 {
214 .name = "event-swipe-x-pos",
215 .link = BIT(2),
216 .mask = BIT(2) | BIT(1),
217 .val = BIT(2),
218 .strict = BIT(4),
219 .enable = BIT(1),
220 .reg_key = IQS7222_REG_KEY_AXIAL,
221 },
222 {
223 .name = "event-swipe-y-pos",
224 .link = BIT(3),
225 .mask = BIT(3) | BIT(1),
226 .val = BIT(3),
227 .strict = BIT(3),
228 .enable = BIT(1),
229 .reg_key = IQS7222_REG_KEY_AXIAL,
230 },
231 {
232 .name = "event-swipe-x-neg",
233 .link = BIT(4),
234 .mask = BIT(4) | BIT(1),
235 .val = BIT(4),
236 .strict = BIT(4),
237 .enable = BIT(1),
238 .reg_key = IQS7222_REG_KEY_AXIAL,
239 },
240 {
241 .name = "event-swipe-y-neg",
242 .link = BIT(5),
243 .mask = BIT(5) | BIT(1),
244 .val = BIT(5),
245 .strict = BIT(3),
246 .enable = BIT(1),
247 .reg_key = IQS7222_REG_KEY_AXIAL,
248 },
249 {
250 .name = "event-flick-x-pos",
251 .link = BIT(2),
252 .mask = BIT(2) | BIT(1),
253 .val = BIT(2) | BIT(1),
254 .strict = BIT(4),
255 .enable = BIT(2),
256 .reg_key = IQS7222_REG_KEY_AXIAL,
257 },
258 {
259 .name = "event-flick-y-pos",
260 .link = BIT(3),
261 .mask = BIT(3) | BIT(1),
262 .val = BIT(3) | BIT(1),
263 .strict = BIT(3),
264 .enable = BIT(2),
265 .reg_key = IQS7222_REG_KEY_AXIAL,
266 },
267 {
268 .name = "event-flick-x-neg",
269 .link = BIT(4),
270 .mask = BIT(4) | BIT(1),
271 .val = BIT(4) | BIT(1),
272 .strict = BIT(4),
273 .enable = BIT(2),
274 .reg_key = IQS7222_REG_KEY_AXIAL,
275 },
276 {
277 .name = "event-flick-y-neg",
278 .link = BIT(5),
279 .mask = BIT(5) | BIT(1),
280 .val = BIT(5) | BIT(1),
281 .strict = BIT(3),
282 .enable = BIT(2),
283 .reg_key = IQS7222_REG_KEY_AXIAL,
284 },
285 };
286
287 struct iqs7222_reg_grp_desc {
288 u16 base;
289 u16 val_len;
290 int num_row;
291 int num_col;
292 };
293
294 struct iqs7222_dev_desc {
295 u16 prod_num;
296 u16 fw_major;
297 u16 fw_minor;
298 u16 sldr_res;
299 u16 touch_link;
300 u16 wheel_enable;
301 int allow_offset;
302 int event_offset;
303 int comms_offset;
304 int ext_chan;
305 bool legacy_gesture;
306 struct iqs7222_reg_grp_desc reg_grps[IQS7222_NUM_REG_GRPS];
307 };
308
309 static const struct iqs7222_dev_desc iqs7222_devs[] = {
310 {
311 .prod_num = IQS7222_PROD_NUM_A,
312 .fw_major = 1,
313 .fw_minor = 13,
314 .sldr_res = U8_MAX * 16,
315 .touch_link = 1768,
316 .allow_offset = 9,
317 .event_offset = 10,
318 .comms_offset = 12,
319 .ext_chan = 10,
320 .reg_grps = {
321 [IQS7222_REG_GRP_STAT] = {
322 .base = IQS7222_SYS_STATUS,
323 .num_row = 1,
324 .num_col = 8,
325 },
326 [IQS7222_REG_GRP_CYCLE] = {
327 .base = 0x8000,
328 .num_row = 7,
329 .num_col = 3,
330 },
331 [IQS7222_REG_GRP_GLBL] = {
332 .base = 0x8700,
333 .num_row = 1,
334 .num_col = 3,
335 },
336 [IQS7222_REG_GRP_BTN] = {
337 .base = 0x9000,
338 .num_row = 12,
339 .num_col = 3,
340 },
341 [IQS7222_REG_GRP_CHAN] = {
342 .base = 0xA000,
343 .num_row = 12,
344 .num_col = 6,
345 },
346 [IQS7222_REG_GRP_FILT] = {
347 .base = 0xAC00,
348 .val_len = 3,
349 .num_row = 1,
350 .num_col = 2,
351 },
352 [IQS7222_REG_GRP_SLDR] = {
353 .base = 0xB000,
354 .num_row = 2,
355 .num_col = 11,
356 },
357 [IQS7222_REG_GRP_GPIO] = {
358 .base = 0xC000,
359 .num_row = 1,
360 .num_col = 3,
361 },
362 [IQS7222_REG_GRP_SYS] = {
363 .base = IQS7222_SYS_SETUP,
364 .num_row = 1,
365 .num_col = 13,
366 },
367 },
368 },
369 {
370 .prod_num = IQS7222_PROD_NUM_A,
371 .fw_major = 1,
372 .fw_minor = 12,
373 .sldr_res = U8_MAX * 16,
374 .touch_link = 1768,
375 .allow_offset = 9,
376 .event_offset = 10,
377 .comms_offset = 12,
378 .ext_chan = 10,
379 .legacy_gesture = true,
380 .reg_grps = {
381 [IQS7222_REG_GRP_STAT] = {
382 .base = IQS7222_SYS_STATUS,
383 .num_row = 1,
384 .num_col = 8,
385 },
386 [IQS7222_REG_GRP_CYCLE] = {
387 .base = 0x8000,
388 .num_row = 7,
389 .num_col = 3,
390 },
391 [IQS7222_REG_GRP_GLBL] = {
392 .base = 0x8700,
393 .num_row = 1,
394 .num_col = 3,
395 },
396 [IQS7222_REG_GRP_BTN] = {
397 .base = 0x9000,
398 .num_row = 12,
399 .num_col = 3,
400 },
401 [IQS7222_REG_GRP_CHAN] = {
402 .base = 0xA000,
403 .num_row = 12,
404 .num_col = 6,
405 },
406 [IQS7222_REG_GRP_FILT] = {
407 .base = 0xAC00,
408 .val_len = 3,
409 .num_row = 1,
410 .num_col = 2,
411 },
412 [IQS7222_REG_GRP_SLDR] = {
413 .base = 0xB000,
414 .num_row = 2,
415 .num_col = 11,
416 },
417 [IQS7222_REG_GRP_GPIO] = {
418 .base = 0xC000,
419 .num_row = 1,
420 .num_col = 3,
421 },
422 [IQS7222_REG_GRP_SYS] = {
423 .base = IQS7222_SYS_SETUP,
424 .num_row = 1,
425 .num_col = 13,
426 },
427 },
428 },
429 {
430 .prod_num = IQS7222_PROD_NUM_B,
431 .fw_major = 1,
432 .fw_minor = 43,
433 .event_offset = 10,
434 .comms_offset = 11,
435 .reg_grps = {
436 [IQS7222_REG_GRP_STAT] = {
437 .base = IQS7222_SYS_STATUS,
438 .num_row = 1,
439 .num_col = 6,
440 },
441 [IQS7222_REG_GRP_CYCLE] = {
442 .base = 0x8000,
443 .num_row = 10,
444 .num_col = 2,
445 },
446 [IQS7222_REG_GRP_GLBL] = {
447 .base = 0x8A00,
448 .num_row = 1,
449 .num_col = 3,
450 },
451 [IQS7222_REG_GRP_BTN] = {
452 .base = 0x9000,
453 .num_row = 20,
454 .num_col = 2,
455 },
456 [IQS7222_REG_GRP_CHAN] = {
457 .base = 0xB000,
458 .num_row = 20,
459 .num_col = 4,
460 },
461 [IQS7222_REG_GRP_FILT] = {
462 .base = 0xC400,
463 .val_len = 3,
464 .num_row = 1,
465 .num_col = 2,
466 },
467 [IQS7222_REG_GRP_SYS] = {
468 .base = IQS7222_SYS_SETUP,
469 .num_row = 1,
470 .num_col = 13,
471 },
472 },
473 },
474 {
475 .prod_num = IQS7222_PROD_NUM_B,
476 .fw_major = 1,
477 .fw_minor = 27,
478 .reg_grps = {
479 [IQS7222_REG_GRP_STAT] = {
480 .base = IQS7222_SYS_STATUS,
481 .num_row = 1,
482 .num_col = 6,
483 },
484 [IQS7222_REG_GRP_CYCLE] = {
485 .base = 0x8000,
486 .num_row = 10,
487 .num_col = 2,
488 },
489 [IQS7222_REG_GRP_GLBL] = {
490 .base = 0x8A00,
491 .num_row = 1,
492 .num_col = 3,
493 },
494 [IQS7222_REG_GRP_BTN] = {
495 .base = 0x9000,
496 .num_row = 20,
497 .num_col = 2,
498 },
499 [IQS7222_REG_GRP_CHAN] = {
500 .base = 0xB000,
501 .num_row = 20,
502 .num_col = 4,
503 },
504 [IQS7222_REG_GRP_FILT] = {
505 .base = 0xC400,
506 .val_len = 3,
507 .num_row = 1,
508 .num_col = 2,
509 },
510 [IQS7222_REG_GRP_SYS] = {
511 .base = IQS7222_SYS_SETUP,
512 .num_row = 1,
513 .num_col = 10,
514 },
515 },
516 },
517 {
518 .prod_num = IQS7222_PROD_NUM_C,
519 .fw_major = 2,
520 .fw_minor = 6,
521 .sldr_res = U16_MAX,
522 .touch_link = 1686,
523 .wheel_enable = BIT(3),
524 .event_offset = 9,
525 .comms_offset = 10,
526 .reg_grps = {
527 [IQS7222_REG_GRP_STAT] = {
528 .base = IQS7222_SYS_STATUS,
529 .num_row = 1,
530 .num_col = 6,
531 },
532 [IQS7222_REG_GRP_CYCLE] = {
533 .base = 0x8000,
534 .num_row = 5,
535 .num_col = 3,
536 },
537 [IQS7222_REG_GRP_GLBL] = {
538 .base = 0x8500,
539 .num_row = 1,
540 .num_col = 3,
541 },
542 [IQS7222_REG_GRP_BTN] = {
543 .base = 0x9000,
544 .num_row = 10,
545 .num_col = 3,
546 },
547 [IQS7222_REG_GRP_CHAN] = {
548 .base = 0xA000,
549 .num_row = 10,
550 .num_col = 6,
551 },
552 [IQS7222_REG_GRP_FILT] = {
553 .base = 0xAA00,
554 .val_len = 3,
555 .num_row = 1,
556 .num_col = 2,
557 },
558 [IQS7222_REG_GRP_SLDR] = {
559 .base = 0xB000,
560 .num_row = 2,
561 .num_col = 10,
562 },
563 [IQS7222_REG_GRP_GPIO] = {
564 .base = 0xC000,
565 .num_row = 3,
566 .num_col = 3,
567 },
568 [IQS7222_REG_GRP_SYS] = {
569 .base = IQS7222_SYS_SETUP,
570 .num_row = 1,
571 .num_col = 12,
572 },
573 },
574 },
575 {
576 .prod_num = IQS7222_PROD_NUM_C,
577 .fw_major = 1,
578 .fw_minor = 13,
579 .sldr_res = U16_MAX,
580 .touch_link = 1674,
581 .wheel_enable = BIT(3),
582 .event_offset = 9,
583 .comms_offset = 10,
584 .reg_grps = {
585 [IQS7222_REG_GRP_STAT] = {
586 .base = IQS7222_SYS_STATUS,
587 .num_row = 1,
588 .num_col = 6,
589 },
590 [IQS7222_REG_GRP_CYCLE] = {
591 .base = 0x8000,
592 .num_row = 5,
593 .num_col = 3,
594 },
595 [IQS7222_REG_GRP_GLBL] = {
596 .base = 0x8500,
597 .num_row = 1,
598 .num_col = 3,
599 },
600 [IQS7222_REG_GRP_BTN] = {
601 .base = 0x9000,
602 .num_row = 10,
603 .num_col = 3,
604 },
605 [IQS7222_REG_GRP_CHAN] = {
606 .base = 0xA000,
607 .num_row = 10,
608 .num_col = 6,
609 },
610 [IQS7222_REG_GRP_FILT] = {
611 .base = 0xAA00,
612 .val_len = 3,
613 .num_row = 1,
614 .num_col = 2,
615 },
616 [IQS7222_REG_GRP_SLDR] = {
617 .base = 0xB000,
618 .num_row = 2,
619 .num_col = 10,
620 },
621 [IQS7222_REG_GRP_GPIO] = {
622 .base = 0xC000,
623 .num_row = 1,
624 .num_col = 3,
625 },
626 [IQS7222_REG_GRP_SYS] = {
627 .base = IQS7222_SYS_SETUP,
628 .num_row = 1,
629 .num_col = 11,
630 },
631 },
632 },
633 {
634 .prod_num = IQS7222_PROD_NUM_D,
635 .fw_major = 1,
636 .fw_minor = 2,
637 .touch_link = 1770,
638 .allow_offset = 9,
639 .event_offset = 10,
640 .comms_offset = 11,
641 .reg_grps = {
642 [IQS7222_REG_GRP_STAT] = {
643 .base = IQS7222_SYS_STATUS,
644 .num_row = 1,
645 .num_col = 7,
646 },
647 [IQS7222_REG_GRP_CYCLE] = {
648 .base = 0x8000,
649 .num_row = 7,
650 .num_col = 2,
651 },
652 [IQS7222_REG_GRP_GLBL] = {
653 .base = 0x8700,
654 .num_row = 1,
655 .num_col = 3,
656 },
657 [IQS7222_REG_GRP_BTN] = {
658 .base = 0x9000,
659 .num_row = 14,
660 .num_col = 3,
661 },
662 [IQS7222_REG_GRP_CHAN] = {
663 .base = 0xA000,
664 .num_row = 14,
665 .num_col = 4,
666 },
667 [IQS7222_REG_GRP_FILT] = {
668 .base = 0xAE00,
669 .val_len = 3,
670 .num_row = 1,
671 .num_col = 2,
672 },
673 [IQS7222_REG_GRP_TPAD] = {
674 .base = 0xB000,
675 .num_row = 1,
676 .num_col = 24,
677 },
678 [IQS7222_REG_GRP_GPIO] = {
679 .base = 0xC000,
680 .num_row = 3,
681 .num_col = 3,
682 },
683 [IQS7222_REG_GRP_SYS] = {
684 .base = IQS7222_SYS_SETUP,
685 .num_row = 1,
686 .num_col = 12,
687 },
688 },
689 },
690 {
691 .prod_num = IQS7222_PROD_NUM_D,
692 .fw_major = 1,
693 .fw_minor = 1,
694 .touch_link = 1774,
695 .allow_offset = 9,
696 .event_offset = 10,
697 .comms_offset = 11,
698 .reg_grps = {
699 [IQS7222_REG_GRP_STAT] = {
700 .base = IQS7222_SYS_STATUS,
701 .num_row = 1,
702 .num_col = 7,
703 },
704 [IQS7222_REG_GRP_CYCLE] = {
705 .base = 0x8000,
706 .num_row = 7,
707 .num_col = 2,
708 },
709 [IQS7222_REG_GRP_GLBL] = {
710 .base = 0x8700,
711 .num_row = 1,
712 .num_col = 3,
713 },
714 [IQS7222_REG_GRP_BTN] = {
715 .base = 0x9000,
716 .num_row = 14,
717 .num_col = 3,
718 },
719 [IQS7222_REG_GRP_CHAN] = {
720 .base = 0xA000,
721 .num_row = 14,
722 .num_col = 4,
723 },
724 [IQS7222_REG_GRP_FILT] = {
725 .base = 0xAE00,
726 .val_len = 3,
727 .num_row = 1,
728 .num_col = 2,
729 },
730 [IQS7222_REG_GRP_TPAD] = {
731 .base = 0xB000,
732 .num_row = 1,
733 .num_col = 24,
734 },
735 [IQS7222_REG_GRP_GPIO] = {
736 .base = 0xC000,
737 .num_row = 3,
738 .num_col = 3,
739 },
740 [IQS7222_REG_GRP_SYS] = {
741 .base = IQS7222_SYS_SETUP,
742 .num_row = 1,
743 .num_col = 12,
744 },
745 },
746 },
747 {
748 .prod_num = IQS7222_PROD_NUM_D,
749 .fw_major = 0,
750 .fw_minor = 37,
751 .touch_link = 1770,
752 .allow_offset = 9,
753 .event_offset = 10,
754 .comms_offset = 11,
755 .reg_grps = {
756 [IQS7222_REG_GRP_STAT] = {
757 .base = IQS7222_SYS_STATUS,
758 .num_row = 1,
759 .num_col = 7,
760 },
761 [IQS7222_REG_GRP_CYCLE] = {
762 .base = 0x8000,
763 .num_row = 7,
764 .num_col = 2,
765 },
766 [IQS7222_REG_GRP_GLBL] = {
767 .base = 0x8700,
768 .num_row = 1,
769 .num_col = 3,
770 },
771 [IQS7222_REG_GRP_BTN] = {
772 .base = 0x9000,
773 .num_row = 14,
774 .num_col = 3,
775 },
776 [IQS7222_REG_GRP_CHAN] = {
777 .base = 0xA000,
778 .num_row = 14,
779 .num_col = 4,
780 },
781 [IQS7222_REG_GRP_FILT] = {
782 .base = 0xAE00,
783 .val_len = 3,
784 .num_row = 1,
785 .num_col = 2,
786 },
787 [IQS7222_REG_GRP_TPAD] = {
788 .base = 0xB000,
789 .num_row = 1,
790 .num_col = 24,
791 },
792 [IQS7222_REG_GRP_GPIO] = {
793 .base = 0xC000,
794 .num_row = 3,
795 .num_col = 3,
796 },
797 [IQS7222_REG_GRP_SYS] = {
798 .base = IQS7222_SYS_SETUP,
799 .num_row = 1,
800 .num_col = 12,
801 },
802 },
803 },
804 };
805
806 struct iqs7222_prop_desc {
807 const char *name;
808 enum iqs7222_reg_grp_id reg_grp;
809 enum iqs7222_reg_key_id reg_key;
810 int reg_offset;
811 int reg_shift;
812 int reg_width;
813 int val_pitch;
814 int val_min;
815 int val_max;
816 bool invert;
817 const char *label;
818 };
819
820 static const struct iqs7222_prop_desc iqs7222_props[] = {
821 {
822 .name = "azoteq,conv-period",
823 .reg_grp = IQS7222_REG_GRP_CYCLE,
824 .reg_offset = 0,
825 .reg_shift = 8,
826 .reg_width = 8,
827 .label = "conversion period",
828 },
829 {
830 .name = "azoteq,conv-frac",
831 .reg_grp = IQS7222_REG_GRP_CYCLE,
832 .reg_offset = 0,
833 .reg_shift = 0,
834 .reg_width = 8,
835 .label = "conversion frequency fractional divider",
836 },
837 {
838 .name = "azoteq,rx-float-inactive",
839 .reg_grp = IQS7222_REG_GRP_CYCLE,
840 .reg_offset = 1,
841 .reg_shift = 6,
842 .reg_width = 1,
843 .invert = true,
844 },
845 {
846 .name = "azoteq,dead-time-enable",
847 .reg_grp = IQS7222_REG_GRP_CYCLE,
848 .reg_offset = 1,
849 .reg_shift = 5,
850 .reg_width = 1,
851 },
852 {
853 .name = "azoteq,tx-freq-fosc",
854 .reg_grp = IQS7222_REG_GRP_CYCLE,
855 .reg_offset = 1,
856 .reg_shift = 4,
857 .reg_width = 1,
858 },
859 {
860 .name = "azoteq,vbias-enable",
861 .reg_grp = IQS7222_REG_GRP_CYCLE,
862 .reg_offset = 1,
863 .reg_shift = 3,
864 .reg_width = 1,
865 },
866 {
867 .name = "azoteq,sense-mode",
868 .reg_grp = IQS7222_REG_GRP_CYCLE,
869 .reg_offset = 1,
870 .reg_shift = 0,
871 .reg_width = 3,
872 .val_max = 3,
873 .label = "sensing mode",
874 },
875 {
876 .name = "azoteq,iref-enable",
877 .reg_grp = IQS7222_REG_GRP_CYCLE,
878 .reg_offset = 2,
879 .reg_shift = 10,
880 .reg_width = 1,
881 },
882 {
883 .name = "azoteq,iref-level",
884 .reg_grp = IQS7222_REG_GRP_CYCLE,
885 .reg_offset = 2,
886 .reg_shift = 4,
887 .reg_width = 4,
888 .label = "current reference level",
889 },
890 {
891 .name = "azoteq,iref-trim",
892 .reg_grp = IQS7222_REG_GRP_CYCLE,
893 .reg_offset = 2,
894 .reg_shift = 0,
895 .reg_width = 4,
896 .label = "current reference trim",
897 },
898 {
899 .name = "azoteq,max-counts",
900 .reg_grp = IQS7222_REG_GRP_GLBL,
901 .reg_offset = 0,
902 .reg_shift = 13,
903 .reg_width = 2,
904 .label = "maximum counts",
905 },
906 {
907 .name = "azoteq,auto-mode",
908 .reg_grp = IQS7222_REG_GRP_GLBL,
909 .reg_offset = 0,
910 .reg_shift = 2,
911 .reg_width = 2,
912 .label = "number of conversions",
913 },
914 {
915 .name = "azoteq,ati-frac-div-fine",
916 .reg_grp = IQS7222_REG_GRP_GLBL,
917 .reg_offset = 1,
918 .reg_shift = 9,
919 .reg_width = 5,
920 .label = "ATI fine fractional divider",
921 },
922 {
923 .name = "azoteq,ati-frac-div-coarse",
924 .reg_grp = IQS7222_REG_GRP_GLBL,
925 .reg_offset = 1,
926 .reg_shift = 0,
927 .reg_width = 5,
928 .label = "ATI coarse fractional divider",
929 },
930 {
931 .name = "azoteq,ati-comp-select",
932 .reg_grp = IQS7222_REG_GRP_GLBL,
933 .reg_offset = 2,
934 .reg_shift = 0,
935 .reg_width = 10,
936 .label = "ATI compensation selection",
937 },
938 {
939 .name = "azoteq,ati-band",
940 .reg_grp = IQS7222_REG_GRP_CHAN,
941 .reg_offset = 0,
942 .reg_shift = 12,
943 .reg_width = 2,
944 .label = "ATI band",
945 },
946 {
947 .name = "azoteq,global-halt",
948 .reg_grp = IQS7222_REG_GRP_CHAN,
949 .reg_offset = 0,
950 .reg_shift = 11,
951 .reg_width = 1,
952 },
953 {
954 .name = "azoteq,invert-enable",
955 .reg_grp = IQS7222_REG_GRP_CHAN,
956 .reg_offset = 0,
957 .reg_shift = 10,
958 .reg_width = 1,
959 },
960 {
961 .name = "azoteq,dual-direction",
962 .reg_grp = IQS7222_REG_GRP_CHAN,
963 .reg_offset = 0,
964 .reg_shift = 9,
965 .reg_width = 1,
966 },
967 {
968 .name = "azoteq,samp-cap-double",
969 .reg_grp = IQS7222_REG_GRP_CHAN,
970 .reg_offset = 0,
971 .reg_shift = 3,
972 .reg_width = 1,
973 },
974 {
975 .name = "azoteq,vref-half",
976 .reg_grp = IQS7222_REG_GRP_CHAN,
977 .reg_offset = 0,
978 .reg_shift = 2,
979 .reg_width = 1,
980 },
981 {
982 .name = "azoteq,proj-bias",
983 .reg_grp = IQS7222_REG_GRP_CHAN,
984 .reg_offset = 0,
985 .reg_shift = 0,
986 .reg_width = 2,
987 .label = "projected bias current",
988 },
989 {
990 .name = "azoteq,ati-target",
991 .reg_grp = IQS7222_REG_GRP_CHAN,
992 .reg_offset = 1,
993 .reg_shift = 8,
994 .reg_width = 8,
995 .val_pitch = 8,
996 .label = "ATI target",
997 },
998 {
999 .name = "azoteq,ati-base",
1000 .reg_grp = IQS7222_REG_GRP_CHAN,
1001 .reg_offset = 1,
1002 .reg_shift = 3,
1003 .reg_width = 5,
1004 .val_pitch = 16,
1005 .label = "ATI base",
1006 },
1007 {
1008 .name = "azoteq,ati-mode",
1009 .reg_grp = IQS7222_REG_GRP_CHAN,
1010 .reg_offset = 1,
1011 .reg_shift = 0,
1012 .reg_width = 3,
1013 .val_max = 5,
1014 .label = "ATI mode",
1015 },
1016 {
1017 .name = "azoteq,ati-frac-div-fine",
1018 .reg_grp = IQS7222_REG_GRP_CHAN,
1019 .reg_offset = 2,
1020 .reg_shift = 9,
1021 .reg_width = 5,
1022 .label = "ATI fine fractional divider",
1023 },
1024 {
1025 .name = "azoteq,ati-frac-mult-coarse",
1026 .reg_grp = IQS7222_REG_GRP_CHAN,
1027 .reg_offset = 2,
1028 .reg_shift = 5,
1029 .reg_width = 4,
1030 .label = "ATI coarse fractional multiplier",
1031 },
1032 {
1033 .name = "azoteq,ati-frac-div-coarse",
1034 .reg_grp = IQS7222_REG_GRP_CHAN,
1035 .reg_offset = 2,
1036 .reg_shift = 0,
1037 .reg_width = 5,
1038 .label = "ATI coarse fractional divider",
1039 },
1040 {
1041 .name = "azoteq,ati-comp-div",
1042 .reg_grp = IQS7222_REG_GRP_CHAN,
1043 .reg_offset = 3,
1044 .reg_shift = 11,
1045 .reg_width = 5,
1046 .label = "ATI compensation divider",
1047 },
1048 {
1049 .name = "azoteq,ati-comp-select",
1050 .reg_grp = IQS7222_REG_GRP_CHAN,
1051 .reg_offset = 3,
1052 .reg_shift = 0,
1053 .reg_width = 10,
1054 .label = "ATI compensation selection",
1055 },
1056 {
1057 .name = "azoteq,debounce-exit",
1058 .reg_grp = IQS7222_REG_GRP_BTN,
1059 .reg_key = IQS7222_REG_KEY_DEBOUNCE,
1060 .reg_offset = 0,
1061 .reg_shift = 12,
1062 .reg_width = 4,
1063 .label = "debounce exit factor",
1064 },
1065 {
1066 .name = "azoteq,debounce-enter",
1067 .reg_grp = IQS7222_REG_GRP_BTN,
1068 .reg_key = IQS7222_REG_KEY_DEBOUNCE,
1069 .reg_offset = 0,
1070 .reg_shift = 8,
1071 .reg_width = 4,
1072 .label = "debounce entrance factor",
1073 },
1074 {
1075 .name = "azoteq,thresh",
1076 .reg_grp = IQS7222_REG_GRP_BTN,
1077 .reg_key = IQS7222_REG_KEY_PROX,
1078 .reg_offset = 0,
1079 .reg_shift = 0,
1080 .reg_width = 8,
1081 .val_max = 127,
1082 .label = "threshold",
1083 },
1084 {
1085 .name = "azoteq,thresh",
1086 .reg_grp = IQS7222_REG_GRP_BTN,
1087 .reg_key = IQS7222_REG_KEY_TOUCH,
1088 .reg_offset = 1,
1089 .reg_shift = 0,
1090 .reg_width = 8,
1091 .label = "threshold",
1092 },
1093 {
1094 .name = "azoteq,hyst",
1095 .reg_grp = IQS7222_REG_GRP_BTN,
1096 .reg_key = IQS7222_REG_KEY_TOUCH,
1097 .reg_offset = 1,
1098 .reg_shift = 8,
1099 .reg_width = 8,
1100 .label = "hysteresis",
1101 },
1102 {
1103 .name = "azoteq,lta-beta-lp",
1104 .reg_grp = IQS7222_REG_GRP_FILT,
1105 .reg_offset = 0,
1106 .reg_shift = 12,
1107 .reg_width = 4,
1108 .label = "low-power mode long-term average beta",
1109 },
1110 {
1111 .name = "azoteq,lta-beta-np",
1112 .reg_grp = IQS7222_REG_GRP_FILT,
1113 .reg_offset = 0,
1114 .reg_shift = 8,
1115 .reg_width = 4,
1116 .label = "normal-power mode long-term average beta",
1117 },
1118 {
1119 .name = "azoteq,counts-beta-lp",
1120 .reg_grp = IQS7222_REG_GRP_FILT,
1121 .reg_offset = 0,
1122 .reg_shift = 4,
1123 .reg_width = 4,
1124 .label = "low-power mode counts beta",
1125 },
1126 {
1127 .name = "azoteq,counts-beta-np",
1128 .reg_grp = IQS7222_REG_GRP_FILT,
1129 .reg_offset = 0,
1130 .reg_shift = 0,
1131 .reg_width = 4,
1132 .label = "normal-power mode counts beta",
1133 },
1134 {
1135 .name = "azoteq,lta-fast-beta-lp",
1136 .reg_grp = IQS7222_REG_GRP_FILT,
1137 .reg_offset = 1,
1138 .reg_shift = 4,
1139 .reg_width = 4,
1140 .label = "low-power mode long-term average fast beta",
1141 },
1142 {
1143 .name = "azoteq,lta-fast-beta-np",
1144 .reg_grp = IQS7222_REG_GRP_FILT,
1145 .reg_offset = 1,
1146 .reg_shift = 0,
1147 .reg_width = 4,
1148 .label = "normal-power mode long-term average fast beta",
1149 },
1150 {
1151 .name = "azoteq,lower-cal",
1152 .reg_grp = IQS7222_REG_GRP_SLDR,
1153 .reg_offset = 0,
1154 .reg_shift = 8,
1155 .reg_width = 8,
1156 .label = "lower calibration",
1157 },
1158 {
1159 .name = "azoteq,static-beta",
1160 .reg_grp = IQS7222_REG_GRP_SLDR,
1161 .reg_key = IQS7222_REG_KEY_NO_WHEEL,
1162 .reg_offset = 0,
1163 .reg_shift = 6,
1164 .reg_width = 1,
1165 },
1166 {
1167 .name = "azoteq,bottom-beta",
1168 .reg_grp = IQS7222_REG_GRP_SLDR,
1169 .reg_key = IQS7222_REG_KEY_NO_WHEEL,
1170 .reg_offset = 0,
1171 .reg_shift = 3,
1172 .reg_width = 3,
1173 .label = "bottom beta",
1174 },
1175 {
1176 .name = "azoteq,static-beta",
1177 .reg_grp = IQS7222_REG_GRP_SLDR,
1178 .reg_key = IQS7222_REG_KEY_WHEEL,
1179 .reg_offset = 0,
1180 .reg_shift = 7,
1181 .reg_width = 1,
1182 },
1183 {
1184 .name = "azoteq,bottom-beta",
1185 .reg_grp = IQS7222_REG_GRP_SLDR,
1186 .reg_key = IQS7222_REG_KEY_WHEEL,
1187 .reg_offset = 0,
1188 .reg_shift = 4,
1189 .reg_width = 3,
1190 .label = "bottom beta",
1191 },
1192 {
1193 .name = "azoteq,bottom-speed",
1194 .reg_grp = IQS7222_REG_GRP_SLDR,
1195 .reg_offset = 1,
1196 .reg_shift = 8,
1197 .reg_width = 8,
1198 .label = "bottom speed",
1199 },
1200 {
1201 .name = "azoteq,upper-cal",
1202 .reg_grp = IQS7222_REG_GRP_SLDR,
1203 .reg_offset = 1,
1204 .reg_shift = 0,
1205 .reg_width = 8,
1206 .label = "upper calibration",
1207 },
1208 {
1209 .name = "azoteq,gesture-max-ms",
1210 .reg_grp = IQS7222_REG_GRP_SLDR,
1211 .reg_key = IQS7222_REG_KEY_TAP,
1212 .reg_offset = 9,
1213 .reg_shift = 8,
1214 .reg_width = 8,
1215 .val_pitch = 16,
1216 .label = "maximum gesture time",
1217 },
1218 {
1219 .name = "azoteq,gesture-max-ms",
1220 .reg_grp = IQS7222_REG_GRP_SLDR,
1221 .reg_key = IQS7222_REG_KEY_TAP_LEGACY,
1222 .reg_offset = 9,
1223 .reg_shift = 8,
1224 .reg_width = 8,
1225 .val_pitch = 4,
1226 .label = "maximum gesture time",
1227 },
1228 {
1229 .name = "azoteq,gesture-min-ms",
1230 .reg_grp = IQS7222_REG_GRP_SLDR,
1231 .reg_key = IQS7222_REG_KEY_TAP,
1232 .reg_offset = 9,
1233 .reg_shift = 3,
1234 .reg_width = 5,
1235 .val_pitch = 16,
1236 .label = "minimum gesture time",
1237 },
1238 {
1239 .name = "azoteq,gesture-min-ms",
1240 .reg_grp = IQS7222_REG_GRP_SLDR,
1241 .reg_key = IQS7222_REG_KEY_TAP_LEGACY,
1242 .reg_offset = 9,
1243 .reg_shift = 3,
1244 .reg_width = 5,
1245 .val_pitch = 4,
1246 .label = "minimum gesture time",
1247 },
1248 {
1249 .name = "azoteq,gesture-dist",
1250 .reg_grp = IQS7222_REG_GRP_SLDR,
1251 .reg_key = IQS7222_REG_KEY_AXIAL,
1252 .reg_offset = 10,
1253 .reg_shift = 8,
1254 .reg_width = 8,
1255 .val_pitch = 16,
1256 .label = "gesture distance",
1257 },
1258 {
1259 .name = "azoteq,gesture-dist",
1260 .reg_grp = IQS7222_REG_GRP_SLDR,
1261 .reg_key = IQS7222_REG_KEY_AXIAL_LEGACY,
1262 .reg_offset = 10,
1263 .reg_shift = 8,
1264 .reg_width = 8,
1265 .val_pitch = 16,
1266 .label = "gesture distance",
1267 },
1268 {
1269 .name = "azoteq,gesture-max-ms",
1270 .reg_grp = IQS7222_REG_GRP_SLDR,
1271 .reg_key = IQS7222_REG_KEY_AXIAL,
1272 .reg_offset = 10,
1273 .reg_shift = 0,
1274 .reg_width = 8,
1275 .val_pitch = 16,
1276 .label = "maximum gesture time",
1277 },
1278 {
1279 .name = "azoteq,gesture-max-ms",
1280 .reg_grp = IQS7222_REG_GRP_SLDR,
1281 .reg_key = IQS7222_REG_KEY_AXIAL_LEGACY,
1282 .reg_offset = 10,
1283 .reg_shift = 0,
1284 .reg_width = 8,
1285 .val_pitch = 4,
1286 .label = "maximum gesture time",
1287 },
1288 {
1289 .name = "azoteq,num-rows",
1290 .reg_grp = IQS7222_REG_GRP_TPAD,
1291 .reg_offset = 0,
1292 .reg_shift = 4,
1293 .reg_width = 4,
1294 .val_min = 1,
1295 .val_max = 12,
1296 .label = "number of rows",
1297 },
1298 {
1299 .name = "azoteq,num-cols",
1300 .reg_grp = IQS7222_REG_GRP_TPAD,
1301 .reg_offset = 0,
1302 .reg_shift = 0,
1303 .reg_width = 4,
1304 .val_min = 1,
1305 .val_max = 12,
1306 .label = "number of columns",
1307 },
1308 {
1309 .name = "azoteq,lower-cal-y",
1310 .reg_grp = IQS7222_REG_GRP_TPAD,
1311 .reg_offset = 1,
1312 .reg_shift = 8,
1313 .reg_width = 8,
1314 .label = "lower vertical calibration",
1315 },
1316 {
1317 .name = "azoteq,lower-cal-x",
1318 .reg_grp = IQS7222_REG_GRP_TPAD,
1319 .reg_offset = 1,
1320 .reg_shift = 0,
1321 .reg_width = 8,
1322 .label = "lower horizontal calibration",
1323 },
1324 {
1325 .name = "azoteq,upper-cal-y",
1326 .reg_grp = IQS7222_REG_GRP_TPAD,
1327 .reg_offset = 2,
1328 .reg_shift = 8,
1329 .reg_width = 8,
1330 .label = "upper vertical calibration",
1331 },
1332 {
1333 .name = "azoteq,upper-cal-x",
1334 .reg_grp = IQS7222_REG_GRP_TPAD,
1335 .reg_offset = 2,
1336 .reg_shift = 0,
1337 .reg_width = 8,
1338 .label = "upper horizontal calibration",
1339 },
1340 {
1341 .name = "azoteq,top-speed",
1342 .reg_grp = IQS7222_REG_GRP_TPAD,
1343 .reg_offset = 3,
1344 .reg_shift = 8,
1345 .reg_width = 8,
1346 .val_pitch = 4,
1347 .label = "top speed",
1348 },
1349 {
1350 .name = "azoteq,bottom-speed",
1351 .reg_grp = IQS7222_REG_GRP_TPAD,
1352 .reg_offset = 3,
1353 .reg_shift = 0,
1354 .reg_width = 8,
1355 .label = "bottom speed",
1356 },
1357 {
1358 .name = "azoteq,gesture-min-ms",
1359 .reg_grp = IQS7222_REG_GRP_TPAD,
1360 .reg_key = IQS7222_REG_KEY_TAP,
1361 .reg_offset = 20,
1362 .reg_shift = 8,
1363 .reg_width = 8,
1364 .val_pitch = 16,
1365 .label = "minimum gesture time",
1366 },
1367 {
1368 .name = "azoteq,gesture-max-ms",
1369 .reg_grp = IQS7222_REG_GRP_TPAD,
1370 .reg_key = IQS7222_REG_KEY_AXIAL,
1371 .reg_offset = 21,
1372 .reg_shift = 8,
1373 .reg_width = 8,
1374 .val_pitch = 16,
1375 .label = "maximum gesture time",
1376 },
1377 {
1378 .name = "azoteq,gesture-max-ms",
1379 .reg_grp = IQS7222_REG_GRP_TPAD,
1380 .reg_key = IQS7222_REG_KEY_TAP,
1381 .reg_offset = 21,
1382 .reg_shift = 0,
1383 .reg_width = 8,
1384 .val_pitch = 16,
1385 .label = "maximum gesture time",
1386 },
1387 {
1388 .name = "azoteq,gesture-dist",
1389 .reg_grp = IQS7222_REG_GRP_TPAD,
1390 .reg_key = IQS7222_REG_KEY_TAP,
1391 .reg_offset = 22,
1392 .reg_shift = 0,
1393 .reg_width = 16,
1394 .label = "gesture distance",
1395 },
1396 {
1397 .name = "azoteq,gesture-dist",
1398 .reg_grp = IQS7222_REG_GRP_TPAD,
1399 .reg_key = IQS7222_REG_KEY_AXIAL,
1400 .reg_offset = 23,
1401 .reg_shift = 0,
1402 .reg_width = 16,
1403 .label = "gesture distance",
1404 },
1405 {
1406 .name = "drive-open-drain",
1407 .reg_grp = IQS7222_REG_GRP_GPIO,
1408 .reg_offset = 0,
1409 .reg_shift = 1,
1410 .reg_width = 1,
1411 },
1412 {
1413 .name = "azoteq,timeout-ati-ms",
1414 .reg_grp = IQS7222_REG_GRP_SYS,
1415 .reg_offset = 1,
1416 .reg_shift = 0,
1417 .reg_width = 16,
1418 .val_pitch = 500,
1419 .label = "ATI error timeout",
1420 },
1421 {
1422 .name = "azoteq,rate-ati-ms",
1423 .reg_grp = IQS7222_REG_GRP_SYS,
1424 .reg_offset = 2,
1425 .reg_shift = 0,
1426 .reg_width = 16,
1427 .label = "ATI report rate",
1428 },
1429 {
1430 .name = "azoteq,timeout-np-ms",
1431 .reg_grp = IQS7222_REG_GRP_SYS,
1432 .reg_offset = 3,
1433 .reg_shift = 0,
1434 .reg_width = 16,
1435 .label = "normal-power mode timeout",
1436 },
1437 {
1438 .name = "azoteq,rate-np-ms",
1439 .reg_grp = IQS7222_REG_GRP_SYS,
1440 .reg_offset = 4,
1441 .reg_shift = 0,
1442 .reg_width = 16,
1443 .val_max = 3000,
1444 .label = "normal-power mode report rate",
1445 },
1446 {
1447 .name = "azoteq,timeout-lp-ms",
1448 .reg_grp = IQS7222_REG_GRP_SYS,
1449 .reg_offset = 5,
1450 .reg_shift = 0,
1451 .reg_width = 16,
1452 .label = "low-power mode timeout",
1453 },
1454 {
1455 .name = "azoteq,rate-lp-ms",
1456 .reg_grp = IQS7222_REG_GRP_SYS,
1457 .reg_offset = 6,
1458 .reg_shift = 0,
1459 .reg_width = 16,
1460 .val_max = 3000,
1461 .label = "low-power mode report rate",
1462 },
1463 {
1464 .name = "azoteq,timeout-ulp-ms",
1465 .reg_grp = IQS7222_REG_GRP_SYS,
1466 .reg_offset = 7,
1467 .reg_shift = 0,
1468 .reg_width = 16,
1469 .label = "ultra-low-power mode timeout",
1470 },
1471 {
1472 .name = "azoteq,rate-ulp-ms",
1473 .reg_grp = IQS7222_REG_GRP_SYS,
1474 .reg_offset = 8,
1475 .reg_shift = 0,
1476 .reg_width = 16,
1477 .val_max = 3000,
1478 .label = "ultra-low-power mode report rate",
1479 },
1480 };
1481
1482 struct iqs7222_private {
1483 const struct iqs7222_dev_desc *dev_desc;
1484 struct gpio_desc *reset_gpio;
1485 struct gpio_desc *irq_gpio;
1486 struct i2c_client *client;
1487 struct input_dev *keypad;
1488 struct touchscreen_properties prop;
1489 unsigned int kp_type[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)];
1490 unsigned int kp_code[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)];
1491 unsigned int sl_code[IQS7222_MAX_SLDR][ARRAY_SIZE(iqs7222_sl_events)];
1492 unsigned int sl_axis[IQS7222_MAX_SLDR];
1493 unsigned int tp_code[ARRAY_SIZE(iqs7222_tp_events)];
1494 u16 cycle_setup[IQS7222_MAX_CHAN / 2][IQS7222_MAX_COLS_CYCLE];
1495 u16 glbl_setup[IQS7222_MAX_COLS_GLBL];
1496 u16 btn_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_BTN];
1497 u16 chan_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_CHAN];
1498 u16 filt_setup[IQS7222_MAX_COLS_FILT];
1499 u16 sldr_setup[IQS7222_MAX_SLDR][IQS7222_MAX_COLS_SLDR];
1500 u16 tpad_setup[IQS7222_MAX_COLS_TPAD];
1501 u16 gpio_setup[ARRAY_SIZE(iqs7222_gpio_links)][IQS7222_MAX_COLS_GPIO];
1502 u16 sys_setup[IQS7222_MAX_COLS_SYS];
1503 };
1504
iqs7222_setup(struct iqs7222_private * iqs7222,enum iqs7222_reg_grp_id reg_grp,int row)1505 static u16 *iqs7222_setup(struct iqs7222_private *iqs7222,
1506 enum iqs7222_reg_grp_id reg_grp, int row)
1507 {
1508 switch (reg_grp) {
1509 case IQS7222_REG_GRP_CYCLE:
1510 return iqs7222->cycle_setup[row];
1511
1512 case IQS7222_REG_GRP_GLBL:
1513 return iqs7222->glbl_setup;
1514
1515 case IQS7222_REG_GRP_BTN:
1516 return iqs7222->btn_setup[row];
1517
1518 case IQS7222_REG_GRP_CHAN:
1519 return iqs7222->chan_setup[row];
1520
1521 case IQS7222_REG_GRP_FILT:
1522 return iqs7222->filt_setup;
1523
1524 case IQS7222_REG_GRP_SLDR:
1525 return iqs7222->sldr_setup[row];
1526
1527 case IQS7222_REG_GRP_TPAD:
1528 return iqs7222->tpad_setup;
1529
1530 case IQS7222_REG_GRP_GPIO:
1531 return iqs7222->gpio_setup[row];
1532
1533 case IQS7222_REG_GRP_SYS:
1534 return iqs7222->sys_setup;
1535
1536 default:
1537 return NULL;
1538 }
1539 }
1540
iqs7222_irq_poll(struct iqs7222_private * iqs7222,u16 timeout_ms)1541 static int iqs7222_irq_poll(struct iqs7222_private *iqs7222, u16 timeout_ms)
1542 {
1543 ktime_t irq_timeout = ktime_add_ms(ktime_get(), timeout_ms);
1544 int ret;
1545
1546 do {
1547 usleep_range(1000, 1100);
1548
1549 ret = gpiod_get_value_cansleep(iqs7222->irq_gpio);
1550 if (ret < 0)
1551 return ret;
1552 else if (ret > 0)
1553 return 0;
1554 } while (ktime_compare(ktime_get(), irq_timeout) < 0);
1555
1556 return -EBUSY;
1557 }
1558
iqs7222_hard_reset(struct iqs7222_private * iqs7222)1559 static int iqs7222_hard_reset(struct iqs7222_private *iqs7222)
1560 {
1561 struct i2c_client *client = iqs7222->client;
1562 int error;
1563
1564 if (!iqs7222->reset_gpio)
1565 return 0;
1566
1567 gpiod_set_value_cansleep(iqs7222->reset_gpio, 1);
1568 usleep_range(1000, 1100);
1569
1570 gpiod_set_value_cansleep(iqs7222->reset_gpio, 0);
1571
1572 error = iqs7222_irq_poll(iqs7222, IQS7222_RESET_TIMEOUT_MS);
1573 if (error)
1574 dev_err(&client->dev, "Failed to reset device: %d\n", error);
1575
1576 return error;
1577 }
1578
iqs7222_force_comms(struct iqs7222_private * iqs7222)1579 static int iqs7222_force_comms(struct iqs7222_private *iqs7222)
1580 {
1581 u8 msg_buf[] = { 0xFF, };
1582 int ret;
1583
1584 /*
1585 * The device cannot communicate until it asserts its interrupt (RDY)
1586 * pin. Attempts to do so while RDY is deasserted return an ACK; how-
1587 * ever all write data is ignored, and all read data returns 0xEE.
1588 *
1589 * Unsolicited communication must be preceded by a special force com-
1590 * munication command, after which the device eventually asserts its
1591 * RDY pin and agrees to communicate.
1592 *
1593 * Regardless of whether communication is forced or the result of an
1594 * interrupt, the device automatically deasserts its RDY pin once it
1595 * detects an I2C stop condition, or a timeout expires.
1596 */
1597 ret = gpiod_get_value_cansleep(iqs7222->irq_gpio);
1598 if (ret < 0)
1599 return ret;
1600 else if (ret > 0)
1601 return 0;
1602
1603 ret = i2c_master_send(iqs7222->client, msg_buf, sizeof(msg_buf));
1604 if (ret < (int)sizeof(msg_buf)) {
1605 if (ret >= 0)
1606 ret = -EIO;
1607
1608 /*
1609 * The datasheet states that the host must wait to retry any
1610 * failed attempt to communicate over I2C.
1611 */
1612 msleep(IQS7222_COMMS_RETRY_MS);
1613 return ret;
1614 }
1615
1616 return iqs7222_irq_poll(iqs7222, IQS7222_COMMS_TIMEOUT_MS);
1617 }
1618
iqs7222_read_burst(struct iqs7222_private * iqs7222,u16 reg,void * val,u16 val_len)1619 static int iqs7222_read_burst(struct iqs7222_private *iqs7222,
1620 u16 reg, void *val, u16 val_len)
1621 {
1622 u8 reg_buf[sizeof(__be16)];
1623 int ret, i;
1624 struct i2c_client *client = iqs7222->client;
1625 struct i2c_msg msg[] = {
1626 {
1627 .addr = client->addr,
1628 .flags = 0,
1629 .len = reg > U8_MAX ? sizeof(reg) : sizeof(u8),
1630 .buf = reg_buf,
1631 },
1632 {
1633 .addr = client->addr,
1634 .flags = I2C_M_RD,
1635 .len = val_len,
1636 .buf = (u8 *)val,
1637 },
1638 };
1639
1640 if (reg > U8_MAX)
1641 put_unaligned_be16(reg, reg_buf);
1642 else
1643 *reg_buf = (u8)reg;
1644
1645 /*
1646 * The following loop protects against an edge case in which the RDY
1647 * pin is automatically deasserted just as the read is initiated. In
1648 * that case, the read must be retried using forced communication.
1649 */
1650 for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1651 ret = iqs7222_force_comms(iqs7222);
1652 if (ret < 0)
1653 continue;
1654
1655 ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg));
1656 if (ret < (int)ARRAY_SIZE(msg)) {
1657 if (ret >= 0)
1658 ret = -EIO;
1659
1660 msleep(IQS7222_COMMS_RETRY_MS);
1661 continue;
1662 }
1663
1664 if (get_unaligned_le16(msg[1].buf) == IQS7222_COMMS_ERROR) {
1665 ret = -ENODATA;
1666 continue;
1667 }
1668
1669 ret = 0;
1670 break;
1671 }
1672
1673 /*
1674 * The following delay ensures the device has deasserted the RDY pin
1675 * following the I2C stop condition.
1676 */
1677 usleep_range(50, 100);
1678
1679 if (ret < 0)
1680 dev_err(&client->dev,
1681 "Failed to read from address 0x%04X: %d\n", reg, ret);
1682
1683 return ret;
1684 }
1685
iqs7222_read_word(struct iqs7222_private * iqs7222,u16 reg,u16 * val)1686 static int iqs7222_read_word(struct iqs7222_private *iqs7222, u16 reg, u16 *val)
1687 {
1688 __le16 val_buf;
1689 int error;
1690
1691 error = iqs7222_read_burst(iqs7222, reg, &val_buf, sizeof(val_buf));
1692 if (error)
1693 return error;
1694
1695 *val = le16_to_cpu(val_buf);
1696
1697 return 0;
1698 }
1699
iqs7222_write_burst(struct iqs7222_private * iqs7222,u16 reg,const void * val,u16 val_len)1700 static int iqs7222_write_burst(struct iqs7222_private *iqs7222,
1701 u16 reg, const void *val, u16 val_len)
1702 {
1703 int reg_len = reg > U8_MAX ? sizeof(reg) : sizeof(u8);
1704 int msg_len = reg_len + val_len;
1705 int ret, i;
1706 struct i2c_client *client = iqs7222->client;
1707 u8 *msg_buf;
1708
1709 msg_buf = kzalloc(msg_len, GFP_KERNEL);
1710 if (!msg_buf)
1711 return -ENOMEM;
1712
1713 if (reg > U8_MAX)
1714 put_unaligned_be16(reg, msg_buf);
1715 else
1716 *msg_buf = (u8)reg;
1717
1718 memcpy(msg_buf + reg_len, val, val_len);
1719
1720 /*
1721 * The following loop protects against an edge case in which the RDY
1722 * pin is automatically asserted just before the force communication
1723 * command is sent.
1724 *
1725 * In that case, the subsequent I2C stop condition tricks the device
1726 * into preemptively deasserting the RDY pin and the command must be
1727 * sent again.
1728 */
1729 for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1730 ret = iqs7222_force_comms(iqs7222);
1731 if (ret < 0)
1732 continue;
1733
1734 ret = i2c_master_send(client, msg_buf, msg_len);
1735 if (ret < msg_len) {
1736 if (ret >= 0)
1737 ret = -EIO;
1738
1739 msleep(IQS7222_COMMS_RETRY_MS);
1740 continue;
1741 }
1742
1743 ret = 0;
1744 break;
1745 }
1746
1747 kfree(msg_buf);
1748
1749 usleep_range(50, 100);
1750
1751 if (ret < 0)
1752 dev_err(&client->dev,
1753 "Failed to write to address 0x%04X: %d\n", reg, ret);
1754
1755 return ret;
1756 }
1757
iqs7222_write_word(struct iqs7222_private * iqs7222,u16 reg,u16 val)1758 static int iqs7222_write_word(struct iqs7222_private *iqs7222, u16 reg, u16 val)
1759 {
1760 __le16 val_buf = cpu_to_le16(val);
1761
1762 return iqs7222_write_burst(iqs7222, reg, &val_buf, sizeof(val_buf));
1763 }
1764
iqs7222_ati_trigger(struct iqs7222_private * iqs7222)1765 static int iqs7222_ati_trigger(struct iqs7222_private *iqs7222)
1766 {
1767 struct i2c_client *client = iqs7222->client;
1768 ktime_t ati_timeout;
1769 u16 sys_status = 0;
1770 u16 sys_setup;
1771 int error, i;
1772
1773 /*
1774 * The reserved fields of the system setup register may have changed
1775 * as a result of other registers having been written. As such, read
1776 * the register's latest value to avoid unexpected behavior when the
1777 * register is written in the loop that follows.
1778 */
1779 error = iqs7222_read_word(iqs7222, IQS7222_SYS_SETUP, &sys_setup);
1780 if (error)
1781 return error;
1782
1783 for (i = 0; i < IQS7222_NUM_RETRIES; i++) {
1784 /*
1785 * Trigger ATI from streaming and normal-power modes so that
1786 * the RDY pin continues to be asserted during ATI.
1787 */
1788 error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1789 sys_setup |
1790 IQS7222_SYS_SETUP_REDO_ATI);
1791 if (error)
1792 return error;
1793
1794 ati_timeout = ktime_add_ms(ktime_get(), IQS7222_ATI_TIMEOUT_MS);
1795
1796 do {
1797 error = iqs7222_irq_poll(iqs7222,
1798 IQS7222_COMMS_TIMEOUT_MS);
1799 if (error)
1800 continue;
1801
1802 error = iqs7222_read_word(iqs7222, IQS7222_SYS_STATUS,
1803 &sys_status);
1804 if (error)
1805 return error;
1806
1807 if (sys_status & IQS7222_SYS_STATUS_RESET)
1808 return 0;
1809
1810 if (sys_status & IQS7222_SYS_STATUS_ATI_ERROR)
1811 break;
1812
1813 if (sys_status & IQS7222_SYS_STATUS_ATI_ACTIVE)
1814 continue;
1815
1816 /*
1817 * Use stream-in-touch mode if either slider reports
1818 * absolute position.
1819 */
1820 sys_setup |= test_bit(EV_ABS, iqs7222->keypad->evbit)
1821 ? IQS7222_SYS_SETUP_INTF_MODE_TOUCH
1822 : IQS7222_SYS_SETUP_INTF_MODE_EVENT;
1823 sys_setup |= IQS7222_SYS_SETUP_PWR_MODE_AUTO;
1824
1825 return iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1826 sys_setup);
1827 } while (ktime_compare(ktime_get(), ati_timeout) < 0);
1828
1829 dev_err(&client->dev,
1830 "ATI attempt %d of %d failed with status 0x%02X, %s\n",
1831 i + 1, IQS7222_NUM_RETRIES, (u8)sys_status,
1832 i + 1 < IQS7222_NUM_RETRIES ? "retrying" : "stopping");
1833 }
1834
1835 return -ETIMEDOUT;
1836 }
1837
iqs7222_dev_init(struct iqs7222_private * iqs7222,int dir)1838 static int iqs7222_dev_init(struct iqs7222_private *iqs7222, int dir)
1839 {
1840 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
1841 int comms_offset = dev_desc->comms_offset;
1842 int error, i, j, k;
1843
1844 /*
1845 * Acknowledge reset before writing any registers in case the device
1846 * suffers a spurious reset during initialization.
1847 */
1848 if (dir == WRITE) {
1849 error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP,
1850 iqs7222->sys_setup[0] |
1851 IQS7222_SYS_SETUP_ACK_RESET);
1852 if (error)
1853 return error;
1854 }
1855
1856 /*
1857 * Take advantage of the stop-bit disable function, if available, to
1858 * save the trouble of having to reopen a communication window after
1859 * each burst read or write.
1860 */
1861 if (comms_offset) {
1862 u16 comms_setup;
1863
1864 error = iqs7222_read_word(iqs7222,
1865 IQS7222_SYS_SETUP + comms_offset,
1866 &comms_setup);
1867 if (error)
1868 return error;
1869
1870 error = iqs7222_write_word(iqs7222,
1871 IQS7222_SYS_SETUP + comms_offset,
1872 comms_setup | IQS7222_COMMS_HOLD);
1873 if (error)
1874 return error;
1875 }
1876
1877 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) {
1878 int num_row = dev_desc->reg_grps[i].num_row;
1879 int num_col = dev_desc->reg_grps[i].num_col;
1880 u16 reg = dev_desc->reg_grps[i].base;
1881 __le16 *val_buf;
1882 u16 val_len = dev_desc->reg_grps[i].val_len ? : num_col * sizeof(*val_buf);
1883 u16 *val;
1884
1885 if (!num_col)
1886 continue;
1887
1888 val = iqs7222_setup(iqs7222, i, 0);
1889 if (!val)
1890 continue;
1891
1892 val_buf = kcalloc(num_col, sizeof(__le16), GFP_KERNEL);
1893 if (!val_buf)
1894 return -ENOMEM;
1895
1896 for (j = 0; j < num_row; j++) {
1897 switch (dir) {
1898 case READ:
1899 error = iqs7222_read_burst(iqs7222, reg,
1900 val_buf, val_len);
1901 for (k = 0; k < num_col; k++)
1902 val[k] = le16_to_cpu(val_buf[k]);
1903 break;
1904
1905 case WRITE:
1906 for (k = 0; k < num_col; k++)
1907 val_buf[k] = cpu_to_le16(val[k]);
1908 error = iqs7222_write_burst(iqs7222, reg,
1909 val_buf, val_len);
1910 break;
1911
1912 default:
1913 error = -EINVAL;
1914 }
1915
1916 if (error)
1917 break;
1918
1919 reg += IQS7222_REG_OFFSET;
1920 val += iqs7222_max_cols[i];
1921 }
1922
1923 kfree(val_buf);
1924
1925 if (error)
1926 return error;
1927 }
1928
1929 if (comms_offset) {
1930 u16 comms_setup;
1931
1932 error = iqs7222_read_word(iqs7222,
1933 IQS7222_SYS_SETUP + comms_offset,
1934 &comms_setup);
1935 if (error)
1936 return error;
1937
1938 error = iqs7222_write_word(iqs7222,
1939 IQS7222_SYS_SETUP + comms_offset,
1940 comms_setup & ~IQS7222_COMMS_HOLD);
1941 if (error)
1942 return error;
1943 }
1944
1945 if (dir == READ) {
1946 iqs7222->sys_setup[0] &= ~IQS7222_SYS_SETUP_INTF_MODE_MASK;
1947 iqs7222->sys_setup[0] &= ~IQS7222_SYS_SETUP_PWR_MODE_MASK;
1948 return 0;
1949 }
1950
1951 return iqs7222_ati_trigger(iqs7222);
1952 }
1953
iqs7222_dev_info(struct iqs7222_private * iqs7222)1954 static int iqs7222_dev_info(struct iqs7222_private *iqs7222)
1955 {
1956 struct i2c_client *client = iqs7222->client;
1957 bool prod_num_valid = false;
1958 __le16 dev_id[3];
1959 int error, i;
1960
1961 error = iqs7222_read_burst(iqs7222, IQS7222_PROD_NUM, dev_id,
1962 sizeof(dev_id));
1963 if (error)
1964 return error;
1965
1966 for (i = 0; i < ARRAY_SIZE(iqs7222_devs); i++) {
1967 if (le16_to_cpu(dev_id[0]) != iqs7222_devs[i].prod_num)
1968 continue;
1969
1970 prod_num_valid = true;
1971
1972 if (le16_to_cpu(dev_id[1]) < iqs7222_devs[i].fw_major)
1973 continue;
1974
1975 if (le16_to_cpu(dev_id[2]) < iqs7222_devs[i].fw_minor)
1976 continue;
1977
1978 iqs7222->dev_desc = &iqs7222_devs[i];
1979 return 0;
1980 }
1981
1982 if (prod_num_valid)
1983 dev_err(&client->dev, "Unsupported firmware revision: %u.%u\n",
1984 le16_to_cpu(dev_id[1]), le16_to_cpu(dev_id[2]));
1985 else
1986 dev_err(&client->dev, "Unrecognized product number: %u\n",
1987 le16_to_cpu(dev_id[0]));
1988
1989 return -EINVAL;
1990 }
1991
iqs7222_gpio_select(struct iqs7222_private * iqs7222,struct fwnode_handle * child_node,int child_enable,u16 child_link)1992 static int iqs7222_gpio_select(struct iqs7222_private *iqs7222,
1993 struct fwnode_handle *child_node,
1994 int child_enable, u16 child_link)
1995 {
1996 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
1997 struct i2c_client *client = iqs7222->client;
1998 int num_gpio = dev_desc->reg_grps[IQS7222_REG_GRP_GPIO].num_row;
1999 int error, count, i;
2000 unsigned int gpio_sel[ARRAY_SIZE(iqs7222_gpio_links)];
2001
2002 if (!num_gpio)
2003 return 0;
2004
2005 if (!fwnode_property_present(child_node, "azoteq,gpio-select"))
2006 return 0;
2007
2008 count = fwnode_property_count_u32(child_node, "azoteq,gpio-select");
2009 if (count > num_gpio) {
2010 dev_err(&client->dev, "Invalid number of %s GPIOs\n",
2011 fwnode_get_name(child_node));
2012 return -EINVAL;
2013 } else if (count < 0) {
2014 dev_err(&client->dev, "Failed to count %s GPIOs: %d\n",
2015 fwnode_get_name(child_node), count);
2016 return count;
2017 }
2018
2019 error = fwnode_property_read_u32_array(child_node,
2020 "azoteq,gpio-select",
2021 gpio_sel, count);
2022 if (error) {
2023 dev_err(&client->dev, "Failed to read %s GPIOs: %d\n",
2024 fwnode_get_name(child_node), error);
2025 return error;
2026 }
2027
2028 for (i = 0; i < count; i++) {
2029 u16 *gpio_setup;
2030
2031 if (gpio_sel[i] >= num_gpio) {
2032 dev_err(&client->dev, "Invalid %s GPIO: %u\n",
2033 fwnode_get_name(child_node), gpio_sel[i]);
2034 return -EINVAL;
2035 }
2036
2037 gpio_setup = iqs7222->gpio_setup[gpio_sel[i]];
2038
2039 if (gpio_setup[2] && child_link != gpio_setup[2]) {
2040 dev_err(&client->dev,
2041 "Conflicting GPIO %u event types\n",
2042 gpio_sel[i]);
2043 return -EINVAL;
2044 }
2045
2046 gpio_setup[0] |= IQS7222_GPIO_SETUP_0_GPIO_EN;
2047 gpio_setup[1] |= child_enable;
2048 gpio_setup[2] = child_link;
2049 }
2050
2051 return 0;
2052 }
2053
iqs7222_parse_props(struct iqs7222_private * iqs7222,struct fwnode_handle * reg_grp_node,int reg_grp_index,enum iqs7222_reg_grp_id reg_grp,enum iqs7222_reg_key_id reg_key)2054 static int iqs7222_parse_props(struct iqs7222_private *iqs7222,
2055 struct fwnode_handle *reg_grp_node,
2056 int reg_grp_index,
2057 enum iqs7222_reg_grp_id reg_grp,
2058 enum iqs7222_reg_key_id reg_key)
2059 {
2060 u16 *setup = iqs7222_setup(iqs7222, reg_grp, reg_grp_index);
2061 struct i2c_client *client = iqs7222->client;
2062 int i;
2063
2064 if (!setup)
2065 return 0;
2066
2067 for (i = 0; i < ARRAY_SIZE(iqs7222_props); i++) {
2068 const char *name = iqs7222_props[i].name;
2069 int reg_offset = iqs7222_props[i].reg_offset;
2070 int reg_shift = iqs7222_props[i].reg_shift;
2071 int reg_width = iqs7222_props[i].reg_width;
2072 int val_pitch = iqs7222_props[i].val_pitch ? : 1;
2073 int val_min = iqs7222_props[i].val_min;
2074 int val_max = iqs7222_props[i].val_max;
2075 bool invert = iqs7222_props[i].invert;
2076 const char *label = iqs7222_props[i].label ? : name;
2077 unsigned int val;
2078 int error;
2079
2080 if (iqs7222_props[i].reg_grp != reg_grp ||
2081 iqs7222_props[i].reg_key != reg_key)
2082 continue;
2083
2084 /*
2085 * Boolean register fields are one bit wide; they are forcibly
2086 * reset to provide a means to undo changes by a bootloader if
2087 * necessary.
2088 *
2089 * Scalar fields, on the other hand, are left untouched unless
2090 * their corresponding properties are present.
2091 */
2092 if (reg_width == 1) {
2093 if (invert)
2094 setup[reg_offset] |= BIT(reg_shift);
2095 else
2096 setup[reg_offset] &= ~BIT(reg_shift);
2097 }
2098
2099 if (!fwnode_property_present(reg_grp_node, name))
2100 continue;
2101
2102 if (reg_width == 1) {
2103 if (invert)
2104 setup[reg_offset] &= ~BIT(reg_shift);
2105 else
2106 setup[reg_offset] |= BIT(reg_shift);
2107
2108 continue;
2109 }
2110
2111 error = fwnode_property_read_u32(reg_grp_node, name, &val);
2112 if (error) {
2113 dev_err(&client->dev, "Failed to read %s %s: %d\n",
2114 fwnode_get_name(reg_grp_node), label, error);
2115 return error;
2116 }
2117
2118 if (!val_max)
2119 val_max = GENMASK(reg_width - 1, 0) * val_pitch;
2120
2121 if (val < val_min || val > val_max) {
2122 dev_err(&client->dev, "Invalid %s %s: %u\n",
2123 fwnode_get_name(reg_grp_node), label, val);
2124 return -EINVAL;
2125 }
2126
2127 setup[reg_offset] &= ~GENMASK(reg_shift + reg_width - 1,
2128 reg_shift);
2129 setup[reg_offset] |= (val / val_pitch << reg_shift);
2130 }
2131
2132 return 0;
2133 }
2134
iqs7222_parse_event(struct iqs7222_private * iqs7222,struct fwnode_handle * event_node,int reg_grp_index,enum iqs7222_reg_grp_id reg_grp,enum iqs7222_reg_key_id reg_key,u16 event_enable,u16 event_link,unsigned int * event_type,unsigned int * event_code)2135 static int iqs7222_parse_event(struct iqs7222_private *iqs7222,
2136 struct fwnode_handle *event_node,
2137 int reg_grp_index,
2138 enum iqs7222_reg_grp_id reg_grp,
2139 enum iqs7222_reg_key_id reg_key,
2140 u16 event_enable, u16 event_link,
2141 unsigned int *event_type,
2142 unsigned int *event_code)
2143 {
2144 struct i2c_client *client = iqs7222->client;
2145 int error;
2146
2147 error = iqs7222_parse_props(iqs7222, event_node, reg_grp_index,
2148 reg_grp, reg_key);
2149 if (error)
2150 return error;
2151
2152 error = iqs7222_gpio_select(iqs7222, event_node, event_enable,
2153 event_link);
2154 if (error)
2155 return error;
2156
2157 error = fwnode_property_read_u32(event_node, "linux,code", event_code);
2158 if (error == -EINVAL) {
2159 return 0;
2160 } else if (error) {
2161 dev_err(&client->dev, "Failed to read %s code: %d\n",
2162 fwnode_get_name(event_node), error);
2163 return error;
2164 }
2165
2166 if (!event_type) {
2167 input_set_capability(iqs7222->keypad, EV_KEY, *event_code);
2168 return 0;
2169 }
2170
2171 error = fwnode_property_read_u32(event_node, "linux,input-type",
2172 event_type);
2173 if (error == -EINVAL) {
2174 *event_type = EV_KEY;
2175 } else if (error) {
2176 dev_err(&client->dev, "Failed to read %s input type: %d\n",
2177 fwnode_get_name(event_node), error);
2178 return error;
2179 } else if (*event_type != EV_KEY && *event_type != EV_SW) {
2180 dev_err(&client->dev, "Invalid %s input type: %d\n",
2181 fwnode_get_name(event_node), *event_type);
2182 return -EINVAL;
2183 }
2184
2185 input_set_capability(iqs7222->keypad, *event_type, *event_code);
2186
2187 return 0;
2188 }
2189
iqs7222_parse_cycle(struct iqs7222_private * iqs7222,struct fwnode_handle * cycle_node,int cycle_index)2190 static int iqs7222_parse_cycle(struct iqs7222_private *iqs7222,
2191 struct fwnode_handle *cycle_node, int cycle_index)
2192 {
2193 u16 *cycle_setup = iqs7222->cycle_setup[cycle_index];
2194 struct i2c_client *client = iqs7222->client;
2195 unsigned int pins[9];
2196 int error, count, i;
2197
2198 /*
2199 * Each channel shares a cycle with one other channel; the mapping of
2200 * channels to cycles is fixed. Properties defined for a cycle impact
2201 * both channels tied to the cycle.
2202 *
2203 * Unlike channels which are restricted to a select range of CRx pins
2204 * based on channel number, any cycle can claim any of the device's 9
2205 * CTx pins (CTx0-8).
2206 */
2207 if (!fwnode_property_present(cycle_node, "azoteq,tx-enable"))
2208 return 0;
2209
2210 count = fwnode_property_count_u32(cycle_node, "azoteq,tx-enable");
2211 if (count < 0) {
2212 dev_err(&client->dev, "Failed to count %s CTx pins: %d\n",
2213 fwnode_get_name(cycle_node), count);
2214 return count;
2215 } else if (count > ARRAY_SIZE(pins)) {
2216 dev_err(&client->dev, "Invalid number of %s CTx pins\n",
2217 fwnode_get_name(cycle_node));
2218 return -EINVAL;
2219 }
2220
2221 error = fwnode_property_read_u32_array(cycle_node, "azoteq,tx-enable",
2222 pins, count);
2223 if (error) {
2224 dev_err(&client->dev, "Failed to read %s CTx pins: %d\n",
2225 fwnode_get_name(cycle_node), error);
2226 return error;
2227 }
2228
2229 cycle_setup[1] &= ~GENMASK(7 + ARRAY_SIZE(pins) - 1, 7);
2230
2231 for (i = 0; i < count; i++) {
2232 if (pins[i] > 8) {
2233 dev_err(&client->dev, "Invalid %s CTx pin: %u\n",
2234 fwnode_get_name(cycle_node), pins[i]);
2235 return -EINVAL;
2236 }
2237
2238 cycle_setup[1] |= BIT(pins[i] + 7);
2239 }
2240
2241 return 0;
2242 }
2243
iqs7222_parse_chan(struct iqs7222_private * iqs7222,struct fwnode_handle * chan_node,int chan_index)2244 static int iqs7222_parse_chan(struct iqs7222_private *iqs7222,
2245 struct fwnode_handle *chan_node, int chan_index)
2246 {
2247 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2248 struct i2c_client *client = iqs7222->client;
2249 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2250 int ext_chan = dev_desc->ext_chan ? : num_chan;
2251 int error, i;
2252 u16 *chan_setup = iqs7222->chan_setup[chan_index];
2253 u16 *sys_setup = iqs7222->sys_setup;
2254 unsigned int val;
2255
2256 if (dev_desc->allow_offset &&
2257 fwnode_property_present(chan_node, "azoteq,ulp-allow"))
2258 sys_setup[dev_desc->allow_offset] &= ~BIT(chan_index);
2259
2260 chan_setup[0] |= IQS7222_CHAN_SETUP_0_CHAN_EN;
2261
2262 /*
2263 * The reference channel function allows for differential measurements
2264 * and is only available in the case of IQS7222A or IQS7222C.
2265 */
2266 if (dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_col > 4 &&
2267 fwnode_property_present(chan_node, "azoteq,ref-select")) {
2268 u16 *ref_setup;
2269
2270 error = fwnode_property_read_u32(chan_node, "azoteq,ref-select",
2271 &val);
2272 if (error) {
2273 dev_err(&client->dev,
2274 "Failed to read %s reference channel: %d\n",
2275 fwnode_get_name(chan_node), error);
2276 return error;
2277 }
2278
2279 if (val >= ext_chan) {
2280 dev_err(&client->dev,
2281 "Invalid %s reference channel: %u\n",
2282 fwnode_get_name(chan_node), val);
2283 return -EINVAL;
2284 }
2285
2286 ref_setup = iqs7222->chan_setup[val];
2287
2288 /*
2289 * Configure the current channel as a follower of the selected
2290 * reference channel.
2291 */
2292 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW;
2293 chan_setup[4] = val * 42 + 1048;
2294
2295 error = fwnode_property_read_u32(chan_node, "azoteq,ref-weight",
2296 &val);
2297 if (!error) {
2298 if (val > U16_MAX) {
2299 dev_err(&client->dev,
2300 "Invalid %s reference weight: %u\n",
2301 fwnode_get_name(chan_node), val);
2302 return -EINVAL;
2303 }
2304
2305 chan_setup[5] = val;
2306 } else if (error != -EINVAL) {
2307 dev_err(&client->dev,
2308 "Failed to read %s reference weight: %d\n",
2309 fwnode_get_name(chan_node), error);
2310 return error;
2311 }
2312
2313 /*
2314 * Configure the selected channel as a reference channel which
2315 * serves the current channel.
2316 */
2317 ref_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF;
2318 ref_setup[5] |= BIT(chan_index);
2319
2320 ref_setup[4] = dev_desc->touch_link;
2321 if (fwnode_property_present(chan_node, "azoteq,use-prox"))
2322 ref_setup[4] -= 2;
2323 } else if (dev_desc->reg_grps[IQS7222_REG_GRP_TPAD].num_row &&
2324 fwnode_property_present(chan_node,
2325 "azoteq,counts-filt-enable")) {
2326 /*
2327 * In the case of IQS7222D, however, the reference mode field
2328 * is partially repurposed as a counts filter enable control.
2329 */
2330 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF;
2331 }
2332
2333 if (fwnode_property_present(chan_node, "azoteq,rx-enable")) {
2334 /*
2335 * Each channel can claim up to 4 CRx pins. The first half of
2336 * the channels can use CRx0-3, while the second half can use
2337 * CRx4-7.
2338 */
2339 unsigned int pins[4];
2340 int count;
2341
2342 count = fwnode_property_count_u32(chan_node,
2343 "azoteq,rx-enable");
2344 if (count < 0) {
2345 dev_err(&client->dev,
2346 "Failed to count %s CRx pins: %d\n",
2347 fwnode_get_name(chan_node), count);
2348 return count;
2349 } else if (count > ARRAY_SIZE(pins)) {
2350 dev_err(&client->dev,
2351 "Invalid number of %s CRx pins\n",
2352 fwnode_get_name(chan_node));
2353 return -EINVAL;
2354 }
2355
2356 error = fwnode_property_read_u32_array(chan_node,
2357 "azoteq,rx-enable",
2358 pins, count);
2359 if (error) {
2360 dev_err(&client->dev,
2361 "Failed to read %s CRx pins: %d\n",
2362 fwnode_get_name(chan_node), error);
2363 return error;
2364 }
2365
2366 chan_setup[0] &= ~GENMASK(4 + ARRAY_SIZE(pins) - 1, 4);
2367
2368 for (i = 0; i < count; i++) {
2369 int min_crx = chan_index < ext_chan / 2 ? 0 : 4;
2370
2371 if (pins[i] < min_crx || pins[i] > min_crx + 3) {
2372 dev_err(&client->dev,
2373 "Invalid %s CRx pin: %u\n",
2374 fwnode_get_name(chan_node), pins[i]);
2375 return -EINVAL;
2376 }
2377
2378 chan_setup[0] |= BIT(pins[i] + 4 - min_crx);
2379 }
2380 }
2381
2382 for (i = 0; i < ARRAY_SIZE(iqs7222_kp_events); i++) {
2383 const char *event_name = iqs7222_kp_events[i].name;
2384 u16 event_enable = iqs7222_kp_events[i].enable;
2385
2386 struct fwnode_handle *event_node __free(fwnode_handle) =
2387 fwnode_get_named_child_node(chan_node, event_name);
2388 if (!event_node)
2389 continue;
2390
2391 error = fwnode_property_read_u32(event_node,
2392 "azoteq,timeout-press-ms",
2393 &val);
2394 if (!error) {
2395 /*
2396 * The IQS7222B employs a global pair of press timeout
2397 * registers as opposed to channel-specific registers.
2398 */
2399 u16 *setup = dev_desc->reg_grps
2400 [IQS7222_REG_GRP_BTN].num_col > 2 ?
2401 &iqs7222->btn_setup[chan_index][2] :
2402 &sys_setup[9];
2403
2404 if (val > U8_MAX * 500) {
2405 dev_err(&client->dev,
2406 "Invalid %s press timeout: %u\n",
2407 fwnode_get_name(event_node), val);
2408 return -EINVAL;
2409 }
2410
2411 *setup &= ~(U8_MAX << i * 8);
2412 *setup |= (val / 500 << i * 8);
2413 } else if (error != -EINVAL) {
2414 dev_err(&client->dev,
2415 "Failed to read %s press timeout: %d\n",
2416 fwnode_get_name(event_node), error);
2417 return error;
2418 }
2419
2420 error = iqs7222_parse_event(iqs7222, event_node, chan_index,
2421 IQS7222_REG_GRP_BTN,
2422 iqs7222_kp_events[i].reg_key,
2423 BIT(chan_index),
2424 dev_desc->touch_link - (i ? 0 : 2),
2425 &iqs7222->kp_type[chan_index][i],
2426 &iqs7222->kp_code[chan_index][i]);
2427 if (error)
2428 return error;
2429
2430 if (!dev_desc->event_offset)
2431 continue;
2432
2433 sys_setup[dev_desc->event_offset] |= event_enable;
2434 }
2435
2436 /*
2437 * The following call handles a special pair of properties that apply
2438 * to a channel node, but reside within the button (event) group.
2439 */
2440 return iqs7222_parse_props(iqs7222, chan_node, chan_index,
2441 IQS7222_REG_GRP_BTN,
2442 IQS7222_REG_KEY_DEBOUNCE);
2443 }
2444
iqs7222_parse_sldr(struct iqs7222_private * iqs7222,struct fwnode_handle * sldr_node,int sldr_index)2445 static int iqs7222_parse_sldr(struct iqs7222_private *iqs7222,
2446 struct fwnode_handle *sldr_node, int sldr_index)
2447 {
2448 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2449 struct i2c_client *client = iqs7222->client;
2450 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2451 int ext_chan = dev_desc->ext_chan ? : num_chan;
2452 int count, error, reg_offset, i;
2453 u16 *event_mask = &iqs7222->sys_setup[dev_desc->event_offset];
2454 u16 *sldr_setup = iqs7222->sldr_setup[sldr_index];
2455 unsigned int chan_sel[4], val;
2456
2457 /*
2458 * Each slider can be spread across 3 to 4 channels. It is possible to
2459 * select only 2 channels, but doing so prevents the slider from using
2460 * the specified resolution.
2461 */
2462 count = fwnode_property_count_u32(sldr_node, "azoteq,channel-select");
2463 if (count < 0) {
2464 dev_err(&client->dev, "Failed to count %s channels: %d\n",
2465 fwnode_get_name(sldr_node), count);
2466 return count;
2467 } else if (count < 3 || count > ARRAY_SIZE(chan_sel)) {
2468 dev_err(&client->dev, "Invalid number of %s channels\n",
2469 fwnode_get_name(sldr_node));
2470 return -EINVAL;
2471 }
2472
2473 error = fwnode_property_read_u32_array(sldr_node,
2474 "azoteq,channel-select",
2475 chan_sel, count);
2476 if (error) {
2477 dev_err(&client->dev, "Failed to read %s channels: %d\n",
2478 fwnode_get_name(sldr_node), error);
2479 return error;
2480 }
2481
2482 /*
2483 * Resolution and top speed, if small enough, are packed into a single
2484 * register. Otherwise, each occupies its own register and the rest of
2485 * the slider-related register addresses are offset by one.
2486 */
2487 reg_offset = dev_desc->sldr_res < U16_MAX ? 0 : 1;
2488
2489 sldr_setup[0] |= count;
2490 sldr_setup[3 + reg_offset] &= ~GENMASK(ext_chan - 1, 0);
2491
2492 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) {
2493 sldr_setup[5 + reg_offset + i] = 0;
2494 if (i >= count)
2495 continue;
2496
2497 if (chan_sel[i] >= ext_chan) {
2498 dev_err(&client->dev, "Invalid %s channel: %u\n",
2499 fwnode_get_name(sldr_node), chan_sel[i]);
2500 return -EINVAL;
2501 }
2502
2503 /*
2504 * The following fields indicate which channels participate in
2505 * the slider, as well as each channel's relative placement.
2506 */
2507 sldr_setup[3 + reg_offset] |= BIT(chan_sel[i]);
2508 sldr_setup[5 + reg_offset + i] = chan_sel[i] * 42 + 1080;
2509 }
2510
2511 sldr_setup[4 + reg_offset] = dev_desc->touch_link;
2512 if (fwnode_property_present(sldr_node, "azoteq,use-prox"))
2513 sldr_setup[4 + reg_offset] -= 2;
2514
2515 error = fwnode_property_read_u32(sldr_node, "azoteq,slider-size", &val);
2516 if (!error) {
2517 if (val > dev_desc->sldr_res) {
2518 dev_err(&client->dev, "Invalid %s size: %u\n",
2519 fwnode_get_name(sldr_node), val);
2520 return -EINVAL;
2521 }
2522
2523 if (reg_offset) {
2524 sldr_setup[3] = val;
2525 } else {
2526 sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_RES_MASK;
2527 sldr_setup[2] |= (val / 16 <<
2528 IQS7222_SLDR_SETUP_2_RES_SHIFT);
2529 }
2530 } else if (error != -EINVAL) {
2531 dev_err(&client->dev, "Failed to read %s size: %d\n",
2532 fwnode_get_name(sldr_node), error);
2533 return error;
2534 }
2535
2536 if (!(reg_offset ? sldr_setup[3]
2537 : sldr_setup[2] & IQS7222_SLDR_SETUP_2_RES_MASK)) {
2538 dev_err(&client->dev, "Undefined %s size\n",
2539 fwnode_get_name(sldr_node));
2540 return -EINVAL;
2541 }
2542
2543 error = fwnode_property_read_u32(sldr_node, "azoteq,top-speed", &val);
2544 if (!error) {
2545 if (val > (reg_offset ? U16_MAX : U8_MAX * 4)) {
2546 dev_err(&client->dev, "Invalid %s top speed: %u\n",
2547 fwnode_get_name(sldr_node), val);
2548 return -EINVAL;
2549 }
2550
2551 if (reg_offset) {
2552 sldr_setup[2] = val;
2553 } else {
2554 sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK;
2555 sldr_setup[2] |= (val / 4);
2556 }
2557 } else if (error != -EINVAL) {
2558 dev_err(&client->dev, "Failed to read %s top speed: %d\n",
2559 fwnode_get_name(sldr_node), error);
2560 return error;
2561 }
2562
2563 error = fwnode_property_read_u32(sldr_node, "linux,axis", &val);
2564 if (!error) {
2565 u16 sldr_max = sldr_setup[3] - 1;
2566
2567 if (!reg_offset) {
2568 sldr_max = sldr_setup[2];
2569
2570 sldr_max &= IQS7222_SLDR_SETUP_2_RES_MASK;
2571 sldr_max >>= IQS7222_SLDR_SETUP_2_RES_SHIFT;
2572
2573 sldr_max = sldr_max * 16 - 1;
2574 }
2575
2576 input_set_abs_params(iqs7222->keypad, val, 0, sldr_max, 0, 0);
2577 iqs7222->sl_axis[sldr_index] = val;
2578 } else if (error != -EINVAL) {
2579 dev_err(&client->dev, "Failed to read %s axis: %d\n",
2580 fwnode_get_name(sldr_node), error);
2581 return error;
2582 }
2583
2584 if (dev_desc->wheel_enable) {
2585 sldr_setup[0] &= ~dev_desc->wheel_enable;
2586 if (iqs7222->sl_axis[sldr_index] == ABS_WHEEL)
2587 sldr_setup[0] |= dev_desc->wheel_enable;
2588 }
2589
2590 /*
2591 * The absence of a register offset makes it safe to assume the device
2592 * supports gestures, each of which is first disabled until explicitly
2593 * enabled.
2594 */
2595 if (!reg_offset)
2596 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++)
2597 sldr_setup[9] &= ~iqs7222_sl_events[i].enable;
2598
2599 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) {
2600 const char *event_name = iqs7222_sl_events[i].name;
2601 enum iqs7222_reg_key_id reg_key;
2602
2603 struct fwnode_handle *event_node __free(fwnode_handle) =
2604 fwnode_get_named_child_node(sldr_node, event_name);
2605 if (!event_node)
2606 continue;
2607
2608 /*
2609 * Depending on the device, gestures are either offered using
2610 * one of two timing resolutions, or are not supported at all.
2611 */
2612 if (reg_offset)
2613 reg_key = IQS7222_REG_KEY_RESERVED;
2614 else if (dev_desc->legacy_gesture &&
2615 iqs7222_sl_events[i].reg_key == IQS7222_REG_KEY_TAP)
2616 reg_key = IQS7222_REG_KEY_TAP_LEGACY;
2617 else if (dev_desc->legacy_gesture &&
2618 iqs7222_sl_events[i].reg_key == IQS7222_REG_KEY_AXIAL)
2619 reg_key = IQS7222_REG_KEY_AXIAL_LEGACY;
2620 else
2621 reg_key = iqs7222_sl_events[i].reg_key;
2622
2623 /*
2624 * The press/release event does not expose a direct GPIO link,
2625 * but one can be emulated by tying each of the participating
2626 * channels to the same GPIO.
2627 */
2628 error = iqs7222_parse_event(iqs7222, event_node, sldr_index,
2629 IQS7222_REG_GRP_SLDR, reg_key,
2630 i ? iqs7222_sl_events[i].enable
2631 : sldr_setup[3 + reg_offset],
2632 i ? 1568 + sldr_index * 30
2633 : sldr_setup[4 + reg_offset],
2634 NULL,
2635 &iqs7222->sl_code[sldr_index][i]);
2636 if (error)
2637 return error;
2638
2639 if (!reg_offset)
2640 sldr_setup[9] |= iqs7222_sl_events[i].enable;
2641
2642 if (!dev_desc->event_offset)
2643 continue;
2644
2645 /*
2646 * The press/release event is determined based on whether the
2647 * coordinate field reports 0xFFFF and solely relies on touch
2648 * or proximity interrupts to be unmasked.
2649 */
2650 if (i && !reg_offset)
2651 *event_mask |= (IQS7222_EVENT_MASK_SLDR << sldr_index);
2652 else if (sldr_setup[4 + reg_offset] == dev_desc->touch_link)
2653 *event_mask |= IQS7222_EVENT_MASK_TOUCH;
2654 else
2655 *event_mask |= IQS7222_EVENT_MASK_PROX;
2656 }
2657
2658 /*
2659 * The following call handles a special pair of properties that shift
2660 * to make room for a wheel enable control in the case of IQS7222C.
2661 */
2662 return iqs7222_parse_props(iqs7222, sldr_node, sldr_index,
2663 IQS7222_REG_GRP_SLDR,
2664 dev_desc->wheel_enable ?
2665 IQS7222_REG_KEY_WHEEL :
2666 IQS7222_REG_KEY_NO_WHEEL);
2667 }
2668
iqs7222_parse_tpad(struct iqs7222_private * iqs7222,struct fwnode_handle * tpad_node,int tpad_index)2669 static int iqs7222_parse_tpad(struct iqs7222_private *iqs7222,
2670 struct fwnode_handle *tpad_node, int tpad_index)
2671 {
2672 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2673 struct touchscreen_properties *prop = &iqs7222->prop;
2674 struct i2c_client *client = iqs7222->client;
2675 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2676 int count, error, i;
2677 u16 *event_mask = &iqs7222->sys_setup[dev_desc->event_offset];
2678 u16 *tpad_setup = iqs7222->tpad_setup;
2679 unsigned int chan_sel[12];
2680
2681 error = iqs7222_parse_props(iqs7222, tpad_node, tpad_index,
2682 IQS7222_REG_GRP_TPAD,
2683 IQS7222_REG_KEY_NONE);
2684 if (error)
2685 return error;
2686
2687 count = fwnode_property_count_u32(tpad_node, "azoteq,channel-select");
2688 if (count < 0) {
2689 dev_err(&client->dev, "Failed to count %s channels: %d\n",
2690 fwnode_get_name(tpad_node), count);
2691 return count;
2692 } else if (!count || count > ARRAY_SIZE(chan_sel)) {
2693 dev_err(&client->dev, "Invalid number of %s channels\n",
2694 fwnode_get_name(tpad_node));
2695 return -EINVAL;
2696 }
2697
2698 error = fwnode_property_read_u32_array(tpad_node,
2699 "azoteq,channel-select",
2700 chan_sel, count);
2701 if (error) {
2702 dev_err(&client->dev, "Failed to read %s channels: %d\n",
2703 fwnode_get_name(tpad_node), error);
2704 return error;
2705 }
2706
2707 tpad_setup[6] &= ~GENMASK(num_chan - 1, 0);
2708
2709 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) {
2710 tpad_setup[8 + i] = 0;
2711 if (i >= count || chan_sel[i] == U8_MAX)
2712 continue;
2713
2714 if (chan_sel[i] >= num_chan) {
2715 dev_err(&client->dev, "Invalid %s channel: %u\n",
2716 fwnode_get_name(tpad_node), chan_sel[i]);
2717 return -EINVAL;
2718 }
2719
2720 /*
2721 * The following fields indicate which channels participate in
2722 * the trackpad, as well as each channel's relative placement.
2723 */
2724 tpad_setup[6] |= BIT(chan_sel[i]);
2725 tpad_setup[8 + i] = chan_sel[i] * 34 + 1072;
2726 }
2727
2728 tpad_setup[7] = dev_desc->touch_link;
2729 if (fwnode_property_present(tpad_node, "azoteq,use-prox"))
2730 tpad_setup[7] -= 2;
2731
2732 for (i = 0; i < ARRAY_SIZE(iqs7222_tp_events); i++)
2733 tpad_setup[20] &= ~(iqs7222_tp_events[i].strict |
2734 iqs7222_tp_events[i].enable);
2735
2736 for (i = 0; i < ARRAY_SIZE(iqs7222_tp_events); i++) {
2737 const char *event_name = iqs7222_tp_events[i].name;
2738
2739 struct fwnode_handle *event_node __free(fwnode_handle) =
2740 fwnode_get_named_child_node(tpad_node, event_name);
2741 if (!event_node)
2742 continue;
2743
2744 if (fwnode_property_present(event_node,
2745 "azoteq,gesture-angle-tighten"))
2746 tpad_setup[20] |= iqs7222_tp_events[i].strict;
2747
2748 tpad_setup[20] |= iqs7222_tp_events[i].enable;
2749
2750 error = iqs7222_parse_event(iqs7222, event_node, tpad_index,
2751 IQS7222_REG_GRP_TPAD,
2752 iqs7222_tp_events[i].reg_key,
2753 iqs7222_tp_events[i].link, 1566,
2754 NULL,
2755 &iqs7222->tp_code[i]);
2756 if (error)
2757 return error;
2758
2759 if (!dev_desc->event_offset)
2760 continue;
2761
2762 /*
2763 * The press/release event is determined based on whether the
2764 * coordinate fields report 0xFFFF and solely relies on touch
2765 * or proximity interrupts to be unmasked.
2766 */
2767 if (i)
2768 *event_mask |= IQS7222_EVENT_MASK_TPAD;
2769 else if (tpad_setup[7] == dev_desc->touch_link)
2770 *event_mask |= IQS7222_EVENT_MASK_TOUCH;
2771 else
2772 *event_mask |= IQS7222_EVENT_MASK_PROX;
2773 }
2774
2775 if (!iqs7222->tp_code[0])
2776 return 0;
2777
2778 input_set_abs_params(iqs7222->keypad, ABS_X,
2779 0, (tpad_setup[4] ? : 1) - 1, 0, 0);
2780
2781 input_set_abs_params(iqs7222->keypad, ABS_Y,
2782 0, (tpad_setup[5] ? : 1) - 1, 0, 0);
2783
2784 touchscreen_parse_properties(iqs7222->keypad, false, prop);
2785
2786 if (prop->max_x >= U16_MAX || prop->max_y >= U16_MAX) {
2787 dev_err(&client->dev, "Invalid trackpad size: %u*%u\n",
2788 prop->max_x, prop->max_y);
2789 return -EINVAL;
2790 }
2791
2792 tpad_setup[4] = prop->max_x + 1;
2793 tpad_setup[5] = prop->max_y + 1;
2794
2795 return 0;
2796 }
2797
2798 static int (*iqs7222_parse_extra[IQS7222_NUM_REG_GRPS])
2799 (struct iqs7222_private *iqs7222,
2800 struct fwnode_handle *reg_grp_node,
2801 int reg_grp_index) = {
2802 [IQS7222_REG_GRP_CYCLE] = iqs7222_parse_cycle,
2803 [IQS7222_REG_GRP_CHAN] = iqs7222_parse_chan,
2804 [IQS7222_REG_GRP_SLDR] = iqs7222_parse_sldr,
2805 [IQS7222_REG_GRP_TPAD] = iqs7222_parse_tpad,
2806 };
2807
iqs7222_parse_reg_grp(struct iqs7222_private * iqs7222,enum iqs7222_reg_grp_id reg_grp,int reg_grp_index)2808 static int iqs7222_parse_reg_grp(struct iqs7222_private *iqs7222,
2809 enum iqs7222_reg_grp_id reg_grp,
2810 int reg_grp_index)
2811 {
2812 struct i2c_client *client = iqs7222->client;
2813 int error;
2814
2815 struct fwnode_handle *reg_grp_node __free(fwnode_handle) = NULL;
2816 if (iqs7222_reg_grp_names[reg_grp]) {
2817 char reg_grp_name[16];
2818
2819 snprintf(reg_grp_name, sizeof(reg_grp_name),
2820 iqs7222_reg_grp_names[reg_grp], reg_grp_index);
2821
2822 reg_grp_node = device_get_named_child_node(&client->dev,
2823 reg_grp_name);
2824 } else {
2825 reg_grp_node = fwnode_handle_get(dev_fwnode(&client->dev));
2826 }
2827
2828 if (!reg_grp_node)
2829 return 0;
2830
2831 error = iqs7222_parse_props(iqs7222, reg_grp_node, reg_grp_index,
2832 reg_grp, IQS7222_REG_KEY_NONE);
2833 if (error)
2834 return error;
2835
2836 if (iqs7222_parse_extra[reg_grp]) {
2837 error = iqs7222_parse_extra[reg_grp](iqs7222, reg_grp_node,
2838 reg_grp_index);
2839 if (error)
2840 return error;
2841 }
2842
2843 return 0;
2844 }
2845
iqs7222_parse_all(struct iqs7222_private * iqs7222)2846 static int iqs7222_parse_all(struct iqs7222_private *iqs7222)
2847 {
2848 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2849 const struct iqs7222_reg_grp_desc *reg_grps = dev_desc->reg_grps;
2850 u16 *sys_setup = iqs7222->sys_setup;
2851 int error, i, j;
2852
2853 if (dev_desc->allow_offset)
2854 sys_setup[dev_desc->allow_offset] = U16_MAX;
2855
2856 if (dev_desc->event_offset)
2857 sys_setup[dev_desc->event_offset] = IQS7222_EVENT_MASK_ATI;
2858
2859 for (i = 0; i < reg_grps[IQS7222_REG_GRP_GPIO].num_row; i++) {
2860 u16 *gpio_setup = iqs7222->gpio_setup[i];
2861
2862 gpio_setup[0] &= ~IQS7222_GPIO_SETUP_0_GPIO_EN;
2863 gpio_setup[1] = 0;
2864 gpio_setup[2] = 0;
2865
2866 if (reg_grps[IQS7222_REG_GRP_GPIO].num_row == 1)
2867 continue;
2868
2869 /*
2870 * The IQS7222C and IQS7222D expose multiple GPIO and must be
2871 * informed as to which GPIO this group represents.
2872 */
2873 for (j = 0; j < ARRAY_SIZE(iqs7222_gpio_links); j++)
2874 gpio_setup[0] &= ~BIT(iqs7222_gpio_links[j]);
2875
2876 gpio_setup[0] |= BIT(iqs7222_gpio_links[i]);
2877 }
2878
2879 for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) {
2880 u16 *chan_setup = iqs7222->chan_setup[i];
2881
2882 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_REF_MODE_MASK;
2883 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_CHAN_EN;
2884
2885 chan_setup[5] = 0;
2886 }
2887
2888 for (i = 0; i < reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) {
2889 u16 *sldr_setup = iqs7222->sldr_setup[i];
2890
2891 sldr_setup[0] &= ~IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK;
2892 }
2893
2894 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) {
2895 for (j = 0; j < reg_grps[i].num_row; j++) {
2896 error = iqs7222_parse_reg_grp(iqs7222, i, j);
2897 if (error)
2898 return error;
2899 }
2900 }
2901
2902 return 0;
2903 }
2904
iqs7222_report(struct iqs7222_private * iqs7222)2905 static int iqs7222_report(struct iqs7222_private *iqs7222)
2906 {
2907 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc;
2908 struct i2c_client *client = iqs7222->client;
2909 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row;
2910 int num_stat = dev_desc->reg_grps[IQS7222_REG_GRP_STAT].num_col;
2911 int error, i, j;
2912 __le16 status[IQS7222_MAX_COLS_STAT];
2913
2914 error = iqs7222_read_burst(iqs7222, IQS7222_SYS_STATUS, status,
2915 num_stat * sizeof(*status));
2916 if (error)
2917 return error;
2918
2919 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_RESET) {
2920 dev_err(&client->dev, "Unexpected device reset\n");
2921 return iqs7222_dev_init(iqs7222, WRITE);
2922 }
2923
2924 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ERROR) {
2925 dev_err(&client->dev, "Unexpected ATI error\n");
2926 return iqs7222_ati_trigger(iqs7222);
2927 }
2928
2929 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ACTIVE)
2930 return 0;
2931
2932 for (i = 0; i < num_chan; i++) {
2933 u16 *chan_setup = iqs7222->chan_setup[i];
2934
2935 if (!(chan_setup[0] & IQS7222_CHAN_SETUP_0_CHAN_EN))
2936 continue;
2937
2938 for (j = 0; j < ARRAY_SIZE(iqs7222_kp_events); j++) {
2939 /*
2940 * Proximity state begins at offset 2 and spills into
2941 * offset 3 for devices with more than 16 channels.
2942 *
2943 * Touch state begins at the first offset immediately
2944 * following proximity state.
2945 */
2946 int k = 2 + j * (num_chan > 16 ? 2 : 1);
2947 u16 state = le16_to_cpu(status[k + i / 16]);
2948
2949 if (!iqs7222->kp_type[i][j])
2950 continue;
2951
2952 input_event(iqs7222->keypad,
2953 iqs7222->kp_type[i][j],
2954 iqs7222->kp_code[i][j],
2955 !!(state & BIT(i % 16)));
2956 }
2957 }
2958
2959 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) {
2960 u16 *sldr_setup = iqs7222->sldr_setup[i];
2961 u16 sldr_pos = le16_to_cpu(status[4 + i]);
2962 u16 state = le16_to_cpu(status[6 + i]);
2963
2964 if (!(sldr_setup[0] & IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK))
2965 continue;
2966
2967 if (sldr_pos < dev_desc->sldr_res)
2968 input_report_abs(iqs7222->keypad, iqs7222->sl_axis[i],
2969 sldr_pos);
2970
2971 input_report_key(iqs7222->keypad, iqs7222->sl_code[i][0],
2972 sldr_pos < dev_desc->sldr_res);
2973
2974 /*
2975 * A maximum resolution indicates the device does not support
2976 * gestures, in which case the remaining fields are ignored.
2977 */
2978 if (dev_desc->sldr_res == U16_MAX)
2979 continue;
2980
2981 if (!(le16_to_cpu(status[1]) & IQS7222_EVENT_MASK_SLDR << i))
2982 continue;
2983
2984 /*
2985 * Skip the press/release event, as it does not have separate
2986 * status fields and is handled separately.
2987 */
2988 for (j = 1; j < ARRAY_SIZE(iqs7222_sl_events); j++) {
2989 u16 mask = iqs7222_sl_events[j].mask;
2990 u16 val = iqs7222_sl_events[j].val;
2991
2992 input_report_key(iqs7222->keypad,
2993 iqs7222->sl_code[i][j],
2994 (state & mask) == val);
2995 }
2996
2997 input_sync(iqs7222->keypad);
2998
2999 for (j = 1; j < ARRAY_SIZE(iqs7222_sl_events); j++)
3000 input_report_key(iqs7222->keypad,
3001 iqs7222->sl_code[i][j], 0);
3002 }
3003
3004 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_TPAD].num_row; i++) {
3005 u16 tpad_pos_x = le16_to_cpu(status[4]);
3006 u16 tpad_pos_y = le16_to_cpu(status[5]);
3007 u16 state = le16_to_cpu(status[6]);
3008
3009 input_report_key(iqs7222->keypad, iqs7222->tp_code[0],
3010 tpad_pos_x < U16_MAX);
3011
3012 if (tpad_pos_x < U16_MAX)
3013 touchscreen_report_pos(iqs7222->keypad, &iqs7222->prop,
3014 tpad_pos_x, tpad_pos_y, false);
3015
3016 if (!(le16_to_cpu(status[1]) & IQS7222_EVENT_MASK_TPAD))
3017 continue;
3018
3019 /*
3020 * Skip the press/release event, as it does not have separate
3021 * status fields and is handled separately.
3022 */
3023 for (j = 1; j < ARRAY_SIZE(iqs7222_tp_events); j++) {
3024 u16 mask = iqs7222_tp_events[j].mask;
3025 u16 val = iqs7222_tp_events[j].val;
3026
3027 input_report_key(iqs7222->keypad,
3028 iqs7222->tp_code[j],
3029 (state & mask) == val);
3030 }
3031
3032 input_sync(iqs7222->keypad);
3033
3034 for (j = 1; j < ARRAY_SIZE(iqs7222_tp_events); j++)
3035 input_report_key(iqs7222->keypad,
3036 iqs7222->tp_code[j], 0);
3037 }
3038
3039 input_sync(iqs7222->keypad);
3040
3041 return 0;
3042 }
3043
iqs7222_irq(int irq,void * context)3044 static irqreturn_t iqs7222_irq(int irq, void *context)
3045 {
3046 struct iqs7222_private *iqs7222 = context;
3047
3048 return iqs7222_report(iqs7222) ? IRQ_NONE : IRQ_HANDLED;
3049 }
3050
iqs7222_probe(struct i2c_client * client)3051 static int iqs7222_probe(struct i2c_client *client)
3052 {
3053 struct iqs7222_private *iqs7222;
3054 unsigned long irq_flags;
3055 int error, irq;
3056
3057 iqs7222 = devm_kzalloc(&client->dev, sizeof(*iqs7222), GFP_KERNEL);
3058 if (!iqs7222)
3059 return -ENOMEM;
3060
3061 i2c_set_clientdata(client, iqs7222);
3062 iqs7222->client = client;
3063
3064 iqs7222->keypad = devm_input_allocate_device(&client->dev);
3065 if (!iqs7222->keypad)
3066 return -ENOMEM;
3067
3068 iqs7222->keypad->name = client->name;
3069 iqs7222->keypad->id.bustype = BUS_I2C;
3070
3071 /*
3072 * The RDY pin behaves as an interrupt, but must also be polled ahead
3073 * of unsolicited I2C communication. As such, it is first opened as a
3074 * GPIO and then passed to gpiod_to_irq() to register the interrupt.
3075 */
3076 iqs7222->irq_gpio = devm_gpiod_get(&client->dev, "irq", GPIOD_IN);
3077 if (IS_ERR(iqs7222->irq_gpio)) {
3078 error = PTR_ERR(iqs7222->irq_gpio);
3079 dev_err(&client->dev, "Failed to request IRQ GPIO: %d\n",
3080 error);
3081 return error;
3082 }
3083
3084 iqs7222->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
3085 GPIOD_OUT_HIGH);
3086 if (IS_ERR(iqs7222->reset_gpio)) {
3087 error = PTR_ERR(iqs7222->reset_gpio);
3088 dev_err(&client->dev, "Failed to request reset GPIO: %d\n",
3089 error);
3090 return error;
3091 }
3092
3093 error = iqs7222_hard_reset(iqs7222);
3094 if (error)
3095 return error;
3096
3097 error = iqs7222_dev_info(iqs7222);
3098 if (error)
3099 return error;
3100
3101 error = iqs7222_dev_init(iqs7222, READ);
3102 if (error)
3103 return error;
3104
3105 error = iqs7222_parse_all(iqs7222);
3106 if (error)
3107 return error;
3108
3109 error = iqs7222_dev_init(iqs7222, WRITE);
3110 if (error)
3111 return error;
3112
3113 error = iqs7222_report(iqs7222);
3114 if (error)
3115 return error;
3116
3117 error = input_register_device(iqs7222->keypad);
3118 if (error) {
3119 dev_err(&client->dev, "Failed to register device: %d\n", error);
3120 return error;
3121 }
3122
3123 irq = gpiod_to_irq(iqs7222->irq_gpio);
3124 if (irq < 0)
3125 return irq;
3126
3127 irq_flags = gpiod_is_active_low(iqs7222->irq_gpio) ? IRQF_TRIGGER_LOW
3128 : IRQF_TRIGGER_HIGH;
3129 irq_flags |= IRQF_ONESHOT;
3130
3131 error = devm_request_threaded_irq(&client->dev, irq, NULL, iqs7222_irq,
3132 irq_flags, client->name, iqs7222);
3133 if (error)
3134 dev_err(&client->dev, "Failed to request IRQ: %d\n", error);
3135
3136 return error;
3137 }
3138
3139 static const struct of_device_id iqs7222_of_match[] = {
3140 { .compatible = "azoteq,iqs7222a" },
3141 { .compatible = "azoteq,iqs7222b" },
3142 { .compatible = "azoteq,iqs7222c" },
3143 { .compatible = "azoteq,iqs7222d" },
3144 { }
3145 };
3146 MODULE_DEVICE_TABLE(of, iqs7222_of_match);
3147
3148 static struct i2c_driver iqs7222_i2c_driver = {
3149 .driver = {
3150 .name = "iqs7222",
3151 .of_match_table = iqs7222_of_match,
3152 },
3153 .probe = iqs7222_probe,
3154 };
3155 module_i2c_driver(iqs7222_i2c_driver);
3156
3157 MODULE_AUTHOR("Jeff LaBundy <jeff@labundy.com>");
3158 MODULE_DESCRIPTION("Azoteq IQS7222A/B/C/D Capacitive Touch Controller");
3159 MODULE_LICENSE("GPL");
3160