1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dcn35_clk_mgr.h"
28
29 #include "dccg.h"
30 #include "clk_mgr_internal.h"
31
32 // For dce12_get_dp_ref_freq_khz
33 #include "dce100/dce_clk_mgr.h"
34
35 // For dcn20_update_clocks_update_dpp_dto
36 #include "dcn20/dcn20_clk_mgr.h"
37
38
39 #include "reg_helper.h"
40 #include "core_types.h"
41 #include "dcn35_smu.h"
42 #include "dm_helpers.h"
43
44 #include "dcn31/dcn31_clk_mgr.h"
45
46 #include "dc_dmub_srv.h"
47 #include "link_service.h"
48 #include "logger_types.h"
49
50 #undef DC_LOGGER
51 #define DC_LOGGER \
52 clk_mgr->base.base.ctx->logger
53
54 #define DCN_BASE__INST0_SEG1 0x000000C0
55 #define mmCLK1_CLK_PLL_REQ 0x16E37
56
57 #define mmCLK1_CLK0_DFS_CNTL 0x16E69
58 #define mmCLK1_CLK1_DFS_CNTL 0x16E6C
59 #define mmCLK1_CLK2_DFS_CNTL 0x16E6F
60 #define mmCLK1_CLK3_DFS_CNTL 0x16E72
61 #define mmCLK1_CLK4_DFS_CNTL 0x16E75
62 #define mmCLK1_CLK5_DFS_CNTL 0x16E78
63
64 #define mmCLK1_CLK0_CURRENT_CNT 0x16EFB
65 #define mmCLK1_CLK1_CURRENT_CNT 0x16EFC
66 #define mmCLK1_CLK2_CURRENT_CNT 0x16EFD
67 #define mmCLK1_CLK3_CURRENT_CNT 0x16EFE
68 #define mmCLK1_CLK4_CURRENT_CNT 0x16EFF
69 #define mmCLK1_CLK5_CURRENT_CNT 0x16F00
70
71 #define mmCLK1_CLK0_BYPASS_CNTL 0x16E8A
72 #define mmCLK1_CLK1_BYPASS_CNTL 0x16E93
73 #define mmCLK1_CLK2_BYPASS_CNTL 0x16E9C
74 #define mmCLK1_CLK3_BYPASS_CNTL 0x16EA5
75 #define mmCLK1_CLK4_BYPASS_CNTL 0x16EAE
76 #define mmCLK1_CLK5_BYPASS_CNTL 0x16EB7
77
78 #define mmCLK1_CLK0_DS_CNTL 0x16E83
79 #define mmCLK1_CLK1_DS_CNTL 0x16E8C
80 #define mmCLK1_CLK2_DS_CNTL 0x16E95
81 #define mmCLK1_CLK3_DS_CNTL 0x16E9E
82 #define mmCLK1_CLK4_DS_CNTL 0x16EA7
83 #define mmCLK1_CLK5_DS_CNTL 0x16EB0
84
85 #define mmCLK1_CLK0_ALLOW_DS 0x16E84
86 #define mmCLK1_CLK1_ALLOW_DS 0x16E8D
87 #define mmCLK1_CLK2_ALLOW_DS 0x16E96
88 #define mmCLK1_CLK3_ALLOW_DS 0x16E9F
89 #define mmCLK1_CLK4_ALLOW_DS 0x16EA8
90 #define mmCLK1_CLK5_ALLOW_DS 0x16EB1
91
92 #define mmCLK5_spll_field_8 0x1B24B
93 #define mmCLK6_spll_field_8 0x1B24B
94 #define mmDENTIST_DISPCLK_CNTL 0x0124
95 #define regDENTIST_DISPCLK_CNTL 0x0064
96 #define regDENTIST_DISPCLK_CNTL_BASE_IDX 1
97
98 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
99 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
100 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
101 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
102 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
103 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
104
105 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK 0x00000007L
106 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK 0x000F0000L
107 // DENTIST_DISPCLK_CNTL
108 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
109 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
110 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
111 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14
112 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18
113 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007FL
114 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007F00L
115 #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L
116 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE_MASK 0x00100000L
117 #define DENTIST_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER_MASK 0x7F000000L
118
119 #define CLK5_spll_field_8__spll_ssc_en_MASK 0x00002000L
120 #define CLK6_spll_field_8__spll_ssc_en_MASK 0x00002000L
121
122 #define SMU_VER_THRESHOLD 0x5D4A00 //93.74.0
123 #undef FN
124 #define FN(reg_name, field_name) \
125 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
126
127 #define REG(reg) \
128 (clk_mgr->regs->reg)
129
130 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
131
132 #define BASE(seg) BASE_INNER(seg)
133
134 #define SR(reg_name)\
135 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
136 reg ## reg_name
137
138 #define CLK_SR_DCN35(reg_name)\
139 .reg_name = mm ## reg_name
140
141 static const struct clk_mgr_registers clk_mgr_regs_dcn35 = {
142 CLK_REG_LIST_DCN35()
143 };
144
145 static const struct clk_mgr_shift clk_mgr_shift_dcn35 = {
146 CLK_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
147 };
148
149 static const struct clk_mgr_mask clk_mgr_mask_dcn35 = {
150 CLK_COMMON_MASK_SH_LIST_DCN32(_MASK)
151 };
152
153 #define TO_CLK_MGR_DCN35(clk_mgr)\
154 container_of(clk_mgr, struct clk_mgr_dcn35, base)
155
dcn35_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context,int * all_active_disps)156 static int dcn35_get_active_display_cnt_wa(
157 struct dc *dc,
158 struct dc_state *context,
159 int *all_active_disps)
160 {
161 int i, display_count = 0;
162 bool tmds_present = false;
163
164 for (i = 0; i < context->stream_count; i++) {
165 const struct dc_stream_state *stream = context->streams[i];
166
167 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
168 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
169 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
170 tmds_present = true;
171 }
172
173 for (i = 0; i < dc->link_count; i++) {
174 const struct dc_link *link = dc->links[i];
175
176 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
177 if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
178 link->link_enc->funcs->is_dig_enabled(link->link_enc))
179 display_count++;
180 }
181 if (all_active_disps != NULL)
182 *all_active_disps = display_count;
183 /* WA for hang on HDMI after display off back on*/
184 if (display_count == 0 && tmds_present)
185 display_count = 1;
186
187 return display_count;
188 }
dcn35_disable_otg_wa(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower,bool disable)189 void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,
190 bool safe_to_lower, bool disable)
191 {
192 struct dc *dc = clk_mgr_base->ctx->dc;
193 uint8_t i;
194
195 if (dc->ctx->dce_environment == DCE_ENV_DIAG)
196 return;
197
198 for (i = 0; i < dc->res_pool->pipe_count; ++i) {
199 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
200 struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
201 struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
202 struct dccg *dccg = clk_mgr_internal->dccg;
203 struct pipe_ctx *pipe = safe_to_lower
204 ? &context->res_ctx.pipe_ctx[i]
205 : &dc->current_state->res_ctx.pipe_ctx[i];
206 struct link_encoder *new_pipe_link_enc = new_pipe->link_res.dio_link_enc;
207 struct link_encoder *pipe_link_enc = pipe->link_res.dio_link_enc;
208 bool stream_changed_otg_dig_on = false;
209 bool has_active_hpo = false;
210
211 if (pipe->top_pipe || pipe->prev_odm_pipe)
212 continue;
213
214 if (!dc->config.unify_link_enc_assignment) {
215 if (new_pipe->stream)
216 new_pipe_link_enc = new_pipe->stream->link_enc;
217 if (pipe->stream)
218 pipe_link_enc = pipe->stream->link_enc;
219 }
220
221 stream_changed_otg_dig_on = old_pipe->stream && new_pipe->stream &&
222 old_pipe->stream != new_pipe->stream &&
223 old_pipe->stream_res.tg == new_pipe->stream_res.tg &&
224 new_pipe_link_enc && !new_pipe->stream->dpms_off &&
225 new_pipe_link_enc->funcs->is_dig_enabled &&
226 new_pipe_link_enc->funcs->is_dig_enabled(
227 new_pipe_link_enc) &&
228 new_pipe->stream_res.stream_enc &&
229 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled &&
230 new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled(new_pipe->stream_res.stream_enc);
231
232 if (old_pipe->stream && new_pipe->stream && old_pipe->stream == new_pipe->stream) {
233 has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) &&
234 dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe);
235 has_active_hpo = has_active_hpo || (old_pipe->stream->signal == SIGNAL_TYPE_HDMI_FRL &&
236 new_pipe->stream->signal == SIGNAL_TYPE_HDMI_FRL);
237
238 }
239
240 if (!has_active_hpo && !stream_changed_otg_dig_on && pipe->stream &&
241 (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) || !pipe_link_enc) &&
242 !dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe)) {
243 /* This w/a should not trigger when we have a dig active */
244 if (disable) {
245 if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)
246 pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
247
248 reset_sync_context_for_pipe(dc, context, i);
249 } else {
250 pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
251 }
252 }
253 }
254 }
255
dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,int ref_dtbclk_khz)256 static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
257 struct dc_state *context,
258 int ref_dtbclk_khz)
259 {
260 struct dccg *dccg = clk_mgr->dccg;
261 uint32_t tg_mask = 0;
262 uint32_t i;
263
264 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
265 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
266 struct dtbclk_dto_params dto_params = {0};
267
268 /* use mask to program DTO once per tg */
269 if (pipe_ctx->stream_res.tg &&
270 !(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
271 tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
272
273 dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
274 dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
275
276 if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal) ||
277 dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
278 dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
279
280 if (pipe_ctx->stream_res.audio != NULL)
281 dto_params.req_audio_dtbclk_khz = 24000;
282 }
283
284 if (dc_is_hdmi_signal(pipe_ctx->stream->signal) ||
285 dc_is_dvi_signal(pipe_ctx->stream->signal))
286 dto_params.is_hdmi = true;
287
288 dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
289 //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
290 }
291 }
292 }
293
dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,bool safe_to_lower)294 static void dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
295 struct dc_state *context, bool safe_to_lower)
296 {
297 uint32_t i;
298 bool dppclk_active[MAX_PIPES] = {0};
299
300
301 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
302 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
303 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
304
305 dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
306
307 if (context->res_ctx.pipe_ctx[i].plane_res.dpp)
308 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
309 else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
310 /* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
311 * In this case just continue in loop
312 */
313 continue;
314 } else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
315 /* The software state is not valid if dpp resource is NULL and
316 * dppclk_khz > 0.
317 */
318 ASSERT(false);
319 continue;
320 }
321
322 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
323
324 if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
325 clk_mgr->dccg->funcs->update_dpp_dto(
326 clk_mgr->dccg, dpp_inst, dppclk_khz);
327 dppclk_active[dpp_inst] = true;
328 }
329 if (safe_to_lower)
330 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
331 struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;
332
333 if (old_dpp && !dppclk_active[old_dpp->inst])
334 clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0);
335 }
336 }
337
get_lowest_dpia_index(const struct dc_link * link)338 static uint8_t get_lowest_dpia_index(const struct dc_link *link)
339 {
340 const struct dc *dc_struct = link->dc;
341 uint8_t idx = 0xFF;
342 int i;
343
344 for (i = 0; i < MAX_PIPES * 2; ++i) {
345 if (!dc_struct->links[i] || dc_struct->links[i]->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)
346 continue;
347
348 if (idx > dc_struct->links[i]->link_index)
349 idx = (uint8_t)dc_struct->links[i]->link_index;
350 }
351
352 return idx;
353 }
354
dcn35_notify_host_router_bw(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)355 static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_state *context,
356 bool safe_to_lower)
357 {
358 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
359 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
360 uint32_t host_router_bw_kbps[MAX_HOST_ROUTERS_NUM] = { 0 };
361 int i;
362 for (i = 0; i < context->stream_count; ++i) {
363 const struct dc_stream_state *stream = context->streams[i];
364 const struct dc_link *link = stream->link;
365 uint8_t lowest_dpia_index = 0;
366 unsigned int hr_index = 0;
367
368 if (!link)
369 continue;
370
371 lowest_dpia_index = get_lowest_dpia_index(link);
372 if (link->link_index < lowest_dpia_index)
373 continue;
374
375 hr_index = (link->link_index - lowest_dpia_index) / 2;
376 if (hr_index >= MAX_HOST_ROUTERS_NUM)
377 continue;
378 host_router_bw_kbps[hr_index] += dc_bandwidth_in_kbps_from_timing(
379 &stream->timing, dc_link_get_highest_encoding_format(link));
380 }
381
382 for (i = 0; i < MAX_HOST_ROUTERS_NUM; ++i) {
383 new_clocks->host_router_bw_kbps[i] = host_router_bw_kbps[i];
384 if (should_set_clock(safe_to_lower, new_clocks->host_router_bw_kbps[i], clk_mgr_base->clks.host_router_bw_kbps[i])) {
385 clk_mgr_base->clks.host_router_bw_kbps[i] = new_clocks->host_router_bw_kbps[i];
386 dcn35_smu_notify_host_router_bw(clk_mgr, i, new_clocks->host_router_bw_kbps[i]);
387 }
388 }
389 }
390
dcn35_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)391 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
392 struct dc_state *context,
393 bool safe_to_lower)
394 {
395 union dmub_rb_cmd cmd;
396 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
397 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
398 struct dc *dc = clk_mgr_base->ctx->dc;
399 int display_count = 0;
400 bool update_dppclk = false;
401 bool update_dispclk = false;
402 bool dpp_clock_lowered = false;
403 int all_active_disps = 0;
404
405 if (dc->work_arounds.skip_clock_update)
406 return;
407
408 display_count = dcn35_get_active_display_cnt_wa(dc, context, &all_active_disps);
409 if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz)
410 new_clocks->ref_dtbclk_khz = 600000;
411 else if (!new_clocks->dtbclk_en && new_clocks->ref_dtbclk_khz > 590000)
412 new_clocks->ref_dtbclk_khz = 0;
413
414 /*
415 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
416 * also if safe to lower is false, we just go in the higher state
417 */
418 if (safe_to_lower) {
419 if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW &&
420 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
421 dcn35_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);
422 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true);
423 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
424 }
425
426 if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
427 if (clk_mgr->base.ctx->dc->config.allow_0_dtb_clk)
428 dcn35_smu_set_dtbclk(clk_mgr, false);
429
430 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
431 }
432 /* check that we're not already in lower */
433 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
434 /* if we can go lower, go lower */
435 if (display_count == 0)
436 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
437 }
438 } else {
439 if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&
440 new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
441 dcn35_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);
442 dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false);
443 clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
444 }
445
446 if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
447 int actual_dtbclk = 0;
448
449 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
450 dcn35_smu_set_dtbclk(clk_mgr, true);
451
452 actual_dtbclk = REG_READ(CLK1_CLK4_CURRENT_CNT);
453
454 if (actual_dtbclk > 590000) {
455 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
456 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
457 }
458 }
459
460 /* check that we're not already in D0 */
461 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
462 union display_idle_optimization_u idle_info = { 0 };
463
464 dcn35_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
465 /* update power state */
466 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
467 }
468 }
469 if (dc->debug.force_min_dcfclk_mhz > 0) {
470 int force_min_dcfclk_khz = dc->debug.force_min_dcfclk_mhz * 1000;
471
472 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > force_min_dcfclk_khz) ?
473 new_clocks->dcfclk_khz : force_min_dcfclk_khz;
474 }
475
476 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
477 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
478 dcn35_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
479 }
480
481 if (should_set_clock(safe_to_lower,
482 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
483 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
484 dcn35_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
485 }
486
487 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
488 if (new_clocks->dppclk_khz < 100000)
489 new_clocks->dppclk_khz = 100000;
490
491 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
492 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
493 dpp_clock_lowered = true;
494 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
495 update_dppclk = true;
496 }
497
498 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) &&
499 (new_clocks->dispclk_khz > 0 || (safe_to_lower && display_count == 0))) {
500 uint32_t requested_dispclk_khz = new_clocks->dispclk_khz;
501
502 dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
503
504 /* Clamp the requested clock to PMFW based on their limit. */
505 if (dc->debug.min_disp_clk_khz > 0 && requested_dispclk_khz < dc->debug.min_disp_clk_khz)
506 requested_dispclk_khz = dc->debug.min_disp_clk_khz;
507
508 dcn35_smu_set_dispclk(clk_mgr, requested_dispclk_khz);
509 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
510
511 dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
512
513 update_dispclk = true;
514 }
515
516 /* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
517 if (!dc->debug.disable_dtb_ref_clk_switch &&
518 should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000,
519 clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
520 dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
521 clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
522 }
523
524 if (dpp_clock_lowered) {
525 // increase per DPP DTO before lowering global dppclk
526 dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
527 dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
528 } else {
529 // increase global DPPCLK before lowering per DPP DTO
530 if (update_dppclk || update_dispclk)
531 dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
532 dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
533 }
534
535 // notify PMFW of bandwidth per DPIA tunnel
536 if (dc->debug.notify_dpia_hr_bw)
537 dcn35_notify_host_router_bw(clk_mgr_base, context, safe_to_lower);
538
539 // notify DMCUB of latest clocks
540 memset(&cmd, 0, sizeof(cmd));
541 cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
542 cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
543 cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
544 cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
545 clk_mgr_base->clks.dcfclk_deep_sleep_khz;
546 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
547 cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
548
549 dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
550 }
551
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)552 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
553 {
554 /* get FbMult value */
555 struct fixed31_32 pll_req;
556 unsigned int fbmult_frac_val = 0;
557 unsigned int fbmult_int_val = 0;
558
559 /*
560 * Register value of fbmult is in 8.16 format, we are converting to 314.32
561 * to leverage the fix point operations available in driver
562 */
563
564 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
565 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
566
567 pll_req = dc_fixpt_from_int(fbmult_int_val);
568
569 /*
570 * since fractional part is only 16 bit in register definition but is 32 bit
571 * in our fix point definiton, need to shift left by 16 to obtain correct value
572 */
573 pll_req.value |= fbmult_frac_val << 16;
574
575 /* multiply by REFCLK period */
576 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
577
578 /* integer part is now VCO frequency in kHz */
579 return dc_fixpt_floor(pll_req);
580 }
581
dcn35_enable_pme_wa(struct clk_mgr * clk_mgr_base)582 static void dcn35_enable_pme_wa(struct clk_mgr *clk_mgr_base)
583 {
584 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
585
586 dcn35_smu_enable_pme_wa(clk_mgr);
587 }
588
589
dcn35_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)590 bool dcn35_are_clock_states_equal(struct dc_clocks *a,
591 struct dc_clocks *b)
592 {
593 if (a->dispclk_khz != b->dispclk_khz)
594 return false;
595 else if (a->dppclk_khz != b->dppclk_khz)
596 return false;
597 else if (a->dcfclk_khz != b->dcfclk_khz)
598 return false;
599 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
600 return false;
601 else if (a->zstate_support != b->zstate_support)
602 return false;
603 else if (a->dtbclk_en != b->dtbclk_en)
604 return false;
605
606 return true;
607 }
608
dcn35_save_clk_registers_internal(struct dcn35_clk_internal * internal,struct clk_mgr * clk_mgr_base)609 static void dcn35_save_clk_registers_internal(struct dcn35_clk_internal *internal, struct clk_mgr *clk_mgr_base)
610 {
611 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
612
613 // read dtbclk
614 internal->CLK1_CLK4_CURRENT_CNT = REG_READ(CLK1_CLK4_CURRENT_CNT);
615 internal->CLK1_CLK4_BYPASS_CNTL = REG_READ(CLK1_CLK4_BYPASS_CNTL);
616
617 // read dcfclk
618 internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_CLK3_CURRENT_CNT);
619 internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_CLK3_BYPASS_CNTL);
620
621 // read dcf deep sleep divider
622 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_CLK3_DS_CNTL);
623 internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_CLK3_ALLOW_DS);
624
625 // read dppclk
626 internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_CLK1_CURRENT_CNT);
627 internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_CLK1_BYPASS_CNTL);
628
629 // read dprefclk
630 internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_CLK2_CURRENT_CNT);
631 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_CLK2_BYPASS_CNTL);
632
633 // read dispclk
634 internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_CLK0_CURRENT_CNT);
635 internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_CLK0_BYPASS_CNTL);
636 }
637
dcn35_save_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr_dcn35 * clk_mgr)638 static void dcn35_save_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
639 struct clk_mgr_dcn35 *clk_mgr)
640 {
641 struct dcn35_clk_internal internal = {0};
642 char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
643
644 dcn35_save_clk_registers_internal(&internal, &clk_mgr->base.base);
645
646 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
647 regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
648 regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;
649 regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
650 regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
651 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
652 regs_and_bypass->dtbclk = internal.CLK1_CLK4_CURRENT_CNT / 10;
653
654 regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
655 if (regs_and_bypass->dppclk_bypass > 4)
656 regs_and_bypass->dppclk_bypass = 0;
657 regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
658 if (regs_and_bypass->dcfclk_bypass > 4)
659 regs_and_bypass->dcfclk_bypass = 0;
660 regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
661 if (regs_and_bypass->dispclk_bypass > 4)
662 regs_and_bypass->dispclk_bypass = 0;
663 regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
664 if (regs_and_bypass->dprefclk_bypass > 4)
665 regs_and_bypass->dprefclk_bypass = 0;
666
667 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
668 DC_LOG_SMU("clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
669
670 DC_LOG_SMU("dcfclk,%d,%d,%d,%s\n",
671 regs_and_bypass->dcfclk,
672 regs_and_bypass->dcf_deep_sleep_divider,
673 regs_and_bypass->dcf_deep_sleep_allow,
674 bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
675
676 DC_LOG_SMU("dprefclk,%d,N/A,N/A,%s\n",
677 regs_and_bypass->dprefclk,
678 bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
679
680 DC_LOG_SMU("dispclk,%d,N/A,N/A,%s\n",
681 regs_and_bypass->dispclk,
682 bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
683
684 // REGISTER VALUES
685 DC_LOG_SMU("reg_name,value,clk_type");
686
687 DC_LOG_SMU("CLK1_CLK3_CURRENT_CNT,%d,dcfclk",
688 internal.CLK1_CLK3_CURRENT_CNT);
689
690 DC_LOG_SMU("CLK1_CLK4_CURRENT_CNT,%d,dtbclk",
691 internal.CLK1_CLK4_CURRENT_CNT);
692
693 DC_LOG_SMU("CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider",
694 internal.CLK1_CLK3_DS_CNTL);
695
696 DC_LOG_SMU("CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow",
697 internal.CLK1_CLK3_ALLOW_DS);
698
699 DC_LOG_SMU("CLK1_CLK2_CURRENT_CNT,%d,dprefclk",
700 internal.CLK1_CLK2_CURRENT_CNT);
701
702 DC_LOG_SMU("CLK1_CLK0_CURRENT_CNT,%d,dispclk",
703 internal.CLK1_CLK0_CURRENT_CNT);
704
705 DC_LOG_SMU("CLK1_CLK1_CURRENT_CNT,%d,dppclk",
706 internal.CLK1_CLK1_CURRENT_CNT);
707
708 DC_LOG_SMU("CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass",
709 internal.CLK1_CLK3_BYPASS_CNTL);
710
711 DC_LOG_SMU("CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass",
712 internal.CLK1_CLK2_BYPASS_CNTL);
713
714 DC_LOG_SMU("CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass",
715 internal.CLK1_CLK0_BYPASS_CNTL);
716
717 DC_LOG_SMU("CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass",
718 internal.CLK1_CLK1_BYPASS_CNTL);
719
720 }
721 }
722
dcn35_is_spll_ssc_enabled(struct clk_mgr * clk_mgr_base)723 static bool dcn35_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base)
724 {
725 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
726
727 uint32_t ssc_enable;
728
729 if (clk_mgr_base->ctx->dce_version == DCN_VERSION_3_51) {
730 ssc_enable = REG_READ(CLK6_spll_field_8) & CLK6_spll_field_8__spll_ssc_en_MASK;
731 } else {
732 ssc_enable = REG_READ(CLK5_spll_field_8) & CLK5_spll_field_8__spll_ssc_en_MASK;
733 }
734
735 return ssc_enable != 0;
736 }
737
init_clk_states(struct clk_mgr * clk_mgr)738 static void init_clk_states(struct clk_mgr *clk_mgr)
739 {
740 uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;
741
742 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
743
744 clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk; // restore ref_dtbclk
745 clk_mgr->clks.p_state_change_support = true;
746 clk_mgr->clks.prev_p_state_change_support = true;
747 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
748 clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
749 }
750
dcn35_init_clocks(struct clk_mgr * clk_mgr)751 void dcn35_init_clocks(struct clk_mgr *clk_mgr)
752 {
753 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
754 struct clk_mgr_dcn35 *clk_mgr_dcn35 = TO_CLK_MGR_DCN35(clk_mgr_int);
755
756 init_clk_states(clk_mgr);
757
758 // to adjust dp_dto reference clock if ssc is enable otherwise to apply dprefclk
759 if (dcn35_is_spll_ssc_enabled(clk_mgr))
760 clk_mgr->dp_dto_source_clock_in_khz =
761 dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr->dprefclk_khz);
762 else
763 clk_mgr->dp_dto_source_clock_in_khz = clk_mgr->dprefclk_khz;
764
765 dcn35_save_clk_registers(&clk_mgr->boot_snapshot, clk_mgr_dcn35);
766
767 clk_mgr->clks.ref_dtbclk_khz = clk_mgr->boot_snapshot.dtbclk * 10;
768 if (clk_mgr->boot_snapshot.dtbclk > 59000) {
769 /*dtbclk enabled based on */
770 clk_mgr->clks.dtbclk_en = true;
771 }
772 }
773 static struct clk_bw_params dcn35_bw_params = {
774 .vram_type = Ddr4MemType,
775 .num_channels = 1,
776 .clk_table = {
777 .num_entries = 4,
778 },
779
780 };
781
782 static struct wm_table ddr5_wm_table = {
783 .entries = {
784 {
785 .wm_inst = WM_A,
786 .wm_type = WM_TYPE_PSTATE_CHG,
787 .pstate_latency_us = 11.72,
788 .sr_exit_time_us = 31.0,
789 .sr_enter_plus_exit_time_us = 33.0,
790 .valid = true,
791 },
792 {
793 .wm_inst = WM_B,
794 .wm_type = WM_TYPE_PSTATE_CHG,
795 .pstate_latency_us = 11.72,
796 .sr_exit_time_us = 31.0,
797 .sr_enter_plus_exit_time_us = 33.0,
798 .valid = true,
799 },
800 {
801 .wm_inst = WM_C,
802 .wm_type = WM_TYPE_PSTATE_CHG,
803 .pstate_latency_us = 11.72,
804 .sr_exit_time_us = 31.0,
805 .sr_enter_plus_exit_time_us = 33.0,
806 .valid = true,
807 },
808 {
809 .wm_inst = WM_D,
810 .wm_type = WM_TYPE_PSTATE_CHG,
811 .pstate_latency_us = 11.72,
812 .sr_exit_time_us = 31.0,
813 .sr_enter_plus_exit_time_us = 33.0,
814 .valid = true,
815 },
816 }
817 };
818
819 static struct wm_table lpddr5_wm_table = {
820 .entries = {
821 {
822 .wm_inst = WM_A,
823 .wm_type = WM_TYPE_PSTATE_CHG,
824 .pstate_latency_us = 11.65333,
825 .sr_exit_time_us = 28.0,
826 .sr_enter_plus_exit_time_us = 30.0,
827 .valid = true,
828 },
829 {
830 .wm_inst = WM_B,
831 .wm_type = WM_TYPE_PSTATE_CHG,
832 .pstate_latency_us = 11.65333,
833 .sr_exit_time_us = 28.0,
834 .sr_enter_plus_exit_time_us = 30.0,
835 .valid = true,
836 },
837 {
838 .wm_inst = WM_C,
839 .wm_type = WM_TYPE_PSTATE_CHG,
840 .pstate_latency_us = 11.65333,
841 .sr_exit_time_us = 28.0,
842 .sr_enter_plus_exit_time_us = 30.0,
843 .valid = true,
844 },
845 {
846 .wm_inst = WM_D,
847 .wm_type = WM_TYPE_PSTATE_CHG,
848 .pstate_latency_us = 11.65333,
849 .sr_exit_time_us = 28.0,
850 .sr_enter_plus_exit_time_us = 30.0,
851 .valid = true,
852 },
853 }
854 };
855
856 static DpmClocks_t_dcn35 dummy_clocks;
857 static DpmClocks_t_dcn351 dummy_clocks_dcn351;
858
859 static struct dcn35_watermarks dummy_wms = { 0 };
860
861 static struct dcn35_ss_info_table ss_info_table = {
862 .ss_divider = 1000,
863 .ss_percentage = {0, 0, 375, 375, 375}
864 };
865
dcn35_read_ss_info_from_lut(struct clk_mgr_internal * clk_mgr)866 static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)
867 {
868 uint32_t clock_source = 0;
869
870 clock_source = REG_READ(CLK1_CLK2_BYPASS_CNTL) & CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK;
871
872 // If it's DFS mode, clock_source is 0.
873 if (dcn35_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(ss_info_table.ss_percentage))) {
874 clk_mgr->dprefclk_ss_percentage = ss_info_table.ss_percentage[clock_source];
875
876 if (clk_mgr->dprefclk_ss_percentage != 0) {
877 clk_mgr->ss_on_dprefclk = true;
878 clk_mgr->dprefclk_ss_divider = ss_info_table.ss_divider;
879 }
880 }
881 }
882
dcn35_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn35_watermarks * table)883 static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table)
884 {
885 uint8_t i, num_valid_sets;
886
887 num_valid_sets = 0;
888
889 for (i = 0; i < WM_SET_COUNT; i++) {
890 /* skip empty entries, the smu array has no holes*/
891 if (!bw_params->wm_table.entries[i].valid)
892 continue;
893
894 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
895 (uint8_t)bw_params->wm_table.entries[i].wm_inst;
896 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
897 (uint8_t)bw_params->wm_table.entries[i].wm_type;
898 /* We will not select WM based on fclk, so leave it as unconstrained */
899 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
900 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
901
902 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
903 if (i == 0)
904 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
905 else {
906 /* add 1 to make it non-overlapping with next lvl */
907 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
908 (uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1);
909 }
910 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
911 (uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
912
913 } else {
914 /* unconstrained for memory retraining */
915 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
916 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
917
918 /* Modify previous watermark range to cover up to max */
919 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
920 }
921 num_valid_sets++;
922 }
923
924 ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
925
926 /* modify the min and max to make sure we cover the whole range*/
927 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
928 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
929 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
930 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
931
932 /* This is for writeback only, does not matter currently as no writeback support*/
933 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
934 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
935 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
936 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
937 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
938 }
939
dcn35_notify_wm_ranges(struct clk_mgr * clk_mgr_base)940 static void dcn35_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
941 {
942 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
943 struct clk_mgr_dcn35 *clk_mgr_dcn35 = TO_CLK_MGR_DCN35(clk_mgr);
944 struct dcn35_watermarks *table = clk_mgr_dcn35->smu_wm_set.wm_set;
945
946 if (!clk_mgr->smu_ver)
947 return;
948
949 if (!table || clk_mgr_dcn35->smu_wm_set.mc_address.quad_part == 0)
950 return;
951
952 memset(table, 0, sizeof(*table));
953
954 dcn35_build_watermark_ranges(clk_mgr_base->bw_params, table);
955
956 dcn35_smu_set_dram_addr_high(clk_mgr,
957 clk_mgr_dcn35->smu_wm_set.mc_address.high_part);
958 dcn35_smu_set_dram_addr_low(clk_mgr,
959 clk_mgr_dcn35->smu_wm_set.mc_address.low_part);
960 dcn35_smu_transfer_wm_table_dram_2_smu(clk_mgr);
961 }
962
dcn35_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn35_smu_dpm_clks * smu_dpm_clks)963 static void dcn35_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
964 struct dcn35_smu_dpm_clks *smu_dpm_clks)
965 {
966 DpmClocks_t_dcn35 *table = smu_dpm_clks->dpm_clks;
967
968 if (!clk_mgr->smu_ver)
969 return;
970
971 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
972 return;
973
974 memset(table, 0, sizeof(*table));
975
976 dcn35_smu_set_dram_addr_high(clk_mgr,
977 smu_dpm_clks->mc_address.high_part);
978 dcn35_smu_set_dram_addr_low(clk_mgr,
979 smu_dpm_clks->mc_address.low_part);
980 dcn35_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
981 }
982
dcn351_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn351_smu_dpm_clks * smu_dpm_clks)983 static void dcn351_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
984 struct dcn351_smu_dpm_clks *smu_dpm_clks)
985 {
986 DpmClocks_t_dcn351 *table = smu_dpm_clks->dpm_clks;
987
988 if (!clk_mgr->smu_ver)
989 return;
990 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
991 return;
992 memset(table, 0, sizeof(*table));
993 dcn35_smu_set_dram_addr_high(clk_mgr,
994 smu_dpm_clks->mc_address.high_part);
995 dcn35_smu_set_dram_addr_low(clk_mgr,
996 smu_dpm_clks->mc_address.low_part);
997 dcn35_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
998 }
find_max_clk_value(const uint32_t clocks[],uint32_t num_clocks)999 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
1000 {
1001 uint32_t max = 0;
1002 uint32_t i;
1003
1004 for (i = 0; i < num_clocks; ++i) {
1005 if (clocks[i] > max)
1006 max = clocks[i];
1007 }
1008
1009 return max;
1010 }
1011
is_valid_clock_value(uint32_t clock_value)1012 static inline bool is_valid_clock_value(uint32_t clock_value)
1013 {
1014 return clock_value > 1 && clock_value < 100000;
1015 }
1016
convert_wck_ratio(uint8_t wck_ratio)1017 static unsigned int convert_wck_ratio(uint8_t wck_ratio)
1018 {
1019 switch (wck_ratio) {
1020 case WCK_RATIO_1_2:
1021 return 2;
1022
1023 case WCK_RATIO_1_4:
1024 return 4;
1025 /* Find lowest DPM, FCLK is filled in reverse order*/
1026
1027 default:
1028 break;
1029 }
1030
1031 return 1;
1032 }
1033
calc_dram_speed_mts(const MemPstateTable_t * entry)1034 static inline uint32_t calc_dram_speed_mts(const MemPstateTable_t *entry)
1035 {
1036 return entry->UClk * convert_wck_ratio(entry->WckRatio) * 2;
1037 }
1038
dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,DpmClocks_t_dcn35 * clock_table)1039 static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
1040 struct integrated_info *bios_info,
1041 DpmClocks_t_dcn35 *clock_table)
1042 {
1043 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
1044 struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
1045 uint32_t max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0;
1046 uint32_t max_pstate = 0, max_dram_speed_mts = 0, min_dram_speed_mts = 0;
1047 uint32_t num_memps, num_fclk, num_dcfclk;
1048 int i;
1049 unsigned int entry_idx;
1050
1051 /* Determine min/max p-state values. */
1052 num_memps = (clock_table->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS) ? NUM_MEM_PSTATE_LEVELS :
1053 clock_table->NumMemPstatesEnabled;
1054 for (entry_idx = 0; entry_idx < num_memps; entry_idx++) {
1055 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[entry_idx]);
1056
1057 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts > max_dram_speed_mts) {
1058 max_dram_speed_mts = dram_speed_mts;
1059 max_pstate = entry_idx;
1060 }
1061 }
1062
1063 min_dram_speed_mts = max_dram_speed_mts;
1064 min_pstate = max_pstate;
1065
1066 for (entry_idx = 0; entry_idx < num_memps; entry_idx++) {
1067 uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[entry_idx]);
1068
1069 if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts < min_dram_speed_mts) {
1070 min_dram_speed_mts = dram_speed_mts;
1071 min_pstate = entry_idx;
1072 }
1073 }
1074
1075 /* We expect the table to contain at least one valid P-state entry. */
1076 ASSERT(clock_table->NumMemPstatesEnabled &&
1077 is_valid_clock_value(max_dram_speed_mts) &&
1078 is_valid_clock_value(min_dram_speed_mts));
1079
1080 /* dispclk and dppclk can be max at any voltage, same number of levels for both */
1081 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
1082 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
1083 max_dispclk = find_max_clk_value(clock_table->DispClocks,
1084 clock_table->NumDispClkLevelsEnabled);
1085 max_dppclk = find_max_clk_value(clock_table->DppClocks,
1086 clock_table->NumDispClkLevelsEnabled);
1087 } else {
1088 /* Invalid number of entries in the table from PMFW. */
1089 ASSERT(0);
1090 }
1091
1092 /* Base the clock table on dcfclk, need at least one entry regardless of pmfw table */
1093 ASSERT(clock_table->NumDcfClkLevelsEnabled > 0);
1094
1095 num_fclk = (clock_table->NumFclkLevelsEnabled > NUM_FCLK_DPM_LEVELS) ? NUM_FCLK_DPM_LEVELS :
1096 clock_table->NumFclkLevelsEnabled;
1097 max_fclk = find_max_clk_value(clock_table->FclkClocks_Freq, num_fclk);
1098
1099 num_dcfclk = (clock_table->NumDcfClkLevelsEnabled > NUM_DCFCLK_DPM_LEVELS) ? NUM_DCFCLK_DPM_LEVELS :
1100 clock_table->NumDcfClkLevelsEnabled;
1101 for (entry_idx = 0; entry_idx < num_dcfclk; entry_idx++) {
1102 int j;
1103
1104 /* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
1105 for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
1106 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[entry_idx])
1107 break;
1108
1109 bw_params->clk_table.entries[entry_idx].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
1110 bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
1111 bw_params->clk_table.entries[entry_idx].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
1112
1113 /* Now update clocks we do read */
1114 bw_params->clk_table.entries[entry_idx].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk;
1115 bw_params->clk_table.entries[entry_idx].voltage = clock_table->MemPstateTable[min_pstate].Voltage;
1116 bw_params->clk_table.entries[entry_idx].dcfclk_mhz = clock_table->DcfClocks[entry_idx];
1117 bw_params->clk_table.entries[entry_idx].socclk_mhz = clock_table->SocClocks[entry_idx];
1118 bw_params->clk_table.entries[entry_idx].dispclk_mhz = max_dispclk;
1119 bw_params->clk_table.entries[entry_idx].dppclk_mhz = max_dppclk;
1120 bw_params->clk_table.entries[entry_idx].wck_ratio =
1121 convert_wck_ratio(clock_table->MemPstateTable[min_pstate].WckRatio);
1122
1123 /* Dcfclk and Fclk are tied, but at a different ratio */
1124 bw_params->clk_table.entries[entry_idx].fclk_mhz = min(max_fclk, 2 * clock_table->DcfClocks[entry_idx]);
1125 }
1126 i = (int)entry_idx;
1127
1128 /* Make sure to include at least one entry at highest pstate */
1129 if (max_pstate != min_pstate || i == 0) {
1130 if (i > MAX_NUM_DPM_LVL - 1)
1131 i = MAX_NUM_DPM_LVL - 1;
1132
1133 bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
1134 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[max_pstate].MemClk;
1135 bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[max_pstate].Voltage;
1136 bw_params->clk_table.entries[i].dcfclk_mhz =
1137 find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS);
1138 bw_params->clk_table.entries[i].socclk_mhz =
1139 find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
1140 bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
1141 bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
1142 bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
1143 clock_table->MemPstateTable[max_pstate].WckRatio);
1144 i++;
1145 }
1146 bw_params->clk_table.num_entries = i--;
1147
1148 /* Make sure all highest clocks are included*/
1149 bw_params->clk_table.entries[i].socclk_mhz =
1150 find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
1151 bw_params->clk_table.entries[i].dispclk_mhz =
1152 find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS);
1153 bw_params->clk_table.entries[i].dppclk_mhz =
1154 find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS);
1155 bw_params->clk_table.entries[i].fclk_mhz =
1156 find_max_clk_value(clock_table->FclkClocks_Freq, NUM_FCLK_DPM_LEVELS);
1157 ASSERT(clock_table->DcfClocks[i] == find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS));
1158 bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
1159 bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
1160 bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
1161 bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = clock_table->NumDcfClkLevelsEnabled;
1162 bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = clock_table->NumDispClkLevelsEnabled;
1163 bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = clock_table->NumDispClkLevelsEnabled;
1164 bw_params->clk_table.num_entries_per_clk.num_fclk_levels = clock_table->NumFclkLevelsEnabled;
1165 bw_params->clk_table.num_entries_per_clk.num_memclk_levels = clock_table->NumMemPstatesEnabled;
1166 bw_params->clk_table.num_entries_per_clk.num_socclk_levels = clock_table->NumSocClkLevelsEnabled;
1167
1168 /*
1169 * Set any 0 clocks to max default setting. Not an issue for
1170 * power since we aren't doing switching in such case anyway
1171 */
1172 for (entry_idx = 0; entry_idx < bw_params->clk_table.num_entries; entry_idx++) {
1173 if (!bw_params->clk_table.entries[entry_idx].fclk_mhz) {
1174 bw_params->clk_table.entries[entry_idx].fclk_mhz = def_max.fclk_mhz;
1175 bw_params->clk_table.entries[entry_idx].memclk_mhz = def_max.memclk_mhz;
1176 bw_params->clk_table.entries[entry_idx].voltage = def_max.voltage;
1177 }
1178 if (!bw_params->clk_table.entries[entry_idx].dcfclk_mhz)
1179 bw_params->clk_table.entries[entry_idx].dcfclk_mhz = def_max.dcfclk_mhz;
1180 if (!bw_params->clk_table.entries[entry_idx].socclk_mhz)
1181 bw_params->clk_table.entries[entry_idx].socclk_mhz = def_max.socclk_mhz;
1182 if (!bw_params->clk_table.entries[entry_idx].dispclk_mhz)
1183 bw_params->clk_table.entries[entry_idx].dispclk_mhz = def_max.dispclk_mhz;
1184 if (!bw_params->clk_table.entries[entry_idx].dppclk_mhz)
1185 bw_params->clk_table.entries[entry_idx].dppclk_mhz = def_max.dppclk_mhz;
1186 if (!bw_params->clk_table.entries[entry_idx].fclk_mhz)
1187 bw_params->clk_table.entries[entry_idx].fclk_mhz = def_max.fclk_mhz;
1188 if (!bw_params->clk_table.entries[entry_idx].phyclk_mhz)
1189 bw_params->clk_table.entries[entry_idx].phyclk_mhz = def_max.phyclk_mhz;
1190 if (!bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz)
1191 bw_params->clk_table.entries[entry_idx].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
1192 if (!bw_params->clk_table.entries[entry_idx].dtbclk_mhz)
1193 bw_params->clk_table.entries[entry_idx].dtbclk_mhz = def_max.dtbclk_mhz;
1194 }
1195 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
1196 bw_params->vram_type = bios_info->memory_type;
1197 bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
1198 bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;
1199
1200 for (entry_idx = 0; entry_idx < (unsigned int)WM_SET_COUNT; entry_idx++) {
1201 bw_params->wm_table.entries[entry_idx].wm_inst = entry_idx;
1202
1203 if (entry_idx >= bw_params->clk_table.num_entries) {
1204 bw_params->wm_table.entries[entry_idx].valid = false;
1205 continue;
1206 }
1207
1208 bw_params->wm_table.entries[entry_idx].wm_type = WM_TYPE_PSTATE_CHG;
1209 bw_params->wm_table.entries[entry_idx].valid = true;
1210 }
1211 }
1212
dcn35_set_low_power_state(struct clk_mgr * clk_mgr_base)1213 static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base)
1214 {
1215 int display_count;
1216 struct dc *dc = clk_mgr_base->ctx->dc;
1217 struct dc_state *context = dc->current_state;
1218
1219 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
1220 display_count = dcn35_get_active_display_cnt_wa(dc, context, NULL);
1221 /* if we can go lower, go lower */
1222 if (display_count == 0)
1223 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
1224 }
1225 }
1226
dcn35_exit_low_power_state(struct clk_mgr * clk_mgr_base)1227 static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)
1228 {
1229 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1230
1231 //SMU optimization is performed part of low power state exit.
1232 dcn35_smu_exit_low_power_state(clk_mgr);
1233
1234 }
1235
dcn35_is_ips_supported(struct clk_mgr * clk_mgr_base)1236 static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base)
1237 {
1238 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1239
1240 return dcn35_smu_get_ips_supported(clk_mgr) ? true : false;
1241 }
1242
dcn35_init_clocks_fpga(struct clk_mgr * clk_mgr)1243 static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)
1244 {
1245 init_clk_states(clk_mgr);
1246
1247 /* TODO: Implement the functions and remove the ifndef guard */
1248 }
1249
dcn35_update_clocks_fpga(struct clk_mgr * clk_mgr,struct dc_state * context,bool safe_to_lower)1250 static void dcn35_update_clocks_fpga(struct clk_mgr *clk_mgr,
1251 struct dc_state *context,
1252 bool safe_to_lower)
1253 {
1254 struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
1255 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
1256 int fclk_adj = new_clocks->fclk_khz;
1257
1258 /* TODO: remove this after correctly set by DML */
1259 new_clocks->dcfclk_khz = 400000;
1260 new_clocks->socclk_khz = 400000;
1261
1262 /* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
1263 //int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
1264 new_clocks->fclk_khz = 4320000;
1265
1266 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
1267 clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
1268 }
1269
1270 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {
1271 clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;
1272 }
1273
1274 if (should_set_clock(safe_to_lower,
1275 new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
1276 clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
1277 }
1278
1279 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {
1280 clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;
1281 }
1282
1283 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {
1284 clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;
1285 }
1286
1287 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
1288 clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
1289 }
1290
1291 if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {
1292 clk_mgr->clks.fclk_khz = fclk_adj;
1293 }
1294
1295 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
1296 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
1297 }
1298
1299 /* Both fclk and ref_dppclk run on the same scemi clock.
1300 * So take the higher value since the DPP DTO is typically programmed
1301 * such that max dppclk is 1:1 with ref_dppclk.
1302 */
1303 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
1304 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
1305 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
1306 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
1307
1308 // Both fclk and ref_dppclk run on the same scemi clock.
1309 clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
1310
1311 /* TODO: set dtbclk in correct place */
1312 clk_mgr->clks.dtbclk_en = true;
1313 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
1314 dcn35_update_clocks_update_dpp_dto(clk_mgr_int, context, safe_to_lower);
1315
1316 dcn35_update_clocks_update_dtb_dto(clk_mgr_int, context, clk_mgr->clks.ref_dtbclk_khz);
1317 }
1318
dcn35_get_max_clock_khz(struct clk_mgr * clk_mgr_base,enum clk_type clk_type)1319 static unsigned int dcn35_get_max_clock_khz(struct clk_mgr *clk_mgr_base, enum clk_type clk_type)
1320 {
1321 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
1322
1323 unsigned int num_clk_levels;
1324
1325 switch (clk_type) {
1326 case CLK_TYPE_DISPCLK:
1327 num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;
1328 return num_clk_levels ?
1329 clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 :
1330 clk_mgr->base.boot_snapshot.dispclk;
1331 case CLK_TYPE_DPPCLK:
1332 num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dppclk_levels;
1333 return num_clk_levels ?
1334 clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dppclk_mhz * 1000 :
1335 clk_mgr->base.boot_snapshot.dppclk;
1336 case CLK_TYPE_DSCCLK:
1337 num_clk_levels = clk_mgr->base.bw_params->clk_table.num_entries_per_clk.num_dispclk_levels;
1338 return num_clk_levels ?
1339 clk_mgr->base.bw_params->clk_table.entries[num_clk_levels - 1].dispclk_mhz * 1000 / 3 :
1340 clk_mgr->base.boot_snapshot.dispclk / 3;
1341 default:
1342 break;
1343 }
1344
1345 return 0;
1346 }
1347
1348 static struct clk_mgr_funcs dcn35_funcs = {
1349 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1350 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
1351 .update_clocks = dcn35_update_clocks,
1352 .init_clocks = dcn35_init_clocks,
1353 .enable_pme_wa = dcn35_enable_pme_wa,
1354 .are_clock_states_equal = dcn35_are_clock_states_equal,
1355 .notify_wm_ranges = dcn35_notify_wm_ranges,
1356 .set_low_power_state = dcn35_set_low_power_state,
1357 .exit_low_power_state = dcn35_exit_low_power_state,
1358 .is_ips_supported = dcn35_is_ips_supported,
1359 .get_max_clock_khz = dcn35_get_max_clock_khz,
1360 };
1361
1362 struct clk_mgr_funcs dcn35_fpga_funcs = {
1363 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1364 .update_clocks = dcn35_update_clocks_fpga,
1365 .init_clocks = dcn35_init_clocks_fpga,
1366 .get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
1367 };
1368
translate_to_DpmClocks_t_dcn35(struct dcn351_smu_dpm_clks * smu_dpm_clks_a,struct dcn35_smu_dpm_clks * smu_dpm_clks_b)1369 static void translate_to_DpmClocks_t_dcn35(struct dcn351_smu_dpm_clks *smu_dpm_clks_a,
1370 struct dcn35_smu_dpm_clks *smu_dpm_clks_b)
1371 {
1372 /*translate two structures and only take need clock tables*/
1373 uint8_t i;
1374
1375 if (smu_dpm_clks_a == NULL || smu_dpm_clks_b == NULL ||
1376 smu_dpm_clks_a->dpm_clks == NULL || smu_dpm_clks_b->dpm_clks == NULL)
1377 return;
1378
1379 for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++)
1380 smu_dpm_clks_b->dpm_clks->DcfClocks[i] = smu_dpm_clks_a->dpm_clks->DcfClocks[i];
1381
1382 for (i = 0; i < NUM_DISPCLK_DPM_LEVELS; i++)
1383 smu_dpm_clks_b->dpm_clks->DispClocks[i] = smu_dpm_clks_a->dpm_clks->DispClocks[i];
1384
1385 for (i = 0; i < NUM_DPPCLK_DPM_LEVELS; i++)
1386 smu_dpm_clks_b->dpm_clks->DppClocks[i] = smu_dpm_clks_a->dpm_clks->DppClocks[i];
1387
1388 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
1389 smu_dpm_clks_b->dpm_clks->FclkClocks_Freq[i] = smu_dpm_clks_a->dpm_clks->FclkClocks_Freq[i];
1390 smu_dpm_clks_b->dpm_clks->FclkClocks_Voltage[i] = smu_dpm_clks_a->dpm_clks->FclkClocks_Voltage[i];
1391 }
1392 for (i = 0; i < NUM_MEM_PSTATE_LEVELS; i++) {
1393 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].MemClk =
1394 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].MemClk;
1395 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].UClk =
1396 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].UClk;
1397 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].Voltage =
1398 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].Voltage;
1399 smu_dpm_clks_b->dpm_clks->MemPstateTable[i].WckRatio =
1400 smu_dpm_clks_a->dpm_clks->MemPstateTable[i].WckRatio;
1401 }
1402 smu_dpm_clks_b->dpm_clks->MaxGfxClk = smu_dpm_clks_a->dpm_clks->MaxGfxClk;
1403 smu_dpm_clks_b->dpm_clks->MinGfxClk = smu_dpm_clks_a->dpm_clks->MinGfxClk;
1404 smu_dpm_clks_b->dpm_clks->NumDcfClkLevelsEnabled =
1405 smu_dpm_clks_a->dpm_clks->NumDcfClkLevelsEnabled;
1406 smu_dpm_clks_b->dpm_clks->NumDispClkLevelsEnabled =
1407 smu_dpm_clks_a->dpm_clks->NumDispClkLevelsEnabled;
1408 smu_dpm_clks_b->dpm_clks->NumFclkLevelsEnabled =
1409 smu_dpm_clks_a->dpm_clks->NumFclkLevelsEnabled;
1410 smu_dpm_clks_b->dpm_clks->NumMemPstatesEnabled =
1411 smu_dpm_clks_a->dpm_clks->NumMemPstatesEnabled;
1412 smu_dpm_clks_b->dpm_clks->NumSocClkLevelsEnabled =
1413 smu_dpm_clks_a->dpm_clks->NumSocClkLevelsEnabled;
1414
1415 for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
1416 smu_dpm_clks_b->dpm_clks->SocClocks[i] = smu_dpm_clks_a->dpm_clks->SocClocks[i];
1417 smu_dpm_clks_b->dpm_clks->SocVoltage[i] = smu_dpm_clks_a->dpm_clks->SocVoltage[i];
1418 }
1419 }
dcn35_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn35 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)1420 void dcn35_clk_mgr_construct(
1421 struct dc_context *ctx,
1422 struct clk_mgr_dcn35 *clk_mgr,
1423 struct pp_smu_funcs *pp_smu,
1424 struct dccg *dccg)
1425 {
1426 struct dcn35_smu_dpm_clks smu_dpm_clks = { 0 };
1427 struct dcn351_smu_dpm_clks smu_dpm_clks_dcn351 = { 0 };
1428 clk_mgr->base.base.ctx = ctx;
1429 clk_mgr->base.base.funcs = &dcn35_funcs;
1430
1431 clk_mgr->base.pp_smu = pp_smu;
1432
1433 clk_mgr->base.dccg = dccg;
1434 clk_mgr->base.dfs_bypass_disp_clk = 0;
1435
1436 clk_mgr->base.dprefclk_ss_percentage = 0;
1437 clk_mgr->base.dprefclk_ss_divider = 1000;
1438 clk_mgr->base.ss_on_dprefclk = false;
1439 clk_mgr->base.dfs_ref_freq_khz = 48000;
1440 if (ctx->dce_version != DCN_VERSION_3_51) {
1441 clk_mgr->base.regs = &clk_mgr_regs_dcn35;
1442 clk_mgr->base.clk_mgr_shift = &clk_mgr_shift_dcn35;
1443 clk_mgr->base.clk_mgr_mask = &clk_mgr_mask_dcn35;
1444 }
1445
1446
1447 clk_mgr->smu_wm_set.wm_set = (struct dcn35_watermarks *)dm_helpers_allocate_gpu_mem(
1448 clk_mgr->base.base.ctx,
1449 DC_MEM_ALLOC_TYPE_GART,
1450 sizeof(struct dcn35_watermarks),
1451 &clk_mgr->smu_wm_set.mc_address.quad_part);
1452
1453 if (!clk_mgr->smu_wm_set.wm_set) {
1454 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
1455 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
1456 }
1457 ASSERT(clk_mgr->smu_wm_set.wm_set);
1458
1459 smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn35 *)dm_helpers_allocate_gpu_mem(
1460 clk_mgr->base.base.ctx,
1461 DC_MEM_ALLOC_TYPE_GART,
1462 sizeof(DpmClocks_t_dcn35),
1463 &smu_dpm_clks.mc_address.quad_part);
1464 if (smu_dpm_clks.dpm_clks == NULL) {
1465 smu_dpm_clks.dpm_clks = &dummy_clocks;
1466 smu_dpm_clks.mc_address.quad_part = 0;
1467 }
1468 ASSERT(smu_dpm_clks.dpm_clks);
1469
1470 if (ctx->dce_version == DCN_VERSION_3_51) {
1471 smu_dpm_clks_dcn351.dpm_clks = (DpmClocks_t_dcn351 *)dm_helpers_allocate_gpu_mem(
1472 clk_mgr->base.base.ctx,
1473 DC_MEM_ALLOC_TYPE_GART,
1474 sizeof(DpmClocks_t_dcn351),
1475 &smu_dpm_clks_dcn351.mc_address.quad_part);
1476 if (smu_dpm_clks_dcn351.dpm_clks == NULL) {
1477 smu_dpm_clks_dcn351.dpm_clks = &dummy_clocks_dcn351;
1478 smu_dpm_clks_dcn351.mc_address.quad_part = 0;
1479 }
1480 }
1481
1482 clk_mgr->base.smu_ver = dcn35_smu_get_smu_version(&clk_mgr->base);
1483
1484 if (clk_mgr->base.smu_ver)
1485 clk_mgr->base.smu_present = true;
1486
1487 /* TODO: Check we get what we expect during bringup */
1488 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
1489
1490 if (ctx->dc_bios->integrated_info &&
1491 ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType)
1492 dcn35_bw_params.wm_table = lpddr5_wm_table;
1493 else
1494 dcn35_bw_params.wm_table = ddr5_wm_table;
1495
1496 /* Saved clocks configured at boot for debug purposes */
1497 dcn35_save_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr);
1498
1499 clk_mgr->base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&clk_mgr->base);
1500 clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
1501
1502 dce_clock_read_ss_info(&clk_mgr->base);
1503 /*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/
1504
1505 dcn35_read_ss_info_from_lut(&clk_mgr->base);
1506
1507 clk_mgr->base.base.bw_params = &dcn35_bw_params;
1508
1509 if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
1510 int i;
1511 if (ctx->dce_version == DCN_VERSION_3_51) {
1512 dcn351_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks_dcn351);
1513 translate_to_DpmClocks_t_dcn35(&smu_dpm_clks_dcn351, &smu_dpm_clks);
1514 } else
1515 dcn35_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
1516 DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
1517 "NumDispClkLevelsEnabled: %d\n"
1518 "NumSocClkLevelsEnabled: %d\n"
1519 "VcnClkLevelsEnabled: %d\n"
1520 "FClkLevelsEnabled: %d\n"
1521 "NumMemPstatesEnabled: %d\n"
1522 "MinGfxClk: %d\n"
1523 "MaxGfxClk: %d\n",
1524 smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
1525 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
1526 smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
1527 smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
1528 smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled,
1529 smu_dpm_clks.dpm_clks->NumMemPstatesEnabled,
1530 smu_dpm_clks.dpm_clks->MinGfxClk,
1531 smu_dpm_clks.dpm_clks->MaxGfxClk);
1532 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
1533 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
1534 i,
1535 smu_dpm_clks.dpm_clks->DcfClocks[i]);
1536 }
1537 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
1538 DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
1539 i, smu_dpm_clks.dpm_clks->DispClocks[i]);
1540 }
1541 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
1542 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
1543 i, smu_dpm_clks.dpm_clks->SocClocks[i]);
1544 }
1545 for (i = 0; i < smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled; i++) {
1546 DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Freq[%d] = %d\n",
1547 i, smu_dpm_clks.dpm_clks->FclkClocks_Freq[i]);
1548 DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Voltage[%d] = %d\n",
1549 i, smu_dpm_clks.dpm_clks->FclkClocks_Voltage[i]);
1550 }
1551 for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++)
1552 DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
1553 i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
1554
1555 for (i = 0; i < smu_dpm_clks.dpm_clks->NumMemPstatesEnabled; i++) {
1556 DC_LOG_SMU("smu_dpm_clks.dpm_clks.MemPstateTable[%d].UClk = %d\n"
1557 "smu_dpm_clks.dpm_clks->MemPstateTable[%d].MemClk= %d\n"
1558 "smu_dpm_clks.dpm_clks->MemPstateTable[%d].Voltage = %d\n",
1559 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].UClk,
1560 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].MemClk,
1561 i, smu_dpm_clks.dpm_clks->MemPstateTable[i].Voltage);
1562 }
1563
1564 if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
1565 dcn35_clk_mgr_helper_populate_bw_params(
1566 &clk_mgr->base,
1567 ctx->dc_bios->integrated_info,
1568 smu_dpm_clks.dpm_clks);
1569 }
1570 }
1571
1572 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
1573 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_GART,
1574 smu_dpm_clks.dpm_clks);
1575
1576 if (smu_dpm_clks_dcn351.dpm_clks && smu_dpm_clks_dcn351.mc_address.quad_part != 0)
1577 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_GART,
1578 smu_dpm_clks_dcn351.dpm_clks);
1579
1580 if (ctx->dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) {
1581 bool ips_support = false;
1582
1583 /*avoid call pmfw at init*/
1584 ips_support = dcn35_smu_get_ips_supported(&clk_mgr->base);
1585 if (ips_support) {
1586 ctx->dc->debug.ignore_pg = false;
1587 ctx->dc->debug.disable_dpp_power_gate = false;
1588 ctx->dc->debug.disable_hubp_power_gate = false;
1589 ctx->dc->debug.disable_dsc_power_gate = false;
1590
1591 /* Disable dynamic IPS2 in older PMFW (93.12) for Z8 interop. */
1592 if (ctx->dc->config.disable_ips == DMUB_IPS_ENABLE &&
1593 ctx->dce_version != DCN_VERSION_3_51 &&
1594 ((clk_mgr->base.smu_ver & 0x00FFFFFF) <= 0x005d0c00))
1595 ctx->dc->config.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
1596 } else {
1597 /*let's reset the config control flag*/
1598 ctx->dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/
1599 }
1600 }
1601 }
1602
dcn35_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)1603 void dcn35_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
1604 {
1605 struct clk_mgr_dcn35 *clk_mgr = TO_CLK_MGR_DCN35(clk_mgr_int);
1606
1607 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
1608 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
1609 clk_mgr->smu_wm_set.wm_set);
1610 }
1611