xref: /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c (revision 3fd6c59042dbba50391e30862beac979491145fe)
1 /*
2  * Copyright 2022 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 
27 #include "dcn35_clk_mgr.h"
28 
29 #include "dccg.h"
30 #include "clk_mgr_internal.h"
31 
32 // For dce12_get_dp_ref_freq_khz
33 #include "dce100/dce_clk_mgr.h"
34 
35 // For dcn20_update_clocks_update_dpp_dto
36 #include "dcn20/dcn20_clk_mgr.h"
37 
38 
39 
40 
41 #include "reg_helper.h"
42 #include "core_types.h"
43 #include "dcn35_smu.h"
44 #include "dm_helpers.h"
45 
46 /* TODO: remove this include once we ported over remaining clk mgr functions*/
47 #include "dcn30/dcn30_clk_mgr.h"
48 #include "dcn31/dcn31_clk_mgr.h"
49 
50 #include "dc_dmub_srv.h"
51 #include "link.h"
52 #include "logger_types.h"
53 
54 #undef DC_LOGGER
55 #define DC_LOGGER \
56 	clk_mgr->base.base.ctx->logger
57 
58 
59 #define regCLK1_CLK_PLL_REQ			0x0237
60 #define regCLK1_CLK_PLL_REQ_BASE_IDX		0
61 
62 #define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT	0x0
63 #define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT	0xc
64 #define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT	0x10
65 #define CLK1_CLK_PLL_REQ__FbMult_int_MASK	0x000001FFL
66 #define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK	0x0000F000L
67 #define CLK1_CLK_PLL_REQ__FbMult_frac_MASK	0xFFFF0000L
68 
69 #define regCLK1_CLK2_BYPASS_CNTL			0x029c
70 #define regCLK1_CLK2_BYPASS_CNTL_BASE_IDX	0
71 
72 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL__SHIFT	0x0
73 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV__SHIFT	0x10
74 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK		0x00000007L
75 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK		0x000F0000L
76 
77 #define regCLK5_0_CLK5_spll_field_8				0x464b
78 #define regCLK5_0_CLK5_spll_field_8_BASE_IDX	0
79 
80 #define CLK5_0_CLK5_spll_field_8__spll_ssc_en__SHIFT	0xd
81 #define CLK5_0_CLK5_spll_field_8__spll_ssc_en_MASK		0x00002000L
82 
83 #define SMU_VER_THRESHOLD 0x5D4A00 //93.74.0
84 
85 #define REG(reg_name) \
86 	(ctx->clk_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
87 
88 #define TO_CLK_MGR_DCN35(clk_mgr)\
89 	container_of(clk_mgr, struct clk_mgr_dcn35, base)
90 
dcn35_get_active_display_cnt_wa(struct dc * dc,struct dc_state * context,int * all_active_disps)91 static int dcn35_get_active_display_cnt_wa(
92 		struct dc *dc,
93 		struct dc_state *context,
94 		int *all_active_disps)
95 {
96 	int i, display_count = 0;
97 	bool tmds_present = false;
98 
99 	for (i = 0; i < context->stream_count; i++) {
100 		const struct dc_stream_state *stream = context->streams[i];
101 
102 		if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
103 				stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
104 				stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
105 			tmds_present = true;
106 	}
107 
108 	for (i = 0; i < dc->link_count; i++) {
109 		const struct dc_link *link = dc->links[i];
110 
111 		/* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
112 		if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
113 				link->link_enc->funcs->is_dig_enabled(link->link_enc))
114 			display_count++;
115 	}
116 	if (all_active_disps != NULL)
117 		*all_active_disps = display_count;
118 	/* WA for hang on HDMI after display off back on*/
119 	if (display_count == 0 && tmds_present)
120 		display_count = 1;
121 
122 	return display_count;
123 }
dcn35_disable_otg_wa(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower,bool disable)124 static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context,
125 		bool safe_to_lower, bool disable)
126 {
127 	struct dc *dc = clk_mgr_base->ctx->dc;
128 	int i;
129 
130 	if (dc->ctx->dce_environment == DCE_ENV_DIAG)
131 		return;
132 
133 	for (i = 0; i < dc->res_pool->pipe_count; ++i) {
134 		struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
135 		struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i];
136 		struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base);
137 		struct dccg *dccg = clk_mgr_internal->dccg;
138 		struct pipe_ctx *pipe = safe_to_lower
139 			? &context->res_ctx.pipe_ctx[i]
140 			: &dc->current_state->res_ctx.pipe_ctx[i];
141 		bool stream_changed_otg_dig_on = false;
142 		if (pipe->top_pipe || pipe->prev_odm_pipe)
143 			continue;
144 		stream_changed_otg_dig_on = old_pipe->stream && new_pipe->stream &&
145 		old_pipe->stream != new_pipe->stream &&
146 		old_pipe->stream_res.tg == new_pipe->stream_res.tg &&
147 		new_pipe->stream->link_enc && !new_pipe->stream->dpms_off &&
148 		new_pipe->stream->link_enc->funcs->is_dig_enabled &&
149 		new_pipe->stream->link_enc->funcs->is_dig_enabled(
150 		new_pipe->stream->link_enc) &&
151 		new_pipe->stream_res.stream_enc &&
152 		new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled &&
153 		new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled(new_pipe->stream_res.stream_enc);
154 
155 		bool has_active_hpo = false;
156 
157 		if (old_pipe->stream && new_pipe->stream && old_pipe->stream == new_pipe->stream) {
158 			has_active_hpo =  dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) &&
159 			dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe);
160 
161 		 }
162 
163 
164 		if (!has_active_hpo && !dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe) &&
165 					(pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) ||
166 					!pipe->stream->link_enc) && !stream_changed_otg_dig_on)) {
167 
168 
169 			/* This w/a should not trigger when we have a dig active */
170 			if (disable) {
171 				if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc)
172 					pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
173 
174 				reset_sync_context_for_pipe(dc, context, i);
175 			} else {
176 				pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
177 			}
178 		}
179 	}
180 }
181 
dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,int ref_dtbclk_khz)182 static void dcn35_update_clocks_update_dtb_dto(struct clk_mgr_internal *clk_mgr,
183 			struct dc_state *context,
184 			int ref_dtbclk_khz)
185 {
186 	struct dccg *dccg = clk_mgr->dccg;
187 	uint32_t tg_mask = 0;
188 	int i;
189 
190 	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
191 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
192 		struct dtbclk_dto_params dto_params = {0};
193 
194 		/* use mask to program DTO once per tg */
195 		if (pipe_ctx->stream_res.tg &&
196 				!(tg_mask & (1 << pipe_ctx->stream_res.tg->inst))) {
197 			tg_mask |= (1 << pipe_ctx->stream_res.tg->inst);
198 
199 			dto_params.otg_inst = pipe_ctx->stream_res.tg->inst;
200 			dto_params.ref_dtbclk_khz = ref_dtbclk_khz;
201 
202 			dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params);
203 			//dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params);
204 		}
205 	}
206 }
207 
dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal * clk_mgr,struct dc_state * context,bool safe_to_lower)208 static void dcn35_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr,
209 		struct dc_state *context, bool safe_to_lower)
210 {
211 	int i;
212 	bool dppclk_active[MAX_PIPES] = {0};
213 
214 
215 	clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz;
216 	for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
217 		int dpp_inst = 0, dppclk_khz, prev_dppclk_khz;
218 
219 		dppclk_khz = context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz;
220 
221 		if (context->res_ctx.pipe_ctx[i].plane_res.dpp)
222 			dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
223 		else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz == 0) {
224 			/* dpp == NULL && dppclk_khz == 0 is valid because of pipe harvesting.
225 			 * In this case just continue in loop
226 			 */
227 			continue;
228 		} else if (!context->res_ctx.pipe_ctx[i].plane_res.dpp && dppclk_khz > 0) {
229 			/* The software state is not valid if dpp resource is NULL and
230 			 * dppclk_khz > 0.
231 			 */
232 			ASSERT(false);
233 			continue;
234 		}
235 
236 		prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i];
237 
238 		if (safe_to_lower || prev_dppclk_khz < dppclk_khz)
239 			clk_mgr->dccg->funcs->update_dpp_dto(
240 							clk_mgr->dccg, dpp_inst, dppclk_khz);
241 		dppclk_active[dpp_inst] = true;
242 	}
243 	if (safe_to_lower)
244 		for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
245 			struct dpp *old_dpp = clk_mgr->base.ctx->dc->current_state->res_ctx.pipe_ctx[i].plane_res.dpp;
246 
247 			if (old_dpp && !dppclk_active[old_dpp->inst])
248 				clk_mgr->dccg->funcs->update_dpp_dto(clk_mgr->dccg, old_dpp->inst, 0);
249 		}
250 }
251 
get_lowest_dpia_index(const struct dc_link * link)252 static uint8_t get_lowest_dpia_index(const struct dc_link *link)
253 {
254 	const struct dc *dc_struct = link->dc;
255 	uint8_t idx = 0xFF;
256 	int i;
257 
258 	for (i = 0; i < MAX_PIPES * 2; ++i) {
259 		if (!dc_struct->links[i] || dc_struct->links[i]->ep_type != DISPLAY_ENDPOINT_USB4_DPIA)
260 			continue;
261 
262 		if (idx > dc_struct->links[i]->link_index)
263 			idx = dc_struct->links[i]->link_index;
264 	}
265 
266 	return idx;
267 }
268 
dcn35_notify_host_router_bw(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)269 static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_state *context,
270 					bool safe_to_lower)
271 {
272 	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
273 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
274 	uint32_t host_router_bw_kbps[MAX_HOST_ROUTERS_NUM] = { 0 };
275 	int i;
276 	for (i = 0; i < context->stream_count; ++i) {
277 		const struct dc_stream_state *stream = context->streams[i];
278 		const struct dc_link *link = stream->link;
279 		uint8_t lowest_dpia_index = 0;
280 		unsigned int hr_index = 0;
281 
282 		if (!link)
283 			continue;
284 
285 		lowest_dpia_index = get_lowest_dpia_index(link);
286 		if (link->link_index < lowest_dpia_index)
287 			continue;
288 
289 		hr_index = (link->link_index - lowest_dpia_index) / 2;
290 		if (hr_index >= MAX_HOST_ROUTERS_NUM)
291 			continue;
292 		host_router_bw_kbps[hr_index] += dc_bandwidth_in_kbps_from_timing(
293 			&stream->timing, dc_link_get_highest_encoding_format(link));
294 	}
295 
296 	for (i = 0; i < MAX_HOST_ROUTERS_NUM; ++i) {
297 		new_clocks->host_router_bw_kbps[i] = host_router_bw_kbps[i];
298 		if (should_set_clock(safe_to_lower, new_clocks->host_router_bw_kbps[i], clk_mgr_base->clks.host_router_bw_kbps[i])) {
299 			clk_mgr_base->clks.host_router_bw_kbps[i] = new_clocks->host_router_bw_kbps[i];
300 			dcn35_smu_notify_host_router_bw(clk_mgr, i, new_clocks->host_router_bw_kbps[i]);
301 		}
302 	}
303 }
304 
dcn35_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)305 void dcn35_update_clocks(struct clk_mgr *clk_mgr_base,
306 			struct dc_state *context,
307 			bool safe_to_lower)
308 {
309 	union dmub_rb_cmd cmd;
310 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
311 	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
312 	struct dc *dc = clk_mgr_base->ctx->dc;
313 	int display_count = 0;
314 	bool update_dppclk = false;
315 	bool update_dispclk = false;
316 	bool dpp_clock_lowered = false;
317 	int all_active_disps = 0;
318 
319 	if (dc->work_arounds.skip_clock_update)
320 		return;
321 
322 	display_count = dcn35_get_active_display_cnt_wa(dc, context, &all_active_disps);
323 	if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz)
324 		new_clocks->ref_dtbclk_khz = 600000;
325 
326 	/*
327 	 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
328 	 * also if safe to lower is false, we just go in the higher state
329 	 */
330 	if (safe_to_lower) {
331 		if (new_clocks->zstate_support != DCN_ZSTATE_SUPPORT_DISALLOW &&
332 				new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
333 			dcn35_smu_set_zstate_support(clk_mgr, new_clocks->zstate_support);
334 			dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, true);
335 			clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
336 		}
337 
338 		if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
339 			if (clk_mgr->base.ctx->dc->config.allow_0_dtb_clk)
340 				dcn35_smu_set_dtbclk(clk_mgr, false);
341 			clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
342 		}
343 		/* check that we're not already in lower */
344 		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
345 			/* if we can go lower, go lower */
346 			if (display_count == 0)
347 				clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
348 		}
349 	} else {
350 		if (new_clocks->zstate_support == DCN_ZSTATE_SUPPORT_DISALLOW &&
351 				new_clocks->zstate_support != clk_mgr_base->clks.zstate_support) {
352 			dcn35_smu_set_zstate_support(clk_mgr, DCN_ZSTATE_SUPPORT_DISALLOW);
353 			dm_helpers_enable_periodic_detection(clk_mgr_base->ctx, false);
354 			clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
355 		}
356 
357 		if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
358 			dcn35_smu_set_dtbclk(clk_mgr, true);
359 			clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
360 
361 			dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
362 			clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
363 		}
364 
365 		/* check that we're not already in D0 */
366 		if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
367 			union display_idle_optimization_u idle_info = { 0 };
368 
369 			dcn35_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
370 			/* update power state */
371 			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
372 		}
373 	}
374 	if (dc->debug.force_min_dcfclk_mhz > 0)
375 		new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
376 				new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
377 
378 	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
379 		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
380 		dcn35_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
381 	}
382 
383 	if (should_set_clock(safe_to_lower,
384 			new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
385 		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
386 		dcn35_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
387 	}
388 
389 	// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
390 	if (new_clocks->dppclk_khz < 100000)
391 		new_clocks->dppclk_khz = 100000;
392 
393 	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
394 		if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
395 			dpp_clock_lowered = true;
396 		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
397 		update_dppclk = true;
398 	}
399 
400 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
401 		dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true);
402 
403 		if (dc->debug.min_disp_clk_khz > 0 && new_clocks->dispclk_khz < dc->debug.min_disp_clk_khz)
404 			new_clocks->dispclk_khz = dc->debug.min_disp_clk_khz;
405 
406 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
407 		dcn35_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
408 		dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false);
409 
410 		update_dispclk = true;
411 	}
412 
413 	/* clock limits are received with MHz precision, divide by 1000 to prevent setting clocks at every call */
414 	if (!dc->debug.disable_dtb_ref_clk_switch &&
415 	    should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000,
416 			     clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
417 		dcn35_update_clocks_update_dtb_dto(clk_mgr, context, new_clocks->ref_dtbclk_khz);
418 		clk_mgr_base->clks.ref_dtbclk_khz = new_clocks->ref_dtbclk_khz;
419 	}
420 
421 	if (dpp_clock_lowered) {
422 		// increase per DPP DTO before lowering global dppclk
423 		dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
424 		dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
425 	} else {
426 		// increase global DPPCLK before lowering per DPP DTO
427 		if (update_dppclk || update_dispclk)
428 			dcn35_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
429 		dcn35_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
430 	}
431 
432 	// notify PMFW of bandwidth per DPIA tunnel
433 	if (dc->debug.notify_dpia_hr_bw)
434 		dcn35_notify_host_router_bw(clk_mgr_base, context, safe_to_lower);
435 
436 	// notify DMCUB of latest clocks
437 	memset(&cmd, 0, sizeof(cmd));
438 	cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
439 	cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
440 	cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
441 	cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
442 		clk_mgr_base->clks.dcfclk_deep_sleep_khz;
443 	cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
444 	cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
445 
446 	dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
447 }
448 
get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)449 static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
450 {
451 	/* get FbMult value */
452 	struct fixed31_32 pll_req;
453 	unsigned int fbmult_frac_val = 0;
454 	unsigned int fbmult_int_val = 0;
455 	struct dc_context *ctx = clk_mgr->base.ctx;
456 
457 	/*
458 	 * Register value of fbmult is in 8.16 format, we are converting to 314.32
459 	 * to leverage the fix point operations available in driver
460 	 */
461 
462 	REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
463 	REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
464 
465 	pll_req = dc_fixpt_from_int(fbmult_int_val);
466 
467 	/*
468 	 * since fractional part is only 16 bit in register definition but is 32 bit
469 	 * in our fix point definiton, need to shift left by 16 to obtain correct value
470 	 */
471 	pll_req.value |= fbmult_frac_val << 16;
472 
473 	/* multiply by REFCLK period */
474 	pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
475 
476 	/* integer part is now VCO frequency in kHz */
477 	return dc_fixpt_floor(pll_req);
478 }
479 
dcn35_enable_pme_wa(struct clk_mgr * clk_mgr_base)480 static void dcn35_enable_pme_wa(struct clk_mgr *clk_mgr_base)
481 {
482 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
483 
484 	dcn35_smu_enable_pme_wa(clk_mgr);
485 }
486 
487 
dcn35_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)488 bool dcn35_are_clock_states_equal(struct dc_clocks *a,
489 		struct dc_clocks *b)
490 {
491 	if (a->dispclk_khz != b->dispclk_khz)
492 		return false;
493 	else if (a->dppclk_khz != b->dppclk_khz)
494 		return false;
495 	else if (a->dcfclk_khz != b->dcfclk_khz)
496 		return false;
497 	else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
498 		return false;
499 	else if (a->zstate_support != b->zstate_support)
500 		return false;
501 	else if (a->dtbclk_en != b->dtbclk_en)
502 		return false;
503 
504 	return true;
505 }
506 
dcn35_dump_clk_registers(struct clk_state_registers_and_bypass * regs_and_bypass,struct clk_mgr_dcn35 * clk_mgr)507 static void dcn35_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
508 		struct clk_mgr_dcn35 *clk_mgr)
509 {
510 }
511 
dcn35_is_spll_ssc_enabled(struct clk_mgr * clk_mgr_base)512 static bool dcn35_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base)
513 {
514 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
515 	struct dc_context *ctx = clk_mgr->base.ctx;
516 	uint32_t ssc_enable;
517 
518 	REG_GET(CLK5_0_CLK5_spll_field_8, spll_ssc_en, &ssc_enable);
519 
520 	return ssc_enable == 1;
521 }
522 
init_clk_states(struct clk_mgr * clk_mgr)523 static void init_clk_states(struct clk_mgr *clk_mgr)
524 {
525 	struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
526 	uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;
527 	memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
528 
529 	if (clk_mgr_int->smu_ver >= SMU_VER_THRESHOLD)
530 		clk_mgr->clks.dtbclk_en = true; // request DTBCLK disable on first commit
531 	clk_mgr->clks.ref_dtbclk_khz = ref_dtbclk;	// restore ref_dtbclk
532 	clk_mgr->clks.p_state_change_support = true;
533 	clk_mgr->clks.prev_p_state_change_support = true;
534 	clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
535 	clk_mgr->clks.zstate_support = DCN_ZSTATE_SUPPORT_UNKNOWN;
536 }
537 
dcn35_init_clocks(struct clk_mgr * clk_mgr)538 void dcn35_init_clocks(struct clk_mgr *clk_mgr)
539 {
540 	struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
541 	init_clk_states(clk_mgr);
542 
543 	// to adjust dp_dto reference clock if ssc is enable otherwise to apply dprefclk
544 	if (dcn35_is_spll_ssc_enabled(clk_mgr))
545 		clk_mgr->dp_dto_source_clock_in_khz =
546 			dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr->dprefclk_khz);
547 	else
548 		clk_mgr->dp_dto_source_clock_in_khz = clk_mgr->dprefclk_khz;
549 
550 }
551 static struct clk_bw_params dcn35_bw_params = {
552 	.vram_type = Ddr4MemType,
553 	.num_channels = 1,
554 	.clk_table = {
555 		.num_entries = 4,
556 	},
557 
558 };
559 
560 static struct wm_table ddr5_wm_table = {
561 	.entries = {
562 		{
563 			.wm_inst = WM_A,
564 			.wm_type = WM_TYPE_PSTATE_CHG,
565 			.pstate_latency_us = 11.72,
566 			.sr_exit_time_us = 28.0,
567 			.sr_enter_plus_exit_time_us = 30.0,
568 			.valid = true,
569 		},
570 		{
571 			.wm_inst = WM_B,
572 			.wm_type = WM_TYPE_PSTATE_CHG,
573 			.pstate_latency_us = 11.72,
574 			.sr_exit_time_us = 28.0,
575 			.sr_enter_plus_exit_time_us = 30.0,
576 			.valid = true,
577 		},
578 		{
579 			.wm_inst = WM_C,
580 			.wm_type = WM_TYPE_PSTATE_CHG,
581 			.pstate_latency_us = 11.72,
582 			.sr_exit_time_us = 28.0,
583 			.sr_enter_plus_exit_time_us = 30.0,
584 			.valid = true,
585 		},
586 		{
587 			.wm_inst = WM_D,
588 			.wm_type = WM_TYPE_PSTATE_CHG,
589 			.pstate_latency_us = 11.72,
590 			.sr_exit_time_us = 28.0,
591 			.sr_enter_plus_exit_time_us = 30.0,
592 			.valid = true,
593 		},
594 	}
595 };
596 
597 static struct wm_table lpddr5_wm_table = {
598 	.entries = {
599 		{
600 			.wm_inst = WM_A,
601 			.wm_type = WM_TYPE_PSTATE_CHG,
602 			.pstate_latency_us = 11.65333,
603 			.sr_exit_time_us = 28.0,
604 			.sr_enter_plus_exit_time_us = 30.0,
605 			.valid = true,
606 		},
607 		{
608 			.wm_inst = WM_B,
609 			.wm_type = WM_TYPE_PSTATE_CHG,
610 			.pstate_latency_us = 11.65333,
611 			.sr_exit_time_us = 28.0,
612 			.sr_enter_plus_exit_time_us = 30.0,
613 			.valid = true,
614 		},
615 		{
616 			.wm_inst = WM_C,
617 			.wm_type = WM_TYPE_PSTATE_CHG,
618 			.pstate_latency_us = 11.65333,
619 			.sr_exit_time_us = 28.0,
620 			.sr_enter_plus_exit_time_us = 30.0,
621 			.valid = true,
622 		},
623 		{
624 			.wm_inst = WM_D,
625 			.wm_type = WM_TYPE_PSTATE_CHG,
626 			.pstate_latency_us = 11.65333,
627 			.sr_exit_time_us = 28.0,
628 			.sr_enter_plus_exit_time_us = 30.0,
629 			.valid = true,
630 		},
631 	}
632 };
633 
634 static DpmClocks_t_dcn35 dummy_clocks;
635 
636 static struct dcn35_watermarks dummy_wms = { 0 };
637 
638 static struct dcn35_ss_info_table ss_info_table = {
639 	.ss_divider = 1000,
640 	.ss_percentage = {0, 0, 375, 375, 375}
641 };
642 
dcn35_read_ss_info_from_lut(struct clk_mgr_internal * clk_mgr)643 static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)
644 {
645 	struct dc_context *ctx = clk_mgr->base.ctx;
646 	uint32_t clock_source;
647 
648 	REG_GET(CLK1_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL, &clock_source);
649 	// If it's DFS mode, clock_source is 0.
650 	if (dcn35_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(ss_info_table.ss_percentage))) {
651 		clk_mgr->dprefclk_ss_percentage = ss_info_table.ss_percentage[clock_source];
652 
653 		if (clk_mgr->dprefclk_ss_percentage != 0) {
654 			clk_mgr->ss_on_dprefclk = true;
655 			clk_mgr->dprefclk_ss_divider = ss_info_table.ss_divider;
656 		}
657 	}
658 }
659 
dcn35_build_watermark_ranges(struct clk_bw_params * bw_params,struct dcn35_watermarks * table)660 static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table)
661 {
662 	int i, num_valid_sets;
663 
664 	num_valid_sets = 0;
665 
666 	for (i = 0; i < WM_SET_COUNT; i++) {
667 		/* skip empty entries, the smu array has no holes*/
668 		if (!bw_params->wm_table.entries[i].valid)
669 			continue;
670 
671 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
672 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
673 		/* We will not select WM based on fclk, so leave it as unconstrained */
674 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
675 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
676 
677 		if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
678 			if (i == 0)
679 				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
680 			else {
681 				/* add 1 to make it non-overlapping with next lvl */
682 				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
683 						bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
684 			}
685 			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
686 					bw_params->clk_table.entries[i].dcfclk_mhz;
687 
688 		} else {
689 			/* unconstrained for memory retraining */
690 			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
691 			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
692 
693 			/* Modify previous watermark range to cover up to max */
694 			table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
695 		}
696 		num_valid_sets++;
697 	}
698 
699 	ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
700 
701 	/* modify the min and max to make sure we cover the whole range*/
702 	table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
703 	table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
704 	table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
705 	table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
706 
707 	/* This is for writeback only, does not matter currently as no writeback support*/
708 	table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
709 	table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
710 	table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
711 	table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
712 	table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
713 }
714 
dcn35_notify_wm_ranges(struct clk_mgr * clk_mgr_base)715 static void dcn35_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
716 {
717 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
718 	struct clk_mgr_dcn35 *clk_mgr_dcn35 = TO_CLK_MGR_DCN35(clk_mgr);
719 	struct dcn35_watermarks *table = clk_mgr_dcn35->smu_wm_set.wm_set;
720 
721 	if (!clk_mgr->smu_ver)
722 		return;
723 
724 	if (!table || clk_mgr_dcn35->smu_wm_set.mc_address.quad_part == 0)
725 		return;
726 
727 	memset(table, 0, sizeof(*table));
728 
729 	dcn35_build_watermark_ranges(clk_mgr_base->bw_params, table);
730 
731 	dcn35_smu_set_dram_addr_high(clk_mgr,
732 			clk_mgr_dcn35->smu_wm_set.mc_address.high_part);
733 	dcn35_smu_set_dram_addr_low(clk_mgr,
734 			clk_mgr_dcn35->smu_wm_set.mc_address.low_part);
735 	dcn35_smu_transfer_wm_table_dram_2_smu(clk_mgr);
736 }
737 
dcn35_get_dpm_table_from_smu(struct clk_mgr_internal * clk_mgr,struct dcn35_smu_dpm_clks * smu_dpm_clks)738 static void dcn35_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
739 		struct dcn35_smu_dpm_clks *smu_dpm_clks)
740 {
741 	DpmClocks_t_dcn35 *table = smu_dpm_clks->dpm_clks;
742 
743 	if (!clk_mgr->smu_ver)
744 		return;
745 
746 	if (!table || smu_dpm_clks->mc_address.quad_part == 0)
747 		return;
748 
749 	memset(table, 0, sizeof(*table));
750 
751 	dcn35_smu_set_dram_addr_high(clk_mgr,
752 			smu_dpm_clks->mc_address.high_part);
753 	dcn35_smu_set_dram_addr_low(clk_mgr,
754 			smu_dpm_clks->mc_address.low_part);
755 	dcn35_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
756 }
757 
find_max_clk_value(const uint32_t clocks[],uint32_t num_clocks)758 static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
759 {
760 	uint32_t max = 0;
761 	int i;
762 
763 	for (i = 0; i < num_clocks; ++i) {
764 		if (clocks[i] > max)
765 			max = clocks[i];
766 	}
767 
768 	return max;
769 }
770 
is_valid_clock_value(uint32_t clock_value)771 static inline bool is_valid_clock_value(uint32_t clock_value)
772 {
773 	return clock_value > 1 && clock_value < 100000;
774 }
775 
convert_wck_ratio(uint8_t wck_ratio)776 static unsigned int convert_wck_ratio(uint8_t wck_ratio)
777 {
778 	switch (wck_ratio) {
779 	case WCK_RATIO_1_2:
780 		return 2;
781 
782 	case WCK_RATIO_1_4:
783 		return 4;
784 	/* Find lowest DPM, FCLK is filled in reverse order*/
785 
786 	default:
787 			break;
788 	}
789 
790 	return 1;
791 }
792 
calc_dram_speed_mts(const MemPstateTable_t * entry)793 static inline uint32_t calc_dram_speed_mts(const MemPstateTable_t *entry)
794 {
795 	return entry->UClk * convert_wck_ratio(entry->WckRatio) * 2;
796 }
797 
dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal * clk_mgr,struct integrated_info * bios_info,DpmClocks_t_dcn35 * clock_table)798 static void dcn35_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk_mgr,
799 						    struct integrated_info *bios_info,
800 						    DpmClocks_t_dcn35 *clock_table)
801 {
802 	struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
803 	struct clk_limit_table_entry def_max = bw_params->clk_table.entries[bw_params->clk_table.num_entries - 1];
804 	uint32_t max_fclk = 0, min_pstate = 0, max_dispclk = 0, max_dppclk = 0;
805 	uint32_t max_pstate = 0, max_dram_speed_mts = 0, min_dram_speed_mts = 0;
806 	uint32_t num_memps, num_fclk, num_dcfclk;
807 	int i;
808 
809 	/* Determine min/max p-state values. */
810 	num_memps = (clock_table->NumMemPstatesEnabled > NUM_MEM_PSTATE_LEVELS) ? NUM_MEM_PSTATE_LEVELS :
811 		clock_table->NumMemPstatesEnabled;
812 	for (i = 0; i < num_memps; i++) {
813 		uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
814 
815 		if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts > max_dram_speed_mts) {
816 			max_dram_speed_mts = dram_speed_mts;
817 			max_pstate = i;
818 		}
819 	}
820 
821 	min_dram_speed_mts = max_dram_speed_mts;
822 	min_pstate = max_pstate;
823 
824 	for (i = 0; i < num_memps; i++) {
825 		uint32_t dram_speed_mts = calc_dram_speed_mts(&clock_table->MemPstateTable[i]);
826 
827 		if (is_valid_clock_value(dram_speed_mts) && dram_speed_mts < min_dram_speed_mts) {
828 			min_dram_speed_mts = dram_speed_mts;
829 			min_pstate = i;
830 		}
831 	}
832 
833 	/* We expect the table to contain at least one valid P-state entry. */
834 	ASSERT(clock_table->NumMemPstatesEnabled &&
835 	       is_valid_clock_value(max_dram_speed_mts) &&
836 	       is_valid_clock_value(min_dram_speed_mts));
837 
838 	/* dispclk and dppclk can be max at any voltage, same number of levels for both */
839 	if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
840 	    clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
841 		max_dispclk = find_max_clk_value(clock_table->DispClocks,
842 			clock_table->NumDispClkLevelsEnabled);
843 		max_dppclk = find_max_clk_value(clock_table->DppClocks,
844 			clock_table->NumDispClkLevelsEnabled);
845 	} else {
846 		/* Invalid number of entries in the table from PMFW. */
847 		ASSERT(0);
848 	}
849 
850 	/* Base the clock table on dcfclk, need at least one entry regardless of pmfw table */
851 	ASSERT(clock_table->NumDcfClkLevelsEnabled > 0);
852 
853 	num_fclk = (clock_table->NumFclkLevelsEnabled > NUM_FCLK_DPM_LEVELS) ? NUM_FCLK_DPM_LEVELS :
854 		clock_table->NumFclkLevelsEnabled;
855 	max_fclk = find_max_clk_value(clock_table->FclkClocks_Freq, num_fclk);
856 
857 	num_dcfclk = (clock_table->NumDcfClkLevelsEnabled > NUM_DCFCLK_DPM_LEVELS) ? NUM_DCFCLK_DPM_LEVELS :
858 		clock_table->NumDcfClkLevelsEnabled;
859 	for (i = 0; i < num_dcfclk; i++) {
860 		int j;
861 
862 		/* First search defaults for the clocks we don't read using closest lower or equal default dcfclk */
863 		for (j = bw_params->clk_table.num_entries - 1; j > 0; j--)
864 			if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
865 				break;
866 
867 		bw_params->clk_table.entries[i].phyclk_mhz = bw_params->clk_table.entries[j].phyclk_mhz;
868 		bw_params->clk_table.entries[i].phyclk_d18_mhz = bw_params->clk_table.entries[j].phyclk_d18_mhz;
869 		bw_params->clk_table.entries[i].dtbclk_mhz = bw_params->clk_table.entries[j].dtbclk_mhz;
870 
871 		/* Now update clocks we do read */
872 		bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[min_pstate].MemClk;
873 		bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[min_pstate].Voltage;
874 		bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
875 		bw_params->clk_table.entries[i].socclk_mhz = clock_table->SocClocks[i];
876 		bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
877 		bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
878 		bw_params->clk_table.entries[i].wck_ratio =
879 			convert_wck_ratio(clock_table->MemPstateTable[min_pstate].WckRatio);
880 
881 		/* Dcfclk and Fclk are tied, but at a different ratio */
882 		bw_params->clk_table.entries[i].fclk_mhz = min(max_fclk, 2 * clock_table->DcfClocks[i]);
883 	}
884 
885 	/* Make sure to include at least one entry at highest pstate */
886 	if (max_pstate != min_pstate || i == 0) {
887 		if (i > MAX_NUM_DPM_LVL - 1)
888 			i = MAX_NUM_DPM_LVL - 1;
889 
890 		bw_params->clk_table.entries[i].fclk_mhz = max_fclk;
891 		bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemPstateTable[max_pstate].MemClk;
892 		bw_params->clk_table.entries[i].voltage = clock_table->MemPstateTable[max_pstate].Voltage;
893 		bw_params->clk_table.entries[i].dcfclk_mhz =
894 			find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS);
895 		bw_params->clk_table.entries[i].socclk_mhz =
896 			find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
897 		bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
898 		bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
899 		bw_params->clk_table.entries[i].wck_ratio = convert_wck_ratio(
900 			clock_table->MemPstateTable[max_pstate].WckRatio);
901 		i++;
902 	}
903 	bw_params->clk_table.num_entries = i--;
904 
905 	/* Make sure all highest clocks are included*/
906 	bw_params->clk_table.entries[i].socclk_mhz =
907 		find_max_clk_value(clock_table->SocClocks, NUM_SOCCLK_DPM_LEVELS);
908 	bw_params->clk_table.entries[i].dispclk_mhz =
909 		find_max_clk_value(clock_table->DispClocks, NUM_DISPCLK_DPM_LEVELS);
910 	bw_params->clk_table.entries[i].dppclk_mhz =
911 		find_max_clk_value(clock_table->DppClocks, NUM_DPPCLK_DPM_LEVELS);
912 	bw_params->clk_table.entries[i].fclk_mhz =
913 		find_max_clk_value(clock_table->FclkClocks_Freq, NUM_FCLK_DPM_LEVELS);
914 	ASSERT(clock_table->DcfClocks[i] == find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS));
915 	bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
916 	bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
917 	bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
918 	bw_params->clk_table.num_entries_per_clk.num_dcfclk_levels = clock_table->NumDcfClkLevelsEnabled;
919 	bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = clock_table->NumDispClkLevelsEnabled;
920 	bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = clock_table->NumDispClkLevelsEnabled;
921 	bw_params->clk_table.num_entries_per_clk.num_fclk_levels = clock_table->NumFclkLevelsEnabled;
922 	bw_params->clk_table.num_entries_per_clk.num_memclk_levels = clock_table->NumMemPstatesEnabled;
923 	bw_params->clk_table.num_entries_per_clk.num_socclk_levels = clock_table->NumSocClkLevelsEnabled;
924 
925 	/*
926 	 * Set any 0 clocks to max default setting. Not an issue for
927 	 * power since we aren't doing switching in such case anyway
928 	 */
929 	for (i = 0; i < bw_params->clk_table.num_entries; i++) {
930 		if (!bw_params->clk_table.entries[i].fclk_mhz) {
931 			bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
932 			bw_params->clk_table.entries[i].memclk_mhz = def_max.memclk_mhz;
933 			bw_params->clk_table.entries[i].voltage = def_max.voltage;
934 		}
935 		if (!bw_params->clk_table.entries[i].dcfclk_mhz)
936 			bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
937 		if (!bw_params->clk_table.entries[i].socclk_mhz)
938 			bw_params->clk_table.entries[i].socclk_mhz = def_max.socclk_mhz;
939 		if (!bw_params->clk_table.entries[i].dispclk_mhz)
940 			bw_params->clk_table.entries[i].dispclk_mhz = def_max.dispclk_mhz;
941 		if (!bw_params->clk_table.entries[i].dppclk_mhz)
942 			bw_params->clk_table.entries[i].dppclk_mhz = def_max.dppclk_mhz;
943 		if (!bw_params->clk_table.entries[i].fclk_mhz)
944 			bw_params->clk_table.entries[i].fclk_mhz = def_max.fclk_mhz;
945 		if (!bw_params->clk_table.entries[i].phyclk_mhz)
946 			bw_params->clk_table.entries[i].phyclk_mhz = def_max.phyclk_mhz;
947 		if (!bw_params->clk_table.entries[i].phyclk_d18_mhz)
948 			bw_params->clk_table.entries[i].phyclk_d18_mhz = def_max.phyclk_d18_mhz;
949 		if (!bw_params->clk_table.entries[i].dtbclk_mhz)
950 			bw_params->clk_table.entries[i].dtbclk_mhz = def_max.dtbclk_mhz;
951 	}
952 	ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
953 	bw_params->vram_type = bios_info->memory_type;
954 	bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
955 	bw_params->num_channels = bios_info->ma_channel_number ? bios_info->ma_channel_number : 4;
956 
957 	for (i = 0; i < WM_SET_COUNT; i++) {
958 		bw_params->wm_table.entries[i].wm_inst = i;
959 
960 		if (i >= bw_params->clk_table.num_entries) {
961 			bw_params->wm_table.entries[i].valid = false;
962 			continue;
963 		}
964 
965 		bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
966 		bw_params->wm_table.entries[i].valid = true;
967 	}
968 }
969 
dcn35_set_low_power_state(struct clk_mgr * clk_mgr_base)970 static void dcn35_set_low_power_state(struct clk_mgr *clk_mgr_base)
971 {
972 	int display_count;
973 	struct dc *dc = clk_mgr_base->ctx->dc;
974 	struct dc_state *context = dc->current_state;
975 
976 	if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
977 		display_count = dcn35_get_active_display_cnt_wa(dc, context, NULL);
978 		/* if we can go lower, go lower */
979 		if (display_count == 0)
980 			clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
981 	}
982 }
983 
dcn35_exit_low_power_state(struct clk_mgr * clk_mgr_base)984 static void dcn35_exit_low_power_state(struct clk_mgr *clk_mgr_base)
985 {
986 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
987 
988 	//SMU optimization is performed part of low power state exit.
989 	dcn35_smu_exit_low_power_state(clk_mgr);
990 
991 }
992 
dcn35_is_ips_supported(struct clk_mgr * clk_mgr_base)993 static bool dcn35_is_ips_supported(struct clk_mgr *clk_mgr_base)
994 {
995 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
996 
997 	return dcn35_smu_get_ips_supported(clk_mgr) ? true : false;
998 }
999 
dcn35_init_clocks_fpga(struct clk_mgr * clk_mgr)1000 static void dcn35_init_clocks_fpga(struct clk_mgr *clk_mgr)
1001 {
1002 	init_clk_states(clk_mgr);
1003 
1004 /* TODO: Implement the functions and remove the ifndef guard */
1005 }
1006 
dcn35_update_clocks_fpga(struct clk_mgr * clk_mgr,struct dc_state * context,bool safe_to_lower)1007 static void dcn35_update_clocks_fpga(struct clk_mgr *clk_mgr,
1008 		struct dc_state *context,
1009 		bool safe_to_lower)
1010 {
1011 	struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
1012 	struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
1013 	int fclk_adj = new_clocks->fclk_khz;
1014 
1015 	/* TODO: remove this after correctly set by DML */
1016 	new_clocks->dcfclk_khz = 400000;
1017 	new_clocks->socclk_khz = 400000;
1018 
1019 	/* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
1020 	//int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
1021 	new_clocks->fclk_khz = 4320000;
1022 
1023 	if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
1024 		clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
1025 	}
1026 
1027 	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr->clks.dcfclk_khz)) {
1028 		clk_mgr->clks.dcfclk_khz = new_clocks->dcfclk_khz;
1029 	}
1030 
1031 	if (should_set_clock(safe_to_lower,
1032 			new_clocks->dcfclk_deep_sleep_khz, clk_mgr->clks.dcfclk_deep_sleep_khz)) {
1033 		clk_mgr->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
1034 	}
1035 
1036 	if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr->clks.socclk_khz)) {
1037 		clk_mgr->clks.socclk_khz = new_clocks->socclk_khz;
1038 	}
1039 
1040 	if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr->clks.dramclk_khz)) {
1041 		clk_mgr->clks.dramclk_khz = new_clocks->dramclk_khz;
1042 	}
1043 
1044 	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->clks.dppclk_khz)) {
1045 		clk_mgr->clks.dppclk_khz = new_clocks->dppclk_khz;
1046 	}
1047 
1048 	if (should_set_clock(safe_to_lower, fclk_adj, clk_mgr->clks.fclk_khz)) {
1049 		clk_mgr->clks.fclk_khz = fclk_adj;
1050 	}
1051 
1052 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) {
1053 		clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz;
1054 	}
1055 
1056 	/* Both fclk and ref_dppclk run on the same scemi clock.
1057 	 * So take the higher value since the DPP DTO is typically programmed
1058 	 * such that max dppclk is 1:1 with ref_dppclk.
1059 	 */
1060 	if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz)
1061 		clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz;
1062 	if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz)
1063 		clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz;
1064 
1065 	// Both fclk and ref_dppclk run on the same scemi clock.
1066 	clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
1067 
1068 	/* TODO: set dtbclk in correct place */
1069 	clk_mgr->clks.dtbclk_en = true;
1070 	dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks);
1071 	dcn35_update_clocks_update_dpp_dto(clk_mgr_int, context, safe_to_lower);
1072 
1073 	dcn35_update_clocks_update_dtb_dto(clk_mgr_int, context, clk_mgr->clks.ref_dtbclk_khz);
1074 }
1075 
1076 static struct clk_mgr_funcs dcn35_funcs = {
1077 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1078 	.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
1079 	.update_clocks = dcn35_update_clocks,
1080 	.init_clocks = dcn35_init_clocks,
1081 	.enable_pme_wa = dcn35_enable_pme_wa,
1082 	.are_clock_states_equal = dcn35_are_clock_states_equal,
1083 	.notify_wm_ranges = dcn35_notify_wm_ranges,
1084 	.set_low_power_state = dcn35_set_low_power_state,
1085 	.exit_low_power_state = dcn35_exit_low_power_state,
1086 	.is_ips_supported = dcn35_is_ips_supported,
1087 };
1088 
1089 struct clk_mgr_funcs dcn35_fpga_funcs = {
1090 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
1091 	.update_clocks = dcn35_update_clocks_fpga,
1092 	.init_clocks = dcn35_init_clocks_fpga,
1093 	.get_dtb_ref_clk_frequency = dcn31_get_dtb_ref_freq_khz,
1094 };
1095 
dcn35_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_dcn35 * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)1096 void dcn35_clk_mgr_construct(
1097 		struct dc_context *ctx,
1098 		struct clk_mgr_dcn35 *clk_mgr,
1099 		struct pp_smu_funcs *pp_smu,
1100 		struct dccg *dccg)
1101 {
1102 	struct dcn35_smu_dpm_clks smu_dpm_clks = { 0 };
1103 	clk_mgr->base.base.ctx = ctx;
1104 	clk_mgr->base.base.funcs = &dcn35_funcs;
1105 
1106 	clk_mgr->base.pp_smu = pp_smu;
1107 
1108 	clk_mgr->base.dccg = dccg;
1109 	clk_mgr->base.dfs_bypass_disp_clk = 0;
1110 
1111 	clk_mgr->base.dprefclk_ss_percentage = 0;
1112 	clk_mgr->base.dprefclk_ss_divider = 1000;
1113 	clk_mgr->base.ss_on_dprefclk = false;
1114 	clk_mgr->base.dfs_ref_freq_khz = 48000;
1115 
1116 	clk_mgr->smu_wm_set.wm_set = (struct dcn35_watermarks *)dm_helpers_allocate_gpu_mem(
1117 				clk_mgr->base.base.ctx,
1118 				DC_MEM_ALLOC_TYPE_GART,
1119 				sizeof(struct dcn35_watermarks),
1120 				&clk_mgr->smu_wm_set.mc_address.quad_part);
1121 
1122 	if (!clk_mgr->smu_wm_set.wm_set) {
1123 		clk_mgr->smu_wm_set.wm_set = &dummy_wms;
1124 		clk_mgr->smu_wm_set.mc_address.quad_part = 0;
1125 	}
1126 	ASSERT(clk_mgr->smu_wm_set.wm_set);
1127 
1128 	smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn35 *)dm_helpers_allocate_gpu_mem(
1129 				clk_mgr->base.base.ctx,
1130 				DC_MEM_ALLOC_TYPE_GART,
1131 				sizeof(DpmClocks_t_dcn35),
1132 				&smu_dpm_clks.mc_address.quad_part);
1133 
1134 	if (smu_dpm_clks.dpm_clks == NULL) {
1135 		smu_dpm_clks.dpm_clks = &dummy_clocks;
1136 		smu_dpm_clks.mc_address.quad_part = 0;
1137 	}
1138 
1139 	ASSERT(smu_dpm_clks.dpm_clks);
1140 
1141 	clk_mgr->base.smu_ver = dcn35_smu_get_smu_version(&clk_mgr->base);
1142 
1143 	if (clk_mgr->base.smu_ver)
1144 		clk_mgr->base.smu_present = true;
1145 
1146 	/* TODO: Check we get what we expect during bringup */
1147 	clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
1148 
1149 	if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
1150 		dcn35_bw_params.wm_table = lpddr5_wm_table;
1151 	} else {
1152 		dcn35_bw_params.wm_table = ddr5_wm_table;
1153 	}
1154 	/* Saved clocks configured at boot for debug purposes */
1155 	dcn35_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, clk_mgr);
1156 
1157 	clk_mgr->base.base.dprefclk_khz = dcn35_smu_get_dprefclk(&clk_mgr->base);
1158 	clk_mgr->base.base.clks.ref_dtbclk_khz = 600000;
1159 
1160 	dce_clock_read_ss_info(&clk_mgr->base);
1161 	/*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/
1162 
1163 	dcn35_read_ss_info_from_lut(&clk_mgr->base);
1164 
1165 	clk_mgr->base.base.bw_params = &dcn35_bw_params;
1166 
1167 	if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
1168 		int i;
1169 		dcn35_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
1170 		DC_LOG_SMU("NumDcfClkLevelsEnabled: %d\n"
1171 				   "NumDispClkLevelsEnabled: %d\n"
1172 				   "NumSocClkLevelsEnabled: %d\n"
1173 				   "VcnClkLevelsEnabled: %d\n"
1174 				   "FClkLevelsEnabled: %d\n"
1175 				   "NumMemPstatesEnabled: %d\n"
1176 				   "MinGfxClk: %d\n"
1177 				   "MaxGfxClk: %d\n",
1178 				   smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled,
1179 				   smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled,
1180 				   smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled,
1181 				   smu_dpm_clks.dpm_clks->VcnClkLevelsEnabled,
1182 				   smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled,
1183 				   smu_dpm_clks.dpm_clks->NumMemPstatesEnabled,
1184 				   smu_dpm_clks.dpm_clks->MinGfxClk,
1185 				   smu_dpm_clks.dpm_clks->MaxGfxClk);
1186 		for (i = 0; i < smu_dpm_clks.dpm_clks->NumDcfClkLevelsEnabled; i++) {
1187 			DC_LOG_SMU("smu_dpm_clks.dpm_clks->DcfClocks[%d] = %d\n",
1188 					   i,
1189 					   smu_dpm_clks.dpm_clks->DcfClocks[i]);
1190 		}
1191 		for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) {
1192 			DC_LOG_SMU("smu_dpm_clks.dpm_clks->DispClocks[%d] = %d\n",
1193 					   i, smu_dpm_clks.dpm_clks->DispClocks[i]);
1194 		}
1195 		for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++) {
1196 			DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocClocks[%d] = %d\n",
1197 					   i, smu_dpm_clks.dpm_clks->SocClocks[i]);
1198 		}
1199 		for (i = 0; i < smu_dpm_clks.dpm_clks->NumFclkLevelsEnabled; i++) {
1200 			DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Freq[%d] = %d\n",
1201 					   i, smu_dpm_clks.dpm_clks->FclkClocks_Freq[i]);
1202 			DC_LOG_SMU("smu_dpm_clks.dpm_clks->FclkClocks_Voltage[%d] = %d\n",
1203 					   i, smu_dpm_clks.dpm_clks->FclkClocks_Voltage[i]);
1204 		}
1205 		for (i = 0; i < smu_dpm_clks.dpm_clks->NumSocClkLevelsEnabled; i++)
1206 			DC_LOG_SMU("smu_dpm_clks.dpm_clks->SocVoltage[%d] = %d\n",
1207 					   i, smu_dpm_clks.dpm_clks->SocVoltage[i]);
1208 
1209 		for (i = 0; i < smu_dpm_clks.dpm_clks->NumMemPstatesEnabled; i++) {
1210 			DC_LOG_SMU("smu_dpm_clks.dpm_clks.MemPstateTable[%d].UClk = %d\n"
1211 					   "smu_dpm_clks.dpm_clks->MemPstateTable[%d].MemClk= %d\n"
1212 					   "smu_dpm_clks.dpm_clks->MemPstateTable[%d].Voltage = %d\n",
1213 					   i, smu_dpm_clks.dpm_clks->MemPstateTable[i].UClk,
1214 					   i, smu_dpm_clks.dpm_clks->MemPstateTable[i].MemClk,
1215 					   i, smu_dpm_clks.dpm_clks->MemPstateTable[i].Voltage);
1216 		}
1217 
1218 		if (ctx->dc_bios->integrated_info && ctx->dc->config.use_default_clock_table == false) {
1219 			dcn35_clk_mgr_helper_populate_bw_params(
1220 					&clk_mgr->base,
1221 					ctx->dc_bios->integrated_info,
1222 					smu_dpm_clks.dpm_clks);
1223 		}
1224 	}
1225 
1226 	if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
1227 		dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_GART,
1228 				smu_dpm_clks.dpm_clks);
1229 
1230 	if (ctx->dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) {
1231 		bool ips_support = false;
1232 
1233 		/*avoid call pmfw at init*/
1234 		ips_support = dcn35_smu_get_ips_supported(&clk_mgr->base);
1235 		if (ips_support) {
1236 			ctx->dc->debug.ignore_pg = false;
1237 			ctx->dc->debug.disable_dpp_power_gate = false;
1238 			ctx->dc->debug.disable_hubp_power_gate = false;
1239 			ctx->dc->debug.disable_dsc_power_gate = false;
1240 
1241 			/* Disable dynamic IPS2 in older PMFW (93.12) for Z8 interop. */
1242 			if (ctx->dc->config.disable_ips == DMUB_IPS_ENABLE &&
1243 			    ctx->dce_version == DCN_VERSION_3_5 &&
1244 			    ((clk_mgr->base.smu_ver & 0x00FFFFFF) <= 0x005d0c00))
1245 				ctx->dc->config.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF;
1246 		} else {
1247 			/*let's reset the config control flag*/
1248 			ctx->dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/
1249 		}
1250 	}
1251 }
1252 
dcn35_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr_int)1253 void dcn35_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
1254 {
1255 	struct clk_mgr_dcn35 *clk_mgr = TO_CLK_MGR_DCN35(clk_mgr_int);
1256 
1257 	if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
1258 		dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
1259 				clk_mgr->smu_wm_set.wm_set);
1260 }
1261