1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * AMD SoC Power Management Controller Driver 4 * 5 * Copyright (c) 2023, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Mario Limonciello <mario.limonciello@amd.com> 9 */ 10 11 #ifndef PMC_H 12 #define PMC_H 13 14 #include <linux/types.h> 15 #include <linux/mutex.h> 16 17 /* SMU communication registers */ 18 #define AMD_PMC_REGISTER_RESPONSE 0x980 19 #define AMD_PMC_REGISTER_ARGUMENT 0x9BC 20 #define AMD_PMC_REGISTER_MESSAGE 0x538 21 22 /* SMU communication registers for 1Ah 20h SoC */ 23 #define AMD_PMC_REGISTER_MSG_1AH_20H 0x938 24 25 /* SMU communication registers for 1Ah 80h SoC */ 26 #define AMD_PMC_REGISTER_MSG_1AH_80H 0xA10 27 #define AMD_PMC_REGISTER_ARG_1AH_80H 0xA18 28 #define AMD_PMC_REGISTER_RSP_1AH_80H 0xA14 29 30 /* PMC Scratch Registers */ 31 #define AMD_PMC_SCRATCH_REG_CZN 0x94 32 #define AMD_PMC_SCRATCH_REG_YC 0xD14 33 #define AMD_PMC_SCRATCH_REG_1AH 0xF14 34 35 /* STB Registers */ 36 #define AMD_PMC_STB_S2IDLE_PREPARE 0xC6000001 37 #define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002 38 #define AMD_PMC_STB_S2IDLE_CHECK 0xC6000003 39 40 /* Base address of SMU for mapping physical address to virtual address */ 41 #define AMD_PMC_MAPPING_SIZE 0x01000 42 #define AMD_PMC_BASE_ADDR_OFFSET 0x10000 43 #define AMD_PMC_BASE_ADDR_LO 0x13B102E8 44 #define AMD_PMC_BASE_ADDR_HI 0x13B102EC 45 #define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0) 46 #define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20) 47 48 /* SMU Response Codes */ 49 #define AMD_PMC_RESULT_OK 0x01 50 #define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC 51 #define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD 52 #define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE 53 #define AMD_PMC_RESULT_FAILED 0xFF 54 55 /* FCH SSC Registers */ 56 #define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30 57 #define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34 58 #define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38 59 #define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C 60 #define FCH_SSC_MAPPING_SIZE 0x800 61 #define FCH_BASE_PHY_ADDR_LOW 0xFED81100 62 #define FCH_BASE_PHY_ADDR_HIGH 0x00000000 63 64 /* SMU Message Definations */ 65 #define SMU_MSG_GETSMUVERSION 0x02 66 #define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04 67 #define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05 68 #define SMU_MSG_LOG_START 0x06 69 #define SMU_MSG_LOG_RESET 0x07 70 #define SMU_MSG_LOG_DUMP_DATA 0x08 71 #define SMU_MSG_GET_SUP_CONSTRAINTS 0x09 72 73 #define PMC_MSG_DELAY_MIN_US 50 74 #define RESPONSE_REGISTER_LOOP_MAX 20000 75 76 #define DELAY_MIN_US 2000 77 #define DELAY_MAX_US 3000 78 79 enum s2d_msg_port { 80 MSG_PORT_PMC, 81 MSG_PORT_S2D, 82 }; 83 84 struct amd_mp2_dev { 85 void __iomem *mmio; 86 void __iomem *vslbase; 87 void *stbdata; 88 void *devres_gid; 89 struct pci_dev *pdev; 90 dma_addr_t dma_addr; 91 int stb_len; 92 bool is_stb_data; 93 }; 94 95 struct stb_arg { 96 u32 s2d_msg_id; 97 u32 msg; 98 u32 arg; 99 u32 resp; 100 }; 101 102 struct amd_pmc_bit_map { 103 const char *name; 104 u32 bit_mask; 105 }; 106 107 /* SoC-specific information */ 108 struct amd_pmc_cpu_info { 109 u32 smu_msg; 110 u32 smu_arg; 111 u32 smu_rsp; 112 u32 num_ips; 113 u32 scratch_reg; 114 const struct amd_pmc_bit_map *ips_ptr; 115 u8 os_hint; 116 }; 117 118 struct amd_pmc_dev { 119 void __iomem *regbase; 120 void __iomem *smu_virt_addr; 121 void __iomem *stb_virt_addr; 122 void __iomem *fch_virt_addr; 123 u32 base_addr; 124 u32 cpu_id; 125 u32 dram_size; 126 u32 active_ips; 127 /* SMU version information */ 128 u8 smu_program; 129 u8 major; 130 u8 minor; 131 u8 rev; 132 u8 msg_port; 133 struct device *dev; 134 struct pci_dev *rdev; 135 struct mutex lock; /* generic mutex lock */ 136 struct dentry *dbgfs_dir; 137 struct quirk_entry *quirks; 138 bool disable_8042_wakeup; 139 bool is_first_check_after_suspend; 140 struct amd_mp2_dev *mp2; 141 struct stb_arg stb_arg; 142 const struct amd_pmc_cpu_info *cpu_info; 143 }; 144 145 struct smu_metrics { 146 u32 table_version; 147 u32 hint_count; 148 u32 s0i3_last_entry_status; 149 u32 timein_s0i2; 150 u64 timeentering_s0i3_lastcapture; 151 u64 timeentering_s0i3_totaltime; 152 u64 timeto_resume_to_os_lastcapture; 153 u64 timeto_resume_to_os_totaltime; 154 u64 timein_s0i3_lastcapture; 155 u64 timein_s0i3_totaltime; 156 u64 timein_swdrips_lastcapture; 157 u64 timein_swdrips_totaltime; 158 u64 timecondition_notmet_lastcapture[32]; 159 u64 timecondition_notmet_totaltime[32]; 160 } __packed; 161 162 enum amd_pmc_def { 163 MSG_TEST = 0x01, 164 MSG_OS_HINT_PCO, 165 MSG_OS_HINT_RN, 166 }; 167 168 void amd_pmc_process_restore_quirks(struct amd_pmc_dev *dev); 169 bool amd_pmc_quirk_need_suspend_delay(struct amd_pmc_dev *dev); 170 void amd_pmc_quirks_init(struct amd_pmc_dev *dev); 171 void amd_mp2_stb_init(struct amd_pmc_dev *dev); 172 void amd_mp2_stb_deinit(struct amd_pmc_dev *dev); 173 174 /* List of supported CPU/device IDs */ 175 #define PCI_DEVICE_ID_AMD_CPU_ID_PCO 0x15D0 176 #define PCI_DEVICE_ID_AMD_CPU_ID_CZN 0x1630 177 #define PCI_DEVICE_ID_AMD_CPU_ID_VG 0x1645 178 #define PCI_DEVICE_ID_AMD_CPU_ID_YC 0x14B5 179 #define PCI_DEVICE_ID_AMD_CPU_ID_CB 0x14D8 180 #define PCI_DEVICE_ID_AMD_CPU_ID_PS 0x14E8 181 #define PCI_DEVICE_ID_AMD_CPU_ID_SP 0x14A4 182 #define PCI_DEVICE_ID_AMD_CPU_ID_SHP 0x153A 183 184 /* Backward compatibility aliases */ 185 #define AMD_CPU_ID_PCO PCI_DEVICE_ID_AMD_CPU_ID_PCO 186 #define AMD_CPU_ID_CZN PCI_DEVICE_ID_AMD_CPU_ID_CZN 187 #define AMD_CPU_ID_VG PCI_DEVICE_ID_AMD_CPU_ID_VG 188 #define AMD_CPU_ID_YC PCI_DEVICE_ID_AMD_CPU_ID_YC 189 #define AMD_CPU_ID_CB PCI_DEVICE_ID_AMD_CPU_ID_CB 190 #define AMD_CPU_ID_PS PCI_DEVICE_ID_AMD_CPU_ID_PS 191 #define AMD_CPU_ID_SP PCI_DEVICE_ID_AMD_CPU_ID_SP 192 #define AMD_CPU_ID_SHP PCI_DEVICE_ID_AMD_CPU_ID_SHP 193 194 #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507 195 #define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122 196 #define PCI_DEVICE_ID_AMD_1AH_M80H_ROOT 0x115b 197 #define PCI_DEVICE_ID_AMD_MP2_STB 0x172c 198 199 int amd_stb_s2d_init(struct amd_pmc_dev *dev); 200 int amd_stb_read(struct amd_pmc_dev *dev, u32 *buf); 201 int amd_stb_write(struct amd_pmc_dev *dev, u32 data); 202 int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret); 203 204 #endif /* PMC_H */ 205